radeonsi: fix culldist_writemask in nir path
[mesa.git] / src / gallium / drivers / radeonsi / si_shader_nir.c
1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "si_shader.h"
25 #include "si_shader_internal.h"
26
27 #include "ac_nir_to_llvm.h"
28
29 #include "tgsi/tgsi_from_mesa.h"
30
31 #include "compiler/nir/nir.h"
32 #include "compiler/nir_types.h"
33
34
35 static int
36 type_size(const struct glsl_type *type)
37 {
38 return glsl_count_attribute_slots(type, false);
39 }
40
41 static void scan_instruction(struct tgsi_shader_info *info,
42 nir_instr *instr)
43 {
44 if (instr->type == nir_instr_type_alu) {
45 nir_alu_instr *alu = nir_instr_as_alu(instr);
46
47 switch (alu->op) {
48 case nir_op_fddx:
49 case nir_op_fddy:
50 case nir_op_fddx_fine:
51 case nir_op_fddy_fine:
52 case nir_op_fddx_coarse:
53 case nir_op_fddy_coarse:
54 info->uses_derivatives = true;
55 break;
56 default:
57 break;
58 }
59 } else if (instr->type == nir_instr_type_tex) {
60 nir_tex_instr *tex = nir_instr_as_tex(instr);
61
62 switch (tex->op) {
63 case nir_texop_tex:
64 case nir_texop_txb:
65 case nir_texop_lod:
66 info->uses_derivatives = true;
67 break;
68 default:
69 break;
70 }
71 } else if (instr->type == nir_instr_type_intrinsic) {
72 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
73
74 switch (intr->intrinsic) {
75 case nir_intrinsic_load_front_face:
76 info->uses_frontface = 1;
77 break;
78 case nir_intrinsic_load_instance_id:
79 info->uses_instanceid = 1;
80 break;
81 case nir_intrinsic_load_vertex_id:
82 info->uses_vertexid = 1;
83 break;
84 case nir_intrinsic_load_vertex_id_zero_base:
85 info->uses_vertexid_nobase = 1;
86 break;
87 case nir_intrinsic_load_base_vertex:
88 info->uses_basevertex = 1;
89 break;
90 case nir_intrinsic_load_primitive_id:
91 info->uses_primid = 1;
92 break;
93 case nir_intrinsic_image_store:
94 case nir_intrinsic_image_atomic_add:
95 case nir_intrinsic_image_atomic_min:
96 case nir_intrinsic_image_atomic_max:
97 case nir_intrinsic_image_atomic_and:
98 case nir_intrinsic_image_atomic_or:
99 case nir_intrinsic_image_atomic_xor:
100 case nir_intrinsic_image_atomic_exchange:
101 case nir_intrinsic_image_atomic_comp_swap:
102 case nir_intrinsic_store_ssbo:
103 case nir_intrinsic_ssbo_atomic_add:
104 case nir_intrinsic_ssbo_atomic_imin:
105 case nir_intrinsic_ssbo_atomic_umin:
106 case nir_intrinsic_ssbo_atomic_imax:
107 case nir_intrinsic_ssbo_atomic_umax:
108 case nir_intrinsic_ssbo_atomic_and:
109 case nir_intrinsic_ssbo_atomic_or:
110 case nir_intrinsic_ssbo_atomic_xor:
111 case nir_intrinsic_ssbo_atomic_exchange:
112 case nir_intrinsic_ssbo_atomic_comp_swap:
113 info->writes_memory = true;
114 break;
115 default:
116 break;
117 }
118 }
119 }
120
121 void si_nir_scan_shader(const struct nir_shader *nir,
122 struct tgsi_shader_info *info)
123 {
124 nir_function *func;
125 unsigned i;
126
127 assert(nir->info.stage == MESA_SHADER_VERTEX ||
128 nir->info.stage == MESA_SHADER_FRAGMENT);
129
130 info->processor = pipe_shader_type_from_mesa(nir->info.stage);
131 info->num_tokens = 2; /* indicate that the shader is non-empty */
132 info->num_instructions = 2;
133
134 info->num_inputs = nir->num_inputs;
135 info->num_outputs = nir->num_outputs;
136
137 i = 0;
138 nir_foreach_variable(variable, &nir->inputs) {
139 unsigned semantic_name, semantic_index;
140 unsigned attrib_count = glsl_count_attribute_slots(variable->type,
141 nir->info.stage == MESA_SHADER_VERTEX);
142
143 assert(attrib_count == 1 && "not implemented");
144
145 /* Vertex shader inputs don't have semantics. The state
146 * tracker has already mapped them to attributes via
147 * variable->data.driver_location.
148 */
149 if (nir->info.stage == MESA_SHADER_VERTEX)
150 continue;
151
152 /* Fragment shader position is a system value. */
153 if (nir->info.stage == MESA_SHADER_FRAGMENT &&
154 variable->data.location == VARYING_SLOT_POS) {
155 if (variable->data.pixel_center_integer)
156 info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] =
157 TGSI_FS_COORD_PIXEL_CENTER_INTEGER;
158 continue;
159 }
160
161 tgsi_get_gl_varying_semantic(variable->data.location, true,
162 &semantic_name, &semantic_index);
163
164 info->input_semantic_name[i] = semantic_name;
165 info->input_semantic_index[i] = semantic_index;
166
167 if (variable->data.sample)
168 info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_SAMPLE;
169 else if (variable->data.centroid)
170 info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_CENTROID;
171 else
172 info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_CENTER;
173
174 enum glsl_base_type base_type =
175 glsl_get_base_type(glsl_without_array(variable->type));
176
177 switch (variable->data.interpolation) {
178 case INTERP_MODE_NONE:
179 if (glsl_base_type_is_integer(base_type)) {
180 info->input_interpolate[i] = TGSI_INTERPOLATE_CONSTANT;
181 break;
182 }
183
184 if (semantic_name == TGSI_SEMANTIC_COLOR) {
185 info->input_interpolate[i] = TGSI_INTERPOLATE_COLOR;
186 goto persp_locations;
187 }
188 /* fall-through */
189 case INTERP_MODE_SMOOTH:
190 assert(!glsl_base_type_is_integer(base_type));
191
192 info->input_interpolate[i] = TGSI_INTERPOLATE_PERSPECTIVE;
193
194 persp_locations:
195 if (variable->data.sample)
196 info->uses_persp_sample = true;
197 else if (variable->data.centroid)
198 info->uses_persp_centroid = true;
199 else
200 info->uses_persp_center = true;
201 break;
202
203 case INTERP_MODE_NOPERSPECTIVE:
204 assert(!glsl_base_type_is_integer(base_type));
205
206 info->input_interpolate[i] = TGSI_INTERPOLATE_LINEAR;
207
208 if (variable->data.sample)
209 info->uses_linear_sample = true;
210 else if (variable->data.centroid)
211 info->uses_linear_centroid = true;
212 else
213 info->uses_linear_center = true;
214 break;
215
216 case INTERP_MODE_FLAT:
217 info->input_interpolate[i] = TGSI_INTERPOLATE_CONSTANT;
218 break;
219 }
220
221 /* TODO make this more precise */
222 if (variable->data.location == VARYING_SLOT_COL0)
223 info->colors_read |= 0x0f;
224 else if (variable->data.location == VARYING_SLOT_COL1)
225 info->colors_read |= 0xf0;
226
227 i++;
228 }
229
230 i = 0;
231 nir_foreach_variable(variable, &nir->outputs) {
232 unsigned semantic_name, semantic_index;
233
234 if (nir->info.stage == MESA_SHADER_FRAGMENT) {
235 tgsi_get_gl_frag_result_semantic(variable->data.location,
236 &semantic_name, &semantic_index);
237 } else {
238 tgsi_get_gl_varying_semantic(variable->data.location, true,
239 &semantic_name, &semantic_index);
240 }
241
242 info->output_semantic_name[i] = semantic_name;
243 info->output_semantic_index[i] = semantic_index;
244 info->output_usagemask[i] = TGSI_WRITEMASK_XYZW;
245
246 switch (semantic_name) {
247 case TGSI_SEMANTIC_PRIMID:
248 info->writes_primid = true;
249 break;
250 case TGSI_SEMANTIC_VIEWPORT_INDEX:
251 info->writes_viewport_index = true;
252 break;
253 case TGSI_SEMANTIC_LAYER:
254 info->writes_layer = true;
255 break;
256 case TGSI_SEMANTIC_PSIZE:
257 info->writes_psize = true;
258 break;
259 case TGSI_SEMANTIC_CLIPVERTEX:
260 info->writes_clipvertex = true;
261 break;
262 case TGSI_SEMANTIC_COLOR:
263 info->colors_written |= 1 << semantic_index;
264 break;
265 case TGSI_SEMANTIC_STENCIL:
266 info->writes_stencil = true;
267 break;
268 case TGSI_SEMANTIC_SAMPLEMASK:
269 info->writes_samplemask = true;
270 break;
271 case TGSI_SEMANTIC_EDGEFLAG:
272 info->writes_edgeflag = true;
273 break;
274 case TGSI_SEMANTIC_POSITION:
275 if (info->processor == PIPE_SHADER_FRAGMENT)
276 info->writes_z = true;
277 else
278 info->writes_position = true;
279 break;
280 }
281
282 i++;
283 }
284
285 nir_foreach_variable(variable, &nir->uniforms) {
286 const struct glsl_type *type = variable->type;
287 enum glsl_base_type base_type =
288 glsl_get_base_type(glsl_without_array(type));
289 unsigned aoa_size = MAX2(1, glsl_get_aoa_size(type));
290
291 /* We rely on the fact that nir_lower_samplers_as_deref has
292 * eliminated struct dereferences.
293 */
294 if (base_type == GLSL_TYPE_SAMPLER)
295 info->samplers_declared |=
296 u_bit_consecutive(variable->data.binding, aoa_size);
297 else if (base_type == GLSL_TYPE_IMAGE)
298 info->images_declared |=
299 u_bit_consecutive(variable->data.binding, aoa_size);
300 }
301
302 info->num_written_clipdistance = nir->info.clip_distance_array_size;
303 info->num_written_culldistance = nir->info.cull_distance_array_size;
304 info->clipdist_writemask = u_bit_consecutive(0, info->num_written_clipdistance);
305 info->culldist_writemask = u_bit_consecutive(0, info->num_written_culldistance);
306
307 if (info->processor == PIPE_SHADER_FRAGMENT)
308 info->uses_kill = nir->info.fs.uses_discard;
309
310 /* TODO make this more accurate */
311 info->const_buffers_declared = u_bit_consecutive(0, SI_NUM_CONST_BUFFERS);
312 info->shader_buffers_declared = u_bit_consecutive(0, SI_NUM_SHADER_BUFFERS);
313
314 func = (struct nir_function *)exec_list_get_head_const(&nir->functions);
315 nir_foreach_block(block, func->impl) {
316 nir_foreach_instr(instr, block)
317 scan_instruction(info, instr);
318 }
319 }
320
321 /**
322 * Perform "lowering" operations on the NIR that are run once when the shader
323 * selector is created.
324 */
325 void
326 si_lower_nir(struct si_shader_selector* sel)
327 {
328 /* Adjust the driver location of inputs and outputs. The state tracker
329 * interprets them as slots, while the ac/nir backend interprets them
330 * as individual components.
331 */
332 nir_foreach_variable(variable, &sel->nir->inputs)
333 variable->data.driver_location *= 4;
334
335 nir_foreach_variable(variable, &sel->nir->outputs) {
336 variable->data.driver_location *= 4;
337
338 if (sel->nir->info.stage == MESA_SHADER_FRAGMENT) {
339 if (variable->data.location == FRAG_RESULT_DEPTH)
340 variable->data.driver_location += 2;
341 else if (variable->data.location == FRAG_RESULT_STENCIL)
342 variable->data.driver_location += 1;
343 }
344 }
345
346 /* Perform lowerings (and optimizations) of code.
347 *
348 * Performance considerations aside, we must:
349 * - lower certain ALU operations
350 * - ensure constant offsets for texture instructions are folded
351 * and copy-propagated
352 */
353 NIR_PASS_V(sel->nir, nir_lower_io, nir_var_uniform, type_size,
354 (nir_lower_io_options)0);
355 NIR_PASS_V(sel->nir, nir_lower_uniforms_to_ubo);
356
357 NIR_PASS_V(sel->nir, nir_lower_returns);
358 NIR_PASS_V(sel->nir, nir_lower_vars_to_ssa);
359 NIR_PASS_V(sel->nir, nir_lower_alu_to_scalar);
360 NIR_PASS_V(sel->nir, nir_lower_phis_to_scalar);
361
362 static const struct nir_lower_tex_options lower_tex_options = {
363 .lower_txp = ~0u,
364 };
365 NIR_PASS_V(sel->nir, nir_lower_tex, &lower_tex_options);
366
367 bool progress;
368 do {
369 progress = false;
370
371 /* (Constant) copy propagation is needed for txf with offsets. */
372 NIR_PASS(progress, sel->nir, nir_copy_prop);
373 NIR_PASS(progress, sel->nir, nir_opt_remove_phis);
374 NIR_PASS(progress, sel->nir, nir_opt_dce);
375 if (nir_opt_trivial_continues(sel->nir)) {
376 progress = true;
377 NIR_PASS(progress, sel->nir, nir_copy_prop);
378 NIR_PASS(progress, sel->nir, nir_opt_dce);
379 }
380 NIR_PASS(progress, sel->nir, nir_opt_if);
381 NIR_PASS(progress, sel->nir, nir_opt_dead_cf);
382 NIR_PASS(progress, sel->nir, nir_opt_cse);
383 NIR_PASS(progress, sel->nir, nir_opt_peephole_select, 8);
384
385 /* Needed for algebraic lowering */
386 NIR_PASS(progress, sel->nir, nir_opt_algebraic);
387 NIR_PASS(progress, sel->nir, nir_opt_constant_folding);
388
389 NIR_PASS(progress, sel->nir, nir_opt_undef);
390 NIR_PASS(progress, sel->nir, nir_opt_conditional_discard);
391 if (sel->nir->options->max_unroll_iterations) {
392 NIR_PASS(progress, sel->nir, nir_opt_loop_unroll, 0);
393 }
394 } while (progress);
395 }
396
397 static void declare_nir_input_vs(struct si_shader_context *ctx,
398 struct nir_variable *variable, unsigned rel,
399 LLVMValueRef out[4])
400 {
401 si_llvm_load_input_vs(ctx, variable->data.driver_location / 4 + rel, out);
402 }
403
404 static void declare_nir_input_fs(struct si_shader_context *ctx,
405 struct nir_variable *variable, unsigned rel,
406 unsigned *fs_attr_idx,
407 LLVMValueRef out[4])
408 {
409 unsigned slot = variable->data.location + rel;
410
411 assert(variable->data.location >= VARYING_SLOT_VAR0 || rel == 0);
412
413 if (slot == VARYING_SLOT_POS) {
414 out[0] = LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT);
415 out[1] = LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT);
416 out[2] = LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Z_FLOAT);
417 out[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
418 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_W_FLOAT));
419 return;
420 }
421
422 si_llvm_load_input_fs(ctx, *fs_attr_idx, out);
423 (*fs_attr_idx)++;
424 }
425
426 static LLVMValueRef
427 si_nir_load_sampler_desc(struct ac_shader_abi *abi,
428 unsigned descriptor_set, unsigned base_index,
429 unsigned constant_index, LLVMValueRef dynamic_index,
430 enum ac_descriptor_type desc_type, bool image,
431 bool write)
432 {
433 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
434 LLVMBuilderRef builder = ctx->ac.builder;
435 LLVMValueRef list = LLVMGetParam(ctx->main_fn, ctx->param_samplers_and_images);
436 LLVMValueRef index = dynamic_index;
437
438 assert(!descriptor_set);
439
440 if (!index)
441 index = ctx->ac.i32_0;
442
443 index = LLVMBuildAdd(builder, index,
444 LLVMConstInt(ctx->ac.i32, base_index + constant_index, false),
445 "");
446
447 if (image) {
448 assert(desc_type == AC_DESC_IMAGE || desc_type == AC_DESC_BUFFER);
449 assert(base_index + constant_index < ctx->num_images);
450
451 if (dynamic_index)
452 index = si_llvm_bound_index(ctx, index, ctx->num_images);
453
454 index = LLVMBuildSub(ctx->gallivm.builder,
455 LLVMConstInt(ctx->i32, SI_NUM_IMAGES - 1, 0),
456 index, "");
457
458 /* TODO: be smarter about when we use dcc_off */
459 return si_load_image_desc(ctx, list, index, desc_type, write);
460 }
461
462 assert(base_index + constant_index < ctx->num_samplers);
463
464 if (dynamic_index)
465 index = si_llvm_bound_index(ctx, index, ctx->num_samplers);
466
467 index = LLVMBuildAdd(ctx->gallivm.builder, index,
468 LLVMConstInt(ctx->i32, SI_NUM_IMAGES / 2, 0), "");
469
470 return si_load_sampler_desc(ctx, list, index, desc_type);
471 }
472
473 bool si_nir_build_llvm(struct si_shader_context *ctx, struct nir_shader *nir)
474 {
475 struct tgsi_shader_info *info = &ctx->shader->selector->info;
476
477 unsigned fs_attr_idx = 0;
478 nir_foreach_variable(variable, &nir->inputs) {
479 unsigned attrib_count = glsl_count_attribute_slots(variable->type,
480 nir->info.stage == MESA_SHADER_VERTEX);
481 unsigned input_idx = variable->data.driver_location;
482
483 for (unsigned i = 0; i < attrib_count; ++i) {
484 LLVMValueRef data[4];
485
486 if (nir->info.stage == MESA_SHADER_VERTEX)
487 declare_nir_input_vs(ctx, variable, i, data);
488 else if (nir->info.stage == MESA_SHADER_FRAGMENT)
489 declare_nir_input_fs(ctx, variable, i, &fs_attr_idx, data);
490
491 for (unsigned chan = 0; chan < 4; chan++) {
492 ctx->inputs[input_idx + chan] =
493 LLVMBuildBitCast(ctx->ac.builder, data[chan], ctx->ac.i32, "");
494 }
495 }
496 }
497
498 ctx->abi.inputs = &ctx->inputs[0];
499 ctx->abi.load_sampler_desc = si_nir_load_sampler_desc;
500 ctx->abi.clamp_shadow_reference = true;
501
502 ctx->num_samplers = util_last_bit(info->samplers_declared);
503 ctx->num_images = util_last_bit(info->images_declared);
504
505 ac_nir_translate(&ctx->ac, &ctx->abi, nir, NULL);
506
507 return true;
508 }