radeonsi/nir: move the interpolation qualifier scanning
[mesa.git] / src / gallium / drivers / radeonsi / si_shader_nir.c
1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "si_shader.h"
25 #include "si_shader_internal.h"
26
27 #include "ac_nir_to_llvm.h"
28
29 #include "tgsi/tgsi_from_mesa.h"
30
31 #include "compiler/nir/nir.h"
32 #include "compiler/nir_types.h"
33
34
35 static int
36 type_size(const struct glsl_type *type)
37 {
38 return glsl_count_attribute_slots(type, false);
39 }
40
41 static void scan_instruction(struct tgsi_shader_info *info,
42 nir_instr *instr)
43 {
44 if (instr->type == nir_instr_type_alu) {
45 nir_alu_instr *alu = nir_instr_as_alu(instr);
46
47 switch (alu->op) {
48 case nir_op_fddx:
49 case nir_op_fddy:
50 case nir_op_fddx_fine:
51 case nir_op_fddy_fine:
52 case nir_op_fddx_coarse:
53 case nir_op_fddy_coarse:
54 info->uses_derivatives = true;
55 break;
56 default:
57 break;
58 }
59 } else if (instr->type == nir_instr_type_tex) {
60 nir_tex_instr *tex = nir_instr_as_tex(instr);
61
62 if (!tex->texture) {
63 info->samplers_declared |=
64 u_bit_consecutive(tex->sampler_index, 1);
65 }
66
67 switch (tex->op) {
68 case nir_texop_tex:
69 case nir_texop_txb:
70 case nir_texop_lod:
71 info->uses_derivatives = true;
72 break;
73 default:
74 break;
75 }
76 } else if (instr->type == nir_instr_type_intrinsic) {
77 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
78
79 switch (intr->intrinsic) {
80 case nir_intrinsic_load_front_face:
81 info->uses_frontface = 1;
82 break;
83 case nir_intrinsic_load_instance_id:
84 info->uses_instanceid = 1;
85 break;
86 case nir_intrinsic_load_invocation_id:
87 info->uses_invocationid = true;
88 break;
89 case nir_intrinsic_load_vertex_id:
90 info->uses_vertexid = 1;
91 break;
92 case nir_intrinsic_load_vertex_id_zero_base:
93 info->uses_vertexid_nobase = 1;
94 break;
95 case nir_intrinsic_load_base_vertex:
96 info->uses_basevertex = 1;
97 break;
98 case nir_intrinsic_load_primitive_id:
99 info->uses_primid = 1;
100 break;
101 case nir_intrinsic_load_sample_mask_in:
102 info->reads_samplemask = true;
103 break;
104 case nir_intrinsic_load_tess_level_inner:
105 case nir_intrinsic_load_tess_level_outer:
106 info->reads_tess_factors = true;
107 break;
108 case nir_intrinsic_image_store:
109 case nir_intrinsic_image_atomic_add:
110 case nir_intrinsic_image_atomic_min:
111 case nir_intrinsic_image_atomic_max:
112 case nir_intrinsic_image_atomic_and:
113 case nir_intrinsic_image_atomic_or:
114 case nir_intrinsic_image_atomic_xor:
115 case nir_intrinsic_image_atomic_exchange:
116 case nir_intrinsic_image_atomic_comp_swap:
117 case nir_intrinsic_store_ssbo:
118 case nir_intrinsic_ssbo_atomic_add:
119 case nir_intrinsic_ssbo_atomic_imin:
120 case nir_intrinsic_ssbo_atomic_umin:
121 case nir_intrinsic_ssbo_atomic_imax:
122 case nir_intrinsic_ssbo_atomic_umax:
123 case nir_intrinsic_ssbo_atomic_and:
124 case nir_intrinsic_ssbo_atomic_or:
125 case nir_intrinsic_ssbo_atomic_xor:
126 case nir_intrinsic_ssbo_atomic_exchange:
127 case nir_intrinsic_ssbo_atomic_comp_swap:
128 info->writes_memory = true;
129 break;
130 case nir_intrinsic_load_var: {
131 nir_variable *var = intr->variables[0]->var;
132 nir_variable_mode mode = var->data.mode;
133 enum glsl_base_type base_type =
134 glsl_get_base_type(glsl_without_array(var->type));
135
136 if (mode == nir_var_shader_in) {
137 switch (var->data.interpolation) {
138 case INTERP_MODE_NONE:
139 if (glsl_base_type_is_integer(base_type))
140 break;
141
142 /* fall-through */
143 case INTERP_MODE_SMOOTH:
144 if (var->data.sample)
145 info->uses_persp_sample = true;
146 else if (var->data.centroid)
147 info->uses_persp_centroid = true;
148 else
149 info->uses_persp_center = true;
150 break;
151
152 case INTERP_MODE_NOPERSPECTIVE:
153 if (var->data.sample)
154 info->uses_linear_sample = true;
155 else if (var->data.centroid)
156 info->uses_linear_centroid = true;
157 else
158 info->uses_linear_center = true;
159 break;
160 }
161 }
162 break;
163 }
164 case nir_intrinsic_interp_var_at_centroid:
165 case nir_intrinsic_interp_var_at_sample:
166 case nir_intrinsic_interp_var_at_offset: {
167 enum glsl_interp_mode interp =
168 intr->variables[0]->var->data.interpolation;
169 switch (interp) {
170 case INTERP_MODE_SMOOTH:
171 case INTERP_MODE_NONE:
172 if (intr->intrinsic == nir_intrinsic_interp_var_at_centroid)
173 info->uses_persp_opcode_interp_centroid = true;
174 else if (intr->intrinsic == nir_intrinsic_interp_var_at_sample)
175 info->uses_persp_opcode_interp_sample = true;
176 else
177 info->uses_persp_opcode_interp_offset = true;
178 break;
179 case INTERP_MODE_NOPERSPECTIVE:
180 if (intr->intrinsic == nir_intrinsic_interp_var_at_centroid)
181 info->uses_linear_opcode_interp_centroid = true;
182 else if (intr->intrinsic == nir_intrinsic_interp_var_at_sample)
183 info->uses_linear_opcode_interp_sample = true;
184 else
185 info->uses_linear_opcode_interp_offset = true;
186 break;
187 case INTERP_MODE_FLAT:
188 break;
189 default:
190 unreachable("Unsupported interpoation type");
191 }
192 break;
193 }
194 default:
195 break;
196 }
197 }
198 }
199
200 void si_nir_scan_tess_ctrl(const struct nir_shader *nir,
201 const struct tgsi_shader_info *info,
202 struct tgsi_tessctrl_info *out)
203 {
204 memset(out, 0, sizeof(*out));
205
206 if (nir->info.stage != MESA_SHADER_TESS_CTRL)
207 return;
208
209 /* Initial value = true. Here the pass will accumulate results from
210 * multiple segments surrounded by barriers. If tess factors aren't
211 * written at all, it's a shader bug and we don't care if this will be
212 * true.
213 */
214 out->tessfactors_are_def_in_all_invocs = true;
215
216 /* TODO: Implement scanning of tess factors, see tgsi backend. */
217 }
218
219 void si_nir_scan_shader(const struct nir_shader *nir,
220 struct tgsi_shader_info *info)
221 {
222 nir_function *func;
223 unsigned i;
224
225 assert(nir->info.stage == MESA_SHADER_VERTEX ||
226 nir->info.stage == MESA_SHADER_GEOMETRY ||
227 nir->info.stage == MESA_SHADER_TESS_CTRL ||
228 nir->info.stage == MESA_SHADER_TESS_EVAL ||
229 nir->info.stage == MESA_SHADER_FRAGMENT);
230
231 info->processor = pipe_shader_type_from_mesa(nir->info.stage);
232 info->num_tokens = 2; /* indicate that the shader is non-empty */
233 info->num_instructions = 2;
234
235 if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
236 info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT] =
237 nir->info.tess.tcs_vertices_out;
238 }
239
240 if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
241 if (nir->info.tess.primitive_mode == GL_ISOLINES)
242 info->properties[TGSI_PROPERTY_TES_PRIM_MODE] = PIPE_PRIM_LINES;
243 else
244 info->properties[TGSI_PROPERTY_TES_PRIM_MODE] = nir->info.tess.primitive_mode;
245
246 STATIC_ASSERT((TESS_SPACING_EQUAL + 1) % 3 == PIPE_TESS_SPACING_EQUAL);
247 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_ODD + 1) % 3 ==
248 PIPE_TESS_SPACING_FRACTIONAL_ODD);
249 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_EVEN + 1) % 3 ==
250 PIPE_TESS_SPACING_FRACTIONAL_EVEN);
251
252 info->properties[TGSI_PROPERTY_TES_SPACING] = (nir->info.tess.spacing + 1) % 3;
253 info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW] = !nir->info.tess.ccw;
254 info->properties[TGSI_PROPERTY_TES_POINT_MODE] = nir->info.tess.point_mode;
255 }
256
257 if (nir->info.stage == MESA_SHADER_GEOMETRY) {
258 info->properties[TGSI_PROPERTY_GS_INPUT_PRIM] = nir->info.gs.input_primitive;
259 info->properties[TGSI_PROPERTY_GS_OUTPUT_PRIM] = nir->info.gs.output_primitive;
260 info->properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES] = nir->info.gs.vertices_out;
261 info->properties[TGSI_PROPERTY_GS_INVOCATIONS] = nir->info.gs.invocations;
262 }
263
264 i = 0;
265 uint64_t processed_inputs = 0;
266 unsigned num_inputs = 0;
267 nir_foreach_variable(variable, &nir->inputs) {
268 unsigned semantic_name, semantic_index;
269 unsigned attrib_count = glsl_count_attribute_slots(variable->type,
270 nir->info.stage == MESA_SHADER_VERTEX);
271
272 /* Vertex shader inputs don't have semantics. The state
273 * tracker has already mapped them to attributes via
274 * variable->data.driver_location.
275 */
276 if (nir->info.stage == MESA_SHADER_VERTEX) {
277 if (glsl_type_is_dual_slot(variable->type))
278 num_inputs += 2;
279 else
280 num_inputs++;
281 continue;
282 }
283
284 assert(nir->info.stage != MESA_SHADER_FRAGMENT ||
285 (attrib_count == 1 && "not implemented"));
286
287 /* Fragment shader position is a system value. */
288 if (nir->info.stage == MESA_SHADER_FRAGMENT &&
289 variable->data.location == VARYING_SLOT_POS) {
290 if (variable->data.pixel_center_integer)
291 info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] =
292 TGSI_FS_COORD_PIXEL_CENTER_INTEGER;
293
294 num_inputs++;
295 continue;
296 }
297
298 i = variable->data.driver_location;
299 if (processed_inputs & ((uint64_t)1 << i))
300 continue;
301
302 processed_inputs |= ((uint64_t)1 << i);
303 num_inputs++;
304
305 tgsi_get_gl_varying_semantic(variable->data.location, true,
306 &semantic_name, &semantic_index);
307
308 info->input_semantic_name[i] = semantic_name;
309 info->input_semantic_index[i] = semantic_index;
310
311 if (semantic_name == TGSI_SEMANTIC_PRIMID)
312 info->uses_primid = true;
313
314 if (variable->data.sample)
315 info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_SAMPLE;
316 else if (variable->data.centroid)
317 info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_CENTROID;
318 else
319 info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_CENTER;
320
321 enum glsl_base_type base_type =
322 glsl_get_base_type(glsl_without_array(variable->type));
323
324 switch (variable->data.interpolation) {
325 case INTERP_MODE_NONE:
326 if (glsl_base_type_is_integer(base_type)) {
327 info->input_interpolate[i] = TGSI_INTERPOLATE_CONSTANT;
328 break;
329 }
330
331 if (semantic_name == TGSI_SEMANTIC_COLOR) {
332 info->input_interpolate[i] = TGSI_INTERPOLATE_COLOR;
333 break;
334 }
335 /* fall-through */
336
337 case INTERP_MODE_SMOOTH:
338 assert(!glsl_base_type_is_integer(base_type));
339
340 info->input_interpolate[i] = TGSI_INTERPOLATE_PERSPECTIVE;
341 break;
342
343 case INTERP_MODE_NOPERSPECTIVE:
344 assert(!glsl_base_type_is_integer(base_type));
345
346 info->input_interpolate[i] = TGSI_INTERPOLATE_LINEAR;
347 break;
348
349 case INTERP_MODE_FLAT:
350 info->input_interpolate[i] = TGSI_INTERPOLATE_CONSTANT;
351 break;
352 }
353
354 /* TODO make this more precise */
355 if (variable->data.location == VARYING_SLOT_COL0)
356 info->colors_read |= 0x0f;
357 else if (variable->data.location == VARYING_SLOT_COL1)
358 info->colors_read |= 0xf0;
359 }
360
361 info->num_inputs = num_inputs;
362
363
364 i = 0;
365 uint64_t processed_outputs = 0;
366 unsigned num_outputs = 0;
367 nir_foreach_variable(variable, &nir->outputs) {
368 unsigned semantic_name, semantic_index;
369
370 if (nir->info.stage == MESA_SHADER_FRAGMENT) {
371 tgsi_get_gl_frag_result_semantic(variable->data.location,
372 &semantic_name, &semantic_index);
373
374 /* Adjust for dual source blending */
375 if (variable->data.index > 0) {
376 semantic_index++;
377 }
378 } else {
379 tgsi_get_gl_varying_semantic(variable->data.location, true,
380 &semantic_name, &semantic_index);
381 }
382
383 i = variable->data.driver_location;
384 if (processed_outputs & ((uint64_t)1 << i))
385 continue;
386
387 processed_outputs |= ((uint64_t)1 << i);
388 num_outputs++;
389
390 info->output_semantic_name[i] = semantic_name;
391 info->output_semantic_index[i] = semantic_index;
392 info->output_usagemask[i] = TGSI_WRITEMASK_XYZW;
393
394 unsigned num_components = 4;
395 unsigned vector_elements = glsl_get_vector_elements(glsl_without_array(variable->type));
396 if (vector_elements)
397 num_components = vector_elements;
398
399 unsigned gs_out_streams;
400 if (variable->data.stream & (1u << 31)) {
401 gs_out_streams = variable->data.stream & ~(1u << 31);
402 } else {
403 assert(variable->data.stream < 4);
404 gs_out_streams = 0;
405 for (unsigned j = 0; j < num_components; ++j)
406 gs_out_streams |= variable->data.stream << (2 * (variable->data.location_frac + j));
407 }
408
409 unsigned streamx = gs_out_streams & 3;
410 unsigned streamy = (gs_out_streams >> 2) & 3;
411 unsigned streamz = (gs_out_streams >> 4) & 3;
412 unsigned streamw = (gs_out_streams >> 6) & 3;
413
414 if (info->output_usagemask[i] & TGSI_WRITEMASK_X) {
415 info->output_streams[i] |= streamx;
416 info->num_stream_output_components[streamx]++;
417 }
418 if (info->output_usagemask[i] & TGSI_WRITEMASK_Y) {
419 info->output_streams[i] |= streamy << 2;
420 info->num_stream_output_components[streamy]++;
421 }
422 if (info->output_usagemask[i] & TGSI_WRITEMASK_Z) {
423 info->output_streams[i] |= streamz << 4;
424 info->num_stream_output_components[streamz]++;
425 }
426 if (info->output_usagemask[i] & TGSI_WRITEMASK_W) {
427 info->output_streams[i] |= streamw << 6;
428 info->num_stream_output_components[streamw]++;
429 }
430
431 switch (semantic_name) {
432 case TGSI_SEMANTIC_PRIMID:
433 info->writes_primid = true;
434 break;
435 case TGSI_SEMANTIC_VIEWPORT_INDEX:
436 info->writes_viewport_index = true;
437 break;
438 case TGSI_SEMANTIC_LAYER:
439 info->writes_layer = true;
440 break;
441 case TGSI_SEMANTIC_PSIZE:
442 info->writes_psize = true;
443 break;
444 case TGSI_SEMANTIC_CLIPVERTEX:
445 info->writes_clipvertex = true;
446 break;
447 case TGSI_SEMANTIC_COLOR:
448 info->colors_written |= 1 << semantic_index;
449 break;
450 case TGSI_SEMANTIC_STENCIL:
451 info->writes_stencil = true;
452 break;
453 case TGSI_SEMANTIC_SAMPLEMASK:
454 info->writes_samplemask = true;
455 break;
456 case TGSI_SEMANTIC_EDGEFLAG:
457 info->writes_edgeflag = true;
458 break;
459 case TGSI_SEMANTIC_POSITION:
460 if (info->processor == PIPE_SHADER_FRAGMENT)
461 info->writes_z = true;
462 else
463 info->writes_position = true;
464 break;
465 }
466
467 if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
468 switch (semantic_name) {
469 case TGSI_SEMANTIC_PATCH:
470 info->reads_perpatch_outputs = true;
471 break;
472 case TGSI_SEMANTIC_TESSINNER:
473 case TGSI_SEMANTIC_TESSOUTER:
474 info->reads_tessfactor_outputs = true;
475 break;
476 default:
477 info->reads_pervertex_outputs = true;
478 }
479 }
480 }
481
482 info->num_outputs = num_outputs;
483
484 nir_foreach_variable(variable, &nir->uniforms) {
485 const struct glsl_type *type = variable->type;
486 enum glsl_base_type base_type =
487 glsl_get_base_type(glsl_without_array(type));
488 unsigned aoa_size = MAX2(1, glsl_get_aoa_size(type));
489
490 /* We rely on the fact that nir_lower_samplers_as_deref has
491 * eliminated struct dereferences.
492 */
493 if (base_type == GLSL_TYPE_SAMPLER)
494 info->samplers_declared |=
495 u_bit_consecutive(variable->data.binding, aoa_size);
496 else if (base_type == GLSL_TYPE_IMAGE)
497 info->images_declared |=
498 u_bit_consecutive(variable->data.binding, aoa_size);
499 }
500
501 info->num_written_clipdistance = nir->info.clip_distance_array_size;
502 info->num_written_culldistance = nir->info.cull_distance_array_size;
503 info->clipdist_writemask = u_bit_consecutive(0, info->num_written_clipdistance);
504 info->culldist_writemask = u_bit_consecutive(0, info->num_written_culldistance);
505
506 if (info->processor == PIPE_SHADER_FRAGMENT)
507 info->uses_kill = nir->info.fs.uses_discard;
508
509 /* TODO make this more accurate */
510 info->const_buffers_declared = u_bit_consecutive(0, SI_NUM_CONST_BUFFERS);
511 info->shader_buffers_declared = u_bit_consecutive(0, SI_NUM_SHADER_BUFFERS);
512
513 func = (struct nir_function *)exec_list_get_head_const(&nir->functions);
514 nir_foreach_block(block, func->impl) {
515 nir_foreach_instr(instr, block)
516 scan_instruction(info, instr);
517 }
518 }
519
520 /**
521 * Perform "lowering" operations on the NIR that are run once when the shader
522 * selector is created.
523 */
524 void
525 si_lower_nir(struct si_shader_selector* sel)
526 {
527 /* Adjust the driver location of inputs and outputs. The state tracker
528 * interprets them as slots, while the ac/nir backend interprets them
529 * as individual components.
530 */
531 nir_foreach_variable(variable, &sel->nir->inputs)
532 variable->data.driver_location *= 4;
533
534 nir_foreach_variable(variable, &sel->nir->outputs) {
535 variable->data.driver_location *= 4;
536
537 if (sel->nir->info.stage == MESA_SHADER_FRAGMENT) {
538 if (variable->data.location == FRAG_RESULT_DEPTH)
539 variable->data.driver_location += 2;
540 else if (variable->data.location == FRAG_RESULT_STENCIL)
541 variable->data.driver_location += 1;
542 }
543 }
544
545 /* Perform lowerings (and optimizations) of code.
546 *
547 * Performance considerations aside, we must:
548 * - lower certain ALU operations
549 * - ensure constant offsets for texture instructions are folded
550 * and copy-propagated
551 */
552 NIR_PASS_V(sel->nir, nir_lower_io, nir_var_uniform, type_size,
553 (nir_lower_io_options)0);
554 NIR_PASS_V(sel->nir, nir_lower_uniforms_to_ubo);
555
556 NIR_PASS_V(sel->nir, nir_lower_returns);
557 NIR_PASS_V(sel->nir, nir_lower_vars_to_ssa);
558 NIR_PASS_V(sel->nir, nir_lower_alu_to_scalar);
559 NIR_PASS_V(sel->nir, nir_lower_phis_to_scalar);
560
561 static const struct nir_lower_tex_options lower_tex_options = {
562 .lower_txp = ~0u,
563 };
564 NIR_PASS_V(sel->nir, nir_lower_tex, &lower_tex_options);
565
566 const nir_lower_subgroups_options subgroups_options = {
567 .subgroup_size = 64,
568 .ballot_bit_size = 32,
569 .lower_to_scalar = true,
570 .lower_subgroup_masks = true,
571 .lower_vote_trivial = false,
572 };
573 NIR_PASS_V(sel->nir, nir_lower_subgroups, &subgroups_options);
574
575 bool progress;
576 do {
577 progress = false;
578
579 /* (Constant) copy propagation is needed for txf with offsets. */
580 NIR_PASS(progress, sel->nir, nir_copy_prop);
581 NIR_PASS(progress, sel->nir, nir_opt_remove_phis);
582 NIR_PASS(progress, sel->nir, nir_opt_dce);
583 if (nir_opt_trivial_continues(sel->nir)) {
584 progress = true;
585 NIR_PASS(progress, sel->nir, nir_copy_prop);
586 NIR_PASS(progress, sel->nir, nir_opt_dce);
587 }
588 NIR_PASS(progress, sel->nir, nir_opt_if);
589 NIR_PASS(progress, sel->nir, nir_opt_dead_cf);
590 NIR_PASS(progress, sel->nir, nir_opt_cse);
591 NIR_PASS(progress, sel->nir, nir_opt_peephole_select, 8);
592
593 /* Needed for algebraic lowering */
594 NIR_PASS(progress, sel->nir, nir_opt_algebraic);
595 NIR_PASS(progress, sel->nir, nir_opt_constant_folding);
596
597 NIR_PASS(progress, sel->nir, nir_opt_undef);
598 NIR_PASS(progress, sel->nir, nir_opt_conditional_discard);
599 if (sel->nir->options->max_unroll_iterations) {
600 NIR_PASS(progress, sel->nir, nir_opt_loop_unroll, 0);
601 }
602 } while (progress);
603 }
604
605 static void declare_nir_input_vs(struct si_shader_context *ctx,
606 struct nir_variable *variable,
607 unsigned input_index,
608 LLVMValueRef out[4])
609 {
610 si_llvm_load_input_vs(ctx, input_index, out);
611 }
612
613 static void declare_nir_input_fs(struct si_shader_context *ctx,
614 struct nir_variable *variable,
615 unsigned input_index,
616 LLVMValueRef out[4])
617 {
618 unsigned slot = variable->data.location;
619 if (slot == VARYING_SLOT_POS) {
620 out[0] = LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT);
621 out[1] = LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT);
622 out[2] = LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Z_FLOAT);
623 out[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
624 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_W_FLOAT));
625 return;
626 }
627
628 si_llvm_load_input_fs(ctx, input_index, out);
629 }
630
631 LLVMValueRef si_nir_load_input_gs(struct ac_shader_abi *abi,
632 unsigned location,
633 unsigned driver_location,
634 unsigned component,
635 unsigned num_components,
636 unsigned vertex_index,
637 unsigned const_index,
638 LLVMTypeRef type)
639 {
640 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
641
642 LLVMValueRef value[4];
643 for (unsigned i = component; i < num_components + component; i++) {
644 value[i] = si_llvm_load_input_gs(&ctx->abi, driver_location / 4,
645 vertex_index, type, i);
646 }
647
648 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
649 }
650
651 static LLVMValueRef
652 si_nir_load_sampler_desc(struct ac_shader_abi *abi,
653 unsigned descriptor_set, unsigned base_index,
654 unsigned constant_index, LLVMValueRef dynamic_index,
655 enum ac_descriptor_type desc_type, bool image,
656 bool write)
657 {
658 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
659 LLVMBuilderRef builder = ctx->ac.builder;
660 LLVMValueRef list = LLVMGetParam(ctx->main_fn, ctx->param_samplers_and_images);
661 LLVMValueRef index = dynamic_index;
662
663 assert(!descriptor_set);
664
665 if (!index)
666 index = ctx->ac.i32_0;
667
668 index = LLVMBuildAdd(builder, index,
669 LLVMConstInt(ctx->ac.i32, base_index + constant_index, false),
670 "");
671
672 if (image) {
673 assert(desc_type == AC_DESC_IMAGE || desc_type == AC_DESC_BUFFER);
674 assert(base_index + constant_index < ctx->num_images);
675
676 if (dynamic_index)
677 index = si_llvm_bound_index(ctx, index, ctx->num_images);
678
679 index = LLVMBuildSub(ctx->gallivm.builder,
680 LLVMConstInt(ctx->i32, SI_NUM_IMAGES - 1, 0),
681 index, "");
682
683 /* TODO: be smarter about when we use dcc_off */
684 return si_load_image_desc(ctx, list, index, desc_type, write);
685 }
686
687 assert(base_index + constant_index < ctx->num_samplers);
688
689 if (dynamic_index)
690 index = si_llvm_bound_index(ctx, index, ctx->num_samplers);
691
692 index = LLVMBuildAdd(ctx->gallivm.builder, index,
693 LLVMConstInt(ctx->i32, SI_NUM_IMAGES / 2, 0), "");
694
695 return si_load_sampler_desc(ctx, list, index, desc_type);
696 }
697
698 static void bitcast_inputs(struct si_shader_context *ctx,
699 LLVMValueRef data[4],
700 unsigned input_idx)
701 {
702 for (unsigned chan = 0; chan < 4; chan++) {
703 ctx->inputs[input_idx + chan] =
704 LLVMBuildBitCast(ctx->ac.builder, data[chan], ctx->ac.i32, "");
705 }
706 }
707
708 bool si_nir_build_llvm(struct si_shader_context *ctx, struct nir_shader *nir)
709 {
710 struct tgsi_shader_info *info = &ctx->shader->selector->info;
711
712 if (nir->info.stage == MESA_SHADER_VERTEX ||
713 nir->info.stage == MESA_SHADER_FRAGMENT) {
714 uint64_t processed_inputs = 0;
715 nir_foreach_variable(variable, &nir->inputs) {
716 unsigned attrib_count = glsl_count_attribute_slots(variable->type,
717 nir->info.stage == MESA_SHADER_VERTEX);
718 unsigned input_idx = variable->data.driver_location;
719
720 assert(attrib_count == 1);
721
722 LLVMValueRef data[4];
723 unsigned loc = variable->data.location;
724
725 /* Packed components share the same location so skip
726 * them if we have already processed the location.
727 */
728 if (processed_inputs & ((uint64_t)1 << loc))
729 continue;
730
731 if (nir->info.stage == MESA_SHADER_VERTEX) {
732 declare_nir_input_vs(ctx, variable, input_idx / 4, data);
733 bitcast_inputs(ctx, data, input_idx);
734 if (glsl_type_is_dual_slot(variable->type)) {
735 input_idx += 4;
736 declare_nir_input_vs(ctx, variable, input_idx / 4, data);
737 bitcast_inputs(ctx, data, input_idx);
738 }
739 } else if (nir->info.stage == MESA_SHADER_FRAGMENT) {
740 declare_nir_input_fs(ctx, variable, input_idx / 4, data);
741 bitcast_inputs(ctx, data, input_idx);
742 }
743
744 processed_inputs |= ((uint64_t)1 << loc);
745 }
746 }
747
748 ctx->abi.inputs = &ctx->inputs[0];
749 ctx->abi.load_sampler_desc = si_nir_load_sampler_desc;
750 ctx->abi.clamp_shadow_reference = true;
751
752 ctx->num_samplers = util_last_bit(info->samplers_declared);
753 ctx->num_images = util_last_bit(info->images_declared);
754
755 ac_nir_translate(&ctx->ac, &ctx->abi, nir, NULL);
756
757 return true;
758 }