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[mesa.git] / src / gallium / drivers / radeonsi / si_shader_tgsi_alu.c
1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "si_shader_internal.h"
25 #include "gallivm/lp_bld_const.h"
26 #include "gallivm/lp_bld_intr.h"
27 #include "gallivm/lp_bld_gather.h"
28 #include "tgsi/tgsi_parse.h"
29
30 static void kill_if_fetch_args(struct lp_build_tgsi_context *bld_base,
31 struct lp_build_emit_data *emit_data)
32 {
33 const struct tgsi_full_instruction *inst = emit_data->inst;
34 struct gallivm_state *gallivm = bld_base->base.gallivm;
35 LLVMBuilderRef builder = gallivm->builder;
36 unsigned i;
37 LLVMValueRef conds[TGSI_NUM_CHANNELS];
38
39 for (i = 0; i < TGSI_NUM_CHANNELS; i++) {
40 LLVMValueRef value = lp_build_emit_fetch(bld_base, inst, 0, i);
41 conds[i] = LLVMBuildFCmp(builder, LLVMRealOLT, value,
42 bld_base->base.zero, "");
43 }
44
45 /* Or the conditions together */
46 for (i = TGSI_NUM_CHANNELS - 1; i > 0; i--) {
47 conds[i - 1] = LLVMBuildOr(builder, conds[i], conds[i - 1], "");
48 }
49
50 emit_data->dst_type = LLVMVoidTypeInContext(gallivm->context);
51 emit_data->arg_count = 1;
52 emit_data->args[0] = LLVMBuildSelect(builder, conds[0],
53 lp_build_const_float(gallivm, -1.0f),
54 bld_base->base.zero, "");
55 }
56
57 static void kil_emit(const struct lp_build_tgsi_action *action,
58 struct lp_build_tgsi_context *bld_base,
59 struct lp_build_emit_data *emit_data)
60 {
61 lp_build_intrinsic(bld_base->base.gallivm->builder,
62 action->intr_name, emit_data->dst_type,
63 &emit_data->args[0], 1, LP_FUNC_ATTR_LEGACY);
64 }
65
66 static void emit_icmp(const struct lp_build_tgsi_action *action,
67 struct lp_build_tgsi_context *bld_base,
68 struct lp_build_emit_data *emit_data)
69 {
70 unsigned pred;
71 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
72 LLVMContextRef context = bld_base->base.gallivm->context;
73
74 switch (emit_data->inst->Instruction.Opcode) {
75 case TGSI_OPCODE_USEQ:
76 case TGSI_OPCODE_U64SEQ: pred = LLVMIntEQ; break;
77 case TGSI_OPCODE_USNE:
78 case TGSI_OPCODE_U64SNE: pred = LLVMIntNE; break;
79 case TGSI_OPCODE_USGE:
80 case TGSI_OPCODE_U64SGE: pred = LLVMIntUGE; break;
81 case TGSI_OPCODE_USLT:
82 case TGSI_OPCODE_U64SLT: pred = LLVMIntULT; break;
83 case TGSI_OPCODE_ISGE:
84 case TGSI_OPCODE_I64SGE: pred = LLVMIntSGE; break;
85 case TGSI_OPCODE_ISLT:
86 case TGSI_OPCODE_I64SLT: pred = LLVMIntSLT; break;
87 default:
88 assert(!"unknown instruction");
89 pred = 0;
90 break;
91 }
92
93 LLVMValueRef v = LLVMBuildICmp(builder, pred,
94 emit_data->args[0], emit_data->args[1],"");
95
96 v = LLVMBuildSExtOrBitCast(builder, v,
97 LLVMInt32TypeInContext(context), "");
98
99 emit_data->output[emit_data->chan] = v;
100 }
101
102 static void emit_ucmp(const struct lp_build_tgsi_action *action,
103 struct lp_build_tgsi_context *bld_base,
104 struct lp_build_emit_data *emit_data)
105 {
106 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
107
108 LLVMValueRef arg0 = LLVMBuildBitCast(builder, emit_data->args[0],
109 bld_base->uint_bld.elem_type, "");
110
111 LLVMValueRef v = LLVMBuildICmp(builder, LLVMIntNE, arg0,
112 bld_base->uint_bld.zero, "");
113
114 emit_data->output[emit_data->chan] =
115 LLVMBuildSelect(builder, v, emit_data->args[1], emit_data->args[2], "");
116 }
117
118 static void emit_cmp(const struct lp_build_tgsi_action *action,
119 struct lp_build_tgsi_context *bld_base,
120 struct lp_build_emit_data *emit_data)
121 {
122 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
123 LLVMValueRef cond, *args = emit_data->args;
124
125 cond = LLVMBuildFCmp(builder, LLVMRealOLT, args[0],
126 bld_base->base.zero, "");
127
128 emit_data->output[emit_data->chan] =
129 LLVMBuildSelect(builder, cond, args[1], args[2], "");
130 }
131
132 static void emit_set_cond(const struct lp_build_tgsi_action *action,
133 struct lp_build_tgsi_context *bld_base,
134 struct lp_build_emit_data *emit_data)
135 {
136 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
137 LLVMRealPredicate pred;
138 LLVMValueRef cond;
139
140 /* Use ordered for everything but NE (which is usual for
141 * float comparisons)
142 */
143 switch (emit_data->inst->Instruction.Opcode) {
144 case TGSI_OPCODE_SGE: pred = LLVMRealOGE; break;
145 case TGSI_OPCODE_SEQ: pred = LLVMRealOEQ; break;
146 case TGSI_OPCODE_SLE: pred = LLVMRealOLE; break;
147 case TGSI_OPCODE_SLT: pred = LLVMRealOLT; break;
148 case TGSI_OPCODE_SNE: pred = LLVMRealUNE; break;
149 case TGSI_OPCODE_SGT: pred = LLVMRealOGT; break;
150 default: assert(!"unknown instruction"); pred = 0; break;
151 }
152
153 cond = LLVMBuildFCmp(builder,
154 pred, emit_data->args[0], emit_data->args[1], "");
155
156 emit_data->output[emit_data->chan] = LLVMBuildSelect(builder,
157 cond, bld_base->base.one, bld_base->base.zero, "");
158 }
159
160 static void emit_fcmp(const struct lp_build_tgsi_action *action,
161 struct lp_build_tgsi_context *bld_base,
162 struct lp_build_emit_data *emit_data)
163 {
164 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
165 LLVMContextRef context = bld_base->base.gallivm->context;
166 LLVMRealPredicate pred;
167
168 /* Use ordered for everything but NE (which is usual for
169 * float comparisons)
170 */
171 switch (emit_data->inst->Instruction.Opcode) {
172 case TGSI_OPCODE_FSEQ: pred = LLVMRealOEQ; break;
173 case TGSI_OPCODE_FSGE: pred = LLVMRealOGE; break;
174 case TGSI_OPCODE_FSLT: pred = LLVMRealOLT; break;
175 case TGSI_OPCODE_FSNE: pred = LLVMRealUNE; break;
176 default: assert(!"unknown instruction"); pred = 0; break;
177 }
178
179 LLVMValueRef v = LLVMBuildFCmp(builder, pred,
180 emit_data->args[0], emit_data->args[1],"");
181
182 v = LLVMBuildSExtOrBitCast(builder, v,
183 LLVMInt32TypeInContext(context), "");
184
185 emit_data->output[emit_data->chan] = v;
186 }
187
188 static void emit_dcmp(const struct lp_build_tgsi_action *action,
189 struct lp_build_tgsi_context *bld_base,
190 struct lp_build_emit_data *emit_data)
191 {
192 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
193 LLVMContextRef context = bld_base->base.gallivm->context;
194 LLVMRealPredicate pred;
195
196 /* Use ordered for everything but NE (which is usual for
197 * float comparisons)
198 */
199 switch (emit_data->inst->Instruction.Opcode) {
200 case TGSI_OPCODE_DSEQ: pred = LLVMRealOEQ; break;
201 case TGSI_OPCODE_DSGE: pred = LLVMRealOGE; break;
202 case TGSI_OPCODE_DSLT: pred = LLVMRealOLT; break;
203 case TGSI_OPCODE_DSNE: pred = LLVMRealUNE; break;
204 default: assert(!"unknown instruction"); pred = 0; break;
205 }
206
207 LLVMValueRef v = LLVMBuildFCmp(builder, pred,
208 emit_data->args[0], emit_data->args[1],"");
209
210 v = LLVMBuildSExtOrBitCast(builder, v,
211 LLVMInt32TypeInContext(context), "");
212
213 emit_data->output[emit_data->chan] = v;
214 }
215
216 static void emit_not(const struct lp_build_tgsi_action *action,
217 struct lp_build_tgsi_context *bld_base,
218 struct lp_build_emit_data *emit_data)
219 {
220 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
221 LLVMValueRef v = bitcast(bld_base, TGSI_TYPE_UNSIGNED,
222 emit_data->args[0]);
223 emit_data->output[emit_data->chan] = LLVMBuildNot(builder, v, "");
224 }
225
226 static void emit_arl(const struct lp_build_tgsi_action *action,
227 struct lp_build_tgsi_context *bld_base,
228 struct lp_build_emit_data *emit_data)
229 {
230 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
231 LLVMValueRef floor_index = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_FLR, emit_data->args[0]);
232 emit_data->output[emit_data->chan] = LLVMBuildFPToSI(builder,
233 floor_index, bld_base->base.int_elem_type , "");
234 }
235
236 static void emit_and(const struct lp_build_tgsi_action *action,
237 struct lp_build_tgsi_context *bld_base,
238 struct lp_build_emit_data *emit_data)
239 {
240 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
241 emit_data->output[emit_data->chan] = LLVMBuildAnd(builder,
242 emit_data->args[0], emit_data->args[1], "");
243 }
244
245 static void emit_or(const struct lp_build_tgsi_action *action,
246 struct lp_build_tgsi_context *bld_base,
247 struct lp_build_emit_data *emit_data)
248 {
249 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
250 emit_data->output[emit_data->chan] = LLVMBuildOr(builder,
251 emit_data->args[0], emit_data->args[1], "");
252 }
253
254 static void emit_uadd(const struct lp_build_tgsi_action *action,
255 struct lp_build_tgsi_context *bld_base,
256 struct lp_build_emit_data *emit_data)
257 {
258 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
259 emit_data->output[emit_data->chan] = LLVMBuildAdd(builder,
260 emit_data->args[0], emit_data->args[1], "");
261 }
262
263 static void emit_udiv(const struct lp_build_tgsi_action *action,
264 struct lp_build_tgsi_context *bld_base,
265 struct lp_build_emit_data *emit_data)
266 {
267 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
268 emit_data->output[emit_data->chan] = LLVMBuildUDiv(builder,
269 emit_data->args[0], emit_data->args[1], "");
270 }
271
272 static void emit_idiv(const struct lp_build_tgsi_action *action,
273 struct lp_build_tgsi_context *bld_base,
274 struct lp_build_emit_data *emit_data)
275 {
276 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
277 emit_data->output[emit_data->chan] = LLVMBuildSDiv(builder,
278 emit_data->args[0], emit_data->args[1], "");
279 }
280
281 static void emit_mod(const struct lp_build_tgsi_action *action,
282 struct lp_build_tgsi_context *bld_base,
283 struct lp_build_emit_data *emit_data)
284 {
285 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
286 emit_data->output[emit_data->chan] = LLVMBuildSRem(builder,
287 emit_data->args[0], emit_data->args[1], "");
288 }
289
290 static void emit_umod(const struct lp_build_tgsi_action *action,
291 struct lp_build_tgsi_context *bld_base,
292 struct lp_build_emit_data *emit_data)
293 {
294 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
295 emit_data->output[emit_data->chan] = LLVMBuildURem(builder,
296 emit_data->args[0], emit_data->args[1], "");
297 }
298
299 static void emit_shl(const struct lp_build_tgsi_action *action,
300 struct lp_build_tgsi_context *bld_base,
301 struct lp_build_emit_data *emit_data)
302 {
303 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
304 emit_data->output[emit_data->chan] = LLVMBuildShl(builder,
305 emit_data->args[0], emit_data->args[1], "");
306 }
307
308 static void emit_ushr(const struct lp_build_tgsi_action *action,
309 struct lp_build_tgsi_context *bld_base,
310 struct lp_build_emit_data *emit_data)
311 {
312 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
313 emit_data->output[emit_data->chan] = LLVMBuildLShr(builder,
314 emit_data->args[0], emit_data->args[1], "");
315 }
316 static void emit_ishr(const struct lp_build_tgsi_action *action,
317 struct lp_build_tgsi_context *bld_base,
318 struct lp_build_emit_data *emit_data)
319 {
320 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
321 emit_data->output[emit_data->chan] = LLVMBuildAShr(builder,
322 emit_data->args[0], emit_data->args[1], "");
323 }
324
325 static void emit_xor(const struct lp_build_tgsi_action *action,
326 struct lp_build_tgsi_context *bld_base,
327 struct lp_build_emit_data *emit_data)
328 {
329 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
330 emit_data->output[emit_data->chan] = LLVMBuildXor(builder,
331 emit_data->args[0], emit_data->args[1], "");
332 }
333
334 static void emit_ssg(const struct lp_build_tgsi_action *action,
335 struct lp_build_tgsi_context *bld_base,
336 struct lp_build_emit_data *emit_data)
337 {
338 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
339
340 LLVMValueRef cmp, val;
341
342 if (emit_data->inst->Instruction.Opcode == TGSI_OPCODE_I64SSG) {
343 cmp = LLVMBuildICmp(builder, LLVMIntSGT, emit_data->args[0], bld_base->int64_bld.zero, "");
344 val = LLVMBuildSelect(builder, cmp, bld_base->int64_bld.one, emit_data->args[0], "");
345 cmp = LLVMBuildICmp(builder, LLVMIntSGE, val, bld_base->int64_bld.zero, "");
346 val = LLVMBuildSelect(builder, cmp, val, LLVMConstInt(bld_base->int64_bld.elem_type, -1, true), "");
347 } else if (emit_data->inst->Instruction.Opcode == TGSI_OPCODE_ISSG) {
348 cmp = LLVMBuildICmp(builder, LLVMIntSGT, emit_data->args[0], bld_base->int_bld.zero, "");
349 val = LLVMBuildSelect(builder, cmp, bld_base->int_bld.one, emit_data->args[0], "");
350 cmp = LLVMBuildICmp(builder, LLVMIntSGE, val, bld_base->int_bld.zero, "");
351 val = LLVMBuildSelect(builder, cmp, val, LLVMConstInt(bld_base->int_bld.elem_type, -1, true), "");
352 } else { // float SSG
353 cmp = LLVMBuildFCmp(builder, LLVMRealOGT, emit_data->args[0], bld_base->base.zero, "");
354 val = LLVMBuildSelect(builder, cmp, bld_base->base.one, emit_data->args[0], "");
355 cmp = LLVMBuildFCmp(builder, LLVMRealOGE, val, bld_base->base.zero, "");
356 val = LLVMBuildSelect(builder, cmp, val, LLVMConstReal(bld_base->base.elem_type, -1), "");
357 }
358
359 emit_data->output[emit_data->chan] = val;
360 }
361
362 static void emit_ineg(const struct lp_build_tgsi_action *action,
363 struct lp_build_tgsi_context *bld_base,
364 struct lp_build_emit_data *emit_data)
365 {
366 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
367 emit_data->output[emit_data->chan] = LLVMBuildNeg(builder,
368 emit_data->args[0], "");
369 }
370
371 static void emit_dneg(const struct lp_build_tgsi_action *action,
372 struct lp_build_tgsi_context *bld_base,
373 struct lp_build_emit_data *emit_data)
374 {
375 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
376 emit_data->output[emit_data->chan] = LLVMBuildFNeg(builder,
377 emit_data->args[0], "");
378 }
379
380 static void emit_frac(const struct lp_build_tgsi_action *action,
381 struct lp_build_tgsi_context *bld_base,
382 struct lp_build_emit_data *emit_data)
383 {
384 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
385 char *intr;
386
387 if (emit_data->info->opcode == TGSI_OPCODE_FRC)
388 intr = "llvm.floor.f32";
389 else if (emit_data->info->opcode == TGSI_OPCODE_DFRAC)
390 intr = "llvm.floor.f64";
391 else {
392 assert(0);
393 return;
394 }
395
396 LLVMValueRef floor = lp_build_intrinsic(builder, intr, emit_data->dst_type,
397 &emit_data->args[0], 1,
398 LP_FUNC_ATTR_READNONE);
399 emit_data->output[emit_data->chan] = LLVMBuildFSub(builder,
400 emit_data->args[0], floor, "");
401 }
402
403 static void emit_f2i(const struct lp_build_tgsi_action *action,
404 struct lp_build_tgsi_context *bld_base,
405 struct lp_build_emit_data *emit_data)
406 {
407 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
408 emit_data->output[emit_data->chan] = LLVMBuildFPToSI(builder,
409 emit_data->args[0], bld_base->int_bld.elem_type, "");
410 }
411
412 static void emit_f2u(const struct lp_build_tgsi_action *action,
413 struct lp_build_tgsi_context *bld_base,
414 struct lp_build_emit_data *emit_data)
415 {
416 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
417 emit_data->output[emit_data->chan] = LLVMBuildFPToUI(builder,
418 emit_data->args[0], bld_base->uint_bld.elem_type, "");
419 }
420
421 static void emit_i2f(const struct lp_build_tgsi_action *action,
422 struct lp_build_tgsi_context *bld_base,
423 struct lp_build_emit_data *emit_data)
424 {
425 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
426 emit_data->output[emit_data->chan] = LLVMBuildSIToFP(builder,
427 emit_data->args[0], bld_base->base.elem_type, "");
428 }
429
430 static void emit_u2f(const struct lp_build_tgsi_action *action,
431 struct lp_build_tgsi_context *bld_base,
432 struct lp_build_emit_data *emit_data)
433 {
434 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
435 emit_data->output[emit_data->chan] = LLVMBuildUIToFP(builder,
436 emit_data->args[0], bld_base->base.elem_type, "");
437 }
438
439 static void
440 build_tgsi_intrinsic_nomem(const struct lp_build_tgsi_action *action,
441 struct lp_build_tgsi_context *bld_base,
442 struct lp_build_emit_data *emit_data)
443 {
444 struct lp_build_context *base = &bld_base->base;
445 emit_data->output[emit_data->chan] =
446 lp_build_intrinsic(base->gallivm->builder, action->intr_name,
447 emit_data->dst_type, emit_data->args,
448 emit_data->arg_count, LP_FUNC_ATTR_READNONE);
449 }
450
451 static void emit_bfi(const struct lp_build_tgsi_action *action,
452 struct lp_build_tgsi_context *bld_base,
453 struct lp_build_emit_data *emit_data)
454 {
455 struct gallivm_state *gallivm = bld_base->base.gallivm;
456 LLVMBuilderRef builder = gallivm->builder;
457 LLVMValueRef bfi_args[3];
458 LLVMValueRef bfi_sm5;
459 LLVMValueRef cond;
460
461 // Calculate the bitmask: (((1 << src3) - 1) << src2
462 bfi_args[0] = LLVMBuildShl(builder,
463 LLVMBuildSub(builder,
464 LLVMBuildShl(builder,
465 bld_base->int_bld.one,
466 emit_data->args[3], ""),
467 bld_base->int_bld.one, ""),
468 emit_data->args[2], "");
469
470 bfi_args[1] = LLVMBuildShl(builder, emit_data->args[1],
471 emit_data->args[2], "");
472
473 bfi_args[2] = emit_data->args[0];
474
475 /* Calculate:
476 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
477 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
478 */
479 bfi_sm5 =
480 LLVMBuildXor(builder, bfi_args[2],
481 LLVMBuildAnd(builder, bfi_args[0],
482 LLVMBuildXor(builder, bfi_args[1], bfi_args[2],
483 ""), ""), "");
484
485 /* Since shifts of >= 32 bits are undefined in LLVM IR, the backend
486 * uses the convenient V_BFI lowering for the above, which follows SM5
487 * and disagrees with GLSL semantics when bits (src3) is 32.
488 */
489 cond = LLVMBuildICmp(builder, LLVMIntUGE, emit_data->args[3],
490 lp_build_const_int32(gallivm, 32), "");
491 emit_data->output[emit_data->chan] =
492 LLVMBuildSelect(builder, cond, emit_data->args[1], bfi_sm5, "");
493 }
494
495 static void emit_bfe(const struct lp_build_tgsi_action *action,
496 struct lp_build_tgsi_context *bld_base,
497 struct lp_build_emit_data *emit_data)
498 {
499 struct gallivm_state *gallivm = bld_base->base.gallivm;
500 LLVMBuilderRef builder = gallivm->builder;
501 LLVMValueRef bfe_sm5;
502 LLVMValueRef cond;
503
504 bfe_sm5 = lp_build_intrinsic(builder, action->intr_name,
505 emit_data->dst_type, emit_data->args,
506 emit_data->arg_count,
507 LP_FUNC_ATTR_READNONE |
508 LP_FUNC_ATTR_LEGACY);
509
510 /* Correct for GLSL semantics. */
511 cond = LLVMBuildICmp(builder, LLVMIntUGE, emit_data->args[2],
512 lp_build_const_int32(gallivm, 32), "");
513 emit_data->output[emit_data->chan] =
514 LLVMBuildSelect(builder, cond, emit_data->args[0], bfe_sm5, "");
515 }
516
517 /* this is ffs in C */
518 static void emit_lsb(const struct lp_build_tgsi_action *action,
519 struct lp_build_tgsi_context *bld_base,
520 struct lp_build_emit_data *emit_data)
521 {
522 struct gallivm_state *gallivm = bld_base->base.gallivm;
523 LLVMBuilderRef builder = gallivm->builder;
524 LLVMValueRef args[2] = {
525 emit_data->args[0],
526
527 /* The value of 1 means that ffs(x=0) = undef, so LLVM won't
528 * add special code to check for x=0. The reason is that
529 * the LLVM behavior for x=0 is different from what we
530 * need here. However, LLVM also assumes that ffs(x) is
531 * in [0, 31], but GLSL expects that ffs(0) = -1, so
532 * a conditional assignment to handle 0 is still required.
533 */
534 LLVMConstInt(LLVMInt1TypeInContext(gallivm->context), 1, 0)
535 };
536
537 LLVMValueRef lsb =
538 lp_build_intrinsic(gallivm->builder, "llvm.cttz.i32",
539 emit_data->dst_type, args, ARRAY_SIZE(args),
540 LP_FUNC_ATTR_READNONE);
541
542 /* TODO: We need an intrinsic to skip this conditional. */
543 /* Check for zero: */
544 emit_data->output[emit_data->chan] =
545 LLVMBuildSelect(builder,
546 LLVMBuildICmp(builder, LLVMIntEQ, args[0],
547 bld_base->uint_bld.zero, ""),
548 lp_build_const_int32(gallivm, -1), lsb, "");
549 }
550
551 /* Find the last bit set. */
552 static void emit_umsb(const struct lp_build_tgsi_action *action,
553 struct lp_build_tgsi_context *bld_base,
554 struct lp_build_emit_data *emit_data)
555 {
556 struct si_shader_context *ctx = si_shader_context(bld_base);
557
558 emit_data->output[emit_data->chan] =
559 ac_emit_umsb(&ctx->ac, emit_data->args[0], emit_data->dst_type);
560 }
561
562 /* Find the last bit opposite of the sign bit. */
563 static void emit_imsb(const struct lp_build_tgsi_action *action,
564 struct lp_build_tgsi_context *bld_base,
565 struct lp_build_emit_data *emit_data)
566 {
567 struct si_shader_context *ctx = si_shader_context(bld_base);
568 emit_data->output[emit_data->chan] =
569 ac_emit_imsb(&ctx->ac, emit_data->args[0],
570 emit_data->dst_type);
571 }
572
573 static void emit_iabs(const struct lp_build_tgsi_action *action,
574 struct lp_build_tgsi_context *bld_base,
575 struct lp_build_emit_data *emit_data)
576 {
577 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
578
579 emit_data->output[emit_data->chan] =
580 lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_IMAX,
581 emit_data->args[0],
582 LLVMBuildNeg(builder,
583 emit_data->args[0], ""));
584 }
585
586 static void emit_minmax_int(const struct lp_build_tgsi_action *action,
587 struct lp_build_tgsi_context *bld_base,
588 struct lp_build_emit_data *emit_data)
589 {
590 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
591 LLVMIntPredicate op;
592
593 switch (emit_data->info->opcode) {
594 default:
595 assert(0);
596 case TGSI_OPCODE_IMAX:
597 case TGSI_OPCODE_I64MAX:
598 op = LLVMIntSGT;
599 break;
600 case TGSI_OPCODE_IMIN:
601 case TGSI_OPCODE_I64MIN:
602 op = LLVMIntSLT;
603 break;
604 case TGSI_OPCODE_UMAX:
605 case TGSI_OPCODE_U64MAX:
606 op = LLVMIntUGT;
607 break;
608 case TGSI_OPCODE_UMIN:
609 case TGSI_OPCODE_U64MIN:
610 op = LLVMIntULT;
611 break;
612 }
613
614 emit_data->output[emit_data->chan] =
615 LLVMBuildSelect(builder,
616 LLVMBuildICmp(builder, op, emit_data->args[0],
617 emit_data->args[1], ""),
618 emit_data->args[0],
619 emit_data->args[1], "");
620 }
621
622 static void pk2h_fetch_args(struct lp_build_tgsi_context *bld_base,
623 struct lp_build_emit_data *emit_data)
624 {
625 emit_data->args[0] = lp_build_emit_fetch(bld_base, emit_data->inst,
626 0, TGSI_CHAN_X);
627 emit_data->args[1] = lp_build_emit_fetch(bld_base, emit_data->inst,
628 0, TGSI_CHAN_Y);
629 }
630
631 static void emit_pk2h(const struct lp_build_tgsi_action *action,
632 struct lp_build_tgsi_context *bld_base,
633 struct lp_build_emit_data *emit_data)
634 {
635 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
636 LLVMContextRef context = bld_base->base.gallivm->context;
637 struct lp_build_context *uint_bld = &bld_base->uint_bld;
638 LLVMTypeRef fp16, i16;
639 LLVMValueRef const16, comp[2];
640 unsigned i;
641
642 fp16 = LLVMHalfTypeInContext(context);
643 i16 = LLVMInt16TypeInContext(context);
644 const16 = lp_build_const_int32(uint_bld->gallivm, 16);
645
646 for (i = 0; i < 2; i++) {
647 comp[i] = LLVMBuildFPTrunc(builder, emit_data->args[i], fp16, "");
648 comp[i] = LLVMBuildBitCast(builder, comp[i], i16, "");
649 comp[i] = LLVMBuildZExt(builder, comp[i], uint_bld->elem_type, "");
650 }
651
652 comp[1] = LLVMBuildShl(builder, comp[1], const16, "");
653 comp[0] = LLVMBuildOr(builder, comp[0], comp[1], "");
654
655 emit_data->output[emit_data->chan] = comp[0];
656 }
657
658 static void up2h_fetch_args(struct lp_build_tgsi_context *bld_base,
659 struct lp_build_emit_data *emit_data)
660 {
661 emit_data->args[0] = lp_build_emit_fetch(bld_base, emit_data->inst,
662 0, TGSI_CHAN_X);
663 }
664
665 static void emit_up2h(const struct lp_build_tgsi_action *action,
666 struct lp_build_tgsi_context *bld_base,
667 struct lp_build_emit_data *emit_data)
668 {
669 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
670 LLVMContextRef context = bld_base->base.gallivm->context;
671 struct lp_build_context *uint_bld = &bld_base->uint_bld;
672 LLVMTypeRef fp16, i16;
673 LLVMValueRef const16, input, val;
674 unsigned i;
675
676 fp16 = LLVMHalfTypeInContext(context);
677 i16 = LLVMInt16TypeInContext(context);
678 const16 = lp_build_const_int32(uint_bld->gallivm, 16);
679 input = emit_data->args[0];
680
681 for (i = 0; i < 2; i++) {
682 val = i == 1 ? LLVMBuildLShr(builder, input, const16, "") : input;
683 val = LLVMBuildTrunc(builder, val, i16, "");
684 val = LLVMBuildBitCast(builder, val, fp16, "");
685 emit_data->output[i] =
686 LLVMBuildFPExt(builder, val, bld_base->base.elem_type, "");
687 }
688 }
689
690 static void emit_fdiv(const struct lp_build_tgsi_action *action,
691 struct lp_build_tgsi_context *bld_base,
692 struct lp_build_emit_data *emit_data)
693 {
694 struct si_shader_context *ctx = si_shader_context(bld_base);
695
696 emit_data->output[emit_data->chan] =
697 LLVMBuildFDiv(bld_base->base.gallivm->builder,
698 emit_data->args[0], emit_data->args[1], "");
699
700 /* Use v_rcp_f32 instead of precise division. */
701 if (HAVE_LLVM >= 0x0309 &&
702 !LLVMIsConstant(emit_data->output[emit_data->chan]))
703 LLVMSetMetadata(emit_data->output[emit_data->chan],
704 ctx->fpmath_md_kind, ctx->fpmath_md_2p5_ulp);
705 }
706
707 /* 1/sqrt is translated to rsq for f32 if fp32 denormals are not enabled in
708 * the target machine. f64 needs global unsafe math flags to get rsq. */
709 static void emit_rsq(const struct lp_build_tgsi_action *action,
710 struct lp_build_tgsi_context *bld_base,
711 struct lp_build_emit_data *emit_data)
712 {
713 LLVMValueRef sqrt =
714 lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_SQRT,
715 emit_data->args[0]);
716
717 emit_data->output[emit_data->chan] =
718 lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_DIV,
719 bld_base->base.one, sqrt);
720 }
721
722 void si_shader_context_init_alu(struct lp_build_tgsi_context *bld_base)
723 {
724 lp_set_default_actions(bld_base);
725
726 bld_base->op_actions[TGSI_OPCODE_AND].emit = emit_and;
727 bld_base->op_actions[TGSI_OPCODE_ARL].emit = emit_arl;
728 bld_base->op_actions[TGSI_OPCODE_BFI].emit = emit_bfi;
729 bld_base->op_actions[TGSI_OPCODE_BREV].emit = build_tgsi_intrinsic_nomem;
730 bld_base->op_actions[TGSI_OPCODE_BREV].intr_name =
731 HAVE_LLVM >= 0x0308 ? "llvm.bitreverse.i32" : "llvm.AMDGPU.brev";
732 bld_base->op_actions[TGSI_OPCODE_CEIL].emit = build_tgsi_intrinsic_nomem;
733 bld_base->op_actions[TGSI_OPCODE_CEIL].intr_name = "llvm.ceil.f32";
734 bld_base->op_actions[TGSI_OPCODE_CMP].emit = emit_cmp;
735 bld_base->op_actions[TGSI_OPCODE_COS].emit = build_tgsi_intrinsic_nomem;
736 bld_base->op_actions[TGSI_OPCODE_COS].intr_name = "llvm.cos.f32";
737 bld_base->op_actions[TGSI_OPCODE_DABS].emit = build_tgsi_intrinsic_nomem;
738 bld_base->op_actions[TGSI_OPCODE_DABS].intr_name = "llvm.fabs.f64";
739 bld_base->op_actions[TGSI_OPCODE_DFMA].emit = build_tgsi_intrinsic_nomem;
740 bld_base->op_actions[TGSI_OPCODE_DFMA].intr_name = "llvm.fma.f64";
741 bld_base->op_actions[TGSI_OPCODE_DFRAC].emit = emit_frac;
742 bld_base->op_actions[TGSI_OPCODE_DIV].emit = emit_fdiv;
743 bld_base->op_actions[TGSI_OPCODE_DNEG].emit = emit_dneg;
744 bld_base->op_actions[TGSI_OPCODE_DSEQ].emit = emit_dcmp;
745 bld_base->op_actions[TGSI_OPCODE_DSGE].emit = emit_dcmp;
746 bld_base->op_actions[TGSI_OPCODE_DSLT].emit = emit_dcmp;
747 bld_base->op_actions[TGSI_OPCODE_DSNE].emit = emit_dcmp;
748 bld_base->op_actions[TGSI_OPCODE_DRSQ].emit = build_tgsi_intrinsic_nomem;
749 bld_base->op_actions[TGSI_OPCODE_DRSQ].intr_name =
750 HAVE_LLVM >= 0x0309 ? "llvm.amdgcn.rsq.f64" : "llvm.AMDGPU.rsq.f64";
751 bld_base->op_actions[TGSI_OPCODE_DSQRT].emit = build_tgsi_intrinsic_nomem;
752 bld_base->op_actions[TGSI_OPCODE_DSQRT].intr_name = "llvm.sqrt.f64";
753 bld_base->op_actions[TGSI_OPCODE_EX2].emit = build_tgsi_intrinsic_nomem;
754 bld_base->op_actions[TGSI_OPCODE_EX2].intr_name =
755 HAVE_LLVM >= 0x0308 ? "llvm.exp2.f32" : "llvm.AMDIL.exp.";
756 bld_base->op_actions[TGSI_OPCODE_FLR].emit = build_tgsi_intrinsic_nomem;
757 bld_base->op_actions[TGSI_OPCODE_FLR].intr_name = "llvm.floor.f32";
758 bld_base->op_actions[TGSI_OPCODE_FMA].emit =
759 bld_base->op_actions[TGSI_OPCODE_MAD].emit;
760 bld_base->op_actions[TGSI_OPCODE_FRC].emit = emit_frac;
761 bld_base->op_actions[TGSI_OPCODE_F2I].emit = emit_f2i;
762 bld_base->op_actions[TGSI_OPCODE_F2U].emit = emit_f2u;
763 bld_base->op_actions[TGSI_OPCODE_FSEQ].emit = emit_fcmp;
764 bld_base->op_actions[TGSI_OPCODE_FSGE].emit = emit_fcmp;
765 bld_base->op_actions[TGSI_OPCODE_FSLT].emit = emit_fcmp;
766 bld_base->op_actions[TGSI_OPCODE_FSNE].emit = emit_fcmp;
767 bld_base->op_actions[TGSI_OPCODE_IABS].emit = emit_iabs;
768 bld_base->op_actions[TGSI_OPCODE_IBFE].emit = emit_bfe;
769 bld_base->op_actions[TGSI_OPCODE_IBFE].intr_name = "llvm.AMDGPU.bfe.i32";
770 bld_base->op_actions[TGSI_OPCODE_IDIV].emit = emit_idiv;
771 bld_base->op_actions[TGSI_OPCODE_IMAX].emit = emit_minmax_int;
772 bld_base->op_actions[TGSI_OPCODE_IMIN].emit = emit_minmax_int;
773 bld_base->op_actions[TGSI_OPCODE_IMSB].emit = emit_imsb;
774 bld_base->op_actions[TGSI_OPCODE_INEG].emit = emit_ineg;
775 bld_base->op_actions[TGSI_OPCODE_ISHR].emit = emit_ishr;
776 bld_base->op_actions[TGSI_OPCODE_ISGE].emit = emit_icmp;
777 bld_base->op_actions[TGSI_OPCODE_ISLT].emit = emit_icmp;
778 bld_base->op_actions[TGSI_OPCODE_ISSG].emit = emit_ssg;
779 bld_base->op_actions[TGSI_OPCODE_I2F].emit = emit_i2f;
780 bld_base->op_actions[TGSI_OPCODE_KILL_IF].fetch_args = kill_if_fetch_args;
781 bld_base->op_actions[TGSI_OPCODE_KILL_IF].emit = kil_emit;
782 bld_base->op_actions[TGSI_OPCODE_KILL_IF].intr_name = "llvm.AMDGPU.kill";
783 bld_base->op_actions[TGSI_OPCODE_KILL].emit = lp_build_tgsi_intrinsic;
784 bld_base->op_actions[TGSI_OPCODE_KILL].intr_name = "llvm.AMDGPU.kilp";
785 bld_base->op_actions[TGSI_OPCODE_LSB].emit = emit_lsb;
786 bld_base->op_actions[TGSI_OPCODE_LG2].emit = build_tgsi_intrinsic_nomem;
787 bld_base->op_actions[TGSI_OPCODE_LG2].intr_name = "llvm.log2.f32";
788 bld_base->op_actions[TGSI_OPCODE_MAX].emit = build_tgsi_intrinsic_nomem;
789 bld_base->op_actions[TGSI_OPCODE_MAX].intr_name = "llvm.maxnum.f32";
790 bld_base->op_actions[TGSI_OPCODE_MIN].emit = build_tgsi_intrinsic_nomem;
791 bld_base->op_actions[TGSI_OPCODE_MIN].intr_name = "llvm.minnum.f32";
792 bld_base->op_actions[TGSI_OPCODE_MOD].emit = emit_mod;
793 bld_base->op_actions[TGSI_OPCODE_UMSB].emit = emit_umsb;
794 bld_base->op_actions[TGSI_OPCODE_NOT].emit = emit_not;
795 bld_base->op_actions[TGSI_OPCODE_OR].emit = emit_or;
796 bld_base->op_actions[TGSI_OPCODE_PK2H].fetch_args = pk2h_fetch_args;
797 bld_base->op_actions[TGSI_OPCODE_PK2H].emit = emit_pk2h;
798 bld_base->op_actions[TGSI_OPCODE_POPC].emit = build_tgsi_intrinsic_nomem;
799 bld_base->op_actions[TGSI_OPCODE_POPC].intr_name = "llvm.ctpop.i32";
800 bld_base->op_actions[TGSI_OPCODE_POW].emit = build_tgsi_intrinsic_nomem;
801 bld_base->op_actions[TGSI_OPCODE_POW].intr_name = "llvm.pow.f32";
802 bld_base->op_actions[TGSI_OPCODE_ROUND].emit = build_tgsi_intrinsic_nomem;
803 bld_base->op_actions[TGSI_OPCODE_ROUND].intr_name = "llvm.rint.f32";
804 bld_base->op_actions[TGSI_OPCODE_RSQ].emit = emit_rsq;
805 bld_base->op_actions[TGSI_OPCODE_SGE].emit = emit_set_cond;
806 bld_base->op_actions[TGSI_OPCODE_SEQ].emit = emit_set_cond;
807 bld_base->op_actions[TGSI_OPCODE_SHL].emit = emit_shl;
808 bld_base->op_actions[TGSI_OPCODE_SLE].emit = emit_set_cond;
809 bld_base->op_actions[TGSI_OPCODE_SLT].emit = emit_set_cond;
810 bld_base->op_actions[TGSI_OPCODE_SNE].emit = emit_set_cond;
811 bld_base->op_actions[TGSI_OPCODE_SGT].emit = emit_set_cond;
812 bld_base->op_actions[TGSI_OPCODE_SIN].emit = build_tgsi_intrinsic_nomem;
813 bld_base->op_actions[TGSI_OPCODE_SIN].intr_name = "llvm.sin.f32";
814 bld_base->op_actions[TGSI_OPCODE_SQRT].emit = build_tgsi_intrinsic_nomem;
815 bld_base->op_actions[TGSI_OPCODE_SQRT].intr_name = "llvm.sqrt.f32";
816 bld_base->op_actions[TGSI_OPCODE_SSG].emit = emit_ssg;
817 bld_base->op_actions[TGSI_OPCODE_TRUNC].emit = build_tgsi_intrinsic_nomem;
818 bld_base->op_actions[TGSI_OPCODE_TRUNC].intr_name = "llvm.trunc.f32";
819 bld_base->op_actions[TGSI_OPCODE_UADD].emit = emit_uadd;
820 bld_base->op_actions[TGSI_OPCODE_UBFE].emit = emit_bfe;
821 bld_base->op_actions[TGSI_OPCODE_UBFE].intr_name = "llvm.AMDGPU.bfe.u32";
822 bld_base->op_actions[TGSI_OPCODE_UDIV].emit = emit_udiv;
823 bld_base->op_actions[TGSI_OPCODE_UMAX].emit = emit_minmax_int;
824 bld_base->op_actions[TGSI_OPCODE_UMIN].emit = emit_minmax_int;
825 bld_base->op_actions[TGSI_OPCODE_UMOD].emit = emit_umod;
826 bld_base->op_actions[TGSI_OPCODE_USEQ].emit = emit_icmp;
827 bld_base->op_actions[TGSI_OPCODE_USGE].emit = emit_icmp;
828 bld_base->op_actions[TGSI_OPCODE_USHR].emit = emit_ushr;
829 bld_base->op_actions[TGSI_OPCODE_USLT].emit = emit_icmp;
830 bld_base->op_actions[TGSI_OPCODE_USNE].emit = emit_icmp;
831 bld_base->op_actions[TGSI_OPCODE_U2F].emit = emit_u2f;
832 bld_base->op_actions[TGSI_OPCODE_XOR].emit = emit_xor;
833 bld_base->op_actions[TGSI_OPCODE_UCMP].emit = emit_ucmp;
834 bld_base->op_actions[TGSI_OPCODE_UP2H].fetch_args = up2h_fetch_args;
835 bld_base->op_actions[TGSI_OPCODE_UP2H].emit = emit_up2h;
836
837 bld_base->op_actions[TGSI_OPCODE_I64MAX].emit = emit_minmax_int;
838 bld_base->op_actions[TGSI_OPCODE_I64MIN].emit = emit_minmax_int;
839 bld_base->op_actions[TGSI_OPCODE_U64MAX].emit = emit_minmax_int;
840 bld_base->op_actions[TGSI_OPCODE_U64MIN].emit = emit_minmax_int;
841 bld_base->op_actions[TGSI_OPCODE_I64ABS].emit = emit_iabs;
842 bld_base->op_actions[TGSI_OPCODE_I64SSG].emit = emit_ssg;
843 bld_base->op_actions[TGSI_OPCODE_I64NEG].emit = emit_ineg;
844
845 bld_base->op_actions[TGSI_OPCODE_U64SEQ].emit = emit_icmp;
846 bld_base->op_actions[TGSI_OPCODE_U64SNE].emit = emit_icmp;
847 bld_base->op_actions[TGSI_OPCODE_U64SGE].emit = emit_icmp;
848 bld_base->op_actions[TGSI_OPCODE_U64SLT].emit = emit_icmp;
849 bld_base->op_actions[TGSI_OPCODE_I64SGE].emit = emit_icmp;
850 bld_base->op_actions[TGSI_OPCODE_I64SLT].emit = emit_icmp;
851
852 bld_base->op_actions[TGSI_OPCODE_U64ADD].emit = emit_uadd;
853 bld_base->op_actions[TGSI_OPCODE_U64SHL].emit = emit_shl;
854 bld_base->op_actions[TGSI_OPCODE_U64SHR].emit = emit_ushr;
855 bld_base->op_actions[TGSI_OPCODE_I64SHR].emit = emit_ishr;
856
857 bld_base->op_actions[TGSI_OPCODE_U64MOD].emit = emit_umod;
858 bld_base->op_actions[TGSI_OPCODE_I64MOD].emit = emit_mod;
859 bld_base->op_actions[TGSI_OPCODE_U64DIV].emit = emit_udiv;
860 bld_base->op_actions[TGSI_OPCODE_I64DIV].emit = emit_idiv;
861 }