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ac: set swizzled bit in cache policy as a hint not to merge loads/stores
[mesa.git] / src / gallium / drivers / radeonsi / si_shader_tgsi_mem.c
1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include <llvm/Config/llvm-config.h>
26
27 #include "si_shader_internal.h"
28 #include "si_pipe.h"
29 #include "sid.h"
30 #include "tgsi/tgsi_build.h"
31 #include "tgsi/tgsi_util.h"
32 #include "ac_llvm_util.h"
33
34 static void tex_fetch_ptrs(struct lp_build_tgsi_context *bld_base,
35 struct lp_build_emit_data *emit_data,
36 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
37 LLVMValueRef *fmask_ptr);
38
39 /**
40 * Given a v8i32 resource descriptor for a buffer, extract the size of the
41 * buffer in number of elements and return it as an i32.
42 */
43 static LLVMValueRef get_buffer_size(
44 struct lp_build_tgsi_context *bld_base,
45 LLVMValueRef descriptor)
46 {
47 struct si_shader_context *ctx = si_shader_context(bld_base);
48 LLVMBuilderRef builder = ctx->ac.builder;
49 LLVMValueRef size =
50 LLVMBuildExtractElement(builder, descriptor,
51 LLVMConstInt(ctx->i32, 2, 0), "");
52
53 if (ctx->screen->info.chip_class == GFX8) {
54 /* On GFX8, the descriptor contains the size in bytes,
55 * but TXQ must return the size in elements.
56 * The stride is always non-zero for resources using TXQ.
57 */
58 LLVMValueRef stride =
59 LLVMBuildExtractElement(builder, descriptor,
60 ctx->i32_1, "");
61 stride = LLVMBuildLShr(builder, stride,
62 LLVMConstInt(ctx->i32, 16, 0), "");
63 stride = LLVMBuildAnd(builder, stride,
64 LLVMConstInt(ctx->i32, 0x3FFF, 0), "");
65
66 size = LLVMBuildUDiv(builder, size, stride, "");
67 }
68
69 return size;
70 }
71
72 static LLVMValueRef
73 shader_buffer_fetch_rsrc(struct si_shader_context *ctx,
74 const struct tgsi_full_src_register *reg,
75 bool ubo)
76 {
77 LLVMValueRef index;
78
79 if (!reg->Register.Indirect) {
80 index = LLVMConstInt(ctx->i32, reg->Register.Index, false);
81 } else {
82 index = si_get_indirect_index(ctx, &reg->Indirect,
83 1, reg->Register.Index);
84 }
85
86 if (ubo)
87 return ctx->abi.load_ubo(&ctx->abi, index);
88 else
89 return ctx->abi.load_ssbo(&ctx->abi, index, false);
90 }
91
92 static enum ac_image_dim
93 ac_texture_dim_from_tgsi_target(struct si_screen *screen, enum tgsi_texture_type target)
94 {
95 switch (target) {
96 case TGSI_TEXTURE_1D:
97 case TGSI_TEXTURE_SHADOW1D:
98 if (screen->info.chip_class == GFX9)
99 return ac_image_2d;
100 return ac_image_1d;
101 case TGSI_TEXTURE_2D:
102 case TGSI_TEXTURE_SHADOW2D:
103 case TGSI_TEXTURE_RECT:
104 case TGSI_TEXTURE_SHADOWRECT:
105 return ac_image_2d;
106 case TGSI_TEXTURE_3D:
107 return ac_image_3d;
108 case TGSI_TEXTURE_CUBE:
109 case TGSI_TEXTURE_SHADOWCUBE:
110 case TGSI_TEXTURE_CUBE_ARRAY:
111 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
112 return ac_image_cube;
113 case TGSI_TEXTURE_1D_ARRAY:
114 case TGSI_TEXTURE_SHADOW1D_ARRAY:
115 if (screen->info.chip_class == GFX9)
116 return ac_image_2darray;
117 return ac_image_1darray;
118 case TGSI_TEXTURE_2D_ARRAY:
119 case TGSI_TEXTURE_SHADOW2D_ARRAY:
120 return ac_image_2darray;
121 case TGSI_TEXTURE_2D_MSAA:
122 return ac_image_2dmsaa;
123 case TGSI_TEXTURE_2D_ARRAY_MSAA:
124 return ac_image_2darraymsaa;
125 default:
126 unreachable("unhandled texture type");
127 }
128 }
129
130 static enum ac_image_dim
131 ac_image_dim_from_tgsi_target(struct si_screen *screen, enum tgsi_texture_type target)
132 {
133 enum ac_image_dim dim = ac_texture_dim_from_tgsi_target(screen, target);
134
135 /* Match the resource type set in the descriptor. */
136 if (dim == ac_image_cube ||
137 (screen->info.chip_class <= GFX8 && dim == ac_image_3d))
138 dim = ac_image_2darray;
139 else if (target == TGSI_TEXTURE_2D && screen->info.chip_class == GFX9) {
140 /* When a single layer of a 3D texture is bound, the shader
141 * will refer to a 2D target, but the descriptor has a 3D type.
142 * Since the HW ignores BASE_ARRAY in this case, we need to
143 * send 3 coordinates. This doesn't hurt when the underlying
144 * texture is non-3D.
145 */
146 dim = ac_image_3d;
147 }
148
149 return dim;
150 }
151
152 /**
153 * Given a 256-bit resource descriptor, force the DCC enable bit to off.
154 *
155 * At least on Tonga, executing image stores on images with DCC enabled and
156 * non-trivial can eventually lead to lockups. This can occur when an
157 * application binds an image as read-only but then uses a shader that writes
158 * to it. The OpenGL spec allows almost arbitrarily bad behavior (including
159 * program termination) in this case, but it doesn't cost much to be a bit
160 * nicer: disabling DCC in the shader still leads to undefined results but
161 * avoids the lockup.
162 */
163 static LLVMValueRef force_dcc_off(struct si_shader_context *ctx,
164 LLVMValueRef rsrc)
165 {
166 if (ctx->screen->info.chip_class <= GFX7) {
167 return rsrc;
168 } else {
169 LLVMValueRef i32_6 = LLVMConstInt(ctx->i32, 6, 0);
170 LLVMValueRef i32_C = LLVMConstInt(ctx->i32, C_008F28_COMPRESSION_EN, 0);
171 LLVMValueRef tmp;
172
173 tmp = LLVMBuildExtractElement(ctx->ac.builder, rsrc, i32_6, "");
174 tmp = LLVMBuildAnd(ctx->ac.builder, tmp, i32_C, "");
175 return LLVMBuildInsertElement(ctx->ac.builder, rsrc, tmp, i32_6, "");
176 }
177 }
178
179 /* AC_DESC_FMASK is handled exactly like AC_DESC_IMAGE. The caller should
180 * adjust "index" to point to FMASK. */
181 LLVMValueRef si_load_image_desc(struct si_shader_context *ctx,
182 LLVMValueRef list, LLVMValueRef index,
183 enum ac_descriptor_type desc_type,
184 bool uses_store, bool bindless)
185 {
186 LLVMBuilderRef builder = ctx->ac.builder;
187 LLVMValueRef rsrc;
188
189 if (desc_type == AC_DESC_BUFFER) {
190 index = ac_build_imad(&ctx->ac, index, LLVMConstInt(ctx->i32, 2, 0),
191 ctx->i32_1);
192 list = LLVMBuildPointerCast(builder, list,
193 ac_array_in_const32_addr_space(ctx->v4i32), "");
194 } else {
195 assert(desc_type == AC_DESC_IMAGE ||
196 desc_type == AC_DESC_FMASK);
197 }
198
199 if (bindless)
200 rsrc = ac_build_load_to_sgpr_uint_wraparound(&ctx->ac, list, index);
201 else
202 rsrc = ac_build_load_to_sgpr(&ctx->ac, list, index);
203
204 if (desc_type == AC_DESC_IMAGE && uses_store)
205 rsrc = force_dcc_off(ctx, rsrc);
206 return rsrc;
207 }
208
209 /**
210 * Load the resource descriptor for \p image.
211 */
212 static void
213 image_fetch_rsrc(
214 struct lp_build_tgsi_context *bld_base,
215 const struct tgsi_full_src_register *image,
216 bool fmask, bool is_store, unsigned target,
217 LLVMValueRef *rsrc)
218 {
219 struct si_shader_context *ctx = si_shader_context(bld_base);
220 bool bindless = image->Register.File != TGSI_FILE_IMAGE;
221 LLVMValueRef rsrc_ptr, index;
222
223 if (bindless) {
224 /* Bindless descriptors are accessible from a different pair of
225 * user SGPR indices.
226 */
227 rsrc_ptr = ac_get_arg(&ctx->ac,
228 ctx->bindless_samplers_and_images);
229 index = lp_build_emit_fetch_src(bld_base, image, TGSI_TYPE_UNSIGNED, 0);
230
231 /* Bindless image descriptors use 16-dword slots. */
232 index = LLVMBuildMul(ctx->ac.builder, index,
233 LLVMConstInt(ctx->i32, 2, 0), "");
234 /* FMASK is right after the image. */
235 if (fmask)
236 index = LLVMBuildAdd(ctx->ac.builder, index, ctx->i32_1, "");
237 } else {
238 rsrc_ptr = ac_get_arg(&ctx->ac, ctx->samplers_and_images);
239
240 if (!image->Register.Indirect) {
241 index = LLVMConstInt(ctx->i32, image->Register.Index, 0);
242 } else {
243 /* From the GL_ARB_shader_image_load_store extension spec:
244 *
245 * If a shader performs an image load, store, or atomic
246 * operation using an image variable declared as an array,
247 * and if the index used to select an individual element is
248 * negative or greater than or equal to the size of the
249 * array, the results of the operation are undefined but may
250 * not lead to termination.
251 */
252 index = si_get_bounded_indirect_index(ctx, &image->Indirect,
253 image->Register.Index,
254 ctx->num_images);
255 }
256 /* FMASKs are separate from images. */
257 if (fmask) {
258 index = LLVMBuildAdd(ctx->ac.builder, index,
259 LLVMConstInt(ctx->i32, SI_NUM_IMAGES, 0), "");
260 }
261 index = LLVMBuildSub(ctx->ac.builder,
262 LLVMConstInt(ctx->i32, SI_NUM_IMAGE_SLOTS - 1, 0),
263 index, "");
264 }
265
266 *rsrc = si_load_image_desc(ctx, rsrc_ptr, index,
267 fmask ? AC_DESC_FMASK :
268 target == TGSI_TEXTURE_BUFFER ? AC_DESC_BUFFER : AC_DESC_IMAGE,
269 is_store, bindless);
270 }
271
272 static void image_fetch_coords(
273 struct lp_build_tgsi_context *bld_base,
274 const struct tgsi_full_instruction *inst,
275 unsigned src, LLVMValueRef desc,
276 LLVMValueRef *coords)
277 {
278 struct si_shader_context *ctx = si_shader_context(bld_base);
279 LLVMBuilderRef builder = ctx->ac.builder;
280 unsigned target = inst->Memory.Texture;
281 unsigned num_coords = tgsi_util_get_texture_coord_dim(target);
282 LLVMValueRef tmp;
283 int chan;
284
285 for (chan = 0; chan < num_coords; ++chan) {
286 tmp = lp_build_emit_fetch(bld_base, inst, src, chan);
287 tmp = ac_to_integer(&ctx->ac, tmp);
288 coords[chan] = tmp;
289 }
290
291 if (target == TGSI_TEXTURE_2D_MSAA ||
292 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
293 /* Need the sample index as well. */
294 tmp = lp_build_emit_fetch(bld_base, inst, src, TGSI_SWIZZLE_W);
295 coords[chan] = ac_to_integer(&ctx->ac, tmp);
296 }
297
298 if (ctx->screen->info.chip_class == GFX9) {
299 /* 1D textures are allocated and used as 2D on GFX9. */
300 if (target == TGSI_TEXTURE_1D) {
301 coords[1] = ctx->i32_0;
302 } else if (target == TGSI_TEXTURE_1D_ARRAY) {
303 coords[2] = coords[1];
304 coords[1] = ctx->i32_0;
305 } else if (target == TGSI_TEXTURE_2D) {
306 /* The hw can't bind a slice of a 3D image as a 2D
307 * image, because it ignores BASE_ARRAY if the target
308 * is 3D. The workaround is to read BASE_ARRAY and set
309 * it as the 3rd address operand for all 2D images.
310 */
311 LLVMValueRef first_layer, const5, mask;
312
313 const5 = LLVMConstInt(ctx->i32, 5, 0);
314 mask = LLVMConstInt(ctx->i32, S_008F24_BASE_ARRAY(~0), 0);
315 first_layer = LLVMBuildExtractElement(builder, desc, const5, "");
316 first_layer = LLVMBuildAnd(builder, first_layer, mask, "");
317
318 coords[2] = first_layer;
319 }
320 }
321 }
322
323 static unsigned get_cache_policy(struct si_shader_context *ctx,
324 const struct tgsi_full_instruction *inst,
325 bool atomic, bool may_store_unaligned,
326 bool writeonly_memory)
327 {
328 unsigned cache_policy = 0;
329
330 if (!atomic &&
331 /* GFX6 has a TC L1 bug causing corruption of 8bit/16bit stores.
332 * All store opcodes not aligned to a dword are affected.
333 * The only way to get unaligned stores in radeonsi is through
334 * shader images. */
335 ((may_store_unaligned && ctx->screen->info.chip_class == GFX6) ||
336 /* If this is write-only, don't keep data in L1 to prevent
337 * evicting L1 cache lines that may be needed by other
338 * instructions. */
339 writeonly_memory ||
340 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE))) {
341 cache_policy |= ac_glc;
342 }
343
344 if (inst->Memory.Qualifier & TGSI_MEMORY_STREAM_CACHE_POLICY)
345 cache_policy |= ac_slc;
346
347 return cache_policy;
348 }
349
350 static LLVMValueRef get_memory_ptr(struct si_shader_context *ctx,
351 const struct tgsi_full_instruction *inst,
352 LLVMTypeRef type, int arg)
353 {
354 LLVMBuilderRef builder = ctx->ac.builder;
355 LLVMValueRef offset, ptr;
356 int addr_space;
357
358 offset = lp_build_emit_fetch(&ctx->bld_base, inst, arg, 0);
359 offset = ac_to_integer(&ctx->ac, offset);
360
361 ptr = ctx->ac.lds;
362 ptr = LLVMBuildGEP(builder, ptr, &offset, 1, "");
363 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
364 ptr = LLVMBuildBitCast(builder, ptr, LLVMPointerType(type, addr_space), "");
365
366 return ptr;
367 }
368
369 static void load_emit_memory(
370 struct si_shader_context *ctx,
371 struct lp_build_emit_data *emit_data)
372 {
373 const struct tgsi_full_instruction *inst = emit_data->inst;
374 unsigned writemask = inst->Dst[0].Register.WriteMask;
375 LLVMValueRef channels[4], ptr, derived_ptr, index;
376 int chan;
377
378 ptr = get_memory_ptr(ctx, inst, ctx->f32, 1);
379
380 for (chan = 0; chan < 4; ++chan) {
381 if (!(writemask & (1 << chan))) {
382 channels[chan] = LLVMGetUndef(ctx->f32);
383 continue;
384 }
385
386 index = LLVMConstInt(ctx->i32, chan, 0);
387 derived_ptr = LLVMBuildGEP(ctx->ac.builder, ptr, &index, 1, "");
388 channels[chan] = LLVMBuildLoad(ctx->ac.builder, derived_ptr, "");
389 }
390 emit_data->output[emit_data->chan] = ac_build_gather_values(&ctx->ac, channels, 4);
391 }
392
393 /**
394 * Return true if the memory accessed by a LOAD or STORE instruction is
395 * read-only or write-only, respectively.
396 *
397 * \param shader_buffers_reverse_access_mask
398 * For LOAD, set this to (store | atomic) slot usage in the shader.
399 * For STORE, set this to (load | atomic) slot usage in the shader.
400 * \param images_reverse_access_mask Same as above, but for images.
401 * \param bindless_buffer_reverse_access_mask Same as above, but for bindless image buffers.
402 * \param bindless_image_reverse_access_mask Same as above, but for bindless images.
403 */
404 static bool is_oneway_access_only(const struct tgsi_full_instruction *inst,
405 const struct tgsi_shader_info *info,
406 unsigned shader_buffers_reverse_access_mask,
407 unsigned images_reverse_access_mask,
408 bool bindless_buffer_reverse_access_mask,
409 bool bindless_image_reverse_access_mask)
410 {
411 enum tgsi_file_type resource_file;
412 unsigned resource_index;
413 bool resource_indirect;
414
415 if (inst->Instruction.Opcode == TGSI_OPCODE_STORE) {
416 resource_file = inst->Dst[0].Register.File;
417 resource_index = inst->Dst[0].Register.Index;
418 resource_indirect = inst->Dst[0].Register.Indirect;
419 } else {
420 resource_file = inst->Src[0].Register.File;
421 resource_index = inst->Src[0].Register.Index;
422 resource_indirect = inst->Src[0].Register.Indirect;
423 }
424
425 assert(resource_file == TGSI_FILE_BUFFER ||
426 resource_file == TGSI_FILE_IMAGE ||
427 /* bindless image */
428 resource_file == TGSI_FILE_INPUT ||
429 resource_file == TGSI_FILE_OUTPUT ||
430 resource_file == TGSI_FILE_CONSTANT ||
431 resource_file == TGSI_FILE_TEMPORARY ||
432 resource_file == TGSI_FILE_IMMEDIATE);
433
434 assert(resource_file != TGSI_FILE_BUFFER ||
435 inst->Memory.Texture == TGSI_TEXTURE_BUFFER);
436
437 bool bindless = resource_file != TGSI_FILE_BUFFER &&
438 resource_file != TGSI_FILE_IMAGE;
439
440 /* RESTRICT means NOALIAS.
441 * If there are no writes, we can assume the accessed memory is read-only.
442 * If there are no reads, we can assume the accessed memory is write-only.
443 */
444 if (inst->Memory.Qualifier & TGSI_MEMORY_RESTRICT && !bindless) {
445 unsigned reverse_access_mask;
446
447 if (resource_file == TGSI_FILE_BUFFER) {
448 reverse_access_mask = shader_buffers_reverse_access_mask;
449 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
450 reverse_access_mask = info->images_buffers &
451 images_reverse_access_mask;
452 } else {
453 reverse_access_mask = ~info->images_buffers &
454 images_reverse_access_mask;
455 }
456
457 if (resource_indirect) {
458 if (!reverse_access_mask)
459 return true;
460 } else {
461 if (!(reverse_access_mask &
462 (1u << resource_index)))
463 return true;
464 }
465 }
466
467 /* If there are no buffer writes (for both shader buffers & image
468 * buffers), it implies that buffer memory is read-only.
469 * If there are no buffer reads (for both shader buffers & image
470 * buffers), it implies that buffer memory is write-only.
471 *
472 * Same for the case when there are no writes/reads for non-buffer
473 * images.
474 */
475 if (resource_file == TGSI_FILE_BUFFER ||
476 inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
477 if (!shader_buffers_reverse_access_mask &&
478 !(info->images_buffers & images_reverse_access_mask) &&
479 !bindless_buffer_reverse_access_mask)
480 return true;
481 } else {
482 if (!(~info->images_buffers & images_reverse_access_mask) &&
483 !bindless_image_reverse_access_mask)
484 return true;
485 }
486 return false;
487 }
488
489 static void load_emit(
490 const struct lp_build_tgsi_action *action,
491 struct lp_build_tgsi_context *bld_base,
492 struct lp_build_emit_data *emit_data)
493 {
494 struct si_shader_context *ctx = si_shader_context(bld_base);
495 const struct tgsi_full_instruction * inst = emit_data->inst;
496 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
497 bool can_speculate = false;
498 LLVMValueRef vindex = ctx->i32_0;
499 LLVMValueRef voffset = ctx->i32_0;
500 struct ac_image_args args = {};
501
502 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
503 load_emit_memory(ctx, emit_data);
504 return;
505 }
506
507 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
508 inst->Src[0].Register.File == TGSI_FILE_CONSTBUF) {
509 bool ubo = inst->Src[0].Register.File == TGSI_FILE_CONSTBUF;
510 args.resource = shader_buffer_fetch_rsrc(ctx, &inst->Src[0], ubo);
511 voffset = ac_to_integer(&ctx->ac, lp_build_emit_fetch(bld_base, inst, 1, 0));
512 } else {
513 unsigned target = inst->Memory.Texture;
514
515 image_fetch_rsrc(bld_base, &inst->Src[0], false, false, target, &args.resource);
516 image_fetch_coords(bld_base, inst, 1, args.resource, args.coords);
517
518 if ((inst->Memory.Texture == TGSI_TEXTURE_2D_MSAA ||
519 inst->Memory.Texture == TGSI_TEXTURE_2D_ARRAY_MSAA) &&
520 !(ctx->screen->debug_flags & DBG(NO_FMASK))) {
521 LLVMValueRef fmask;
522
523 image_fetch_rsrc(bld_base, &inst->Src[0], true, false, target, &fmask);
524 ac_apply_fmask_to_sample(&ctx->ac, fmask, args.coords,
525 inst->Memory.Texture == TGSI_TEXTURE_2D_ARRAY_MSAA);
526 }
527 vindex = args.coords[0]; /* for buffers only */
528 }
529
530 if (inst->Src[0].Register.File == TGSI_FILE_CONSTBUF) {
531 emit_data->output[emit_data->chan] =
532 ac_build_buffer_load(&ctx->ac, args.resource,
533 util_last_bit(inst->Dst[0].Register.WriteMask),
534 NULL, voffset, NULL, 0, 0, true, true);
535 return;
536 }
537
538 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
539 ac_build_waitcnt(&ctx->ac, AC_WAIT_VLOAD | AC_WAIT_VSTORE);
540
541 can_speculate = !(inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE) &&
542 is_oneway_access_only(inst, info,
543 info->shader_buffers_store |
544 info->shader_buffers_atomic,
545 info->images_store |
546 info->images_atomic,
547 info->uses_bindless_buffer_store |
548 info->uses_bindless_buffer_atomic,
549 info->uses_bindless_image_store |
550 info->uses_bindless_image_atomic);
551 args.cache_policy = get_cache_policy(ctx, inst, false, false, false);
552
553 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
554 /* Don't use SMEM for shader buffer loads, because LLVM doesn't
555 * select SMEM for SI.load.const with a non-constant offset, and
556 * constant offsets practically don't exist with shader buffers.
557 *
558 * Also, SI.load.const doesn't use inst_offset when it's lowered
559 * to VMEM, so we just end up with more VALU instructions in the end
560 * and no benefit.
561 *
562 * TODO: Remove this line once LLVM can select SMEM with a non-constant
563 * offset, and can derive inst_offset when VMEM is selected.
564 * After that, si_memory_barrier should invalidate sL1 for shader
565 * buffers.
566 */
567 emit_data->output[emit_data->chan] =
568 ac_build_buffer_load(&ctx->ac, args.resource,
569 util_last_bit(inst->Dst[0].Register.WriteMask),
570 NULL, voffset, NULL, 0,
571 args.cache_policy, can_speculate, false);
572 return;
573 }
574
575 if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
576 unsigned num_channels = util_last_bit(inst->Dst[0].Register.WriteMask);
577 LLVMValueRef result =
578 ac_build_buffer_load_format(&ctx->ac,
579 args.resource,
580 vindex,
581 ctx->i32_0,
582 num_channels,
583 args.cache_policy,
584 can_speculate);
585 emit_data->output[emit_data->chan] =
586 ac_build_expand_to_vec4(&ctx->ac, result, num_channels);
587 } else {
588 args.opcode = ac_image_load;
589 args.dim = ac_image_dim_from_tgsi_target(ctx->screen, inst->Memory.Texture);
590 args.attributes = ac_get_load_intr_attribs(can_speculate);
591 args.dmask = 0xf;
592
593 emit_data->output[emit_data->chan] =
594 ac_build_image_opcode(&ctx->ac, &args);
595 }
596 }
597
598 static void store_emit_buffer(struct si_shader_context *ctx,
599 LLVMValueRef resource,
600 unsigned writemask,
601 LLVMValueRef value,
602 LLVMValueRef voffset,
603 unsigned cache_policy,
604 bool writeonly_memory)
605 {
606 LLVMBuilderRef builder = ctx->ac.builder;
607 LLVMValueRef base_data = value;
608 LLVMValueRef base_offset = voffset;
609
610 while (writemask) {
611 int start, count;
612 LLVMValueRef data, voff;
613
614 u_bit_scan_consecutive_range(&writemask, &start, &count);
615
616 if (count == 3 && ac_has_vec3_support(ctx->ac.chip_class, false)) {
617 LLVMValueRef values[3] = {
618 LLVMBuildExtractElement(builder, base_data,
619 LLVMConstInt(ctx->i32, start, 0), ""),
620 LLVMBuildExtractElement(builder, base_data,
621 LLVMConstInt(ctx->i32, start + 1, 0), ""),
622 LLVMBuildExtractElement(builder, base_data,
623 LLVMConstInt(ctx->i32, start + 2, 0), ""),
624 };
625 data = ac_build_gather_values(&ctx->ac, values, 3);
626 } else if (count >= 3) {
627 data = base_data;
628 } else if (count == 2) {
629 LLVMValueRef values[2] = {
630 LLVMBuildExtractElement(builder, base_data,
631 LLVMConstInt(ctx->i32, start, 0), ""),
632 LLVMBuildExtractElement(builder, base_data,
633 LLVMConstInt(ctx->i32, start + 1, 0), ""),
634 };
635
636 data = ac_build_gather_values(&ctx->ac, values, 2);
637 } else {
638 assert(count == 1);
639 data = LLVMBuildExtractElement(
640 builder, base_data,
641 LLVMConstInt(ctx->i32, start, 0), "");
642 }
643
644 voff = base_offset;
645 if (start != 0) {
646 voff = LLVMBuildAdd(
647 builder, voff,
648 LLVMConstInt(ctx->i32, start * 4, 0), "");
649 }
650
651 ac_build_buffer_store_dword(&ctx->ac, resource, data, count,
652 voff, ctx->i32_0, 0, cache_policy);
653 }
654 }
655
656 static void store_emit_memory(
657 struct si_shader_context *ctx,
658 struct lp_build_emit_data *emit_data)
659 {
660 const struct tgsi_full_instruction *inst = emit_data->inst;
661 LLVMBuilderRef builder = ctx->ac.builder;
662 unsigned writemask = inst->Dst[0].Register.WriteMask;
663 LLVMValueRef ptr, derived_ptr, data, index;
664 int chan;
665
666 ptr = get_memory_ptr(ctx, inst, ctx->f32, 0);
667
668 for (chan = 0; chan < 4; ++chan) {
669 if (!(writemask & (1 << chan))) {
670 continue;
671 }
672 data = lp_build_emit_fetch(&ctx->bld_base, inst, 1, chan);
673 index = LLVMConstInt(ctx->i32, chan, 0);
674 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
675 LLVMBuildStore(builder, data, derived_ptr);
676 }
677 }
678
679 static void store_emit(
680 const struct lp_build_tgsi_action *action,
681 struct lp_build_tgsi_context *bld_base,
682 struct lp_build_emit_data *emit_data)
683 {
684 struct si_shader_context *ctx = si_shader_context(bld_base);
685 const struct tgsi_full_instruction * inst = emit_data->inst;
686 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
687 struct tgsi_full_src_register resource_reg =
688 tgsi_full_src_register_from_dst(&inst->Dst[0]);
689 unsigned target = inst->Memory.Texture;
690
691 if (inst->Dst[0].Register.File == TGSI_FILE_MEMORY) {
692 store_emit_memory(ctx, emit_data);
693 return;
694 }
695
696 bool writeonly_memory = is_oneway_access_only(inst, info,
697 info->shader_buffers_load |
698 info->shader_buffers_atomic,
699 info->images_load |
700 info->images_atomic,
701 info->uses_bindless_buffer_load |
702 info->uses_bindless_buffer_atomic,
703 info->uses_bindless_image_load |
704 info->uses_bindless_image_atomic);
705 LLVMValueRef chans[4];
706 LLVMValueRef vindex = ctx->i32_0;
707 LLVMValueRef voffset = ctx->i32_0;
708 struct ac_image_args args = {};
709
710 for (unsigned chan = 0; chan < 4; ++chan)
711 chans[chan] = lp_build_emit_fetch(bld_base, inst, 1, chan);
712
713 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
714 args.resource = shader_buffer_fetch_rsrc(ctx, &resource_reg, false);
715 voffset = ac_to_integer(&ctx->ac, lp_build_emit_fetch(bld_base, inst, 0, 0));
716 } else {
717 image_fetch_rsrc(bld_base, &resource_reg, false, true, target, &args.resource);
718 image_fetch_coords(bld_base, inst, 0, args.resource, args.coords);
719 vindex = args.coords[0]; /* for buffers only */
720 }
721
722 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
723 ac_build_waitcnt(&ctx->ac, AC_WAIT_VLOAD | AC_WAIT_VSTORE);
724
725 bool is_image = inst->Dst[0].Register.File != TGSI_FILE_BUFFER;
726 args.cache_policy = get_cache_policy(ctx, inst,
727 false, /* atomic */
728 is_image, /* may_store_unaligned */
729 writeonly_memory);
730
731 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
732 store_emit_buffer(ctx, args.resource, inst->Dst[0].Register.WriteMask,
733 ac_build_gather_values(&ctx->ac, chans, 4),
734 voffset, args.cache_policy, writeonly_memory);
735 return;
736 }
737
738 if (target == TGSI_TEXTURE_BUFFER) {
739 unsigned num_channels = util_last_bit(inst->Dst[0].Register.WriteMask);
740
741 ac_build_buffer_store_format(&ctx->ac, args.resource,
742 ac_build_gather_values(&ctx->ac, chans, num_channels),
743 vindex, ctx->i32_0 /* voffset */,
744 num_channels,
745 args.cache_policy);
746 } else {
747 args.opcode = ac_image_store;
748 args.data[0] = ac_build_gather_values(&ctx->ac, chans, 4);
749 args.dim = ac_image_dim_from_tgsi_target(ctx->screen, inst->Memory.Texture);
750 args.attributes = AC_FUNC_ATTR_INACCESSIBLE_MEM_ONLY;
751 args.dmask = 0xf;
752
753 emit_data->output[emit_data->chan] =
754 ac_build_image_opcode(&ctx->ac, &args);
755 }
756 }
757
758 static void atomic_emit_memory(struct si_shader_context *ctx,
759 struct lp_build_emit_data *emit_data) {
760 LLVMBuilderRef builder = ctx->ac.builder;
761 const struct tgsi_full_instruction * inst = emit_data->inst;
762 LLVMValueRef ptr, result, arg;
763 const char *sync_scope = LLVM_VERSION_MAJOR >= 9 ? "workgroup-one-as" : "workgroup";
764
765 ptr = get_memory_ptr(ctx, inst, ctx->i32, 1);
766
767 arg = lp_build_emit_fetch(&ctx->bld_base, inst, 2, 0);
768 arg = ac_to_integer(&ctx->ac, arg);
769
770 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
771 LLVMValueRef new_data;
772 new_data = lp_build_emit_fetch(&ctx->bld_base,
773 inst, 3, 0);
774
775 new_data = ac_to_integer(&ctx->ac, new_data);
776
777 result = ac_build_atomic_cmp_xchg(&ctx->ac, ptr, arg, new_data,
778 sync_scope);
779 result = LLVMBuildExtractValue(builder, result, 0, "");
780 } else {
781 LLVMAtomicRMWBinOp op;
782
783 switch(inst->Instruction.Opcode) {
784 case TGSI_OPCODE_ATOMUADD:
785 op = LLVMAtomicRMWBinOpAdd;
786 break;
787 case TGSI_OPCODE_ATOMXCHG:
788 op = LLVMAtomicRMWBinOpXchg;
789 break;
790 case TGSI_OPCODE_ATOMAND:
791 op = LLVMAtomicRMWBinOpAnd;
792 break;
793 case TGSI_OPCODE_ATOMOR:
794 op = LLVMAtomicRMWBinOpOr;
795 break;
796 case TGSI_OPCODE_ATOMXOR:
797 op = LLVMAtomicRMWBinOpXor;
798 break;
799 case TGSI_OPCODE_ATOMUMIN:
800 op = LLVMAtomicRMWBinOpUMin;
801 break;
802 case TGSI_OPCODE_ATOMUMAX:
803 op = LLVMAtomicRMWBinOpUMax;
804 break;
805 case TGSI_OPCODE_ATOMIMIN:
806 op = LLVMAtomicRMWBinOpMin;
807 break;
808 case TGSI_OPCODE_ATOMIMAX:
809 op = LLVMAtomicRMWBinOpMax;
810 break;
811 default:
812 unreachable("unknown atomic opcode");
813 }
814
815 result = ac_build_atomic_rmw(&ctx->ac, op, ptr, arg, sync_scope);
816 }
817 emit_data->output[emit_data->chan] =
818 LLVMBuildBitCast(builder, result, ctx->f32, "");
819 }
820
821 static void atomic_emit(
822 const struct lp_build_tgsi_action *action,
823 struct lp_build_tgsi_context *bld_base,
824 struct lp_build_emit_data *emit_data)
825 {
826 struct si_shader_context *ctx = si_shader_context(bld_base);
827 const struct tgsi_full_instruction * inst = emit_data->inst;
828 struct ac_image_args args = {};
829 unsigned num_data = 0;
830 LLVMValueRef vindex = ctx->i32_0;
831 LLVMValueRef voffset = ctx->i32_0;
832
833 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
834 atomic_emit_memory(ctx, emit_data);
835 return;
836 }
837
838 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
839 /* llvm.amdgcn.image/buffer.atomic.cmpswap reflect the hardware order
840 * of arguments, which is reversed relative to TGSI (and GLSL)
841 */
842 args.data[num_data++] =
843 ac_to_integer(&ctx->ac, lp_build_emit_fetch(bld_base, inst, 3, 0));
844 }
845
846 args.data[num_data++] =
847 ac_to_integer(&ctx->ac, lp_build_emit_fetch(bld_base, inst, 2, 0));
848
849 args.cache_policy = get_cache_policy(ctx, inst, true, false, false);
850
851 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
852 args.resource = shader_buffer_fetch_rsrc(ctx, &inst->Src[0], false);
853 voffset = ac_to_integer(&ctx->ac, lp_build_emit_fetch(bld_base, inst, 1, 0));
854 } else {
855 image_fetch_rsrc(bld_base, &inst->Src[0], false, true,
856 inst->Memory.Texture, &args.resource);
857 image_fetch_coords(bld_base, inst, 1, args.resource, args.coords);
858 vindex = args.coords[0]; /* for buffers only */
859 }
860
861 if (inst->Src[0].Register.File != TGSI_FILE_BUFFER &&
862 inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
863 LLVMValueRef buf_args[7];
864 unsigned num_args = 0;
865
866 buf_args[num_args++] = args.data[0];
867 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
868 buf_args[num_args++] = args.data[1];
869
870 buf_args[num_args++] = args.resource;
871 buf_args[num_args++] = vindex;
872 buf_args[num_args++] = voffset;
873 buf_args[num_args++] = ctx->i32_0; /* soffset */
874 buf_args[num_args++] = LLVMConstInt(ctx->i32, args.cache_policy & ac_slc, 0);
875
876 char intrinsic_name[64];
877 snprintf(intrinsic_name, sizeof(intrinsic_name),
878 "llvm.amdgcn.struct.buffer.atomic.%s", action->intr_name);
879 emit_data->output[emit_data->chan] =
880 ac_to_float(&ctx->ac,
881 ac_build_intrinsic(&ctx->ac, intrinsic_name,
882 ctx->i32, buf_args, num_args, 0));
883 return;
884 }
885
886 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
887 LLVMValueRef buf_args[7];
888 unsigned num_args = 0;
889
890 buf_args[num_args++] = args.data[0];
891 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
892 buf_args[num_args++] = args.data[1];
893
894 buf_args[num_args++] = args.resource;
895 buf_args[num_args++] = vindex;
896 buf_args[num_args++] = voffset;
897 buf_args[num_args++] = args.cache_policy & ac_slc ? ctx->i1true : ctx->i1false;
898
899 char intrinsic_name[40];
900 snprintf(intrinsic_name, sizeof(intrinsic_name),
901 "llvm.amdgcn.buffer.atomic.%s", action->intr_name);
902 emit_data->output[emit_data->chan] =
903 ac_to_float(&ctx->ac,
904 ac_build_intrinsic(&ctx->ac, intrinsic_name,
905 ctx->i32, buf_args, num_args, 0));
906 } else {
907 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
908 args.opcode = ac_image_atomic_cmpswap;
909 } else {
910 args.opcode = ac_image_atomic;
911 switch (inst->Instruction.Opcode) {
912 case TGSI_OPCODE_ATOMXCHG: args.atomic = ac_atomic_swap; break;
913 case TGSI_OPCODE_ATOMUADD: args.atomic = ac_atomic_add; break;
914 case TGSI_OPCODE_ATOMAND: args.atomic = ac_atomic_and; break;
915 case TGSI_OPCODE_ATOMOR: args.atomic = ac_atomic_or; break;
916 case TGSI_OPCODE_ATOMXOR: args.atomic = ac_atomic_xor; break;
917 case TGSI_OPCODE_ATOMUMIN: args.atomic = ac_atomic_umin; break;
918 case TGSI_OPCODE_ATOMUMAX: args.atomic = ac_atomic_umax; break;
919 case TGSI_OPCODE_ATOMIMIN: args.atomic = ac_atomic_smin; break;
920 case TGSI_OPCODE_ATOMIMAX: args.atomic = ac_atomic_smax; break;
921 case TGSI_OPCODE_ATOMINC_WRAP:
922 args.atomic = ac_atomic_inc_wrap;
923 break;
924 case TGSI_OPCODE_ATOMDEC_WRAP:
925 args.atomic = ac_atomic_dec_wrap;
926 break;
927 default: unreachable("unhandled image atomic");
928 }
929 }
930
931 args.dim = ac_image_dim_from_tgsi_target(ctx->screen, inst->Memory.Texture);
932 emit_data->output[emit_data->chan] =
933 ac_to_float(&ctx->ac, ac_build_image_opcode(&ctx->ac, &args));
934 }
935 }
936
937 static LLVMValueRef fix_resinfo(struct si_shader_context *ctx,
938 unsigned target, LLVMValueRef out)
939 {
940 LLVMBuilderRef builder = ctx->ac.builder;
941
942 /* 1D textures are allocated and used as 2D on GFX9. */
943 if (ctx->screen->info.chip_class == GFX9 &&
944 (target == TGSI_TEXTURE_1D_ARRAY ||
945 target == TGSI_TEXTURE_SHADOW1D_ARRAY)) {
946 LLVMValueRef layers =
947 LLVMBuildExtractElement(builder, out,
948 LLVMConstInt(ctx->i32, 2, 0), "");
949 out = LLVMBuildInsertElement(builder, out, layers,
950 ctx->i32_1, "");
951 }
952
953 /* Divide the number of layers by 6 to get the number of cubes. */
954 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
955 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
956 LLVMValueRef imm2 = LLVMConstInt(ctx->i32, 2, 0);
957
958 LLVMValueRef z = LLVMBuildExtractElement(builder, out, imm2, "");
959 z = LLVMBuildSDiv(builder, z, LLVMConstInt(ctx->i32, 6, 0), "");
960
961 out = LLVMBuildInsertElement(builder, out, z, imm2, "");
962 }
963 return out;
964 }
965
966 static void resq_emit(
967 const struct lp_build_tgsi_action *action,
968 struct lp_build_tgsi_context *bld_base,
969 struct lp_build_emit_data *emit_data)
970 {
971 struct si_shader_context *ctx = si_shader_context(bld_base);
972 LLVMBuilderRef builder = ctx->ac.builder;
973 const struct tgsi_full_instruction *inst = emit_data->inst;
974 const struct tgsi_full_src_register *reg =
975 &inst->Src[inst->Instruction.Opcode == TGSI_OPCODE_TXQ ? 1 : 0];
976
977 if (reg->Register.File == TGSI_FILE_BUFFER) {
978 LLVMValueRef rsrc = shader_buffer_fetch_rsrc(ctx, reg, false);
979
980 emit_data->output[emit_data->chan] =
981 LLVMBuildExtractElement(builder, rsrc,
982 LLVMConstInt(ctx->i32, 2, 0), "");
983 return;
984 }
985
986 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ &&
987 inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
988 LLVMValueRef rsrc;
989
990 tex_fetch_ptrs(bld_base, emit_data, &rsrc, NULL, NULL);
991 /* Read the size from the buffer descriptor directly. */
992 emit_data->output[emit_data->chan] =
993 get_buffer_size(bld_base, rsrc);
994 return;
995 }
996
997 if (inst->Instruction.Opcode == TGSI_OPCODE_RESQ &&
998 inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
999 LLVMValueRef rsrc;
1000
1001 image_fetch_rsrc(bld_base, reg, false, false, inst->Memory.Texture, &rsrc);
1002 emit_data->output[emit_data->chan] =
1003 get_buffer_size(bld_base, rsrc);
1004 return;
1005 }
1006
1007 unsigned target;
1008
1009 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ) {
1010 target = inst->Texture.Texture;
1011 } else {
1012 if (inst->Memory.Texture == TGSI_TEXTURE_3D)
1013 target = TGSI_TEXTURE_2D_ARRAY;
1014 else
1015 target = inst->Memory.Texture;
1016 }
1017
1018 struct ac_image_args args = {};
1019 args.opcode = ac_image_get_resinfo;
1020 args.dim = ac_texture_dim_from_tgsi_target(ctx->screen, target);
1021 args.dmask = 0xf;
1022 args.attributes = AC_FUNC_ATTR_READNONE;
1023
1024 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ) {
1025 tex_fetch_ptrs(bld_base, emit_data, &args.resource, NULL, NULL);
1026 args.lod = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
1027 } else {
1028 image_fetch_rsrc(bld_base, reg, false, false, target, &args.resource);
1029 args.lod = ctx->i32_0;
1030 }
1031
1032 emit_data->output[emit_data->chan] =
1033 fix_resinfo(ctx, target, ac_build_image_opcode(&ctx->ac, &args));
1034
1035 if (inst->Instruction.Opcode == TGSI_OPCODE_RESQ &&
1036 (target == TGSI_TEXTURE_2D_MSAA ||
1037 target == TGSI_TEXTURE_2D_ARRAY_MSAA)) {
1038 LLVMValueRef samples =
1039 ac_build_image_get_sample_count(&ctx->ac, args.resource);
1040
1041 emit_data->output[emit_data->chan] =
1042 LLVMBuildInsertElement(ctx->ac.builder,
1043 emit_data->output[emit_data->chan],
1044 samples,
1045 LLVMConstInt(ctx->i32, 3, 0), "");
1046 }
1047 }
1048
1049 /**
1050 * Load an image view, fmask view. or sampler state descriptor.
1051 */
1052 LLVMValueRef si_load_sampler_desc(struct si_shader_context *ctx,
1053 LLVMValueRef list, LLVMValueRef index,
1054 enum ac_descriptor_type type)
1055 {
1056 LLVMBuilderRef builder = ctx->ac.builder;
1057
1058 switch (type) {
1059 case AC_DESC_IMAGE:
1060 /* The image is at [0:7]. */
1061 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
1062 break;
1063 case AC_DESC_BUFFER:
1064 /* The buffer is in [4:7]. */
1065 index = ac_build_imad(&ctx->ac, index, LLVMConstInt(ctx->i32, 4, 0),
1066 ctx->i32_1);
1067 list = LLVMBuildPointerCast(builder, list,
1068 ac_array_in_const32_addr_space(ctx->v4i32), "");
1069 break;
1070 case AC_DESC_FMASK:
1071 /* The FMASK is at [8:15]. */
1072 index = ac_build_imad(&ctx->ac, index, LLVMConstInt(ctx->i32, 2, 0),
1073 ctx->i32_1);
1074 break;
1075 case AC_DESC_SAMPLER:
1076 /* The sampler state is at [12:15]. */
1077 index = ac_build_imad(&ctx->ac, index, LLVMConstInt(ctx->i32, 4, 0),
1078 LLVMConstInt(ctx->i32, 3, 0));
1079 list = LLVMBuildPointerCast(builder, list,
1080 ac_array_in_const32_addr_space(ctx->v4i32), "");
1081 break;
1082 case AC_DESC_PLANE_0:
1083 case AC_DESC_PLANE_1:
1084 case AC_DESC_PLANE_2:
1085 /* Only used for the multiplane image support for Vulkan. Should
1086 * never be reached in radeonsi.
1087 */
1088 unreachable("Plane descriptor requested in radeonsi.");
1089 }
1090
1091 return ac_build_load_to_sgpr(&ctx->ac, list, index);
1092 }
1093
1094 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
1095 *
1096 * GFX6-GFX7:
1097 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
1098 * filtering manually. The driver sets img7 to a mask clearing
1099 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
1100 * s_and_b32 samp0, samp0, img7
1101 *
1102 * GFX8:
1103 * The ANISO_OVERRIDE sampler field enables this fix in TA.
1104 */
1105 static LLVMValueRef sici_fix_sampler_aniso(struct si_shader_context *ctx,
1106 LLVMValueRef res, LLVMValueRef samp)
1107 {
1108 LLVMValueRef img7, samp0;
1109
1110 if (ctx->screen->info.chip_class >= GFX8)
1111 return samp;
1112
1113 img7 = LLVMBuildExtractElement(ctx->ac.builder, res,
1114 LLVMConstInt(ctx->i32, 7, 0), "");
1115 samp0 = LLVMBuildExtractElement(ctx->ac.builder, samp,
1116 ctx->i32_0, "");
1117 samp0 = LLVMBuildAnd(ctx->ac.builder, samp0, img7, "");
1118 return LLVMBuildInsertElement(ctx->ac.builder, samp, samp0,
1119 ctx->i32_0, "");
1120 }
1121
1122 static void tex_fetch_ptrs(struct lp_build_tgsi_context *bld_base,
1123 struct lp_build_emit_data *emit_data,
1124 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
1125 LLVMValueRef *fmask_ptr)
1126 {
1127 struct si_shader_context *ctx = si_shader_context(bld_base);
1128 LLVMValueRef list = ac_get_arg(&ctx->ac, ctx->samplers_and_images);
1129 const struct tgsi_full_instruction *inst = emit_data->inst;
1130 const struct tgsi_full_src_register *reg;
1131 unsigned target = inst->Texture.Texture;
1132 unsigned sampler_src;
1133 LLVMValueRef index;
1134
1135 sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
1136 reg = &emit_data->inst->Src[sampler_src];
1137
1138 if (reg->Register.Indirect) {
1139 index = si_get_bounded_indirect_index(ctx,
1140 &reg->Indirect,
1141 reg->Register.Index,
1142 ctx->num_samplers);
1143 index = LLVMBuildAdd(ctx->ac.builder, index,
1144 LLVMConstInt(ctx->i32, SI_NUM_IMAGE_SLOTS / 2, 0), "");
1145 } else {
1146 index = LLVMConstInt(ctx->i32,
1147 si_get_sampler_slot(reg->Register.Index), 0);
1148 }
1149
1150 if (reg->Register.File != TGSI_FILE_SAMPLER) {
1151 /* Bindless descriptors are accessible from a different pair of
1152 * user SGPR indices.
1153 */
1154 list = ac_get_arg(&ctx->ac, ctx->bindless_samplers_and_images);
1155 index = lp_build_emit_fetch_src(bld_base, reg,
1156 TGSI_TYPE_UNSIGNED, 0);
1157
1158 /* Since bindless handle arithmetic can contain an unsigned integer
1159 * wraparound and si_load_sampler_desc assumes there isn't any,
1160 * use GEP without "inbounds" (inside ac_build_pointer_add)
1161 * to prevent incorrect code generation and hangs.
1162 */
1163 index = LLVMBuildMul(ctx->ac.builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
1164 list = ac_build_pointer_add(&ctx->ac, list, index);
1165 index = ctx->i32_0;
1166 }
1167
1168 if (target == TGSI_TEXTURE_BUFFER)
1169 *res_ptr = si_load_sampler_desc(ctx, list, index, AC_DESC_BUFFER);
1170 else
1171 *res_ptr = si_load_sampler_desc(ctx, list, index, AC_DESC_IMAGE);
1172
1173 if (samp_ptr)
1174 *samp_ptr = NULL;
1175 if (fmask_ptr)
1176 *fmask_ptr = NULL;
1177
1178 if (target == TGSI_TEXTURE_2D_MSAA ||
1179 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
1180 if (fmask_ptr)
1181 *fmask_ptr = si_load_sampler_desc(ctx, list, index,
1182 AC_DESC_FMASK);
1183 } else if (target != TGSI_TEXTURE_BUFFER) {
1184 if (samp_ptr) {
1185 *samp_ptr = si_load_sampler_desc(ctx, list, index,
1186 AC_DESC_SAMPLER);
1187 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
1188 }
1189 }
1190 }
1191
1192 /* Gather4 should follow the same rules as bilinear filtering, but the hardware
1193 * incorrectly forces nearest filtering if the texture format is integer.
1194 * The only effect it has on Gather4, which always returns 4 texels for
1195 * bilinear filtering, is that the final coordinates are off by 0.5 of
1196 * the texel size.
1197 *
1198 * The workaround is to subtract 0.5 from the unnormalized coordinates,
1199 * or (0.5 / size) from the normalized coordinates.
1200 *
1201 * However, cube textures with 8_8_8_8 data formats require a different
1202 * workaround of overriding the num format to USCALED/SSCALED. This would lose
1203 * precision in 32-bit data formats, so it needs to be applied dynamically at
1204 * runtime. In this case, return an i1 value that indicates whether the
1205 * descriptor was overridden (and hence a fixup of the sampler result is needed).
1206 */
1207 static LLVMValueRef
1208 si_lower_gather4_integer(struct si_shader_context *ctx,
1209 struct ac_image_args *args,
1210 unsigned target,
1211 enum tgsi_return_type return_type)
1212 {
1213 LLVMBuilderRef builder = ctx->ac.builder;
1214 LLVMValueRef wa_8888 = NULL;
1215 LLVMValueRef half_texel[2];
1216
1217 assert(return_type == TGSI_RETURN_TYPE_SINT ||
1218 return_type == TGSI_RETURN_TYPE_UINT);
1219
1220 if (target == TGSI_TEXTURE_CUBE ||
1221 target == TGSI_TEXTURE_CUBE_ARRAY) {
1222 LLVMValueRef formats;
1223 LLVMValueRef data_format;
1224 LLVMValueRef wa_formats;
1225
1226 formats = LLVMBuildExtractElement(builder, args->resource, ctx->i32_1, "");
1227
1228 data_format = LLVMBuildLShr(builder, formats,
1229 LLVMConstInt(ctx->i32, 20, false), "");
1230 data_format = LLVMBuildAnd(builder, data_format,
1231 LLVMConstInt(ctx->i32, (1u << 6) - 1, false), "");
1232 wa_8888 = LLVMBuildICmp(
1233 builder, LLVMIntEQ, data_format,
1234 LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false),
1235 "");
1236
1237 uint32_t wa_num_format =
1238 return_type == TGSI_RETURN_TYPE_UINT ?
1239 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_USCALED) :
1240 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_SSCALED);
1241 wa_formats = LLVMBuildAnd(builder, formats,
1242 LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT, false),
1243 "");
1244 wa_formats = LLVMBuildOr(builder, wa_formats,
1245 LLVMConstInt(ctx->i32, wa_num_format, false), "");
1246
1247 formats = LLVMBuildSelect(builder, wa_8888, wa_formats, formats, "");
1248 args->resource = LLVMBuildInsertElement(
1249 builder, args->resource, formats, ctx->i32_1, "");
1250 }
1251
1252 if (target == TGSI_TEXTURE_RECT ||
1253 target == TGSI_TEXTURE_SHADOWRECT) {
1254 assert(!wa_8888);
1255 half_texel[0] = half_texel[1] = LLVMConstReal(ctx->f32, -0.5);
1256 } else {
1257 struct ac_image_args resinfo = {};
1258 struct lp_build_if_state if_ctx;
1259
1260 if (wa_8888) {
1261 /* Skip the texture size query entirely if we don't need it. */
1262 lp_build_if(&if_ctx, &ctx->gallivm, LLVMBuildNot(builder, wa_8888, ""));
1263 }
1264
1265 /* Query the texture size. */
1266 resinfo.opcode = ac_image_get_resinfo;
1267 resinfo.dim = ac_texture_dim_from_tgsi_target(ctx->screen, target);
1268 resinfo.resource = args->resource;
1269 resinfo.sampler = args->sampler;
1270 resinfo.lod = ctx->ac.i32_0;
1271 resinfo.dmask = 0xf;
1272 resinfo.attributes = AC_FUNC_ATTR_READNONE;
1273
1274 LLVMValueRef texsize =
1275 fix_resinfo(ctx, target,
1276 ac_build_image_opcode(&ctx->ac, &resinfo));
1277
1278 /* Compute -0.5 / size. */
1279 for (unsigned c = 0; c < 2; c++) {
1280 half_texel[c] =
1281 LLVMBuildExtractElement(builder, texsize,
1282 LLVMConstInt(ctx->i32, c, 0), "");
1283 half_texel[c] = LLVMBuildUIToFP(builder, half_texel[c], ctx->f32, "");
1284 half_texel[c] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, half_texel[c]);
1285 half_texel[c] = LLVMBuildFMul(builder, half_texel[c],
1286 LLVMConstReal(ctx->f32, -0.5), "");
1287 }
1288
1289 if (wa_8888) {
1290 lp_build_endif(&if_ctx);
1291
1292 LLVMBasicBlockRef bb[2] = { if_ctx.true_block, if_ctx.entry_block };
1293
1294 for (unsigned c = 0; c < 2; c++) {
1295 LLVMValueRef values[2] = { half_texel[c], ctx->ac.f32_0 };
1296 half_texel[c] = ac_build_phi(&ctx->ac, ctx->f32, 2,
1297 values, bb);
1298 }
1299 }
1300 }
1301
1302 for (unsigned c = 0; c < 2; c++) {
1303 LLVMValueRef tmp;
1304 tmp = ac_to_float(&ctx->ac, args->coords[c]);
1305 tmp = LLVMBuildFAdd(builder, tmp, half_texel[c], "");
1306 args->coords[c] = ac_to_integer(&ctx->ac, tmp);
1307 }
1308
1309 return wa_8888;
1310 }
1311
1312 /* The second half of the cube texture 8_8_8_8 integer workaround: adjust the
1313 * result after the gather operation.
1314 */
1315 static LLVMValueRef
1316 si_fix_gather4_integer_result(struct si_shader_context *ctx,
1317 LLVMValueRef result,
1318 enum tgsi_return_type return_type,
1319 LLVMValueRef wa)
1320 {
1321 LLVMBuilderRef builder = ctx->ac.builder;
1322
1323 assert(return_type == TGSI_RETURN_TYPE_SINT ||
1324 return_type == TGSI_RETURN_TYPE_UINT);
1325
1326 for (unsigned chan = 0; chan < 4; ++chan) {
1327 LLVMValueRef chanv = LLVMConstInt(ctx->i32, chan, false);
1328 LLVMValueRef value;
1329 LLVMValueRef wa_value;
1330
1331 value = LLVMBuildExtractElement(builder, result, chanv, "");
1332
1333 if (return_type == TGSI_RETURN_TYPE_UINT)
1334 wa_value = LLVMBuildFPToUI(builder, value, ctx->i32, "");
1335 else
1336 wa_value = LLVMBuildFPToSI(builder, value, ctx->i32, "");
1337 wa_value = ac_to_float(&ctx->ac, wa_value);
1338 value = LLVMBuildSelect(builder, wa, wa_value, value, "");
1339
1340 result = LLVMBuildInsertElement(builder, result, value, chanv, "");
1341 }
1342
1343 return result;
1344 }
1345
1346 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
1347 struct lp_build_tgsi_context *bld_base,
1348 struct lp_build_emit_data *emit_data)
1349 {
1350 struct si_shader_context *ctx = si_shader_context(bld_base);
1351 const struct tgsi_full_instruction *inst = emit_data->inst;
1352 unsigned opcode = inst->Instruction.Opcode;
1353 unsigned target = inst->Texture.Texture;
1354 struct ac_image_args args = {};
1355 int ref_pos = tgsi_util_get_shadow_ref_src_index(target);
1356 unsigned chan;
1357 bool has_offset = inst->Texture.NumOffsets > 0;
1358 LLVMValueRef fmask_ptr = NULL;
1359
1360 tex_fetch_ptrs(bld_base, emit_data, &args.resource, &args.sampler, &fmask_ptr);
1361
1362 if (target == TGSI_TEXTURE_BUFFER) {
1363 LLVMValueRef vindex = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
1364 unsigned num_channels =
1365 util_last_bit(inst->Dst[0].Register.WriteMask);
1366 LLVMValueRef result =
1367 ac_build_buffer_load_format(&ctx->ac,
1368 args.resource,
1369 vindex,
1370 ctx->i32_0,
1371 num_channels, 0, true);
1372 emit_data->output[emit_data->chan] =
1373 ac_build_expand_to_vec4(&ctx->ac, result, num_channels);
1374 return;
1375 }
1376
1377 /* Fetch and project texture coordinates */
1378 args.coords[3] = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_W);
1379 for (chan = 0; chan < 3; chan++) {
1380 args.coords[chan] = lp_build_emit_fetch(bld_base, inst, 0, chan);
1381 if (opcode == TGSI_OPCODE_TXP)
1382 args.coords[chan] = ac_build_fdiv(&ctx->ac,
1383 args.coords[chan], args.coords[3]);
1384 }
1385
1386 if (opcode == TGSI_OPCODE_TXP)
1387 args.coords[3] = ctx->ac.f32_1;
1388
1389 /* Pack offsets. */
1390 if (has_offset &&
1391 opcode != TGSI_OPCODE_TXF &&
1392 opcode != TGSI_OPCODE_TXF_LZ) {
1393 /* The offsets are six-bit signed integers packed like this:
1394 * X=[5:0], Y=[13:8], and Z=[21:16].
1395 */
1396 LLVMValueRef offset[3], pack;
1397
1398 assert(inst->Texture.NumOffsets == 1);
1399
1400 for (chan = 0; chan < 3; chan++) {
1401 offset[chan] = lp_build_emit_fetch_texoffset(bld_base, inst, 0, chan);
1402 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
1403 LLVMConstInt(ctx->i32, 0x3f, 0), "");
1404 if (chan)
1405 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
1406 LLVMConstInt(ctx->i32, chan*8, 0), "");
1407 }
1408
1409 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
1410 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
1411 args.offset = pack;
1412 }
1413
1414 /* Pack LOD bias value */
1415 if (opcode == TGSI_OPCODE_TXB)
1416 args.bias = args.coords[3];
1417 if (opcode == TGSI_OPCODE_TXB2)
1418 args.bias = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
1419
1420 /* Pack depth comparison value */
1421 if (tgsi_is_shadow_target(target) && opcode != TGSI_OPCODE_LODQ) {
1422 LLVMValueRef z;
1423
1424 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
1425 z = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
1426 } else {
1427 assert(ref_pos >= 0);
1428 z = args.coords[ref_pos];
1429 }
1430
1431 /* Section 8.23.1 (Depth Texture Comparison Mode) of the
1432 * OpenGL 4.5 spec says:
1433 *
1434 * "If the texture’s internal format indicates a fixed-point
1435 * depth texture, then D_t and D_ref are clamped to the
1436 * range [0, 1]; otherwise no clamping is performed."
1437 *
1438 * TC-compatible HTILE promotes Z16 and Z24 to Z32_FLOAT,
1439 * so the depth comparison value isn't clamped for Z16 and
1440 * Z24 anymore. Do it manually here for GFX8-9; GFX10 has
1441 * an explicitly clamped 32-bit float format.
1442 */
1443 if (ctx->screen->info.chip_class >= GFX8 &&
1444 ctx->screen->info.chip_class <= GFX9) {
1445 LLVMValueRef upgraded;
1446 LLVMValueRef clamped;
1447 upgraded = LLVMBuildExtractElement(ctx->ac.builder, args.sampler,
1448 LLVMConstInt(ctx->i32, 3, false), "");
1449 upgraded = LLVMBuildLShr(ctx->ac.builder, upgraded,
1450 LLVMConstInt(ctx->i32, 29, false), "");
1451 upgraded = LLVMBuildTrunc(ctx->ac.builder, upgraded, ctx->i1, "");
1452 clamped = ac_build_clamp(&ctx->ac, z);
1453 z = LLVMBuildSelect(ctx->ac.builder, upgraded, clamped, z, "");
1454 }
1455
1456 args.compare = z;
1457 }
1458
1459 /* Pack user derivatives */
1460 if (opcode == TGSI_OPCODE_TXD) {
1461 int param, num_src_deriv_channels, num_dst_deriv_channels;
1462
1463 switch (target) {
1464 case TGSI_TEXTURE_3D:
1465 num_src_deriv_channels = 3;
1466 num_dst_deriv_channels = 3;
1467 break;
1468 case TGSI_TEXTURE_2D:
1469 case TGSI_TEXTURE_SHADOW2D:
1470 case TGSI_TEXTURE_RECT:
1471 case TGSI_TEXTURE_SHADOWRECT:
1472 case TGSI_TEXTURE_2D_ARRAY:
1473 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1474 num_src_deriv_channels = 2;
1475 num_dst_deriv_channels = 2;
1476 break;
1477 case TGSI_TEXTURE_CUBE:
1478 case TGSI_TEXTURE_SHADOWCUBE:
1479 case TGSI_TEXTURE_CUBE_ARRAY:
1480 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
1481 /* Cube derivatives will be converted to 2D. */
1482 num_src_deriv_channels = 3;
1483 num_dst_deriv_channels = 3;
1484 break;
1485 case TGSI_TEXTURE_1D:
1486 case TGSI_TEXTURE_SHADOW1D:
1487 case TGSI_TEXTURE_1D_ARRAY:
1488 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1489 num_src_deriv_channels = 1;
1490
1491 /* 1D textures are allocated and used as 2D on GFX9. */
1492 if (ctx->screen->info.chip_class == GFX9) {
1493 num_dst_deriv_channels = 2;
1494 } else {
1495 num_dst_deriv_channels = 1;
1496 }
1497 break;
1498 default:
1499 unreachable("invalid target");
1500 }
1501
1502 for (param = 0; param < 2; param++) {
1503 for (chan = 0; chan < num_src_deriv_channels; chan++)
1504 args.derivs[param * num_dst_deriv_channels + chan] =
1505 lp_build_emit_fetch(bld_base, inst, param+1, chan);
1506
1507 /* Fill in the rest with zeros. */
1508 for (chan = num_src_deriv_channels;
1509 chan < num_dst_deriv_channels; chan++)
1510 args.derivs[param * num_dst_deriv_channels + chan] =
1511 ctx->ac.f32_0;
1512 }
1513 }
1514
1515 if (target == TGSI_TEXTURE_CUBE ||
1516 target == TGSI_TEXTURE_CUBE_ARRAY ||
1517 target == TGSI_TEXTURE_SHADOWCUBE ||
1518 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
1519 ac_prepare_cube_coords(&ctx->ac,
1520 opcode == TGSI_OPCODE_TXD,
1521 target == TGSI_TEXTURE_CUBE_ARRAY ||
1522 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY,
1523 opcode == TGSI_OPCODE_LODQ,
1524 args.coords, args.derivs);
1525 } else if (tgsi_is_array_sampler(target) &&
1526 opcode != TGSI_OPCODE_TXF &&
1527 opcode != TGSI_OPCODE_TXF_LZ &&
1528 ctx->screen->info.chip_class <= GFX8) {
1529 unsigned array_coord = target == TGSI_TEXTURE_1D_ARRAY ? 1 : 2;
1530 args.coords[array_coord] = ac_build_round(&ctx->ac, args.coords[array_coord]);
1531 }
1532
1533 /* 1D textures are allocated and used as 2D on GFX9. */
1534 if (ctx->screen->info.chip_class == GFX9) {
1535 LLVMValueRef filler;
1536
1537 /* Use 0.5, so that we don't sample the border color. */
1538 if (opcode == TGSI_OPCODE_TXF ||
1539 opcode == TGSI_OPCODE_TXF_LZ)
1540 filler = ctx->i32_0;
1541 else
1542 filler = LLVMConstReal(ctx->f32, 0.5);
1543
1544 if (target == TGSI_TEXTURE_1D ||
1545 target == TGSI_TEXTURE_SHADOW1D) {
1546 args.coords[1] = filler;
1547 } else if (target == TGSI_TEXTURE_1D_ARRAY ||
1548 target == TGSI_TEXTURE_SHADOW1D_ARRAY) {
1549 args.coords[2] = args.coords[1];
1550 args.coords[1] = filler;
1551 }
1552 }
1553
1554 /* Pack LOD or sample index */
1555 if (opcode == TGSI_OPCODE_TXL)
1556 args.lod = args.coords[3];
1557 else if (opcode == TGSI_OPCODE_TXL2)
1558 args.lod = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
1559 else if (opcode == TGSI_OPCODE_TXF) {
1560 if (target == TGSI_TEXTURE_2D_MSAA) {
1561 /* No LOD, but move sample index into the right place. */
1562 args.coords[2] = args.coords[3];
1563 } else if (target != TGSI_TEXTURE_2D_ARRAY_MSAA) {
1564 args.lod = args.coords[3];
1565 }
1566 }
1567
1568 if ((target == TGSI_TEXTURE_2D_MSAA ||
1569 target == TGSI_TEXTURE_2D_ARRAY_MSAA) &&
1570 !(ctx->screen->debug_flags & DBG(NO_FMASK))) {
1571 ac_apply_fmask_to_sample(&ctx->ac, fmask_ptr, args.coords,
1572 target == TGSI_TEXTURE_2D_ARRAY_MSAA);
1573 }
1574
1575 if (opcode == TGSI_OPCODE_TXF ||
1576 opcode == TGSI_OPCODE_TXF_LZ) {
1577 /* add tex offsets */
1578 if (inst->Texture.NumOffsets) {
1579 const struct tgsi_texture_offset *off = inst->TexOffsets;
1580
1581 assert(inst->Texture.NumOffsets == 1);
1582
1583 switch (target) {
1584 case TGSI_TEXTURE_3D:
1585 args.coords[2] =
1586 LLVMBuildAdd(ctx->ac.builder, args.coords[2],
1587 ctx->imms[off->Index * TGSI_NUM_CHANNELS + off->SwizzleZ], "");
1588 /* fall through */
1589 case TGSI_TEXTURE_2D:
1590 case TGSI_TEXTURE_SHADOW2D:
1591 case TGSI_TEXTURE_RECT:
1592 case TGSI_TEXTURE_SHADOWRECT:
1593 case TGSI_TEXTURE_2D_ARRAY:
1594 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1595 args.coords[1] =
1596 LLVMBuildAdd(ctx->ac.builder, args.coords[1],
1597 ctx->imms[off->Index * TGSI_NUM_CHANNELS + off->SwizzleY], "");
1598 /* fall through */
1599 case TGSI_TEXTURE_1D:
1600 case TGSI_TEXTURE_SHADOW1D:
1601 case TGSI_TEXTURE_1D_ARRAY:
1602 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1603 args.coords[0] =
1604 LLVMBuildAdd(ctx->ac.builder, args.coords[0],
1605 ctx->imms[off->Index * TGSI_NUM_CHANNELS + off->SwizzleX], "");
1606 break;
1607 /* texture offsets do not apply to other texture targets */
1608 }
1609 }
1610 }
1611
1612 if (opcode == TGSI_OPCODE_TG4) {
1613 unsigned gather_comp = 0;
1614
1615 /* DMASK was repurposed for GATHER4. 4 components are always
1616 * returned and DMASK works like a swizzle - it selects
1617 * the component to fetch. The only valid DMASK values are
1618 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
1619 * (red,red,red,red) etc.) The ISA document doesn't mention
1620 * this.
1621 */
1622
1623 /* Get the component index from src1.x for Gather4. */
1624 if (!tgsi_is_shadow_target(target)) {
1625 LLVMValueRef comp_imm;
1626 struct tgsi_src_register src1 = inst->Src[1].Register;
1627
1628 assert(src1.File == TGSI_FILE_IMMEDIATE);
1629
1630 comp_imm = ctx->imms[src1.Index * TGSI_NUM_CHANNELS + src1.SwizzleX];
1631 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
1632 gather_comp = CLAMP(gather_comp, 0, 3);
1633 }
1634
1635 args.dmask = 1 << gather_comp;
1636 } else {
1637 args.dmask = 0xf;
1638 }
1639
1640 args.dim = ac_texture_dim_from_tgsi_target(ctx->screen, target);
1641 args.unorm = target == TGSI_TEXTURE_RECT ||
1642 target == TGSI_TEXTURE_SHADOWRECT;
1643 args.opcode = ac_image_sample;
1644
1645 switch (opcode) {
1646 case TGSI_OPCODE_TXF:
1647 case TGSI_OPCODE_TXF_LZ:
1648 args.opcode = opcode == TGSI_OPCODE_TXF_LZ ||
1649 target == TGSI_TEXTURE_2D_MSAA ||
1650 target == TGSI_TEXTURE_2D_ARRAY_MSAA ?
1651 ac_image_load : ac_image_load_mip;
1652 break;
1653 case TGSI_OPCODE_LODQ:
1654 args.opcode = ac_image_get_lod;
1655 break;
1656 case TGSI_OPCODE_TEX:
1657 case TGSI_OPCODE_TEX2:
1658 case TGSI_OPCODE_TXP:
1659 if (ctx->type != PIPE_SHADER_FRAGMENT)
1660 args.level_zero = true;
1661 break;
1662 case TGSI_OPCODE_TEX_LZ:
1663 args.level_zero = true;
1664 break;
1665 case TGSI_OPCODE_TXB:
1666 case TGSI_OPCODE_TXB2:
1667 assert(ctx->type == PIPE_SHADER_FRAGMENT);
1668 break;
1669 case TGSI_OPCODE_TXL:
1670 case TGSI_OPCODE_TXL2:
1671 break;
1672 case TGSI_OPCODE_TXD:
1673 break;
1674 case TGSI_OPCODE_TG4:
1675 args.opcode = ac_image_gather4;
1676 args.level_zero = true;
1677 break;
1678 default:
1679 assert(0);
1680 return;
1681 }
1682
1683 /* The hardware needs special lowering for Gather4 with integer formats. */
1684 LLVMValueRef gather4_int_result_workaround = NULL;
1685
1686 if (ctx->screen->info.chip_class <= GFX8 &&
1687 opcode == TGSI_OPCODE_TG4) {
1688 assert(inst->Texture.ReturnType != TGSI_RETURN_TYPE_UNKNOWN);
1689
1690 if (inst->Texture.ReturnType == TGSI_RETURN_TYPE_SINT ||
1691 inst->Texture.ReturnType == TGSI_RETURN_TYPE_UINT) {
1692 gather4_int_result_workaround =
1693 si_lower_gather4_integer(ctx, &args, target,
1694 inst->Texture.ReturnType);
1695 }
1696 }
1697
1698 args.attributes = AC_FUNC_ATTR_READNONE;
1699 LLVMValueRef result = ac_build_image_opcode(&ctx->ac, &args);
1700
1701 if (gather4_int_result_workaround) {
1702 result = si_fix_gather4_integer_result(ctx, result,
1703 inst->Texture.ReturnType,
1704 gather4_int_result_workaround);
1705 }
1706
1707 emit_data->output[emit_data->chan] = result;
1708 }
1709
1710 static void si_llvm_emit_txqs(
1711 const struct lp_build_tgsi_action *action,
1712 struct lp_build_tgsi_context *bld_base,
1713 struct lp_build_emit_data *emit_data)
1714 {
1715 struct si_shader_context *ctx = si_shader_context(bld_base);
1716 LLVMValueRef rsrc;
1717
1718 tex_fetch_ptrs(bld_base, emit_data, &rsrc, NULL, NULL);
1719
1720 rsrc = LLVMBuildBitCast(ctx->ac.builder, rsrc, ctx->v8i32, "");
1721 emit_data->output[emit_data->chan] =
1722 ac_build_image_get_sample_count(&ctx->ac, rsrc);
1723 }
1724
1725 static LLVMValueRef si_llvm_emit_fbfetch(struct si_shader_context *ctx)
1726 {
1727 struct ac_image_args args = {};
1728 LLVMValueRef ptr, image, fmask;
1729
1730 /* Ignore src0, because KHR_blend_func_extended disallows multiple render
1731 * targets.
1732 */
1733
1734 /* Load the image descriptor. */
1735 STATIC_ASSERT(SI_PS_IMAGE_COLORBUF0 % 2 == 0);
1736 ptr = ac_get_arg(&ctx->ac, ctx->rw_buffers);
1737 ptr = LLVMBuildPointerCast(ctx->ac.builder, ptr,
1738 ac_array_in_const32_addr_space(ctx->v8i32), "");
1739 image = ac_build_load_to_sgpr(&ctx->ac, ptr,
1740 LLVMConstInt(ctx->i32, SI_PS_IMAGE_COLORBUF0 / 2, 0));
1741
1742 unsigned chan = 0;
1743
1744 args.coords[chan++] = si_unpack_param(ctx, ctx->pos_fixed_pt, 0, 16);
1745
1746 if (!ctx->shader->key.mono.u.ps.fbfetch_is_1D)
1747 args.coords[chan++] = si_unpack_param(ctx, ctx->pos_fixed_pt, 16, 16);
1748
1749 /* Get the current render target layer index. */
1750 if (ctx->shader->key.mono.u.ps.fbfetch_layered)
1751 args.coords[chan++] = si_unpack_param(ctx, ctx->args.ancillary, 16, 11);
1752
1753 if (ctx->shader->key.mono.u.ps.fbfetch_msaa)
1754 args.coords[chan++] = si_get_sample_id(ctx);
1755
1756 if (ctx->shader->key.mono.u.ps.fbfetch_msaa &&
1757 !(ctx->screen->debug_flags & DBG(NO_FMASK))) {
1758 fmask = ac_build_load_to_sgpr(&ctx->ac, ptr,
1759 LLVMConstInt(ctx->i32, SI_PS_IMAGE_COLORBUF0_FMASK / 2, 0));
1760
1761 ac_apply_fmask_to_sample(&ctx->ac, fmask, args.coords,
1762 ctx->shader->key.mono.u.ps.fbfetch_layered);
1763 }
1764
1765 args.opcode = ac_image_load;
1766 args.resource = image;
1767 args.dmask = 0xf;
1768 args.attributes = AC_FUNC_ATTR_READNONE;
1769
1770 if (ctx->shader->key.mono.u.ps.fbfetch_msaa)
1771 args.dim = ctx->shader->key.mono.u.ps.fbfetch_layered ?
1772 ac_image_2darraymsaa : ac_image_2dmsaa;
1773 else if (ctx->shader->key.mono.u.ps.fbfetch_is_1D)
1774 args.dim = ctx->shader->key.mono.u.ps.fbfetch_layered ?
1775 ac_image_1darray : ac_image_1d;
1776 else
1777 args.dim = ctx->shader->key.mono.u.ps.fbfetch_layered ?
1778 ac_image_2darray : ac_image_2d;
1779
1780 return ac_build_image_opcode(&ctx->ac, &args);
1781 }
1782
1783 static void si_tgsi_emit_fbfetch(const struct lp_build_tgsi_action *action,
1784 struct lp_build_tgsi_context *bld_base,
1785 struct lp_build_emit_data *emit_data)
1786 {
1787 struct si_shader_context *ctx = si_shader_context(bld_base);
1788
1789 emit_data->output[emit_data->chan] = si_llvm_emit_fbfetch(ctx);
1790 }
1791
1792 LLVMValueRef si_nir_emit_fbfetch(struct ac_shader_abi *abi)
1793 {
1794 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1795
1796 return si_llvm_emit_fbfetch(ctx);
1797 }
1798
1799 /**
1800 * Setup actions for TGSI memory opcode, including texture opcodes.
1801 */
1802 void si_shader_context_init_mem(struct si_shader_context *ctx)
1803 {
1804 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
1805
1806 bld_base->op_actions[TGSI_OPCODE_TEX].emit = build_tex_intrinsic;
1807 bld_base->op_actions[TGSI_OPCODE_TEX_LZ].emit = build_tex_intrinsic;
1808 bld_base->op_actions[TGSI_OPCODE_TEX2].emit = build_tex_intrinsic;
1809 bld_base->op_actions[TGSI_OPCODE_TXB].emit = build_tex_intrinsic;
1810 bld_base->op_actions[TGSI_OPCODE_TXB2].emit = build_tex_intrinsic;
1811 bld_base->op_actions[TGSI_OPCODE_TXD].emit = build_tex_intrinsic;
1812 bld_base->op_actions[TGSI_OPCODE_TXF].emit = build_tex_intrinsic;
1813 bld_base->op_actions[TGSI_OPCODE_TXF_LZ].emit = build_tex_intrinsic;
1814 bld_base->op_actions[TGSI_OPCODE_TXL].emit = build_tex_intrinsic;
1815 bld_base->op_actions[TGSI_OPCODE_TXL2].emit = build_tex_intrinsic;
1816 bld_base->op_actions[TGSI_OPCODE_TXP].emit = build_tex_intrinsic;
1817 bld_base->op_actions[TGSI_OPCODE_TXQ].emit = resq_emit;
1818 bld_base->op_actions[TGSI_OPCODE_TG4].emit = build_tex_intrinsic;
1819 bld_base->op_actions[TGSI_OPCODE_LODQ].emit = build_tex_intrinsic;
1820 bld_base->op_actions[TGSI_OPCODE_TXQS].emit = si_llvm_emit_txqs;
1821
1822 bld_base->op_actions[TGSI_OPCODE_FBFETCH].emit = si_tgsi_emit_fbfetch;
1823
1824 bld_base->op_actions[TGSI_OPCODE_LOAD].emit = load_emit;
1825 bld_base->op_actions[TGSI_OPCODE_STORE].emit = store_emit;
1826 bld_base->op_actions[TGSI_OPCODE_RESQ].emit = resq_emit;
1827
1828 bld_base->op_actions[TGSI_OPCODE_ATOMUADD].emit = atomic_emit;
1829 bld_base->op_actions[TGSI_OPCODE_ATOMUADD].intr_name = "add";
1830 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG].emit = atomic_emit;
1831 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG].intr_name = "swap";
1832 bld_base->op_actions[TGSI_OPCODE_ATOMCAS].emit = atomic_emit;
1833 bld_base->op_actions[TGSI_OPCODE_ATOMCAS].intr_name = "cmpswap";
1834 bld_base->op_actions[TGSI_OPCODE_ATOMAND].emit = atomic_emit;
1835 bld_base->op_actions[TGSI_OPCODE_ATOMAND].intr_name = "and";
1836 bld_base->op_actions[TGSI_OPCODE_ATOMOR].emit = atomic_emit;
1837 bld_base->op_actions[TGSI_OPCODE_ATOMOR].intr_name = "or";
1838 bld_base->op_actions[TGSI_OPCODE_ATOMXOR].emit = atomic_emit;
1839 bld_base->op_actions[TGSI_OPCODE_ATOMXOR].intr_name = "xor";
1840 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN].emit = atomic_emit;
1841 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN].intr_name = "umin";
1842 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX].emit = atomic_emit;
1843 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX].intr_name = "umax";
1844 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN].emit = atomic_emit;
1845 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN].intr_name = "smin";
1846 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX].emit = atomic_emit;
1847 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX].intr_name = "smax";
1848 bld_base->op_actions[TGSI_OPCODE_ATOMINC_WRAP].emit = atomic_emit;
1849 bld_base->op_actions[TGSI_OPCODE_ATOMINC_WRAP].intr_name = "inc";
1850 bld_base->op_actions[TGSI_OPCODE_ATOMDEC_WRAP].emit = atomic_emit;
1851 bld_base->op_actions[TGSI_OPCODE_ATOMDEC_WRAP].intr_name = "dec";
1852 }