2 * Copyright 2017 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "si_shader_internal.h"
28 #include "tgsi/tgsi_build.h"
29 #include "tgsi/tgsi_util.h"
30 #include "ac_llvm_util.h"
32 static void build_tex_intrinsic(const struct lp_build_tgsi_action
*action
,
33 struct lp_build_tgsi_context
*bld_base
,
34 struct lp_build_emit_data
*emit_data
);
36 static const struct lp_build_tgsi_action tex_action
;
39 * Given a v8i32 resource descriptor for a buffer, extract the size of the
40 * buffer in number of elements and return it as an i32.
42 static LLVMValueRef
get_buffer_size(
43 struct lp_build_tgsi_context
*bld_base
,
44 LLVMValueRef descriptor
)
46 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
47 LLVMBuilderRef builder
= ctx
->ac
.builder
;
49 LLVMBuildExtractElement(builder
, descriptor
,
50 LLVMConstInt(ctx
->i32
, 2, 0), "");
52 if (ctx
->screen
->info
.chip_class
== VI
) {
53 /* On VI, the descriptor contains the size in bytes,
54 * but TXQ must return the size in elements.
55 * The stride is always non-zero for resources using TXQ.
58 LLVMBuildExtractElement(builder
, descriptor
,
60 stride
= LLVMBuildLShr(builder
, stride
,
61 LLVMConstInt(ctx
->i32
, 16, 0), "");
62 stride
= LLVMBuildAnd(builder
, stride
,
63 LLVMConstInt(ctx
->i32
, 0x3FFF, 0), "");
65 size
= LLVMBuildUDiv(builder
, size
, stride
, "");
72 shader_buffer_fetch_rsrc(struct si_shader_context
*ctx
,
73 const struct tgsi_full_src_register
*reg
,
78 if (!reg
->Register
.Indirect
) {
79 index
= LLVMConstInt(ctx
->i32
, reg
->Register
.Index
, false);
81 index
= si_get_indirect_index(ctx
, ®
->Indirect
,
82 1, reg
->Register
.Index
);
86 return ctx
->abi
.load_ubo(&ctx
->abi
, index
);
88 return ctx
->abi
.load_ssbo(&ctx
->abi
, index
, false);
91 static enum ac_image_dim
92 ac_texture_dim_from_tgsi_target(struct si_screen
*screen
, enum tgsi_texture_type target
)
96 case TGSI_TEXTURE_SHADOW1D
:
97 if (screen
->info
.chip_class
>= GFX9
)
100 case TGSI_TEXTURE_2D
:
101 case TGSI_TEXTURE_SHADOW2D
:
102 case TGSI_TEXTURE_RECT
:
103 case TGSI_TEXTURE_SHADOWRECT
:
105 case TGSI_TEXTURE_3D
:
107 case TGSI_TEXTURE_CUBE
:
108 case TGSI_TEXTURE_SHADOWCUBE
:
109 case TGSI_TEXTURE_CUBE_ARRAY
:
110 case TGSI_TEXTURE_SHADOWCUBE_ARRAY
:
111 return ac_image_cube
;
112 case TGSI_TEXTURE_1D_ARRAY
:
113 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
114 if (screen
->info
.chip_class
>= GFX9
)
115 return ac_image_2darray
;
116 return ac_image_1darray
;
117 case TGSI_TEXTURE_2D_ARRAY
:
118 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
119 return ac_image_2darray
;
120 case TGSI_TEXTURE_2D_MSAA
:
121 return ac_image_2dmsaa
;
122 case TGSI_TEXTURE_2D_ARRAY_MSAA
:
123 return ac_image_2darraymsaa
;
125 unreachable("unhandled texture type");
129 static enum ac_image_dim
130 ac_image_dim_from_tgsi_target(struct si_screen
*screen
, enum tgsi_texture_type target
)
132 enum ac_image_dim dim
= ac_texture_dim_from_tgsi_target(screen
, target
);
134 /* Match the resource type set in the descriptor. */
135 if (dim
== ac_image_cube
||
136 (screen
->info
.chip_class
<= VI
&& dim
== ac_image_3d
))
137 dim
= ac_image_2darray
;
138 else if (target
== TGSI_TEXTURE_2D
&& screen
->info
.chip_class
>= GFX9
) {
139 /* When a single layer of a 3D texture is bound, the shader
140 * will refer to a 2D target, but the descriptor has a 3D type.
141 * Since the HW ignores BASE_ARRAY in this case, we need to
142 * send 3 coordinates. This doesn't hurt when the underlying
152 * Given a 256-bit resource descriptor, force the DCC enable bit to off.
154 * At least on Tonga, executing image stores on images with DCC enabled and
155 * non-trivial can eventually lead to lockups. This can occur when an
156 * application binds an image as read-only but then uses a shader that writes
157 * to it. The OpenGL spec allows almost arbitrarily bad behavior (including
158 * program termination) in this case, but it doesn't cost much to be a bit
159 * nicer: disabling DCC in the shader still leads to undefined results but
162 static LLVMValueRef
force_dcc_off(struct si_shader_context
*ctx
,
165 if (ctx
->screen
->info
.chip_class
<= CIK
) {
168 LLVMValueRef i32_6
= LLVMConstInt(ctx
->i32
, 6, 0);
169 LLVMValueRef i32_C
= LLVMConstInt(ctx
->i32
, C_008F28_COMPRESSION_EN
, 0);
172 tmp
= LLVMBuildExtractElement(ctx
->ac
.builder
, rsrc
, i32_6
, "");
173 tmp
= LLVMBuildAnd(ctx
->ac
.builder
, tmp
, i32_C
, "");
174 return LLVMBuildInsertElement(ctx
->ac
.builder
, rsrc
, tmp
, i32_6
, "");
178 LLVMValueRef
si_load_image_desc(struct si_shader_context
*ctx
,
179 LLVMValueRef list
, LLVMValueRef index
,
180 enum ac_descriptor_type desc_type
, bool dcc_off
)
182 LLVMBuilderRef builder
= ctx
->ac
.builder
;
185 if (desc_type
== AC_DESC_BUFFER
) {
186 index
= LLVMBuildMul(builder
, index
,
187 LLVMConstInt(ctx
->i32
, 2, 0), "");
188 index
= LLVMBuildAdd(builder
, index
,
190 list
= LLVMBuildPointerCast(builder
, list
,
191 ac_array_in_const32_addr_space(ctx
->v4i32
), "");
193 assert(desc_type
== AC_DESC_IMAGE
);
196 rsrc
= ac_build_load_to_sgpr(&ctx
->ac
, list
, index
);
197 if (desc_type
== AC_DESC_IMAGE
&& dcc_off
)
198 rsrc
= force_dcc_off(ctx
, rsrc
);
203 * Load the resource descriptor for \p image.
207 struct lp_build_tgsi_context
*bld_base
,
208 const struct tgsi_full_src_register
*image
,
209 bool is_store
, unsigned target
,
212 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
213 LLVMValueRef rsrc_ptr
= LLVMGetParam(ctx
->main_fn
,
214 ctx
->param_samplers_and_images
);
216 bool dcc_off
= is_store
;
218 if (!image
->Register
.Indirect
) {
219 const struct tgsi_shader_info
*info
= bld_base
->info
;
220 unsigned images_writemask
= info
->images_store
|
223 index
= LLVMConstInt(ctx
->i32
,
224 si_get_image_slot(image
->Register
.Index
), 0);
226 if (images_writemask
& (1 << image
->Register
.Index
))
229 /* From the GL_ARB_shader_image_load_store extension spec:
231 * If a shader performs an image load, store, or atomic
232 * operation using an image variable declared as an array,
233 * and if the index used to select an individual element is
234 * negative or greater than or equal to the size of the
235 * array, the results of the operation are undefined but may
236 * not lead to termination.
238 index
= si_get_bounded_indirect_index(ctx
, &image
->Indirect
,
239 image
->Register
.Index
,
241 index
= LLVMBuildSub(ctx
->ac
.builder
,
242 LLVMConstInt(ctx
->i32
, SI_NUM_IMAGES
- 1, 0),
246 if (image
->Register
.File
!= TGSI_FILE_IMAGE
) {
247 /* Bindless descriptors are accessible from a different pair of
250 rsrc_ptr
= LLVMGetParam(ctx
->main_fn
,
251 ctx
->param_bindless_samplers_and_images
);
252 index
= lp_build_emit_fetch_src(bld_base
, image
,
253 TGSI_TYPE_UNSIGNED
, 0);
255 /* For simplicity, bindless image descriptors use fixed
256 * 16-dword slots for now.
258 index
= LLVMBuildMul(ctx
->ac
.builder
, index
,
259 LLVMConstInt(ctx
->i32
, 2, 0), "");
262 *rsrc
= si_load_image_desc(ctx
, rsrc_ptr
, index
,
263 target
== TGSI_TEXTURE_BUFFER
? AC_DESC_BUFFER
: AC_DESC_IMAGE
,
267 static void image_fetch_coords(
268 struct lp_build_tgsi_context
*bld_base
,
269 const struct tgsi_full_instruction
*inst
,
270 unsigned src
, LLVMValueRef desc
,
271 LLVMValueRef
*coords
)
273 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
274 LLVMBuilderRef builder
= ctx
->ac
.builder
;
275 unsigned target
= inst
->Memory
.Texture
;
276 unsigned num_coords
= tgsi_util_get_texture_coord_dim(target
);
280 if (target
== TGSI_TEXTURE_2D_MSAA
||
281 target
== TGSI_TEXTURE_2D_ARRAY_MSAA
) {
282 /* Need the sample index as well. */
286 for (chan
= 0; chan
< num_coords
; ++chan
) {
287 tmp
= lp_build_emit_fetch(bld_base
, inst
, src
, chan
);
288 tmp
= ac_to_integer(&ctx
->ac
, tmp
);
292 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
293 /* 1D textures are allocated and used as 2D on GFX9. */
294 if (target
== TGSI_TEXTURE_1D
) {
295 coords
[1] = ctx
->i32_0
;
296 } else if (target
== TGSI_TEXTURE_1D_ARRAY
) {
297 coords
[2] = coords
[1];
298 coords
[1] = ctx
->i32_0
;
299 } else if (target
== TGSI_TEXTURE_2D
) {
300 /* The hw can't bind a slice of a 3D image as a 2D
301 * image, because it ignores BASE_ARRAY if the target
302 * is 3D. The workaround is to read BASE_ARRAY and set
303 * it as the 3rd address operand for all 2D images.
305 LLVMValueRef first_layer
, const5
, mask
;
307 const5
= LLVMConstInt(ctx
->i32
, 5, 0);
308 mask
= LLVMConstInt(ctx
->i32
, S_008F24_BASE_ARRAY(~0), 0);
309 first_layer
= LLVMBuildExtractElement(builder
, desc
, const5
, "");
310 first_layer
= LLVMBuildAnd(builder
, first_layer
, mask
, "");
312 coords
[2] = first_layer
;
318 * Append the resource and indexing arguments for buffer intrinsics.
320 * \param rsrc the v4i32 buffer resource
321 * \param index index into the buffer (stride-based)
322 * \param offset byte offset into the buffer
324 static void buffer_append_args(
325 struct si_shader_context
*ctx
,
326 struct lp_build_emit_data
*emit_data
,
333 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
334 LLVMValueRef i1false
= LLVMConstInt(ctx
->i1
, 0, 0);
335 LLVMValueRef i1true
= LLVMConstInt(ctx
->i1
, 1, 0);
337 emit_data
->args
[emit_data
->arg_count
++] = rsrc
;
338 emit_data
->args
[emit_data
->arg_count
++] = index
; /* vindex */
339 emit_data
->args
[emit_data
->arg_count
++] = offset
; /* voffset */
341 emit_data
->args
[emit_data
->arg_count
++] =
343 inst
->Memory
.Qualifier
& (TGSI_MEMORY_COHERENT
| TGSI_MEMORY_VOLATILE
) ?
344 i1true
: i1false
; /* glc */
346 emit_data
->args
[emit_data
->arg_count
++] = i1false
; /* slc */
349 static void load_fetch_args(
350 struct lp_build_tgsi_context
* bld_base
,
351 struct lp_build_emit_data
* emit_data
)
353 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
354 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
355 unsigned target
= inst
->Memory
.Texture
;
358 emit_data
->dst_type
= ctx
->v4f32
;
360 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
||
361 inst
->Src
[0].Register
.File
== TGSI_FILE_CONSTBUF
) {
365 bool ubo
= inst
->Src
[0].Register
.File
== TGSI_FILE_CONSTBUF
;
366 rsrc
= shader_buffer_fetch_rsrc(ctx
, &inst
->Src
[0], ubo
);
368 tmp
= lp_build_emit_fetch(bld_base
, inst
, 1, 0);
369 offset
= ac_to_integer(&ctx
->ac
, tmp
);
371 buffer_append_args(ctx
, emit_data
, rsrc
, ctx
->i32_0
,
372 offset
, false, false);
373 } else if (inst
->Src
[0].Register
.File
== TGSI_FILE_IMAGE
||
374 tgsi_is_bindless_image_file(inst
->Src
[0].Register
.File
)) {
375 image_fetch_rsrc(bld_base
, &inst
->Src
[0], false, target
, &rsrc
);
376 image_fetch_coords(bld_base
, inst
, 1, rsrc
, &emit_data
->args
[1]);
378 if (target
== TGSI_TEXTURE_BUFFER
) {
379 buffer_append_args(ctx
, emit_data
, rsrc
, emit_data
->args
[1],
380 ctx
->i32_0
, false, false);
382 emit_data
->args
[0] = rsrc
;
387 static void load_emit_buffer(struct si_shader_context
*ctx
,
388 struct lp_build_emit_data
*emit_data
,
389 bool can_speculate
, bool allow_smem
)
391 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
392 uint writemask
= inst
->Dst
[0].Register
.WriteMask
;
393 uint count
= util_last_bit(writemask
);
394 LLVMValueRef
*args
= emit_data
->args
;
396 /* Don't use SMEM for shader buffer loads, because LLVM doesn't
397 * select SMEM for SI.load.const with a non-constant offset, and
398 * constant offsets practically don't exist with shader buffers.
400 * Also, SI.load.const doesn't use inst_offset when it's lowered
401 * to VMEM, so we just end up with more VALU instructions in the end
404 * TODO: Remove this line once LLVM can select SMEM with a non-constant
405 * offset, and can derive inst_offset when VMEM is selected.
406 * After that, si_memory_barrier should invalidate sL1 for shader
410 assert(LLVMConstIntGetZExtValue(args
[1]) == 0); /* vindex */
411 emit_data
->output
[emit_data
->chan
] =
412 ac_build_buffer_load(&ctx
->ac
, args
[0], count
, NULL
,
414 LLVMConstIntGetZExtValue(args
[3]),
415 LLVMConstIntGetZExtValue(args
[4]),
416 can_speculate
, allow_smem
);
419 static LLVMValueRef
get_memory_ptr(struct si_shader_context
*ctx
,
420 const struct tgsi_full_instruction
*inst
,
421 LLVMTypeRef type
, int arg
)
423 LLVMBuilderRef builder
= ctx
->ac
.builder
;
424 LLVMValueRef offset
, ptr
;
427 offset
= lp_build_emit_fetch(&ctx
->bld_base
, inst
, arg
, 0);
428 offset
= ac_to_integer(&ctx
->ac
, offset
);
431 ptr
= LLVMBuildGEP(builder
, ptr
, &offset
, 1, "");
432 addr_space
= LLVMGetPointerAddressSpace(LLVMTypeOf(ptr
));
433 ptr
= LLVMBuildBitCast(builder
, ptr
, LLVMPointerType(type
, addr_space
), "");
438 static void load_emit_memory(
439 struct si_shader_context
*ctx
,
440 struct lp_build_emit_data
*emit_data
)
442 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
443 unsigned writemask
= inst
->Dst
[0].Register
.WriteMask
;
444 LLVMValueRef channels
[4], ptr
, derived_ptr
, index
;
447 ptr
= get_memory_ptr(ctx
, inst
, ctx
->f32
, 1);
449 for (chan
= 0; chan
< 4; ++chan
) {
450 if (!(writemask
& (1 << chan
))) {
451 channels
[chan
] = LLVMGetUndef(ctx
->f32
);
455 index
= LLVMConstInt(ctx
->i32
, chan
, 0);
456 derived_ptr
= LLVMBuildGEP(ctx
->ac
.builder
, ptr
, &index
, 1, "");
457 channels
[chan
] = LLVMBuildLoad(ctx
->ac
.builder
, derived_ptr
, "");
459 emit_data
->output
[emit_data
->chan
] = ac_build_gather_values(&ctx
->ac
, channels
, 4);
463 * Return true if the memory accessed by a LOAD or STORE instruction is
464 * read-only or write-only, respectively.
466 * \param shader_buffers_reverse_access_mask
467 * For LOAD, set this to (store | atomic) slot usage in the shader.
468 * For STORE, set this to (load | atomic) slot usage in the shader.
469 * \param images_reverse_access_mask Same as above, but for images.
471 static bool is_oneway_access_only(const struct tgsi_full_instruction
*inst
,
472 const struct tgsi_shader_info
*info
,
473 unsigned shader_buffers_reverse_access_mask
,
474 unsigned images_reverse_access_mask
)
476 /* RESTRICT means NOALIAS.
477 * If there are no writes, we can assume the accessed memory is read-only.
478 * If there are no reads, we can assume the accessed memory is write-only.
480 if (inst
->Memory
.Qualifier
& TGSI_MEMORY_RESTRICT
) {
481 unsigned reverse_access_mask
;
483 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
) {
484 reverse_access_mask
= shader_buffers_reverse_access_mask
;
485 } else if (inst
->Memory
.Texture
== TGSI_TEXTURE_BUFFER
) {
486 reverse_access_mask
= info
->images_buffers
&
487 images_reverse_access_mask
;
489 reverse_access_mask
= ~info
->images_buffers
&
490 images_reverse_access_mask
;
493 if (inst
->Src
[0].Register
.Indirect
) {
494 if (!reverse_access_mask
)
497 if (!(reverse_access_mask
&
498 (1u << inst
->Src
[0].Register
.Index
)))
503 /* If there are no buffer writes (for both shader buffers & image
504 * buffers), it implies that buffer memory is read-only.
505 * If there are no buffer reads (for both shader buffers & image
506 * buffers), it implies that buffer memory is write-only.
508 * Same for the case when there are no writes/reads for non-buffer
511 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
||
512 (inst
->Memory
.Texture
== TGSI_TEXTURE_BUFFER
&&
513 (inst
->Src
[0].Register
.File
== TGSI_FILE_IMAGE
||
514 tgsi_is_bindless_image_file(inst
->Src
[0].Register
.File
)))) {
515 if (!shader_buffers_reverse_access_mask
&&
516 !(info
->images_buffers
& images_reverse_access_mask
))
519 if (!(~info
->images_buffers
& images_reverse_access_mask
))
525 static void load_emit(
526 const struct lp_build_tgsi_action
*action
,
527 struct lp_build_tgsi_context
*bld_base
,
528 struct lp_build_emit_data
*emit_data
)
530 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
531 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
532 const struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
533 bool can_speculate
= false;
535 if (inst
->Src
[0].Register
.File
== TGSI_FILE_MEMORY
) {
536 load_emit_memory(ctx
, emit_data
);
540 if (inst
->Src
[0].Register
.File
== TGSI_FILE_CONSTBUF
) {
541 load_emit_buffer(ctx
, emit_data
, true, true);
545 if (inst
->Memory
.Qualifier
& TGSI_MEMORY_VOLATILE
)
546 ac_build_waitcnt(&ctx
->ac
, VM_CNT
);
548 can_speculate
= !(inst
->Memory
.Qualifier
& TGSI_MEMORY_VOLATILE
) &&
549 is_oneway_access_only(inst
, info
,
550 info
->shader_buffers_store
|
551 info
->shader_buffers_atomic
,
553 info
->images_atomic
);
555 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
) {
556 load_emit_buffer(ctx
, emit_data
, can_speculate
, false);
560 if (inst
->Memory
.Texture
== TGSI_TEXTURE_BUFFER
) {
561 unsigned num_channels
= util_last_bit(inst
->Dst
[0].Register
.WriteMask
);
562 LLVMValueRef result
=
563 ac_build_buffer_load_format(&ctx
->ac
,
568 LLVMConstIntGetZExtValue(emit_data
->args
[3]),
570 emit_data
->output
[emit_data
->chan
] =
571 ac_build_expand_to_vec4(&ctx
->ac
, result
, num_channels
);
573 struct ac_image_args args
= {};
574 args
.opcode
= ac_image_load
;
575 args
.resource
= emit_data
->args
[0];
576 memcpy(args
.coords
, &emit_data
->args
[1], sizeof(args
.coords
));
577 args
.dim
= ac_image_dim_from_tgsi_target(ctx
->screen
, inst
->Memory
.Texture
);
578 if (inst
->Memory
.Qualifier
& (TGSI_MEMORY_COHERENT
| TGSI_MEMORY_VOLATILE
))
579 args
.cache_policy
= ac_glc
;
580 args
.attributes
= ac_get_load_intr_attribs(can_speculate
);
583 emit_data
->output
[emit_data
->chan
] =
584 ac_build_image_opcode(&ctx
->ac
, &args
);
588 static void store_fetch_args(
589 struct lp_build_tgsi_context
* bld_base
,
590 struct lp_build_emit_data
* emit_data
)
592 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
593 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
594 struct tgsi_full_src_register memory
;
595 LLVMValueRef chans
[4];
600 emit_data
->dst_type
= ctx
->voidt
;
602 for (chan
= 0; chan
< 4; ++chan
) {
603 chans
[chan
] = lp_build_emit_fetch(bld_base
, inst
, 1, chan
);
605 data
= ac_build_gather_values(&ctx
->ac
, chans
, 4);
607 emit_data
->args
[emit_data
->arg_count
++] = data
;
609 memory
= tgsi_full_src_register_from_dst(&inst
->Dst
[0]);
611 if (inst
->Dst
[0].Register
.File
== TGSI_FILE_BUFFER
) {
615 rsrc
= shader_buffer_fetch_rsrc(ctx
, &memory
, false);
617 tmp
= lp_build_emit_fetch(bld_base
, inst
, 0, 0);
618 offset
= ac_to_integer(&ctx
->ac
, tmp
);
620 buffer_append_args(ctx
, emit_data
, rsrc
, ctx
->i32_0
,
621 offset
, false, false);
622 } else if (inst
->Dst
[0].Register
.File
== TGSI_FILE_IMAGE
||
623 tgsi_is_bindless_image_file(inst
->Dst
[0].Register
.File
)) {
624 unsigned target
= inst
->Memory
.Texture
;
626 /* 8bit/16bit TC L1 write corruption bug on SI.
627 * All store opcodes not aligned to a dword are affected.
629 * The only way to get unaligned stores in radeonsi is through
632 bool force_glc
= ctx
->screen
->info
.chip_class
== SI
;
634 image_fetch_rsrc(bld_base
, &memory
, true, target
, &rsrc
);
635 image_fetch_coords(bld_base
, inst
, 0, rsrc
, &emit_data
->args
[2]);
637 if (target
== TGSI_TEXTURE_BUFFER
) {
638 buffer_append_args(ctx
, emit_data
, rsrc
, emit_data
->args
[2],
639 ctx
->i32_0
, false, force_glc
);
641 emit_data
->args
[1] = rsrc
;
646 static void store_emit_buffer(
647 struct si_shader_context
*ctx
,
648 struct lp_build_emit_data
*emit_data
,
649 bool writeonly_memory
)
651 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
652 LLVMBuilderRef builder
= ctx
->ac
.builder
;
653 LLVMValueRef base_data
= emit_data
->args
[0];
654 LLVMValueRef base_offset
= emit_data
->args
[3];
655 unsigned writemask
= inst
->Dst
[0].Register
.WriteMask
;
659 const char *intrinsic_name
;
664 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
666 /* Due to an LLVM limitation, split 3-element writes
667 * into a 2-element and a 1-element write. */
669 writemask
|= 1 << (start
+ 2);
675 intrinsic_name
= "llvm.amdgcn.buffer.store.v4f32";
676 } else if (count
== 2) {
677 LLVMTypeRef v2f32
= LLVMVectorType(ctx
->f32
, 2);
679 tmp
= LLVMBuildExtractElement(
681 LLVMConstInt(ctx
->i32
, start
, 0), "");
682 data
= LLVMBuildInsertElement(
683 builder
, LLVMGetUndef(v2f32
), tmp
,
686 tmp
= LLVMBuildExtractElement(
688 LLVMConstInt(ctx
->i32
, start
+ 1, 0), "");
689 data
= LLVMBuildInsertElement(
690 builder
, data
, tmp
, ctx
->i32_1
, "");
692 intrinsic_name
= "llvm.amdgcn.buffer.store.v2f32";
695 data
= LLVMBuildExtractElement(
697 LLVMConstInt(ctx
->i32
, start
, 0), "");
698 intrinsic_name
= "llvm.amdgcn.buffer.store.f32";
701 offset
= base_offset
;
703 offset
= LLVMBuildAdd(
705 LLVMConstInt(ctx
->i32
, start
* 4, 0), "");
708 emit_data
->args
[0] = data
;
709 emit_data
->args
[3] = offset
;
712 &ctx
->ac
, intrinsic_name
, emit_data
->dst_type
,
713 emit_data
->args
, emit_data
->arg_count
,
714 ac_get_store_intr_attribs(writeonly_memory
));
718 static void store_emit_memory(
719 struct si_shader_context
*ctx
,
720 struct lp_build_emit_data
*emit_data
)
722 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
723 LLVMBuilderRef builder
= ctx
->ac
.builder
;
724 unsigned writemask
= inst
->Dst
[0].Register
.WriteMask
;
725 LLVMValueRef ptr
, derived_ptr
, data
, index
;
728 ptr
= get_memory_ptr(ctx
, inst
, ctx
->f32
, 0);
730 for (chan
= 0; chan
< 4; ++chan
) {
731 if (!(writemask
& (1 << chan
))) {
734 data
= lp_build_emit_fetch(&ctx
->bld_base
, inst
, 1, chan
);
735 index
= LLVMConstInt(ctx
->i32
, chan
, 0);
736 derived_ptr
= LLVMBuildGEP(builder
, ptr
, &index
, 1, "");
737 LLVMBuildStore(builder
, data
, derived_ptr
);
741 static void store_emit(
742 const struct lp_build_tgsi_action
*action
,
743 struct lp_build_tgsi_context
*bld_base
,
744 struct lp_build_emit_data
*emit_data
)
746 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
747 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
748 const struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
749 unsigned target
= inst
->Memory
.Texture
;
750 bool writeonly_memory
= false;
752 if (inst
->Dst
[0].Register
.File
== TGSI_FILE_MEMORY
) {
753 store_emit_memory(ctx
, emit_data
);
757 if (inst
->Memory
.Qualifier
& TGSI_MEMORY_VOLATILE
)
758 ac_build_waitcnt(&ctx
->ac
, VM_CNT
);
760 writeonly_memory
= is_oneway_access_only(inst
, info
,
761 info
->shader_buffers_load
|
762 info
->shader_buffers_atomic
,
764 info
->images_atomic
);
766 if (inst
->Dst
[0].Register
.File
== TGSI_FILE_BUFFER
) {
767 store_emit_buffer(ctx
, emit_data
, writeonly_memory
);
771 if (target
== TGSI_TEXTURE_BUFFER
) {
772 emit_data
->output
[emit_data
->chan
] = ac_build_intrinsic(
773 &ctx
->ac
, "llvm.amdgcn.buffer.store.format.v4f32",
774 emit_data
->dst_type
, emit_data
->args
,
775 emit_data
->arg_count
,
776 ac_get_store_intr_attribs(writeonly_memory
));
778 struct ac_image_args args
= {};
779 args
.opcode
= ac_image_store
;
780 args
.data
[0] = emit_data
->args
[0];
781 args
.resource
= emit_data
->args
[1];
782 memcpy(args
.coords
, &emit_data
->args
[2], sizeof(args
.coords
));
783 args
.dim
= ac_image_dim_from_tgsi_target(ctx
->screen
, inst
->Memory
.Texture
);
784 args
.attributes
= ac_get_store_intr_attribs(writeonly_memory
);
787 /* Workaround for 8bit/16bit TC L1 write corruption bug on SI.
788 * All store opcodes not aligned to a dword are affected.
790 bool force_glc
= ctx
->screen
->info
.chip_class
== SI
;
792 inst
->Memory
.Qualifier
& (TGSI_MEMORY_COHERENT
| TGSI_MEMORY_VOLATILE
))
793 args
.cache_policy
= ac_glc
;
795 emit_data
->output
[emit_data
->chan
] =
796 ac_build_image_opcode(&ctx
->ac
, &args
);
800 static void atomic_fetch_args(
801 struct lp_build_tgsi_context
* bld_base
,
802 struct lp_build_emit_data
* emit_data
)
804 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
805 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
806 LLVMValueRef data1
, data2
;
810 emit_data
->dst_type
= ctx
->f32
;
812 tmp
= lp_build_emit_fetch(bld_base
, inst
, 2, 0);
813 data1
= ac_to_integer(&ctx
->ac
, tmp
);
815 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
) {
816 tmp
= lp_build_emit_fetch(bld_base
, inst
, 3, 0);
817 data2
= ac_to_integer(&ctx
->ac
, tmp
);
820 /* llvm.amdgcn.image/buffer.atomic.cmpswap reflect the hardware order
821 * of arguments, which is reversed relative to TGSI (and GLSL)
823 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
)
824 emit_data
->args
[emit_data
->arg_count
++] = data2
;
825 emit_data
->args
[emit_data
->arg_count
++] = data1
;
827 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
) {
830 rsrc
= shader_buffer_fetch_rsrc(ctx
, &inst
->Src
[0], false);
832 tmp
= lp_build_emit_fetch(bld_base
, inst
, 1, 0);
833 offset
= ac_to_integer(&ctx
->ac
, tmp
);
835 buffer_append_args(ctx
, emit_data
, rsrc
, ctx
->i32_0
,
836 offset
, true, false);
837 } else if (inst
->Src
[0].Register
.File
== TGSI_FILE_IMAGE
||
838 tgsi_is_bindless_image_file(inst
->Src
[0].Register
.File
)) {
839 unsigned target
= inst
->Memory
.Texture
;
841 image_fetch_rsrc(bld_base
, &inst
->Src
[0], true, target
, &rsrc
);
842 image_fetch_coords(bld_base
, inst
, 1, rsrc
,
843 &emit_data
->args
[emit_data
->arg_count
+ 1]);
845 if (target
== TGSI_TEXTURE_BUFFER
) {
846 buffer_append_args(ctx
, emit_data
, rsrc
,
847 emit_data
->args
[emit_data
->arg_count
+ 1],
848 ctx
->i32_0
, true, false);
850 emit_data
->args
[emit_data
->arg_count
] = rsrc
;
855 static void atomic_emit_memory(struct si_shader_context
*ctx
,
856 struct lp_build_emit_data
*emit_data
) {
857 LLVMBuilderRef builder
= ctx
->ac
.builder
;
858 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
859 LLVMValueRef ptr
, result
, arg
;
861 ptr
= get_memory_ptr(ctx
, inst
, ctx
->i32
, 1);
863 arg
= lp_build_emit_fetch(&ctx
->bld_base
, inst
, 2, 0);
864 arg
= ac_to_integer(&ctx
->ac
, arg
);
866 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
) {
867 LLVMValueRef new_data
;
868 new_data
= lp_build_emit_fetch(&ctx
->bld_base
,
871 new_data
= ac_to_integer(&ctx
->ac
, new_data
);
873 result
= LLVMBuildAtomicCmpXchg(builder
, ptr
, arg
, new_data
,
874 LLVMAtomicOrderingSequentiallyConsistent
,
875 LLVMAtomicOrderingSequentiallyConsistent
,
878 result
= LLVMBuildExtractValue(builder
, result
, 0, "");
880 LLVMAtomicRMWBinOp op
;
882 switch(inst
->Instruction
.Opcode
) {
883 case TGSI_OPCODE_ATOMUADD
:
884 op
= LLVMAtomicRMWBinOpAdd
;
886 case TGSI_OPCODE_ATOMXCHG
:
887 op
= LLVMAtomicRMWBinOpXchg
;
889 case TGSI_OPCODE_ATOMAND
:
890 op
= LLVMAtomicRMWBinOpAnd
;
892 case TGSI_OPCODE_ATOMOR
:
893 op
= LLVMAtomicRMWBinOpOr
;
895 case TGSI_OPCODE_ATOMXOR
:
896 op
= LLVMAtomicRMWBinOpXor
;
898 case TGSI_OPCODE_ATOMUMIN
:
899 op
= LLVMAtomicRMWBinOpUMin
;
901 case TGSI_OPCODE_ATOMUMAX
:
902 op
= LLVMAtomicRMWBinOpUMax
;
904 case TGSI_OPCODE_ATOMIMIN
:
905 op
= LLVMAtomicRMWBinOpMin
;
907 case TGSI_OPCODE_ATOMIMAX
:
908 op
= LLVMAtomicRMWBinOpMax
;
911 unreachable("unknown atomic opcode");
914 result
= LLVMBuildAtomicRMW(builder
, op
, ptr
, arg
,
915 LLVMAtomicOrderingSequentiallyConsistent
,
918 emit_data
->output
[emit_data
->chan
] = LLVMBuildBitCast(builder
, result
, emit_data
->dst_type
, "");
921 static void atomic_emit(
922 const struct lp_build_tgsi_action
*action
,
923 struct lp_build_tgsi_context
*bld_base
,
924 struct lp_build_emit_data
*emit_data
)
926 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
927 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
930 if (inst
->Src
[0].Register
.File
== TGSI_FILE_MEMORY
) {
931 atomic_emit_memory(ctx
, emit_data
);
935 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
||
936 inst
->Memory
.Texture
== TGSI_TEXTURE_BUFFER
) {
937 char intrinsic_name
[40];
938 snprintf(intrinsic_name
, sizeof(intrinsic_name
),
939 "llvm.amdgcn.buffer.atomic.%s", action
->intr_name
);
940 tmp
= ac_build_intrinsic(
941 &ctx
->ac
, intrinsic_name
, ctx
->i32
,
942 emit_data
->args
, emit_data
->arg_count
, 0);
943 emit_data
->output
[emit_data
->chan
] = ac_to_float(&ctx
->ac
, tmp
);
945 unsigned num_data
= inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
? 2 : 1;
946 struct ac_image_args args
= {};
948 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
) {
949 args
.opcode
= ac_image_atomic_cmpswap
;
951 args
.opcode
= ac_image_atomic
;
952 switch (inst
->Instruction
.Opcode
) {
953 case TGSI_OPCODE_ATOMXCHG
: args
.atomic
= ac_atomic_swap
; break;
954 case TGSI_OPCODE_ATOMUADD
: args
.atomic
= ac_atomic_add
; break;
955 case TGSI_OPCODE_ATOMAND
: args
.atomic
= ac_atomic_and
; break;
956 case TGSI_OPCODE_ATOMOR
: args
.atomic
= ac_atomic_or
; break;
957 case TGSI_OPCODE_ATOMXOR
: args
.atomic
= ac_atomic_xor
; break;
958 case TGSI_OPCODE_ATOMUMIN
: args
.atomic
= ac_atomic_umin
; break;
959 case TGSI_OPCODE_ATOMUMAX
: args
.atomic
= ac_atomic_umax
; break;
960 case TGSI_OPCODE_ATOMIMIN
: args
.atomic
= ac_atomic_smin
; break;
961 case TGSI_OPCODE_ATOMIMAX
: args
.atomic
= ac_atomic_smax
; break;
962 default: unreachable("unhandled image atomic");
966 for (unsigned i
= 0; i
< num_data
; ++i
)
967 args
.data
[i
] = emit_data
->args
[i
];
969 args
.resource
= emit_data
->args
[num_data
];
970 memcpy(args
.coords
, &emit_data
->args
[num_data
+ 1], sizeof(args
.coords
));
971 args
.dim
= ac_image_dim_from_tgsi_target(ctx
->screen
, inst
->Memory
.Texture
);
973 emit_data
->output
[emit_data
->chan
] =
974 ac_to_float(&ctx
->ac
, ac_build_image_opcode(&ctx
->ac
, &args
));
978 static void set_tex_fetch_args(struct si_shader_context
*ctx
,
979 struct lp_build_emit_data
*emit_data
,
980 struct ac_image_args
*args
,
983 args
->dim
= ac_texture_dim_from_tgsi_target(ctx
->screen
, target
);
984 args
->unorm
= target
== TGSI_TEXTURE_RECT
||
985 target
== TGSI_TEXTURE_SHADOWRECT
;
987 /* Ugly, but we seem to have no other choice right now. */
988 STATIC_ASSERT(sizeof(*args
) <= sizeof(emit_data
->args
));
989 memcpy(emit_data
->args
, args
, sizeof(*args
));
992 static LLVMValueRef
fix_resinfo(struct si_shader_context
*ctx
,
993 unsigned target
, LLVMValueRef out
)
995 LLVMBuilderRef builder
= ctx
->ac
.builder
;
997 /* 1D textures are allocated and used as 2D on GFX9. */
998 if (ctx
->screen
->info
.chip_class
>= GFX9
&&
999 (target
== TGSI_TEXTURE_1D_ARRAY
||
1000 target
== TGSI_TEXTURE_SHADOW1D_ARRAY
)) {
1001 LLVMValueRef layers
=
1002 LLVMBuildExtractElement(builder
, out
,
1003 LLVMConstInt(ctx
->i32
, 2, 0), "");
1004 out
= LLVMBuildInsertElement(builder
, out
, layers
,
1008 /* Divide the number of layers by 6 to get the number of cubes. */
1009 if (target
== TGSI_TEXTURE_CUBE_ARRAY
||
1010 target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
1011 LLVMValueRef imm2
= LLVMConstInt(ctx
->i32
, 2, 0);
1013 LLVMValueRef z
= LLVMBuildExtractElement(builder
, out
, imm2
, "");
1014 z
= LLVMBuildSDiv(builder
, z
, LLVMConstInt(ctx
->i32
, 6, 0), "");
1016 out
= LLVMBuildInsertElement(builder
, out
, z
, imm2
, "");
1021 static void resq_fetch_args(
1022 struct lp_build_tgsi_context
* bld_base
,
1023 struct lp_build_emit_data
* emit_data
)
1025 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1026 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
1027 const struct tgsi_full_src_register
*reg
= &inst
->Src
[0];
1029 emit_data
->dst_type
= ctx
->v4i32
;
1031 if (reg
->Register
.File
== TGSI_FILE_BUFFER
) {
1032 emit_data
->args
[0] = shader_buffer_fetch_rsrc(ctx
, reg
, false);
1033 emit_data
->arg_count
= 1;
1034 } else if (inst
->Memory
.Texture
== TGSI_TEXTURE_BUFFER
) {
1035 image_fetch_rsrc(bld_base
, reg
, false, inst
->Memory
.Texture
,
1036 &emit_data
->args
[0]);
1037 emit_data
->arg_count
= 1;
1039 struct ac_image_args args
= {};
1040 unsigned image_target
;
1042 if (inst
->Memory
.Texture
== TGSI_TEXTURE_3D
)
1043 image_target
= TGSI_TEXTURE_2D_ARRAY
;
1045 image_target
= inst
->Memory
.Texture
;
1047 image_fetch_rsrc(bld_base
, reg
, false, inst
->Memory
.Texture
,
1049 args
.lod
= ctx
->i32_0
;
1051 set_tex_fetch_args(ctx
, emit_data
, &args
, image_target
);
1055 static void resq_emit(
1056 const struct lp_build_tgsi_action
*action
,
1057 struct lp_build_tgsi_context
*bld_base
,
1058 struct lp_build_emit_data
*emit_data
)
1060 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1061 LLVMBuilderRef builder
= ctx
->ac
.builder
;
1062 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
1065 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
) {
1066 out
= LLVMBuildExtractElement(builder
, emit_data
->args
[0],
1067 LLVMConstInt(ctx
->i32
, 2, 0), "");
1068 } else if (inst
->Memory
.Texture
== TGSI_TEXTURE_BUFFER
) {
1069 out
= get_buffer_size(bld_base
, emit_data
->args
[0]);
1071 struct ac_image_args args
;
1073 memcpy(&args
, emit_data
->args
, sizeof(args
)); /* ugly */
1074 args
.opcode
= ac_image_get_resinfo
;
1075 out
= ac_build_image_opcode(&ctx
->ac
, &args
);
1077 out
= fix_resinfo(ctx
, inst
->Memory
.Texture
, out
);
1080 emit_data
->output
[emit_data
->chan
] = out
;
1084 * Load an image view, fmask view. or sampler state descriptor.
1086 LLVMValueRef
si_load_sampler_desc(struct si_shader_context
*ctx
,
1087 LLVMValueRef list
, LLVMValueRef index
,
1088 enum ac_descriptor_type type
)
1090 LLVMBuilderRef builder
= ctx
->ac
.builder
;
1094 /* The image is at [0:7]. */
1095 index
= LLVMBuildMul(builder
, index
, LLVMConstInt(ctx
->i32
, 2, 0), "");
1097 case AC_DESC_BUFFER
:
1098 /* The buffer is in [4:7]. */
1099 index
= LLVMBuildMul(builder
, index
, LLVMConstInt(ctx
->i32
, 4, 0), "");
1100 index
= LLVMBuildAdd(builder
, index
, ctx
->i32_1
, "");
1101 list
= LLVMBuildPointerCast(builder
, list
,
1102 ac_array_in_const32_addr_space(ctx
->v4i32
), "");
1105 /* The FMASK is at [8:15]. */
1106 index
= LLVMBuildMul(builder
, index
, LLVMConstInt(ctx
->i32
, 2, 0), "");
1107 index
= LLVMBuildAdd(builder
, index
, ctx
->i32_1
, "");
1109 case AC_DESC_SAMPLER
:
1110 /* The sampler state is at [12:15]. */
1111 index
= LLVMBuildMul(builder
, index
, LLVMConstInt(ctx
->i32
, 4, 0), "");
1112 index
= LLVMBuildAdd(builder
, index
, LLVMConstInt(ctx
->i32
, 3, 0), "");
1113 list
= LLVMBuildPointerCast(builder
, list
,
1114 ac_array_in_const32_addr_space(ctx
->v4i32
), "");
1118 return ac_build_load_to_sgpr(&ctx
->ac
, list
, index
);
1121 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
1124 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
1125 * filtering manually. The driver sets img7 to a mask clearing
1126 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
1127 * s_and_b32 samp0, samp0, img7
1130 * The ANISO_OVERRIDE sampler field enables this fix in TA.
1132 static LLVMValueRef
sici_fix_sampler_aniso(struct si_shader_context
*ctx
,
1133 LLVMValueRef res
, LLVMValueRef samp
)
1135 LLVMValueRef img7
, samp0
;
1137 if (ctx
->screen
->info
.chip_class
>= VI
)
1140 img7
= LLVMBuildExtractElement(ctx
->ac
.builder
, res
,
1141 LLVMConstInt(ctx
->i32
, 7, 0), "");
1142 samp0
= LLVMBuildExtractElement(ctx
->ac
.builder
, samp
,
1144 samp0
= LLVMBuildAnd(ctx
->ac
.builder
, samp0
, img7
, "");
1145 return LLVMBuildInsertElement(ctx
->ac
.builder
, samp
, samp0
,
1149 static void tex_fetch_ptrs(
1150 struct lp_build_tgsi_context
*bld_base
,
1151 struct lp_build_emit_data
*emit_data
,
1152 LLVMValueRef
*res_ptr
, LLVMValueRef
*samp_ptr
, LLVMValueRef
*fmask_ptr
)
1154 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1155 LLVMValueRef list
= LLVMGetParam(ctx
->main_fn
, ctx
->param_samplers_and_images
);
1156 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
1157 const struct tgsi_full_src_register
*reg
;
1158 unsigned target
= inst
->Texture
.Texture
;
1159 unsigned sampler_src
;
1162 sampler_src
= emit_data
->inst
->Instruction
.NumSrcRegs
- 1;
1163 reg
= &emit_data
->inst
->Src
[sampler_src
];
1165 if (reg
->Register
.Indirect
) {
1166 index
= si_get_bounded_indirect_index(ctx
,
1168 reg
->Register
.Index
,
1170 index
= LLVMBuildAdd(ctx
->ac
.builder
, index
,
1171 LLVMConstInt(ctx
->i32
, SI_NUM_IMAGES
/ 2, 0), "");
1173 index
= LLVMConstInt(ctx
->i32
,
1174 si_get_sampler_slot(reg
->Register
.Index
), 0);
1177 if (reg
->Register
.File
!= TGSI_FILE_SAMPLER
) {
1178 /* Bindless descriptors are accessible from a different pair of
1179 * user SGPR indices.
1181 list
= LLVMGetParam(ctx
->main_fn
,
1182 ctx
->param_bindless_samplers_and_images
);
1183 index
= lp_build_emit_fetch_src(bld_base
, reg
,
1184 TGSI_TYPE_UNSIGNED
, 0);
1187 if (target
== TGSI_TEXTURE_BUFFER
)
1188 *res_ptr
= si_load_sampler_desc(ctx
, list
, index
, AC_DESC_BUFFER
);
1190 *res_ptr
= si_load_sampler_desc(ctx
, list
, index
, AC_DESC_IMAGE
);
1197 if (target
== TGSI_TEXTURE_2D_MSAA
||
1198 target
== TGSI_TEXTURE_2D_ARRAY_MSAA
) {
1200 *fmask_ptr
= si_load_sampler_desc(ctx
, list
, index
,
1202 } else if (target
!= TGSI_TEXTURE_BUFFER
) {
1204 *samp_ptr
= si_load_sampler_desc(ctx
, list
, index
,
1206 *samp_ptr
= sici_fix_sampler_aniso(ctx
, *res_ptr
, *samp_ptr
);
1211 static void txq_fetch_args(
1212 struct lp_build_tgsi_context
*bld_base
,
1213 struct lp_build_emit_data
*emit_data
)
1215 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1216 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
1217 unsigned target
= inst
->Texture
.Texture
;
1218 struct ac_image_args args
= {};
1220 tex_fetch_ptrs(bld_base
, emit_data
, &args
.resource
, NULL
, NULL
);
1222 if (target
== TGSI_TEXTURE_BUFFER
) {
1223 /* Read the size from the buffer descriptor directly. */
1224 emit_data
->args
[0] = get_buffer_size(bld_base
, args
.resource
);
1228 /* Textures - set the mip level. */
1229 args
.lod
= lp_build_emit_fetch(bld_base
, inst
, 0, TGSI_CHAN_X
);
1232 set_tex_fetch_args(ctx
, emit_data
, &args
, target
);
1235 static void txq_emit(const struct lp_build_tgsi_action
*action
,
1236 struct lp_build_tgsi_context
*bld_base
,
1237 struct lp_build_emit_data
*emit_data
)
1239 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1240 struct ac_image_args args
;
1241 unsigned target
= emit_data
->inst
->Texture
.Texture
;
1243 if (target
== TGSI_TEXTURE_BUFFER
) {
1244 /* Just return the buffer size. */
1245 emit_data
->output
[emit_data
->chan
] = emit_data
->args
[0];
1249 memcpy(&args
, emit_data
->args
, sizeof(args
)); /* ugly */
1251 args
.opcode
= ac_image_get_resinfo
;
1252 LLVMValueRef result
= ac_build_image_opcode(&ctx
->ac
, &args
);
1254 emit_data
->output
[emit_data
->chan
] = fix_resinfo(ctx
, target
, result
);
1257 static void tex_fetch_args(
1258 struct lp_build_tgsi_context
*bld_base
,
1259 struct lp_build_emit_data
*emit_data
)
1261 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1262 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
1263 unsigned opcode
= inst
->Instruction
.Opcode
;
1264 unsigned target
= inst
->Texture
.Texture
;
1265 struct ac_image_args args
= {};
1266 int ref_pos
= tgsi_util_get_shadow_ref_src_index(target
);
1268 bool has_offset
= inst
->Texture
.NumOffsets
> 0;
1269 LLVMValueRef fmask_ptr
= NULL
;
1271 tex_fetch_ptrs(bld_base
, emit_data
, &args
.resource
, &args
.sampler
, &fmask_ptr
);
1273 if (target
== TGSI_TEXTURE_BUFFER
) {
1274 emit_data
->dst_type
= ctx
->v4f32
;
1275 emit_data
->args
[0] = args
.resource
;
1276 emit_data
->args
[1] = ctx
->i32_0
;
1277 emit_data
->args
[2] = lp_build_emit_fetch(bld_base
, emit_data
->inst
, 0, TGSI_CHAN_X
);
1278 emit_data
->arg_count
= 3;
1282 /* Fetch and project texture coordinates */
1283 args
.coords
[3] = lp_build_emit_fetch(bld_base
, emit_data
->inst
, 0, TGSI_CHAN_W
);
1284 for (chan
= 0; chan
< 3; chan
++) {
1285 args
.coords
[chan
] = lp_build_emit_fetch(bld_base
,
1288 if (opcode
== TGSI_OPCODE_TXP
)
1289 args
.coords
[chan
] = ac_build_fdiv(&ctx
->ac
,
1290 args
.coords
[chan
], args
.coords
[3]);
1293 if (opcode
== TGSI_OPCODE_TXP
)
1294 args
.coords
[3] = ctx
->ac
.f32_1
;
1298 opcode
!= TGSI_OPCODE_TXF
&&
1299 opcode
!= TGSI_OPCODE_TXF_LZ
) {
1300 /* The offsets are six-bit signed integers packed like this:
1301 * X=[5:0], Y=[13:8], and Z=[21:16].
1303 LLVMValueRef offset
[3], pack
;
1305 assert(inst
->Texture
.NumOffsets
== 1);
1307 for (chan
= 0; chan
< 3; chan
++) {
1308 offset
[chan
] = lp_build_emit_fetch_texoffset(bld_base
,
1309 emit_data
->inst
, 0, chan
);
1310 offset
[chan
] = LLVMBuildAnd(ctx
->ac
.builder
, offset
[chan
],
1311 LLVMConstInt(ctx
->i32
, 0x3f, 0), "");
1313 offset
[chan
] = LLVMBuildShl(ctx
->ac
.builder
, offset
[chan
],
1314 LLVMConstInt(ctx
->i32
, chan
*8, 0), "");
1317 pack
= LLVMBuildOr(ctx
->ac
.builder
, offset
[0], offset
[1], "");
1318 pack
= LLVMBuildOr(ctx
->ac
.builder
, pack
, offset
[2], "");
1322 /* Pack LOD bias value */
1323 if (opcode
== TGSI_OPCODE_TXB
)
1324 args
.bias
= args
.coords
[3];
1325 if (opcode
== TGSI_OPCODE_TXB2
)
1326 args
.bias
= lp_build_emit_fetch(bld_base
, inst
, 1, TGSI_CHAN_X
);
1328 /* Pack depth comparison value */
1329 if (tgsi_is_shadow_target(target
) && opcode
!= TGSI_OPCODE_LODQ
) {
1332 if (target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
1333 z
= lp_build_emit_fetch(bld_base
, inst
, 1, TGSI_CHAN_X
);
1335 assert(ref_pos
>= 0);
1336 z
= args
.coords
[ref_pos
];
1339 /* Section 8.23.1 (Depth Texture Comparison Mode) of the
1340 * OpenGL 4.5 spec says:
1342 * "If the texture’s internal format indicates a fixed-point
1343 * depth texture, then D_t and D_ref are clamped to the
1344 * range [0, 1]; otherwise no clamping is performed."
1346 * TC-compatible HTILE promotes Z16 and Z24 to Z32_FLOAT,
1347 * so the depth comparison value isn't clamped for Z16 and
1348 * Z24 anymore. Do it manually here.
1350 if (ctx
->screen
->info
.chip_class
>= VI
) {
1351 LLVMValueRef upgraded
;
1352 LLVMValueRef clamped
;
1353 upgraded
= LLVMBuildExtractElement(ctx
->ac
.builder
, args
.sampler
,
1354 LLVMConstInt(ctx
->i32
, 3, false), "");
1355 upgraded
= LLVMBuildLShr(ctx
->ac
.builder
, upgraded
,
1356 LLVMConstInt(ctx
->i32
, 29, false), "");
1357 upgraded
= LLVMBuildTrunc(ctx
->ac
.builder
, upgraded
, ctx
->i1
, "");
1358 clamped
= ac_build_clamp(&ctx
->ac
, z
);
1359 z
= LLVMBuildSelect(ctx
->ac
.builder
, upgraded
, clamped
, z
, "");
1365 /* Pack user derivatives */
1366 if (opcode
== TGSI_OPCODE_TXD
) {
1367 int param
, num_src_deriv_channels
, num_dst_deriv_channels
;
1370 case TGSI_TEXTURE_3D
:
1371 num_src_deriv_channels
= 3;
1372 num_dst_deriv_channels
= 3;
1374 case TGSI_TEXTURE_2D
:
1375 case TGSI_TEXTURE_SHADOW2D
:
1376 case TGSI_TEXTURE_RECT
:
1377 case TGSI_TEXTURE_SHADOWRECT
:
1378 case TGSI_TEXTURE_2D_ARRAY
:
1379 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
1380 num_src_deriv_channels
= 2;
1381 num_dst_deriv_channels
= 2;
1383 case TGSI_TEXTURE_CUBE
:
1384 case TGSI_TEXTURE_SHADOWCUBE
:
1385 case TGSI_TEXTURE_CUBE_ARRAY
:
1386 case TGSI_TEXTURE_SHADOWCUBE_ARRAY
:
1387 /* Cube derivatives will be converted to 2D. */
1388 num_src_deriv_channels
= 3;
1389 num_dst_deriv_channels
= 3;
1391 case TGSI_TEXTURE_1D
:
1392 case TGSI_TEXTURE_SHADOW1D
:
1393 case TGSI_TEXTURE_1D_ARRAY
:
1394 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
1395 num_src_deriv_channels
= 1;
1397 /* 1D textures are allocated and used as 2D on GFX9. */
1398 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
1399 num_dst_deriv_channels
= 2;
1401 num_dst_deriv_channels
= 1;
1405 unreachable("invalid target");
1408 for (param
= 0; param
< 2; param
++) {
1409 for (chan
= 0; chan
< num_src_deriv_channels
; chan
++)
1410 args
.derivs
[param
* num_dst_deriv_channels
+ chan
] =
1411 lp_build_emit_fetch(bld_base
, inst
, param
+1, chan
);
1413 /* Fill in the rest with zeros. */
1414 for (chan
= num_src_deriv_channels
;
1415 chan
< num_dst_deriv_channels
; chan
++)
1416 args
.derivs
[param
* num_dst_deriv_channels
+ chan
] =
1421 if (target
== TGSI_TEXTURE_CUBE
||
1422 target
== TGSI_TEXTURE_CUBE_ARRAY
||
1423 target
== TGSI_TEXTURE_SHADOWCUBE
||
1424 target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
1425 ac_prepare_cube_coords(&ctx
->ac
,
1426 opcode
== TGSI_OPCODE_TXD
,
1427 target
== TGSI_TEXTURE_CUBE_ARRAY
||
1428 target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
,
1429 opcode
== TGSI_OPCODE_LODQ
,
1430 args
.coords
, args
.derivs
);
1431 } else if (tgsi_is_array_sampler(target
) &&
1432 opcode
!= TGSI_OPCODE_TXF
&&
1433 opcode
!= TGSI_OPCODE_TXF_LZ
&&
1434 ctx
->screen
->info
.chip_class
<= VI
) {
1435 unsigned array_coord
= target
== TGSI_TEXTURE_1D_ARRAY
? 1 : 2;
1436 args
.coords
[array_coord
] =
1437 ac_build_intrinsic(&ctx
->ac
, "llvm.rint.f32", ctx
->f32
,
1438 &args
.coords
[array_coord
], 1, 0);
1441 /* 1D textures are allocated and used as 2D on GFX9. */
1442 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
1443 LLVMValueRef filler
;
1445 /* Use 0.5, so that we don't sample the border color. */
1446 if (opcode
== TGSI_OPCODE_TXF
||
1447 opcode
== TGSI_OPCODE_TXF_LZ
)
1448 filler
= ctx
->i32_0
;
1450 filler
= LLVMConstReal(ctx
->f32
, 0.5);
1452 if (target
== TGSI_TEXTURE_1D
||
1453 target
== TGSI_TEXTURE_SHADOW1D
) {
1454 args
.coords
[1] = filler
;
1455 } else if (target
== TGSI_TEXTURE_1D_ARRAY
||
1456 target
== TGSI_TEXTURE_SHADOW1D_ARRAY
) {
1457 args
.coords
[2] = args
.coords
[1];
1458 args
.coords
[1] = filler
;
1462 /* Pack LOD or sample index */
1463 if (opcode
== TGSI_OPCODE_TXL
)
1464 args
.lod
= args
.coords
[3];
1465 else if (opcode
== TGSI_OPCODE_TXL2
)
1466 args
.lod
= lp_build_emit_fetch(bld_base
, inst
, 1, TGSI_CHAN_X
);
1467 else if (opcode
== TGSI_OPCODE_TXF
) {
1468 if (target
== TGSI_TEXTURE_2D_MSAA
) {
1469 /* No LOD, but move sample index into the right place. */
1470 args
.coords
[2] = args
.coords
[3];
1471 } else if (target
!= TGSI_TEXTURE_2D_ARRAY_MSAA
) {
1472 args
.lod
= args
.coords
[3];
1476 if (target
== TGSI_TEXTURE_2D_MSAA
||
1477 target
== TGSI_TEXTURE_2D_ARRAY_MSAA
) {
1478 ac_apply_fmask_to_sample(&ctx
->ac
, fmask_ptr
, args
.coords
,
1479 target
== TGSI_TEXTURE_2D_ARRAY_MSAA
);
1482 if (opcode
== TGSI_OPCODE_TXF
||
1483 opcode
== TGSI_OPCODE_TXF_LZ
) {
1484 /* add tex offsets */
1485 if (inst
->Texture
.NumOffsets
) {
1486 const struct tgsi_texture_offset
*off
= inst
->TexOffsets
;
1488 assert(inst
->Texture
.NumOffsets
== 1);
1491 case TGSI_TEXTURE_3D
:
1493 LLVMBuildAdd(ctx
->ac
.builder
, args
.coords
[2],
1494 ctx
->imms
[off
->Index
* TGSI_NUM_CHANNELS
+ off
->SwizzleZ
], "");
1496 case TGSI_TEXTURE_2D
:
1497 case TGSI_TEXTURE_SHADOW2D
:
1498 case TGSI_TEXTURE_RECT
:
1499 case TGSI_TEXTURE_SHADOWRECT
:
1500 case TGSI_TEXTURE_2D_ARRAY
:
1501 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
1503 LLVMBuildAdd(ctx
->ac
.builder
, args
.coords
[1],
1504 ctx
->imms
[off
->Index
* TGSI_NUM_CHANNELS
+ off
->SwizzleY
], "");
1506 case TGSI_TEXTURE_1D
:
1507 case TGSI_TEXTURE_SHADOW1D
:
1508 case TGSI_TEXTURE_1D_ARRAY
:
1509 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
1511 LLVMBuildAdd(ctx
->ac
.builder
, args
.coords
[0],
1512 ctx
->imms
[off
->Index
* TGSI_NUM_CHANNELS
+ off
->SwizzleX
], "");
1514 /* texture offsets do not apply to other texture targets */
1521 if (opcode
== TGSI_OPCODE_TG4
) {
1522 unsigned gather_comp
= 0;
1524 /* DMASK was repurposed for GATHER4. 4 components are always
1525 * returned and DMASK works like a swizzle - it selects
1526 * the component to fetch. The only valid DMASK values are
1527 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
1528 * (red,red,red,red) etc.) The ISA document doesn't mention
1532 /* Get the component index from src1.x for Gather4. */
1533 if (!tgsi_is_shadow_target(target
)) {
1534 LLVMValueRef comp_imm
;
1535 struct tgsi_src_register src1
= inst
->Src
[1].Register
;
1537 assert(src1
.File
== TGSI_FILE_IMMEDIATE
);
1539 comp_imm
= ctx
->imms
[src1
.Index
* TGSI_NUM_CHANNELS
+ src1
.SwizzleX
];
1540 gather_comp
= LLVMConstIntGetZExtValue(comp_imm
);
1541 gather_comp
= CLAMP(gather_comp
, 0, 3);
1544 args
.dmask
= 1 << gather_comp
;
1547 set_tex_fetch_args(ctx
, emit_data
, &args
, target
);
1550 /* Gather4 should follow the same rules as bilinear filtering, but the hardware
1551 * incorrectly forces nearest filtering if the texture format is integer.
1552 * The only effect it has on Gather4, which always returns 4 texels for
1553 * bilinear filtering, is that the final coordinates are off by 0.5 of
1556 * The workaround is to subtract 0.5 from the unnormalized coordinates,
1557 * or (0.5 / size) from the normalized coordinates.
1559 * However, cube textures with 8_8_8_8 data formats require a different
1560 * workaround of overriding the num format to USCALED/SSCALED. This would lose
1561 * precision in 32-bit data formats, so it needs to be applied dynamically at
1562 * runtime. In this case, return an i1 value that indicates whether the
1563 * descriptor was overridden (and hence a fixup of the sampler result is needed).
1566 si_lower_gather4_integer(struct si_shader_context
*ctx
,
1567 struct ac_image_args
*args
,
1569 enum tgsi_return_type return_type
)
1571 LLVMBuilderRef builder
= ctx
->ac
.builder
;
1572 LLVMValueRef wa_8888
= NULL
;
1573 LLVMValueRef half_texel
[2];
1575 assert(return_type
== TGSI_RETURN_TYPE_SINT
||
1576 return_type
== TGSI_RETURN_TYPE_UINT
);
1578 if (target
== TGSI_TEXTURE_CUBE
||
1579 target
== TGSI_TEXTURE_CUBE_ARRAY
) {
1580 LLVMValueRef formats
;
1581 LLVMValueRef data_format
;
1582 LLVMValueRef wa_formats
;
1584 formats
= LLVMBuildExtractElement(builder
, args
->resource
, ctx
->i32_1
, "");
1586 data_format
= LLVMBuildLShr(builder
, formats
,
1587 LLVMConstInt(ctx
->i32
, 20, false), "");
1588 data_format
= LLVMBuildAnd(builder
, data_format
,
1589 LLVMConstInt(ctx
->i32
, (1u << 6) - 1, false), "");
1590 wa_8888
= LLVMBuildICmp(
1591 builder
, LLVMIntEQ
, data_format
,
1592 LLVMConstInt(ctx
->i32
, V_008F14_IMG_DATA_FORMAT_8_8_8_8
, false),
1595 uint32_t wa_num_format
=
1596 return_type
== TGSI_RETURN_TYPE_UINT
?
1597 S_008F14_NUM_FORMAT_GFX6(V_008F14_IMG_NUM_FORMAT_USCALED
) :
1598 S_008F14_NUM_FORMAT_GFX6(V_008F14_IMG_NUM_FORMAT_SSCALED
);
1599 wa_formats
= LLVMBuildAnd(builder
, formats
,
1600 LLVMConstInt(ctx
->i32
, C_008F14_NUM_FORMAT_GFX6
, false),
1602 wa_formats
= LLVMBuildOr(builder
, wa_formats
,
1603 LLVMConstInt(ctx
->i32
, wa_num_format
, false), "");
1605 formats
= LLVMBuildSelect(builder
, wa_8888
, wa_formats
, formats
, "");
1606 args
->resource
= LLVMBuildInsertElement(
1607 builder
, args
->resource
, formats
, ctx
->i32_1
, "");
1610 if (target
== TGSI_TEXTURE_RECT
||
1611 target
== TGSI_TEXTURE_SHADOWRECT
) {
1613 half_texel
[0] = half_texel
[1] = LLVMConstReal(ctx
->f32
, -0.5);
1615 struct tgsi_full_instruction txq_inst
= {};
1616 struct ac_image_args txq_args
= {};
1617 struct lp_build_emit_data txq_emit_data
= {};
1618 struct lp_build_if_state if_ctx
;
1621 /* Skip the texture size query entirely if we don't need it. */
1622 lp_build_if(&if_ctx
, &ctx
->gallivm
, LLVMBuildNot(builder
, wa_8888
, ""));
1625 /* Query the texture size. */
1626 txq_inst
.Texture
.Texture
= target
;
1627 txq_emit_data
.inst
= &txq_inst
;
1628 txq_emit_data
.dst_type
= ctx
->v4i32
;
1629 txq_args
.resource
= args
->resource
;
1630 txq_args
.sampler
= args
->sampler
;
1631 txq_args
.lod
= ctx
->ac
.i32_0
;
1632 txq_args
.dmask
= 0xf;
1633 set_tex_fetch_args(ctx
, &txq_emit_data
, &txq_args
, target
);
1634 txq_emit(NULL
, &ctx
->bld_base
, &txq_emit_data
);
1636 /* Compute -0.5 / size. */
1637 for (unsigned c
= 0; c
< 2; c
++) {
1639 LLVMBuildExtractElement(builder
, txq_emit_data
.output
[0],
1640 LLVMConstInt(ctx
->i32
, c
, 0), "");
1641 half_texel
[c
] = LLVMBuildUIToFP(builder
, half_texel
[c
], ctx
->f32
, "");
1642 half_texel
[c
] = ac_build_fdiv(&ctx
->ac
, ctx
->ac
.f32_1
, half_texel
[c
]);
1643 half_texel
[c
] = LLVMBuildFMul(builder
, half_texel
[c
],
1644 LLVMConstReal(ctx
->f32
, -0.5), "");
1648 lp_build_endif(&if_ctx
);
1650 LLVMBasicBlockRef bb
[2] = { if_ctx
.true_block
, if_ctx
.entry_block
};
1652 for (unsigned c
= 0; c
< 2; c
++) {
1653 LLVMValueRef values
[2] = { half_texel
[c
], ctx
->ac
.f32_0
};
1654 half_texel
[c
] = ac_build_phi(&ctx
->ac
, ctx
->f32
, 2,
1660 for (unsigned c
= 0; c
< 2; c
++) {
1662 tmp
= ac_to_float(&ctx
->ac
, args
->coords
[c
]);
1663 tmp
= LLVMBuildFAdd(builder
, tmp
, half_texel
[c
], "");
1664 args
->coords
[c
] = ac_to_integer(&ctx
->ac
, tmp
);
1670 /* The second half of the cube texture 8_8_8_8 integer workaround: adjust the
1671 * result after the gather operation.
1674 si_fix_gather4_integer_result(struct si_shader_context
*ctx
,
1675 LLVMValueRef result
,
1676 enum tgsi_return_type return_type
,
1679 LLVMBuilderRef builder
= ctx
->ac
.builder
;
1681 assert(return_type
== TGSI_RETURN_TYPE_SINT
||
1682 return_type
== TGSI_RETURN_TYPE_UINT
);
1684 for (unsigned chan
= 0; chan
< 4; ++chan
) {
1685 LLVMValueRef chanv
= LLVMConstInt(ctx
->i32
, chan
, false);
1687 LLVMValueRef wa_value
;
1689 value
= LLVMBuildExtractElement(builder
, result
, chanv
, "");
1691 if (return_type
== TGSI_RETURN_TYPE_UINT
)
1692 wa_value
= LLVMBuildFPToUI(builder
, value
, ctx
->i32
, "");
1694 wa_value
= LLVMBuildFPToSI(builder
, value
, ctx
->i32
, "");
1695 wa_value
= ac_to_float(&ctx
->ac
, wa_value
);
1696 value
= LLVMBuildSelect(builder
, wa
, wa_value
, value
, "");
1698 result
= LLVMBuildInsertElement(builder
, result
, value
, chanv
, "");
1704 static void build_tex_intrinsic(const struct lp_build_tgsi_action
*action
,
1705 struct lp_build_tgsi_context
*bld_base
,
1706 struct lp_build_emit_data
*emit_data
)
1708 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1709 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
1710 struct ac_image_args args
;
1711 unsigned opcode
= inst
->Instruction
.Opcode
;
1712 unsigned target
= inst
->Texture
.Texture
;
1714 if (target
== TGSI_TEXTURE_BUFFER
) {
1715 unsigned num_channels
=
1716 util_last_bit(inst
->Dst
[0].Register
.WriteMask
);
1717 LLVMValueRef result
=
1718 ac_build_buffer_load_format(&ctx
->ac
,
1722 num_channels
, false, true);
1723 emit_data
->output
[emit_data
->chan
] =
1724 ac_build_expand_to_vec4(&ctx
->ac
, result
, num_channels
);
1728 memcpy(&args
, emit_data
->args
, sizeof(args
)); /* ugly */
1730 args
.opcode
= ac_image_sample
;
1733 case TGSI_OPCODE_TXF
:
1734 case TGSI_OPCODE_TXF_LZ
:
1735 args
.opcode
= opcode
== TGSI_OPCODE_TXF_LZ
||
1736 target
== TGSI_TEXTURE_2D_MSAA
||
1737 target
== TGSI_TEXTURE_2D_ARRAY_MSAA
?
1738 ac_image_load
: ac_image_load_mip
;
1740 case TGSI_OPCODE_LODQ
:
1741 args
.opcode
= ac_image_get_lod
;
1743 case TGSI_OPCODE_TEX
:
1744 case TGSI_OPCODE_TEX2
:
1745 case TGSI_OPCODE_TXP
:
1746 if (ctx
->type
!= PIPE_SHADER_FRAGMENT
)
1747 args
.level_zero
= true;
1749 case TGSI_OPCODE_TEX_LZ
:
1750 args
.level_zero
= true;
1752 case TGSI_OPCODE_TXB
:
1753 case TGSI_OPCODE_TXB2
:
1754 assert(ctx
->type
== PIPE_SHADER_FRAGMENT
);
1756 case TGSI_OPCODE_TXL
:
1757 case TGSI_OPCODE_TXL2
:
1759 case TGSI_OPCODE_TXD
:
1761 case TGSI_OPCODE_TG4
:
1762 args
.opcode
= ac_image_gather4
;
1763 args
.level_zero
= true;
1770 /* The hardware needs special lowering for Gather4 with integer formats. */
1771 LLVMValueRef gather4_int_result_workaround
= NULL
;
1773 if (ctx
->screen
->info
.chip_class
<= VI
&&
1774 opcode
== TGSI_OPCODE_TG4
) {
1775 assert(inst
->Texture
.ReturnType
!= TGSI_RETURN_TYPE_UNKNOWN
);
1777 if (inst
->Texture
.ReturnType
== TGSI_RETURN_TYPE_SINT
||
1778 inst
->Texture
.ReturnType
== TGSI_RETURN_TYPE_UINT
) {
1779 gather4_int_result_workaround
=
1780 si_lower_gather4_integer(ctx
, &args
, target
,
1781 inst
->Texture
.ReturnType
);
1785 args
.attributes
= AC_FUNC_ATTR_READNONE
;
1786 LLVMValueRef result
= ac_build_image_opcode(&ctx
->ac
, &args
);
1788 if (gather4_int_result_workaround
) {
1789 result
= si_fix_gather4_integer_result(ctx
, result
,
1790 inst
->Texture
.ReturnType
,
1791 gather4_int_result_workaround
);
1794 emit_data
->output
[emit_data
->chan
] = result
;
1797 static void si_llvm_emit_txqs(
1798 const struct lp_build_tgsi_action
*action
,
1799 struct lp_build_tgsi_context
*bld_base
,
1800 struct lp_build_emit_data
*emit_data
)
1802 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1803 LLVMValueRef res
, samples
;
1804 LLVMValueRef res_ptr
, samp_ptr
, fmask_ptr
= NULL
;
1806 tex_fetch_ptrs(bld_base
, emit_data
, &res_ptr
, &samp_ptr
, &fmask_ptr
);
1808 /* Read the samples from the descriptor directly. */
1809 res
= LLVMBuildBitCast(ctx
->ac
.builder
, res_ptr
, ctx
->v8i32
, "");
1810 samples
= LLVMBuildExtractElement(ctx
->ac
.builder
, res
,
1811 LLVMConstInt(ctx
->i32
, 3, 0), "");
1812 samples
= LLVMBuildLShr(ctx
->ac
.builder
, samples
,
1813 LLVMConstInt(ctx
->i32
, 16, 0), "");
1814 samples
= LLVMBuildAnd(ctx
->ac
.builder
, samples
,
1815 LLVMConstInt(ctx
->i32
, 0xf, 0), "");
1816 samples
= LLVMBuildShl(ctx
->ac
.builder
, ctx
->i32_1
,
1819 emit_data
->output
[emit_data
->chan
] = samples
;
1822 static void si_llvm_emit_fbfetch(const struct lp_build_tgsi_action
*action
,
1823 struct lp_build_tgsi_context
*bld_base
,
1824 struct lp_build_emit_data
*emit_data
)
1826 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1827 struct ac_image_args args
= {};
1828 LLVMValueRef ptr
, image
, fmask
;
1830 /* Ignore src0, because KHR_blend_func_extended disallows multiple render
1834 /* Load the image descriptor. */
1835 STATIC_ASSERT(SI_PS_IMAGE_COLORBUF0
% 2 == 0);
1836 ptr
= LLVMGetParam(ctx
->main_fn
, ctx
->param_rw_buffers
);
1837 ptr
= LLVMBuildPointerCast(ctx
->ac
.builder
, ptr
,
1838 ac_array_in_const32_addr_space(ctx
->v8i32
), "");
1839 image
= ac_build_load_to_sgpr(&ctx
->ac
, ptr
,
1840 LLVMConstInt(ctx
->i32
, SI_PS_IMAGE_COLORBUF0
/ 2, 0));
1844 args
.coords
[chan
++] = si_unpack_param(ctx
, SI_PARAM_POS_FIXED_PT
, 0, 16);
1846 if (!ctx
->shader
->key
.mono
.u
.ps
.fbfetch_is_1D
)
1847 args
.coords
[chan
++] = si_unpack_param(ctx
, SI_PARAM_POS_FIXED_PT
, 16, 16);
1849 /* Get the current render target layer index. */
1850 if (ctx
->shader
->key
.mono
.u
.ps
.fbfetch_layered
)
1851 args
.coords
[chan
++] = si_unpack_param(ctx
, SI_PARAM_ANCILLARY
, 16, 11);
1853 if (ctx
->shader
->key
.mono
.u
.ps
.fbfetch_msaa
)
1854 args
.coords
[chan
++] = si_get_sample_id(ctx
);
1856 if (ctx
->shader
->key
.mono
.u
.ps
.fbfetch_msaa
) {
1857 fmask
= ac_build_load_to_sgpr(&ctx
->ac
, ptr
,
1858 LLVMConstInt(ctx
->i32
, SI_PS_IMAGE_COLORBUF0_FMASK
/ 2, 0));
1860 ac_apply_fmask_to_sample(&ctx
->ac
, fmask
, args
.coords
,
1861 ctx
->shader
->key
.mono
.u
.ps
.fbfetch_layered
);
1864 args
.opcode
= ac_image_load
;
1865 args
.resource
= image
;
1867 if (ctx
->shader
->key
.mono
.u
.ps
.fbfetch_msaa
)
1868 args
.dim
= ctx
->shader
->key
.mono
.u
.ps
.fbfetch_layered
?
1869 ac_image_2darraymsaa
: ac_image_2dmsaa
;
1870 else if (ctx
->shader
->key
.mono
.u
.ps
.fbfetch_is_1D
)
1871 args
.dim
= ctx
->shader
->key
.mono
.u
.ps
.fbfetch_layered
?
1872 ac_image_1darray
: ac_image_1d
;
1874 args
.dim
= ctx
->shader
->key
.mono
.u
.ps
.fbfetch_layered
?
1875 ac_image_2darray
: ac_image_2d
;
1877 emit_data
->output
[emit_data
->chan
] =
1878 ac_build_image_opcode(&ctx
->ac
, &args
);
1881 static const struct lp_build_tgsi_action tex_action
= {
1882 .fetch_args
= tex_fetch_args
,
1883 .emit
= build_tex_intrinsic
,
1887 * Setup actions for TGSI memory opcode, including texture opcodes.
1889 void si_shader_context_init_mem(struct si_shader_context
*ctx
)
1891 struct lp_build_tgsi_context
*bld_base
;
1892 struct lp_build_tgsi_action tmpl
= {};
1894 bld_base
= &ctx
->bld_base
;
1896 bld_base
->op_actions
[TGSI_OPCODE_TEX
] = tex_action
;
1897 bld_base
->op_actions
[TGSI_OPCODE_TEX_LZ
] = tex_action
;
1898 bld_base
->op_actions
[TGSI_OPCODE_TEX2
] = tex_action
;
1899 bld_base
->op_actions
[TGSI_OPCODE_TXB
] = tex_action
;
1900 bld_base
->op_actions
[TGSI_OPCODE_TXB2
] = tex_action
;
1901 bld_base
->op_actions
[TGSI_OPCODE_TXD
] = tex_action
;
1902 bld_base
->op_actions
[TGSI_OPCODE_TXF
] = tex_action
;
1903 bld_base
->op_actions
[TGSI_OPCODE_TXF_LZ
] = tex_action
;
1904 bld_base
->op_actions
[TGSI_OPCODE_TXL
] = tex_action
;
1905 bld_base
->op_actions
[TGSI_OPCODE_TXL2
] = tex_action
;
1906 bld_base
->op_actions
[TGSI_OPCODE_TXP
] = tex_action
;
1907 bld_base
->op_actions
[TGSI_OPCODE_TXQ
].fetch_args
= txq_fetch_args
;
1908 bld_base
->op_actions
[TGSI_OPCODE_TXQ
].emit
= txq_emit
;
1909 bld_base
->op_actions
[TGSI_OPCODE_TG4
] = tex_action
;
1910 bld_base
->op_actions
[TGSI_OPCODE_LODQ
] = tex_action
;
1911 bld_base
->op_actions
[TGSI_OPCODE_TXQS
].emit
= si_llvm_emit_txqs
;
1913 bld_base
->op_actions
[TGSI_OPCODE_FBFETCH
].emit
= si_llvm_emit_fbfetch
;
1915 bld_base
->op_actions
[TGSI_OPCODE_LOAD
].fetch_args
= load_fetch_args
;
1916 bld_base
->op_actions
[TGSI_OPCODE_LOAD
].emit
= load_emit
;
1917 bld_base
->op_actions
[TGSI_OPCODE_STORE
].fetch_args
= store_fetch_args
;
1918 bld_base
->op_actions
[TGSI_OPCODE_STORE
].emit
= store_emit
;
1919 bld_base
->op_actions
[TGSI_OPCODE_RESQ
].fetch_args
= resq_fetch_args
;
1920 bld_base
->op_actions
[TGSI_OPCODE_RESQ
].emit
= resq_emit
;
1922 tmpl
.fetch_args
= atomic_fetch_args
;
1923 tmpl
.emit
= atomic_emit
;
1924 bld_base
->op_actions
[TGSI_OPCODE_ATOMUADD
] = tmpl
;
1925 bld_base
->op_actions
[TGSI_OPCODE_ATOMUADD
].intr_name
= "add";
1926 bld_base
->op_actions
[TGSI_OPCODE_ATOMXCHG
] = tmpl
;
1927 bld_base
->op_actions
[TGSI_OPCODE_ATOMXCHG
].intr_name
= "swap";
1928 bld_base
->op_actions
[TGSI_OPCODE_ATOMCAS
] = tmpl
;
1929 bld_base
->op_actions
[TGSI_OPCODE_ATOMCAS
].intr_name
= "cmpswap";
1930 bld_base
->op_actions
[TGSI_OPCODE_ATOMAND
] = tmpl
;
1931 bld_base
->op_actions
[TGSI_OPCODE_ATOMAND
].intr_name
= "and";
1932 bld_base
->op_actions
[TGSI_OPCODE_ATOMOR
] = tmpl
;
1933 bld_base
->op_actions
[TGSI_OPCODE_ATOMOR
].intr_name
= "or";
1934 bld_base
->op_actions
[TGSI_OPCODE_ATOMXOR
] = tmpl
;
1935 bld_base
->op_actions
[TGSI_OPCODE_ATOMXOR
].intr_name
= "xor";
1936 bld_base
->op_actions
[TGSI_OPCODE_ATOMUMIN
] = tmpl
;
1937 bld_base
->op_actions
[TGSI_OPCODE_ATOMUMIN
].intr_name
= "umin";
1938 bld_base
->op_actions
[TGSI_OPCODE_ATOMUMAX
] = tmpl
;
1939 bld_base
->op_actions
[TGSI_OPCODE_ATOMUMAX
].intr_name
= "umax";
1940 bld_base
->op_actions
[TGSI_OPCODE_ATOMIMIN
] = tmpl
;
1941 bld_base
->op_actions
[TGSI_OPCODE_ATOMIMIN
].intr_name
= "smin";
1942 bld_base
->op_actions
[TGSI_OPCODE_ATOMIMAX
] = tmpl
;
1943 bld_base
->op_actions
[TGSI_OPCODE_ATOMIMAX
].intr_name
= "smax";