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radeonsi: prepare for driver-specific driconf options
[mesa.git] / src / gallium / drivers / radeonsi / si_shader_tgsi_mem.c
1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "si_shader_internal.h"
25 #include "si_pipe.h"
26 #include "sid.h"
27 #include "gallivm/lp_bld_arit.h"
28 #include "gallivm/lp_bld_gather.h"
29 #include "gallivm/lp_bld_intr.h"
30 #include "tgsi/tgsi_build.h"
31 #include "tgsi/tgsi_parse.h"
32 #include "tgsi/tgsi_util.h"
33
34 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
35 struct lp_build_tgsi_context *bld_base,
36 struct lp_build_emit_data *emit_data);
37
38 static const struct lp_build_tgsi_action tex_action;
39
40 /**
41 * Given a v8i32 resource descriptor for a buffer, extract the size of the
42 * buffer in number of elements and return it as an i32.
43 */
44 static LLVMValueRef get_buffer_size(
45 struct lp_build_tgsi_context *bld_base,
46 LLVMValueRef descriptor)
47 {
48 struct si_shader_context *ctx = si_shader_context(bld_base);
49 struct gallivm_state *gallivm = &ctx->gallivm;
50 LLVMBuilderRef builder = gallivm->builder;
51 LLVMValueRef size =
52 LLVMBuildExtractElement(builder, descriptor,
53 LLVMConstInt(ctx->i32, 2, 0), "");
54
55 if (ctx->screen->b.chip_class == VI) {
56 /* On VI, the descriptor contains the size in bytes,
57 * but TXQ must return the size in elements.
58 * The stride is always non-zero for resources using TXQ.
59 */
60 LLVMValueRef stride =
61 LLVMBuildExtractElement(builder, descriptor,
62 ctx->i32_1, "");
63 stride = LLVMBuildLShr(builder, stride,
64 LLVMConstInt(ctx->i32, 16, 0), "");
65 stride = LLVMBuildAnd(builder, stride,
66 LLVMConstInt(ctx->i32, 0x3FFF, 0), "");
67
68 size = LLVMBuildUDiv(builder, size, stride, "");
69 }
70
71 return size;
72 }
73
74 static LLVMValueRef
75 shader_buffer_fetch_rsrc(struct si_shader_context *ctx,
76 const struct tgsi_full_src_register *reg)
77 {
78 LLVMValueRef index;
79
80 if (!reg->Register.Indirect) {
81 index = LLVMConstInt(ctx->i32, reg->Register.Index, false);
82 } else {
83 index = si_get_indirect_index(ctx, &reg->Indirect,
84 reg->Register.Index);
85 }
86
87 return ctx->abi.load_ssbo(&ctx->abi, index, false);
88 }
89
90 static bool tgsi_is_array_sampler(unsigned target)
91 {
92 return target == TGSI_TEXTURE_1D_ARRAY ||
93 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
94 target == TGSI_TEXTURE_2D_ARRAY ||
95 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
96 target == TGSI_TEXTURE_CUBE_ARRAY ||
97 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY ||
98 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
99 }
100
101 static bool tgsi_is_array_image(unsigned target)
102 {
103 return target == TGSI_TEXTURE_3D ||
104 target == TGSI_TEXTURE_CUBE ||
105 target == TGSI_TEXTURE_1D_ARRAY ||
106 target == TGSI_TEXTURE_2D_ARRAY ||
107 target == TGSI_TEXTURE_CUBE_ARRAY ||
108 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
109 }
110
111 /**
112 * Given a 256-bit resource descriptor, force the DCC enable bit to off.
113 *
114 * At least on Tonga, executing image stores on images with DCC enabled and
115 * non-trivial can eventually lead to lockups. This can occur when an
116 * application binds an image as read-only but then uses a shader that writes
117 * to it. The OpenGL spec allows almost arbitrarily bad behavior (including
118 * program termination) in this case, but it doesn't cost much to be a bit
119 * nicer: disabling DCC in the shader still leads to undefined results but
120 * avoids the lockup.
121 */
122 static LLVMValueRef force_dcc_off(struct si_shader_context *ctx,
123 LLVMValueRef rsrc)
124 {
125 if (ctx->screen->b.chip_class <= CIK) {
126 return rsrc;
127 } else {
128 LLVMBuilderRef builder = ctx->gallivm.builder;
129 LLVMValueRef i32_6 = LLVMConstInt(ctx->i32, 6, 0);
130 LLVMValueRef i32_C = LLVMConstInt(ctx->i32, C_008F28_COMPRESSION_EN, 0);
131 LLVMValueRef tmp;
132
133 tmp = LLVMBuildExtractElement(builder, rsrc, i32_6, "");
134 tmp = LLVMBuildAnd(builder, tmp, i32_C, "");
135 return LLVMBuildInsertElement(builder, rsrc, tmp, i32_6, "");
136 }
137 }
138
139 LLVMValueRef si_load_image_desc(struct si_shader_context *ctx,
140 LLVMValueRef list, LLVMValueRef index,
141 enum ac_descriptor_type desc_type, bool dcc_off)
142 {
143 LLVMBuilderRef builder = ctx->gallivm.builder;
144 LLVMValueRef rsrc;
145
146 if (desc_type == AC_DESC_BUFFER) {
147 index = LLVMBuildMul(builder, index,
148 LLVMConstInt(ctx->i32, 2, 0), "");
149 index = LLVMBuildAdd(builder, index,
150 ctx->i32_1, "");
151 list = LLVMBuildPointerCast(builder, list,
152 si_const_array(ctx->v4i32, 0), "");
153 } else {
154 assert(desc_type == AC_DESC_IMAGE);
155 }
156
157 rsrc = ac_build_indexed_load_const(&ctx->ac, list, index);
158 if (dcc_off)
159 rsrc = force_dcc_off(ctx, rsrc);
160 return rsrc;
161 }
162
163 /**
164 * Load the resource descriptor for \p image.
165 */
166 static void
167 image_fetch_rsrc(
168 struct lp_build_tgsi_context *bld_base,
169 const struct tgsi_full_src_register *image,
170 bool is_store, unsigned target,
171 LLVMValueRef *rsrc)
172 {
173 struct si_shader_context *ctx = si_shader_context(bld_base);
174 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
175 ctx->param_samplers_and_images);
176 LLVMValueRef index;
177 bool dcc_off = is_store;
178
179 if (!image->Register.Indirect) {
180 const struct tgsi_shader_info *info = bld_base->info;
181 unsigned images_writemask = info->images_store |
182 info->images_atomic;
183
184 index = LLVMConstInt(ctx->i32,
185 si_get_image_slot(image->Register.Index), 0);
186
187 if (images_writemask & (1 << image->Register.Index))
188 dcc_off = true;
189 } else {
190 /* From the GL_ARB_shader_image_load_store extension spec:
191 *
192 * If a shader performs an image load, store, or atomic
193 * operation using an image variable declared as an array,
194 * and if the index used to select an individual element is
195 * negative or greater than or equal to the size of the
196 * array, the results of the operation are undefined but may
197 * not lead to termination.
198 */
199 index = si_get_bounded_indirect_index(ctx, &image->Indirect,
200 image->Register.Index,
201 ctx->num_images);
202 index = LLVMBuildSub(ctx->gallivm.builder,
203 LLVMConstInt(ctx->i32, SI_NUM_IMAGES - 1, 0),
204 index, "");
205 }
206
207 if (image->Register.File != TGSI_FILE_IMAGE) {
208 struct gallivm_state *gallivm = &ctx->gallivm;
209 LLVMBuilderRef builder = gallivm->builder;
210
211 LLVMValueRef ptr =
212 lp_build_emit_fetch_src(bld_base, image,
213 TGSI_TYPE_UNSIGNED64, 0);
214 rsrc_ptr = LLVMBuildIntToPtr(builder, ptr,
215 si_const_array(ctx->v8i32, 0), "");
216 index = LLVMConstInt(ctx->i32, 0, 0);
217 }
218
219 *rsrc = si_load_image_desc(ctx, rsrc_ptr, index,
220 target == TGSI_TEXTURE_BUFFER ? AC_DESC_BUFFER : AC_DESC_IMAGE,
221 dcc_off);
222 }
223
224 static LLVMValueRef image_fetch_coords(
225 struct lp_build_tgsi_context *bld_base,
226 const struct tgsi_full_instruction *inst,
227 unsigned src, LLVMValueRef desc)
228 {
229 struct si_shader_context *ctx = si_shader_context(bld_base);
230 struct gallivm_state *gallivm = &ctx->gallivm;
231 LLVMBuilderRef builder = gallivm->builder;
232 unsigned target = inst->Memory.Texture;
233 unsigned num_coords = tgsi_util_get_texture_coord_dim(target);
234 LLVMValueRef coords[4];
235 LLVMValueRef tmp;
236 int chan;
237
238 for (chan = 0; chan < num_coords; ++chan) {
239 tmp = lp_build_emit_fetch(bld_base, inst, src, chan);
240 tmp = LLVMBuildBitCast(builder, tmp, ctx->i32, "");
241 coords[chan] = tmp;
242 }
243
244 if (ctx->screen->b.chip_class >= GFX9) {
245 /* 1D textures are allocated and used as 2D on GFX9. */
246 if (target == TGSI_TEXTURE_1D) {
247 coords[1] = ctx->i32_0;
248 num_coords++;
249 } else if (target == TGSI_TEXTURE_1D_ARRAY) {
250 coords[2] = coords[1];
251 coords[1] = ctx->i32_0;
252 num_coords++;
253 } else if (target == TGSI_TEXTURE_2D) {
254 /* The hw can't bind a slice of a 3D image as a 2D
255 * image, because it ignores BASE_ARRAY if the target
256 * is 3D. The workaround is to read BASE_ARRAY and set
257 * it as the 3rd address operand for all 2D images.
258 */
259 LLVMValueRef first_layer, const5, mask;
260
261 const5 = LLVMConstInt(ctx->i32, 5, 0);
262 mask = LLVMConstInt(ctx->i32, S_008F24_BASE_ARRAY(~0), 0);
263 first_layer = LLVMBuildExtractElement(builder, desc, const5, "");
264 first_layer = LLVMBuildAnd(builder, first_layer, mask, "");
265
266 coords[2] = first_layer;
267 num_coords++;
268 }
269 }
270
271 if (num_coords == 1)
272 return coords[0];
273
274 if (num_coords == 3) {
275 /* LLVM has difficulties lowering 3-element vectors. */
276 coords[3] = bld_base->uint_bld.undef;
277 num_coords = 4;
278 }
279
280 return lp_build_gather_values(gallivm, coords, num_coords);
281 }
282
283 /**
284 * Append the extra mode bits that are used by image load and store.
285 */
286 static void image_append_args(
287 struct si_shader_context *ctx,
288 struct lp_build_emit_data * emit_data,
289 unsigned target,
290 bool atomic,
291 bool force_glc)
292 {
293 const struct tgsi_full_instruction *inst = emit_data->inst;
294 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
295 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
296 LLVMValueRef r128 = i1false;
297 LLVMValueRef da = tgsi_is_array_image(target) ? i1true : i1false;
298 LLVMValueRef glc =
299 force_glc ||
300 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE) ?
301 i1true : i1false;
302 LLVMValueRef slc = i1false;
303 LLVMValueRef lwe = i1false;
304
305 if (atomic || (HAVE_LLVM <= 0x0309)) {
306 emit_data->args[emit_data->arg_count++] = r128;
307 emit_data->args[emit_data->arg_count++] = da;
308 if (!atomic) {
309 emit_data->args[emit_data->arg_count++] = glc;
310 }
311 emit_data->args[emit_data->arg_count++] = slc;
312 return;
313 }
314
315 /* HAVE_LLVM >= 0x0400 */
316 emit_data->args[emit_data->arg_count++] = glc;
317 emit_data->args[emit_data->arg_count++] = slc;
318 emit_data->args[emit_data->arg_count++] = lwe;
319 emit_data->args[emit_data->arg_count++] = da;
320 }
321
322 /**
323 * Append the resource and indexing arguments for buffer intrinsics.
324 *
325 * \param rsrc the v4i32 buffer resource
326 * \param index index into the buffer (stride-based)
327 * \param offset byte offset into the buffer
328 */
329 static void buffer_append_args(
330 struct si_shader_context *ctx,
331 struct lp_build_emit_data *emit_data,
332 LLVMValueRef rsrc,
333 LLVMValueRef index,
334 LLVMValueRef offset,
335 bool atomic,
336 bool force_glc)
337 {
338 const struct tgsi_full_instruction *inst = emit_data->inst;
339 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
340 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
341
342 emit_data->args[emit_data->arg_count++] = rsrc;
343 emit_data->args[emit_data->arg_count++] = index; /* vindex */
344 emit_data->args[emit_data->arg_count++] = offset; /* voffset */
345 if (!atomic) {
346 emit_data->args[emit_data->arg_count++] =
347 force_glc ||
348 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE) ?
349 i1true : i1false; /* glc */
350 }
351 emit_data->args[emit_data->arg_count++] = i1false; /* slc */
352 }
353
354 static void load_fetch_args(
355 struct lp_build_tgsi_context * bld_base,
356 struct lp_build_emit_data * emit_data)
357 {
358 struct si_shader_context *ctx = si_shader_context(bld_base);
359 struct gallivm_state *gallivm = &ctx->gallivm;
360 const struct tgsi_full_instruction * inst = emit_data->inst;
361 unsigned target = inst->Memory.Texture;
362 LLVMValueRef rsrc;
363
364 emit_data->dst_type = ctx->v4f32;
365
366 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
367 LLVMBuilderRef builder = gallivm->builder;
368 LLVMValueRef offset;
369 LLVMValueRef tmp;
370
371 rsrc = shader_buffer_fetch_rsrc(ctx, &inst->Src[0]);
372
373 tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
374 offset = LLVMBuildBitCast(builder, tmp, ctx->i32, "");
375
376 buffer_append_args(ctx, emit_data, rsrc, ctx->i32_0,
377 offset, false, false);
378 } else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE ||
379 tgsi_is_bindless_image_file(inst->Src[0].Register.File)) {
380 LLVMValueRef coords;
381
382 image_fetch_rsrc(bld_base, &inst->Src[0], false, target, &rsrc);
383 coords = image_fetch_coords(bld_base, inst, 1, rsrc);
384
385 if (target == TGSI_TEXTURE_BUFFER) {
386 buffer_append_args(ctx, emit_data, rsrc, coords,
387 ctx->i32_0, false, false);
388 } else {
389 emit_data->args[0] = coords;
390 emit_data->args[1] = rsrc;
391 emit_data->args[2] = LLVMConstInt(ctx->i32, 15, 0); /* dmask */
392 emit_data->arg_count = 3;
393
394 image_append_args(ctx, emit_data, target, false, false);
395 }
396 }
397 }
398
399 static unsigned get_load_intr_attribs(bool can_speculate)
400 {
401 /* READNONE means writes can't affect it, while READONLY means that
402 * writes can affect it. */
403 return can_speculate && HAVE_LLVM >= 0x0400 ?
404 LP_FUNC_ATTR_READNONE :
405 LP_FUNC_ATTR_READONLY;
406 }
407
408 static unsigned get_store_intr_attribs(bool writeonly_memory)
409 {
410 return writeonly_memory && HAVE_LLVM >= 0x0400 ?
411 LP_FUNC_ATTR_INACCESSIBLE_MEM_ONLY :
412 LP_FUNC_ATTR_WRITEONLY;
413 }
414
415 static void load_emit_buffer(struct si_shader_context *ctx,
416 struct lp_build_emit_data *emit_data,
417 bool can_speculate)
418 {
419 const struct tgsi_full_instruction *inst = emit_data->inst;
420 uint writemask = inst->Dst[0].Register.WriteMask;
421 uint count = util_last_bit(writemask);
422 LLVMValueRef *args = emit_data->args;
423
424 /* Don't use SMEM for shader buffer loads, because LLVM doesn't
425 * select SMEM for SI.load.const with a non-constant offset, and
426 * constant offsets practically don't exist with shader buffers.
427 *
428 * Also, SI.load.const doesn't use inst_offset when it's lowered
429 * to VMEM, so we just end up with more VALU instructions in the end
430 * and no benefit.
431 *
432 * TODO: Remove this line once LLVM can select SMEM with a non-constant
433 * offset, and can derive inst_offset when VMEM is selected.
434 * After that, si_memory_barrier should invalidate sL1 for shader
435 * buffers.
436 */
437
438 assert(LLVMConstIntGetZExtValue(args[1]) == 0); /* vindex */
439 emit_data->output[emit_data->chan] =
440 ac_build_buffer_load(&ctx->ac, args[0], count, NULL,
441 args[2], NULL, 0,
442 LLVMConstIntGetZExtValue(args[3]),
443 LLVMConstIntGetZExtValue(args[4]),
444 can_speculate, false);
445 }
446
447 static LLVMValueRef get_memory_ptr(struct si_shader_context *ctx,
448 const struct tgsi_full_instruction *inst,
449 LLVMTypeRef type, int arg)
450 {
451 struct gallivm_state *gallivm = &ctx->gallivm;
452 LLVMBuilderRef builder = gallivm->builder;
453 LLVMValueRef offset, ptr;
454 int addr_space;
455
456 offset = lp_build_emit_fetch(&ctx->bld_base, inst, arg, 0);
457 offset = LLVMBuildBitCast(builder, offset, ctx->i32, "");
458
459 ptr = ctx->shared_memory;
460 ptr = LLVMBuildGEP(builder, ptr, &offset, 1, "");
461 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
462 ptr = LLVMBuildBitCast(builder, ptr, LLVMPointerType(type, addr_space), "");
463
464 return ptr;
465 }
466
467 static void load_emit_memory(
468 struct si_shader_context *ctx,
469 struct lp_build_emit_data *emit_data)
470 {
471 const struct tgsi_full_instruction *inst = emit_data->inst;
472 struct gallivm_state *gallivm = &ctx->gallivm;
473 LLVMBuilderRef builder = gallivm->builder;
474 unsigned writemask = inst->Dst[0].Register.WriteMask;
475 LLVMValueRef channels[4], ptr, derived_ptr, index;
476 int chan;
477
478 ptr = get_memory_ptr(ctx, inst, ctx->f32, 1);
479
480 for (chan = 0; chan < 4; ++chan) {
481 if (!(writemask & (1 << chan))) {
482 channels[chan] = LLVMGetUndef(ctx->f32);
483 continue;
484 }
485
486 index = LLVMConstInt(ctx->i32, chan, 0);
487 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
488 channels[chan] = LLVMBuildLoad(builder, derived_ptr, "");
489 }
490 emit_data->output[emit_data->chan] = lp_build_gather_values(gallivm, channels, 4);
491 }
492
493 /**
494 * Return true if the memory accessed by a LOAD or STORE instruction is
495 * read-only or write-only, respectively.
496 *
497 * \param shader_buffers_reverse_access_mask
498 * For LOAD, set this to (store | atomic) slot usage in the shader.
499 * For STORE, set this to (load | atomic) slot usage in the shader.
500 * \param images_reverse_access_mask Same as above, but for images.
501 */
502 static bool is_oneway_access_only(const struct tgsi_full_instruction *inst,
503 const struct tgsi_shader_info *info,
504 unsigned shader_buffers_reverse_access_mask,
505 unsigned images_reverse_access_mask)
506 {
507 /* RESTRICT means NOALIAS.
508 * If there are no writes, we can assume the accessed memory is read-only.
509 * If there are no reads, we can assume the accessed memory is write-only.
510 */
511 if (inst->Memory.Qualifier & TGSI_MEMORY_RESTRICT) {
512 unsigned reverse_access_mask;
513
514 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
515 reverse_access_mask = shader_buffers_reverse_access_mask;
516 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
517 reverse_access_mask = info->images_buffers &
518 images_reverse_access_mask;
519 } else {
520 reverse_access_mask = ~info->images_buffers &
521 images_reverse_access_mask;
522 }
523
524 if (inst->Src[0].Register.Indirect) {
525 if (!reverse_access_mask)
526 return true;
527 } else {
528 if (!(reverse_access_mask &
529 (1u << inst->Src[0].Register.Index)))
530 return true;
531 }
532 }
533
534 /* If there are no buffer writes (for both shader buffers & image
535 * buffers), it implies that buffer memory is read-only.
536 * If there are no buffer reads (for both shader buffers & image
537 * buffers), it implies that buffer memory is write-only.
538 *
539 * Same for the case when there are no writes/reads for non-buffer
540 * images.
541 */
542 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
543 (inst->Memory.Texture == TGSI_TEXTURE_BUFFER &&
544 (inst->Src[0].Register.File == TGSI_FILE_IMAGE ||
545 tgsi_is_bindless_image_file(inst->Src[0].Register.File)))) {
546 if (!shader_buffers_reverse_access_mask &&
547 !(info->images_buffers & images_reverse_access_mask))
548 return true;
549 } else {
550 if (!(~info->images_buffers & images_reverse_access_mask))
551 return true;
552 }
553 return false;
554 }
555
556 static void load_emit(
557 const struct lp_build_tgsi_action *action,
558 struct lp_build_tgsi_context *bld_base,
559 struct lp_build_emit_data *emit_data)
560 {
561 struct si_shader_context *ctx = si_shader_context(bld_base);
562 struct gallivm_state *gallivm = &ctx->gallivm;
563 LLVMBuilderRef builder = gallivm->builder;
564 const struct tgsi_full_instruction * inst = emit_data->inst;
565 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
566 char intrinsic_name[64];
567 bool can_speculate = false;
568
569 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
570 load_emit_memory(ctx, emit_data);
571 return;
572 }
573
574 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
575 si_emit_waitcnt(ctx, VM_CNT);
576
577 can_speculate = !(inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE) &&
578 is_oneway_access_only(inst, info,
579 info->shader_buffers_store |
580 info->shader_buffers_atomic,
581 info->images_store |
582 info->images_atomic);
583
584 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
585 load_emit_buffer(ctx, emit_data, can_speculate);
586 return;
587 }
588
589 if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
590 emit_data->output[emit_data->chan] =
591 lp_build_intrinsic(
592 builder, "llvm.amdgcn.buffer.load.format.v4f32", emit_data->dst_type,
593 emit_data->args, emit_data->arg_count,
594 get_load_intr_attribs(can_speculate));
595 } else {
596 ac_get_image_intr_name("llvm.amdgcn.image.load",
597 emit_data->dst_type, /* vdata */
598 LLVMTypeOf(emit_data->args[0]), /* coords */
599 LLVMTypeOf(emit_data->args[1]), /* rsrc */
600 intrinsic_name, sizeof(intrinsic_name));
601
602 emit_data->output[emit_data->chan] =
603 lp_build_intrinsic(
604 builder, intrinsic_name, emit_data->dst_type,
605 emit_data->args, emit_data->arg_count,
606 get_load_intr_attribs(can_speculate));
607 }
608 }
609
610 static void store_fetch_args(
611 struct lp_build_tgsi_context * bld_base,
612 struct lp_build_emit_data * emit_data)
613 {
614 struct si_shader_context *ctx = si_shader_context(bld_base);
615 struct gallivm_state *gallivm = &ctx->gallivm;
616 LLVMBuilderRef builder = gallivm->builder;
617 const struct tgsi_full_instruction * inst = emit_data->inst;
618 struct tgsi_full_src_register memory;
619 LLVMValueRef chans[4];
620 LLVMValueRef data;
621 LLVMValueRef rsrc;
622 unsigned chan;
623
624 emit_data->dst_type = LLVMVoidTypeInContext(gallivm->context);
625
626 for (chan = 0; chan < 4; ++chan) {
627 chans[chan] = lp_build_emit_fetch(bld_base, inst, 1, chan);
628 }
629 data = lp_build_gather_values(gallivm, chans, 4);
630
631 emit_data->args[emit_data->arg_count++] = data;
632
633 memory = tgsi_full_src_register_from_dst(&inst->Dst[0]);
634
635 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
636 LLVMValueRef offset;
637 LLVMValueRef tmp;
638
639 rsrc = shader_buffer_fetch_rsrc(ctx, &memory);
640
641 tmp = lp_build_emit_fetch(bld_base, inst, 0, 0);
642 offset = LLVMBuildBitCast(builder, tmp, ctx->i32, "");
643
644 buffer_append_args(ctx, emit_data, rsrc, ctx->i32_0,
645 offset, false, false);
646 } else if (inst->Dst[0].Register.File == TGSI_FILE_IMAGE ||
647 tgsi_is_bindless_image_file(inst->Dst[0].Register.File)) {
648 unsigned target = inst->Memory.Texture;
649 LLVMValueRef coords;
650
651 /* 8bit/16bit TC L1 write corruption bug on SI.
652 * All store opcodes not aligned to a dword are affected.
653 *
654 * The only way to get unaligned stores in radeonsi is through
655 * shader images.
656 */
657 bool force_glc = ctx->screen->b.chip_class == SI;
658
659 image_fetch_rsrc(bld_base, &memory, true, target, &rsrc);
660 coords = image_fetch_coords(bld_base, inst, 0, rsrc);
661
662 if (target == TGSI_TEXTURE_BUFFER) {
663 buffer_append_args(ctx, emit_data, rsrc, coords,
664 ctx->i32_0, false, force_glc);
665 } else {
666 emit_data->args[1] = coords;
667 emit_data->args[2] = rsrc;
668 emit_data->args[3] = LLVMConstInt(ctx->i32, 15, 0); /* dmask */
669 emit_data->arg_count = 4;
670
671 image_append_args(ctx, emit_data, target, false, force_glc);
672 }
673 }
674 }
675
676 static void store_emit_buffer(
677 struct si_shader_context *ctx,
678 struct lp_build_emit_data *emit_data,
679 bool writeonly_memory)
680 {
681 const struct tgsi_full_instruction *inst = emit_data->inst;
682 struct gallivm_state *gallivm = &ctx->gallivm;
683 LLVMBuilderRef builder = gallivm->builder;
684 LLVMValueRef base_data = emit_data->args[0];
685 LLVMValueRef base_offset = emit_data->args[3];
686 unsigned writemask = inst->Dst[0].Register.WriteMask;
687
688 while (writemask) {
689 int start, count;
690 const char *intrinsic_name;
691 LLVMValueRef data;
692 LLVMValueRef offset;
693 LLVMValueRef tmp;
694
695 u_bit_scan_consecutive_range(&writemask, &start, &count);
696
697 /* Due to an LLVM limitation, split 3-element writes
698 * into a 2-element and a 1-element write. */
699 if (count == 3) {
700 writemask |= 1 << (start + 2);
701 count = 2;
702 }
703
704 if (count == 4) {
705 data = base_data;
706 intrinsic_name = "llvm.amdgcn.buffer.store.v4f32";
707 } else if (count == 2) {
708 LLVMTypeRef v2f32 = LLVMVectorType(ctx->f32, 2);
709
710 tmp = LLVMBuildExtractElement(
711 builder, base_data,
712 LLVMConstInt(ctx->i32, start, 0), "");
713 data = LLVMBuildInsertElement(
714 builder, LLVMGetUndef(v2f32), tmp,
715 ctx->i32_0, "");
716
717 tmp = LLVMBuildExtractElement(
718 builder, base_data,
719 LLVMConstInt(ctx->i32, start + 1, 0), "");
720 data = LLVMBuildInsertElement(
721 builder, data, tmp, ctx->i32_1, "");
722
723 intrinsic_name = "llvm.amdgcn.buffer.store.v2f32";
724 } else {
725 assert(count == 1);
726 data = LLVMBuildExtractElement(
727 builder, base_data,
728 LLVMConstInt(ctx->i32, start, 0), "");
729 intrinsic_name = "llvm.amdgcn.buffer.store.f32";
730 }
731
732 offset = base_offset;
733 if (start != 0) {
734 offset = LLVMBuildAdd(
735 builder, offset,
736 LLVMConstInt(ctx->i32, start * 4, 0), "");
737 }
738
739 emit_data->args[0] = data;
740 emit_data->args[3] = offset;
741
742 lp_build_intrinsic(
743 builder, intrinsic_name, emit_data->dst_type,
744 emit_data->args, emit_data->arg_count,
745 get_store_intr_attribs(writeonly_memory));
746 }
747 }
748
749 static void store_emit_memory(
750 struct si_shader_context *ctx,
751 struct lp_build_emit_data *emit_data)
752 {
753 const struct tgsi_full_instruction *inst = emit_data->inst;
754 struct gallivm_state *gallivm = &ctx->gallivm;
755 LLVMBuilderRef builder = gallivm->builder;
756 unsigned writemask = inst->Dst[0].Register.WriteMask;
757 LLVMValueRef ptr, derived_ptr, data, index;
758 int chan;
759
760 ptr = get_memory_ptr(ctx, inst, ctx->f32, 0);
761
762 for (chan = 0; chan < 4; ++chan) {
763 if (!(writemask & (1 << chan))) {
764 continue;
765 }
766 data = lp_build_emit_fetch(&ctx->bld_base, inst, 1, chan);
767 index = LLVMConstInt(ctx->i32, chan, 0);
768 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
769 LLVMBuildStore(builder, data, derived_ptr);
770 }
771 }
772
773 static void store_emit(
774 const struct lp_build_tgsi_action *action,
775 struct lp_build_tgsi_context *bld_base,
776 struct lp_build_emit_data *emit_data)
777 {
778 struct si_shader_context *ctx = si_shader_context(bld_base);
779 struct gallivm_state *gallivm = &ctx->gallivm;
780 LLVMBuilderRef builder = gallivm->builder;
781 const struct tgsi_full_instruction * inst = emit_data->inst;
782 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
783 unsigned target = inst->Memory.Texture;
784 char intrinsic_name[64];
785 bool writeonly_memory = false;
786
787 if (inst->Dst[0].Register.File == TGSI_FILE_MEMORY) {
788 store_emit_memory(ctx, emit_data);
789 return;
790 }
791
792 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
793 si_emit_waitcnt(ctx, VM_CNT);
794
795 writeonly_memory = is_oneway_access_only(inst, info,
796 info->shader_buffers_load |
797 info->shader_buffers_atomic,
798 info->images_load |
799 info->images_atomic);
800
801 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
802 store_emit_buffer(ctx, emit_data, writeonly_memory);
803 return;
804 }
805
806 if (target == TGSI_TEXTURE_BUFFER) {
807 emit_data->output[emit_data->chan] = lp_build_intrinsic(
808 builder, "llvm.amdgcn.buffer.store.format.v4f32",
809 emit_data->dst_type, emit_data->args,
810 emit_data->arg_count,
811 get_store_intr_attribs(writeonly_memory));
812 } else {
813 ac_get_image_intr_name("llvm.amdgcn.image.store",
814 LLVMTypeOf(emit_data->args[0]), /* vdata */
815 LLVMTypeOf(emit_data->args[1]), /* coords */
816 LLVMTypeOf(emit_data->args[2]), /* rsrc */
817 intrinsic_name, sizeof(intrinsic_name));
818
819 emit_data->output[emit_data->chan] =
820 lp_build_intrinsic(
821 builder, intrinsic_name, emit_data->dst_type,
822 emit_data->args, emit_data->arg_count,
823 get_store_intr_attribs(writeonly_memory));
824 }
825 }
826
827 static void atomic_fetch_args(
828 struct lp_build_tgsi_context * bld_base,
829 struct lp_build_emit_data * emit_data)
830 {
831 struct si_shader_context *ctx = si_shader_context(bld_base);
832 struct gallivm_state *gallivm = &ctx->gallivm;
833 LLVMBuilderRef builder = gallivm->builder;
834 const struct tgsi_full_instruction * inst = emit_data->inst;
835 LLVMValueRef data1, data2;
836 LLVMValueRef rsrc;
837 LLVMValueRef tmp;
838
839 emit_data->dst_type = ctx->f32;
840
841 tmp = lp_build_emit_fetch(bld_base, inst, 2, 0);
842 data1 = LLVMBuildBitCast(builder, tmp, ctx->i32, "");
843
844 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
845 tmp = lp_build_emit_fetch(bld_base, inst, 3, 0);
846 data2 = LLVMBuildBitCast(builder, tmp, ctx->i32, "");
847 }
848
849 /* llvm.amdgcn.image/buffer.atomic.cmpswap reflect the hardware order
850 * of arguments, which is reversed relative to TGSI (and GLSL)
851 */
852 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
853 emit_data->args[emit_data->arg_count++] = data2;
854 emit_data->args[emit_data->arg_count++] = data1;
855
856 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
857 LLVMValueRef offset;
858
859 rsrc = shader_buffer_fetch_rsrc(ctx, &inst->Src[0]);
860
861 tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
862 offset = LLVMBuildBitCast(builder, tmp, ctx->i32, "");
863
864 buffer_append_args(ctx, emit_data, rsrc, ctx->i32_0,
865 offset, true, false);
866 } else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE ||
867 tgsi_is_bindless_image_file(inst->Src[0].Register.File)) {
868 unsigned target = inst->Memory.Texture;
869 LLVMValueRef coords;
870
871 image_fetch_rsrc(bld_base, &inst->Src[0], true, target, &rsrc);
872 coords = image_fetch_coords(bld_base, inst, 1, rsrc);
873
874 if (target == TGSI_TEXTURE_BUFFER) {
875 buffer_append_args(ctx, emit_data, rsrc, coords,
876 ctx->i32_0, true, false);
877 } else {
878 emit_data->args[emit_data->arg_count++] = coords;
879 emit_data->args[emit_data->arg_count++] = rsrc;
880
881 image_append_args(ctx, emit_data, target, true, false);
882 }
883 }
884 }
885
886 static void atomic_emit_memory(struct si_shader_context *ctx,
887 struct lp_build_emit_data *emit_data) {
888 struct gallivm_state *gallivm = &ctx->gallivm;
889 LLVMBuilderRef builder = gallivm->builder;
890 const struct tgsi_full_instruction * inst = emit_data->inst;
891 LLVMValueRef ptr, result, arg;
892
893 ptr = get_memory_ptr(ctx, inst, ctx->i32, 1);
894
895 arg = lp_build_emit_fetch(&ctx->bld_base, inst, 2, 0);
896 arg = LLVMBuildBitCast(builder, arg, ctx->i32, "");
897
898 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
899 LLVMValueRef new_data;
900 new_data = lp_build_emit_fetch(&ctx->bld_base,
901 inst, 3, 0);
902
903 new_data = LLVMBuildBitCast(builder, new_data, ctx->i32, "");
904
905 result = LLVMBuildAtomicCmpXchg(builder, ptr, arg, new_data,
906 LLVMAtomicOrderingSequentiallyConsistent,
907 LLVMAtomicOrderingSequentiallyConsistent,
908 false);
909
910 result = LLVMBuildExtractValue(builder, result, 0, "");
911 } else {
912 LLVMAtomicRMWBinOp op;
913
914 switch(inst->Instruction.Opcode) {
915 case TGSI_OPCODE_ATOMUADD:
916 op = LLVMAtomicRMWBinOpAdd;
917 break;
918 case TGSI_OPCODE_ATOMXCHG:
919 op = LLVMAtomicRMWBinOpXchg;
920 break;
921 case TGSI_OPCODE_ATOMAND:
922 op = LLVMAtomicRMWBinOpAnd;
923 break;
924 case TGSI_OPCODE_ATOMOR:
925 op = LLVMAtomicRMWBinOpOr;
926 break;
927 case TGSI_OPCODE_ATOMXOR:
928 op = LLVMAtomicRMWBinOpXor;
929 break;
930 case TGSI_OPCODE_ATOMUMIN:
931 op = LLVMAtomicRMWBinOpUMin;
932 break;
933 case TGSI_OPCODE_ATOMUMAX:
934 op = LLVMAtomicRMWBinOpUMax;
935 break;
936 case TGSI_OPCODE_ATOMIMIN:
937 op = LLVMAtomicRMWBinOpMin;
938 break;
939 case TGSI_OPCODE_ATOMIMAX:
940 op = LLVMAtomicRMWBinOpMax;
941 break;
942 default:
943 unreachable("unknown atomic opcode");
944 }
945
946 result = LLVMBuildAtomicRMW(builder, op, ptr, arg,
947 LLVMAtomicOrderingSequentiallyConsistent,
948 false);
949 }
950 emit_data->output[emit_data->chan] = LLVMBuildBitCast(builder, result, emit_data->dst_type, "");
951 }
952
953 static void atomic_emit(
954 const struct lp_build_tgsi_action *action,
955 struct lp_build_tgsi_context *bld_base,
956 struct lp_build_emit_data *emit_data)
957 {
958 struct si_shader_context *ctx = si_shader_context(bld_base);
959 struct gallivm_state *gallivm = &ctx->gallivm;
960 LLVMBuilderRef builder = gallivm->builder;
961 const struct tgsi_full_instruction * inst = emit_data->inst;
962 char intrinsic_name[40];
963 LLVMValueRef tmp;
964
965 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
966 atomic_emit_memory(ctx, emit_data);
967 return;
968 }
969
970 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
971 inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
972 snprintf(intrinsic_name, sizeof(intrinsic_name),
973 "llvm.amdgcn.buffer.atomic.%s", action->intr_name);
974 } else {
975 LLVMValueRef coords;
976 char coords_type[8];
977
978 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
979 coords = emit_data->args[2];
980 else
981 coords = emit_data->args[1];
982
983 ac_build_type_name_for_intr(LLVMTypeOf(coords), coords_type, sizeof(coords_type));
984 snprintf(intrinsic_name, sizeof(intrinsic_name),
985 "llvm.amdgcn.image.atomic.%s.%s",
986 action->intr_name, coords_type);
987 }
988
989 tmp = lp_build_intrinsic(
990 builder, intrinsic_name, ctx->i32,
991 emit_data->args, emit_data->arg_count, 0);
992 emit_data->output[emit_data->chan] =
993 LLVMBuildBitCast(builder, tmp, ctx->f32, "");
994 }
995
996 static void set_tex_fetch_args(struct si_shader_context *ctx,
997 struct lp_build_emit_data *emit_data,
998 unsigned target,
999 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
1000 LLVMValueRef *param, unsigned count,
1001 unsigned dmask)
1002 {
1003 struct gallivm_state *gallivm = &ctx->gallivm;
1004 struct ac_image_args args = {};
1005
1006 /* Pad to power of two vector */
1007 while (count < util_next_power_of_two(count))
1008 param[count++] = LLVMGetUndef(ctx->i32);
1009
1010 if (count > 1)
1011 args.addr = lp_build_gather_values(gallivm, param, count);
1012 else
1013 args.addr = param[0];
1014
1015 args.resource = res_ptr;
1016 args.sampler = samp_ptr;
1017 args.dmask = dmask;
1018 args.unorm = target == TGSI_TEXTURE_RECT ||
1019 target == TGSI_TEXTURE_SHADOWRECT;
1020 args.da = tgsi_is_array_sampler(target);
1021
1022 /* Ugly, but we seem to have no other choice right now. */
1023 STATIC_ASSERT(sizeof(args) <= sizeof(emit_data->args));
1024 memcpy(emit_data->args, &args, sizeof(args));
1025 }
1026
1027 static LLVMValueRef fix_resinfo(struct si_shader_context *ctx,
1028 unsigned target, LLVMValueRef out)
1029 {
1030 LLVMBuilderRef builder = ctx->gallivm.builder;
1031
1032 /* 1D textures are allocated and used as 2D on GFX9. */
1033 if (ctx->screen->b.chip_class >= GFX9 &&
1034 (target == TGSI_TEXTURE_1D_ARRAY ||
1035 target == TGSI_TEXTURE_SHADOW1D_ARRAY)) {
1036 LLVMValueRef layers =
1037 LLVMBuildExtractElement(builder, out,
1038 LLVMConstInt(ctx->i32, 2, 0), "");
1039 out = LLVMBuildInsertElement(builder, out, layers,
1040 ctx->i32_1, "");
1041 }
1042
1043 /* Divide the number of layers by 6 to get the number of cubes. */
1044 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
1045 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
1046 LLVMValueRef imm2 = LLVMConstInt(ctx->i32, 2, 0);
1047
1048 LLVMValueRef z = LLVMBuildExtractElement(builder, out, imm2, "");
1049 z = LLVMBuildSDiv(builder, z, LLVMConstInt(ctx->i32, 6, 0), "");
1050
1051 out = LLVMBuildInsertElement(builder, out, z, imm2, "");
1052 }
1053 return out;
1054 }
1055
1056 static void resq_fetch_args(
1057 struct lp_build_tgsi_context * bld_base,
1058 struct lp_build_emit_data * emit_data)
1059 {
1060 struct si_shader_context *ctx = si_shader_context(bld_base);
1061 const struct tgsi_full_instruction *inst = emit_data->inst;
1062 const struct tgsi_full_src_register *reg = &inst->Src[0];
1063
1064 emit_data->dst_type = ctx->v4i32;
1065
1066 if (reg->Register.File == TGSI_FILE_BUFFER) {
1067 emit_data->args[0] = shader_buffer_fetch_rsrc(ctx, reg);
1068 emit_data->arg_count = 1;
1069 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
1070 image_fetch_rsrc(bld_base, reg, false, inst->Memory.Texture,
1071 &emit_data->args[0]);
1072 emit_data->arg_count = 1;
1073 } else {
1074 LLVMValueRef res_ptr;
1075 unsigned image_target;
1076
1077 if (inst->Memory.Texture == TGSI_TEXTURE_3D)
1078 image_target = TGSI_TEXTURE_2D_ARRAY;
1079 else
1080 image_target = inst->Memory.Texture;
1081
1082 image_fetch_rsrc(bld_base, reg, false, inst->Memory.Texture,
1083 &res_ptr);
1084 set_tex_fetch_args(ctx, emit_data, image_target,
1085 res_ptr, NULL, &ctx->i32_0, 1,
1086 0xf);
1087 }
1088 }
1089
1090 static void resq_emit(
1091 const struct lp_build_tgsi_action *action,
1092 struct lp_build_tgsi_context *bld_base,
1093 struct lp_build_emit_data *emit_data)
1094 {
1095 struct si_shader_context *ctx = si_shader_context(bld_base);
1096 struct gallivm_state *gallivm = &ctx->gallivm;
1097 LLVMBuilderRef builder = gallivm->builder;
1098 const struct tgsi_full_instruction *inst = emit_data->inst;
1099 LLVMValueRef out;
1100
1101 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
1102 out = LLVMBuildExtractElement(builder, emit_data->args[0],
1103 LLVMConstInt(ctx->i32, 2, 0), "");
1104 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
1105 out = get_buffer_size(bld_base, emit_data->args[0]);
1106 } else {
1107 struct ac_image_args args;
1108
1109 memcpy(&args, emit_data->args, sizeof(args)); /* ugly */
1110 args.opcode = ac_image_get_resinfo;
1111 out = ac_build_image_opcode(&ctx->ac, &args);
1112
1113 out = fix_resinfo(ctx, inst->Memory.Texture, out);
1114 }
1115
1116 emit_data->output[emit_data->chan] = out;
1117 }
1118
1119 /**
1120 * Load an image view, fmask view. or sampler state descriptor.
1121 */
1122 LLVMValueRef si_load_sampler_desc(struct si_shader_context *ctx,
1123 LLVMValueRef list, LLVMValueRef index,
1124 enum ac_descriptor_type type)
1125 {
1126 struct gallivm_state *gallivm = &ctx->gallivm;
1127 LLVMBuilderRef builder = gallivm->builder;
1128
1129 switch (type) {
1130 case AC_DESC_IMAGE:
1131 /* The image is at [0:7]. */
1132 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
1133 break;
1134 case AC_DESC_BUFFER:
1135 /* The buffer is in [4:7]. */
1136 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 4, 0), "");
1137 index = LLVMBuildAdd(builder, index, ctx->i32_1, "");
1138 list = LLVMBuildPointerCast(builder, list,
1139 si_const_array(ctx->v4i32, 0), "");
1140 break;
1141 case AC_DESC_FMASK:
1142 /* The FMASK is at [8:15]. */
1143 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
1144 index = LLVMBuildAdd(builder, index, ctx->i32_1, "");
1145 break;
1146 case AC_DESC_SAMPLER:
1147 /* The sampler state is at [12:15]. */
1148 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 4, 0), "");
1149 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 3, 0), "");
1150 list = LLVMBuildPointerCast(builder, list,
1151 si_const_array(ctx->v4i32, 0), "");
1152 break;
1153 }
1154
1155 return ac_build_indexed_load_const(&ctx->ac, list, index);
1156 }
1157
1158 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
1159 *
1160 * SI-CI:
1161 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
1162 * filtering manually. The driver sets img7 to a mask clearing
1163 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
1164 * s_and_b32 samp0, samp0, img7
1165 *
1166 * VI:
1167 * The ANISO_OVERRIDE sampler field enables this fix in TA.
1168 */
1169 static LLVMValueRef sici_fix_sampler_aniso(struct si_shader_context *ctx,
1170 LLVMValueRef res, LLVMValueRef samp)
1171 {
1172 LLVMBuilderRef builder = ctx->gallivm.builder;
1173 LLVMValueRef img7, samp0;
1174
1175 if (ctx->screen->b.chip_class >= VI)
1176 return samp;
1177
1178 img7 = LLVMBuildExtractElement(builder, res,
1179 LLVMConstInt(ctx->i32, 7, 0), "");
1180 samp0 = LLVMBuildExtractElement(builder, samp,
1181 ctx->i32_0, "");
1182 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
1183 return LLVMBuildInsertElement(builder, samp, samp0,
1184 ctx->i32_0, "");
1185 }
1186
1187 static void tex_fetch_ptrs(
1188 struct lp_build_tgsi_context *bld_base,
1189 struct lp_build_emit_data *emit_data,
1190 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr, LLVMValueRef *fmask_ptr)
1191 {
1192 struct si_shader_context *ctx = si_shader_context(bld_base);
1193 LLVMValueRef list = LLVMGetParam(ctx->main_fn, ctx->param_samplers_and_images);
1194 const struct tgsi_full_instruction *inst = emit_data->inst;
1195 const struct tgsi_full_src_register *reg;
1196 unsigned target = inst->Texture.Texture;
1197 unsigned sampler_src;
1198 LLVMValueRef index;
1199
1200 sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
1201 reg = &emit_data->inst->Src[sampler_src];
1202
1203 if (reg->Register.Indirect) {
1204 index = si_get_bounded_indirect_index(ctx,
1205 &reg->Indirect,
1206 reg->Register.Index,
1207 ctx->num_samplers);
1208 index = LLVMBuildAdd(ctx->gallivm.builder, index,
1209 LLVMConstInt(ctx->i32, SI_NUM_IMAGES / 2, 0), "");
1210 } else {
1211 index = LLVMConstInt(ctx->i32,
1212 si_get_sampler_slot(reg->Register.Index), 0);
1213 }
1214
1215 if (reg->Register.File != TGSI_FILE_SAMPLER) {
1216 struct gallivm_state *gallivm = &ctx->gallivm;
1217 LLVMBuilderRef builder = gallivm->builder;
1218
1219 LLVMValueRef ptr =
1220 lp_build_emit_fetch_src(bld_base, reg,
1221 TGSI_TYPE_UNSIGNED64, 0);
1222 list = LLVMBuildIntToPtr(builder, ptr,
1223 si_const_array(ctx->v8i32, 0), "");
1224 index = LLVMConstInt(ctx->i32, 0, 0);
1225 }
1226
1227 if (target == TGSI_TEXTURE_BUFFER)
1228 *res_ptr = si_load_sampler_desc(ctx, list, index, AC_DESC_BUFFER);
1229 else
1230 *res_ptr = si_load_sampler_desc(ctx, list, index, AC_DESC_IMAGE);
1231
1232 if (samp_ptr)
1233 *samp_ptr = NULL;
1234 if (fmask_ptr)
1235 *fmask_ptr = NULL;
1236
1237 if (target == TGSI_TEXTURE_2D_MSAA ||
1238 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
1239 if (fmask_ptr)
1240 *fmask_ptr = si_load_sampler_desc(ctx, list, index,
1241 AC_DESC_FMASK);
1242 } else if (target != TGSI_TEXTURE_BUFFER) {
1243 if (samp_ptr) {
1244 *samp_ptr = si_load_sampler_desc(ctx, list, index,
1245 AC_DESC_SAMPLER);
1246 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
1247 }
1248 }
1249 }
1250
1251 static void txq_fetch_args(
1252 struct lp_build_tgsi_context *bld_base,
1253 struct lp_build_emit_data *emit_data)
1254 {
1255 struct si_shader_context *ctx = si_shader_context(bld_base);
1256 const struct tgsi_full_instruction *inst = emit_data->inst;
1257 unsigned target = inst->Texture.Texture;
1258 LLVMValueRef res_ptr;
1259 LLVMValueRef address;
1260
1261 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, NULL, NULL);
1262
1263 if (target == TGSI_TEXTURE_BUFFER) {
1264 /* Read the size from the buffer descriptor directly. */
1265 emit_data->args[0] = get_buffer_size(bld_base, res_ptr);
1266 return;
1267 }
1268
1269 /* Textures - set the mip level. */
1270 address = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
1271
1272 set_tex_fetch_args(ctx, emit_data, target, res_ptr,
1273 NULL, &address, 1, 0xf);
1274 }
1275
1276 static void txq_emit(const struct lp_build_tgsi_action *action,
1277 struct lp_build_tgsi_context *bld_base,
1278 struct lp_build_emit_data *emit_data)
1279 {
1280 struct si_shader_context *ctx = si_shader_context(bld_base);
1281 struct ac_image_args args;
1282 unsigned target = emit_data->inst->Texture.Texture;
1283
1284 if (target == TGSI_TEXTURE_BUFFER) {
1285 /* Just return the buffer size. */
1286 emit_data->output[emit_data->chan] = emit_data->args[0];
1287 return;
1288 }
1289
1290 memcpy(&args, emit_data->args, sizeof(args)); /* ugly */
1291
1292 args.opcode = ac_image_get_resinfo;
1293 LLVMValueRef result = ac_build_image_opcode(&ctx->ac, &args);
1294
1295 emit_data->output[emit_data->chan] = fix_resinfo(ctx, target, result);
1296 }
1297
1298 static void tex_fetch_args(
1299 struct lp_build_tgsi_context *bld_base,
1300 struct lp_build_emit_data *emit_data)
1301 {
1302 struct si_shader_context *ctx = si_shader_context(bld_base);
1303 struct gallivm_state *gallivm = &ctx->gallivm;
1304 const struct tgsi_full_instruction *inst = emit_data->inst;
1305 unsigned opcode = inst->Instruction.Opcode;
1306 unsigned target = inst->Texture.Texture;
1307 LLVMValueRef coords[5], derivs[6];
1308 LLVMValueRef address[16];
1309 unsigned num_coords = tgsi_util_get_texture_coord_dim(target);
1310 int ref_pos = tgsi_util_get_shadow_ref_src_index(target);
1311 unsigned count = 0;
1312 unsigned chan;
1313 unsigned num_deriv_channels = 0;
1314 bool has_offset = inst->Texture.NumOffsets > 0;
1315 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
1316 unsigned dmask = 0xf;
1317
1318 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
1319
1320 if (target == TGSI_TEXTURE_BUFFER) {
1321 emit_data->dst_type = ctx->v4f32;
1322 emit_data->args[0] = res_ptr;
1323 emit_data->args[1] = ctx->i32_0;
1324 emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
1325 emit_data->arg_count = 3;
1326 return;
1327 }
1328
1329 /* Fetch and project texture coordinates */
1330 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
1331 for (chan = 0; chan < 3; chan++ ) {
1332 coords[chan] = lp_build_emit_fetch(bld_base,
1333 emit_data->inst, 0,
1334 chan);
1335 if (opcode == TGSI_OPCODE_TXP)
1336 coords[chan] = lp_build_emit_llvm_binary(bld_base,
1337 TGSI_OPCODE_DIV,
1338 coords[chan],
1339 coords[3]);
1340 }
1341
1342 if (opcode == TGSI_OPCODE_TXP)
1343 coords[3] = bld_base->base.one;
1344
1345 /* Pack offsets. */
1346 if (has_offset &&
1347 opcode != TGSI_OPCODE_TXF &&
1348 opcode != TGSI_OPCODE_TXF_LZ) {
1349 /* The offsets are six-bit signed integers packed like this:
1350 * X=[5:0], Y=[13:8], and Z=[21:16].
1351 */
1352 LLVMValueRef offset[3], pack;
1353
1354 assert(inst->Texture.NumOffsets == 1);
1355
1356 for (chan = 0; chan < 3; chan++) {
1357 offset[chan] = lp_build_emit_fetch_texoffset(bld_base,
1358 emit_data->inst, 0, chan);
1359 offset[chan] = LLVMBuildAnd(gallivm->builder, offset[chan],
1360 LLVMConstInt(ctx->i32, 0x3f, 0), "");
1361 if (chan)
1362 offset[chan] = LLVMBuildShl(gallivm->builder, offset[chan],
1363 LLVMConstInt(ctx->i32, chan*8, 0), "");
1364 }
1365
1366 pack = LLVMBuildOr(gallivm->builder, offset[0], offset[1], "");
1367 pack = LLVMBuildOr(gallivm->builder, pack, offset[2], "");
1368 address[count++] = pack;
1369 }
1370
1371 /* Pack LOD bias value */
1372 if (opcode == TGSI_OPCODE_TXB)
1373 address[count++] = coords[3];
1374 if (opcode == TGSI_OPCODE_TXB2)
1375 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
1376
1377 /* Pack depth comparison value */
1378 if (tgsi_is_shadow_target(target) && opcode != TGSI_OPCODE_LODQ) {
1379 LLVMValueRef z;
1380
1381 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
1382 z = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
1383 } else {
1384 assert(ref_pos >= 0);
1385 z = coords[ref_pos];
1386 }
1387
1388 /* TC-compatible HTILE promotes Z16 and Z24 to Z32_FLOAT,
1389 * so the depth comparison value isn't clamped for Z16 and
1390 * Z24 anymore. Do it manually here.
1391 *
1392 * It's unnecessary if the original texture format was
1393 * Z32_FLOAT, but we don't know that here.
1394 */
1395 if (ctx->screen->b.chip_class == VI)
1396 z = ac_build_clamp(&ctx->ac, z);
1397
1398 address[count++] = z;
1399 }
1400
1401 /* Pack user derivatives */
1402 if (opcode == TGSI_OPCODE_TXD) {
1403 int param, num_src_deriv_channels, num_dst_deriv_channels;
1404
1405 switch (target) {
1406 case TGSI_TEXTURE_3D:
1407 num_src_deriv_channels = 3;
1408 num_dst_deriv_channels = 3;
1409 num_deriv_channels = 3;
1410 break;
1411 case TGSI_TEXTURE_2D:
1412 case TGSI_TEXTURE_SHADOW2D:
1413 case TGSI_TEXTURE_RECT:
1414 case TGSI_TEXTURE_SHADOWRECT:
1415 case TGSI_TEXTURE_2D_ARRAY:
1416 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1417 num_src_deriv_channels = 2;
1418 num_dst_deriv_channels = 2;
1419 num_deriv_channels = 2;
1420 break;
1421 case TGSI_TEXTURE_CUBE:
1422 case TGSI_TEXTURE_SHADOWCUBE:
1423 case TGSI_TEXTURE_CUBE_ARRAY:
1424 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
1425 /* Cube derivatives will be converted to 2D. */
1426 num_src_deriv_channels = 3;
1427 num_dst_deriv_channels = 3;
1428 num_deriv_channels = 2;
1429 break;
1430 case TGSI_TEXTURE_1D:
1431 case TGSI_TEXTURE_SHADOW1D:
1432 case TGSI_TEXTURE_1D_ARRAY:
1433 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1434 num_src_deriv_channels = 1;
1435
1436 /* 1D textures are allocated and used as 2D on GFX9. */
1437 if (ctx->screen->b.chip_class >= GFX9) {
1438 num_dst_deriv_channels = 2;
1439 num_deriv_channels = 2;
1440 } else {
1441 num_dst_deriv_channels = 1;
1442 num_deriv_channels = 1;
1443 }
1444 break;
1445 default:
1446 unreachable("invalid target");
1447 }
1448
1449 for (param = 0; param < 2; param++) {
1450 for (chan = 0; chan < num_src_deriv_channels; chan++)
1451 derivs[param * num_dst_deriv_channels + chan] =
1452 lp_build_emit_fetch(bld_base, inst, param+1, chan);
1453
1454 /* Fill in the rest with zeros. */
1455 for (chan = num_src_deriv_channels;
1456 chan < num_dst_deriv_channels; chan++)
1457 derivs[param * num_dst_deriv_channels + chan] =
1458 bld_base->base.zero;
1459 }
1460 }
1461
1462 if (target == TGSI_TEXTURE_CUBE ||
1463 target == TGSI_TEXTURE_CUBE_ARRAY ||
1464 target == TGSI_TEXTURE_SHADOWCUBE ||
1465 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
1466 ac_prepare_cube_coords(&ctx->ac,
1467 opcode == TGSI_OPCODE_TXD,
1468 target == TGSI_TEXTURE_CUBE_ARRAY ||
1469 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY,
1470 coords, derivs);
1471
1472 if (opcode == TGSI_OPCODE_TXD)
1473 for (int i = 0; i < num_deriv_channels * 2; i++)
1474 address[count++] = derivs[i];
1475
1476 /* Pack texture coordinates */
1477 address[count++] = coords[0];
1478 if (num_coords > 1)
1479 address[count++] = coords[1];
1480 if (num_coords > 2)
1481 address[count++] = coords[2];
1482
1483 /* 1D textures are allocated and used as 2D on GFX9. */
1484 if (ctx->screen->b.chip_class >= GFX9) {
1485 LLVMValueRef filler;
1486
1487 /* Use 0.5, so that we don't sample the border color. */
1488 if (opcode == TGSI_OPCODE_TXF ||
1489 opcode == TGSI_OPCODE_TXF_LZ)
1490 filler = ctx->i32_0;
1491 else
1492 filler = LLVMConstReal(ctx->f32, 0.5);
1493
1494 if (target == TGSI_TEXTURE_1D ||
1495 target == TGSI_TEXTURE_SHADOW1D) {
1496 address[count++] = filler;
1497 } else if (target == TGSI_TEXTURE_1D_ARRAY ||
1498 target == TGSI_TEXTURE_SHADOW1D_ARRAY) {
1499 address[count] = address[count - 1];
1500 address[count - 1] = filler;
1501 count++;
1502 }
1503 }
1504
1505 /* Pack LOD or sample index */
1506 if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
1507 address[count++] = coords[3];
1508 else if (opcode == TGSI_OPCODE_TXL2)
1509 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
1510
1511 if (count > 16) {
1512 assert(!"Cannot handle more than 16 texture address parameters");
1513 count = 16;
1514 }
1515
1516 for (chan = 0; chan < count; chan++ ) {
1517 address[chan] = LLVMBuildBitCast(gallivm->builder,
1518 address[chan], ctx->i32, "");
1519 }
1520
1521 /* Adjust the sample index according to FMASK.
1522 *
1523 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
1524 * which is the identity mapping. Each nibble says which physical sample
1525 * should be fetched to get that sample.
1526 *
1527 * For example, 0x11111100 means there are only 2 samples stored and
1528 * the second sample covers 3/4 of the pixel. When reading samples 0
1529 * and 1, return physical sample 0 (determined by the first two 0s
1530 * in FMASK), otherwise return physical sample 1.
1531 *
1532 * The sample index should be adjusted as follows:
1533 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
1534 */
1535 if (target == TGSI_TEXTURE_2D_MSAA ||
1536 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
1537 struct lp_build_emit_data txf_emit_data = *emit_data;
1538 LLVMValueRef txf_address[4];
1539 /* We only need .xy for non-arrays, and .xyz for arrays. */
1540 unsigned txf_count = target == TGSI_TEXTURE_2D_MSAA ? 2 : 3;
1541 struct tgsi_full_instruction inst = {};
1542
1543 memcpy(txf_address, address, sizeof(txf_address));
1544
1545 /* Read FMASK using TXF_LZ. */
1546 inst.Instruction.Opcode = TGSI_OPCODE_TXF_LZ;
1547 inst.Texture.Texture = target;
1548 txf_emit_data.inst = &inst;
1549 txf_emit_data.chan = 0;
1550 set_tex_fetch_args(ctx, &txf_emit_data,
1551 target, fmask_ptr, NULL,
1552 txf_address, txf_count, 0xf);
1553 build_tex_intrinsic(&tex_action, bld_base, &txf_emit_data);
1554
1555 /* Initialize some constants. */
1556 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, 0);
1557 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xF, 0);
1558
1559 /* Apply the formula. */
1560 LLVMValueRef fmask =
1561 LLVMBuildExtractElement(gallivm->builder,
1562 txf_emit_data.output[0],
1563 ctx->i32_0, "");
1564
1565 unsigned sample_chan = txf_count; /* the sample index is last */
1566
1567 LLVMValueRef sample_index4 =
1568 LLVMBuildMul(gallivm->builder, address[sample_chan], four, "");
1569
1570 LLVMValueRef shifted_fmask =
1571 LLVMBuildLShr(gallivm->builder, fmask, sample_index4, "");
1572
1573 LLVMValueRef final_sample =
1574 LLVMBuildAnd(gallivm->builder, shifted_fmask, F, "");
1575
1576 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
1577 * resource descriptor is 0 (invalid),
1578 */
1579 LLVMValueRef fmask_desc =
1580 LLVMBuildBitCast(gallivm->builder, fmask_ptr,
1581 ctx->v8i32, "");
1582
1583 LLVMValueRef fmask_word1 =
1584 LLVMBuildExtractElement(gallivm->builder, fmask_desc,
1585 ctx->i32_1, "");
1586
1587 LLVMValueRef word1_is_nonzero =
1588 LLVMBuildICmp(gallivm->builder, LLVMIntNE,
1589 fmask_word1, ctx->i32_0, "");
1590
1591 /* Replace the MSAA sample index. */
1592 address[sample_chan] =
1593 LLVMBuildSelect(gallivm->builder, word1_is_nonzero,
1594 final_sample, address[sample_chan], "");
1595 }
1596
1597 if (opcode == TGSI_OPCODE_TXF ||
1598 opcode == TGSI_OPCODE_TXF_LZ) {
1599 /* add tex offsets */
1600 if (inst->Texture.NumOffsets) {
1601 struct lp_build_context *uint_bld = &bld_base->uint_bld;
1602 const struct tgsi_texture_offset *off = inst->TexOffsets;
1603
1604 assert(inst->Texture.NumOffsets == 1);
1605
1606 switch (target) {
1607 case TGSI_TEXTURE_3D:
1608 address[2] = lp_build_add(uint_bld, address[2],
1609 ctx->imms[off->Index * TGSI_NUM_CHANNELS + off->SwizzleZ]);
1610 /* fall through */
1611 case TGSI_TEXTURE_2D:
1612 case TGSI_TEXTURE_SHADOW2D:
1613 case TGSI_TEXTURE_RECT:
1614 case TGSI_TEXTURE_SHADOWRECT:
1615 case TGSI_TEXTURE_2D_ARRAY:
1616 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1617 address[1] =
1618 lp_build_add(uint_bld, address[1],
1619 ctx->imms[off->Index * TGSI_NUM_CHANNELS + off->SwizzleY]);
1620 /* fall through */
1621 case TGSI_TEXTURE_1D:
1622 case TGSI_TEXTURE_SHADOW1D:
1623 case TGSI_TEXTURE_1D_ARRAY:
1624 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1625 address[0] =
1626 lp_build_add(uint_bld, address[0],
1627 ctx->imms[off->Index * TGSI_NUM_CHANNELS + off->SwizzleX]);
1628 break;
1629 /* texture offsets do not apply to other texture targets */
1630 }
1631 }
1632 }
1633
1634 if (opcode == TGSI_OPCODE_TG4) {
1635 unsigned gather_comp = 0;
1636
1637 /* DMASK was repurposed for GATHER4. 4 components are always
1638 * returned and DMASK works like a swizzle - it selects
1639 * the component to fetch. The only valid DMASK values are
1640 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
1641 * (red,red,red,red) etc.) The ISA document doesn't mention
1642 * this.
1643 */
1644
1645 /* Get the component index from src1.x for Gather4. */
1646 if (!tgsi_is_shadow_target(target)) {
1647 LLVMValueRef comp_imm;
1648 struct tgsi_src_register src1 = inst->Src[1].Register;
1649
1650 assert(src1.File == TGSI_FILE_IMMEDIATE);
1651
1652 comp_imm = ctx->imms[src1.Index * TGSI_NUM_CHANNELS + src1.SwizzleX];
1653 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
1654 gather_comp = CLAMP(gather_comp, 0, 3);
1655 }
1656
1657 dmask = 1 << gather_comp;
1658 }
1659
1660 set_tex_fetch_args(ctx, emit_data, target, res_ptr,
1661 samp_ptr, address, count, dmask);
1662 }
1663
1664 /* Gather4 should follow the same rules as bilinear filtering, but the hardware
1665 * incorrectly forces nearest filtering if the texture format is integer.
1666 * The only effect it has on Gather4, which always returns 4 texels for
1667 * bilinear filtering, is that the final coordinates are off by 0.5 of
1668 * the texel size.
1669 *
1670 * The workaround is to subtract 0.5 from the unnormalized coordinates,
1671 * or (0.5 / size) from the normalized coordinates.
1672 */
1673 static void si_lower_gather4_integer(struct si_shader_context *ctx,
1674 struct ac_image_args *args,
1675 unsigned target)
1676 {
1677 LLVMBuilderRef builder = ctx->gallivm.builder;
1678 LLVMValueRef coord = args->addr;
1679 LLVMValueRef half_texel[2];
1680 /* Texture coordinates start after:
1681 * {offset, bias, z-compare, derivatives}
1682 * Only the offset and z-compare can occur here.
1683 */
1684 unsigned coord_vgpr_index = (int)args->offset + (int)args->compare;
1685 int c;
1686
1687 if (target == TGSI_TEXTURE_RECT ||
1688 target == TGSI_TEXTURE_SHADOWRECT) {
1689 half_texel[0] = half_texel[1] = LLVMConstReal(ctx->f32, -0.5);
1690 } else {
1691 struct tgsi_full_instruction txq_inst = {};
1692 struct lp_build_emit_data txq_emit_data = {};
1693
1694 /* Query the texture size. */
1695 txq_inst.Texture.Texture = target;
1696 txq_emit_data.inst = &txq_inst;
1697 txq_emit_data.dst_type = ctx->v4i32;
1698 set_tex_fetch_args(ctx, &txq_emit_data, target,
1699 args->resource, NULL, &ctx->i32_0,
1700 1, 0xf);
1701 txq_emit(NULL, &ctx->bld_base, &txq_emit_data);
1702
1703 /* Compute -0.5 / size. */
1704 for (c = 0; c < 2; c++) {
1705 half_texel[c] =
1706 LLVMBuildExtractElement(builder, txq_emit_data.output[0],
1707 LLVMConstInt(ctx->i32, c, 0), "");
1708 half_texel[c] = LLVMBuildUIToFP(builder, half_texel[c], ctx->f32, "");
1709 half_texel[c] =
1710 lp_build_emit_llvm_unary(&ctx->bld_base,
1711 TGSI_OPCODE_RCP, half_texel[c]);
1712 half_texel[c] = LLVMBuildFMul(builder, half_texel[c],
1713 LLVMConstReal(ctx->f32, -0.5), "");
1714 }
1715 }
1716
1717 for (c = 0; c < 2; c++) {
1718 LLVMValueRef tmp;
1719 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
1720
1721 tmp = LLVMBuildExtractElement(builder, coord, index, "");
1722 tmp = LLVMBuildBitCast(builder, tmp, ctx->f32, "");
1723 tmp = LLVMBuildFAdd(builder, tmp, half_texel[c], "");
1724 tmp = LLVMBuildBitCast(builder, tmp, ctx->i32, "");
1725 coord = LLVMBuildInsertElement(builder, coord, tmp, index, "");
1726 }
1727
1728 args->addr = coord;
1729 }
1730
1731 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
1732 struct lp_build_tgsi_context *bld_base,
1733 struct lp_build_emit_data *emit_data)
1734 {
1735 struct si_shader_context *ctx = si_shader_context(bld_base);
1736 const struct tgsi_full_instruction *inst = emit_data->inst;
1737 struct ac_image_args args;
1738 unsigned opcode = inst->Instruction.Opcode;
1739 unsigned target = inst->Texture.Texture;
1740
1741 if (target == TGSI_TEXTURE_BUFFER) {
1742 emit_data->output[emit_data->chan] =
1743 ac_build_buffer_load_format(&ctx->ac,
1744 emit_data->args[0],
1745 emit_data->args[2],
1746 emit_data->args[1],
1747 true);
1748 return;
1749 }
1750
1751 memcpy(&args, emit_data->args, sizeof(args)); /* ugly */
1752
1753 args.opcode = ac_image_sample;
1754 args.compare = tgsi_is_shadow_target(target);
1755 args.offset = inst->Texture.NumOffsets > 0;
1756
1757 switch (opcode) {
1758 case TGSI_OPCODE_TXF:
1759 case TGSI_OPCODE_TXF_LZ:
1760 args.opcode = opcode == TGSI_OPCODE_TXF_LZ ||
1761 target == TGSI_TEXTURE_2D_MSAA ||
1762 target == TGSI_TEXTURE_2D_ARRAY_MSAA ?
1763 ac_image_load : ac_image_load_mip;
1764 args.compare = false;
1765 args.offset = false;
1766 break;
1767 case TGSI_OPCODE_LODQ:
1768 args.opcode = ac_image_get_lod;
1769 args.compare = false;
1770 args.offset = false;
1771 break;
1772 case TGSI_OPCODE_TEX:
1773 case TGSI_OPCODE_TEX2:
1774 case TGSI_OPCODE_TXP:
1775 if (ctx->type != PIPE_SHADER_FRAGMENT)
1776 args.level_zero = true;
1777 break;
1778 case TGSI_OPCODE_TEX_LZ:
1779 args.level_zero = true;
1780 break;
1781 case TGSI_OPCODE_TXB:
1782 case TGSI_OPCODE_TXB2:
1783 assert(ctx->type == PIPE_SHADER_FRAGMENT);
1784 args.bias = true;
1785 break;
1786 case TGSI_OPCODE_TXL:
1787 case TGSI_OPCODE_TXL2:
1788 args.lod = true;
1789 break;
1790 case TGSI_OPCODE_TXD:
1791 args.deriv = true;
1792 break;
1793 case TGSI_OPCODE_TG4:
1794 args.opcode = ac_image_gather4;
1795 args.level_zero = true;
1796 break;
1797 default:
1798 assert(0);
1799 return;
1800 }
1801
1802 /* The hardware needs special lowering for Gather4 with integer formats. */
1803 if (ctx->screen->b.chip_class <= VI &&
1804 opcode == TGSI_OPCODE_TG4) {
1805 assert(inst->Texture.ReturnType != TGSI_RETURN_TYPE_UNKNOWN);
1806
1807 if (inst->Texture.ReturnType == TGSI_RETURN_TYPE_SINT ||
1808 inst->Texture.ReturnType == TGSI_RETURN_TYPE_UINT)
1809 si_lower_gather4_integer(ctx, &args, target);
1810 }
1811
1812 emit_data->output[emit_data->chan] =
1813 ac_build_image_opcode(&ctx->ac, &args);
1814 }
1815
1816 static void si_llvm_emit_txqs(
1817 const struct lp_build_tgsi_action *action,
1818 struct lp_build_tgsi_context *bld_base,
1819 struct lp_build_emit_data *emit_data)
1820 {
1821 struct si_shader_context *ctx = si_shader_context(bld_base);
1822 struct gallivm_state *gallivm = &ctx->gallivm;
1823 LLVMBuilderRef builder = gallivm->builder;
1824 LLVMValueRef res, samples;
1825 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
1826
1827 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
1828
1829
1830 /* Read the samples from the descriptor directly. */
1831 res = LLVMBuildBitCast(builder, res_ptr, ctx->v8i32, "");
1832 samples = LLVMBuildExtractElement(
1833 builder, res,
1834 LLVMConstInt(ctx->i32, 3, 0), "");
1835 samples = LLVMBuildLShr(builder, samples,
1836 LLVMConstInt(ctx->i32, 16, 0), "");
1837 samples = LLVMBuildAnd(builder, samples,
1838 LLVMConstInt(ctx->i32, 0xf, 0), "");
1839 samples = LLVMBuildShl(builder, ctx->i32_1,
1840 samples, "");
1841
1842 emit_data->output[emit_data->chan] = samples;
1843 }
1844
1845 static const struct lp_build_tgsi_action tex_action = {
1846 .fetch_args = tex_fetch_args,
1847 .emit = build_tex_intrinsic,
1848 };
1849
1850 /**
1851 * Setup actions for TGSI memory opcode, including texture opcodes.
1852 */
1853 void si_shader_context_init_mem(struct si_shader_context *ctx)
1854 {
1855 struct lp_build_tgsi_context *bld_base;
1856 struct lp_build_tgsi_action tmpl = {};
1857
1858 bld_base = &ctx->bld_base;
1859
1860 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
1861 bld_base->op_actions[TGSI_OPCODE_TEX_LZ] = tex_action;
1862 bld_base->op_actions[TGSI_OPCODE_TEX2] = tex_action;
1863 bld_base->op_actions[TGSI_OPCODE_TXB] = tex_action;
1864 bld_base->op_actions[TGSI_OPCODE_TXB2] = tex_action;
1865 bld_base->op_actions[TGSI_OPCODE_TXD] = tex_action;
1866 bld_base->op_actions[TGSI_OPCODE_TXF] = tex_action;
1867 bld_base->op_actions[TGSI_OPCODE_TXF_LZ] = tex_action;
1868 bld_base->op_actions[TGSI_OPCODE_TXL] = tex_action;
1869 bld_base->op_actions[TGSI_OPCODE_TXL2] = tex_action;
1870 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
1871 bld_base->op_actions[TGSI_OPCODE_TXQ].fetch_args = txq_fetch_args;
1872 bld_base->op_actions[TGSI_OPCODE_TXQ].emit = txq_emit;
1873 bld_base->op_actions[TGSI_OPCODE_TG4] = tex_action;
1874 bld_base->op_actions[TGSI_OPCODE_LODQ] = tex_action;
1875 bld_base->op_actions[TGSI_OPCODE_TXQS].emit = si_llvm_emit_txqs;
1876
1877 bld_base->op_actions[TGSI_OPCODE_LOAD].fetch_args = load_fetch_args;
1878 bld_base->op_actions[TGSI_OPCODE_LOAD].emit = load_emit;
1879 bld_base->op_actions[TGSI_OPCODE_STORE].fetch_args = store_fetch_args;
1880 bld_base->op_actions[TGSI_OPCODE_STORE].emit = store_emit;
1881 bld_base->op_actions[TGSI_OPCODE_RESQ].fetch_args = resq_fetch_args;
1882 bld_base->op_actions[TGSI_OPCODE_RESQ].emit = resq_emit;
1883
1884 tmpl.fetch_args = atomic_fetch_args;
1885 tmpl.emit = atomic_emit;
1886 bld_base->op_actions[TGSI_OPCODE_ATOMUADD] = tmpl;
1887 bld_base->op_actions[TGSI_OPCODE_ATOMUADD].intr_name = "add";
1888 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG] = tmpl;
1889 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG].intr_name = "swap";
1890 bld_base->op_actions[TGSI_OPCODE_ATOMCAS] = tmpl;
1891 bld_base->op_actions[TGSI_OPCODE_ATOMCAS].intr_name = "cmpswap";
1892 bld_base->op_actions[TGSI_OPCODE_ATOMAND] = tmpl;
1893 bld_base->op_actions[TGSI_OPCODE_ATOMAND].intr_name = "and";
1894 bld_base->op_actions[TGSI_OPCODE_ATOMOR] = tmpl;
1895 bld_base->op_actions[TGSI_OPCODE_ATOMOR].intr_name = "or";
1896 bld_base->op_actions[TGSI_OPCODE_ATOMXOR] = tmpl;
1897 bld_base->op_actions[TGSI_OPCODE_ATOMXOR].intr_name = "xor";
1898 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN] = tmpl;
1899 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN].intr_name = "umin";
1900 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX] = tmpl;
1901 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX].intr_name = "umax";
1902 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN] = tmpl;
1903 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN].intr_name = "smin";
1904 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX] = tmpl;
1905 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX].intr_name = "smax";
1906 }