2 * Copyright 2017 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "si_shader_internal.h"
28 #include "tgsi/tgsi_build.h"
29 #include "tgsi/tgsi_util.h"
30 #include "ac_llvm_util.h"
32 static void tex_fetch_ptrs(struct lp_build_tgsi_context
*bld_base
,
33 struct lp_build_emit_data
*emit_data
,
34 LLVMValueRef
*res_ptr
, LLVMValueRef
*samp_ptr
,
35 LLVMValueRef
*fmask_ptr
);
38 * Given a v8i32 resource descriptor for a buffer, extract the size of the
39 * buffer in number of elements and return it as an i32.
41 static LLVMValueRef
get_buffer_size(
42 struct lp_build_tgsi_context
*bld_base
,
43 LLVMValueRef descriptor
)
45 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
46 LLVMBuilderRef builder
= ctx
->ac
.builder
;
48 LLVMBuildExtractElement(builder
, descriptor
,
49 LLVMConstInt(ctx
->i32
, 2, 0), "");
51 if (ctx
->screen
->info
.chip_class
== GFX8
) {
52 /* On GFX8, the descriptor contains the size in bytes,
53 * but TXQ must return the size in elements.
54 * The stride is always non-zero for resources using TXQ.
57 LLVMBuildExtractElement(builder
, descriptor
,
59 stride
= LLVMBuildLShr(builder
, stride
,
60 LLVMConstInt(ctx
->i32
, 16, 0), "");
61 stride
= LLVMBuildAnd(builder
, stride
,
62 LLVMConstInt(ctx
->i32
, 0x3FFF, 0), "");
64 size
= LLVMBuildUDiv(builder
, size
, stride
, "");
71 shader_buffer_fetch_rsrc(struct si_shader_context
*ctx
,
72 const struct tgsi_full_src_register
*reg
,
77 if (!reg
->Register
.Indirect
) {
78 index
= LLVMConstInt(ctx
->i32
, reg
->Register
.Index
, false);
80 index
= si_get_indirect_index(ctx
, ®
->Indirect
,
81 1, reg
->Register
.Index
);
85 return ctx
->abi
.load_ubo(&ctx
->abi
, index
);
87 return ctx
->abi
.load_ssbo(&ctx
->abi
, index
, false);
90 static enum ac_image_dim
91 ac_texture_dim_from_tgsi_target(struct si_screen
*screen
, enum tgsi_texture_type target
)
95 case TGSI_TEXTURE_SHADOW1D
:
96 if (screen
->info
.chip_class
>= GFX9
)
100 case TGSI_TEXTURE_SHADOW2D
:
101 case TGSI_TEXTURE_RECT
:
102 case TGSI_TEXTURE_SHADOWRECT
:
104 case TGSI_TEXTURE_3D
:
106 case TGSI_TEXTURE_CUBE
:
107 case TGSI_TEXTURE_SHADOWCUBE
:
108 case TGSI_TEXTURE_CUBE_ARRAY
:
109 case TGSI_TEXTURE_SHADOWCUBE_ARRAY
:
110 return ac_image_cube
;
111 case TGSI_TEXTURE_1D_ARRAY
:
112 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
113 if (screen
->info
.chip_class
>= GFX9
)
114 return ac_image_2darray
;
115 return ac_image_1darray
;
116 case TGSI_TEXTURE_2D_ARRAY
:
117 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
118 return ac_image_2darray
;
119 case TGSI_TEXTURE_2D_MSAA
:
120 return ac_image_2dmsaa
;
121 case TGSI_TEXTURE_2D_ARRAY_MSAA
:
122 return ac_image_2darraymsaa
;
124 unreachable("unhandled texture type");
128 static enum ac_image_dim
129 ac_image_dim_from_tgsi_target(struct si_screen
*screen
, enum tgsi_texture_type target
)
131 enum ac_image_dim dim
= ac_texture_dim_from_tgsi_target(screen
, target
);
133 /* Match the resource type set in the descriptor. */
134 if (dim
== ac_image_cube
||
135 (screen
->info
.chip_class
<= GFX8
&& dim
== ac_image_3d
))
136 dim
= ac_image_2darray
;
137 else if (target
== TGSI_TEXTURE_2D
&& screen
->info
.chip_class
>= GFX9
) {
138 /* When a single layer of a 3D texture is bound, the shader
139 * will refer to a 2D target, but the descriptor has a 3D type.
140 * Since the HW ignores BASE_ARRAY in this case, we need to
141 * send 3 coordinates. This doesn't hurt when the underlying
151 * Given a 256-bit resource descriptor, force the DCC enable bit to off.
153 * At least on Tonga, executing image stores on images with DCC enabled and
154 * non-trivial can eventually lead to lockups. This can occur when an
155 * application binds an image as read-only but then uses a shader that writes
156 * to it. The OpenGL spec allows almost arbitrarily bad behavior (including
157 * program termination) in this case, but it doesn't cost much to be a bit
158 * nicer: disabling DCC in the shader still leads to undefined results but
161 static LLVMValueRef
force_dcc_off(struct si_shader_context
*ctx
,
164 if (ctx
->screen
->info
.chip_class
<= GFX7
) {
167 LLVMValueRef i32_6
= LLVMConstInt(ctx
->i32
, 6, 0);
168 LLVMValueRef i32_C
= LLVMConstInt(ctx
->i32
, C_008F28_COMPRESSION_EN
, 0);
171 tmp
= LLVMBuildExtractElement(ctx
->ac
.builder
, rsrc
, i32_6
, "");
172 tmp
= LLVMBuildAnd(ctx
->ac
.builder
, tmp
, i32_C
, "");
173 return LLVMBuildInsertElement(ctx
->ac
.builder
, rsrc
, tmp
, i32_6
, "");
177 LLVMValueRef
si_load_image_desc(struct si_shader_context
*ctx
,
178 LLVMValueRef list
, LLVMValueRef index
,
179 enum ac_descriptor_type desc_type
, bool dcc_off
,
182 LLVMBuilderRef builder
= ctx
->ac
.builder
;
185 if (desc_type
== AC_DESC_BUFFER
) {
186 index
= ac_build_imad(&ctx
->ac
, index
, LLVMConstInt(ctx
->i32
, 2, 0),
188 list
= LLVMBuildPointerCast(builder
, list
,
189 ac_array_in_const32_addr_space(ctx
->v4i32
), "");
191 assert(desc_type
== AC_DESC_IMAGE
);
195 rsrc
= ac_build_load_to_sgpr_uint_wraparound(&ctx
->ac
, list
, index
);
197 rsrc
= ac_build_load_to_sgpr(&ctx
->ac
, list
, index
);
199 if (desc_type
== AC_DESC_IMAGE
&& dcc_off
)
200 rsrc
= force_dcc_off(ctx
, rsrc
);
205 * Load the resource descriptor for \p image.
209 struct lp_build_tgsi_context
*bld_base
,
210 const struct tgsi_full_src_register
*image
,
211 bool is_store
, unsigned target
,
214 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
215 LLVMValueRef rsrc_ptr
= LLVMGetParam(ctx
->main_fn
,
216 ctx
->param_samplers_and_images
);
218 bool dcc_off
= is_store
;
220 if (!image
->Register
.Indirect
) {
221 index
= LLVMConstInt(ctx
->i32
,
222 si_get_image_slot(image
->Register
.Index
), 0);
224 /* From the GL_ARB_shader_image_load_store extension spec:
226 * If a shader performs an image load, store, or atomic
227 * operation using an image variable declared as an array,
228 * and if the index used to select an individual element is
229 * negative or greater than or equal to the size of the
230 * array, the results of the operation are undefined but may
231 * not lead to termination.
233 index
= si_get_bounded_indirect_index(ctx
, &image
->Indirect
,
234 image
->Register
.Index
,
236 index
= LLVMBuildSub(ctx
->ac
.builder
,
237 LLVMConstInt(ctx
->i32
, SI_NUM_IMAGES
- 1, 0),
241 bool bindless
= false;
243 if (image
->Register
.File
!= TGSI_FILE_IMAGE
) {
244 /* Bindless descriptors are accessible from a different pair of
247 rsrc_ptr
= LLVMGetParam(ctx
->main_fn
,
248 ctx
->param_bindless_samplers_and_images
);
249 index
= lp_build_emit_fetch_src(bld_base
, image
,
250 TGSI_TYPE_UNSIGNED
, 0);
252 /* For simplicity, bindless image descriptors use fixed
253 * 16-dword slots for now.
255 index
= LLVMBuildMul(ctx
->ac
.builder
, index
,
256 LLVMConstInt(ctx
->i32
, 2, 0), "");
260 *rsrc
= si_load_image_desc(ctx
, rsrc_ptr
, index
,
261 target
== TGSI_TEXTURE_BUFFER
? AC_DESC_BUFFER
: AC_DESC_IMAGE
,
265 static void image_fetch_coords(
266 struct lp_build_tgsi_context
*bld_base
,
267 const struct tgsi_full_instruction
*inst
,
268 unsigned src
, LLVMValueRef desc
,
269 LLVMValueRef
*coords
)
271 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
272 LLVMBuilderRef builder
= ctx
->ac
.builder
;
273 unsigned target
= inst
->Memory
.Texture
;
274 unsigned num_coords
= tgsi_util_get_texture_coord_dim(target
);
278 if (target
== TGSI_TEXTURE_2D_MSAA
||
279 target
== TGSI_TEXTURE_2D_ARRAY_MSAA
) {
280 /* Need the sample index as well. */
284 for (chan
= 0; chan
< num_coords
; ++chan
) {
285 tmp
= lp_build_emit_fetch(bld_base
, inst
, src
, chan
);
286 tmp
= ac_to_integer(&ctx
->ac
, tmp
);
290 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
291 /* 1D textures are allocated and used as 2D on GFX9. */
292 if (target
== TGSI_TEXTURE_1D
) {
293 coords
[1] = ctx
->i32_0
;
294 } else if (target
== TGSI_TEXTURE_1D_ARRAY
) {
295 coords
[2] = coords
[1];
296 coords
[1] = ctx
->i32_0
;
297 } else if (target
== TGSI_TEXTURE_2D
) {
298 /* The hw can't bind a slice of a 3D image as a 2D
299 * image, because it ignores BASE_ARRAY if the target
300 * is 3D. The workaround is to read BASE_ARRAY and set
301 * it as the 3rd address operand for all 2D images.
303 LLVMValueRef first_layer
, const5
, mask
;
305 const5
= LLVMConstInt(ctx
->i32
, 5, 0);
306 mask
= LLVMConstInt(ctx
->i32
, S_008F24_BASE_ARRAY(~0), 0);
307 first_layer
= LLVMBuildExtractElement(builder
, desc
, const5
, "");
308 first_layer
= LLVMBuildAnd(builder
, first_layer
, mask
, "");
310 coords
[2] = first_layer
;
315 static unsigned get_cache_policy(struct si_shader_context
*ctx
,
316 const struct tgsi_full_instruction
*inst
,
317 bool atomic
, bool may_store_unaligned
,
318 bool writeonly_memory
)
320 unsigned cache_policy
= 0;
323 /* GFX6 has a TC L1 bug causing corruption of 8bit/16bit stores.
324 * All store opcodes not aligned to a dword are affected.
325 * The only way to get unaligned stores in radeonsi is through
327 ((may_store_unaligned
&& ctx
->screen
->info
.chip_class
== GFX6
) ||
328 /* If this is write-only, don't keep data in L1 to prevent
329 * evicting L1 cache lines that may be needed by other
332 inst
->Memory
.Qualifier
& (TGSI_MEMORY_COHERENT
| TGSI_MEMORY_VOLATILE
)))
333 cache_policy
|= ac_glc
;
335 if (inst
->Memory
.Qualifier
& TGSI_MEMORY_STREAM_CACHE_POLICY
)
336 cache_policy
|= ac_slc
;
341 static LLVMValueRef
get_memory_ptr(struct si_shader_context
*ctx
,
342 const struct tgsi_full_instruction
*inst
,
343 LLVMTypeRef type
, int arg
)
345 LLVMBuilderRef builder
= ctx
->ac
.builder
;
346 LLVMValueRef offset
, ptr
;
349 offset
= lp_build_emit_fetch(&ctx
->bld_base
, inst
, arg
, 0);
350 offset
= ac_to_integer(&ctx
->ac
, offset
);
353 ptr
= LLVMBuildGEP(builder
, ptr
, &offset
, 1, "");
354 addr_space
= LLVMGetPointerAddressSpace(LLVMTypeOf(ptr
));
355 ptr
= LLVMBuildBitCast(builder
, ptr
, LLVMPointerType(type
, addr_space
), "");
360 static void load_emit_memory(
361 struct si_shader_context
*ctx
,
362 struct lp_build_emit_data
*emit_data
)
364 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
365 unsigned writemask
= inst
->Dst
[0].Register
.WriteMask
;
366 LLVMValueRef channels
[4], ptr
, derived_ptr
, index
;
369 ptr
= get_memory_ptr(ctx
, inst
, ctx
->f32
, 1);
371 for (chan
= 0; chan
< 4; ++chan
) {
372 if (!(writemask
& (1 << chan
))) {
373 channels
[chan
] = LLVMGetUndef(ctx
->f32
);
377 index
= LLVMConstInt(ctx
->i32
, chan
, 0);
378 derived_ptr
= LLVMBuildGEP(ctx
->ac
.builder
, ptr
, &index
, 1, "");
379 channels
[chan
] = LLVMBuildLoad(ctx
->ac
.builder
, derived_ptr
, "");
381 emit_data
->output
[emit_data
->chan
] = ac_build_gather_values(&ctx
->ac
, channels
, 4);
385 * Return true if the memory accessed by a LOAD or STORE instruction is
386 * read-only or write-only, respectively.
388 * \param shader_buffers_reverse_access_mask
389 * For LOAD, set this to (store | atomic) slot usage in the shader.
390 * For STORE, set this to (load | atomic) slot usage in the shader.
391 * \param images_reverse_access_mask Same as above, but for images.
392 * \param bindless_buffer_reverse_access_mask Same as above, but for bindless image buffers.
393 * \param bindless_image_reverse_access_mask Same as above, but for bindless images.
395 static bool is_oneway_access_only(const struct tgsi_full_instruction
*inst
,
396 const struct tgsi_shader_info
*info
,
397 unsigned shader_buffers_reverse_access_mask
,
398 unsigned images_reverse_access_mask
,
399 bool bindless_buffer_reverse_access_mask
,
400 bool bindless_image_reverse_access_mask
)
402 enum tgsi_file_type resource_file
;
403 unsigned resource_index
;
404 bool resource_indirect
;
406 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_STORE
) {
407 resource_file
= inst
->Dst
[0].Register
.File
;
408 resource_index
= inst
->Dst
[0].Register
.Index
;
409 resource_indirect
= inst
->Dst
[0].Register
.Indirect
;
411 resource_file
= inst
->Src
[0].Register
.File
;
412 resource_index
= inst
->Src
[0].Register
.Index
;
413 resource_indirect
= inst
->Src
[0].Register
.Indirect
;
416 assert(resource_file
== TGSI_FILE_BUFFER
||
417 resource_file
== TGSI_FILE_IMAGE
||
419 resource_file
== TGSI_FILE_INPUT
||
420 resource_file
== TGSI_FILE_OUTPUT
||
421 resource_file
== TGSI_FILE_CONSTANT
||
422 resource_file
== TGSI_FILE_TEMPORARY
||
423 resource_file
== TGSI_FILE_IMMEDIATE
);
425 assert(resource_file
!= TGSI_FILE_BUFFER
||
426 inst
->Memory
.Texture
== TGSI_TEXTURE_BUFFER
);
428 bool bindless
= resource_file
!= TGSI_FILE_BUFFER
&&
429 resource_file
!= TGSI_FILE_IMAGE
;
431 /* RESTRICT means NOALIAS.
432 * If there are no writes, we can assume the accessed memory is read-only.
433 * If there are no reads, we can assume the accessed memory is write-only.
435 if (inst
->Memory
.Qualifier
& TGSI_MEMORY_RESTRICT
&& !bindless
) {
436 unsigned reverse_access_mask
;
438 if (resource_file
== TGSI_FILE_BUFFER
) {
439 reverse_access_mask
= shader_buffers_reverse_access_mask
;
440 } else if (inst
->Memory
.Texture
== TGSI_TEXTURE_BUFFER
) {
441 reverse_access_mask
= info
->images_buffers
&
442 images_reverse_access_mask
;
444 reverse_access_mask
= ~info
->images_buffers
&
445 images_reverse_access_mask
;
448 if (resource_indirect
) {
449 if (!reverse_access_mask
)
452 if (!(reverse_access_mask
&
453 (1u << resource_index
)))
458 /* If there are no buffer writes (for both shader buffers & image
459 * buffers), it implies that buffer memory is read-only.
460 * If there are no buffer reads (for both shader buffers & image
461 * buffers), it implies that buffer memory is write-only.
463 * Same for the case when there are no writes/reads for non-buffer
466 if (resource_file
== TGSI_FILE_BUFFER
||
467 inst
->Memory
.Texture
== TGSI_TEXTURE_BUFFER
) {
468 if (!shader_buffers_reverse_access_mask
&&
469 !(info
->images_buffers
& images_reverse_access_mask
) &&
470 !bindless_buffer_reverse_access_mask
)
473 if (!(~info
->images_buffers
& images_reverse_access_mask
) &&
474 !bindless_image_reverse_access_mask
)
480 static void load_emit(
481 const struct lp_build_tgsi_action
*action
,
482 struct lp_build_tgsi_context
*bld_base
,
483 struct lp_build_emit_data
*emit_data
)
485 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
486 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
487 const struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
488 bool can_speculate
= false;
489 LLVMValueRef vindex
= ctx
->i32_0
;
490 LLVMValueRef voffset
= ctx
->i32_0
;
491 struct ac_image_args args
= {};
493 if (inst
->Src
[0].Register
.File
== TGSI_FILE_MEMORY
) {
494 load_emit_memory(ctx
, emit_data
);
498 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
||
499 inst
->Src
[0].Register
.File
== TGSI_FILE_CONSTBUF
) {
500 bool ubo
= inst
->Src
[0].Register
.File
== TGSI_FILE_CONSTBUF
;
501 args
.resource
= shader_buffer_fetch_rsrc(ctx
, &inst
->Src
[0], ubo
);
502 voffset
= ac_to_integer(&ctx
->ac
, lp_build_emit_fetch(bld_base
, inst
, 1, 0));
504 unsigned target
= inst
->Memory
.Texture
;
506 image_fetch_rsrc(bld_base
, &inst
->Src
[0], false, target
, &args
.resource
);
507 image_fetch_coords(bld_base
, inst
, 1, args
.resource
, args
.coords
);
508 vindex
= args
.coords
[0]; /* for buffers only */
511 if (inst
->Src
[0].Register
.File
== TGSI_FILE_CONSTBUF
) {
512 emit_data
->output
[emit_data
->chan
] =
513 ac_build_buffer_load(&ctx
->ac
, args
.resource
,
514 util_last_bit(inst
->Dst
[0].Register
.WriteMask
),
515 NULL
, voffset
, NULL
, 0, 0, 0, true, true);
519 if (inst
->Memory
.Qualifier
& TGSI_MEMORY_VOLATILE
)
520 ac_build_waitcnt(&ctx
->ac
, VM_CNT
);
522 can_speculate
= !(inst
->Memory
.Qualifier
& TGSI_MEMORY_VOLATILE
) &&
523 is_oneway_access_only(inst
, info
,
524 info
->shader_buffers_store
|
525 info
->shader_buffers_atomic
,
528 info
->uses_bindless_buffer_store
|
529 info
->uses_bindless_buffer_atomic
,
530 info
->uses_bindless_image_store
|
531 info
->uses_bindless_image_atomic
);
532 args
.cache_policy
= get_cache_policy(ctx
, inst
, false, false, false);
534 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
) {
535 /* Don't use SMEM for shader buffer loads, because LLVM doesn't
536 * select SMEM for SI.load.const with a non-constant offset, and
537 * constant offsets practically don't exist with shader buffers.
539 * Also, SI.load.const doesn't use inst_offset when it's lowered
540 * to VMEM, so we just end up with more VALU instructions in the end
543 * TODO: Remove this line once LLVM can select SMEM with a non-constant
544 * offset, and can derive inst_offset when VMEM is selected.
545 * After that, si_memory_barrier should invalidate sL1 for shader
548 emit_data
->output
[emit_data
->chan
] =
549 ac_build_buffer_load(&ctx
->ac
, args
.resource
,
550 util_last_bit(inst
->Dst
[0].Register
.WriteMask
),
551 NULL
, voffset
, NULL
, 0,
552 !!(args
.cache_policy
& ac_glc
),
553 !!(args
.cache_policy
& ac_slc
),
554 can_speculate
, false);
558 if (inst
->Memory
.Texture
== TGSI_TEXTURE_BUFFER
) {
559 unsigned num_channels
= util_last_bit(inst
->Dst
[0].Register
.WriteMask
);
560 LLVMValueRef result
=
561 ac_build_buffer_load_format(&ctx
->ac
,
566 !!(args
.cache_policy
& ac_glc
),
568 emit_data
->output
[emit_data
->chan
] =
569 ac_build_expand_to_vec4(&ctx
->ac
, result
, num_channels
);
571 args
.opcode
= ac_image_load
;
572 args
.dim
= ac_image_dim_from_tgsi_target(ctx
->screen
, inst
->Memory
.Texture
);
573 args
.attributes
= ac_get_load_intr_attribs(can_speculate
);
576 emit_data
->output
[emit_data
->chan
] =
577 ac_build_image_opcode(&ctx
->ac
, &args
);
581 static void store_emit_buffer(struct si_shader_context
*ctx
,
582 LLVMValueRef resource
,
585 LLVMValueRef voffset
,
586 unsigned cache_policy
,
587 bool writeonly_memory
)
589 LLVMBuilderRef builder
= ctx
->ac
.builder
;
590 LLVMValueRef base_data
= value
;
591 LLVMValueRef base_offset
= voffset
;
595 LLVMValueRef data
, voff
;
597 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
599 if (count
== 3 && ac_has_vec3_support(ctx
->ac
.chip_class
, false)) {
600 LLVMValueRef values
[3] = {
601 LLVMBuildExtractElement(builder
, base_data
,
602 LLVMConstInt(ctx
->i32
, start
, 0), ""),
603 LLVMBuildExtractElement(builder
, base_data
,
604 LLVMConstInt(ctx
->i32
, start
+ 1, 0), ""),
605 LLVMBuildExtractElement(builder
, base_data
,
606 LLVMConstInt(ctx
->i32
, start
+ 2, 0), ""),
608 data
= ac_build_gather_values(&ctx
->ac
, values
, 3);
609 } else if (count
>= 3) {
611 } else if (count
== 2) {
612 LLVMValueRef values
[2] = {
613 LLVMBuildExtractElement(builder
, base_data
,
614 LLVMConstInt(ctx
->i32
, start
, 0), ""),
615 LLVMBuildExtractElement(builder
, base_data
,
616 LLVMConstInt(ctx
->i32
, start
+ 1, 0), ""),
619 data
= ac_build_gather_values(&ctx
->ac
, values
, 2);
622 data
= LLVMBuildExtractElement(
624 LLVMConstInt(ctx
->i32
, start
, 0), "");
631 LLVMConstInt(ctx
->i32
, start
* 4, 0), "");
634 ac_build_buffer_store_dword(&ctx
->ac
, resource
, data
, count
,
636 !!(cache_policy
& ac_glc
),
637 !!(cache_policy
& ac_slc
),
638 writeonly_memory
, false);
642 static void store_emit_memory(
643 struct si_shader_context
*ctx
,
644 struct lp_build_emit_data
*emit_data
)
646 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
647 LLVMBuilderRef builder
= ctx
->ac
.builder
;
648 unsigned writemask
= inst
->Dst
[0].Register
.WriteMask
;
649 LLVMValueRef ptr
, derived_ptr
, data
, index
;
652 ptr
= get_memory_ptr(ctx
, inst
, ctx
->f32
, 0);
654 for (chan
= 0; chan
< 4; ++chan
) {
655 if (!(writemask
& (1 << chan
))) {
658 data
= lp_build_emit_fetch(&ctx
->bld_base
, inst
, 1, chan
);
659 index
= LLVMConstInt(ctx
->i32
, chan
, 0);
660 derived_ptr
= LLVMBuildGEP(builder
, ptr
, &index
, 1, "");
661 LLVMBuildStore(builder
, data
, derived_ptr
);
665 static void store_emit(
666 const struct lp_build_tgsi_action
*action
,
667 struct lp_build_tgsi_context
*bld_base
,
668 struct lp_build_emit_data
*emit_data
)
670 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
671 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
672 const struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
673 struct tgsi_full_src_register resource_reg
=
674 tgsi_full_src_register_from_dst(&inst
->Dst
[0]);
675 unsigned target
= inst
->Memory
.Texture
;
677 if (inst
->Dst
[0].Register
.File
== TGSI_FILE_MEMORY
) {
678 store_emit_memory(ctx
, emit_data
);
682 bool writeonly_memory
= is_oneway_access_only(inst
, info
,
683 info
->shader_buffers_load
|
684 info
->shader_buffers_atomic
,
687 info
->uses_bindless_buffer_load
|
688 info
->uses_bindless_buffer_atomic
,
689 info
->uses_bindless_image_load
|
690 info
->uses_bindless_image_atomic
);
691 LLVMValueRef chans
[4];
692 LLVMValueRef vindex
= ctx
->i32_0
;
693 LLVMValueRef voffset
= ctx
->i32_0
;
694 struct ac_image_args args
= {};
696 for (unsigned chan
= 0; chan
< 4; ++chan
)
697 chans
[chan
] = lp_build_emit_fetch(bld_base
, inst
, 1, chan
);
699 if (inst
->Dst
[0].Register
.File
== TGSI_FILE_BUFFER
) {
700 args
.resource
= shader_buffer_fetch_rsrc(ctx
, &resource_reg
, false);
701 voffset
= ac_to_integer(&ctx
->ac
, lp_build_emit_fetch(bld_base
, inst
, 0, 0));
703 image_fetch_rsrc(bld_base
, &resource_reg
, true, target
, &args
.resource
);
704 image_fetch_coords(bld_base
, inst
, 0, args
.resource
, args
.coords
);
705 vindex
= args
.coords
[0]; /* for buffers only */
708 if (inst
->Memory
.Qualifier
& TGSI_MEMORY_VOLATILE
)
709 ac_build_waitcnt(&ctx
->ac
, VM_CNT
);
711 bool is_image
= inst
->Dst
[0].Register
.File
!= TGSI_FILE_BUFFER
;
712 args
.cache_policy
= get_cache_policy(ctx
, inst
,
714 is_image
, /* may_store_unaligned */
717 if (inst
->Dst
[0].Register
.File
== TGSI_FILE_BUFFER
) {
718 store_emit_buffer(ctx
, args
.resource
, inst
->Dst
[0].Register
.WriteMask
,
719 ac_build_gather_values(&ctx
->ac
, chans
, 4),
720 voffset
, args
.cache_policy
, writeonly_memory
);
724 if (target
== TGSI_TEXTURE_BUFFER
) {
725 unsigned num_channels
= util_last_bit(inst
->Dst
[0].Register
.WriteMask
);
727 ac_build_buffer_store_format(&ctx
->ac
, args
.resource
,
728 ac_build_gather_values(&ctx
->ac
, chans
, num_channels
),
729 vindex
, ctx
->i32_0
/* voffset */,
731 !!(args
.cache_policy
& ac_glc
), false,
734 args
.opcode
= ac_image_store
;
735 args
.data
[0] = ac_build_gather_values(&ctx
->ac
, chans
, 4);
736 args
.dim
= ac_image_dim_from_tgsi_target(ctx
->screen
, inst
->Memory
.Texture
);
737 args
.attributes
= ac_get_store_intr_attribs(writeonly_memory
);
740 emit_data
->output
[emit_data
->chan
] =
741 ac_build_image_opcode(&ctx
->ac
, &args
);
745 static void atomic_emit_memory(struct si_shader_context
*ctx
,
746 struct lp_build_emit_data
*emit_data
) {
747 LLVMBuilderRef builder
= ctx
->ac
.builder
;
748 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
749 LLVMValueRef ptr
, result
, arg
;
750 const char *sync_scope
= HAVE_LLVM
>= 0x0900 ? "workgroup-one-as" : "workgroup";
752 ptr
= get_memory_ptr(ctx
, inst
, ctx
->i32
, 1);
754 arg
= lp_build_emit_fetch(&ctx
->bld_base
, inst
, 2, 0);
755 arg
= ac_to_integer(&ctx
->ac
, arg
);
757 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
) {
758 LLVMValueRef new_data
;
759 new_data
= lp_build_emit_fetch(&ctx
->bld_base
,
762 new_data
= ac_to_integer(&ctx
->ac
, new_data
);
764 result
= ac_build_atomic_cmp_xchg(&ctx
->ac
, ptr
, arg
, new_data
,
766 result
= LLVMBuildExtractValue(builder
, result
, 0, "");
768 LLVMAtomicRMWBinOp op
;
770 switch(inst
->Instruction
.Opcode
) {
771 case TGSI_OPCODE_ATOMUADD
:
772 op
= LLVMAtomicRMWBinOpAdd
;
774 case TGSI_OPCODE_ATOMXCHG
:
775 op
= LLVMAtomicRMWBinOpXchg
;
777 case TGSI_OPCODE_ATOMAND
:
778 op
= LLVMAtomicRMWBinOpAnd
;
780 case TGSI_OPCODE_ATOMOR
:
781 op
= LLVMAtomicRMWBinOpOr
;
783 case TGSI_OPCODE_ATOMXOR
:
784 op
= LLVMAtomicRMWBinOpXor
;
786 case TGSI_OPCODE_ATOMUMIN
:
787 op
= LLVMAtomicRMWBinOpUMin
;
789 case TGSI_OPCODE_ATOMUMAX
:
790 op
= LLVMAtomicRMWBinOpUMax
;
792 case TGSI_OPCODE_ATOMIMIN
:
793 op
= LLVMAtomicRMWBinOpMin
;
795 case TGSI_OPCODE_ATOMIMAX
:
796 op
= LLVMAtomicRMWBinOpMax
;
799 unreachable("unknown atomic opcode");
802 result
= ac_build_atomic_rmw(&ctx
->ac
, op
, ptr
, arg
, sync_scope
);
804 emit_data
->output
[emit_data
->chan
] =
805 LLVMBuildBitCast(builder
, result
, ctx
->f32
, "");
808 static void atomic_emit(
809 const struct lp_build_tgsi_action
*action
,
810 struct lp_build_tgsi_context
*bld_base
,
811 struct lp_build_emit_data
*emit_data
)
813 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
814 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
815 struct ac_image_args args
= {};
816 unsigned num_data
= 0;
817 LLVMValueRef vindex
= ctx
->i32_0
;
818 LLVMValueRef voffset
= ctx
->i32_0
;
820 if (inst
->Src
[0].Register
.File
== TGSI_FILE_MEMORY
) {
821 atomic_emit_memory(ctx
, emit_data
);
825 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
) {
826 /* llvm.amdgcn.image/buffer.atomic.cmpswap reflect the hardware order
827 * of arguments, which is reversed relative to TGSI (and GLSL)
829 args
.data
[num_data
++] =
830 ac_to_integer(&ctx
->ac
, lp_build_emit_fetch(bld_base
, inst
, 3, 0));
833 args
.data
[num_data
++] =
834 ac_to_integer(&ctx
->ac
, lp_build_emit_fetch(bld_base
, inst
, 2, 0));
835 args
.cache_policy
= get_cache_policy(ctx
, inst
, true, false, false);
837 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
) {
838 args
.resource
= shader_buffer_fetch_rsrc(ctx
, &inst
->Src
[0], false);
839 voffset
= ac_to_integer(&ctx
->ac
, lp_build_emit_fetch(bld_base
, inst
, 1, 0));
841 image_fetch_rsrc(bld_base
, &inst
->Src
[0], true,
842 inst
->Memory
.Texture
, &args
.resource
);
843 image_fetch_coords(bld_base
, inst
, 1, args
.resource
, args
.coords
);
844 vindex
= args
.coords
[0]; /* for buffers only */
847 if (HAVE_LLVM
>= 0x0800 &&
848 inst
->Src
[0].Register
.File
!= TGSI_FILE_BUFFER
&&
849 inst
->Memory
.Texture
== TGSI_TEXTURE_BUFFER
) {
850 LLVMValueRef buf_args
[7];
851 unsigned num_args
= 0;
853 buf_args
[num_args
++] = args
.data
[0];
854 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
)
855 buf_args
[num_args
++] = args
.data
[1];
857 buf_args
[num_args
++] = args
.resource
;
858 buf_args
[num_args
++] = vindex
;
859 buf_args
[num_args
++] = voffset
;
860 buf_args
[num_args
++] = ctx
->i32_0
; /* soffset */
861 buf_args
[num_args
++] = LLVMConstInt(ctx
->i32
, args
.cache_policy
& ac_slc
, 0);
863 char intrinsic_name
[64];
864 snprintf(intrinsic_name
, sizeof(intrinsic_name
),
865 "llvm.amdgcn.struct.buffer.atomic.%s", action
->intr_name
);
866 emit_data
->output
[emit_data
->chan
] =
867 ac_to_float(&ctx
->ac
,
868 ac_build_intrinsic(&ctx
->ac
, intrinsic_name
,
869 ctx
->i32
, buf_args
, num_args
, 0));
873 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
||
874 (HAVE_LLVM
< 0x0800 &&
875 inst
->Memory
.Texture
== TGSI_TEXTURE_BUFFER
)) {
876 LLVMValueRef buf_args
[7];
877 unsigned num_args
= 0;
879 buf_args
[num_args
++] = args
.data
[0];
880 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
)
881 buf_args
[num_args
++] = args
.data
[1];
883 buf_args
[num_args
++] = args
.resource
;
884 buf_args
[num_args
++] = vindex
;
885 buf_args
[num_args
++] = voffset
;
886 buf_args
[num_args
++] = args
.cache_policy
& ac_slc
? ctx
->i1true
: ctx
->i1false
;
888 char intrinsic_name
[40];
889 snprintf(intrinsic_name
, sizeof(intrinsic_name
),
890 "llvm.amdgcn.buffer.atomic.%s", action
->intr_name
);
891 emit_data
->output
[emit_data
->chan
] =
892 ac_to_float(&ctx
->ac
,
893 ac_build_intrinsic(&ctx
->ac
, intrinsic_name
,
894 ctx
->i32
, buf_args
, num_args
, 0));
896 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
) {
897 args
.opcode
= ac_image_atomic_cmpswap
;
899 args
.opcode
= ac_image_atomic
;
900 switch (inst
->Instruction
.Opcode
) {
901 case TGSI_OPCODE_ATOMXCHG
: args
.atomic
= ac_atomic_swap
; break;
902 case TGSI_OPCODE_ATOMUADD
: args
.atomic
= ac_atomic_add
; break;
903 case TGSI_OPCODE_ATOMAND
: args
.atomic
= ac_atomic_and
; break;
904 case TGSI_OPCODE_ATOMOR
: args
.atomic
= ac_atomic_or
; break;
905 case TGSI_OPCODE_ATOMXOR
: args
.atomic
= ac_atomic_xor
; break;
906 case TGSI_OPCODE_ATOMUMIN
: args
.atomic
= ac_atomic_umin
; break;
907 case TGSI_OPCODE_ATOMUMAX
: args
.atomic
= ac_atomic_umax
; break;
908 case TGSI_OPCODE_ATOMIMIN
: args
.atomic
= ac_atomic_smin
; break;
909 case TGSI_OPCODE_ATOMIMAX
: args
.atomic
= ac_atomic_smax
; break;
910 default: unreachable("unhandled image atomic");
914 args
.dim
= ac_image_dim_from_tgsi_target(ctx
->screen
, inst
->Memory
.Texture
);
915 emit_data
->output
[emit_data
->chan
] =
916 ac_to_float(&ctx
->ac
, ac_build_image_opcode(&ctx
->ac
, &args
));
920 static LLVMValueRef
fix_resinfo(struct si_shader_context
*ctx
,
921 unsigned target
, LLVMValueRef out
)
923 LLVMBuilderRef builder
= ctx
->ac
.builder
;
925 /* 1D textures are allocated and used as 2D on GFX9. */
926 if (ctx
->screen
->info
.chip_class
>= GFX9
&&
927 (target
== TGSI_TEXTURE_1D_ARRAY
||
928 target
== TGSI_TEXTURE_SHADOW1D_ARRAY
)) {
929 LLVMValueRef layers
=
930 LLVMBuildExtractElement(builder
, out
,
931 LLVMConstInt(ctx
->i32
, 2, 0), "");
932 out
= LLVMBuildInsertElement(builder
, out
, layers
,
936 /* Divide the number of layers by 6 to get the number of cubes. */
937 if (target
== TGSI_TEXTURE_CUBE_ARRAY
||
938 target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
939 LLVMValueRef imm2
= LLVMConstInt(ctx
->i32
, 2, 0);
941 LLVMValueRef z
= LLVMBuildExtractElement(builder
, out
, imm2
, "");
942 z
= LLVMBuildSDiv(builder
, z
, LLVMConstInt(ctx
->i32
, 6, 0), "");
944 out
= LLVMBuildInsertElement(builder
, out
, z
, imm2
, "");
949 static void resq_emit(
950 const struct lp_build_tgsi_action
*action
,
951 struct lp_build_tgsi_context
*bld_base
,
952 struct lp_build_emit_data
*emit_data
)
954 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
955 LLVMBuilderRef builder
= ctx
->ac
.builder
;
956 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
957 const struct tgsi_full_src_register
*reg
=
958 &inst
->Src
[inst
->Instruction
.Opcode
== TGSI_OPCODE_TXQ
? 1 : 0];
960 if (reg
->Register
.File
== TGSI_FILE_BUFFER
) {
961 LLVMValueRef rsrc
= shader_buffer_fetch_rsrc(ctx
, reg
, false);
963 emit_data
->output
[emit_data
->chan
] =
964 LLVMBuildExtractElement(builder
, rsrc
,
965 LLVMConstInt(ctx
->i32
, 2, 0), "");
969 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXQ
&&
970 inst
->Texture
.Texture
== TGSI_TEXTURE_BUFFER
) {
973 tex_fetch_ptrs(bld_base
, emit_data
, &rsrc
, NULL
, NULL
);
974 /* Read the size from the buffer descriptor directly. */
975 emit_data
->output
[emit_data
->chan
] =
976 get_buffer_size(bld_base
, rsrc
);
980 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_RESQ
&&
981 inst
->Memory
.Texture
== TGSI_TEXTURE_BUFFER
) {
984 image_fetch_rsrc(bld_base
, reg
, false, inst
->Memory
.Texture
, &rsrc
);
985 emit_data
->output
[emit_data
->chan
] =
986 get_buffer_size(bld_base
, rsrc
);
992 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXQ
) {
993 target
= inst
->Texture
.Texture
;
995 if (inst
->Memory
.Texture
== TGSI_TEXTURE_3D
)
996 target
= TGSI_TEXTURE_2D_ARRAY
;
998 target
= inst
->Memory
.Texture
;
1001 struct ac_image_args args
= {};
1002 args
.opcode
= ac_image_get_resinfo
;
1003 args
.dim
= ac_texture_dim_from_tgsi_target(ctx
->screen
, target
);
1005 args
.attributes
= AC_FUNC_ATTR_READNONE
;
1007 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXQ
) {
1008 tex_fetch_ptrs(bld_base
, emit_data
, &args
.resource
, NULL
, NULL
);
1009 args
.lod
= lp_build_emit_fetch(bld_base
, inst
, 0, TGSI_CHAN_X
);
1011 image_fetch_rsrc(bld_base
, reg
, false, target
, &args
.resource
);
1012 args
.lod
= ctx
->i32_0
;
1015 emit_data
->output
[emit_data
->chan
] =
1016 fix_resinfo(ctx
, target
, ac_build_image_opcode(&ctx
->ac
, &args
));
1020 * Load an image view, fmask view. or sampler state descriptor.
1022 LLVMValueRef
si_load_sampler_desc(struct si_shader_context
*ctx
,
1023 LLVMValueRef list
, LLVMValueRef index
,
1024 enum ac_descriptor_type type
)
1026 LLVMBuilderRef builder
= ctx
->ac
.builder
;
1030 /* The image is at [0:7]. */
1031 index
= LLVMBuildMul(builder
, index
, LLVMConstInt(ctx
->i32
, 2, 0), "");
1033 case AC_DESC_BUFFER
:
1034 /* The buffer is in [4:7]. */
1035 index
= ac_build_imad(&ctx
->ac
, index
, LLVMConstInt(ctx
->i32
, 4, 0),
1037 list
= LLVMBuildPointerCast(builder
, list
,
1038 ac_array_in_const32_addr_space(ctx
->v4i32
), "");
1041 /* The FMASK is at [8:15]. */
1042 index
= ac_build_imad(&ctx
->ac
, index
, LLVMConstInt(ctx
->i32
, 2, 0),
1045 case AC_DESC_SAMPLER
:
1046 /* The sampler state is at [12:15]. */
1047 index
= ac_build_imad(&ctx
->ac
, index
, LLVMConstInt(ctx
->i32
, 4, 0),
1048 LLVMConstInt(ctx
->i32
, 3, 0));
1049 list
= LLVMBuildPointerCast(builder
, list
,
1050 ac_array_in_const32_addr_space(ctx
->v4i32
), "");
1052 case AC_DESC_PLANE_0
:
1053 case AC_DESC_PLANE_1
:
1054 case AC_DESC_PLANE_2
:
1055 /* Only used for the multiplane image support for Vulkan. Should
1056 * never be reached in radeonsi.
1058 unreachable("Plane descriptor requested in radeonsi.");
1061 return ac_build_load_to_sgpr(&ctx
->ac
, list
, index
);
1064 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
1067 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
1068 * filtering manually. The driver sets img7 to a mask clearing
1069 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
1070 * s_and_b32 samp0, samp0, img7
1073 * The ANISO_OVERRIDE sampler field enables this fix in TA.
1075 static LLVMValueRef
sici_fix_sampler_aniso(struct si_shader_context
*ctx
,
1076 LLVMValueRef res
, LLVMValueRef samp
)
1078 LLVMValueRef img7
, samp0
;
1080 if (ctx
->screen
->info
.chip_class
>= GFX8
)
1083 img7
= LLVMBuildExtractElement(ctx
->ac
.builder
, res
,
1084 LLVMConstInt(ctx
->i32
, 7, 0), "");
1085 samp0
= LLVMBuildExtractElement(ctx
->ac
.builder
, samp
,
1087 samp0
= LLVMBuildAnd(ctx
->ac
.builder
, samp0
, img7
, "");
1088 return LLVMBuildInsertElement(ctx
->ac
.builder
, samp
, samp0
,
1092 static void tex_fetch_ptrs(struct lp_build_tgsi_context
*bld_base
,
1093 struct lp_build_emit_data
*emit_data
,
1094 LLVMValueRef
*res_ptr
, LLVMValueRef
*samp_ptr
,
1095 LLVMValueRef
*fmask_ptr
)
1097 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1098 LLVMValueRef list
= LLVMGetParam(ctx
->main_fn
, ctx
->param_samplers_and_images
);
1099 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
1100 const struct tgsi_full_src_register
*reg
;
1101 unsigned target
= inst
->Texture
.Texture
;
1102 unsigned sampler_src
;
1105 sampler_src
= emit_data
->inst
->Instruction
.NumSrcRegs
- 1;
1106 reg
= &emit_data
->inst
->Src
[sampler_src
];
1108 if (reg
->Register
.Indirect
) {
1109 index
= si_get_bounded_indirect_index(ctx
,
1111 reg
->Register
.Index
,
1113 index
= LLVMBuildAdd(ctx
->ac
.builder
, index
,
1114 LLVMConstInt(ctx
->i32
, SI_NUM_IMAGES
/ 2, 0), "");
1116 index
= LLVMConstInt(ctx
->i32
,
1117 si_get_sampler_slot(reg
->Register
.Index
), 0);
1120 if (reg
->Register
.File
!= TGSI_FILE_SAMPLER
) {
1121 /* Bindless descriptors are accessible from a different pair of
1122 * user SGPR indices.
1124 list
= LLVMGetParam(ctx
->main_fn
,
1125 ctx
->param_bindless_samplers_and_images
);
1126 index
= lp_build_emit_fetch_src(bld_base
, reg
,
1127 TGSI_TYPE_UNSIGNED
, 0);
1129 /* Since bindless handle arithmetic can contain an unsigned integer
1130 * wraparound and si_load_sampler_desc assumes there isn't any,
1131 * use GEP without "inbounds" (inside ac_build_pointer_add)
1132 * to prevent incorrect code generation and hangs.
1134 index
= LLVMBuildMul(ctx
->ac
.builder
, index
, LLVMConstInt(ctx
->i32
, 2, 0), "");
1135 list
= ac_build_pointer_add(&ctx
->ac
, list
, index
);
1139 if (target
== TGSI_TEXTURE_BUFFER
)
1140 *res_ptr
= si_load_sampler_desc(ctx
, list
, index
, AC_DESC_BUFFER
);
1142 *res_ptr
= si_load_sampler_desc(ctx
, list
, index
, AC_DESC_IMAGE
);
1149 if (target
== TGSI_TEXTURE_2D_MSAA
||
1150 target
== TGSI_TEXTURE_2D_ARRAY_MSAA
) {
1152 *fmask_ptr
= si_load_sampler_desc(ctx
, list
, index
,
1154 } else if (target
!= TGSI_TEXTURE_BUFFER
) {
1156 *samp_ptr
= si_load_sampler_desc(ctx
, list
, index
,
1158 *samp_ptr
= sici_fix_sampler_aniso(ctx
, *res_ptr
, *samp_ptr
);
1163 /* Gather4 should follow the same rules as bilinear filtering, but the hardware
1164 * incorrectly forces nearest filtering if the texture format is integer.
1165 * The only effect it has on Gather4, which always returns 4 texels for
1166 * bilinear filtering, is that the final coordinates are off by 0.5 of
1169 * The workaround is to subtract 0.5 from the unnormalized coordinates,
1170 * or (0.5 / size) from the normalized coordinates.
1172 * However, cube textures with 8_8_8_8 data formats require a different
1173 * workaround of overriding the num format to USCALED/SSCALED. This would lose
1174 * precision in 32-bit data formats, so it needs to be applied dynamically at
1175 * runtime. In this case, return an i1 value that indicates whether the
1176 * descriptor was overridden (and hence a fixup of the sampler result is needed).
1179 si_lower_gather4_integer(struct si_shader_context
*ctx
,
1180 struct ac_image_args
*args
,
1182 enum tgsi_return_type return_type
)
1184 LLVMBuilderRef builder
= ctx
->ac
.builder
;
1185 LLVMValueRef wa_8888
= NULL
;
1186 LLVMValueRef half_texel
[2];
1188 assert(return_type
== TGSI_RETURN_TYPE_SINT
||
1189 return_type
== TGSI_RETURN_TYPE_UINT
);
1191 if (target
== TGSI_TEXTURE_CUBE
||
1192 target
== TGSI_TEXTURE_CUBE_ARRAY
) {
1193 LLVMValueRef formats
;
1194 LLVMValueRef data_format
;
1195 LLVMValueRef wa_formats
;
1197 formats
= LLVMBuildExtractElement(builder
, args
->resource
, ctx
->i32_1
, "");
1199 data_format
= LLVMBuildLShr(builder
, formats
,
1200 LLVMConstInt(ctx
->i32
, 20, false), "");
1201 data_format
= LLVMBuildAnd(builder
, data_format
,
1202 LLVMConstInt(ctx
->i32
, (1u << 6) - 1, false), "");
1203 wa_8888
= LLVMBuildICmp(
1204 builder
, LLVMIntEQ
, data_format
,
1205 LLVMConstInt(ctx
->i32
, V_008F14_IMG_DATA_FORMAT_8_8_8_8
, false),
1208 uint32_t wa_num_format
=
1209 return_type
== TGSI_RETURN_TYPE_UINT
?
1210 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_USCALED
) :
1211 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_SSCALED
);
1212 wa_formats
= LLVMBuildAnd(builder
, formats
,
1213 LLVMConstInt(ctx
->i32
, C_008F14_NUM_FORMAT
, false),
1215 wa_formats
= LLVMBuildOr(builder
, wa_formats
,
1216 LLVMConstInt(ctx
->i32
, wa_num_format
, false), "");
1218 formats
= LLVMBuildSelect(builder
, wa_8888
, wa_formats
, formats
, "");
1219 args
->resource
= LLVMBuildInsertElement(
1220 builder
, args
->resource
, formats
, ctx
->i32_1
, "");
1223 if (target
== TGSI_TEXTURE_RECT
||
1224 target
== TGSI_TEXTURE_SHADOWRECT
) {
1226 half_texel
[0] = half_texel
[1] = LLVMConstReal(ctx
->f32
, -0.5);
1228 struct ac_image_args resinfo
= {};
1229 struct lp_build_if_state if_ctx
;
1232 /* Skip the texture size query entirely if we don't need it. */
1233 lp_build_if(&if_ctx
, &ctx
->gallivm
, LLVMBuildNot(builder
, wa_8888
, ""));
1236 /* Query the texture size. */
1237 resinfo
.opcode
= ac_image_get_resinfo
;
1238 resinfo
.dim
= ac_texture_dim_from_tgsi_target(ctx
->screen
, target
);
1239 resinfo
.resource
= args
->resource
;
1240 resinfo
.sampler
= args
->sampler
;
1241 resinfo
.lod
= ctx
->ac
.i32_0
;
1242 resinfo
.dmask
= 0xf;
1243 resinfo
.attributes
= AC_FUNC_ATTR_READNONE
;
1245 LLVMValueRef texsize
=
1246 fix_resinfo(ctx
, target
,
1247 ac_build_image_opcode(&ctx
->ac
, &resinfo
));
1249 /* Compute -0.5 / size. */
1250 for (unsigned c
= 0; c
< 2; c
++) {
1252 LLVMBuildExtractElement(builder
, texsize
,
1253 LLVMConstInt(ctx
->i32
, c
, 0), "");
1254 half_texel
[c
] = LLVMBuildUIToFP(builder
, half_texel
[c
], ctx
->f32
, "");
1255 half_texel
[c
] = ac_build_fdiv(&ctx
->ac
, ctx
->ac
.f32_1
, half_texel
[c
]);
1256 half_texel
[c
] = LLVMBuildFMul(builder
, half_texel
[c
],
1257 LLVMConstReal(ctx
->f32
, -0.5), "");
1261 lp_build_endif(&if_ctx
);
1263 LLVMBasicBlockRef bb
[2] = { if_ctx
.true_block
, if_ctx
.entry_block
};
1265 for (unsigned c
= 0; c
< 2; c
++) {
1266 LLVMValueRef values
[2] = { half_texel
[c
], ctx
->ac
.f32_0
};
1267 half_texel
[c
] = ac_build_phi(&ctx
->ac
, ctx
->f32
, 2,
1273 for (unsigned c
= 0; c
< 2; c
++) {
1275 tmp
= ac_to_float(&ctx
->ac
, args
->coords
[c
]);
1276 tmp
= LLVMBuildFAdd(builder
, tmp
, half_texel
[c
], "");
1277 args
->coords
[c
] = ac_to_integer(&ctx
->ac
, tmp
);
1283 /* The second half of the cube texture 8_8_8_8 integer workaround: adjust the
1284 * result after the gather operation.
1287 si_fix_gather4_integer_result(struct si_shader_context
*ctx
,
1288 LLVMValueRef result
,
1289 enum tgsi_return_type return_type
,
1292 LLVMBuilderRef builder
= ctx
->ac
.builder
;
1294 assert(return_type
== TGSI_RETURN_TYPE_SINT
||
1295 return_type
== TGSI_RETURN_TYPE_UINT
);
1297 for (unsigned chan
= 0; chan
< 4; ++chan
) {
1298 LLVMValueRef chanv
= LLVMConstInt(ctx
->i32
, chan
, false);
1300 LLVMValueRef wa_value
;
1302 value
= LLVMBuildExtractElement(builder
, result
, chanv
, "");
1304 if (return_type
== TGSI_RETURN_TYPE_UINT
)
1305 wa_value
= LLVMBuildFPToUI(builder
, value
, ctx
->i32
, "");
1307 wa_value
= LLVMBuildFPToSI(builder
, value
, ctx
->i32
, "");
1308 wa_value
= ac_to_float(&ctx
->ac
, wa_value
);
1309 value
= LLVMBuildSelect(builder
, wa
, wa_value
, value
, "");
1311 result
= LLVMBuildInsertElement(builder
, result
, value
, chanv
, "");
1317 static void build_tex_intrinsic(const struct lp_build_tgsi_action
*action
,
1318 struct lp_build_tgsi_context
*bld_base
,
1319 struct lp_build_emit_data
*emit_data
)
1321 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1322 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
1323 unsigned opcode
= inst
->Instruction
.Opcode
;
1324 unsigned target
= inst
->Texture
.Texture
;
1325 struct ac_image_args args
= {};
1326 int ref_pos
= tgsi_util_get_shadow_ref_src_index(target
);
1328 bool has_offset
= inst
->Texture
.NumOffsets
> 0;
1329 LLVMValueRef fmask_ptr
= NULL
;
1331 tex_fetch_ptrs(bld_base
, emit_data
, &args
.resource
, &args
.sampler
, &fmask_ptr
);
1333 if (target
== TGSI_TEXTURE_BUFFER
) {
1334 LLVMValueRef vindex
= lp_build_emit_fetch(bld_base
, inst
, 0, TGSI_CHAN_X
);
1335 unsigned num_channels
=
1336 util_last_bit(inst
->Dst
[0].Register
.WriteMask
);
1337 LLVMValueRef result
=
1338 ac_build_buffer_load_format(&ctx
->ac
,
1342 num_channels
, false, true);
1343 emit_data
->output
[emit_data
->chan
] =
1344 ac_build_expand_to_vec4(&ctx
->ac
, result
, num_channels
);
1348 /* Fetch and project texture coordinates */
1349 args
.coords
[3] = lp_build_emit_fetch(bld_base
, inst
, 0, TGSI_CHAN_W
);
1350 for (chan
= 0; chan
< 3; chan
++) {
1351 args
.coords
[chan
] = lp_build_emit_fetch(bld_base
, inst
, 0, chan
);
1352 if (opcode
== TGSI_OPCODE_TXP
)
1353 args
.coords
[chan
] = ac_build_fdiv(&ctx
->ac
,
1354 args
.coords
[chan
], args
.coords
[3]);
1357 if (opcode
== TGSI_OPCODE_TXP
)
1358 args
.coords
[3] = ctx
->ac
.f32_1
;
1362 opcode
!= TGSI_OPCODE_TXF
&&
1363 opcode
!= TGSI_OPCODE_TXF_LZ
) {
1364 /* The offsets are six-bit signed integers packed like this:
1365 * X=[5:0], Y=[13:8], and Z=[21:16].
1367 LLVMValueRef offset
[3], pack
;
1369 assert(inst
->Texture
.NumOffsets
== 1);
1371 for (chan
= 0; chan
< 3; chan
++) {
1372 offset
[chan
] = lp_build_emit_fetch_texoffset(bld_base
, inst
, 0, chan
);
1373 offset
[chan
] = LLVMBuildAnd(ctx
->ac
.builder
, offset
[chan
],
1374 LLVMConstInt(ctx
->i32
, 0x3f, 0), "");
1376 offset
[chan
] = LLVMBuildShl(ctx
->ac
.builder
, offset
[chan
],
1377 LLVMConstInt(ctx
->i32
, chan
*8, 0), "");
1380 pack
= LLVMBuildOr(ctx
->ac
.builder
, offset
[0], offset
[1], "");
1381 pack
= LLVMBuildOr(ctx
->ac
.builder
, pack
, offset
[2], "");
1385 /* Pack LOD bias value */
1386 if (opcode
== TGSI_OPCODE_TXB
)
1387 args
.bias
= args
.coords
[3];
1388 if (opcode
== TGSI_OPCODE_TXB2
)
1389 args
.bias
= lp_build_emit_fetch(bld_base
, inst
, 1, TGSI_CHAN_X
);
1391 /* Pack depth comparison value */
1392 if (tgsi_is_shadow_target(target
) && opcode
!= TGSI_OPCODE_LODQ
) {
1395 if (target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
1396 z
= lp_build_emit_fetch(bld_base
, inst
, 1, TGSI_CHAN_X
);
1398 assert(ref_pos
>= 0);
1399 z
= args
.coords
[ref_pos
];
1402 /* Section 8.23.1 (Depth Texture Comparison Mode) of the
1403 * OpenGL 4.5 spec says:
1405 * "If the texture’s internal format indicates a fixed-point
1406 * depth texture, then D_t and D_ref are clamped to the
1407 * range [0, 1]; otherwise no clamping is performed."
1409 * TC-compatible HTILE promotes Z16 and Z24 to Z32_FLOAT,
1410 * so the depth comparison value isn't clamped for Z16 and
1411 * Z24 anymore. Do it manually here.
1413 if (ctx
->screen
->info
.chip_class
>= GFX8
) {
1414 LLVMValueRef upgraded
;
1415 LLVMValueRef clamped
;
1416 upgraded
= LLVMBuildExtractElement(ctx
->ac
.builder
, args
.sampler
,
1417 LLVMConstInt(ctx
->i32
, 3, false), "");
1418 upgraded
= LLVMBuildLShr(ctx
->ac
.builder
, upgraded
,
1419 LLVMConstInt(ctx
->i32
, 29, false), "");
1420 upgraded
= LLVMBuildTrunc(ctx
->ac
.builder
, upgraded
, ctx
->i1
, "");
1421 clamped
= ac_build_clamp(&ctx
->ac
, z
);
1422 z
= LLVMBuildSelect(ctx
->ac
.builder
, upgraded
, clamped
, z
, "");
1428 /* Pack user derivatives */
1429 if (opcode
== TGSI_OPCODE_TXD
) {
1430 int param
, num_src_deriv_channels
, num_dst_deriv_channels
;
1433 case TGSI_TEXTURE_3D
:
1434 num_src_deriv_channels
= 3;
1435 num_dst_deriv_channels
= 3;
1437 case TGSI_TEXTURE_2D
:
1438 case TGSI_TEXTURE_SHADOW2D
:
1439 case TGSI_TEXTURE_RECT
:
1440 case TGSI_TEXTURE_SHADOWRECT
:
1441 case TGSI_TEXTURE_2D_ARRAY
:
1442 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
1443 num_src_deriv_channels
= 2;
1444 num_dst_deriv_channels
= 2;
1446 case TGSI_TEXTURE_CUBE
:
1447 case TGSI_TEXTURE_SHADOWCUBE
:
1448 case TGSI_TEXTURE_CUBE_ARRAY
:
1449 case TGSI_TEXTURE_SHADOWCUBE_ARRAY
:
1450 /* Cube derivatives will be converted to 2D. */
1451 num_src_deriv_channels
= 3;
1452 num_dst_deriv_channels
= 3;
1454 case TGSI_TEXTURE_1D
:
1455 case TGSI_TEXTURE_SHADOW1D
:
1456 case TGSI_TEXTURE_1D_ARRAY
:
1457 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
1458 num_src_deriv_channels
= 1;
1460 /* 1D textures are allocated and used as 2D on GFX9. */
1461 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
1462 num_dst_deriv_channels
= 2;
1464 num_dst_deriv_channels
= 1;
1468 unreachable("invalid target");
1471 for (param
= 0; param
< 2; param
++) {
1472 for (chan
= 0; chan
< num_src_deriv_channels
; chan
++)
1473 args
.derivs
[param
* num_dst_deriv_channels
+ chan
] =
1474 lp_build_emit_fetch(bld_base
, inst
, param
+1, chan
);
1476 /* Fill in the rest with zeros. */
1477 for (chan
= num_src_deriv_channels
;
1478 chan
< num_dst_deriv_channels
; chan
++)
1479 args
.derivs
[param
* num_dst_deriv_channels
+ chan
] =
1484 if (target
== TGSI_TEXTURE_CUBE
||
1485 target
== TGSI_TEXTURE_CUBE_ARRAY
||
1486 target
== TGSI_TEXTURE_SHADOWCUBE
||
1487 target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
1488 ac_prepare_cube_coords(&ctx
->ac
,
1489 opcode
== TGSI_OPCODE_TXD
,
1490 target
== TGSI_TEXTURE_CUBE_ARRAY
||
1491 target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
,
1492 opcode
== TGSI_OPCODE_LODQ
,
1493 args
.coords
, args
.derivs
);
1494 } else if (tgsi_is_array_sampler(target
) &&
1495 opcode
!= TGSI_OPCODE_TXF
&&
1496 opcode
!= TGSI_OPCODE_TXF_LZ
&&
1497 ctx
->screen
->info
.chip_class
<= GFX8
) {
1498 unsigned array_coord
= target
== TGSI_TEXTURE_1D_ARRAY
? 1 : 2;
1499 args
.coords
[array_coord
] = ac_build_round(&ctx
->ac
, args
.coords
[array_coord
]);
1502 /* 1D textures are allocated and used as 2D on GFX9. */
1503 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
1504 LLVMValueRef filler
;
1506 /* Use 0.5, so that we don't sample the border color. */
1507 if (opcode
== TGSI_OPCODE_TXF
||
1508 opcode
== TGSI_OPCODE_TXF_LZ
)
1509 filler
= ctx
->i32_0
;
1511 filler
= LLVMConstReal(ctx
->f32
, 0.5);
1513 if (target
== TGSI_TEXTURE_1D
||
1514 target
== TGSI_TEXTURE_SHADOW1D
) {
1515 args
.coords
[1] = filler
;
1516 } else if (target
== TGSI_TEXTURE_1D_ARRAY
||
1517 target
== TGSI_TEXTURE_SHADOW1D_ARRAY
) {
1518 args
.coords
[2] = args
.coords
[1];
1519 args
.coords
[1] = filler
;
1523 /* Pack LOD or sample index */
1524 if (opcode
== TGSI_OPCODE_TXL
)
1525 args
.lod
= args
.coords
[3];
1526 else if (opcode
== TGSI_OPCODE_TXL2
)
1527 args
.lod
= lp_build_emit_fetch(bld_base
, inst
, 1, TGSI_CHAN_X
);
1528 else if (opcode
== TGSI_OPCODE_TXF
) {
1529 if (target
== TGSI_TEXTURE_2D_MSAA
) {
1530 /* No LOD, but move sample index into the right place. */
1531 args
.coords
[2] = args
.coords
[3];
1532 } else if (target
!= TGSI_TEXTURE_2D_ARRAY_MSAA
) {
1533 args
.lod
= args
.coords
[3];
1537 if (target
== TGSI_TEXTURE_2D_MSAA
||
1538 target
== TGSI_TEXTURE_2D_ARRAY_MSAA
) {
1539 ac_apply_fmask_to_sample(&ctx
->ac
, fmask_ptr
, args
.coords
,
1540 target
== TGSI_TEXTURE_2D_ARRAY_MSAA
);
1543 if (opcode
== TGSI_OPCODE_TXF
||
1544 opcode
== TGSI_OPCODE_TXF_LZ
) {
1545 /* add tex offsets */
1546 if (inst
->Texture
.NumOffsets
) {
1547 const struct tgsi_texture_offset
*off
= inst
->TexOffsets
;
1549 assert(inst
->Texture
.NumOffsets
== 1);
1552 case TGSI_TEXTURE_3D
:
1554 LLVMBuildAdd(ctx
->ac
.builder
, args
.coords
[2],
1555 ctx
->imms
[off
->Index
* TGSI_NUM_CHANNELS
+ off
->SwizzleZ
], "");
1557 case TGSI_TEXTURE_2D
:
1558 case TGSI_TEXTURE_SHADOW2D
:
1559 case TGSI_TEXTURE_RECT
:
1560 case TGSI_TEXTURE_SHADOWRECT
:
1561 case TGSI_TEXTURE_2D_ARRAY
:
1562 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
1564 LLVMBuildAdd(ctx
->ac
.builder
, args
.coords
[1],
1565 ctx
->imms
[off
->Index
* TGSI_NUM_CHANNELS
+ off
->SwizzleY
], "");
1567 case TGSI_TEXTURE_1D
:
1568 case TGSI_TEXTURE_SHADOW1D
:
1569 case TGSI_TEXTURE_1D_ARRAY
:
1570 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
1572 LLVMBuildAdd(ctx
->ac
.builder
, args
.coords
[0],
1573 ctx
->imms
[off
->Index
* TGSI_NUM_CHANNELS
+ off
->SwizzleX
], "");
1575 /* texture offsets do not apply to other texture targets */
1580 if (opcode
== TGSI_OPCODE_TG4
) {
1581 unsigned gather_comp
= 0;
1583 /* DMASK was repurposed for GATHER4. 4 components are always
1584 * returned and DMASK works like a swizzle - it selects
1585 * the component to fetch. The only valid DMASK values are
1586 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
1587 * (red,red,red,red) etc.) The ISA document doesn't mention
1591 /* Get the component index from src1.x for Gather4. */
1592 if (!tgsi_is_shadow_target(target
)) {
1593 LLVMValueRef comp_imm
;
1594 struct tgsi_src_register src1
= inst
->Src
[1].Register
;
1596 assert(src1
.File
== TGSI_FILE_IMMEDIATE
);
1598 comp_imm
= ctx
->imms
[src1
.Index
* TGSI_NUM_CHANNELS
+ src1
.SwizzleX
];
1599 gather_comp
= LLVMConstIntGetZExtValue(comp_imm
);
1600 gather_comp
= CLAMP(gather_comp
, 0, 3);
1603 args
.dmask
= 1 << gather_comp
;
1608 args
.dim
= ac_texture_dim_from_tgsi_target(ctx
->screen
, target
);
1609 args
.unorm
= target
== TGSI_TEXTURE_RECT
||
1610 target
== TGSI_TEXTURE_SHADOWRECT
;
1611 args
.opcode
= ac_image_sample
;
1614 case TGSI_OPCODE_TXF
:
1615 case TGSI_OPCODE_TXF_LZ
:
1616 args
.opcode
= opcode
== TGSI_OPCODE_TXF_LZ
||
1617 target
== TGSI_TEXTURE_2D_MSAA
||
1618 target
== TGSI_TEXTURE_2D_ARRAY_MSAA
?
1619 ac_image_load
: ac_image_load_mip
;
1621 case TGSI_OPCODE_LODQ
:
1622 args
.opcode
= ac_image_get_lod
;
1624 case TGSI_OPCODE_TEX
:
1625 case TGSI_OPCODE_TEX2
:
1626 case TGSI_OPCODE_TXP
:
1627 if (ctx
->type
!= PIPE_SHADER_FRAGMENT
)
1628 args
.level_zero
= true;
1630 case TGSI_OPCODE_TEX_LZ
:
1631 args
.level_zero
= true;
1633 case TGSI_OPCODE_TXB
:
1634 case TGSI_OPCODE_TXB2
:
1635 assert(ctx
->type
== PIPE_SHADER_FRAGMENT
);
1637 case TGSI_OPCODE_TXL
:
1638 case TGSI_OPCODE_TXL2
:
1640 case TGSI_OPCODE_TXD
:
1642 case TGSI_OPCODE_TG4
:
1643 args
.opcode
= ac_image_gather4
;
1644 args
.level_zero
= true;
1651 /* The hardware needs special lowering for Gather4 with integer formats. */
1652 LLVMValueRef gather4_int_result_workaround
= NULL
;
1654 if (ctx
->screen
->info
.chip_class
<= GFX8
&&
1655 opcode
== TGSI_OPCODE_TG4
) {
1656 assert(inst
->Texture
.ReturnType
!= TGSI_RETURN_TYPE_UNKNOWN
);
1658 if (inst
->Texture
.ReturnType
== TGSI_RETURN_TYPE_SINT
||
1659 inst
->Texture
.ReturnType
== TGSI_RETURN_TYPE_UINT
) {
1660 gather4_int_result_workaround
=
1661 si_lower_gather4_integer(ctx
, &args
, target
,
1662 inst
->Texture
.ReturnType
);
1666 args
.attributes
= AC_FUNC_ATTR_READNONE
;
1667 LLVMValueRef result
= ac_build_image_opcode(&ctx
->ac
, &args
);
1669 if (gather4_int_result_workaround
) {
1670 result
= si_fix_gather4_integer_result(ctx
, result
,
1671 inst
->Texture
.ReturnType
,
1672 gather4_int_result_workaround
);
1675 emit_data
->output
[emit_data
->chan
] = result
;
1678 static void si_llvm_emit_txqs(
1679 const struct lp_build_tgsi_action
*action
,
1680 struct lp_build_tgsi_context
*bld_base
,
1681 struct lp_build_emit_data
*emit_data
)
1683 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1684 LLVMValueRef res
, samples
;
1685 LLVMValueRef res_ptr
, samp_ptr
, fmask_ptr
= NULL
;
1687 tex_fetch_ptrs(bld_base
, emit_data
, &res_ptr
, &samp_ptr
, &fmask_ptr
);
1689 /* Read the samples from the descriptor directly. */
1690 res
= LLVMBuildBitCast(ctx
->ac
.builder
, res_ptr
, ctx
->v8i32
, "");
1691 samples
= LLVMBuildExtractElement(ctx
->ac
.builder
, res
,
1692 LLVMConstInt(ctx
->i32
, 3, 0), "");
1693 samples
= LLVMBuildLShr(ctx
->ac
.builder
, samples
,
1694 LLVMConstInt(ctx
->i32
, 16, 0), "");
1695 samples
= LLVMBuildAnd(ctx
->ac
.builder
, samples
,
1696 LLVMConstInt(ctx
->i32
, 0xf, 0), "");
1697 samples
= LLVMBuildShl(ctx
->ac
.builder
, ctx
->i32_1
,
1700 emit_data
->output
[emit_data
->chan
] = samples
;
1703 static void si_llvm_emit_fbfetch(const struct lp_build_tgsi_action
*action
,
1704 struct lp_build_tgsi_context
*bld_base
,
1705 struct lp_build_emit_data
*emit_data
)
1707 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1708 struct ac_image_args args
= {};
1709 LLVMValueRef ptr
, image
, fmask
;
1711 /* Ignore src0, because KHR_blend_func_extended disallows multiple render
1715 /* Load the image descriptor. */
1716 STATIC_ASSERT(SI_PS_IMAGE_COLORBUF0
% 2 == 0);
1717 ptr
= LLVMGetParam(ctx
->main_fn
, ctx
->param_rw_buffers
);
1718 ptr
= LLVMBuildPointerCast(ctx
->ac
.builder
, ptr
,
1719 ac_array_in_const32_addr_space(ctx
->v8i32
), "");
1720 image
= ac_build_load_to_sgpr(&ctx
->ac
, ptr
,
1721 LLVMConstInt(ctx
->i32
, SI_PS_IMAGE_COLORBUF0
/ 2, 0));
1725 args
.coords
[chan
++] = si_unpack_param(ctx
, SI_PARAM_POS_FIXED_PT
, 0, 16);
1727 if (!ctx
->shader
->key
.mono
.u
.ps
.fbfetch_is_1D
)
1728 args
.coords
[chan
++] = si_unpack_param(ctx
, SI_PARAM_POS_FIXED_PT
, 16, 16);
1730 /* Get the current render target layer index. */
1731 if (ctx
->shader
->key
.mono
.u
.ps
.fbfetch_layered
)
1732 args
.coords
[chan
++] = si_unpack_param(ctx
, SI_PARAM_ANCILLARY
, 16, 11);
1734 if (ctx
->shader
->key
.mono
.u
.ps
.fbfetch_msaa
)
1735 args
.coords
[chan
++] = si_get_sample_id(ctx
);
1737 if (ctx
->shader
->key
.mono
.u
.ps
.fbfetch_msaa
) {
1738 fmask
= ac_build_load_to_sgpr(&ctx
->ac
, ptr
,
1739 LLVMConstInt(ctx
->i32
, SI_PS_IMAGE_COLORBUF0_FMASK
/ 2, 0));
1741 ac_apply_fmask_to_sample(&ctx
->ac
, fmask
, args
.coords
,
1742 ctx
->shader
->key
.mono
.u
.ps
.fbfetch_layered
);
1745 args
.opcode
= ac_image_load
;
1746 args
.resource
= image
;
1748 args
.attributes
= AC_FUNC_ATTR_READNONE
;
1750 if (ctx
->shader
->key
.mono
.u
.ps
.fbfetch_msaa
)
1751 args
.dim
= ctx
->shader
->key
.mono
.u
.ps
.fbfetch_layered
?
1752 ac_image_2darraymsaa
: ac_image_2dmsaa
;
1753 else if (ctx
->shader
->key
.mono
.u
.ps
.fbfetch_is_1D
)
1754 args
.dim
= ctx
->shader
->key
.mono
.u
.ps
.fbfetch_layered
?
1755 ac_image_1darray
: ac_image_1d
;
1757 args
.dim
= ctx
->shader
->key
.mono
.u
.ps
.fbfetch_layered
?
1758 ac_image_2darray
: ac_image_2d
;
1760 emit_data
->output
[emit_data
->chan
] =
1761 ac_build_image_opcode(&ctx
->ac
, &args
);
1765 * Setup actions for TGSI memory opcode, including texture opcodes.
1767 void si_shader_context_init_mem(struct si_shader_context
*ctx
)
1769 struct lp_build_tgsi_context
*bld_base
= &ctx
->bld_base
;
1771 bld_base
->op_actions
[TGSI_OPCODE_TEX
].emit
= build_tex_intrinsic
;
1772 bld_base
->op_actions
[TGSI_OPCODE_TEX_LZ
].emit
= build_tex_intrinsic
;
1773 bld_base
->op_actions
[TGSI_OPCODE_TEX2
].emit
= build_tex_intrinsic
;
1774 bld_base
->op_actions
[TGSI_OPCODE_TXB
].emit
= build_tex_intrinsic
;
1775 bld_base
->op_actions
[TGSI_OPCODE_TXB2
].emit
= build_tex_intrinsic
;
1776 bld_base
->op_actions
[TGSI_OPCODE_TXD
].emit
= build_tex_intrinsic
;
1777 bld_base
->op_actions
[TGSI_OPCODE_TXF
].emit
= build_tex_intrinsic
;
1778 bld_base
->op_actions
[TGSI_OPCODE_TXF_LZ
].emit
= build_tex_intrinsic
;
1779 bld_base
->op_actions
[TGSI_OPCODE_TXL
].emit
= build_tex_intrinsic
;
1780 bld_base
->op_actions
[TGSI_OPCODE_TXL2
].emit
= build_tex_intrinsic
;
1781 bld_base
->op_actions
[TGSI_OPCODE_TXP
].emit
= build_tex_intrinsic
;
1782 bld_base
->op_actions
[TGSI_OPCODE_TXQ
].emit
= resq_emit
;
1783 bld_base
->op_actions
[TGSI_OPCODE_TG4
].emit
= build_tex_intrinsic
;
1784 bld_base
->op_actions
[TGSI_OPCODE_LODQ
].emit
= build_tex_intrinsic
;
1785 bld_base
->op_actions
[TGSI_OPCODE_TXQS
].emit
= si_llvm_emit_txqs
;
1787 bld_base
->op_actions
[TGSI_OPCODE_FBFETCH
].emit
= si_llvm_emit_fbfetch
;
1789 bld_base
->op_actions
[TGSI_OPCODE_LOAD
].emit
= load_emit
;
1790 bld_base
->op_actions
[TGSI_OPCODE_STORE
].emit
= store_emit
;
1791 bld_base
->op_actions
[TGSI_OPCODE_RESQ
].emit
= resq_emit
;
1793 bld_base
->op_actions
[TGSI_OPCODE_ATOMUADD
].emit
= atomic_emit
;
1794 bld_base
->op_actions
[TGSI_OPCODE_ATOMUADD
].intr_name
= "add";
1795 bld_base
->op_actions
[TGSI_OPCODE_ATOMXCHG
].emit
= atomic_emit
;
1796 bld_base
->op_actions
[TGSI_OPCODE_ATOMXCHG
].intr_name
= "swap";
1797 bld_base
->op_actions
[TGSI_OPCODE_ATOMCAS
].emit
= atomic_emit
;
1798 bld_base
->op_actions
[TGSI_OPCODE_ATOMCAS
].intr_name
= "cmpswap";
1799 bld_base
->op_actions
[TGSI_OPCODE_ATOMAND
].emit
= atomic_emit
;
1800 bld_base
->op_actions
[TGSI_OPCODE_ATOMAND
].intr_name
= "and";
1801 bld_base
->op_actions
[TGSI_OPCODE_ATOMOR
].emit
= atomic_emit
;
1802 bld_base
->op_actions
[TGSI_OPCODE_ATOMOR
].intr_name
= "or";
1803 bld_base
->op_actions
[TGSI_OPCODE_ATOMXOR
].emit
= atomic_emit
;
1804 bld_base
->op_actions
[TGSI_OPCODE_ATOMXOR
].intr_name
= "xor";
1805 bld_base
->op_actions
[TGSI_OPCODE_ATOMUMIN
].emit
= atomic_emit
;
1806 bld_base
->op_actions
[TGSI_OPCODE_ATOMUMIN
].intr_name
= "umin";
1807 bld_base
->op_actions
[TGSI_OPCODE_ATOMUMAX
].emit
= atomic_emit
;
1808 bld_base
->op_actions
[TGSI_OPCODE_ATOMUMAX
].intr_name
= "umax";
1809 bld_base
->op_actions
[TGSI_OPCODE_ATOMIMIN
].emit
= atomic_emit
;
1810 bld_base
->op_actions
[TGSI_OPCODE_ATOMIMIN
].intr_name
= "smin";
1811 bld_base
->op_actions
[TGSI_OPCODE_ATOMIMAX
].emit
= atomic_emit
;
1812 bld_base
->op_actions
[TGSI_OPCODE_ATOMIMAX
].intr_name
= "smax";