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ac: replace glc,slc with cache_policy for stores
[mesa.git] / src / gallium / drivers / radeonsi / si_shader_tgsi_mem.c
1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_shader_internal.h"
26 #include "si_pipe.h"
27 #include "sid.h"
28 #include "tgsi/tgsi_build.h"
29 #include "tgsi/tgsi_util.h"
30 #include "ac_llvm_util.h"
31
32 static void tex_fetch_ptrs(struct lp_build_tgsi_context *bld_base,
33 struct lp_build_emit_data *emit_data,
34 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
35 LLVMValueRef *fmask_ptr);
36
37 /**
38 * Given a v8i32 resource descriptor for a buffer, extract the size of the
39 * buffer in number of elements and return it as an i32.
40 */
41 static LLVMValueRef get_buffer_size(
42 struct lp_build_tgsi_context *bld_base,
43 LLVMValueRef descriptor)
44 {
45 struct si_shader_context *ctx = si_shader_context(bld_base);
46 LLVMBuilderRef builder = ctx->ac.builder;
47 LLVMValueRef size =
48 LLVMBuildExtractElement(builder, descriptor,
49 LLVMConstInt(ctx->i32, 2, 0), "");
50
51 if (ctx->screen->info.chip_class == GFX8) {
52 /* On GFX8, the descriptor contains the size in bytes,
53 * but TXQ must return the size in elements.
54 * The stride is always non-zero for resources using TXQ.
55 */
56 LLVMValueRef stride =
57 LLVMBuildExtractElement(builder, descriptor,
58 ctx->i32_1, "");
59 stride = LLVMBuildLShr(builder, stride,
60 LLVMConstInt(ctx->i32, 16, 0), "");
61 stride = LLVMBuildAnd(builder, stride,
62 LLVMConstInt(ctx->i32, 0x3FFF, 0), "");
63
64 size = LLVMBuildUDiv(builder, size, stride, "");
65 }
66
67 return size;
68 }
69
70 static LLVMValueRef
71 shader_buffer_fetch_rsrc(struct si_shader_context *ctx,
72 const struct tgsi_full_src_register *reg,
73 bool ubo)
74 {
75 LLVMValueRef index;
76
77 if (!reg->Register.Indirect) {
78 index = LLVMConstInt(ctx->i32, reg->Register.Index, false);
79 } else {
80 index = si_get_indirect_index(ctx, &reg->Indirect,
81 1, reg->Register.Index);
82 }
83
84 if (ubo)
85 return ctx->abi.load_ubo(&ctx->abi, index);
86 else
87 return ctx->abi.load_ssbo(&ctx->abi, index, false);
88 }
89
90 static enum ac_image_dim
91 ac_texture_dim_from_tgsi_target(struct si_screen *screen, enum tgsi_texture_type target)
92 {
93 switch (target) {
94 case TGSI_TEXTURE_1D:
95 case TGSI_TEXTURE_SHADOW1D:
96 if (screen->info.chip_class >= GFX9)
97 return ac_image_2d;
98 return ac_image_1d;
99 case TGSI_TEXTURE_2D:
100 case TGSI_TEXTURE_SHADOW2D:
101 case TGSI_TEXTURE_RECT:
102 case TGSI_TEXTURE_SHADOWRECT:
103 return ac_image_2d;
104 case TGSI_TEXTURE_3D:
105 return ac_image_3d;
106 case TGSI_TEXTURE_CUBE:
107 case TGSI_TEXTURE_SHADOWCUBE:
108 case TGSI_TEXTURE_CUBE_ARRAY:
109 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
110 return ac_image_cube;
111 case TGSI_TEXTURE_1D_ARRAY:
112 case TGSI_TEXTURE_SHADOW1D_ARRAY:
113 if (screen->info.chip_class >= GFX9)
114 return ac_image_2darray;
115 return ac_image_1darray;
116 case TGSI_TEXTURE_2D_ARRAY:
117 case TGSI_TEXTURE_SHADOW2D_ARRAY:
118 return ac_image_2darray;
119 case TGSI_TEXTURE_2D_MSAA:
120 return ac_image_2dmsaa;
121 case TGSI_TEXTURE_2D_ARRAY_MSAA:
122 return ac_image_2darraymsaa;
123 default:
124 unreachable("unhandled texture type");
125 }
126 }
127
128 static enum ac_image_dim
129 ac_image_dim_from_tgsi_target(struct si_screen *screen, enum tgsi_texture_type target)
130 {
131 enum ac_image_dim dim = ac_texture_dim_from_tgsi_target(screen, target);
132
133 /* Match the resource type set in the descriptor. */
134 if (dim == ac_image_cube ||
135 (screen->info.chip_class <= GFX8 && dim == ac_image_3d))
136 dim = ac_image_2darray;
137 else if (target == TGSI_TEXTURE_2D && screen->info.chip_class == GFX9) {
138 /* When a single layer of a 3D texture is bound, the shader
139 * will refer to a 2D target, but the descriptor has a 3D type.
140 * Since the HW ignores BASE_ARRAY in this case, we need to
141 * send 3 coordinates. This doesn't hurt when the underlying
142 * texture is non-3D.
143 */
144 dim = ac_image_3d;
145 }
146
147 return dim;
148 }
149
150 /**
151 * Given a 256-bit resource descriptor, force the DCC enable bit to off.
152 *
153 * At least on Tonga, executing image stores on images with DCC enabled and
154 * non-trivial can eventually lead to lockups. This can occur when an
155 * application binds an image as read-only but then uses a shader that writes
156 * to it. The OpenGL spec allows almost arbitrarily bad behavior (including
157 * program termination) in this case, but it doesn't cost much to be a bit
158 * nicer: disabling DCC in the shader still leads to undefined results but
159 * avoids the lockup.
160 */
161 static LLVMValueRef force_dcc_off(struct si_shader_context *ctx,
162 LLVMValueRef rsrc)
163 {
164 if (ctx->screen->info.chip_class <= GFX7) {
165 return rsrc;
166 } else {
167 LLVMValueRef i32_6 = LLVMConstInt(ctx->i32, 6, 0);
168 LLVMValueRef i32_C = LLVMConstInt(ctx->i32, C_008F28_COMPRESSION_EN, 0);
169 LLVMValueRef tmp;
170
171 tmp = LLVMBuildExtractElement(ctx->ac.builder, rsrc, i32_6, "");
172 tmp = LLVMBuildAnd(ctx->ac.builder, tmp, i32_C, "");
173 return LLVMBuildInsertElement(ctx->ac.builder, rsrc, tmp, i32_6, "");
174 }
175 }
176
177 LLVMValueRef si_load_image_desc(struct si_shader_context *ctx,
178 LLVMValueRef list, LLVMValueRef index,
179 enum ac_descriptor_type desc_type, bool dcc_off,
180 bool bindless)
181 {
182 LLVMBuilderRef builder = ctx->ac.builder;
183 LLVMValueRef rsrc;
184
185 if (desc_type == AC_DESC_BUFFER) {
186 index = ac_build_imad(&ctx->ac, index, LLVMConstInt(ctx->i32, 2, 0),
187 ctx->i32_1);
188 list = LLVMBuildPointerCast(builder, list,
189 ac_array_in_const32_addr_space(ctx->v4i32), "");
190 } else {
191 assert(desc_type == AC_DESC_IMAGE);
192 }
193
194 if (bindless)
195 rsrc = ac_build_load_to_sgpr_uint_wraparound(&ctx->ac, list, index);
196 else
197 rsrc = ac_build_load_to_sgpr(&ctx->ac, list, index);
198
199 if (desc_type == AC_DESC_IMAGE && dcc_off)
200 rsrc = force_dcc_off(ctx, rsrc);
201 return rsrc;
202 }
203
204 /**
205 * Load the resource descriptor for \p image.
206 */
207 static void
208 image_fetch_rsrc(
209 struct lp_build_tgsi_context *bld_base,
210 const struct tgsi_full_src_register *image,
211 bool is_store, unsigned target,
212 LLVMValueRef *rsrc)
213 {
214 struct si_shader_context *ctx = si_shader_context(bld_base);
215 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
216 ctx->param_samplers_and_images);
217 LLVMValueRef index;
218 bool dcc_off = is_store;
219
220 if (!image->Register.Indirect) {
221 index = LLVMConstInt(ctx->i32,
222 si_get_image_slot(image->Register.Index), 0);
223 } else {
224 /* From the GL_ARB_shader_image_load_store extension spec:
225 *
226 * If a shader performs an image load, store, or atomic
227 * operation using an image variable declared as an array,
228 * and if the index used to select an individual element is
229 * negative or greater than or equal to the size of the
230 * array, the results of the operation are undefined but may
231 * not lead to termination.
232 */
233 index = si_get_bounded_indirect_index(ctx, &image->Indirect,
234 image->Register.Index,
235 ctx->num_images);
236 index = LLVMBuildSub(ctx->ac.builder,
237 LLVMConstInt(ctx->i32, SI_NUM_IMAGES - 1, 0),
238 index, "");
239 }
240
241 bool bindless = false;
242
243 if (image->Register.File != TGSI_FILE_IMAGE) {
244 /* Bindless descriptors are accessible from a different pair of
245 * user SGPR indices.
246 */
247 rsrc_ptr = LLVMGetParam(ctx->main_fn,
248 ctx->param_bindless_samplers_and_images);
249 index = lp_build_emit_fetch_src(bld_base, image,
250 TGSI_TYPE_UNSIGNED, 0);
251
252 /* For simplicity, bindless image descriptors use fixed
253 * 16-dword slots for now.
254 */
255 index = LLVMBuildMul(ctx->ac.builder, index,
256 LLVMConstInt(ctx->i32, 2, 0), "");
257 bindless = true;
258 }
259
260 *rsrc = si_load_image_desc(ctx, rsrc_ptr, index,
261 target == TGSI_TEXTURE_BUFFER ? AC_DESC_BUFFER : AC_DESC_IMAGE,
262 dcc_off, bindless);
263 }
264
265 static void image_fetch_coords(
266 struct lp_build_tgsi_context *bld_base,
267 const struct tgsi_full_instruction *inst,
268 unsigned src, LLVMValueRef desc,
269 LLVMValueRef *coords)
270 {
271 struct si_shader_context *ctx = si_shader_context(bld_base);
272 LLVMBuilderRef builder = ctx->ac.builder;
273 unsigned target = inst->Memory.Texture;
274 unsigned num_coords = tgsi_util_get_texture_coord_dim(target);
275 LLVMValueRef tmp;
276 int chan;
277
278 if (target == TGSI_TEXTURE_2D_MSAA ||
279 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
280 /* Need the sample index as well. */
281 num_coords++;
282 }
283
284 for (chan = 0; chan < num_coords; ++chan) {
285 tmp = lp_build_emit_fetch(bld_base, inst, src, chan);
286 tmp = ac_to_integer(&ctx->ac, tmp);
287 coords[chan] = tmp;
288 }
289
290 if (ctx->screen->info.chip_class >= GFX9) {
291 /* 1D textures are allocated and used as 2D on GFX9. */
292 if (target == TGSI_TEXTURE_1D) {
293 coords[1] = ctx->i32_0;
294 } else if (target == TGSI_TEXTURE_1D_ARRAY) {
295 coords[2] = coords[1];
296 coords[1] = ctx->i32_0;
297 } else if (ctx->screen->info.chip_class == GFX9 &&
298 target == TGSI_TEXTURE_2D) {
299 /* The hw can't bind a slice of a 3D image as a 2D
300 * image, because it ignores BASE_ARRAY if the target
301 * is 3D. The workaround is to read BASE_ARRAY and set
302 * it as the 3rd address operand for all 2D images.
303 */
304 LLVMValueRef first_layer, const5, mask;
305
306 const5 = LLVMConstInt(ctx->i32, 5, 0);
307 mask = LLVMConstInt(ctx->i32, S_008F24_BASE_ARRAY(~0), 0);
308 first_layer = LLVMBuildExtractElement(builder, desc, const5, "");
309 first_layer = LLVMBuildAnd(builder, first_layer, mask, "");
310
311 coords[2] = first_layer;
312 }
313 }
314 }
315
316 static unsigned get_cache_policy(struct si_shader_context *ctx,
317 const struct tgsi_full_instruction *inst,
318 bool load, bool atomic, bool may_store_unaligned,
319 bool writeonly_memory)
320 {
321 unsigned cache_policy = 0;
322
323 if (!atomic &&
324 /* GFX6 has a TC L1 bug causing corruption of 8bit/16bit stores.
325 * All store opcodes not aligned to a dword are affected.
326 * The only way to get unaligned stores in radeonsi is through
327 * shader images. */
328 ((may_store_unaligned && ctx->screen->info.chip_class == GFX6) ||
329 /* If this is write-only, don't keep data in L1 to prevent
330 * evicting L1 cache lines that may be needed by other
331 * instructions. */
332 writeonly_memory ||
333 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE))) {
334 cache_policy |= ac_glc |
335 (ctx->screen->info.chip_class >= GFX10 && load ? ac_dlc : 0);
336 }
337
338 if (inst->Memory.Qualifier & TGSI_MEMORY_STREAM_CACHE_POLICY)
339 cache_policy |= ac_slc;
340
341 return cache_policy;
342 }
343
344 static LLVMValueRef get_memory_ptr(struct si_shader_context *ctx,
345 const struct tgsi_full_instruction *inst,
346 LLVMTypeRef type, int arg)
347 {
348 LLVMBuilderRef builder = ctx->ac.builder;
349 LLVMValueRef offset, ptr;
350 int addr_space;
351
352 offset = lp_build_emit_fetch(&ctx->bld_base, inst, arg, 0);
353 offset = ac_to_integer(&ctx->ac, offset);
354
355 ptr = ctx->ac.lds;
356 ptr = LLVMBuildGEP(builder, ptr, &offset, 1, "");
357 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
358 ptr = LLVMBuildBitCast(builder, ptr, LLVMPointerType(type, addr_space), "");
359
360 return ptr;
361 }
362
363 static void load_emit_memory(
364 struct si_shader_context *ctx,
365 struct lp_build_emit_data *emit_data)
366 {
367 const struct tgsi_full_instruction *inst = emit_data->inst;
368 unsigned writemask = inst->Dst[0].Register.WriteMask;
369 LLVMValueRef channels[4], ptr, derived_ptr, index;
370 int chan;
371
372 ptr = get_memory_ptr(ctx, inst, ctx->f32, 1);
373
374 for (chan = 0; chan < 4; ++chan) {
375 if (!(writemask & (1 << chan))) {
376 channels[chan] = LLVMGetUndef(ctx->f32);
377 continue;
378 }
379
380 index = LLVMConstInt(ctx->i32, chan, 0);
381 derived_ptr = LLVMBuildGEP(ctx->ac.builder, ptr, &index, 1, "");
382 channels[chan] = LLVMBuildLoad(ctx->ac.builder, derived_ptr, "");
383 }
384 emit_data->output[emit_data->chan] = ac_build_gather_values(&ctx->ac, channels, 4);
385 }
386
387 /**
388 * Return true if the memory accessed by a LOAD or STORE instruction is
389 * read-only or write-only, respectively.
390 *
391 * \param shader_buffers_reverse_access_mask
392 * For LOAD, set this to (store | atomic) slot usage in the shader.
393 * For STORE, set this to (load | atomic) slot usage in the shader.
394 * \param images_reverse_access_mask Same as above, but for images.
395 * \param bindless_buffer_reverse_access_mask Same as above, but for bindless image buffers.
396 * \param bindless_image_reverse_access_mask Same as above, but for bindless images.
397 */
398 static bool is_oneway_access_only(const struct tgsi_full_instruction *inst,
399 const struct tgsi_shader_info *info,
400 unsigned shader_buffers_reverse_access_mask,
401 unsigned images_reverse_access_mask,
402 bool bindless_buffer_reverse_access_mask,
403 bool bindless_image_reverse_access_mask)
404 {
405 enum tgsi_file_type resource_file;
406 unsigned resource_index;
407 bool resource_indirect;
408
409 if (inst->Instruction.Opcode == TGSI_OPCODE_STORE) {
410 resource_file = inst->Dst[0].Register.File;
411 resource_index = inst->Dst[0].Register.Index;
412 resource_indirect = inst->Dst[0].Register.Indirect;
413 } else {
414 resource_file = inst->Src[0].Register.File;
415 resource_index = inst->Src[0].Register.Index;
416 resource_indirect = inst->Src[0].Register.Indirect;
417 }
418
419 assert(resource_file == TGSI_FILE_BUFFER ||
420 resource_file == TGSI_FILE_IMAGE ||
421 /* bindless image */
422 resource_file == TGSI_FILE_INPUT ||
423 resource_file == TGSI_FILE_OUTPUT ||
424 resource_file == TGSI_FILE_CONSTANT ||
425 resource_file == TGSI_FILE_TEMPORARY ||
426 resource_file == TGSI_FILE_IMMEDIATE);
427
428 assert(resource_file != TGSI_FILE_BUFFER ||
429 inst->Memory.Texture == TGSI_TEXTURE_BUFFER);
430
431 bool bindless = resource_file != TGSI_FILE_BUFFER &&
432 resource_file != TGSI_FILE_IMAGE;
433
434 /* RESTRICT means NOALIAS.
435 * If there are no writes, we can assume the accessed memory is read-only.
436 * If there are no reads, we can assume the accessed memory is write-only.
437 */
438 if (inst->Memory.Qualifier & TGSI_MEMORY_RESTRICT && !bindless) {
439 unsigned reverse_access_mask;
440
441 if (resource_file == TGSI_FILE_BUFFER) {
442 reverse_access_mask = shader_buffers_reverse_access_mask;
443 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
444 reverse_access_mask = info->images_buffers &
445 images_reverse_access_mask;
446 } else {
447 reverse_access_mask = ~info->images_buffers &
448 images_reverse_access_mask;
449 }
450
451 if (resource_indirect) {
452 if (!reverse_access_mask)
453 return true;
454 } else {
455 if (!(reverse_access_mask &
456 (1u << resource_index)))
457 return true;
458 }
459 }
460
461 /* If there are no buffer writes (for both shader buffers & image
462 * buffers), it implies that buffer memory is read-only.
463 * If there are no buffer reads (for both shader buffers & image
464 * buffers), it implies that buffer memory is write-only.
465 *
466 * Same for the case when there are no writes/reads for non-buffer
467 * images.
468 */
469 if (resource_file == TGSI_FILE_BUFFER ||
470 inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
471 if (!shader_buffers_reverse_access_mask &&
472 !(info->images_buffers & images_reverse_access_mask) &&
473 !bindless_buffer_reverse_access_mask)
474 return true;
475 } else {
476 if (!(~info->images_buffers & images_reverse_access_mask) &&
477 !bindless_image_reverse_access_mask)
478 return true;
479 }
480 return false;
481 }
482
483 static void load_emit(
484 const struct lp_build_tgsi_action *action,
485 struct lp_build_tgsi_context *bld_base,
486 struct lp_build_emit_data *emit_data)
487 {
488 struct si_shader_context *ctx = si_shader_context(bld_base);
489 const struct tgsi_full_instruction * inst = emit_data->inst;
490 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
491 bool can_speculate = false;
492 LLVMValueRef vindex = ctx->i32_0;
493 LLVMValueRef voffset = ctx->i32_0;
494 struct ac_image_args args = {};
495
496 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
497 load_emit_memory(ctx, emit_data);
498 return;
499 }
500
501 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
502 inst->Src[0].Register.File == TGSI_FILE_CONSTBUF) {
503 bool ubo = inst->Src[0].Register.File == TGSI_FILE_CONSTBUF;
504 args.resource = shader_buffer_fetch_rsrc(ctx, &inst->Src[0], ubo);
505 voffset = ac_to_integer(&ctx->ac, lp_build_emit_fetch(bld_base, inst, 1, 0));
506 } else {
507 unsigned target = inst->Memory.Texture;
508
509 image_fetch_rsrc(bld_base, &inst->Src[0], false, target, &args.resource);
510 image_fetch_coords(bld_base, inst, 1, args.resource, args.coords);
511 vindex = args.coords[0]; /* for buffers only */
512 }
513
514 if (inst->Src[0].Register.File == TGSI_FILE_CONSTBUF) {
515 emit_data->output[emit_data->chan] =
516 ac_build_buffer_load(&ctx->ac, args.resource,
517 util_last_bit(inst->Dst[0].Register.WriteMask),
518 NULL, voffset, NULL, 0, 0, 0, true, true);
519 return;
520 }
521
522 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
523 ac_build_waitcnt(&ctx->ac, AC_WAIT_VLOAD | AC_WAIT_VSTORE);
524
525 can_speculate = !(inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE) &&
526 is_oneway_access_only(inst, info,
527 info->shader_buffers_store |
528 info->shader_buffers_atomic,
529 info->images_store |
530 info->images_atomic,
531 info->uses_bindless_buffer_store |
532 info->uses_bindless_buffer_atomic,
533 info->uses_bindless_image_store |
534 info->uses_bindless_image_atomic);
535 args.cache_policy = get_cache_policy(ctx, inst, true, false, false, false);
536
537 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
538 /* Don't use SMEM for shader buffer loads, because LLVM doesn't
539 * select SMEM for SI.load.const with a non-constant offset, and
540 * constant offsets practically don't exist with shader buffers.
541 *
542 * Also, SI.load.const doesn't use inst_offset when it's lowered
543 * to VMEM, so we just end up with more VALU instructions in the end
544 * and no benefit.
545 *
546 * TODO: Remove this line once LLVM can select SMEM with a non-constant
547 * offset, and can derive inst_offset when VMEM is selected.
548 * After that, si_memory_barrier should invalidate sL1 for shader
549 * buffers.
550 */
551 emit_data->output[emit_data->chan] =
552 ac_build_buffer_load(&ctx->ac, args.resource,
553 util_last_bit(inst->Dst[0].Register.WriteMask),
554 NULL, voffset, NULL, 0,
555 !!(args.cache_policy & ac_glc),
556 !!(args.cache_policy & ac_slc),
557 can_speculate, false);
558 return;
559 }
560
561 if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
562 unsigned num_channels = util_last_bit(inst->Dst[0].Register.WriteMask);
563 LLVMValueRef result =
564 ac_build_buffer_load_format(&ctx->ac,
565 args.resource,
566 vindex,
567 ctx->i32_0,
568 num_channels,
569 !!(args.cache_policy & ac_glc),
570 can_speculate);
571 emit_data->output[emit_data->chan] =
572 ac_build_expand_to_vec4(&ctx->ac, result, num_channels);
573 } else {
574 args.opcode = ac_image_load;
575 args.dim = ac_image_dim_from_tgsi_target(ctx->screen, inst->Memory.Texture);
576 args.attributes = ac_get_load_intr_attribs(can_speculate);
577 args.dmask = 0xf;
578
579 emit_data->output[emit_data->chan] =
580 ac_build_image_opcode(&ctx->ac, &args);
581 }
582 }
583
584 static void store_emit_buffer(struct si_shader_context *ctx,
585 LLVMValueRef resource,
586 unsigned writemask,
587 LLVMValueRef value,
588 LLVMValueRef voffset,
589 unsigned cache_policy,
590 bool writeonly_memory)
591 {
592 LLVMBuilderRef builder = ctx->ac.builder;
593 LLVMValueRef base_data = value;
594 LLVMValueRef base_offset = voffset;
595
596 while (writemask) {
597 int start, count;
598 LLVMValueRef data, voff;
599
600 u_bit_scan_consecutive_range(&writemask, &start, &count);
601
602 if (count == 3 && ac_has_vec3_support(ctx->ac.chip_class, false)) {
603 LLVMValueRef values[3] = {
604 LLVMBuildExtractElement(builder, base_data,
605 LLVMConstInt(ctx->i32, start, 0), ""),
606 LLVMBuildExtractElement(builder, base_data,
607 LLVMConstInt(ctx->i32, start + 1, 0), ""),
608 LLVMBuildExtractElement(builder, base_data,
609 LLVMConstInt(ctx->i32, start + 2, 0), ""),
610 };
611 data = ac_build_gather_values(&ctx->ac, values, 3);
612 } else if (count >= 3) {
613 data = base_data;
614 } else if (count == 2) {
615 LLVMValueRef values[2] = {
616 LLVMBuildExtractElement(builder, base_data,
617 LLVMConstInt(ctx->i32, start, 0), ""),
618 LLVMBuildExtractElement(builder, base_data,
619 LLVMConstInt(ctx->i32, start + 1, 0), ""),
620 };
621
622 data = ac_build_gather_values(&ctx->ac, values, 2);
623 } else {
624 assert(count == 1);
625 data = LLVMBuildExtractElement(
626 builder, base_data,
627 LLVMConstInt(ctx->i32, start, 0), "");
628 }
629
630 voff = base_offset;
631 if (start != 0) {
632 voff = LLVMBuildAdd(
633 builder, voff,
634 LLVMConstInt(ctx->i32, start * 4, 0), "");
635 }
636
637 ac_build_buffer_store_dword(&ctx->ac, resource, data, count,
638 voff, ctx->i32_0, 0, cache_policy,
639 false);
640 }
641 }
642
643 static void store_emit_memory(
644 struct si_shader_context *ctx,
645 struct lp_build_emit_data *emit_data)
646 {
647 const struct tgsi_full_instruction *inst = emit_data->inst;
648 LLVMBuilderRef builder = ctx->ac.builder;
649 unsigned writemask = inst->Dst[0].Register.WriteMask;
650 LLVMValueRef ptr, derived_ptr, data, index;
651 int chan;
652
653 ptr = get_memory_ptr(ctx, inst, ctx->f32, 0);
654
655 for (chan = 0; chan < 4; ++chan) {
656 if (!(writemask & (1 << chan))) {
657 continue;
658 }
659 data = lp_build_emit_fetch(&ctx->bld_base, inst, 1, chan);
660 index = LLVMConstInt(ctx->i32, chan, 0);
661 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
662 LLVMBuildStore(builder, data, derived_ptr);
663 }
664 }
665
666 static void store_emit(
667 const struct lp_build_tgsi_action *action,
668 struct lp_build_tgsi_context *bld_base,
669 struct lp_build_emit_data *emit_data)
670 {
671 struct si_shader_context *ctx = si_shader_context(bld_base);
672 const struct tgsi_full_instruction * inst = emit_data->inst;
673 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
674 struct tgsi_full_src_register resource_reg =
675 tgsi_full_src_register_from_dst(&inst->Dst[0]);
676 unsigned target = inst->Memory.Texture;
677
678 if (inst->Dst[0].Register.File == TGSI_FILE_MEMORY) {
679 store_emit_memory(ctx, emit_data);
680 return;
681 }
682
683 bool writeonly_memory = is_oneway_access_only(inst, info,
684 info->shader_buffers_load |
685 info->shader_buffers_atomic,
686 info->images_load |
687 info->images_atomic,
688 info->uses_bindless_buffer_load |
689 info->uses_bindless_buffer_atomic,
690 info->uses_bindless_image_load |
691 info->uses_bindless_image_atomic);
692 LLVMValueRef chans[4];
693 LLVMValueRef vindex = ctx->i32_0;
694 LLVMValueRef voffset = ctx->i32_0;
695 struct ac_image_args args = {};
696
697 for (unsigned chan = 0; chan < 4; ++chan)
698 chans[chan] = lp_build_emit_fetch(bld_base, inst, 1, chan);
699
700 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
701 args.resource = shader_buffer_fetch_rsrc(ctx, &resource_reg, false);
702 voffset = ac_to_integer(&ctx->ac, lp_build_emit_fetch(bld_base, inst, 0, 0));
703 } else {
704 image_fetch_rsrc(bld_base, &resource_reg, true, target, &args.resource);
705 image_fetch_coords(bld_base, inst, 0, args.resource, args.coords);
706 vindex = args.coords[0]; /* for buffers only */
707 }
708
709 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
710 ac_build_waitcnt(&ctx->ac, AC_WAIT_VLOAD | AC_WAIT_VSTORE);
711
712 bool is_image = inst->Dst[0].Register.File != TGSI_FILE_BUFFER;
713 args.cache_policy = get_cache_policy(ctx, inst,
714 false, /* load */
715 false, /* atomic */
716 is_image, /* may_store_unaligned */
717 writeonly_memory);
718
719 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
720 store_emit_buffer(ctx, args.resource, inst->Dst[0].Register.WriteMask,
721 ac_build_gather_values(&ctx->ac, chans, 4),
722 voffset, args.cache_policy, writeonly_memory);
723 return;
724 }
725
726 if (target == TGSI_TEXTURE_BUFFER) {
727 unsigned num_channels = util_last_bit(inst->Dst[0].Register.WriteMask);
728
729 ac_build_buffer_store_format(&ctx->ac, args.resource,
730 ac_build_gather_values(&ctx->ac, chans, num_channels),
731 vindex, ctx->i32_0 /* voffset */,
732 num_channels,
733 args.cache_policy);
734 } else {
735 args.opcode = ac_image_store;
736 args.data[0] = ac_build_gather_values(&ctx->ac, chans, 4);
737 args.dim = ac_image_dim_from_tgsi_target(ctx->screen, inst->Memory.Texture);
738 args.attributes = AC_FUNC_ATTR_INACCESSIBLE_MEM_ONLY;
739 args.dmask = 0xf;
740
741 emit_data->output[emit_data->chan] =
742 ac_build_image_opcode(&ctx->ac, &args);
743 }
744 }
745
746 static void atomic_emit_memory(struct si_shader_context *ctx,
747 struct lp_build_emit_data *emit_data) {
748 LLVMBuilderRef builder = ctx->ac.builder;
749 const struct tgsi_full_instruction * inst = emit_data->inst;
750 LLVMValueRef ptr, result, arg;
751 const char *sync_scope = HAVE_LLVM >= 0x0900 ? "workgroup-one-as" : "workgroup";
752
753 ptr = get_memory_ptr(ctx, inst, ctx->i32, 1);
754
755 arg = lp_build_emit_fetch(&ctx->bld_base, inst, 2, 0);
756 arg = ac_to_integer(&ctx->ac, arg);
757
758 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
759 LLVMValueRef new_data;
760 new_data = lp_build_emit_fetch(&ctx->bld_base,
761 inst, 3, 0);
762
763 new_data = ac_to_integer(&ctx->ac, new_data);
764
765 result = ac_build_atomic_cmp_xchg(&ctx->ac, ptr, arg, new_data,
766 sync_scope);
767 result = LLVMBuildExtractValue(builder, result, 0, "");
768 } else {
769 LLVMAtomicRMWBinOp op;
770
771 switch(inst->Instruction.Opcode) {
772 case TGSI_OPCODE_ATOMUADD:
773 op = LLVMAtomicRMWBinOpAdd;
774 break;
775 case TGSI_OPCODE_ATOMXCHG:
776 op = LLVMAtomicRMWBinOpXchg;
777 break;
778 case TGSI_OPCODE_ATOMAND:
779 op = LLVMAtomicRMWBinOpAnd;
780 break;
781 case TGSI_OPCODE_ATOMOR:
782 op = LLVMAtomicRMWBinOpOr;
783 break;
784 case TGSI_OPCODE_ATOMXOR:
785 op = LLVMAtomicRMWBinOpXor;
786 break;
787 case TGSI_OPCODE_ATOMUMIN:
788 op = LLVMAtomicRMWBinOpUMin;
789 break;
790 case TGSI_OPCODE_ATOMUMAX:
791 op = LLVMAtomicRMWBinOpUMax;
792 break;
793 case TGSI_OPCODE_ATOMIMIN:
794 op = LLVMAtomicRMWBinOpMin;
795 break;
796 case TGSI_OPCODE_ATOMIMAX:
797 op = LLVMAtomicRMWBinOpMax;
798 break;
799 default:
800 unreachable("unknown atomic opcode");
801 }
802
803 result = ac_build_atomic_rmw(&ctx->ac, op, ptr, arg, sync_scope);
804 }
805 emit_data->output[emit_data->chan] =
806 LLVMBuildBitCast(builder, result, ctx->f32, "");
807 }
808
809 static void atomic_emit(
810 const struct lp_build_tgsi_action *action,
811 struct lp_build_tgsi_context *bld_base,
812 struct lp_build_emit_data *emit_data)
813 {
814 struct si_shader_context *ctx = si_shader_context(bld_base);
815 const struct tgsi_full_instruction * inst = emit_data->inst;
816 struct ac_image_args args = {};
817 unsigned num_data = 0;
818 LLVMValueRef vindex = ctx->i32_0;
819 LLVMValueRef voffset = ctx->i32_0;
820
821 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
822 atomic_emit_memory(ctx, emit_data);
823 return;
824 }
825
826 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
827 /* llvm.amdgcn.image/buffer.atomic.cmpswap reflect the hardware order
828 * of arguments, which is reversed relative to TGSI (and GLSL)
829 */
830 args.data[num_data++] =
831 ac_to_integer(&ctx->ac, lp_build_emit_fetch(bld_base, inst, 3, 0));
832 }
833
834 args.data[num_data++] =
835 ac_to_integer(&ctx->ac, lp_build_emit_fetch(bld_base, inst, 2, 0));
836 args.cache_policy = get_cache_policy(ctx, inst, false, true, false, false);
837
838 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
839 args.resource = shader_buffer_fetch_rsrc(ctx, &inst->Src[0], false);
840 voffset = ac_to_integer(&ctx->ac, lp_build_emit_fetch(bld_base, inst, 1, 0));
841 } else {
842 image_fetch_rsrc(bld_base, &inst->Src[0], true,
843 inst->Memory.Texture, &args.resource);
844 image_fetch_coords(bld_base, inst, 1, args.resource, args.coords);
845 vindex = args.coords[0]; /* for buffers only */
846 }
847
848 if (HAVE_LLVM >= 0x0800 &&
849 inst->Src[0].Register.File != TGSI_FILE_BUFFER &&
850 inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
851 LLVMValueRef buf_args[7];
852 unsigned num_args = 0;
853
854 buf_args[num_args++] = args.data[0];
855 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
856 buf_args[num_args++] = args.data[1];
857
858 buf_args[num_args++] = args.resource;
859 buf_args[num_args++] = vindex;
860 buf_args[num_args++] = voffset;
861 buf_args[num_args++] = ctx->i32_0; /* soffset */
862 buf_args[num_args++] = LLVMConstInt(ctx->i32, args.cache_policy & ac_slc, 0);
863
864 char intrinsic_name[64];
865 snprintf(intrinsic_name, sizeof(intrinsic_name),
866 "llvm.amdgcn.struct.buffer.atomic.%s", action->intr_name);
867 emit_data->output[emit_data->chan] =
868 ac_to_float(&ctx->ac,
869 ac_build_intrinsic(&ctx->ac, intrinsic_name,
870 ctx->i32, buf_args, num_args, 0));
871 return;
872 }
873
874 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
875 (HAVE_LLVM < 0x0800 &&
876 inst->Memory.Texture == TGSI_TEXTURE_BUFFER)) {
877 LLVMValueRef buf_args[7];
878 unsigned num_args = 0;
879
880 buf_args[num_args++] = args.data[0];
881 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
882 buf_args[num_args++] = args.data[1];
883
884 buf_args[num_args++] = args.resource;
885 buf_args[num_args++] = vindex;
886 buf_args[num_args++] = voffset;
887 buf_args[num_args++] = args.cache_policy & ac_slc ? ctx->i1true : ctx->i1false;
888
889 char intrinsic_name[40];
890 snprintf(intrinsic_name, sizeof(intrinsic_name),
891 "llvm.amdgcn.buffer.atomic.%s", action->intr_name);
892 emit_data->output[emit_data->chan] =
893 ac_to_float(&ctx->ac,
894 ac_build_intrinsic(&ctx->ac, intrinsic_name,
895 ctx->i32, buf_args, num_args, 0));
896 } else {
897 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
898 args.opcode = ac_image_atomic_cmpswap;
899 } else {
900 args.opcode = ac_image_atomic;
901 switch (inst->Instruction.Opcode) {
902 case TGSI_OPCODE_ATOMXCHG: args.atomic = ac_atomic_swap; break;
903 case TGSI_OPCODE_ATOMUADD: args.atomic = ac_atomic_add; break;
904 case TGSI_OPCODE_ATOMAND: args.atomic = ac_atomic_and; break;
905 case TGSI_OPCODE_ATOMOR: args.atomic = ac_atomic_or; break;
906 case TGSI_OPCODE_ATOMXOR: args.atomic = ac_atomic_xor; break;
907 case TGSI_OPCODE_ATOMUMIN: args.atomic = ac_atomic_umin; break;
908 case TGSI_OPCODE_ATOMUMAX: args.atomic = ac_atomic_umax; break;
909 case TGSI_OPCODE_ATOMIMIN: args.atomic = ac_atomic_smin; break;
910 case TGSI_OPCODE_ATOMIMAX: args.atomic = ac_atomic_smax; break;
911 default: unreachable("unhandled image atomic");
912 }
913 }
914
915 args.dim = ac_image_dim_from_tgsi_target(ctx->screen, inst->Memory.Texture);
916 emit_data->output[emit_data->chan] =
917 ac_to_float(&ctx->ac, ac_build_image_opcode(&ctx->ac, &args));
918 }
919 }
920
921 static LLVMValueRef fix_resinfo(struct si_shader_context *ctx,
922 unsigned target, LLVMValueRef out)
923 {
924 LLVMBuilderRef builder = ctx->ac.builder;
925
926 /* 1D textures are allocated and used as 2D on GFX9. */
927 if (ctx->screen->info.chip_class >= GFX9 &&
928 (target == TGSI_TEXTURE_1D_ARRAY ||
929 target == TGSI_TEXTURE_SHADOW1D_ARRAY)) {
930 LLVMValueRef layers =
931 LLVMBuildExtractElement(builder, out,
932 LLVMConstInt(ctx->i32, 2, 0), "");
933 out = LLVMBuildInsertElement(builder, out, layers,
934 ctx->i32_1, "");
935 }
936
937 /* Divide the number of layers by 6 to get the number of cubes. */
938 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
939 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
940 LLVMValueRef imm2 = LLVMConstInt(ctx->i32, 2, 0);
941
942 LLVMValueRef z = LLVMBuildExtractElement(builder, out, imm2, "");
943 z = LLVMBuildSDiv(builder, z, LLVMConstInt(ctx->i32, 6, 0), "");
944
945 out = LLVMBuildInsertElement(builder, out, z, imm2, "");
946 }
947 return out;
948 }
949
950 static void resq_emit(
951 const struct lp_build_tgsi_action *action,
952 struct lp_build_tgsi_context *bld_base,
953 struct lp_build_emit_data *emit_data)
954 {
955 struct si_shader_context *ctx = si_shader_context(bld_base);
956 LLVMBuilderRef builder = ctx->ac.builder;
957 const struct tgsi_full_instruction *inst = emit_data->inst;
958 const struct tgsi_full_src_register *reg =
959 &inst->Src[inst->Instruction.Opcode == TGSI_OPCODE_TXQ ? 1 : 0];
960
961 if (reg->Register.File == TGSI_FILE_BUFFER) {
962 LLVMValueRef rsrc = shader_buffer_fetch_rsrc(ctx, reg, false);
963
964 emit_data->output[emit_data->chan] =
965 LLVMBuildExtractElement(builder, rsrc,
966 LLVMConstInt(ctx->i32, 2, 0), "");
967 return;
968 }
969
970 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ &&
971 inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
972 LLVMValueRef rsrc;
973
974 tex_fetch_ptrs(bld_base, emit_data, &rsrc, NULL, NULL);
975 /* Read the size from the buffer descriptor directly. */
976 emit_data->output[emit_data->chan] =
977 get_buffer_size(bld_base, rsrc);
978 return;
979 }
980
981 if (inst->Instruction.Opcode == TGSI_OPCODE_RESQ &&
982 inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
983 LLVMValueRef rsrc;
984
985 image_fetch_rsrc(bld_base, reg, false, inst->Memory.Texture, &rsrc);
986 emit_data->output[emit_data->chan] =
987 get_buffer_size(bld_base, rsrc);
988 return;
989 }
990
991 unsigned target;
992
993 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ) {
994 target = inst->Texture.Texture;
995 } else {
996 if (inst->Memory.Texture == TGSI_TEXTURE_3D)
997 target = TGSI_TEXTURE_2D_ARRAY;
998 else
999 target = inst->Memory.Texture;
1000 }
1001
1002 struct ac_image_args args = {};
1003 args.opcode = ac_image_get_resinfo;
1004 args.dim = ac_texture_dim_from_tgsi_target(ctx->screen, target);
1005 args.dmask = 0xf;
1006 args.attributes = AC_FUNC_ATTR_READNONE;
1007
1008 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ) {
1009 tex_fetch_ptrs(bld_base, emit_data, &args.resource, NULL, NULL);
1010 args.lod = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
1011 } else {
1012 image_fetch_rsrc(bld_base, reg, false, target, &args.resource);
1013 args.lod = ctx->i32_0;
1014 }
1015
1016 emit_data->output[emit_data->chan] =
1017 fix_resinfo(ctx, target, ac_build_image_opcode(&ctx->ac, &args));
1018 }
1019
1020 /**
1021 * Load an image view, fmask view. or sampler state descriptor.
1022 */
1023 LLVMValueRef si_load_sampler_desc(struct si_shader_context *ctx,
1024 LLVMValueRef list, LLVMValueRef index,
1025 enum ac_descriptor_type type)
1026 {
1027 LLVMBuilderRef builder = ctx->ac.builder;
1028
1029 switch (type) {
1030 case AC_DESC_IMAGE:
1031 /* The image is at [0:7]. */
1032 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
1033 break;
1034 case AC_DESC_BUFFER:
1035 /* The buffer is in [4:7]. */
1036 index = ac_build_imad(&ctx->ac, index, LLVMConstInt(ctx->i32, 4, 0),
1037 ctx->i32_1);
1038 list = LLVMBuildPointerCast(builder, list,
1039 ac_array_in_const32_addr_space(ctx->v4i32), "");
1040 break;
1041 case AC_DESC_FMASK:
1042 /* The FMASK is at [8:15]. */
1043 index = ac_build_imad(&ctx->ac, index, LLVMConstInt(ctx->i32, 2, 0),
1044 ctx->i32_1);
1045 break;
1046 case AC_DESC_SAMPLER:
1047 /* The sampler state is at [12:15]. */
1048 index = ac_build_imad(&ctx->ac, index, LLVMConstInt(ctx->i32, 4, 0),
1049 LLVMConstInt(ctx->i32, 3, 0));
1050 list = LLVMBuildPointerCast(builder, list,
1051 ac_array_in_const32_addr_space(ctx->v4i32), "");
1052 break;
1053 case AC_DESC_PLANE_0:
1054 case AC_DESC_PLANE_1:
1055 case AC_DESC_PLANE_2:
1056 /* Only used for the multiplane image support for Vulkan. Should
1057 * never be reached in radeonsi.
1058 */
1059 unreachable("Plane descriptor requested in radeonsi.");
1060 }
1061
1062 return ac_build_load_to_sgpr(&ctx->ac, list, index);
1063 }
1064
1065 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
1066 *
1067 * GFX6-GFX7:
1068 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
1069 * filtering manually. The driver sets img7 to a mask clearing
1070 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
1071 * s_and_b32 samp0, samp0, img7
1072 *
1073 * GFX8:
1074 * The ANISO_OVERRIDE sampler field enables this fix in TA.
1075 */
1076 static LLVMValueRef sici_fix_sampler_aniso(struct si_shader_context *ctx,
1077 LLVMValueRef res, LLVMValueRef samp)
1078 {
1079 LLVMValueRef img7, samp0;
1080
1081 if (ctx->screen->info.chip_class >= GFX8)
1082 return samp;
1083
1084 img7 = LLVMBuildExtractElement(ctx->ac.builder, res,
1085 LLVMConstInt(ctx->i32, 7, 0), "");
1086 samp0 = LLVMBuildExtractElement(ctx->ac.builder, samp,
1087 ctx->i32_0, "");
1088 samp0 = LLVMBuildAnd(ctx->ac.builder, samp0, img7, "");
1089 return LLVMBuildInsertElement(ctx->ac.builder, samp, samp0,
1090 ctx->i32_0, "");
1091 }
1092
1093 static void tex_fetch_ptrs(struct lp_build_tgsi_context *bld_base,
1094 struct lp_build_emit_data *emit_data,
1095 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
1096 LLVMValueRef *fmask_ptr)
1097 {
1098 struct si_shader_context *ctx = si_shader_context(bld_base);
1099 LLVMValueRef list = LLVMGetParam(ctx->main_fn, ctx->param_samplers_and_images);
1100 const struct tgsi_full_instruction *inst = emit_data->inst;
1101 const struct tgsi_full_src_register *reg;
1102 unsigned target = inst->Texture.Texture;
1103 unsigned sampler_src;
1104 LLVMValueRef index;
1105
1106 sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
1107 reg = &emit_data->inst->Src[sampler_src];
1108
1109 if (reg->Register.Indirect) {
1110 index = si_get_bounded_indirect_index(ctx,
1111 &reg->Indirect,
1112 reg->Register.Index,
1113 ctx->num_samplers);
1114 index = LLVMBuildAdd(ctx->ac.builder, index,
1115 LLVMConstInt(ctx->i32, SI_NUM_IMAGES / 2, 0), "");
1116 } else {
1117 index = LLVMConstInt(ctx->i32,
1118 si_get_sampler_slot(reg->Register.Index), 0);
1119 }
1120
1121 if (reg->Register.File != TGSI_FILE_SAMPLER) {
1122 /* Bindless descriptors are accessible from a different pair of
1123 * user SGPR indices.
1124 */
1125 list = LLVMGetParam(ctx->main_fn,
1126 ctx->param_bindless_samplers_and_images);
1127 index = lp_build_emit_fetch_src(bld_base, reg,
1128 TGSI_TYPE_UNSIGNED, 0);
1129
1130 /* Since bindless handle arithmetic can contain an unsigned integer
1131 * wraparound and si_load_sampler_desc assumes there isn't any,
1132 * use GEP without "inbounds" (inside ac_build_pointer_add)
1133 * to prevent incorrect code generation and hangs.
1134 */
1135 index = LLVMBuildMul(ctx->ac.builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
1136 list = ac_build_pointer_add(&ctx->ac, list, index);
1137 index = ctx->i32_0;
1138 }
1139
1140 if (target == TGSI_TEXTURE_BUFFER)
1141 *res_ptr = si_load_sampler_desc(ctx, list, index, AC_DESC_BUFFER);
1142 else
1143 *res_ptr = si_load_sampler_desc(ctx, list, index, AC_DESC_IMAGE);
1144
1145 if (samp_ptr)
1146 *samp_ptr = NULL;
1147 if (fmask_ptr)
1148 *fmask_ptr = NULL;
1149
1150 if (target == TGSI_TEXTURE_2D_MSAA ||
1151 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
1152 if (fmask_ptr)
1153 *fmask_ptr = si_load_sampler_desc(ctx, list, index,
1154 AC_DESC_FMASK);
1155 } else if (target != TGSI_TEXTURE_BUFFER) {
1156 if (samp_ptr) {
1157 *samp_ptr = si_load_sampler_desc(ctx, list, index,
1158 AC_DESC_SAMPLER);
1159 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
1160 }
1161 }
1162 }
1163
1164 /* Gather4 should follow the same rules as bilinear filtering, but the hardware
1165 * incorrectly forces nearest filtering if the texture format is integer.
1166 * The only effect it has on Gather4, which always returns 4 texels for
1167 * bilinear filtering, is that the final coordinates are off by 0.5 of
1168 * the texel size.
1169 *
1170 * The workaround is to subtract 0.5 from the unnormalized coordinates,
1171 * or (0.5 / size) from the normalized coordinates.
1172 *
1173 * However, cube textures with 8_8_8_8 data formats require a different
1174 * workaround of overriding the num format to USCALED/SSCALED. This would lose
1175 * precision in 32-bit data formats, so it needs to be applied dynamically at
1176 * runtime. In this case, return an i1 value that indicates whether the
1177 * descriptor was overridden (and hence a fixup of the sampler result is needed).
1178 */
1179 static LLVMValueRef
1180 si_lower_gather4_integer(struct si_shader_context *ctx,
1181 struct ac_image_args *args,
1182 unsigned target,
1183 enum tgsi_return_type return_type)
1184 {
1185 LLVMBuilderRef builder = ctx->ac.builder;
1186 LLVMValueRef wa_8888 = NULL;
1187 LLVMValueRef half_texel[2];
1188
1189 assert(return_type == TGSI_RETURN_TYPE_SINT ||
1190 return_type == TGSI_RETURN_TYPE_UINT);
1191
1192 if (target == TGSI_TEXTURE_CUBE ||
1193 target == TGSI_TEXTURE_CUBE_ARRAY) {
1194 LLVMValueRef formats;
1195 LLVMValueRef data_format;
1196 LLVMValueRef wa_formats;
1197
1198 formats = LLVMBuildExtractElement(builder, args->resource, ctx->i32_1, "");
1199
1200 data_format = LLVMBuildLShr(builder, formats,
1201 LLVMConstInt(ctx->i32, 20, false), "");
1202 data_format = LLVMBuildAnd(builder, data_format,
1203 LLVMConstInt(ctx->i32, (1u << 6) - 1, false), "");
1204 wa_8888 = LLVMBuildICmp(
1205 builder, LLVMIntEQ, data_format,
1206 LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false),
1207 "");
1208
1209 uint32_t wa_num_format =
1210 return_type == TGSI_RETURN_TYPE_UINT ?
1211 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_USCALED) :
1212 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_SSCALED);
1213 wa_formats = LLVMBuildAnd(builder, formats,
1214 LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT, false),
1215 "");
1216 wa_formats = LLVMBuildOr(builder, wa_formats,
1217 LLVMConstInt(ctx->i32, wa_num_format, false), "");
1218
1219 formats = LLVMBuildSelect(builder, wa_8888, wa_formats, formats, "");
1220 args->resource = LLVMBuildInsertElement(
1221 builder, args->resource, formats, ctx->i32_1, "");
1222 }
1223
1224 if (target == TGSI_TEXTURE_RECT ||
1225 target == TGSI_TEXTURE_SHADOWRECT) {
1226 assert(!wa_8888);
1227 half_texel[0] = half_texel[1] = LLVMConstReal(ctx->f32, -0.5);
1228 } else {
1229 struct ac_image_args resinfo = {};
1230 struct lp_build_if_state if_ctx;
1231
1232 if (wa_8888) {
1233 /* Skip the texture size query entirely if we don't need it. */
1234 lp_build_if(&if_ctx, &ctx->gallivm, LLVMBuildNot(builder, wa_8888, ""));
1235 }
1236
1237 /* Query the texture size. */
1238 resinfo.opcode = ac_image_get_resinfo;
1239 resinfo.dim = ac_texture_dim_from_tgsi_target(ctx->screen, target);
1240 resinfo.resource = args->resource;
1241 resinfo.sampler = args->sampler;
1242 resinfo.lod = ctx->ac.i32_0;
1243 resinfo.dmask = 0xf;
1244 resinfo.attributes = AC_FUNC_ATTR_READNONE;
1245
1246 LLVMValueRef texsize =
1247 fix_resinfo(ctx, target,
1248 ac_build_image_opcode(&ctx->ac, &resinfo));
1249
1250 /* Compute -0.5 / size. */
1251 for (unsigned c = 0; c < 2; c++) {
1252 half_texel[c] =
1253 LLVMBuildExtractElement(builder, texsize,
1254 LLVMConstInt(ctx->i32, c, 0), "");
1255 half_texel[c] = LLVMBuildUIToFP(builder, half_texel[c], ctx->f32, "");
1256 half_texel[c] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, half_texel[c]);
1257 half_texel[c] = LLVMBuildFMul(builder, half_texel[c],
1258 LLVMConstReal(ctx->f32, -0.5), "");
1259 }
1260
1261 if (wa_8888) {
1262 lp_build_endif(&if_ctx);
1263
1264 LLVMBasicBlockRef bb[2] = { if_ctx.true_block, if_ctx.entry_block };
1265
1266 for (unsigned c = 0; c < 2; c++) {
1267 LLVMValueRef values[2] = { half_texel[c], ctx->ac.f32_0 };
1268 half_texel[c] = ac_build_phi(&ctx->ac, ctx->f32, 2,
1269 values, bb);
1270 }
1271 }
1272 }
1273
1274 for (unsigned c = 0; c < 2; c++) {
1275 LLVMValueRef tmp;
1276 tmp = ac_to_float(&ctx->ac, args->coords[c]);
1277 tmp = LLVMBuildFAdd(builder, tmp, half_texel[c], "");
1278 args->coords[c] = ac_to_integer(&ctx->ac, tmp);
1279 }
1280
1281 return wa_8888;
1282 }
1283
1284 /* The second half of the cube texture 8_8_8_8 integer workaround: adjust the
1285 * result after the gather operation.
1286 */
1287 static LLVMValueRef
1288 si_fix_gather4_integer_result(struct si_shader_context *ctx,
1289 LLVMValueRef result,
1290 enum tgsi_return_type return_type,
1291 LLVMValueRef wa)
1292 {
1293 LLVMBuilderRef builder = ctx->ac.builder;
1294
1295 assert(return_type == TGSI_RETURN_TYPE_SINT ||
1296 return_type == TGSI_RETURN_TYPE_UINT);
1297
1298 for (unsigned chan = 0; chan < 4; ++chan) {
1299 LLVMValueRef chanv = LLVMConstInt(ctx->i32, chan, false);
1300 LLVMValueRef value;
1301 LLVMValueRef wa_value;
1302
1303 value = LLVMBuildExtractElement(builder, result, chanv, "");
1304
1305 if (return_type == TGSI_RETURN_TYPE_UINT)
1306 wa_value = LLVMBuildFPToUI(builder, value, ctx->i32, "");
1307 else
1308 wa_value = LLVMBuildFPToSI(builder, value, ctx->i32, "");
1309 wa_value = ac_to_float(&ctx->ac, wa_value);
1310 value = LLVMBuildSelect(builder, wa, wa_value, value, "");
1311
1312 result = LLVMBuildInsertElement(builder, result, value, chanv, "");
1313 }
1314
1315 return result;
1316 }
1317
1318 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
1319 struct lp_build_tgsi_context *bld_base,
1320 struct lp_build_emit_data *emit_data)
1321 {
1322 struct si_shader_context *ctx = si_shader_context(bld_base);
1323 const struct tgsi_full_instruction *inst = emit_data->inst;
1324 unsigned opcode = inst->Instruction.Opcode;
1325 unsigned target = inst->Texture.Texture;
1326 struct ac_image_args args = {};
1327 int ref_pos = tgsi_util_get_shadow_ref_src_index(target);
1328 unsigned chan;
1329 bool has_offset = inst->Texture.NumOffsets > 0;
1330 LLVMValueRef fmask_ptr = NULL;
1331
1332 tex_fetch_ptrs(bld_base, emit_data, &args.resource, &args.sampler, &fmask_ptr);
1333
1334 if (target == TGSI_TEXTURE_BUFFER) {
1335 LLVMValueRef vindex = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
1336 unsigned num_channels =
1337 util_last_bit(inst->Dst[0].Register.WriteMask);
1338 LLVMValueRef result =
1339 ac_build_buffer_load_format(&ctx->ac,
1340 args.resource,
1341 vindex,
1342 ctx->i32_0,
1343 num_channels, false, true);
1344 emit_data->output[emit_data->chan] =
1345 ac_build_expand_to_vec4(&ctx->ac, result, num_channels);
1346 return;
1347 }
1348
1349 /* Fetch and project texture coordinates */
1350 args.coords[3] = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_W);
1351 for (chan = 0; chan < 3; chan++) {
1352 args.coords[chan] = lp_build_emit_fetch(bld_base, inst, 0, chan);
1353 if (opcode == TGSI_OPCODE_TXP)
1354 args.coords[chan] = ac_build_fdiv(&ctx->ac,
1355 args.coords[chan], args.coords[3]);
1356 }
1357
1358 if (opcode == TGSI_OPCODE_TXP)
1359 args.coords[3] = ctx->ac.f32_1;
1360
1361 /* Pack offsets. */
1362 if (has_offset &&
1363 opcode != TGSI_OPCODE_TXF &&
1364 opcode != TGSI_OPCODE_TXF_LZ) {
1365 /* The offsets are six-bit signed integers packed like this:
1366 * X=[5:0], Y=[13:8], and Z=[21:16].
1367 */
1368 LLVMValueRef offset[3], pack;
1369
1370 assert(inst->Texture.NumOffsets == 1);
1371
1372 for (chan = 0; chan < 3; chan++) {
1373 offset[chan] = lp_build_emit_fetch_texoffset(bld_base, inst, 0, chan);
1374 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
1375 LLVMConstInt(ctx->i32, 0x3f, 0), "");
1376 if (chan)
1377 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
1378 LLVMConstInt(ctx->i32, chan*8, 0), "");
1379 }
1380
1381 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
1382 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
1383 args.offset = pack;
1384 }
1385
1386 /* Pack LOD bias value */
1387 if (opcode == TGSI_OPCODE_TXB)
1388 args.bias = args.coords[3];
1389 if (opcode == TGSI_OPCODE_TXB2)
1390 args.bias = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
1391
1392 /* Pack depth comparison value */
1393 if (tgsi_is_shadow_target(target) && opcode != TGSI_OPCODE_LODQ) {
1394 LLVMValueRef z;
1395
1396 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
1397 z = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
1398 } else {
1399 assert(ref_pos >= 0);
1400 z = args.coords[ref_pos];
1401 }
1402
1403 /* Section 8.23.1 (Depth Texture Comparison Mode) of the
1404 * OpenGL 4.5 spec says:
1405 *
1406 * "If the texture’s internal format indicates a fixed-point
1407 * depth texture, then D_t and D_ref are clamped to the
1408 * range [0, 1]; otherwise no clamping is performed."
1409 *
1410 * TC-compatible HTILE promotes Z16 and Z24 to Z32_FLOAT,
1411 * so the depth comparison value isn't clamped for Z16 and
1412 * Z24 anymore. Do it manually here for GFX8-9; GFX10 has
1413 * an explicitly clamped 32-bit float format.
1414 */
1415 if (ctx->screen->info.chip_class >= GFX8 &&
1416 ctx->screen->info.chip_class <= GFX9) {
1417 LLVMValueRef upgraded;
1418 LLVMValueRef clamped;
1419 upgraded = LLVMBuildExtractElement(ctx->ac.builder, args.sampler,
1420 LLVMConstInt(ctx->i32, 3, false), "");
1421 upgraded = LLVMBuildLShr(ctx->ac.builder, upgraded,
1422 LLVMConstInt(ctx->i32, 29, false), "");
1423 upgraded = LLVMBuildTrunc(ctx->ac.builder, upgraded, ctx->i1, "");
1424 clamped = ac_build_clamp(&ctx->ac, z);
1425 z = LLVMBuildSelect(ctx->ac.builder, upgraded, clamped, z, "");
1426 }
1427
1428 args.compare = z;
1429 }
1430
1431 /* Pack user derivatives */
1432 if (opcode == TGSI_OPCODE_TXD) {
1433 int param, num_src_deriv_channels, num_dst_deriv_channels;
1434
1435 switch (target) {
1436 case TGSI_TEXTURE_3D:
1437 num_src_deriv_channels = 3;
1438 num_dst_deriv_channels = 3;
1439 break;
1440 case TGSI_TEXTURE_2D:
1441 case TGSI_TEXTURE_SHADOW2D:
1442 case TGSI_TEXTURE_RECT:
1443 case TGSI_TEXTURE_SHADOWRECT:
1444 case TGSI_TEXTURE_2D_ARRAY:
1445 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1446 num_src_deriv_channels = 2;
1447 num_dst_deriv_channels = 2;
1448 break;
1449 case TGSI_TEXTURE_CUBE:
1450 case TGSI_TEXTURE_SHADOWCUBE:
1451 case TGSI_TEXTURE_CUBE_ARRAY:
1452 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
1453 /* Cube derivatives will be converted to 2D. */
1454 num_src_deriv_channels = 3;
1455 num_dst_deriv_channels = 3;
1456 break;
1457 case TGSI_TEXTURE_1D:
1458 case TGSI_TEXTURE_SHADOW1D:
1459 case TGSI_TEXTURE_1D_ARRAY:
1460 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1461 num_src_deriv_channels = 1;
1462
1463 /* 1D textures are allocated and used as 2D on GFX9. */
1464 if (ctx->screen->info.chip_class >= GFX9) {
1465 num_dst_deriv_channels = 2;
1466 } else {
1467 num_dst_deriv_channels = 1;
1468 }
1469 break;
1470 default:
1471 unreachable("invalid target");
1472 }
1473
1474 for (param = 0; param < 2; param++) {
1475 for (chan = 0; chan < num_src_deriv_channels; chan++)
1476 args.derivs[param * num_dst_deriv_channels + chan] =
1477 lp_build_emit_fetch(bld_base, inst, param+1, chan);
1478
1479 /* Fill in the rest with zeros. */
1480 for (chan = num_src_deriv_channels;
1481 chan < num_dst_deriv_channels; chan++)
1482 args.derivs[param * num_dst_deriv_channels + chan] =
1483 ctx->ac.f32_0;
1484 }
1485 }
1486
1487 if (target == TGSI_TEXTURE_CUBE ||
1488 target == TGSI_TEXTURE_CUBE_ARRAY ||
1489 target == TGSI_TEXTURE_SHADOWCUBE ||
1490 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
1491 ac_prepare_cube_coords(&ctx->ac,
1492 opcode == TGSI_OPCODE_TXD,
1493 target == TGSI_TEXTURE_CUBE_ARRAY ||
1494 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY,
1495 opcode == TGSI_OPCODE_LODQ,
1496 args.coords, args.derivs);
1497 } else if (tgsi_is_array_sampler(target) &&
1498 opcode != TGSI_OPCODE_TXF &&
1499 opcode != TGSI_OPCODE_TXF_LZ &&
1500 ctx->screen->info.chip_class <= GFX8) {
1501 unsigned array_coord = target == TGSI_TEXTURE_1D_ARRAY ? 1 : 2;
1502 args.coords[array_coord] = ac_build_round(&ctx->ac, args.coords[array_coord]);
1503 }
1504
1505 /* 1D textures are allocated and used as 2D on GFX9. */
1506 if (ctx->screen->info.chip_class >= GFX9) {
1507 LLVMValueRef filler;
1508
1509 /* Use 0.5, so that we don't sample the border color. */
1510 if (opcode == TGSI_OPCODE_TXF ||
1511 opcode == TGSI_OPCODE_TXF_LZ)
1512 filler = ctx->i32_0;
1513 else
1514 filler = LLVMConstReal(ctx->f32, 0.5);
1515
1516 if (target == TGSI_TEXTURE_1D ||
1517 target == TGSI_TEXTURE_SHADOW1D) {
1518 args.coords[1] = filler;
1519 } else if (target == TGSI_TEXTURE_1D_ARRAY ||
1520 target == TGSI_TEXTURE_SHADOW1D_ARRAY) {
1521 args.coords[2] = args.coords[1];
1522 args.coords[1] = filler;
1523 }
1524 }
1525
1526 /* Pack LOD or sample index */
1527 if (opcode == TGSI_OPCODE_TXL)
1528 args.lod = args.coords[3];
1529 else if (opcode == TGSI_OPCODE_TXL2)
1530 args.lod = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
1531 else if (opcode == TGSI_OPCODE_TXF) {
1532 if (target == TGSI_TEXTURE_2D_MSAA) {
1533 /* No LOD, but move sample index into the right place. */
1534 args.coords[2] = args.coords[3];
1535 } else if (target != TGSI_TEXTURE_2D_ARRAY_MSAA) {
1536 args.lod = args.coords[3];
1537 }
1538 }
1539
1540 if ((target == TGSI_TEXTURE_2D_MSAA ||
1541 target == TGSI_TEXTURE_2D_ARRAY_MSAA) &&
1542 !(ctx->screen->debug_flags & DBG(NO_FMASK))) {
1543 ac_apply_fmask_to_sample(&ctx->ac, fmask_ptr, args.coords,
1544 target == TGSI_TEXTURE_2D_ARRAY_MSAA);
1545 }
1546
1547 if (opcode == TGSI_OPCODE_TXF ||
1548 opcode == TGSI_OPCODE_TXF_LZ) {
1549 /* add tex offsets */
1550 if (inst->Texture.NumOffsets) {
1551 const struct tgsi_texture_offset *off = inst->TexOffsets;
1552
1553 assert(inst->Texture.NumOffsets == 1);
1554
1555 switch (target) {
1556 case TGSI_TEXTURE_3D:
1557 args.coords[2] =
1558 LLVMBuildAdd(ctx->ac.builder, args.coords[2],
1559 ctx->imms[off->Index * TGSI_NUM_CHANNELS + off->SwizzleZ], "");
1560 /* fall through */
1561 case TGSI_TEXTURE_2D:
1562 case TGSI_TEXTURE_SHADOW2D:
1563 case TGSI_TEXTURE_RECT:
1564 case TGSI_TEXTURE_SHADOWRECT:
1565 case TGSI_TEXTURE_2D_ARRAY:
1566 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1567 args.coords[1] =
1568 LLVMBuildAdd(ctx->ac.builder, args.coords[1],
1569 ctx->imms[off->Index * TGSI_NUM_CHANNELS + off->SwizzleY], "");
1570 /* fall through */
1571 case TGSI_TEXTURE_1D:
1572 case TGSI_TEXTURE_SHADOW1D:
1573 case TGSI_TEXTURE_1D_ARRAY:
1574 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1575 args.coords[0] =
1576 LLVMBuildAdd(ctx->ac.builder, args.coords[0],
1577 ctx->imms[off->Index * TGSI_NUM_CHANNELS + off->SwizzleX], "");
1578 break;
1579 /* texture offsets do not apply to other texture targets */
1580 }
1581 }
1582 }
1583
1584 if (opcode == TGSI_OPCODE_TG4) {
1585 unsigned gather_comp = 0;
1586
1587 /* DMASK was repurposed for GATHER4. 4 components are always
1588 * returned and DMASK works like a swizzle - it selects
1589 * the component to fetch. The only valid DMASK values are
1590 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
1591 * (red,red,red,red) etc.) The ISA document doesn't mention
1592 * this.
1593 */
1594
1595 /* Get the component index from src1.x for Gather4. */
1596 if (!tgsi_is_shadow_target(target)) {
1597 LLVMValueRef comp_imm;
1598 struct tgsi_src_register src1 = inst->Src[1].Register;
1599
1600 assert(src1.File == TGSI_FILE_IMMEDIATE);
1601
1602 comp_imm = ctx->imms[src1.Index * TGSI_NUM_CHANNELS + src1.SwizzleX];
1603 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
1604 gather_comp = CLAMP(gather_comp, 0, 3);
1605 }
1606
1607 args.dmask = 1 << gather_comp;
1608 } else {
1609 args.dmask = 0xf;
1610 }
1611
1612 args.dim = ac_texture_dim_from_tgsi_target(ctx->screen, target);
1613 args.unorm = target == TGSI_TEXTURE_RECT ||
1614 target == TGSI_TEXTURE_SHADOWRECT;
1615 args.opcode = ac_image_sample;
1616
1617 switch (opcode) {
1618 case TGSI_OPCODE_TXF:
1619 case TGSI_OPCODE_TXF_LZ:
1620 args.opcode = opcode == TGSI_OPCODE_TXF_LZ ||
1621 target == TGSI_TEXTURE_2D_MSAA ||
1622 target == TGSI_TEXTURE_2D_ARRAY_MSAA ?
1623 ac_image_load : ac_image_load_mip;
1624 break;
1625 case TGSI_OPCODE_LODQ:
1626 args.opcode = ac_image_get_lod;
1627 break;
1628 case TGSI_OPCODE_TEX:
1629 case TGSI_OPCODE_TEX2:
1630 case TGSI_OPCODE_TXP:
1631 if (ctx->type != PIPE_SHADER_FRAGMENT)
1632 args.level_zero = true;
1633 break;
1634 case TGSI_OPCODE_TEX_LZ:
1635 args.level_zero = true;
1636 break;
1637 case TGSI_OPCODE_TXB:
1638 case TGSI_OPCODE_TXB2:
1639 assert(ctx->type == PIPE_SHADER_FRAGMENT);
1640 break;
1641 case TGSI_OPCODE_TXL:
1642 case TGSI_OPCODE_TXL2:
1643 break;
1644 case TGSI_OPCODE_TXD:
1645 break;
1646 case TGSI_OPCODE_TG4:
1647 args.opcode = ac_image_gather4;
1648 args.level_zero = true;
1649 break;
1650 default:
1651 assert(0);
1652 return;
1653 }
1654
1655 /* The hardware needs special lowering for Gather4 with integer formats. */
1656 LLVMValueRef gather4_int_result_workaround = NULL;
1657
1658 if (ctx->screen->info.chip_class <= GFX8 &&
1659 opcode == TGSI_OPCODE_TG4) {
1660 assert(inst->Texture.ReturnType != TGSI_RETURN_TYPE_UNKNOWN);
1661
1662 if (inst->Texture.ReturnType == TGSI_RETURN_TYPE_SINT ||
1663 inst->Texture.ReturnType == TGSI_RETURN_TYPE_UINT) {
1664 gather4_int_result_workaround =
1665 si_lower_gather4_integer(ctx, &args, target,
1666 inst->Texture.ReturnType);
1667 }
1668 }
1669
1670 args.attributes = AC_FUNC_ATTR_READNONE;
1671 LLVMValueRef result = ac_build_image_opcode(&ctx->ac, &args);
1672
1673 if (gather4_int_result_workaround) {
1674 result = si_fix_gather4_integer_result(ctx, result,
1675 inst->Texture.ReturnType,
1676 gather4_int_result_workaround);
1677 }
1678
1679 emit_data->output[emit_data->chan] = result;
1680 }
1681
1682 static void si_llvm_emit_txqs(
1683 const struct lp_build_tgsi_action *action,
1684 struct lp_build_tgsi_context *bld_base,
1685 struct lp_build_emit_data *emit_data)
1686 {
1687 struct si_shader_context *ctx = si_shader_context(bld_base);
1688 LLVMValueRef res, samples;
1689 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
1690
1691 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
1692
1693 /* Read the samples from the descriptor directly. */
1694 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->v8i32, "");
1695 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
1696 LLVMConstInt(ctx->i32, 3, 0), "");
1697 samples = LLVMBuildLShr(ctx->ac.builder, samples,
1698 LLVMConstInt(ctx->i32, 16, 0), "");
1699 samples = LLVMBuildAnd(ctx->ac.builder, samples,
1700 LLVMConstInt(ctx->i32, 0xf, 0), "");
1701 samples = LLVMBuildShl(ctx->ac.builder, ctx->i32_1,
1702 samples, "");
1703
1704 emit_data->output[emit_data->chan] = samples;
1705 }
1706
1707 static void si_llvm_emit_fbfetch(const struct lp_build_tgsi_action *action,
1708 struct lp_build_tgsi_context *bld_base,
1709 struct lp_build_emit_data *emit_data)
1710 {
1711 struct si_shader_context *ctx = si_shader_context(bld_base);
1712 struct ac_image_args args = {};
1713 LLVMValueRef ptr, image, fmask;
1714
1715 /* Ignore src0, because KHR_blend_func_extended disallows multiple render
1716 * targets.
1717 */
1718
1719 /* Load the image descriptor. */
1720 STATIC_ASSERT(SI_PS_IMAGE_COLORBUF0 % 2 == 0);
1721 ptr = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
1722 ptr = LLVMBuildPointerCast(ctx->ac.builder, ptr,
1723 ac_array_in_const32_addr_space(ctx->v8i32), "");
1724 image = ac_build_load_to_sgpr(&ctx->ac, ptr,
1725 LLVMConstInt(ctx->i32, SI_PS_IMAGE_COLORBUF0 / 2, 0));
1726
1727 unsigned chan = 0;
1728
1729 args.coords[chan++] = si_unpack_param(ctx, SI_PARAM_POS_FIXED_PT, 0, 16);
1730
1731 if (!ctx->shader->key.mono.u.ps.fbfetch_is_1D)
1732 args.coords[chan++] = si_unpack_param(ctx, SI_PARAM_POS_FIXED_PT, 16, 16);
1733
1734 /* Get the current render target layer index. */
1735 if (ctx->shader->key.mono.u.ps.fbfetch_layered)
1736 args.coords[chan++] = si_unpack_param(ctx, SI_PARAM_ANCILLARY, 16, 11);
1737
1738 if (ctx->shader->key.mono.u.ps.fbfetch_msaa)
1739 args.coords[chan++] = si_get_sample_id(ctx);
1740
1741 if (ctx->shader->key.mono.u.ps.fbfetch_msaa &&
1742 !(ctx->screen->debug_flags & DBG(NO_FMASK))) {
1743 fmask = ac_build_load_to_sgpr(&ctx->ac, ptr,
1744 LLVMConstInt(ctx->i32, SI_PS_IMAGE_COLORBUF0_FMASK / 2, 0));
1745
1746 ac_apply_fmask_to_sample(&ctx->ac, fmask, args.coords,
1747 ctx->shader->key.mono.u.ps.fbfetch_layered);
1748 }
1749
1750 args.opcode = ac_image_load;
1751 args.resource = image;
1752 args.dmask = 0xf;
1753 args.attributes = AC_FUNC_ATTR_READNONE;
1754
1755 if (ctx->shader->key.mono.u.ps.fbfetch_msaa)
1756 args.dim = ctx->shader->key.mono.u.ps.fbfetch_layered ?
1757 ac_image_2darraymsaa : ac_image_2dmsaa;
1758 else if (ctx->shader->key.mono.u.ps.fbfetch_is_1D)
1759 args.dim = ctx->shader->key.mono.u.ps.fbfetch_layered ?
1760 ac_image_1darray : ac_image_1d;
1761 else
1762 args.dim = ctx->shader->key.mono.u.ps.fbfetch_layered ?
1763 ac_image_2darray : ac_image_2d;
1764
1765 emit_data->output[emit_data->chan] =
1766 ac_build_image_opcode(&ctx->ac, &args);
1767 }
1768
1769 /**
1770 * Setup actions for TGSI memory opcode, including texture opcodes.
1771 */
1772 void si_shader_context_init_mem(struct si_shader_context *ctx)
1773 {
1774 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
1775
1776 bld_base->op_actions[TGSI_OPCODE_TEX].emit = build_tex_intrinsic;
1777 bld_base->op_actions[TGSI_OPCODE_TEX_LZ].emit = build_tex_intrinsic;
1778 bld_base->op_actions[TGSI_OPCODE_TEX2].emit = build_tex_intrinsic;
1779 bld_base->op_actions[TGSI_OPCODE_TXB].emit = build_tex_intrinsic;
1780 bld_base->op_actions[TGSI_OPCODE_TXB2].emit = build_tex_intrinsic;
1781 bld_base->op_actions[TGSI_OPCODE_TXD].emit = build_tex_intrinsic;
1782 bld_base->op_actions[TGSI_OPCODE_TXF].emit = build_tex_intrinsic;
1783 bld_base->op_actions[TGSI_OPCODE_TXF_LZ].emit = build_tex_intrinsic;
1784 bld_base->op_actions[TGSI_OPCODE_TXL].emit = build_tex_intrinsic;
1785 bld_base->op_actions[TGSI_OPCODE_TXL2].emit = build_tex_intrinsic;
1786 bld_base->op_actions[TGSI_OPCODE_TXP].emit = build_tex_intrinsic;
1787 bld_base->op_actions[TGSI_OPCODE_TXQ].emit = resq_emit;
1788 bld_base->op_actions[TGSI_OPCODE_TG4].emit = build_tex_intrinsic;
1789 bld_base->op_actions[TGSI_OPCODE_LODQ].emit = build_tex_intrinsic;
1790 bld_base->op_actions[TGSI_OPCODE_TXQS].emit = si_llvm_emit_txqs;
1791
1792 bld_base->op_actions[TGSI_OPCODE_FBFETCH].emit = si_llvm_emit_fbfetch;
1793
1794 bld_base->op_actions[TGSI_OPCODE_LOAD].emit = load_emit;
1795 bld_base->op_actions[TGSI_OPCODE_STORE].emit = store_emit;
1796 bld_base->op_actions[TGSI_OPCODE_RESQ].emit = resq_emit;
1797
1798 bld_base->op_actions[TGSI_OPCODE_ATOMUADD].emit = atomic_emit;
1799 bld_base->op_actions[TGSI_OPCODE_ATOMUADD].intr_name = "add";
1800 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG].emit = atomic_emit;
1801 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG].intr_name = "swap";
1802 bld_base->op_actions[TGSI_OPCODE_ATOMCAS].emit = atomic_emit;
1803 bld_base->op_actions[TGSI_OPCODE_ATOMCAS].intr_name = "cmpswap";
1804 bld_base->op_actions[TGSI_OPCODE_ATOMAND].emit = atomic_emit;
1805 bld_base->op_actions[TGSI_OPCODE_ATOMAND].intr_name = "and";
1806 bld_base->op_actions[TGSI_OPCODE_ATOMOR].emit = atomic_emit;
1807 bld_base->op_actions[TGSI_OPCODE_ATOMOR].intr_name = "or";
1808 bld_base->op_actions[TGSI_OPCODE_ATOMXOR].emit = atomic_emit;
1809 bld_base->op_actions[TGSI_OPCODE_ATOMXOR].intr_name = "xor";
1810 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN].emit = atomic_emit;
1811 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN].intr_name = "umin";
1812 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX].emit = atomic_emit;
1813 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX].intr_name = "umax";
1814 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN].emit = atomic_emit;
1815 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN].intr_name = "smin";
1816 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX].emit = atomic_emit;
1817 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX].intr_name = "smax";
1818 }