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radeonsi: take reference glsl types for compile threads
[mesa.git] / src / gallium / drivers / radeonsi / si_shader_tgsi_mem.c
1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_shader_internal.h"
26 #include "si_pipe.h"
27 #include "sid.h"
28 #include "tgsi/tgsi_build.h"
29 #include "tgsi/tgsi_util.h"
30 #include "ac_llvm_util.h"
31
32 static void tex_fetch_ptrs(struct lp_build_tgsi_context *bld_base,
33 struct lp_build_emit_data *emit_data,
34 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
35 LLVMValueRef *fmask_ptr);
36
37 /**
38 * Given a v8i32 resource descriptor for a buffer, extract the size of the
39 * buffer in number of elements and return it as an i32.
40 */
41 static LLVMValueRef get_buffer_size(
42 struct lp_build_tgsi_context *bld_base,
43 LLVMValueRef descriptor)
44 {
45 struct si_shader_context *ctx = si_shader_context(bld_base);
46 LLVMBuilderRef builder = ctx->ac.builder;
47 LLVMValueRef size =
48 LLVMBuildExtractElement(builder, descriptor,
49 LLVMConstInt(ctx->i32, 2, 0), "");
50
51 if (ctx->screen->info.chip_class == GFX8) {
52 /* On GFX8, the descriptor contains the size in bytes,
53 * but TXQ must return the size in elements.
54 * The stride is always non-zero for resources using TXQ.
55 */
56 LLVMValueRef stride =
57 LLVMBuildExtractElement(builder, descriptor,
58 ctx->i32_1, "");
59 stride = LLVMBuildLShr(builder, stride,
60 LLVMConstInt(ctx->i32, 16, 0), "");
61 stride = LLVMBuildAnd(builder, stride,
62 LLVMConstInt(ctx->i32, 0x3FFF, 0), "");
63
64 size = LLVMBuildUDiv(builder, size, stride, "");
65 }
66
67 return size;
68 }
69
70 static LLVMValueRef
71 shader_buffer_fetch_rsrc(struct si_shader_context *ctx,
72 const struct tgsi_full_src_register *reg,
73 bool ubo)
74 {
75 LLVMValueRef index;
76
77 if (!reg->Register.Indirect) {
78 index = LLVMConstInt(ctx->i32, reg->Register.Index, false);
79 } else {
80 index = si_get_indirect_index(ctx, &reg->Indirect,
81 1, reg->Register.Index);
82 }
83
84 if (ubo)
85 return ctx->abi.load_ubo(&ctx->abi, index);
86 else
87 return ctx->abi.load_ssbo(&ctx->abi, index, false);
88 }
89
90 static enum ac_image_dim
91 ac_texture_dim_from_tgsi_target(struct si_screen *screen, enum tgsi_texture_type target)
92 {
93 switch (target) {
94 case TGSI_TEXTURE_1D:
95 case TGSI_TEXTURE_SHADOW1D:
96 if (screen->info.chip_class == GFX9)
97 return ac_image_2d;
98 return ac_image_1d;
99 case TGSI_TEXTURE_2D:
100 case TGSI_TEXTURE_SHADOW2D:
101 case TGSI_TEXTURE_RECT:
102 case TGSI_TEXTURE_SHADOWRECT:
103 return ac_image_2d;
104 case TGSI_TEXTURE_3D:
105 return ac_image_3d;
106 case TGSI_TEXTURE_CUBE:
107 case TGSI_TEXTURE_SHADOWCUBE:
108 case TGSI_TEXTURE_CUBE_ARRAY:
109 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
110 return ac_image_cube;
111 case TGSI_TEXTURE_1D_ARRAY:
112 case TGSI_TEXTURE_SHADOW1D_ARRAY:
113 if (screen->info.chip_class == GFX9)
114 return ac_image_2darray;
115 return ac_image_1darray;
116 case TGSI_TEXTURE_2D_ARRAY:
117 case TGSI_TEXTURE_SHADOW2D_ARRAY:
118 return ac_image_2darray;
119 case TGSI_TEXTURE_2D_MSAA:
120 return ac_image_2dmsaa;
121 case TGSI_TEXTURE_2D_ARRAY_MSAA:
122 return ac_image_2darraymsaa;
123 default:
124 unreachable("unhandled texture type");
125 }
126 }
127
128 static enum ac_image_dim
129 ac_image_dim_from_tgsi_target(struct si_screen *screen, enum tgsi_texture_type target)
130 {
131 enum ac_image_dim dim = ac_texture_dim_from_tgsi_target(screen, target);
132
133 /* Match the resource type set in the descriptor. */
134 if (dim == ac_image_cube ||
135 (screen->info.chip_class <= GFX8 && dim == ac_image_3d))
136 dim = ac_image_2darray;
137 else if (target == TGSI_TEXTURE_2D && screen->info.chip_class == GFX9) {
138 /* When a single layer of a 3D texture is bound, the shader
139 * will refer to a 2D target, but the descriptor has a 3D type.
140 * Since the HW ignores BASE_ARRAY in this case, we need to
141 * send 3 coordinates. This doesn't hurt when the underlying
142 * texture is non-3D.
143 */
144 dim = ac_image_3d;
145 }
146
147 return dim;
148 }
149
150 /**
151 * Given a 256-bit resource descriptor, force the DCC enable bit to off.
152 *
153 * At least on Tonga, executing image stores on images with DCC enabled and
154 * non-trivial can eventually lead to lockups. This can occur when an
155 * application binds an image as read-only but then uses a shader that writes
156 * to it. The OpenGL spec allows almost arbitrarily bad behavior (including
157 * program termination) in this case, but it doesn't cost much to be a bit
158 * nicer: disabling DCC in the shader still leads to undefined results but
159 * avoids the lockup.
160 */
161 static LLVMValueRef force_dcc_off(struct si_shader_context *ctx,
162 LLVMValueRef rsrc)
163 {
164 if (ctx->screen->info.chip_class <= GFX7) {
165 return rsrc;
166 } else {
167 LLVMValueRef i32_6 = LLVMConstInt(ctx->i32, 6, 0);
168 LLVMValueRef i32_C = LLVMConstInt(ctx->i32, C_008F28_COMPRESSION_EN, 0);
169 LLVMValueRef tmp;
170
171 tmp = LLVMBuildExtractElement(ctx->ac.builder, rsrc, i32_6, "");
172 tmp = LLVMBuildAnd(ctx->ac.builder, tmp, i32_C, "");
173 return LLVMBuildInsertElement(ctx->ac.builder, rsrc, tmp, i32_6, "");
174 }
175 }
176
177 LLVMValueRef si_load_image_desc(struct si_shader_context *ctx,
178 LLVMValueRef list, LLVMValueRef index,
179 enum ac_descriptor_type desc_type,
180 bool uses_store, bool bindless)
181 {
182 LLVMBuilderRef builder = ctx->ac.builder;
183 LLVMValueRef rsrc;
184
185 if (desc_type == AC_DESC_BUFFER) {
186 index = ac_build_imad(&ctx->ac, index, LLVMConstInt(ctx->i32, 2, 0),
187 ctx->i32_1);
188 list = LLVMBuildPointerCast(builder, list,
189 ac_array_in_const32_addr_space(ctx->v4i32), "");
190 } else {
191 assert(desc_type == AC_DESC_IMAGE);
192 }
193
194 if (bindless)
195 rsrc = ac_build_load_to_sgpr_uint_wraparound(&ctx->ac, list, index);
196 else
197 rsrc = ac_build_load_to_sgpr(&ctx->ac, list, index);
198
199 if (desc_type == AC_DESC_IMAGE && uses_store)
200 rsrc = force_dcc_off(ctx, rsrc);
201 return rsrc;
202 }
203
204 /**
205 * Load the resource descriptor for \p image.
206 */
207 static void
208 image_fetch_rsrc(
209 struct lp_build_tgsi_context *bld_base,
210 const struct tgsi_full_src_register *image,
211 bool is_store, unsigned target,
212 LLVMValueRef *rsrc)
213 {
214 struct si_shader_context *ctx = si_shader_context(bld_base);
215 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
216 ctx->param_samplers_and_images);
217 LLVMValueRef index;
218
219 if (!image->Register.Indirect) {
220 index = LLVMConstInt(ctx->i32,
221 si_get_image_slot(image->Register.Index), 0);
222 } else {
223 /* From the GL_ARB_shader_image_load_store extension spec:
224 *
225 * If a shader performs an image load, store, or atomic
226 * operation using an image variable declared as an array,
227 * and if the index used to select an individual element is
228 * negative or greater than or equal to the size of the
229 * array, the results of the operation are undefined but may
230 * not lead to termination.
231 */
232 index = si_get_bounded_indirect_index(ctx, &image->Indirect,
233 image->Register.Index,
234 ctx->num_images);
235 index = LLVMBuildSub(ctx->ac.builder,
236 LLVMConstInt(ctx->i32, SI_NUM_IMAGES - 1, 0),
237 index, "");
238 }
239
240 bool bindless = false;
241
242 if (image->Register.File != TGSI_FILE_IMAGE) {
243 /* Bindless descriptors are accessible from a different pair of
244 * user SGPR indices.
245 */
246 rsrc_ptr = LLVMGetParam(ctx->main_fn,
247 ctx->param_bindless_samplers_and_images);
248 index = lp_build_emit_fetch_src(bld_base, image,
249 TGSI_TYPE_UNSIGNED, 0);
250
251 /* For simplicity, bindless image descriptors use fixed
252 * 16-dword slots for now.
253 */
254 index = LLVMBuildMul(ctx->ac.builder, index,
255 LLVMConstInt(ctx->i32, 2, 0), "");
256 bindless = true;
257 }
258
259 *rsrc = si_load_image_desc(ctx, rsrc_ptr, index,
260 target == TGSI_TEXTURE_BUFFER ? AC_DESC_BUFFER : AC_DESC_IMAGE,
261 is_store, bindless);
262 }
263
264 static void image_fetch_coords(
265 struct lp_build_tgsi_context *bld_base,
266 const struct tgsi_full_instruction *inst,
267 unsigned src, LLVMValueRef desc,
268 LLVMValueRef *coords)
269 {
270 struct si_shader_context *ctx = si_shader_context(bld_base);
271 LLVMBuilderRef builder = ctx->ac.builder;
272 unsigned target = inst->Memory.Texture;
273 unsigned num_coords = tgsi_util_get_texture_coord_dim(target);
274 LLVMValueRef tmp;
275 int chan;
276
277 if (target == TGSI_TEXTURE_2D_MSAA ||
278 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
279 /* Need the sample index as well. */
280 num_coords++;
281 }
282
283 for (chan = 0; chan < num_coords; ++chan) {
284 tmp = lp_build_emit_fetch(bld_base, inst, src, chan);
285 tmp = ac_to_integer(&ctx->ac, tmp);
286 coords[chan] = tmp;
287 }
288
289 if (ctx->screen->info.chip_class == GFX9) {
290 /* 1D textures are allocated and used as 2D on GFX9. */
291 if (target == TGSI_TEXTURE_1D) {
292 coords[1] = ctx->i32_0;
293 } else if (target == TGSI_TEXTURE_1D_ARRAY) {
294 coords[2] = coords[1];
295 coords[1] = ctx->i32_0;
296 } else if (target == TGSI_TEXTURE_2D) {
297 /* The hw can't bind a slice of a 3D image as a 2D
298 * image, because it ignores BASE_ARRAY if the target
299 * is 3D. The workaround is to read BASE_ARRAY and set
300 * it as the 3rd address operand for all 2D images.
301 */
302 LLVMValueRef first_layer, const5, mask;
303
304 const5 = LLVMConstInt(ctx->i32, 5, 0);
305 mask = LLVMConstInt(ctx->i32, S_008F24_BASE_ARRAY(~0), 0);
306 first_layer = LLVMBuildExtractElement(builder, desc, const5, "");
307 first_layer = LLVMBuildAnd(builder, first_layer, mask, "");
308
309 coords[2] = first_layer;
310 }
311 }
312 }
313
314 static unsigned get_cache_policy(struct si_shader_context *ctx,
315 const struct tgsi_full_instruction *inst,
316 bool atomic, bool may_store_unaligned,
317 bool writeonly_memory)
318 {
319 unsigned cache_policy = 0;
320
321 if (!atomic &&
322 /* GFX6 has a TC L1 bug causing corruption of 8bit/16bit stores.
323 * All store opcodes not aligned to a dword are affected.
324 * The only way to get unaligned stores in radeonsi is through
325 * shader images. */
326 ((may_store_unaligned && ctx->screen->info.chip_class == GFX6) ||
327 /* If this is write-only, don't keep data in L1 to prevent
328 * evicting L1 cache lines that may be needed by other
329 * instructions. */
330 writeonly_memory ||
331 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE))) {
332 cache_policy |= ac_glc;
333 }
334
335 if (inst->Memory.Qualifier & TGSI_MEMORY_STREAM_CACHE_POLICY)
336 cache_policy |= ac_slc;
337
338 return cache_policy;
339 }
340
341 static LLVMValueRef get_memory_ptr(struct si_shader_context *ctx,
342 const struct tgsi_full_instruction *inst,
343 LLVMTypeRef type, int arg)
344 {
345 LLVMBuilderRef builder = ctx->ac.builder;
346 LLVMValueRef offset, ptr;
347 int addr_space;
348
349 offset = lp_build_emit_fetch(&ctx->bld_base, inst, arg, 0);
350 offset = ac_to_integer(&ctx->ac, offset);
351
352 ptr = ctx->ac.lds;
353 ptr = LLVMBuildGEP(builder, ptr, &offset, 1, "");
354 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
355 ptr = LLVMBuildBitCast(builder, ptr, LLVMPointerType(type, addr_space), "");
356
357 return ptr;
358 }
359
360 static void load_emit_memory(
361 struct si_shader_context *ctx,
362 struct lp_build_emit_data *emit_data)
363 {
364 const struct tgsi_full_instruction *inst = emit_data->inst;
365 unsigned writemask = inst->Dst[0].Register.WriteMask;
366 LLVMValueRef channels[4], ptr, derived_ptr, index;
367 int chan;
368
369 ptr = get_memory_ptr(ctx, inst, ctx->f32, 1);
370
371 for (chan = 0; chan < 4; ++chan) {
372 if (!(writemask & (1 << chan))) {
373 channels[chan] = LLVMGetUndef(ctx->f32);
374 continue;
375 }
376
377 index = LLVMConstInt(ctx->i32, chan, 0);
378 derived_ptr = LLVMBuildGEP(ctx->ac.builder, ptr, &index, 1, "");
379 channels[chan] = LLVMBuildLoad(ctx->ac.builder, derived_ptr, "");
380 }
381 emit_data->output[emit_data->chan] = ac_build_gather_values(&ctx->ac, channels, 4);
382 }
383
384 /**
385 * Return true if the memory accessed by a LOAD or STORE instruction is
386 * read-only or write-only, respectively.
387 *
388 * \param shader_buffers_reverse_access_mask
389 * For LOAD, set this to (store | atomic) slot usage in the shader.
390 * For STORE, set this to (load | atomic) slot usage in the shader.
391 * \param images_reverse_access_mask Same as above, but for images.
392 * \param bindless_buffer_reverse_access_mask Same as above, but for bindless image buffers.
393 * \param bindless_image_reverse_access_mask Same as above, but for bindless images.
394 */
395 static bool is_oneway_access_only(const struct tgsi_full_instruction *inst,
396 const struct tgsi_shader_info *info,
397 unsigned shader_buffers_reverse_access_mask,
398 unsigned images_reverse_access_mask,
399 bool bindless_buffer_reverse_access_mask,
400 bool bindless_image_reverse_access_mask)
401 {
402 enum tgsi_file_type resource_file;
403 unsigned resource_index;
404 bool resource_indirect;
405
406 if (inst->Instruction.Opcode == TGSI_OPCODE_STORE) {
407 resource_file = inst->Dst[0].Register.File;
408 resource_index = inst->Dst[0].Register.Index;
409 resource_indirect = inst->Dst[0].Register.Indirect;
410 } else {
411 resource_file = inst->Src[0].Register.File;
412 resource_index = inst->Src[0].Register.Index;
413 resource_indirect = inst->Src[0].Register.Indirect;
414 }
415
416 assert(resource_file == TGSI_FILE_BUFFER ||
417 resource_file == TGSI_FILE_IMAGE ||
418 /* bindless image */
419 resource_file == TGSI_FILE_INPUT ||
420 resource_file == TGSI_FILE_OUTPUT ||
421 resource_file == TGSI_FILE_CONSTANT ||
422 resource_file == TGSI_FILE_TEMPORARY ||
423 resource_file == TGSI_FILE_IMMEDIATE);
424
425 assert(resource_file != TGSI_FILE_BUFFER ||
426 inst->Memory.Texture == TGSI_TEXTURE_BUFFER);
427
428 bool bindless = resource_file != TGSI_FILE_BUFFER &&
429 resource_file != TGSI_FILE_IMAGE;
430
431 /* RESTRICT means NOALIAS.
432 * If there are no writes, we can assume the accessed memory is read-only.
433 * If there are no reads, we can assume the accessed memory is write-only.
434 */
435 if (inst->Memory.Qualifier & TGSI_MEMORY_RESTRICT && !bindless) {
436 unsigned reverse_access_mask;
437
438 if (resource_file == TGSI_FILE_BUFFER) {
439 reverse_access_mask = shader_buffers_reverse_access_mask;
440 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
441 reverse_access_mask = info->images_buffers &
442 images_reverse_access_mask;
443 } else {
444 reverse_access_mask = ~info->images_buffers &
445 images_reverse_access_mask;
446 }
447
448 if (resource_indirect) {
449 if (!reverse_access_mask)
450 return true;
451 } else {
452 if (!(reverse_access_mask &
453 (1u << resource_index)))
454 return true;
455 }
456 }
457
458 /* If there are no buffer writes (for both shader buffers & image
459 * buffers), it implies that buffer memory is read-only.
460 * If there are no buffer reads (for both shader buffers & image
461 * buffers), it implies that buffer memory is write-only.
462 *
463 * Same for the case when there are no writes/reads for non-buffer
464 * images.
465 */
466 if (resource_file == TGSI_FILE_BUFFER ||
467 inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
468 if (!shader_buffers_reverse_access_mask &&
469 !(info->images_buffers & images_reverse_access_mask) &&
470 !bindless_buffer_reverse_access_mask)
471 return true;
472 } else {
473 if (!(~info->images_buffers & images_reverse_access_mask) &&
474 !bindless_image_reverse_access_mask)
475 return true;
476 }
477 return false;
478 }
479
480 static void load_emit(
481 const struct lp_build_tgsi_action *action,
482 struct lp_build_tgsi_context *bld_base,
483 struct lp_build_emit_data *emit_data)
484 {
485 struct si_shader_context *ctx = si_shader_context(bld_base);
486 const struct tgsi_full_instruction * inst = emit_data->inst;
487 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
488 bool can_speculate = false;
489 LLVMValueRef vindex = ctx->i32_0;
490 LLVMValueRef voffset = ctx->i32_0;
491 struct ac_image_args args = {};
492
493 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
494 load_emit_memory(ctx, emit_data);
495 return;
496 }
497
498 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
499 inst->Src[0].Register.File == TGSI_FILE_CONSTBUF) {
500 bool ubo = inst->Src[0].Register.File == TGSI_FILE_CONSTBUF;
501 args.resource = shader_buffer_fetch_rsrc(ctx, &inst->Src[0], ubo);
502 voffset = ac_to_integer(&ctx->ac, lp_build_emit_fetch(bld_base, inst, 1, 0));
503 } else {
504 unsigned target = inst->Memory.Texture;
505
506 image_fetch_rsrc(bld_base, &inst->Src[0], false, target, &args.resource);
507 image_fetch_coords(bld_base, inst, 1, args.resource, args.coords);
508 vindex = args.coords[0]; /* for buffers only */
509 }
510
511 if (inst->Src[0].Register.File == TGSI_FILE_CONSTBUF) {
512 emit_data->output[emit_data->chan] =
513 ac_build_buffer_load(&ctx->ac, args.resource,
514 util_last_bit(inst->Dst[0].Register.WriteMask),
515 NULL, voffset, NULL, 0, 0, true, true);
516 return;
517 }
518
519 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
520 ac_build_waitcnt(&ctx->ac, AC_WAIT_VLOAD | AC_WAIT_VSTORE);
521
522 can_speculate = !(inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE) &&
523 is_oneway_access_only(inst, info,
524 info->shader_buffers_store |
525 info->shader_buffers_atomic,
526 info->images_store |
527 info->images_atomic,
528 info->uses_bindless_buffer_store |
529 info->uses_bindless_buffer_atomic,
530 info->uses_bindless_image_store |
531 info->uses_bindless_image_atomic);
532 args.cache_policy = get_cache_policy(ctx, inst, false, false, false);
533
534 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
535 /* Don't use SMEM for shader buffer loads, because LLVM doesn't
536 * select SMEM for SI.load.const with a non-constant offset, and
537 * constant offsets practically don't exist with shader buffers.
538 *
539 * Also, SI.load.const doesn't use inst_offset when it's lowered
540 * to VMEM, so we just end up with more VALU instructions in the end
541 * and no benefit.
542 *
543 * TODO: Remove this line once LLVM can select SMEM with a non-constant
544 * offset, and can derive inst_offset when VMEM is selected.
545 * After that, si_memory_barrier should invalidate sL1 for shader
546 * buffers.
547 */
548 emit_data->output[emit_data->chan] =
549 ac_build_buffer_load(&ctx->ac, args.resource,
550 util_last_bit(inst->Dst[0].Register.WriteMask),
551 NULL, voffset, NULL, 0,
552 args.cache_policy, can_speculate, false);
553 return;
554 }
555
556 if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
557 unsigned num_channels = util_last_bit(inst->Dst[0].Register.WriteMask);
558 LLVMValueRef result =
559 ac_build_buffer_load_format(&ctx->ac,
560 args.resource,
561 vindex,
562 ctx->i32_0,
563 num_channels,
564 args.cache_policy,
565 can_speculate);
566 emit_data->output[emit_data->chan] =
567 ac_build_expand_to_vec4(&ctx->ac, result, num_channels);
568 } else {
569 args.opcode = ac_image_load;
570 args.dim = ac_image_dim_from_tgsi_target(ctx->screen, inst->Memory.Texture);
571 args.attributes = ac_get_load_intr_attribs(can_speculate);
572 args.dmask = 0xf;
573
574 emit_data->output[emit_data->chan] =
575 ac_build_image_opcode(&ctx->ac, &args);
576 }
577 }
578
579 static void store_emit_buffer(struct si_shader_context *ctx,
580 LLVMValueRef resource,
581 unsigned writemask,
582 LLVMValueRef value,
583 LLVMValueRef voffset,
584 unsigned cache_policy,
585 bool writeonly_memory)
586 {
587 LLVMBuilderRef builder = ctx->ac.builder;
588 LLVMValueRef base_data = value;
589 LLVMValueRef base_offset = voffset;
590
591 while (writemask) {
592 int start, count;
593 LLVMValueRef data, voff;
594
595 u_bit_scan_consecutive_range(&writemask, &start, &count);
596
597 if (count == 3 && ac_has_vec3_support(ctx->ac.chip_class, false)) {
598 LLVMValueRef values[3] = {
599 LLVMBuildExtractElement(builder, base_data,
600 LLVMConstInt(ctx->i32, start, 0), ""),
601 LLVMBuildExtractElement(builder, base_data,
602 LLVMConstInt(ctx->i32, start + 1, 0), ""),
603 LLVMBuildExtractElement(builder, base_data,
604 LLVMConstInt(ctx->i32, start + 2, 0), ""),
605 };
606 data = ac_build_gather_values(&ctx->ac, values, 3);
607 } else if (count >= 3) {
608 data = base_data;
609 } else if (count == 2) {
610 LLVMValueRef values[2] = {
611 LLVMBuildExtractElement(builder, base_data,
612 LLVMConstInt(ctx->i32, start, 0), ""),
613 LLVMBuildExtractElement(builder, base_data,
614 LLVMConstInt(ctx->i32, start + 1, 0), ""),
615 };
616
617 data = ac_build_gather_values(&ctx->ac, values, 2);
618 } else {
619 assert(count == 1);
620 data = LLVMBuildExtractElement(
621 builder, base_data,
622 LLVMConstInt(ctx->i32, start, 0), "");
623 }
624
625 voff = base_offset;
626 if (start != 0) {
627 voff = LLVMBuildAdd(
628 builder, voff,
629 LLVMConstInt(ctx->i32, start * 4, 0), "");
630 }
631
632 ac_build_buffer_store_dword(&ctx->ac, resource, data, count,
633 voff, ctx->i32_0, 0, cache_policy,
634 false);
635 }
636 }
637
638 static void store_emit_memory(
639 struct si_shader_context *ctx,
640 struct lp_build_emit_data *emit_data)
641 {
642 const struct tgsi_full_instruction *inst = emit_data->inst;
643 LLVMBuilderRef builder = ctx->ac.builder;
644 unsigned writemask = inst->Dst[0].Register.WriteMask;
645 LLVMValueRef ptr, derived_ptr, data, index;
646 int chan;
647
648 ptr = get_memory_ptr(ctx, inst, ctx->f32, 0);
649
650 for (chan = 0; chan < 4; ++chan) {
651 if (!(writemask & (1 << chan))) {
652 continue;
653 }
654 data = lp_build_emit_fetch(&ctx->bld_base, inst, 1, chan);
655 index = LLVMConstInt(ctx->i32, chan, 0);
656 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
657 LLVMBuildStore(builder, data, derived_ptr);
658 }
659 }
660
661 static void store_emit(
662 const struct lp_build_tgsi_action *action,
663 struct lp_build_tgsi_context *bld_base,
664 struct lp_build_emit_data *emit_data)
665 {
666 struct si_shader_context *ctx = si_shader_context(bld_base);
667 const struct tgsi_full_instruction * inst = emit_data->inst;
668 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
669 struct tgsi_full_src_register resource_reg =
670 tgsi_full_src_register_from_dst(&inst->Dst[0]);
671 unsigned target = inst->Memory.Texture;
672
673 if (inst->Dst[0].Register.File == TGSI_FILE_MEMORY) {
674 store_emit_memory(ctx, emit_data);
675 return;
676 }
677
678 bool writeonly_memory = is_oneway_access_only(inst, info,
679 info->shader_buffers_load |
680 info->shader_buffers_atomic,
681 info->images_load |
682 info->images_atomic,
683 info->uses_bindless_buffer_load |
684 info->uses_bindless_buffer_atomic,
685 info->uses_bindless_image_load |
686 info->uses_bindless_image_atomic);
687 LLVMValueRef chans[4];
688 LLVMValueRef vindex = ctx->i32_0;
689 LLVMValueRef voffset = ctx->i32_0;
690 struct ac_image_args args = {};
691
692 for (unsigned chan = 0; chan < 4; ++chan)
693 chans[chan] = lp_build_emit_fetch(bld_base, inst, 1, chan);
694
695 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
696 args.resource = shader_buffer_fetch_rsrc(ctx, &resource_reg, false);
697 voffset = ac_to_integer(&ctx->ac, lp_build_emit_fetch(bld_base, inst, 0, 0));
698 } else {
699 image_fetch_rsrc(bld_base, &resource_reg, true, target, &args.resource);
700 image_fetch_coords(bld_base, inst, 0, args.resource, args.coords);
701 vindex = args.coords[0]; /* for buffers only */
702 }
703
704 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
705 ac_build_waitcnt(&ctx->ac, AC_WAIT_VLOAD | AC_WAIT_VSTORE);
706
707 bool is_image = inst->Dst[0].Register.File != TGSI_FILE_BUFFER;
708 args.cache_policy = get_cache_policy(ctx, inst,
709 false, /* atomic */
710 is_image, /* may_store_unaligned */
711 writeonly_memory);
712
713 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
714 store_emit_buffer(ctx, args.resource, inst->Dst[0].Register.WriteMask,
715 ac_build_gather_values(&ctx->ac, chans, 4),
716 voffset, args.cache_policy, writeonly_memory);
717 return;
718 }
719
720 if (target == TGSI_TEXTURE_BUFFER) {
721 unsigned num_channels = util_last_bit(inst->Dst[0].Register.WriteMask);
722
723 ac_build_buffer_store_format(&ctx->ac, args.resource,
724 ac_build_gather_values(&ctx->ac, chans, num_channels),
725 vindex, ctx->i32_0 /* voffset */,
726 num_channels,
727 args.cache_policy);
728 } else {
729 args.opcode = ac_image_store;
730 args.data[0] = ac_build_gather_values(&ctx->ac, chans, 4);
731 args.dim = ac_image_dim_from_tgsi_target(ctx->screen, inst->Memory.Texture);
732 args.attributes = AC_FUNC_ATTR_INACCESSIBLE_MEM_ONLY;
733 args.dmask = 0xf;
734
735 emit_data->output[emit_data->chan] =
736 ac_build_image_opcode(&ctx->ac, &args);
737 }
738 }
739
740 static void atomic_emit_memory(struct si_shader_context *ctx,
741 struct lp_build_emit_data *emit_data) {
742 LLVMBuilderRef builder = ctx->ac.builder;
743 const struct tgsi_full_instruction * inst = emit_data->inst;
744 LLVMValueRef ptr, result, arg;
745 const char *sync_scope = HAVE_LLVM >= 0x0900 ? "workgroup-one-as" : "workgroup";
746
747 ptr = get_memory_ptr(ctx, inst, ctx->i32, 1);
748
749 arg = lp_build_emit_fetch(&ctx->bld_base, inst, 2, 0);
750 arg = ac_to_integer(&ctx->ac, arg);
751
752 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
753 LLVMValueRef new_data;
754 new_data = lp_build_emit_fetch(&ctx->bld_base,
755 inst, 3, 0);
756
757 new_data = ac_to_integer(&ctx->ac, new_data);
758
759 result = ac_build_atomic_cmp_xchg(&ctx->ac, ptr, arg, new_data,
760 sync_scope);
761 result = LLVMBuildExtractValue(builder, result, 0, "");
762 } else {
763 LLVMAtomicRMWBinOp op;
764
765 switch(inst->Instruction.Opcode) {
766 case TGSI_OPCODE_ATOMUADD:
767 op = LLVMAtomicRMWBinOpAdd;
768 break;
769 case TGSI_OPCODE_ATOMXCHG:
770 op = LLVMAtomicRMWBinOpXchg;
771 break;
772 case TGSI_OPCODE_ATOMAND:
773 op = LLVMAtomicRMWBinOpAnd;
774 break;
775 case TGSI_OPCODE_ATOMOR:
776 op = LLVMAtomicRMWBinOpOr;
777 break;
778 case TGSI_OPCODE_ATOMXOR:
779 op = LLVMAtomicRMWBinOpXor;
780 break;
781 case TGSI_OPCODE_ATOMUMIN:
782 op = LLVMAtomicRMWBinOpUMin;
783 break;
784 case TGSI_OPCODE_ATOMUMAX:
785 op = LLVMAtomicRMWBinOpUMax;
786 break;
787 case TGSI_OPCODE_ATOMIMIN:
788 op = LLVMAtomicRMWBinOpMin;
789 break;
790 case TGSI_OPCODE_ATOMIMAX:
791 op = LLVMAtomicRMWBinOpMax;
792 break;
793 default:
794 unreachable("unknown atomic opcode");
795 }
796
797 result = ac_build_atomic_rmw(&ctx->ac, op, ptr, arg, sync_scope);
798 }
799 emit_data->output[emit_data->chan] =
800 LLVMBuildBitCast(builder, result, ctx->f32, "");
801 }
802
803 static void atomic_emit(
804 const struct lp_build_tgsi_action *action,
805 struct lp_build_tgsi_context *bld_base,
806 struct lp_build_emit_data *emit_data)
807 {
808 struct si_shader_context *ctx = si_shader_context(bld_base);
809 const struct tgsi_full_instruction * inst = emit_data->inst;
810 struct ac_image_args args = {};
811 unsigned num_data = 0;
812 LLVMValueRef vindex = ctx->i32_0;
813 LLVMValueRef voffset = ctx->i32_0;
814
815 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
816 atomic_emit_memory(ctx, emit_data);
817 return;
818 }
819
820 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
821 /* llvm.amdgcn.image/buffer.atomic.cmpswap reflect the hardware order
822 * of arguments, which is reversed relative to TGSI (and GLSL)
823 */
824 args.data[num_data++] =
825 ac_to_integer(&ctx->ac, lp_build_emit_fetch(bld_base, inst, 3, 0));
826 }
827
828 args.data[num_data++] =
829 ac_to_integer(&ctx->ac, lp_build_emit_fetch(bld_base, inst, 2, 0));
830
831 args.cache_policy = get_cache_policy(ctx, inst, true, false, false);
832
833 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
834 args.resource = shader_buffer_fetch_rsrc(ctx, &inst->Src[0], false);
835 voffset = ac_to_integer(&ctx->ac, lp_build_emit_fetch(bld_base, inst, 1, 0));
836 } else {
837 image_fetch_rsrc(bld_base, &inst->Src[0], true,
838 inst->Memory.Texture, &args.resource);
839 image_fetch_coords(bld_base, inst, 1, args.resource, args.coords);
840 vindex = args.coords[0]; /* for buffers only */
841 }
842
843 if (HAVE_LLVM >= 0x0800 &&
844 inst->Src[0].Register.File != TGSI_FILE_BUFFER &&
845 inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
846 LLVMValueRef buf_args[7];
847 unsigned num_args = 0;
848
849 buf_args[num_args++] = args.data[0];
850 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
851 buf_args[num_args++] = args.data[1];
852
853 buf_args[num_args++] = args.resource;
854 buf_args[num_args++] = vindex;
855 buf_args[num_args++] = voffset;
856 buf_args[num_args++] = ctx->i32_0; /* soffset */
857 buf_args[num_args++] = LLVMConstInt(ctx->i32, args.cache_policy & ac_slc, 0);
858
859 char intrinsic_name[64];
860 snprintf(intrinsic_name, sizeof(intrinsic_name),
861 "llvm.amdgcn.struct.buffer.atomic.%s", action->intr_name);
862 emit_data->output[emit_data->chan] =
863 ac_to_float(&ctx->ac,
864 ac_build_intrinsic(&ctx->ac, intrinsic_name,
865 ctx->i32, buf_args, num_args, 0));
866 return;
867 }
868
869 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
870 (HAVE_LLVM < 0x0800 &&
871 inst->Memory.Texture == TGSI_TEXTURE_BUFFER)) {
872 LLVMValueRef buf_args[7];
873 unsigned num_args = 0;
874
875 buf_args[num_args++] = args.data[0];
876 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
877 buf_args[num_args++] = args.data[1];
878
879 buf_args[num_args++] = args.resource;
880 buf_args[num_args++] = vindex;
881 buf_args[num_args++] = voffset;
882 buf_args[num_args++] = args.cache_policy & ac_slc ? ctx->i1true : ctx->i1false;
883
884 char intrinsic_name[40];
885 snprintf(intrinsic_name, sizeof(intrinsic_name),
886 "llvm.amdgcn.buffer.atomic.%s", action->intr_name);
887 emit_data->output[emit_data->chan] =
888 ac_to_float(&ctx->ac,
889 ac_build_intrinsic(&ctx->ac, intrinsic_name,
890 ctx->i32, buf_args, num_args, 0));
891 } else {
892 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
893 args.opcode = ac_image_atomic_cmpswap;
894 } else {
895 args.opcode = ac_image_atomic;
896 switch (inst->Instruction.Opcode) {
897 case TGSI_OPCODE_ATOMXCHG: args.atomic = ac_atomic_swap; break;
898 case TGSI_OPCODE_ATOMUADD: args.atomic = ac_atomic_add; break;
899 case TGSI_OPCODE_ATOMAND: args.atomic = ac_atomic_and; break;
900 case TGSI_OPCODE_ATOMOR: args.atomic = ac_atomic_or; break;
901 case TGSI_OPCODE_ATOMXOR: args.atomic = ac_atomic_xor; break;
902 case TGSI_OPCODE_ATOMUMIN: args.atomic = ac_atomic_umin; break;
903 case TGSI_OPCODE_ATOMUMAX: args.atomic = ac_atomic_umax; break;
904 case TGSI_OPCODE_ATOMIMIN: args.atomic = ac_atomic_smin; break;
905 case TGSI_OPCODE_ATOMIMAX: args.atomic = ac_atomic_smax; break;
906 case TGSI_OPCODE_ATOMINC_WRAP:
907 args.atomic = ac_atomic_inc_wrap;
908 break;
909 case TGSI_OPCODE_ATOMDEC_WRAP:
910 args.atomic = ac_atomic_dec_wrap;
911 break;
912 default: unreachable("unhandled image atomic");
913 }
914 }
915
916 args.dim = ac_image_dim_from_tgsi_target(ctx->screen, inst->Memory.Texture);
917 emit_data->output[emit_data->chan] =
918 ac_to_float(&ctx->ac, ac_build_image_opcode(&ctx->ac, &args));
919 }
920 }
921
922 static LLVMValueRef fix_resinfo(struct si_shader_context *ctx,
923 unsigned target, LLVMValueRef out)
924 {
925 LLVMBuilderRef builder = ctx->ac.builder;
926
927 /* 1D textures are allocated and used as 2D on GFX9. */
928 if (ctx->screen->info.chip_class == GFX9 &&
929 (target == TGSI_TEXTURE_1D_ARRAY ||
930 target == TGSI_TEXTURE_SHADOW1D_ARRAY)) {
931 LLVMValueRef layers =
932 LLVMBuildExtractElement(builder, out,
933 LLVMConstInt(ctx->i32, 2, 0), "");
934 out = LLVMBuildInsertElement(builder, out, layers,
935 ctx->i32_1, "");
936 }
937
938 /* Divide the number of layers by 6 to get the number of cubes. */
939 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
940 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
941 LLVMValueRef imm2 = LLVMConstInt(ctx->i32, 2, 0);
942
943 LLVMValueRef z = LLVMBuildExtractElement(builder, out, imm2, "");
944 z = LLVMBuildSDiv(builder, z, LLVMConstInt(ctx->i32, 6, 0), "");
945
946 out = LLVMBuildInsertElement(builder, out, z, imm2, "");
947 }
948 return out;
949 }
950
951 static void resq_emit(
952 const struct lp_build_tgsi_action *action,
953 struct lp_build_tgsi_context *bld_base,
954 struct lp_build_emit_data *emit_data)
955 {
956 struct si_shader_context *ctx = si_shader_context(bld_base);
957 LLVMBuilderRef builder = ctx->ac.builder;
958 const struct tgsi_full_instruction *inst = emit_data->inst;
959 const struct tgsi_full_src_register *reg =
960 &inst->Src[inst->Instruction.Opcode == TGSI_OPCODE_TXQ ? 1 : 0];
961
962 if (reg->Register.File == TGSI_FILE_BUFFER) {
963 LLVMValueRef rsrc = shader_buffer_fetch_rsrc(ctx, reg, false);
964
965 emit_data->output[emit_data->chan] =
966 LLVMBuildExtractElement(builder, rsrc,
967 LLVMConstInt(ctx->i32, 2, 0), "");
968 return;
969 }
970
971 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ &&
972 inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
973 LLVMValueRef rsrc;
974
975 tex_fetch_ptrs(bld_base, emit_data, &rsrc, NULL, NULL);
976 /* Read the size from the buffer descriptor directly. */
977 emit_data->output[emit_data->chan] =
978 get_buffer_size(bld_base, rsrc);
979 return;
980 }
981
982 if (inst->Instruction.Opcode == TGSI_OPCODE_RESQ &&
983 inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
984 LLVMValueRef rsrc;
985
986 image_fetch_rsrc(bld_base, reg, false, inst->Memory.Texture, &rsrc);
987 emit_data->output[emit_data->chan] =
988 get_buffer_size(bld_base, rsrc);
989 return;
990 }
991
992 unsigned target;
993
994 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ) {
995 target = inst->Texture.Texture;
996 } else {
997 if (inst->Memory.Texture == TGSI_TEXTURE_3D)
998 target = TGSI_TEXTURE_2D_ARRAY;
999 else
1000 target = inst->Memory.Texture;
1001 }
1002
1003 struct ac_image_args args = {};
1004 args.opcode = ac_image_get_resinfo;
1005 args.dim = ac_texture_dim_from_tgsi_target(ctx->screen, target);
1006 args.dmask = 0xf;
1007 args.attributes = AC_FUNC_ATTR_READNONE;
1008
1009 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ) {
1010 tex_fetch_ptrs(bld_base, emit_data, &args.resource, NULL, NULL);
1011 args.lod = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
1012 } else {
1013 image_fetch_rsrc(bld_base, reg, false, target, &args.resource);
1014 args.lod = ctx->i32_0;
1015 }
1016
1017 emit_data->output[emit_data->chan] =
1018 fix_resinfo(ctx, target, ac_build_image_opcode(&ctx->ac, &args));
1019 }
1020
1021 /**
1022 * Load an image view, fmask view. or sampler state descriptor.
1023 */
1024 LLVMValueRef si_load_sampler_desc(struct si_shader_context *ctx,
1025 LLVMValueRef list, LLVMValueRef index,
1026 enum ac_descriptor_type type)
1027 {
1028 LLVMBuilderRef builder = ctx->ac.builder;
1029
1030 switch (type) {
1031 case AC_DESC_IMAGE:
1032 /* The image is at [0:7]. */
1033 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
1034 break;
1035 case AC_DESC_BUFFER:
1036 /* The buffer is in [4:7]. */
1037 index = ac_build_imad(&ctx->ac, index, LLVMConstInt(ctx->i32, 4, 0),
1038 ctx->i32_1);
1039 list = LLVMBuildPointerCast(builder, list,
1040 ac_array_in_const32_addr_space(ctx->v4i32), "");
1041 break;
1042 case AC_DESC_FMASK:
1043 /* The FMASK is at [8:15]. */
1044 index = ac_build_imad(&ctx->ac, index, LLVMConstInt(ctx->i32, 2, 0),
1045 ctx->i32_1);
1046 break;
1047 case AC_DESC_SAMPLER:
1048 /* The sampler state is at [12:15]. */
1049 index = ac_build_imad(&ctx->ac, index, LLVMConstInt(ctx->i32, 4, 0),
1050 LLVMConstInt(ctx->i32, 3, 0));
1051 list = LLVMBuildPointerCast(builder, list,
1052 ac_array_in_const32_addr_space(ctx->v4i32), "");
1053 break;
1054 case AC_DESC_PLANE_0:
1055 case AC_DESC_PLANE_1:
1056 case AC_DESC_PLANE_2:
1057 /* Only used for the multiplane image support for Vulkan. Should
1058 * never be reached in radeonsi.
1059 */
1060 unreachable("Plane descriptor requested in radeonsi.");
1061 }
1062
1063 return ac_build_load_to_sgpr(&ctx->ac, list, index);
1064 }
1065
1066 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
1067 *
1068 * GFX6-GFX7:
1069 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
1070 * filtering manually. The driver sets img7 to a mask clearing
1071 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
1072 * s_and_b32 samp0, samp0, img7
1073 *
1074 * GFX8:
1075 * The ANISO_OVERRIDE sampler field enables this fix in TA.
1076 */
1077 static LLVMValueRef sici_fix_sampler_aniso(struct si_shader_context *ctx,
1078 LLVMValueRef res, LLVMValueRef samp)
1079 {
1080 LLVMValueRef img7, samp0;
1081
1082 if (ctx->screen->info.chip_class >= GFX8)
1083 return samp;
1084
1085 img7 = LLVMBuildExtractElement(ctx->ac.builder, res,
1086 LLVMConstInt(ctx->i32, 7, 0), "");
1087 samp0 = LLVMBuildExtractElement(ctx->ac.builder, samp,
1088 ctx->i32_0, "");
1089 samp0 = LLVMBuildAnd(ctx->ac.builder, samp0, img7, "");
1090 return LLVMBuildInsertElement(ctx->ac.builder, samp, samp0,
1091 ctx->i32_0, "");
1092 }
1093
1094 static void tex_fetch_ptrs(struct lp_build_tgsi_context *bld_base,
1095 struct lp_build_emit_data *emit_data,
1096 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
1097 LLVMValueRef *fmask_ptr)
1098 {
1099 struct si_shader_context *ctx = si_shader_context(bld_base);
1100 LLVMValueRef list = LLVMGetParam(ctx->main_fn, ctx->param_samplers_and_images);
1101 const struct tgsi_full_instruction *inst = emit_data->inst;
1102 const struct tgsi_full_src_register *reg;
1103 unsigned target = inst->Texture.Texture;
1104 unsigned sampler_src;
1105 LLVMValueRef index;
1106
1107 sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
1108 reg = &emit_data->inst->Src[sampler_src];
1109
1110 if (reg->Register.Indirect) {
1111 index = si_get_bounded_indirect_index(ctx,
1112 &reg->Indirect,
1113 reg->Register.Index,
1114 ctx->num_samplers);
1115 index = LLVMBuildAdd(ctx->ac.builder, index,
1116 LLVMConstInt(ctx->i32, SI_NUM_IMAGES / 2, 0), "");
1117 } else {
1118 index = LLVMConstInt(ctx->i32,
1119 si_get_sampler_slot(reg->Register.Index), 0);
1120 }
1121
1122 if (reg->Register.File != TGSI_FILE_SAMPLER) {
1123 /* Bindless descriptors are accessible from a different pair of
1124 * user SGPR indices.
1125 */
1126 list = LLVMGetParam(ctx->main_fn,
1127 ctx->param_bindless_samplers_and_images);
1128 index = lp_build_emit_fetch_src(bld_base, reg,
1129 TGSI_TYPE_UNSIGNED, 0);
1130
1131 /* Since bindless handle arithmetic can contain an unsigned integer
1132 * wraparound and si_load_sampler_desc assumes there isn't any,
1133 * use GEP without "inbounds" (inside ac_build_pointer_add)
1134 * to prevent incorrect code generation and hangs.
1135 */
1136 index = LLVMBuildMul(ctx->ac.builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
1137 list = ac_build_pointer_add(&ctx->ac, list, index);
1138 index = ctx->i32_0;
1139 }
1140
1141 if (target == TGSI_TEXTURE_BUFFER)
1142 *res_ptr = si_load_sampler_desc(ctx, list, index, AC_DESC_BUFFER);
1143 else
1144 *res_ptr = si_load_sampler_desc(ctx, list, index, AC_DESC_IMAGE);
1145
1146 if (samp_ptr)
1147 *samp_ptr = NULL;
1148 if (fmask_ptr)
1149 *fmask_ptr = NULL;
1150
1151 if (target == TGSI_TEXTURE_2D_MSAA ||
1152 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
1153 if (fmask_ptr)
1154 *fmask_ptr = si_load_sampler_desc(ctx, list, index,
1155 AC_DESC_FMASK);
1156 } else if (target != TGSI_TEXTURE_BUFFER) {
1157 if (samp_ptr) {
1158 *samp_ptr = si_load_sampler_desc(ctx, list, index,
1159 AC_DESC_SAMPLER);
1160 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
1161 }
1162 }
1163 }
1164
1165 /* Gather4 should follow the same rules as bilinear filtering, but the hardware
1166 * incorrectly forces nearest filtering if the texture format is integer.
1167 * The only effect it has on Gather4, which always returns 4 texels for
1168 * bilinear filtering, is that the final coordinates are off by 0.5 of
1169 * the texel size.
1170 *
1171 * The workaround is to subtract 0.5 from the unnormalized coordinates,
1172 * or (0.5 / size) from the normalized coordinates.
1173 *
1174 * However, cube textures with 8_8_8_8 data formats require a different
1175 * workaround of overriding the num format to USCALED/SSCALED. This would lose
1176 * precision in 32-bit data formats, so it needs to be applied dynamically at
1177 * runtime. In this case, return an i1 value that indicates whether the
1178 * descriptor was overridden (and hence a fixup of the sampler result is needed).
1179 */
1180 static LLVMValueRef
1181 si_lower_gather4_integer(struct si_shader_context *ctx,
1182 struct ac_image_args *args,
1183 unsigned target,
1184 enum tgsi_return_type return_type)
1185 {
1186 LLVMBuilderRef builder = ctx->ac.builder;
1187 LLVMValueRef wa_8888 = NULL;
1188 LLVMValueRef half_texel[2];
1189
1190 assert(return_type == TGSI_RETURN_TYPE_SINT ||
1191 return_type == TGSI_RETURN_TYPE_UINT);
1192
1193 if (target == TGSI_TEXTURE_CUBE ||
1194 target == TGSI_TEXTURE_CUBE_ARRAY) {
1195 LLVMValueRef formats;
1196 LLVMValueRef data_format;
1197 LLVMValueRef wa_formats;
1198
1199 formats = LLVMBuildExtractElement(builder, args->resource, ctx->i32_1, "");
1200
1201 data_format = LLVMBuildLShr(builder, formats,
1202 LLVMConstInt(ctx->i32, 20, false), "");
1203 data_format = LLVMBuildAnd(builder, data_format,
1204 LLVMConstInt(ctx->i32, (1u << 6) - 1, false), "");
1205 wa_8888 = LLVMBuildICmp(
1206 builder, LLVMIntEQ, data_format,
1207 LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false),
1208 "");
1209
1210 uint32_t wa_num_format =
1211 return_type == TGSI_RETURN_TYPE_UINT ?
1212 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_USCALED) :
1213 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_SSCALED);
1214 wa_formats = LLVMBuildAnd(builder, formats,
1215 LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT, false),
1216 "");
1217 wa_formats = LLVMBuildOr(builder, wa_formats,
1218 LLVMConstInt(ctx->i32, wa_num_format, false), "");
1219
1220 formats = LLVMBuildSelect(builder, wa_8888, wa_formats, formats, "");
1221 args->resource = LLVMBuildInsertElement(
1222 builder, args->resource, formats, ctx->i32_1, "");
1223 }
1224
1225 if (target == TGSI_TEXTURE_RECT ||
1226 target == TGSI_TEXTURE_SHADOWRECT) {
1227 assert(!wa_8888);
1228 half_texel[0] = half_texel[1] = LLVMConstReal(ctx->f32, -0.5);
1229 } else {
1230 struct ac_image_args resinfo = {};
1231 struct lp_build_if_state if_ctx;
1232
1233 if (wa_8888) {
1234 /* Skip the texture size query entirely if we don't need it. */
1235 lp_build_if(&if_ctx, &ctx->gallivm, LLVMBuildNot(builder, wa_8888, ""));
1236 }
1237
1238 /* Query the texture size. */
1239 resinfo.opcode = ac_image_get_resinfo;
1240 resinfo.dim = ac_texture_dim_from_tgsi_target(ctx->screen, target);
1241 resinfo.resource = args->resource;
1242 resinfo.sampler = args->sampler;
1243 resinfo.lod = ctx->ac.i32_0;
1244 resinfo.dmask = 0xf;
1245 resinfo.attributes = AC_FUNC_ATTR_READNONE;
1246
1247 LLVMValueRef texsize =
1248 fix_resinfo(ctx, target,
1249 ac_build_image_opcode(&ctx->ac, &resinfo));
1250
1251 /* Compute -0.5 / size. */
1252 for (unsigned c = 0; c < 2; c++) {
1253 half_texel[c] =
1254 LLVMBuildExtractElement(builder, texsize,
1255 LLVMConstInt(ctx->i32, c, 0), "");
1256 half_texel[c] = LLVMBuildUIToFP(builder, half_texel[c], ctx->f32, "");
1257 half_texel[c] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, half_texel[c]);
1258 half_texel[c] = LLVMBuildFMul(builder, half_texel[c],
1259 LLVMConstReal(ctx->f32, -0.5), "");
1260 }
1261
1262 if (wa_8888) {
1263 lp_build_endif(&if_ctx);
1264
1265 LLVMBasicBlockRef bb[2] = { if_ctx.true_block, if_ctx.entry_block };
1266
1267 for (unsigned c = 0; c < 2; c++) {
1268 LLVMValueRef values[2] = { half_texel[c], ctx->ac.f32_0 };
1269 half_texel[c] = ac_build_phi(&ctx->ac, ctx->f32, 2,
1270 values, bb);
1271 }
1272 }
1273 }
1274
1275 for (unsigned c = 0; c < 2; c++) {
1276 LLVMValueRef tmp;
1277 tmp = ac_to_float(&ctx->ac, args->coords[c]);
1278 tmp = LLVMBuildFAdd(builder, tmp, half_texel[c], "");
1279 args->coords[c] = ac_to_integer(&ctx->ac, tmp);
1280 }
1281
1282 return wa_8888;
1283 }
1284
1285 /* The second half of the cube texture 8_8_8_8 integer workaround: adjust the
1286 * result after the gather operation.
1287 */
1288 static LLVMValueRef
1289 si_fix_gather4_integer_result(struct si_shader_context *ctx,
1290 LLVMValueRef result,
1291 enum tgsi_return_type return_type,
1292 LLVMValueRef wa)
1293 {
1294 LLVMBuilderRef builder = ctx->ac.builder;
1295
1296 assert(return_type == TGSI_RETURN_TYPE_SINT ||
1297 return_type == TGSI_RETURN_TYPE_UINT);
1298
1299 for (unsigned chan = 0; chan < 4; ++chan) {
1300 LLVMValueRef chanv = LLVMConstInt(ctx->i32, chan, false);
1301 LLVMValueRef value;
1302 LLVMValueRef wa_value;
1303
1304 value = LLVMBuildExtractElement(builder, result, chanv, "");
1305
1306 if (return_type == TGSI_RETURN_TYPE_UINT)
1307 wa_value = LLVMBuildFPToUI(builder, value, ctx->i32, "");
1308 else
1309 wa_value = LLVMBuildFPToSI(builder, value, ctx->i32, "");
1310 wa_value = ac_to_float(&ctx->ac, wa_value);
1311 value = LLVMBuildSelect(builder, wa, wa_value, value, "");
1312
1313 result = LLVMBuildInsertElement(builder, result, value, chanv, "");
1314 }
1315
1316 return result;
1317 }
1318
1319 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
1320 struct lp_build_tgsi_context *bld_base,
1321 struct lp_build_emit_data *emit_data)
1322 {
1323 struct si_shader_context *ctx = si_shader_context(bld_base);
1324 const struct tgsi_full_instruction *inst = emit_data->inst;
1325 unsigned opcode = inst->Instruction.Opcode;
1326 unsigned target = inst->Texture.Texture;
1327 struct ac_image_args args = {};
1328 int ref_pos = tgsi_util_get_shadow_ref_src_index(target);
1329 unsigned chan;
1330 bool has_offset = inst->Texture.NumOffsets > 0;
1331 LLVMValueRef fmask_ptr = NULL;
1332
1333 tex_fetch_ptrs(bld_base, emit_data, &args.resource, &args.sampler, &fmask_ptr);
1334
1335 if (target == TGSI_TEXTURE_BUFFER) {
1336 LLVMValueRef vindex = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
1337 unsigned num_channels =
1338 util_last_bit(inst->Dst[0].Register.WriteMask);
1339 LLVMValueRef result =
1340 ac_build_buffer_load_format(&ctx->ac,
1341 args.resource,
1342 vindex,
1343 ctx->i32_0,
1344 num_channels, 0, true);
1345 emit_data->output[emit_data->chan] =
1346 ac_build_expand_to_vec4(&ctx->ac, result, num_channels);
1347 return;
1348 }
1349
1350 /* Fetch and project texture coordinates */
1351 args.coords[3] = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_W);
1352 for (chan = 0; chan < 3; chan++) {
1353 args.coords[chan] = lp_build_emit_fetch(bld_base, inst, 0, chan);
1354 if (opcode == TGSI_OPCODE_TXP)
1355 args.coords[chan] = ac_build_fdiv(&ctx->ac,
1356 args.coords[chan], args.coords[3]);
1357 }
1358
1359 if (opcode == TGSI_OPCODE_TXP)
1360 args.coords[3] = ctx->ac.f32_1;
1361
1362 /* Pack offsets. */
1363 if (has_offset &&
1364 opcode != TGSI_OPCODE_TXF &&
1365 opcode != TGSI_OPCODE_TXF_LZ) {
1366 /* The offsets are six-bit signed integers packed like this:
1367 * X=[5:0], Y=[13:8], and Z=[21:16].
1368 */
1369 LLVMValueRef offset[3], pack;
1370
1371 assert(inst->Texture.NumOffsets == 1);
1372
1373 for (chan = 0; chan < 3; chan++) {
1374 offset[chan] = lp_build_emit_fetch_texoffset(bld_base, inst, 0, chan);
1375 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
1376 LLVMConstInt(ctx->i32, 0x3f, 0), "");
1377 if (chan)
1378 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
1379 LLVMConstInt(ctx->i32, chan*8, 0), "");
1380 }
1381
1382 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
1383 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
1384 args.offset = pack;
1385 }
1386
1387 /* Pack LOD bias value */
1388 if (opcode == TGSI_OPCODE_TXB)
1389 args.bias = args.coords[3];
1390 if (opcode == TGSI_OPCODE_TXB2)
1391 args.bias = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
1392
1393 /* Pack depth comparison value */
1394 if (tgsi_is_shadow_target(target) && opcode != TGSI_OPCODE_LODQ) {
1395 LLVMValueRef z;
1396
1397 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
1398 z = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
1399 } else {
1400 assert(ref_pos >= 0);
1401 z = args.coords[ref_pos];
1402 }
1403
1404 /* Section 8.23.1 (Depth Texture Comparison Mode) of the
1405 * OpenGL 4.5 spec says:
1406 *
1407 * "If the texture’s internal format indicates a fixed-point
1408 * depth texture, then D_t and D_ref are clamped to the
1409 * range [0, 1]; otherwise no clamping is performed."
1410 *
1411 * TC-compatible HTILE promotes Z16 and Z24 to Z32_FLOAT,
1412 * so the depth comparison value isn't clamped for Z16 and
1413 * Z24 anymore. Do it manually here for GFX8-9; GFX10 has
1414 * an explicitly clamped 32-bit float format.
1415 */
1416 if (ctx->screen->info.chip_class >= GFX8 &&
1417 ctx->screen->info.chip_class <= GFX9) {
1418 LLVMValueRef upgraded;
1419 LLVMValueRef clamped;
1420 upgraded = LLVMBuildExtractElement(ctx->ac.builder, args.sampler,
1421 LLVMConstInt(ctx->i32, 3, false), "");
1422 upgraded = LLVMBuildLShr(ctx->ac.builder, upgraded,
1423 LLVMConstInt(ctx->i32, 29, false), "");
1424 upgraded = LLVMBuildTrunc(ctx->ac.builder, upgraded, ctx->i1, "");
1425 clamped = ac_build_clamp(&ctx->ac, z);
1426 z = LLVMBuildSelect(ctx->ac.builder, upgraded, clamped, z, "");
1427 }
1428
1429 args.compare = z;
1430 }
1431
1432 /* Pack user derivatives */
1433 if (opcode == TGSI_OPCODE_TXD) {
1434 int param, num_src_deriv_channels, num_dst_deriv_channels;
1435
1436 switch (target) {
1437 case TGSI_TEXTURE_3D:
1438 num_src_deriv_channels = 3;
1439 num_dst_deriv_channels = 3;
1440 break;
1441 case TGSI_TEXTURE_2D:
1442 case TGSI_TEXTURE_SHADOW2D:
1443 case TGSI_TEXTURE_RECT:
1444 case TGSI_TEXTURE_SHADOWRECT:
1445 case TGSI_TEXTURE_2D_ARRAY:
1446 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1447 num_src_deriv_channels = 2;
1448 num_dst_deriv_channels = 2;
1449 break;
1450 case TGSI_TEXTURE_CUBE:
1451 case TGSI_TEXTURE_SHADOWCUBE:
1452 case TGSI_TEXTURE_CUBE_ARRAY:
1453 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
1454 /* Cube derivatives will be converted to 2D. */
1455 num_src_deriv_channels = 3;
1456 num_dst_deriv_channels = 3;
1457 break;
1458 case TGSI_TEXTURE_1D:
1459 case TGSI_TEXTURE_SHADOW1D:
1460 case TGSI_TEXTURE_1D_ARRAY:
1461 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1462 num_src_deriv_channels = 1;
1463
1464 /* 1D textures are allocated and used as 2D on GFX9. */
1465 if (ctx->screen->info.chip_class == GFX9) {
1466 num_dst_deriv_channels = 2;
1467 } else {
1468 num_dst_deriv_channels = 1;
1469 }
1470 break;
1471 default:
1472 unreachable("invalid target");
1473 }
1474
1475 for (param = 0; param < 2; param++) {
1476 for (chan = 0; chan < num_src_deriv_channels; chan++)
1477 args.derivs[param * num_dst_deriv_channels + chan] =
1478 lp_build_emit_fetch(bld_base, inst, param+1, chan);
1479
1480 /* Fill in the rest with zeros. */
1481 for (chan = num_src_deriv_channels;
1482 chan < num_dst_deriv_channels; chan++)
1483 args.derivs[param * num_dst_deriv_channels + chan] =
1484 ctx->ac.f32_0;
1485 }
1486 }
1487
1488 if (target == TGSI_TEXTURE_CUBE ||
1489 target == TGSI_TEXTURE_CUBE_ARRAY ||
1490 target == TGSI_TEXTURE_SHADOWCUBE ||
1491 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
1492 ac_prepare_cube_coords(&ctx->ac,
1493 opcode == TGSI_OPCODE_TXD,
1494 target == TGSI_TEXTURE_CUBE_ARRAY ||
1495 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY,
1496 opcode == TGSI_OPCODE_LODQ,
1497 args.coords, args.derivs);
1498 } else if (tgsi_is_array_sampler(target) &&
1499 opcode != TGSI_OPCODE_TXF &&
1500 opcode != TGSI_OPCODE_TXF_LZ &&
1501 ctx->screen->info.chip_class <= GFX8) {
1502 unsigned array_coord = target == TGSI_TEXTURE_1D_ARRAY ? 1 : 2;
1503 args.coords[array_coord] = ac_build_round(&ctx->ac, args.coords[array_coord]);
1504 }
1505
1506 /* 1D textures are allocated and used as 2D on GFX9. */
1507 if (ctx->screen->info.chip_class == GFX9) {
1508 LLVMValueRef filler;
1509
1510 /* Use 0.5, so that we don't sample the border color. */
1511 if (opcode == TGSI_OPCODE_TXF ||
1512 opcode == TGSI_OPCODE_TXF_LZ)
1513 filler = ctx->i32_0;
1514 else
1515 filler = LLVMConstReal(ctx->f32, 0.5);
1516
1517 if (target == TGSI_TEXTURE_1D ||
1518 target == TGSI_TEXTURE_SHADOW1D) {
1519 args.coords[1] = filler;
1520 } else if (target == TGSI_TEXTURE_1D_ARRAY ||
1521 target == TGSI_TEXTURE_SHADOW1D_ARRAY) {
1522 args.coords[2] = args.coords[1];
1523 args.coords[1] = filler;
1524 }
1525 }
1526
1527 /* Pack LOD or sample index */
1528 if (opcode == TGSI_OPCODE_TXL)
1529 args.lod = args.coords[3];
1530 else if (opcode == TGSI_OPCODE_TXL2)
1531 args.lod = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
1532 else if (opcode == TGSI_OPCODE_TXF) {
1533 if (target == TGSI_TEXTURE_2D_MSAA) {
1534 /* No LOD, but move sample index into the right place. */
1535 args.coords[2] = args.coords[3];
1536 } else if (target != TGSI_TEXTURE_2D_ARRAY_MSAA) {
1537 args.lod = args.coords[3];
1538 }
1539 }
1540
1541 if ((target == TGSI_TEXTURE_2D_MSAA ||
1542 target == TGSI_TEXTURE_2D_ARRAY_MSAA) &&
1543 !(ctx->screen->debug_flags & DBG(NO_FMASK))) {
1544 ac_apply_fmask_to_sample(&ctx->ac, fmask_ptr, args.coords,
1545 target == TGSI_TEXTURE_2D_ARRAY_MSAA);
1546 }
1547
1548 if (opcode == TGSI_OPCODE_TXF ||
1549 opcode == TGSI_OPCODE_TXF_LZ) {
1550 /* add tex offsets */
1551 if (inst->Texture.NumOffsets) {
1552 const struct tgsi_texture_offset *off = inst->TexOffsets;
1553
1554 assert(inst->Texture.NumOffsets == 1);
1555
1556 switch (target) {
1557 case TGSI_TEXTURE_3D:
1558 args.coords[2] =
1559 LLVMBuildAdd(ctx->ac.builder, args.coords[2],
1560 ctx->imms[off->Index * TGSI_NUM_CHANNELS + off->SwizzleZ], "");
1561 /* fall through */
1562 case TGSI_TEXTURE_2D:
1563 case TGSI_TEXTURE_SHADOW2D:
1564 case TGSI_TEXTURE_RECT:
1565 case TGSI_TEXTURE_SHADOWRECT:
1566 case TGSI_TEXTURE_2D_ARRAY:
1567 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1568 args.coords[1] =
1569 LLVMBuildAdd(ctx->ac.builder, args.coords[1],
1570 ctx->imms[off->Index * TGSI_NUM_CHANNELS + off->SwizzleY], "");
1571 /* fall through */
1572 case TGSI_TEXTURE_1D:
1573 case TGSI_TEXTURE_SHADOW1D:
1574 case TGSI_TEXTURE_1D_ARRAY:
1575 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1576 args.coords[0] =
1577 LLVMBuildAdd(ctx->ac.builder, args.coords[0],
1578 ctx->imms[off->Index * TGSI_NUM_CHANNELS + off->SwizzleX], "");
1579 break;
1580 /* texture offsets do not apply to other texture targets */
1581 }
1582 }
1583 }
1584
1585 if (opcode == TGSI_OPCODE_TG4) {
1586 unsigned gather_comp = 0;
1587
1588 /* DMASK was repurposed for GATHER4. 4 components are always
1589 * returned and DMASK works like a swizzle - it selects
1590 * the component to fetch. The only valid DMASK values are
1591 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
1592 * (red,red,red,red) etc.) The ISA document doesn't mention
1593 * this.
1594 */
1595
1596 /* Get the component index from src1.x for Gather4. */
1597 if (!tgsi_is_shadow_target(target)) {
1598 LLVMValueRef comp_imm;
1599 struct tgsi_src_register src1 = inst->Src[1].Register;
1600
1601 assert(src1.File == TGSI_FILE_IMMEDIATE);
1602
1603 comp_imm = ctx->imms[src1.Index * TGSI_NUM_CHANNELS + src1.SwizzleX];
1604 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
1605 gather_comp = CLAMP(gather_comp, 0, 3);
1606 }
1607
1608 args.dmask = 1 << gather_comp;
1609 } else {
1610 args.dmask = 0xf;
1611 }
1612
1613 args.dim = ac_texture_dim_from_tgsi_target(ctx->screen, target);
1614 args.unorm = target == TGSI_TEXTURE_RECT ||
1615 target == TGSI_TEXTURE_SHADOWRECT;
1616 args.opcode = ac_image_sample;
1617
1618 switch (opcode) {
1619 case TGSI_OPCODE_TXF:
1620 case TGSI_OPCODE_TXF_LZ:
1621 args.opcode = opcode == TGSI_OPCODE_TXF_LZ ||
1622 target == TGSI_TEXTURE_2D_MSAA ||
1623 target == TGSI_TEXTURE_2D_ARRAY_MSAA ?
1624 ac_image_load : ac_image_load_mip;
1625 break;
1626 case TGSI_OPCODE_LODQ:
1627 args.opcode = ac_image_get_lod;
1628 break;
1629 case TGSI_OPCODE_TEX:
1630 case TGSI_OPCODE_TEX2:
1631 case TGSI_OPCODE_TXP:
1632 if (ctx->type != PIPE_SHADER_FRAGMENT)
1633 args.level_zero = true;
1634 break;
1635 case TGSI_OPCODE_TEX_LZ:
1636 args.level_zero = true;
1637 break;
1638 case TGSI_OPCODE_TXB:
1639 case TGSI_OPCODE_TXB2:
1640 assert(ctx->type == PIPE_SHADER_FRAGMENT);
1641 break;
1642 case TGSI_OPCODE_TXL:
1643 case TGSI_OPCODE_TXL2:
1644 break;
1645 case TGSI_OPCODE_TXD:
1646 break;
1647 case TGSI_OPCODE_TG4:
1648 args.opcode = ac_image_gather4;
1649 args.level_zero = true;
1650 break;
1651 default:
1652 assert(0);
1653 return;
1654 }
1655
1656 /* The hardware needs special lowering for Gather4 with integer formats. */
1657 LLVMValueRef gather4_int_result_workaround = NULL;
1658
1659 if (ctx->screen->info.chip_class <= GFX8 &&
1660 opcode == TGSI_OPCODE_TG4) {
1661 assert(inst->Texture.ReturnType != TGSI_RETURN_TYPE_UNKNOWN);
1662
1663 if (inst->Texture.ReturnType == TGSI_RETURN_TYPE_SINT ||
1664 inst->Texture.ReturnType == TGSI_RETURN_TYPE_UINT) {
1665 gather4_int_result_workaround =
1666 si_lower_gather4_integer(ctx, &args, target,
1667 inst->Texture.ReturnType);
1668 }
1669 }
1670
1671 args.attributes = AC_FUNC_ATTR_READNONE;
1672 LLVMValueRef result = ac_build_image_opcode(&ctx->ac, &args);
1673
1674 if (gather4_int_result_workaround) {
1675 result = si_fix_gather4_integer_result(ctx, result,
1676 inst->Texture.ReturnType,
1677 gather4_int_result_workaround);
1678 }
1679
1680 emit_data->output[emit_data->chan] = result;
1681 }
1682
1683 static void si_llvm_emit_txqs(
1684 const struct lp_build_tgsi_action *action,
1685 struct lp_build_tgsi_context *bld_base,
1686 struct lp_build_emit_data *emit_data)
1687 {
1688 struct si_shader_context *ctx = si_shader_context(bld_base);
1689 LLVMValueRef res, samples;
1690 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
1691
1692 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
1693
1694 /* Read the samples from the descriptor directly. */
1695 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->v8i32, "");
1696 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
1697 LLVMConstInt(ctx->i32, 3, 0), "");
1698 samples = LLVMBuildLShr(ctx->ac.builder, samples,
1699 LLVMConstInt(ctx->i32, 16, 0), "");
1700 samples = LLVMBuildAnd(ctx->ac.builder, samples,
1701 LLVMConstInt(ctx->i32, 0xf, 0), "");
1702 samples = LLVMBuildShl(ctx->ac.builder, ctx->i32_1,
1703 samples, "");
1704
1705 emit_data->output[emit_data->chan] = samples;
1706 }
1707
1708 static LLVMValueRef si_llvm_emit_fbfetch(struct si_shader_context *ctx)
1709 {
1710 struct ac_image_args args = {};
1711 LLVMValueRef ptr, image, fmask;
1712
1713 /* Ignore src0, because KHR_blend_func_extended disallows multiple render
1714 * targets.
1715 */
1716
1717 /* Load the image descriptor. */
1718 STATIC_ASSERT(SI_PS_IMAGE_COLORBUF0 % 2 == 0);
1719 ptr = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
1720 ptr = LLVMBuildPointerCast(ctx->ac.builder, ptr,
1721 ac_array_in_const32_addr_space(ctx->v8i32), "");
1722 image = ac_build_load_to_sgpr(&ctx->ac, ptr,
1723 LLVMConstInt(ctx->i32, SI_PS_IMAGE_COLORBUF0 / 2, 0));
1724
1725 unsigned chan = 0;
1726
1727 args.coords[chan++] = si_unpack_param(ctx, SI_PARAM_POS_FIXED_PT, 0, 16);
1728
1729 if (!ctx->shader->key.mono.u.ps.fbfetch_is_1D)
1730 args.coords[chan++] = si_unpack_param(ctx, SI_PARAM_POS_FIXED_PT, 16, 16);
1731
1732 /* Get the current render target layer index. */
1733 if (ctx->shader->key.mono.u.ps.fbfetch_layered)
1734 args.coords[chan++] = si_unpack_param(ctx, SI_PARAM_ANCILLARY, 16, 11);
1735
1736 if (ctx->shader->key.mono.u.ps.fbfetch_msaa)
1737 args.coords[chan++] = si_get_sample_id(ctx);
1738
1739 if (ctx->shader->key.mono.u.ps.fbfetch_msaa &&
1740 !(ctx->screen->debug_flags & DBG(NO_FMASK))) {
1741 fmask = ac_build_load_to_sgpr(&ctx->ac, ptr,
1742 LLVMConstInt(ctx->i32, SI_PS_IMAGE_COLORBUF0_FMASK / 2, 0));
1743
1744 ac_apply_fmask_to_sample(&ctx->ac, fmask, args.coords,
1745 ctx->shader->key.mono.u.ps.fbfetch_layered);
1746 }
1747
1748 args.opcode = ac_image_load;
1749 args.resource = image;
1750 args.dmask = 0xf;
1751 args.attributes = AC_FUNC_ATTR_READNONE;
1752
1753 if (ctx->shader->key.mono.u.ps.fbfetch_msaa)
1754 args.dim = ctx->shader->key.mono.u.ps.fbfetch_layered ?
1755 ac_image_2darraymsaa : ac_image_2dmsaa;
1756 else if (ctx->shader->key.mono.u.ps.fbfetch_is_1D)
1757 args.dim = ctx->shader->key.mono.u.ps.fbfetch_layered ?
1758 ac_image_1darray : ac_image_1d;
1759 else
1760 args.dim = ctx->shader->key.mono.u.ps.fbfetch_layered ?
1761 ac_image_2darray : ac_image_2d;
1762
1763 return ac_build_image_opcode(&ctx->ac, &args);
1764 }
1765
1766 static void si_tgsi_emit_fbfetch(const struct lp_build_tgsi_action *action,
1767 struct lp_build_tgsi_context *bld_base,
1768 struct lp_build_emit_data *emit_data)
1769 {
1770 struct si_shader_context *ctx = si_shader_context(bld_base);
1771
1772 emit_data->output[emit_data->chan] = si_llvm_emit_fbfetch(ctx);
1773 }
1774
1775 LLVMValueRef si_nir_emit_fbfetch(struct ac_shader_abi *abi)
1776 {
1777 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1778
1779 return si_llvm_emit_fbfetch(ctx);
1780 }
1781
1782 /**
1783 * Setup actions for TGSI memory opcode, including texture opcodes.
1784 */
1785 void si_shader_context_init_mem(struct si_shader_context *ctx)
1786 {
1787 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
1788
1789 bld_base->op_actions[TGSI_OPCODE_TEX].emit = build_tex_intrinsic;
1790 bld_base->op_actions[TGSI_OPCODE_TEX_LZ].emit = build_tex_intrinsic;
1791 bld_base->op_actions[TGSI_OPCODE_TEX2].emit = build_tex_intrinsic;
1792 bld_base->op_actions[TGSI_OPCODE_TXB].emit = build_tex_intrinsic;
1793 bld_base->op_actions[TGSI_OPCODE_TXB2].emit = build_tex_intrinsic;
1794 bld_base->op_actions[TGSI_OPCODE_TXD].emit = build_tex_intrinsic;
1795 bld_base->op_actions[TGSI_OPCODE_TXF].emit = build_tex_intrinsic;
1796 bld_base->op_actions[TGSI_OPCODE_TXF_LZ].emit = build_tex_intrinsic;
1797 bld_base->op_actions[TGSI_OPCODE_TXL].emit = build_tex_intrinsic;
1798 bld_base->op_actions[TGSI_OPCODE_TXL2].emit = build_tex_intrinsic;
1799 bld_base->op_actions[TGSI_OPCODE_TXP].emit = build_tex_intrinsic;
1800 bld_base->op_actions[TGSI_OPCODE_TXQ].emit = resq_emit;
1801 bld_base->op_actions[TGSI_OPCODE_TG4].emit = build_tex_intrinsic;
1802 bld_base->op_actions[TGSI_OPCODE_LODQ].emit = build_tex_intrinsic;
1803 bld_base->op_actions[TGSI_OPCODE_TXQS].emit = si_llvm_emit_txqs;
1804
1805 bld_base->op_actions[TGSI_OPCODE_FBFETCH].emit = si_tgsi_emit_fbfetch;
1806
1807 bld_base->op_actions[TGSI_OPCODE_LOAD].emit = load_emit;
1808 bld_base->op_actions[TGSI_OPCODE_STORE].emit = store_emit;
1809 bld_base->op_actions[TGSI_OPCODE_RESQ].emit = resq_emit;
1810
1811 bld_base->op_actions[TGSI_OPCODE_ATOMUADD].emit = atomic_emit;
1812 bld_base->op_actions[TGSI_OPCODE_ATOMUADD].intr_name = "add";
1813 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG].emit = atomic_emit;
1814 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG].intr_name = "swap";
1815 bld_base->op_actions[TGSI_OPCODE_ATOMCAS].emit = atomic_emit;
1816 bld_base->op_actions[TGSI_OPCODE_ATOMCAS].intr_name = "cmpswap";
1817 bld_base->op_actions[TGSI_OPCODE_ATOMAND].emit = atomic_emit;
1818 bld_base->op_actions[TGSI_OPCODE_ATOMAND].intr_name = "and";
1819 bld_base->op_actions[TGSI_OPCODE_ATOMOR].emit = atomic_emit;
1820 bld_base->op_actions[TGSI_OPCODE_ATOMOR].intr_name = "or";
1821 bld_base->op_actions[TGSI_OPCODE_ATOMXOR].emit = atomic_emit;
1822 bld_base->op_actions[TGSI_OPCODE_ATOMXOR].intr_name = "xor";
1823 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN].emit = atomic_emit;
1824 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN].intr_name = "umin";
1825 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX].emit = atomic_emit;
1826 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX].intr_name = "umax";
1827 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN].emit = atomic_emit;
1828 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN].intr_name = "smin";
1829 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX].emit = atomic_emit;
1830 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX].intr_name = "smax";
1831 bld_base->op_actions[TGSI_OPCODE_ATOMINC_WRAP].emit = atomic_emit;
1832 bld_base->op_actions[TGSI_OPCODE_ATOMINC_WRAP].intr_name = "inc";
1833 bld_base->op_actions[TGSI_OPCODE_ATOMDEC_WRAP].emit = atomic_emit;
1834 bld_base->op_actions[TGSI_OPCODE_ATOMDEC_WRAP].intr_name = "dec";
1835 }