2 * Copyright 2017 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "si_shader_internal.h"
28 #include "gallivm/lp_bld_arit.h"
29 #include "gallivm/lp_bld_gather.h"
30 #include "gallivm/lp_bld_intr.h"
31 #include "tgsi/tgsi_build.h"
32 #include "tgsi/tgsi_parse.h"
33 #include "tgsi/tgsi_util.h"
35 static void build_tex_intrinsic(const struct lp_build_tgsi_action
*action
,
36 struct lp_build_tgsi_context
*bld_base
,
37 struct lp_build_emit_data
*emit_data
);
39 static const struct lp_build_tgsi_action tex_action
;
42 * Given a v8i32 resource descriptor for a buffer, extract the size of the
43 * buffer in number of elements and return it as an i32.
45 static LLVMValueRef
get_buffer_size(
46 struct lp_build_tgsi_context
*bld_base
,
47 LLVMValueRef descriptor
)
49 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
50 LLVMBuilderRef builder
= ctx
->ac
.builder
;
52 LLVMBuildExtractElement(builder
, descriptor
,
53 LLVMConstInt(ctx
->i32
, 2, 0), "");
55 if (ctx
->screen
->info
.chip_class
== VI
) {
56 /* On VI, the descriptor contains the size in bytes,
57 * but TXQ must return the size in elements.
58 * The stride is always non-zero for resources using TXQ.
61 LLVMBuildExtractElement(builder
, descriptor
,
63 stride
= LLVMBuildLShr(builder
, stride
,
64 LLVMConstInt(ctx
->i32
, 16, 0), "");
65 stride
= LLVMBuildAnd(builder
, stride
,
66 LLVMConstInt(ctx
->i32
, 0x3FFF, 0), "");
68 size
= LLVMBuildUDiv(builder
, size
, stride
, "");
75 shader_buffer_fetch_rsrc(struct si_shader_context
*ctx
,
76 const struct tgsi_full_src_register
*reg
,
81 if (!reg
->Register
.Indirect
) {
82 index
= LLVMConstInt(ctx
->i32
, reg
->Register
.Index
, false);
84 index
= si_get_indirect_index(ctx
, ®
->Indirect
,
85 1, reg
->Register
.Index
);
89 return ctx
->abi
.load_ubo(&ctx
->abi
, index
);
91 return ctx
->abi
.load_ssbo(&ctx
->abi
, index
, false);
94 static enum ac_image_dim
95 ac_texture_dim_from_tgsi_target(struct si_screen
*screen
, enum tgsi_texture_type target
)
99 case TGSI_TEXTURE_SHADOW1D
:
100 if (screen
->info
.chip_class
>= GFX9
)
103 case TGSI_TEXTURE_2D
:
104 case TGSI_TEXTURE_SHADOW2D
:
105 case TGSI_TEXTURE_RECT
:
106 case TGSI_TEXTURE_SHADOWRECT
:
108 case TGSI_TEXTURE_3D
:
110 case TGSI_TEXTURE_CUBE
:
111 case TGSI_TEXTURE_SHADOWCUBE
:
112 case TGSI_TEXTURE_CUBE_ARRAY
:
113 case TGSI_TEXTURE_SHADOWCUBE_ARRAY
:
114 return ac_image_cube
;
115 case TGSI_TEXTURE_1D_ARRAY
:
116 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
117 if (screen
->info
.chip_class
>= GFX9
)
118 return ac_image_2darray
;
119 return ac_image_1darray
;
120 case TGSI_TEXTURE_2D_ARRAY
:
121 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
122 return ac_image_2darray
;
123 case TGSI_TEXTURE_2D_MSAA
:
124 return ac_image_2dmsaa
;
125 case TGSI_TEXTURE_2D_ARRAY_MSAA
:
126 return ac_image_2darraymsaa
;
128 unreachable("unhandled texture type");
132 static enum ac_image_dim
133 ac_image_dim_from_tgsi_target(struct si_screen
*screen
, enum tgsi_texture_type target
)
135 enum ac_image_dim dim
= ac_texture_dim_from_tgsi_target(screen
, target
);
137 /* Match the resource type set in the descriptor. */
138 if (dim
== ac_image_cube
||
139 (screen
->info
.chip_class
<= VI
&& dim
== ac_image_3d
))
140 dim
= ac_image_2darray
;
141 else if (target
== TGSI_TEXTURE_2D
&& screen
->info
.chip_class
>= GFX9
) {
142 /* When a single layer of a 3D texture is bound, the shader
143 * will refer to a 2D target, but the descriptor has a 3D type.
144 * Since the HW ignores BASE_ARRAY in this case, we need to
145 * send 3 coordinates. This doesn't hurt when the underlying
155 * Given a 256-bit resource descriptor, force the DCC enable bit to off.
157 * At least on Tonga, executing image stores on images with DCC enabled and
158 * non-trivial can eventually lead to lockups. This can occur when an
159 * application binds an image as read-only but then uses a shader that writes
160 * to it. The OpenGL spec allows almost arbitrarily bad behavior (including
161 * program termination) in this case, but it doesn't cost much to be a bit
162 * nicer: disabling DCC in the shader still leads to undefined results but
165 static LLVMValueRef
force_dcc_off(struct si_shader_context
*ctx
,
168 if (ctx
->screen
->info
.chip_class
<= CIK
) {
171 LLVMValueRef i32_6
= LLVMConstInt(ctx
->i32
, 6, 0);
172 LLVMValueRef i32_C
= LLVMConstInt(ctx
->i32
, C_008F28_COMPRESSION_EN
, 0);
175 tmp
= LLVMBuildExtractElement(ctx
->ac
.builder
, rsrc
, i32_6
, "");
176 tmp
= LLVMBuildAnd(ctx
->ac
.builder
, tmp
, i32_C
, "");
177 return LLVMBuildInsertElement(ctx
->ac
.builder
, rsrc
, tmp
, i32_6
, "");
181 LLVMValueRef
si_load_image_desc(struct si_shader_context
*ctx
,
182 LLVMValueRef list
, LLVMValueRef index
,
183 enum ac_descriptor_type desc_type
, bool dcc_off
)
185 LLVMBuilderRef builder
= ctx
->ac
.builder
;
188 if (desc_type
== AC_DESC_BUFFER
) {
189 index
= LLVMBuildMul(builder
, index
,
190 LLVMConstInt(ctx
->i32
, 2, 0), "");
191 index
= LLVMBuildAdd(builder
, index
,
193 list
= LLVMBuildPointerCast(builder
, list
,
194 ac_array_in_const32_addr_space(ctx
->v4i32
), "");
196 assert(desc_type
== AC_DESC_IMAGE
);
199 rsrc
= ac_build_load_to_sgpr(&ctx
->ac
, list
, index
);
200 if (desc_type
== AC_DESC_IMAGE
&& dcc_off
)
201 rsrc
= force_dcc_off(ctx
, rsrc
);
206 * Load the resource descriptor for \p image.
210 struct lp_build_tgsi_context
*bld_base
,
211 const struct tgsi_full_src_register
*image
,
212 bool is_store
, unsigned target
,
215 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
216 LLVMValueRef rsrc_ptr
= LLVMGetParam(ctx
->main_fn
,
217 ctx
->param_samplers_and_images
);
219 bool dcc_off
= is_store
;
221 if (!image
->Register
.Indirect
) {
222 const struct tgsi_shader_info
*info
= bld_base
->info
;
223 unsigned images_writemask
= info
->images_store
|
226 index
= LLVMConstInt(ctx
->i32
,
227 si_get_image_slot(image
->Register
.Index
), 0);
229 if (images_writemask
& (1 << image
->Register
.Index
))
232 /* From the GL_ARB_shader_image_load_store extension spec:
234 * If a shader performs an image load, store, or atomic
235 * operation using an image variable declared as an array,
236 * and if the index used to select an individual element is
237 * negative or greater than or equal to the size of the
238 * array, the results of the operation are undefined but may
239 * not lead to termination.
241 index
= si_get_bounded_indirect_index(ctx
, &image
->Indirect
,
242 image
->Register
.Index
,
244 index
= LLVMBuildSub(ctx
->ac
.builder
,
245 LLVMConstInt(ctx
->i32
, SI_NUM_IMAGES
- 1, 0),
249 if (image
->Register
.File
!= TGSI_FILE_IMAGE
) {
250 /* Bindless descriptors are accessible from a different pair of
253 rsrc_ptr
= LLVMGetParam(ctx
->main_fn
,
254 ctx
->param_bindless_samplers_and_images
);
255 index
= lp_build_emit_fetch_src(bld_base
, image
,
256 TGSI_TYPE_UNSIGNED
, 0);
258 /* For simplicity, bindless image descriptors use fixed
259 * 16-dword slots for now.
261 index
= LLVMBuildMul(ctx
->ac
.builder
, index
,
262 LLVMConstInt(ctx
->i32
, 2, 0), "");
265 *rsrc
= si_load_image_desc(ctx
, rsrc_ptr
, index
,
266 target
== TGSI_TEXTURE_BUFFER
? AC_DESC_BUFFER
: AC_DESC_IMAGE
,
270 static void image_fetch_coords(
271 struct lp_build_tgsi_context
*bld_base
,
272 const struct tgsi_full_instruction
*inst
,
273 unsigned src
, LLVMValueRef desc
,
274 LLVMValueRef
*coords
)
276 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
277 LLVMBuilderRef builder
= ctx
->ac
.builder
;
278 unsigned target
= inst
->Memory
.Texture
;
279 const unsigned num_coords
= tgsi_util_get_texture_coord_dim(target
);
283 for (chan
= 0; chan
< num_coords
; ++chan
) {
284 tmp
= lp_build_emit_fetch(bld_base
, inst
, src
, chan
);
285 tmp
= ac_to_integer(&ctx
->ac
, tmp
);
289 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
290 /* 1D textures are allocated and used as 2D on GFX9. */
291 if (target
== TGSI_TEXTURE_1D
) {
292 coords
[1] = ctx
->i32_0
;
293 } else if (target
== TGSI_TEXTURE_1D_ARRAY
) {
294 coords
[2] = coords
[1];
295 coords
[1] = ctx
->i32_0
;
296 } else if (target
== TGSI_TEXTURE_2D
) {
297 /* The hw can't bind a slice of a 3D image as a 2D
298 * image, because it ignores BASE_ARRAY if the target
299 * is 3D. The workaround is to read BASE_ARRAY and set
300 * it as the 3rd address operand for all 2D images.
302 LLVMValueRef first_layer
, const5
, mask
;
304 const5
= LLVMConstInt(ctx
->i32
, 5, 0);
305 mask
= LLVMConstInt(ctx
->i32
, S_008F24_BASE_ARRAY(~0), 0);
306 first_layer
= LLVMBuildExtractElement(builder
, desc
, const5
, "");
307 first_layer
= LLVMBuildAnd(builder
, first_layer
, mask
, "");
309 coords
[2] = first_layer
;
315 * Append the resource and indexing arguments for buffer intrinsics.
317 * \param rsrc the v4i32 buffer resource
318 * \param index index into the buffer (stride-based)
319 * \param offset byte offset into the buffer
321 static void buffer_append_args(
322 struct si_shader_context
*ctx
,
323 struct lp_build_emit_data
*emit_data
,
330 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
331 LLVMValueRef i1false
= LLVMConstInt(ctx
->i1
, 0, 0);
332 LLVMValueRef i1true
= LLVMConstInt(ctx
->i1
, 1, 0);
334 emit_data
->args
[emit_data
->arg_count
++] = rsrc
;
335 emit_data
->args
[emit_data
->arg_count
++] = index
; /* vindex */
336 emit_data
->args
[emit_data
->arg_count
++] = offset
; /* voffset */
338 emit_data
->args
[emit_data
->arg_count
++] =
340 inst
->Memory
.Qualifier
& (TGSI_MEMORY_COHERENT
| TGSI_MEMORY_VOLATILE
) ?
341 i1true
: i1false
; /* glc */
343 emit_data
->args
[emit_data
->arg_count
++] = i1false
; /* slc */
346 static void load_fetch_args(
347 struct lp_build_tgsi_context
* bld_base
,
348 struct lp_build_emit_data
* emit_data
)
350 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
351 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
352 unsigned target
= inst
->Memory
.Texture
;
355 emit_data
->dst_type
= ctx
->v4f32
;
357 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
||
358 inst
->Src
[0].Register
.File
== TGSI_FILE_CONSTBUF
) {
362 bool ubo
= inst
->Src
[0].Register
.File
== TGSI_FILE_CONSTBUF
;
363 rsrc
= shader_buffer_fetch_rsrc(ctx
, &inst
->Src
[0], ubo
);
365 tmp
= lp_build_emit_fetch(bld_base
, inst
, 1, 0);
366 offset
= ac_to_integer(&ctx
->ac
, tmp
);
368 buffer_append_args(ctx
, emit_data
, rsrc
, ctx
->i32_0
,
369 offset
, false, false);
370 } else if (inst
->Src
[0].Register
.File
== TGSI_FILE_IMAGE
||
371 tgsi_is_bindless_image_file(inst
->Src
[0].Register
.File
)) {
372 image_fetch_rsrc(bld_base
, &inst
->Src
[0], false, target
, &rsrc
);
373 image_fetch_coords(bld_base
, inst
, 1, rsrc
, &emit_data
->args
[1]);
375 if (target
== TGSI_TEXTURE_BUFFER
) {
376 buffer_append_args(ctx
, emit_data
, rsrc
, emit_data
->args
[1],
377 ctx
->i32_0
, false, false);
379 emit_data
->args
[0] = rsrc
;
384 static void load_emit_buffer(struct si_shader_context
*ctx
,
385 struct lp_build_emit_data
*emit_data
,
386 bool can_speculate
, bool allow_smem
)
388 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
389 uint writemask
= inst
->Dst
[0].Register
.WriteMask
;
390 uint count
= util_last_bit(writemask
);
391 LLVMValueRef
*args
= emit_data
->args
;
393 /* Don't use SMEM for shader buffer loads, because LLVM doesn't
394 * select SMEM for SI.load.const with a non-constant offset, and
395 * constant offsets practically don't exist with shader buffers.
397 * Also, SI.load.const doesn't use inst_offset when it's lowered
398 * to VMEM, so we just end up with more VALU instructions in the end
401 * TODO: Remove this line once LLVM can select SMEM with a non-constant
402 * offset, and can derive inst_offset when VMEM is selected.
403 * After that, si_memory_barrier should invalidate sL1 for shader
407 assert(LLVMConstIntGetZExtValue(args
[1]) == 0); /* vindex */
408 emit_data
->output
[emit_data
->chan
] =
409 ac_build_buffer_load(&ctx
->ac
, args
[0], count
, NULL
,
411 LLVMConstIntGetZExtValue(args
[3]),
412 LLVMConstIntGetZExtValue(args
[4]),
413 can_speculate
, allow_smem
);
416 static LLVMValueRef
get_memory_ptr(struct si_shader_context
*ctx
,
417 const struct tgsi_full_instruction
*inst
,
418 LLVMTypeRef type
, int arg
)
420 LLVMBuilderRef builder
= ctx
->ac
.builder
;
421 LLVMValueRef offset
, ptr
;
424 offset
= lp_build_emit_fetch(&ctx
->bld_base
, inst
, arg
, 0);
425 offset
= ac_to_integer(&ctx
->ac
, offset
);
428 ptr
= LLVMBuildGEP(builder
, ptr
, &offset
, 1, "");
429 addr_space
= LLVMGetPointerAddressSpace(LLVMTypeOf(ptr
));
430 ptr
= LLVMBuildBitCast(builder
, ptr
, LLVMPointerType(type
, addr_space
), "");
435 static void load_emit_memory(
436 struct si_shader_context
*ctx
,
437 struct lp_build_emit_data
*emit_data
)
439 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
440 unsigned writemask
= inst
->Dst
[0].Register
.WriteMask
;
441 LLVMValueRef channels
[4], ptr
, derived_ptr
, index
;
444 ptr
= get_memory_ptr(ctx
, inst
, ctx
->f32
, 1);
446 for (chan
= 0; chan
< 4; ++chan
) {
447 if (!(writemask
& (1 << chan
))) {
448 channels
[chan
] = LLVMGetUndef(ctx
->f32
);
452 index
= LLVMConstInt(ctx
->i32
, chan
, 0);
453 derived_ptr
= LLVMBuildGEP(ctx
->ac
.builder
, ptr
, &index
, 1, "");
454 channels
[chan
] = LLVMBuildLoad(ctx
->ac
.builder
, derived_ptr
, "");
456 emit_data
->output
[emit_data
->chan
] = lp_build_gather_values(&ctx
->gallivm
, channels
, 4);
460 * Return true if the memory accessed by a LOAD or STORE instruction is
461 * read-only or write-only, respectively.
463 * \param shader_buffers_reverse_access_mask
464 * For LOAD, set this to (store | atomic) slot usage in the shader.
465 * For STORE, set this to (load | atomic) slot usage in the shader.
466 * \param images_reverse_access_mask Same as above, but for images.
468 static bool is_oneway_access_only(const struct tgsi_full_instruction
*inst
,
469 const struct tgsi_shader_info
*info
,
470 unsigned shader_buffers_reverse_access_mask
,
471 unsigned images_reverse_access_mask
)
473 /* RESTRICT means NOALIAS.
474 * If there are no writes, we can assume the accessed memory is read-only.
475 * If there are no reads, we can assume the accessed memory is write-only.
477 if (inst
->Memory
.Qualifier
& TGSI_MEMORY_RESTRICT
) {
478 unsigned reverse_access_mask
;
480 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
) {
481 reverse_access_mask
= shader_buffers_reverse_access_mask
;
482 } else if (inst
->Memory
.Texture
== TGSI_TEXTURE_BUFFER
) {
483 reverse_access_mask
= info
->images_buffers
&
484 images_reverse_access_mask
;
486 reverse_access_mask
= ~info
->images_buffers
&
487 images_reverse_access_mask
;
490 if (inst
->Src
[0].Register
.Indirect
) {
491 if (!reverse_access_mask
)
494 if (!(reverse_access_mask
&
495 (1u << inst
->Src
[0].Register
.Index
)))
500 /* If there are no buffer writes (for both shader buffers & image
501 * buffers), it implies that buffer memory is read-only.
502 * If there are no buffer reads (for both shader buffers & image
503 * buffers), it implies that buffer memory is write-only.
505 * Same for the case when there are no writes/reads for non-buffer
508 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
||
509 (inst
->Memory
.Texture
== TGSI_TEXTURE_BUFFER
&&
510 (inst
->Src
[0].Register
.File
== TGSI_FILE_IMAGE
||
511 tgsi_is_bindless_image_file(inst
->Src
[0].Register
.File
)))) {
512 if (!shader_buffers_reverse_access_mask
&&
513 !(info
->images_buffers
& images_reverse_access_mask
))
516 if (!(~info
->images_buffers
& images_reverse_access_mask
))
522 static void load_emit(
523 const struct lp_build_tgsi_action
*action
,
524 struct lp_build_tgsi_context
*bld_base
,
525 struct lp_build_emit_data
*emit_data
)
527 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
528 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
529 const struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
530 bool can_speculate
= false;
532 if (inst
->Src
[0].Register
.File
== TGSI_FILE_MEMORY
) {
533 load_emit_memory(ctx
, emit_data
);
537 if (inst
->Src
[0].Register
.File
== TGSI_FILE_CONSTBUF
) {
538 load_emit_buffer(ctx
, emit_data
, true, true);
542 if (inst
->Memory
.Qualifier
& TGSI_MEMORY_VOLATILE
)
543 ac_build_waitcnt(&ctx
->ac
, VM_CNT
);
545 can_speculate
= !(inst
->Memory
.Qualifier
& TGSI_MEMORY_VOLATILE
) &&
546 is_oneway_access_only(inst
, info
,
547 info
->shader_buffers_store
|
548 info
->shader_buffers_atomic
,
550 info
->images_atomic
);
552 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
) {
553 load_emit_buffer(ctx
, emit_data
, can_speculate
, false);
557 if (inst
->Memory
.Texture
== TGSI_TEXTURE_BUFFER
) {
558 unsigned num_channels
= util_last_bit(inst
->Dst
[0].Register
.WriteMask
);
559 LLVMValueRef result
=
560 ac_build_buffer_load_format(&ctx
->ac
,
565 LLVMConstIntGetZExtValue(emit_data
->args
[3]),
567 emit_data
->output
[emit_data
->chan
] =
568 ac_build_expand_to_vec4(&ctx
->ac
, result
, num_channels
);
570 struct ac_image_args args
= {};
571 args
.opcode
= ac_image_load
;
572 args
.resource
= emit_data
->args
[0];
573 memcpy(args
.coords
, &emit_data
->args
[1], sizeof(args
.coords
));
574 args
.dim
= ac_image_dim_from_tgsi_target(ctx
->screen
, inst
->Memory
.Texture
);
575 if (inst
->Memory
.Qualifier
& (TGSI_MEMORY_COHERENT
| TGSI_MEMORY_VOLATILE
))
576 args
.cache_policy
= ac_glc
;
577 args
.attributes
= ac_get_load_intr_attribs(can_speculate
);
580 emit_data
->output
[emit_data
->chan
] =
581 ac_build_image_opcode(&ctx
->ac
, &args
);
585 static void store_fetch_args(
586 struct lp_build_tgsi_context
* bld_base
,
587 struct lp_build_emit_data
* emit_data
)
589 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
590 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
591 struct tgsi_full_src_register memory
;
592 LLVMValueRef chans
[4];
597 emit_data
->dst_type
= ctx
->voidt
;
599 for (chan
= 0; chan
< 4; ++chan
) {
600 chans
[chan
] = lp_build_emit_fetch(bld_base
, inst
, 1, chan
);
602 data
= lp_build_gather_values(&ctx
->gallivm
, chans
, 4);
604 emit_data
->args
[emit_data
->arg_count
++] = data
;
606 memory
= tgsi_full_src_register_from_dst(&inst
->Dst
[0]);
608 if (inst
->Dst
[0].Register
.File
== TGSI_FILE_BUFFER
) {
612 rsrc
= shader_buffer_fetch_rsrc(ctx
, &memory
, false);
614 tmp
= lp_build_emit_fetch(bld_base
, inst
, 0, 0);
615 offset
= ac_to_integer(&ctx
->ac
, tmp
);
617 buffer_append_args(ctx
, emit_data
, rsrc
, ctx
->i32_0
,
618 offset
, false, false);
619 } else if (inst
->Dst
[0].Register
.File
== TGSI_FILE_IMAGE
||
620 tgsi_is_bindless_image_file(inst
->Dst
[0].Register
.File
)) {
621 unsigned target
= inst
->Memory
.Texture
;
623 /* 8bit/16bit TC L1 write corruption bug on SI.
624 * All store opcodes not aligned to a dword are affected.
626 * The only way to get unaligned stores in radeonsi is through
629 bool force_glc
= ctx
->screen
->info
.chip_class
== SI
;
631 image_fetch_rsrc(bld_base
, &memory
, true, target
, &rsrc
);
632 image_fetch_coords(bld_base
, inst
, 0, rsrc
, &emit_data
->args
[2]);
634 if (target
== TGSI_TEXTURE_BUFFER
) {
635 buffer_append_args(ctx
, emit_data
, rsrc
, emit_data
->args
[2],
636 ctx
->i32_0
, false, force_glc
);
638 emit_data
->args
[1] = rsrc
;
643 static void store_emit_buffer(
644 struct si_shader_context
*ctx
,
645 struct lp_build_emit_data
*emit_data
,
646 bool writeonly_memory
)
648 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
649 LLVMBuilderRef builder
= ctx
->ac
.builder
;
650 LLVMValueRef base_data
= emit_data
->args
[0];
651 LLVMValueRef base_offset
= emit_data
->args
[3];
652 unsigned writemask
= inst
->Dst
[0].Register
.WriteMask
;
656 const char *intrinsic_name
;
661 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
663 /* Due to an LLVM limitation, split 3-element writes
664 * into a 2-element and a 1-element write. */
666 writemask
|= 1 << (start
+ 2);
672 intrinsic_name
= "llvm.amdgcn.buffer.store.v4f32";
673 } else if (count
== 2) {
674 LLVMTypeRef v2f32
= LLVMVectorType(ctx
->f32
, 2);
676 tmp
= LLVMBuildExtractElement(
678 LLVMConstInt(ctx
->i32
, start
, 0), "");
679 data
= LLVMBuildInsertElement(
680 builder
, LLVMGetUndef(v2f32
), tmp
,
683 tmp
= LLVMBuildExtractElement(
685 LLVMConstInt(ctx
->i32
, start
+ 1, 0), "");
686 data
= LLVMBuildInsertElement(
687 builder
, data
, tmp
, ctx
->i32_1
, "");
689 intrinsic_name
= "llvm.amdgcn.buffer.store.v2f32";
692 data
= LLVMBuildExtractElement(
694 LLVMConstInt(ctx
->i32
, start
, 0), "");
695 intrinsic_name
= "llvm.amdgcn.buffer.store.f32";
698 offset
= base_offset
;
700 offset
= LLVMBuildAdd(
702 LLVMConstInt(ctx
->i32
, start
* 4, 0), "");
705 emit_data
->args
[0] = data
;
706 emit_data
->args
[3] = offset
;
709 builder
, intrinsic_name
, emit_data
->dst_type
,
710 emit_data
->args
, emit_data
->arg_count
,
711 ac_get_store_intr_attribs(writeonly_memory
));
715 static void store_emit_memory(
716 struct si_shader_context
*ctx
,
717 struct lp_build_emit_data
*emit_data
)
719 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
720 LLVMBuilderRef builder
= ctx
->ac
.builder
;
721 unsigned writemask
= inst
->Dst
[0].Register
.WriteMask
;
722 LLVMValueRef ptr
, derived_ptr
, data
, index
;
725 ptr
= get_memory_ptr(ctx
, inst
, ctx
->f32
, 0);
727 for (chan
= 0; chan
< 4; ++chan
) {
728 if (!(writemask
& (1 << chan
))) {
731 data
= lp_build_emit_fetch(&ctx
->bld_base
, inst
, 1, chan
);
732 index
= LLVMConstInt(ctx
->i32
, chan
, 0);
733 derived_ptr
= LLVMBuildGEP(builder
, ptr
, &index
, 1, "");
734 LLVMBuildStore(builder
, data
, derived_ptr
);
738 static void store_emit(
739 const struct lp_build_tgsi_action
*action
,
740 struct lp_build_tgsi_context
*bld_base
,
741 struct lp_build_emit_data
*emit_data
)
743 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
744 LLVMBuilderRef builder
= ctx
->ac
.builder
;
745 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
746 const struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
747 unsigned target
= inst
->Memory
.Texture
;
748 bool writeonly_memory
= false;
750 if (inst
->Dst
[0].Register
.File
== TGSI_FILE_MEMORY
) {
751 store_emit_memory(ctx
, emit_data
);
755 if (inst
->Memory
.Qualifier
& TGSI_MEMORY_VOLATILE
)
756 ac_build_waitcnt(&ctx
->ac
, VM_CNT
);
758 writeonly_memory
= is_oneway_access_only(inst
, info
,
759 info
->shader_buffers_load
|
760 info
->shader_buffers_atomic
,
762 info
->images_atomic
);
764 if (inst
->Dst
[0].Register
.File
== TGSI_FILE_BUFFER
) {
765 store_emit_buffer(ctx
, emit_data
, writeonly_memory
);
769 if (target
== TGSI_TEXTURE_BUFFER
) {
770 emit_data
->output
[emit_data
->chan
] = lp_build_intrinsic(
771 builder
, "llvm.amdgcn.buffer.store.format.v4f32",
772 emit_data
->dst_type
, emit_data
->args
,
773 emit_data
->arg_count
,
774 ac_get_store_intr_attribs(writeonly_memory
));
776 struct ac_image_args args
= {};
777 args
.opcode
= ac_image_store
;
778 args
.data
[0] = emit_data
->args
[0];
779 args
.resource
= emit_data
->args
[1];
780 memcpy(args
.coords
, &emit_data
->args
[2], sizeof(args
.coords
));
781 args
.dim
= ac_image_dim_from_tgsi_target(ctx
->screen
, inst
->Memory
.Texture
);
782 args
.attributes
= ac_get_store_intr_attribs(writeonly_memory
);
785 /* Workaround for 8bit/16bit TC L1 write corruption bug on SI.
786 * All store opcodes not aligned to a dword are affected.
788 bool force_glc
= ctx
->screen
->info
.chip_class
== SI
;
790 inst
->Memory
.Qualifier
& (TGSI_MEMORY_COHERENT
| TGSI_MEMORY_VOLATILE
))
791 args
.cache_policy
= ac_glc
;
793 emit_data
->output
[emit_data
->chan
] =
794 ac_build_image_opcode(&ctx
->ac
, &args
);
798 static void atomic_fetch_args(
799 struct lp_build_tgsi_context
* bld_base
,
800 struct lp_build_emit_data
* emit_data
)
802 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
803 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
804 LLVMValueRef data1
, data2
;
808 emit_data
->dst_type
= ctx
->f32
;
810 tmp
= lp_build_emit_fetch(bld_base
, inst
, 2, 0);
811 data1
= ac_to_integer(&ctx
->ac
, tmp
);
813 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
) {
814 tmp
= lp_build_emit_fetch(bld_base
, inst
, 3, 0);
815 data2
= ac_to_integer(&ctx
->ac
, tmp
);
818 /* llvm.amdgcn.image/buffer.atomic.cmpswap reflect the hardware order
819 * of arguments, which is reversed relative to TGSI (and GLSL)
821 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
)
822 emit_data
->args
[emit_data
->arg_count
++] = data2
;
823 emit_data
->args
[emit_data
->arg_count
++] = data1
;
825 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
) {
828 rsrc
= shader_buffer_fetch_rsrc(ctx
, &inst
->Src
[0], false);
830 tmp
= lp_build_emit_fetch(bld_base
, inst
, 1, 0);
831 offset
= ac_to_integer(&ctx
->ac
, tmp
);
833 buffer_append_args(ctx
, emit_data
, rsrc
, ctx
->i32_0
,
834 offset
, true, false);
835 } else if (inst
->Src
[0].Register
.File
== TGSI_FILE_IMAGE
||
836 tgsi_is_bindless_image_file(inst
->Src
[0].Register
.File
)) {
837 unsigned target
= inst
->Memory
.Texture
;
839 image_fetch_rsrc(bld_base
, &inst
->Src
[0], true, target
, &rsrc
);
840 image_fetch_coords(bld_base
, inst
, 1, rsrc
,
841 &emit_data
->args
[emit_data
->arg_count
+ 1]);
843 if (target
== TGSI_TEXTURE_BUFFER
) {
844 buffer_append_args(ctx
, emit_data
, rsrc
,
845 emit_data
->args
[emit_data
->arg_count
+ 1],
846 ctx
->i32_0
, true, false);
848 emit_data
->args
[emit_data
->arg_count
] = rsrc
;
853 static void atomic_emit_memory(struct si_shader_context
*ctx
,
854 struct lp_build_emit_data
*emit_data
) {
855 LLVMBuilderRef builder
= ctx
->ac
.builder
;
856 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
857 LLVMValueRef ptr
, result
, arg
;
859 ptr
= get_memory_ptr(ctx
, inst
, ctx
->i32
, 1);
861 arg
= lp_build_emit_fetch(&ctx
->bld_base
, inst
, 2, 0);
862 arg
= ac_to_integer(&ctx
->ac
, arg
);
864 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
) {
865 LLVMValueRef new_data
;
866 new_data
= lp_build_emit_fetch(&ctx
->bld_base
,
869 new_data
= ac_to_integer(&ctx
->ac
, new_data
);
871 result
= LLVMBuildAtomicCmpXchg(builder
, ptr
, arg
, new_data
,
872 LLVMAtomicOrderingSequentiallyConsistent
,
873 LLVMAtomicOrderingSequentiallyConsistent
,
876 result
= LLVMBuildExtractValue(builder
, result
, 0, "");
878 LLVMAtomicRMWBinOp op
;
880 switch(inst
->Instruction
.Opcode
) {
881 case TGSI_OPCODE_ATOMUADD
:
882 op
= LLVMAtomicRMWBinOpAdd
;
884 case TGSI_OPCODE_ATOMXCHG
:
885 op
= LLVMAtomicRMWBinOpXchg
;
887 case TGSI_OPCODE_ATOMAND
:
888 op
= LLVMAtomicRMWBinOpAnd
;
890 case TGSI_OPCODE_ATOMOR
:
891 op
= LLVMAtomicRMWBinOpOr
;
893 case TGSI_OPCODE_ATOMXOR
:
894 op
= LLVMAtomicRMWBinOpXor
;
896 case TGSI_OPCODE_ATOMUMIN
:
897 op
= LLVMAtomicRMWBinOpUMin
;
899 case TGSI_OPCODE_ATOMUMAX
:
900 op
= LLVMAtomicRMWBinOpUMax
;
902 case TGSI_OPCODE_ATOMIMIN
:
903 op
= LLVMAtomicRMWBinOpMin
;
905 case TGSI_OPCODE_ATOMIMAX
:
906 op
= LLVMAtomicRMWBinOpMax
;
909 unreachable("unknown atomic opcode");
912 result
= LLVMBuildAtomicRMW(builder
, op
, ptr
, arg
,
913 LLVMAtomicOrderingSequentiallyConsistent
,
916 emit_data
->output
[emit_data
->chan
] = LLVMBuildBitCast(builder
, result
, emit_data
->dst_type
, "");
919 static void atomic_emit(
920 const struct lp_build_tgsi_action
*action
,
921 struct lp_build_tgsi_context
*bld_base
,
922 struct lp_build_emit_data
*emit_data
)
924 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
925 LLVMBuilderRef builder
= ctx
->ac
.builder
;
926 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
929 if (inst
->Src
[0].Register
.File
== TGSI_FILE_MEMORY
) {
930 atomic_emit_memory(ctx
, emit_data
);
934 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
||
935 inst
->Memory
.Texture
== TGSI_TEXTURE_BUFFER
) {
936 char intrinsic_name
[40];
937 snprintf(intrinsic_name
, sizeof(intrinsic_name
),
938 "llvm.amdgcn.buffer.atomic.%s", action
->intr_name
);
939 tmp
= lp_build_intrinsic(
940 builder
, intrinsic_name
, ctx
->i32
,
941 emit_data
->args
, emit_data
->arg_count
, 0);
942 emit_data
->output
[emit_data
->chan
] = ac_to_float(&ctx
->ac
, tmp
);
944 unsigned num_data
= inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
? 2 : 1;
945 struct ac_image_args args
= {};
947 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
) {
948 args
.opcode
= ac_image_atomic_cmpswap
;
950 args
.opcode
= ac_image_atomic
;
951 switch (inst
->Instruction
.Opcode
) {
952 case TGSI_OPCODE_ATOMXCHG
: args
.atomic
= ac_atomic_swap
; break;
953 case TGSI_OPCODE_ATOMUADD
: args
.atomic
= ac_atomic_add
; break;
954 case TGSI_OPCODE_ATOMAND
: args
.atomic
= ac_atomic_and
; break;
955 case TGSI_OPCODE_ATOMOR
: args
.atomic
= ac_atomic_or
; break;
956 case TGSI_OPCODE_ATOMXOR
: args
.atomic
= ac_atomic_xor
; break;
957 case TGSI_OPCODE_ATOMUMIN
: args
.atomic
= ac_atomic_umin
; break;
958 case TGSI_OPCODE_ATOMUMAX
: args
.atomic
= ac_atomic_umax
; break;
959 case TGSI_OPCODE_ATOMIMIN
: args
.atomic
= ac_atomic_smin
; break;
960 case TGSI_OPCODE_ATOMIMAX
: args
.atomic
= ac_atomic_smax
; break;
961 default: unreachable("unhandled image atomic");
965 for (unsigned i
= 0; i
< num_data
; ++i
)
966 args
.data
[i
] = emit_data
->args
[i
];
968 args
.resource
= emit_data
->args
[num_data
];
969 memcpy(args
.coords
, &emit_data
->args
[num_data
+ 1], sizeof(args
.coords
));
970 args
.dim
= ac_image_dim_from_tgsi_target(ctx
->screen
, inst
->Memory
.Texture
);
972 emit_data
->output
[emit_data
->chan
] =
973 ac_to_float(&ctx
->ac
, ac_build_image_opcode(&ctx
->ac
, &args
));
977 static void set_tex_fetch_args(struct si_shader_context
*ctx
,
978 struct lp_build_emit_data
*emit_data
,
979 struct ac_image_args
*args
,
982 args
->dim
= ac_texture_dim_from_tgsi_target(ctx
->screen
, target
);
983 args
->unorm
= target
== TGSI_TEXTURE_RECT
||
984 target
== TGSI_TEXTURE_SHADOWRECT
;
986 /* Ugly, but we seem to have no other choice right now. */
987 STATIC_ASSERT(sizeof(*args
) <= sizeof(emit_data
->args
));
988 memcpy(emit_data
->args
, args
, sizeof(*args
));
991 static LLVMValueRef
fix_resinfo(struct si_shader_context
*ctx
,
992 unsigned target
, LLVMValueRef out
)
994 LLVMBuilderRef builder
= ctx
->ac
.builder
;
996 /* 1D textures are allocated and used as 2D on GFX9. */
997 if (ctx
->screen
->info
.chip_class
>= GFX9
&&
998 (target
== TGSI_TEXTURE_1D_ARRAY
||
999 target
== TGSI_TEXTURE_SHADOW1D_ARRAY
)) {
1000 LLVMValueRef layers
=
1001 LLVMBuildExtractElement(builder
, out
,
1002 LLVMConstInt(ctx
->i32
, 2, 0), "");
1003 out
= LLVMBuildInsertElement(builder
, out
, layers
,
1007 /* Divide the number of layers by 6 to get the number of cubes. */
1008 if (target
== TGSI_TEXTURE_CUBE_ARRAY
||
1009 target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
1010 LLVMValueRef imm2
= LLVMConstInt(ctx
->i32
, 2, 0);
1012 LLVMValueRef z
= LLVMBuildExtractElement(builder
, out
, imm2
, "");
1013 z
= LLVMBuildSDiv(builder
, z
, LLVMConstInt(ctx
->i32
, 6, 0), "");
1015 out
= LLVMBuildInsertElement(builder
, out
, z
, imm2
, "");
1020 static void resq_fetch_args(
1021 struct lp_build_tgsi_context
* bld_base
,
1022 struct lp_build_emit_data
* emit_data
)
1024 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1025 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
1026 const struct tgsi_full_src_register
*reg
= &inst
->Src
[0];
1028 emit_data
->dst_type
= ctx
->v4i32
;
1030 if (reg
->Register
.File
== TGSI_FILE_BUFFER
) {
1031 emit_data
->args
[0] = shader_buffer_fetch_rsrc(ctx
, reg
, false);
1032 emit_data
->arg_count
= 1;
1033 } else if (inst
->Memory
.Texture
== TGSI_TEXTURE_BUFFER
) {
1034 image_fetch_rsrc(bld_base
, reg
, false, inst
->Memory
.Texture
,
1035 &emit_data
->args
[0]);
1036 emit_data
->arg_count
= 1;
1038 struct ac_image_args args
= {};
1039 unsigned image_target
;
1041 if (inst
->Memory
.Texture
== TGSI_TEXTURE_3D
)
1042 image_target
= TGSI_TEXTURE_2D_ARRAY
;
1044 image_target
= inst
->Memory
.Texture
;
1046 image_fetch_rsrc(bld_base
, reg
, false, inst
->Memory
.Texture
,
1048 args
.lod
= ctx
->i32_0
;
1050 set_tex_fetch_args(ctx
, emit_data
, &args
, image_target
);
1054 static void resq_emit(
1055 const struct lp_build_tgsi_action
*action
,
1056 struct lp_build_tgsi_context
*bld_base
,
1057 struct lp_build_emit_data
*emit_data
)
1059 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1060 LLVMBuilderRef builder
= ctx
->ac
.builder
;
1061 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
1064 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
) {
1065 out
= LLVMBuildExtractElement(builder
, emit_data
->args
[0],
1066 LLVMConstInt(ctx
->i32
, 2, 0), "");
1067 } else if (inst
->Memory
.Texture
== TGSI_TEXTURE_BUFFER
) {
1068 out
= get_buffer_size(bld_base
, emit_data
->args
[0]);
1070 struct ac_image_args args
;
1072 memcpy(&args
, emit_data
->args
, sizeof(args
)); /* ugly */
1073 args
.opcode
= ac_image_get_resinfo
;
1074 out
= ac_build_image_opcode(&ctx
->ac
, &args
);
1076 out
= fix_resinfo(ctx
, inst
->Memory
.Texture
, out
);
1079 emit_data
->output
[emit_data
->chan
] = out
;
1083 * Load an image view, fmask view. or sampler state descriptor.
1085 LLVMValueRef
si_load_sampler_desc(struct si_shader_context
*ctx
,
1086 LLVMValueRef list
, LLVMValueRef index
,
1087 enum ac_descriptor_type type
)
1089 LLVMBuilderRef builder
= ctx
->ac
.builder
;
1093 /* The image is at [0:7]. */
1094 index
= LLVMBuildMul(builder
, index
, LLVMConstInt(ctx
->i32
, 2, 0), "");
1096 case AC_DESC_BUFFER
:
1097 /* The buffer is in [4:7]. */
1098 index
= LLVMBuildMul(builder
, index
, LLVMConstInt(ctx
->i32
, 4, 0), "");
1099 index
= LLVMBuildAdd(builder
, index
, ctx
->i32_1
, "");
1100 list
= LLVMBuildPointerCast(builder
, list
,
1101 ac_array_in_const32_addr_space(ctx
->v4i32
), "");
1104 /* The FMASK is at [8:15]. */
1105 index
= LLVMBuildMul(builder
, index
, LLVMConstInt(ctx
->i32
, 2, 0), "");
1106 index
= LLVMBuildAdd(builder
, index
, ctx
->i32_1
, "");
1108 case AC_DESC_SAMPLER
:
1109 /* The sampler state is at [12:15]. */
1110 index
= LLVMBuildMul(builder
, index
, LLVMConstInt(ctx
->i32
, 4, 0), "");
1111 index
= LLVMBuildAdd(builder
, index
, LLVMConstInt(ctx
->i32
, 3, 0), "");
1112 list
= LLVMBuildPointerCast(builder
, list
,
1113 ac_array_in_const32_addr_space(ctx
->v4i32
), "");
1117 return ac_build_load_to_sgpr(&ctx
->ac
, list
, index
);
1120 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
1123 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
1124 * filtering manually. The driver sets img7 to a mask clearing
1125 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
1126 * s_and_b32 samp0, samp0, img7
1129 * The ANISO_OVERRIDE sampler field enables this fix in TA.
1131 static LLVMValueRef
sici_fix_sampler_aniso(struct si_shader_context
*ctx
,
1132 LLVMValueRef res
, LLVMValueRef samp
)
1134 LLVMValueRef img7
, samp0
;
1136 if (ctx
->screen
->info
.chip_class
>= VI
)
1139 img7
= LLVMBuildExtractElement(ctx
->ac
.builder
, res
,
1140 LLVMConstInt(ctx
->i32
, 7, 0), "");
1141 samp0
= LLVMBuildExtractElement(ctx
->ac
.builder
, samp
,
1143 samp0
= LLVMBuildAnd(ctx
->ac
.builder
, samp0
, img7
, "");
1144 return LLVMBuildInsertElement(ctx
->ac
.builder
, samp
, samp0
,
1148 static void tex_fetch_ptrs(
1149 struct lp_build_tgsi_context
*bld_base
,
1150 struct lp_build_emit_data
*emit_data
,
1151 LLVMValueRef
*res_ptr
, LLVMValueRef
*samp_ptr
, LLVMValueRef
*fmask_ptr
)
1153 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1154 LLVMValueRef list
= LLVMGetParam(ctx
->main_fn
, ctx
->param_samplers_and_images
);
1155 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
1156 const struct tgsi_full_src_register
*reg
;
1157 unsigned target
= inst
->Texture
.Texture
;
1158 unsigned sampler_src
;
1161 sampler_src
= emit_data
->inst
->Instruction
.NumSrcRegs
- 1;
1162 reg
= &emit_data
->inst
->Src
[sampler_src
];
1164 if (reg
->Register
.Indirect
) {
1165 index
= si_get_bounded_indirect_index(ctx
,
1167 reg
->Register
.Index
,
1169 index
= LLVMBuildAdd(ctx
->ac
.builder
, index
,
1170 LLVMConstInt(ctx
->i32
, SI_NUM_IMAGES
/ 2, 0), "");
1172 index
= LLVMConstInt(ctx
->i32
,
1173 si_get_sampler_slot(reg
->Register
.Index
), 0);
1176 if (reg
->Register
.File
!= TGSI_FILE_SAMPLER
) {
1177 /* Bindless descriptors are accessible from a different pair of
1178 * user SGPR indices.
1180 list
= LLVMGetParam(ctx
->main_fn
,
1181 ctx
->param_bindless_samplers_and_images
);
1182 index
= lp_build_emit_fetch_src(bld_base
, reg
,
1183 TGSI_TYPE_UNSIGNED
, 0);
1186 if (target
== TGSI_TEXTURE_BUFFER
)
1187 *res_ptr
= si_load_sampler_desc(ctx
, list
, index
, AC_DESC_BUFFER
);
1189 *res_ptr
= si_load_sampler_desc(ctx
, list
, index
, AC_DESC_IMAGE
);
1196 if (target
== TGSI_TEXTURE_2D_MSAA
||
1197 target
== TGSI_TEXTURE_2D_ARRAY_MSAA
) {
1199 *fmask_ptr
= si_load_sampler_desc(ctx
, list
, index
,
1201 } else if (target
!= TGSI_TEXTURE_BUFFER
) {
1203 *samp_ptr
= si_load_sampler_desc(ctx
, list
, index
,
1205 *samp_ptr
= sici_fix_sampler_aniso(ctx
, *res_ptr
, *samp_ptr
);
1210 static void txq_fetch_args(
1211 struct lp_build_tgsi_context
*bld_base
,
1212 struct lp_build_emit_data
*emit_data
)
1214 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1215 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
1216 unsigned target
= inst
->Texture
.Texture
;
1217 struct ac_image_args args
= {};
1219 tex_fetch_ptrs(bld_base
, emit_data
, &args
.resource
, NULL
, NULL
);
1221 if (target
== TGSI_TEXTURE_BUFFER
) {
1222 /* Read the size from the buffer descriptor directly. */
1223 emit_data
->args
[0] = get_buffer_size(bld_base
, args
.resource
);
1227 /* Textures - set the mip level. */
1228 args
.lod
= lp_build_emit_fetch(bld_base
, inst
, 0, TGSI_CHAN_X
);
1231 set_tex_fetch_args(ctx
, emit_data
, &args
, target
);
1234 static void txq_emit(const struct lp_build_tgsi_action
*action
,
1235 struct lp_build_tgsi_context
*bld_base
,
1236 struct lp_build_emit_data
*emit_data
)
1238 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1239 struct ac_image_args args
;
1240 unsigned target
= emit_data
->inst
->Texture
.Texture
;
1242 if (target
== TGSI_TEXTURE_BUFFER
) {
1243 /* Just return the buffer size. */
1244 emit_data
->output
[emit_data
->chan
] = emit_data
->args
[0];
1248 memcpy(&args
, emit_data
->args
, sizeof(args
)); /* ugly */
1250 args
.opcode
= ac_image_get_resinfo
;
1251 LLVMValueRef result
= ac_build_image_opcode(&ctx
->ac
, &args
);
1253 emit_data
->output
[emit_data
->chan
] = fix_resinfo(ctx
, target
, result
);
1256 static void tex_fetch_args(
1257 struct lp_build_tgsi_context
*bld_base
,
1258 struct lp_build_emit_data
*emit_data
)
1260 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1261 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
1262 unsigned opcode
= inst
->Instruction
.Opcode
;
1263 unsigned target
= inst
->Texture
.Texture
;
1264 struct ac_image_args args
= {};
1265 int ref_pos
= tgsi_util_get_shadow_ref_src_index(target
);
1267 bool has_offset
= inst
->Texture
.NumOffsets
> 0;
1268 LLVMValueRef fmask_ptr
= NULL
;
1270 tex_fetch_ptrs(bld_base
, emit_data
, &args
.resource
, &args
.sampler
, &fmask_ptr
);
1272 if (target
== TGSI_TEXTURE_BUFFER
) {
1273 emit_data
->dst_type
= ctx
->v4f32
;
1274 emit_data
->args
[0] = args
.resource
;
1275 emit_data
->args
[1] = ctx
->i32_0
;
1276 emit_data
->args
[2] = lp_build_emit_fetch(bld_base
, emit_data
->inst
, 0, TGSI_CHAN_X
);
1277 emit_data
->arg_count
= 3;
1281 /* Fetch and project texture coordinates */
1282 args
.coords
[3] = lp_build_emit_fetch(bld_base
, emit_data
->inst
, 0, TGSI_CHAN_W
);
1283 for (chan
= 0; chan
< 3; chan
++) {
1284 args
.coords
[chan
] = lp_build_emit_fetch(bld_base
,
1287 if (opcode
== TGSI_OPCODE_TXP
)
1288 args
.coords
[chan
] = lp_build_emit_llvm_binary(
1289 bld_base
, TGSI_OPCODE_DIV
,
1290 args
.coords
[chan
], args
.coords
[3]);
1293 if (opcode
== TGSI_OPCODE_TXP
)
1294 args
.coords
[3] = ctx
->ac
.f32_1
;
1298 opcode
!= TGSI_OPCODE_TXF
&&
1299 opcode
!= TGSI_OPCODE_TXF_LZ
) {
1300 /* The offsets are six-bit signed integers packed like this:
1301 * X=[5:0], Y=[13:8], and Z=[21:16].
1303 LLVMValueRef offset
[3], pack
;
1305 assert(inst
->Texture
.NumOffsets
== 1);
1307 for (chan
= 0; chan
< 3; chan
++) {
1308 offset
[chan
] = lp_build_emit_fetch_texoffset(bld_base
,
1309 emit_data
->inst
, 0, chan
);
1310 offset
[chan
] = LLVMBuildAnd(ctx
->ac
.builder
, offset
[chan
],
1311 LLVMConstInt(ctx
->i32
, 0x3f, 0), "");
1313 offset
[chan
] = LLVMBuildShl(ctx
->ac
.builder
, offset
[chan
],
1314 LLVMConstInt(ctx
->i32
, chan
*8, 0), "");
1317 pack
= LLVMBuildOr(ctx
->ac
.builder
, offset
[0], offset
[1], "");
1318 pack
= LLVMBuildOr(ctx
->ac
.builder
, pack
, offset
[2], "");
1322 /* Pack LOD bias value */
1323 if (opcode
== TGSI_OPCODE_TXB
)
1324 args
.bias
= args
.coords
[3];
1325 if (opcode
== TGSI_OPCODE_TXB2
)
1326 args
.bias
= lp_build_emit_fetch(bld_base
, inst
, 1, TGSI_CHAN_X
);
1328 /* Pack depth comparison value */
1329 if (tgsi_is_shadow_target(target
) && opcode
!= TGSI_OPCODE_LODQ
) {
1332 if (target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
1333 z
= lp_build_emit_fetch(bld_base
, inst
, 1, TGSI_CHAN_X
);
1335 assert(ref_pos
>= 0);
1336 z
= args
.coords
[ref_pos
];
1339 /* Section 8.23.1 (Depth Texture Comparison Mode) of the
1340 * OpenGL 4.5 spec says:
1342 * "If the texture’s internal format indicates a fixed-point
1343 * depth texture, then D_t and D_ref are clamped to the
1344 * range [0, 1]; otherwise no clamping is performed."
1346 * TC-compatible HTILE promotes Z16 and Z24 to Z32_FLOAT,
1347 * so the depth comparison value isn't clamped for Z16 and
1348 * Z24 anymore. Do it manually here.
1350 if (ctx
->screen
->info
.chip_class
>= VI
) {
1351 LLVMValueRef upgraded
;
1352 LLVMValueRef clamped
;
1353 upgraded
= LLVMBuildExtractElement(ctx
->ac
.builder
, args
.sampler
,
1354 LLVMConstInt(ctx
->i32
, 3, false), "");
1355 upgraded
= LLVMBuildLShr(ctx
->ac
.builder
, upgraded
,
1356 LLVMConstInt(ctx
->i32
, 29, false), "");
1357 upgraded
= LLVMBuildTrunc(ctx
->ac
.builder
, upgraded
, ctx
->i1
, "");
1358 clamped
= ac_build_clamp(&ctx
->ac
, z
);
1359 z
= LLVMBuildSelect(ctx
->ac
.builder
, upgraded
, clamped
, z
, "");
1365 /* Pack user derivatives */
1366 if (opcode
== TGSI_OPCODE_TXD
) {
1367 int param
, num_src_deriv_channels
, num_dst_deriv_channels
;
1370 case TGSI_TEXTURE_3D
:
1371 num_src_deriv_channels
= 3;
1372 num_dst_deriv_channels
= 3;
1374 case TGSI_TEXTURE_2D
:
1375 case TGSI_TEXTURE_SHADOW2D
:
1376 case TGSI_TEXTURE_RECT
:
1377 case TGSI_TEXTURE_SHADOWRECT
:
1378 case TGSI_TEXTURE_2D_ARRAY
:
1379 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
1380 num_src_deriv_channels
= 2;
1381 num_dst_deriv_channels
= 2;
1383 case TGSI_TEXTURE_CUBE
:
1384 case TGSI_TEXTURE_SHADOWCUBE
:
1385 case TGSI_TEXTURE_CUBE_ARRAY
:
1386 case TGSI_TEXTURE_SHADOWCUBE_ARRAY
:
1387 /* Cube derivatives will be converted to 2D. */
1388 num_src_deriv_channels
= 3;
1389 num_dst_deriv_channels
= 3;
1391 case TGSI_TEXTURE_1D
:
1392 case TGSI_TEXTURE_SHADOW1D
:
1393 case TGSI_TEXTURE_1D_ARRAY
:
1394 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
1395 num_src_deriv_channels
= 1;
1397 /* 1D textures are allocated and used as 2D on GFX9. */
1398 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
1399 num_dst_deriv_channels
= 2;
1401 num_dst_deriv_channels
= 1;
1405 unreachable("invalid target");
1408 for (param
= 0; param
< 2; param
++) {
1409 for (chan
= 0; chan
< num_src_deriv_channels
; chan
++)
1410 args
.derivs
[param
* num_dst_deriv_channels
+ chan
] =
1411 lp_build_emit_fetch(bld_base
, inst
, param
+1, chan
);
1413 /* Fill in the rest with zeros. */
1414 for (chan
= num_src_deriv_channels
;
1415 chan
< num_dst_deriv_channels
; chan
++)
1416 args
.derivs
[param
* num_dst_deriv_channels
+ chan
] =
1421 if (target
== TGSI_TEXTURE_CUBE
||
1422 target
== TGSI_TEXTURE_CUBE_ARRAY
||
1423 target
== TGSI_TEXTURE_SHADOWCUBE
||
1424 target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
1425 ac_prepare_cube_coords(&ctx
->ac
,
1426 opcode
== TGSI_OPCODE_TXD
,
1427 target
== TGSI_TEXTURE_CUBE_ARRAY
||
1428 target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
,
1429 opcode
== TGSI_OPCODE_LODQ
,
1430 args
.coords
, args
.derivs
);
1431 } else if (tgsi_is_array_sampler(target
) &&
1432 opcode
!= TGSI_OPCODE_TXF
&&
1433 opcode
!= TGSI_OPCODE_TXF_LZ
&&
1434 ctx
->screen
->info
.chip_class
<= VI
) {
1435 unsigned array_coord
= target
== TGSI_TEXTURE_1D_ARRAY
? 1 : 2;
1436 args
.coords
[array_coord
] =
1437 ac_build_intrinsic(&ctx
->ac
, "llvm.rint.f32", ctx
->f32
,
1438 &args
.coords
[array_coord
], 1, 0);
1441 /* 1D textures are allocated and used as 2D on GFX9. */
1442 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
1443 LLVMValueRef filler
;
1445 /* Use 0.5, so that we don't sample the border color. */
1446 if (opcode
== TGSI_OPCODE_TXF
||
1447 opcode
== TGSI_OPCODE_TXF_LZ
)
1448 filler
= ctx
->i32_0
;
1450 filler
= LLVMConstReal(ctx
->f32
, 0.5);
1452 if (target
== TGSI_TEXTURE_1D
||
1453 target
== TGSI_TEXTURE_SHADOW1D
) {
1454 args
.coords
[1] = filler
;
1455 } else if (target
== TGSI_TEXTURE_1D_ARRAY
||
1456 target
== TGSI_TEXTURE_SHADOW1D_ARRAY
) {
1457 args
.coords
[2] = args
.coords
[1];
1458 args
.coords
[1] = filler
;
1462 /* Pack LOD or sample index */
1463 if (opcode
== TGSI_OPCODE_TXL
)
1464 args
.lod
= args
.coords
[3];
1465 else if (opcode
== TGSI_OPCODE_TXL2
)
1466 args
.lod
= lp_build_emit_fetch(bld_base
, inst
, 1, TGSI_CHAN_X
);
1467 else if (opcode
== TGSI_OPCODE_TXF
) {
1468 if (target
== TGSI_TEXTURE_2D_MSAA
) {
1469 /* No LOD, but move sample index into the right place. */
1470 args
.coords
[2] = args
.coords
[3];
1471 } else if (target
!= TGSI_TEXTURE_2D_ARRAY_MSAA
) {
1472 args
.lod
= args
.coords
[3];
1476 if (target
== TGSI_TEXTURE_2D_MSAA
||
1477 target
== TGSI_TEXTURE_2D_ARRAY_MSAA
) {
1478 ac_apply_fmask_to_sample(&ctx
->ac
, fmask_ptr
, args
.coords
,
1479 target
== TGSI_TEXTURE_2D_ARRAY_MSAA
);
1482 if (opcode
== TGSI_OPCODE_TXF
||
1483 opcode
== TGSI_OPCODE_TXF_LZ
) {
1484 /* add tex offsets */
1485 if (inst
->Texture
.NumOffsets
) {
1486 struct lp_build_context
*uint_bld
= &bld_base
->uint_bld
;
1487 const struct tgsi_texture_offset
*off
= inst
->TexOffsets
;
1489 assert(inst
->Texture
.NumOffsets
== 1);
1492 case TGSI_TEXTURE_3D
:
1493 args
.coords
[2] = lp_build_add(uint_bld
, args
.coords
[2],
1494 ctx
->imms
[off
->Index
* TGSI_NUM_CHANNELS
+ off
->SwizzleZ
]);
1496 case TGSI_TEXTURE_2D
:
1497 case TGSI_TEXTURE_SHADOW2D
:
1498 case TGSI_TEXTURE_RECT
:
1499 case TGSI_TEXTURE_SHADOWRECT
:
1500 case TGSI_TEXTURE_2D_ARRAY
:
1501 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
1503 lp_build_add(uint_bld
, args
.coords
[1],
1504 ctx
->imms
[off
->Index
* TGSI_NUM_CHANNELS
+ off
->SwizzleY
]);
1506 case TGSI_TEXTURE_1D
:
1507 case TGSI_TEXTURE_SHADOW1D
:
1508 case TGSI_TEXTURE_1D_ARRAY
:
1509 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
1511 lp_build_add(uint_bld
, args
.coords
[0],
1512 ctx
->imms
[off
->Index
* TGSI_NUM_CHANNELS
+ off
->SwizzleX
]);
1514 /* texture offsets do not apply to other texture targets */
1521 if (opcode
== TGSI_OPCODE_TG4
) {
1522 unsigned gather_comp
= 0;
1524 /* DMASK was repurposed for GATHER4. 4 components are always
1525 * returned and DMASK works like a swizzle - it selects
1526 * the component to fetch. The only valid DMASK values are
1527 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
1528 * (red,red,red,red) etc.) The ISA document doesn't mention
1532 /* Get the component index from src1.x for Gather4. */
1533 if (!tgsi_is_shadow_target(target
)) {
1534 LLVMValueRef comp_imm
;
1535 struct tgsi_src_register src1
= inst
->Src
[1].Register
;
1537 assert(src1
.File
== TGSI_FILE_IMMEDIATE
);
1539 comp_imm
= ctx
->imms
[src1
.Index
* TGSI_NUM_CHANNELS
+ src1
.SwizzleX
];
1540 gather_comp
= LLVMConstIntGetZExtValue(comp_imm
);
1541 gather_comp
= CLAMP(gather_comp
, 0, 3);
1544 args
.dmask
= 1 << gather_comp
;
1547 set_tex_fetch_args(ctx
, emit_data
, &args
, target
);
1550 /* Gather4 should follow the same rules as bilinear filtering, but the hardware
1551 * incorrectly forces nearest filtering if the texture format is integer.
1552 * The only effect it has on Gather4, which always returns 4 texels for
1553 * bilinear filtering, is that the final coordinates are off by 0.5 of
1556 * The workaround is to subtract 0.5 from the unnormalized coordinates,
1557 * or (0.5 / size) from the normalized coordinates.
1559 * However, cube textures with 8_8_8_8 data formats require a different
1560 * workaround of overriding the num format to USCALED/SSCALED. This would lose
1561 * precision in 32-bit data formats, so it needs to be applied dynamically at
1562 * runtime. In this case, return an i1 value that indicates whether the
1563 * descriptor was overridden (and hence a fixup of the sampler result is needed).
1566 si_lower_gather4_integer(struct si_shader_context
*ctx
,
1567 struct ac_image_args
*args
,
1569 enum tgsi_return_type return_type
)
1571 LLVMBuilderRef builder
= ctx
->ac
.builder
;
1572 LLVMValueRef wa_8888
= NULL
;
1573 LLVMValueRef half_texel
[2];
1575 assert(return_type
== TGSI_RETURN_TYPE_SINT
||
1576 return_type
== TGSI_RETURN_TYPE_UINT
);
1578 if (target
== TGSI_TEXTURE_CUBE
||
1579 target
== TGSI_TEXTURE_CUBE_ARRAY
) {
1580 LLVMValueRef formats
;
1581 LLVMValueRef data_format
;
1582 LLVMValueRef wa_formats
;
1584 formats
= LLVMBuildExtractElement(builder
, args
->resource
, ctx
->i32_1
, "");
1586 data_format
= LLVMBuildLShr(builder
, formats
,
1587 LLVMConstInt(ctx
->i32
, 20, false), "");
1588 data_format
= LLVMBuildAnd(builder
, data_format
,
1589 LLVMConstInt(ctx
->i32
, (1u << 6) - 1, false), "");
1590 wa_8888
= LLVMBuildICmp(
1591 builder
, LLVMIntEQ
, data_format
,
1592 LLVMConstInt(ctx
->i32
, V_008F14_IMG_DATA_FORMAT_8_8_8_8
, false),
1595 uint32_t wa_num_format
=
1596 return_type
== TGSI_RETURN_TYPE_UINT
?
1597 S_008F14_NUM_FORMAT_GFX6(V_008F14_IMG_NUM_FORMAT_USCALED
) :
1598 S_008F14_NUM_FORMAT_GFX6(V_008F14_IMG_NUM_FORMAT_SSCALED
);
1599 wa_formats
= LLVMBuildAnd(builder
, formats
,
1600 LLVMConstInt(ctx
->i32
, C_008F14_NUM_FORMAT_GFX6
, false),
1602 wa_formats
= LLVMBuildOr(builder
, wa_formats
,
1603 LLVMConstInt(ctx
->i32
, wa_num_format
, false), "");
1605 formats
= LLVMBuildSelect(builder
, wa_8888
, wa_formats
, formats
, "");
1606 args
->resource
= LLVMBuildInsertElement(
1607 builder
, args
->resource
, formats
, ctx
->i32_1
, "");
1610 if (target
== TGSI_TEXTURE_RECT
||
1611 target
== TGSI_TEXTURE_SHADOWRECT
) {
1613 half_texel
[0] = half_texel
[1] = LLVMConstReal(ctx
->f32
, -0.5);
1615 struct tgsi_full_instruction txq_inst
= {};
1616 struct ac_image_args txq_args
= {};
1617 struct lp_build_emit_data txq_emit_data
= {};
1618 struct lp_build_if_state if_ctx
;
1621 /* Skip the texture size query entirely if we don't need it. */
1622 lp_build_if(&if_ctx
, &ctx
->gallivm
, LLVMBuildNot(builder
, wa_8888
, ""));
1625 /* Query the texture size. */
1626 txq_inst
.Texture
.Texture
= target
;
1627 txq_emit_data
.inst
= &txq_inst
;
1628 txq_emit_data
.dst_type
= ctx
->v4i32
;
1629 txq_args
.resource
= args
->resource
;
1630 txq_args
.sampler
= args
->sampler
;
1631 txq_args
.lod
= ctx
->ac
.i32_0
;
1632 txq_args
.dmask
= 0xf;
1633 set_tex_fetch_args(ctx
, &txq_emit_data
, &txq_args
, target
);
1634 txq_emit(NULL
, &ctx
->bld_base
, &txq_emit_data
);
1636 /* Compute -0.5 / size. */
1637 for (unsigned c
= 0; c
< 2; c
++) {
1639 LLVMBuildExtractElement(builder
, txq_emit_data
.output
[0],
1640 LLVMConstInt(ctx
->i32
, c
, 0), "");
1641 half_texel
[c
] = LLVMBuildUIToFP(builder
, half_texel
[c
], ctx
->f32
, "");
1643 lp_build_emit_llvm_unary(&ctx
->bld_base
,
1644 TGSI_OPCODE_RCP
, half_texel
[c
]);
1645 half_texel
[c
] = LLVMBuildFMul(builder
, half_texel
[c
],
1646 LLVMConstReal(ctx
->f32
, -0.5), "");
1650 lp_build_endif(&if_ctx
);
1652 LLVMBasicBlockRef bb
[2] = { if_ctx
.true_block
, if_ctx
.entry_block
};
1654 for (unsigned c
= 0; c
< 2; c
++) {
1655 LLVMValueRef values
[2] = { half_texel
[c
], ctx
->ac
.f32_0
};
1656 half_texel
[c
] = ac_build_phi(&ctx
->ac
, ctx
->f32
, 2,
1662 for (unsigned c
= 0; c
< 2; c
++) {
1664 tmp
= ac_to_float(&ctx
->ac
, args
->coords
[c
]);
1665 tmp
= LLVMBuildFAdd(builder
, tmp
, half_texel
[c
], "");
1666 args
->coords
[c
] = ac_to_integer(&ctx
->ac
, tmp
);
1672 /* The second half of the cube texture 8_8_8_8 integer workaround: adjust the
1673 * result after the gather operation.
1676 si_fix_gather4_integer_result(struct si_shader_context
*ctx
,
1677 LLVMValueRef result
,
1678 enum tgsi_return_type return_type
,
1681 LLVMBuilderRef builder
= ctx
->ac
.builder
;
1683 assert(return_type
== TGSI_RETURN_TYPE_SINT
||
1684 return_type
== TGSI_RETURN_TYPE_UINT
);
1686 for (unsigned chan
= 0; chan
< 4; ++chan
) {
1687 LLVMValueRef chanv
= LLVMConstInt(ctx
->i32
, chan
, false);
1689 LLVMValueRef wa_value
;
1691 value
= LLVMBuildExtractElement(builder
, result
, chanv
, "");
1693 if (return_type
== TGSI_RETURN_TYPE_UINT
)
1694 wa_value
= LLVMBuildFPToUI(builder
, value
, ctx
->i32
, "");
1696 wa_value
= LLVMBuildFPToSI(builder
, value
, ctx
->i32
, "");
1697 wa_value
= ac_to_float(&ctx
->ac
, wa_value
);
1698 value
= LLVMBuildSelect(builder
, wa
, wa_value
, value
, "");
1700 result
= LLVMBuildInsertElement(builder
, result
, value
, chanv
, "");
1706 static void build_tex_intrinsic(const struct lp_build_tgsi_action
*action
,
1707 struct lp_build_tgsi_context
*bld_base
,
1708 struct lp_build_emit_data
*emit_data
)
1710 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1711 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
1712 struct ac_image_args args
;
1713 unsigned opcode
= inst
->Instruction
.Opcode
;
1714 unsigned target
= inst
->Texture
.Texture
;
1716 if (target
== TGSI_TEXTURE_BUFFER
) {
1717 unsigned num_channels
=
1718 util_last_bit(inst
->Dst
[0].Register
.WriteMask
);
1719 LLVMValueRef result
=
1720 ac_build_buffer_load_format(&ctx
->ac
,
1724 num_channels
, false, true);
1725 emit_data
->output
[emit_data
->chan
] =
1726 ac_build_expand_to_vec4(&ctx
->ac
, result
, num_channels
);
1730 memcpy(&args
, emit_data
->args
, sizeof(args
)); /* ugly */
1732 args
.opcode
= ac_image_sample
;
1735 case TGSI_OPCODE_TXF
:
1736 case TGSI_OPCODE_TXF_LZ
:
1737 args
.opcode
= opcode
== TGSI_OPCODE_TXF_LZ
||
1738 target
== TGSI_TEXTURE_2D_MSAA
||
1739 target
== TGSI_TEXTURE_2D_ARRAY_MSAA
?
1740 ac_image_load
: ac_image_load_mip
;
1742 case TGSI_OPCODE_LODQ
:
1743 args
.opcode
= ac_image_get_lod
;
1745 case TGSI_OPCODE_TEX
:
1746 case TGSI_OPCODE_TEX2
:
1747 case TGSI_OPCODE_TXP
:
1748 if (ctx
->type
!= PIPE_SHADER_FRAGMENT
)
1749 args
.level_zero
= true;
1751 case TGSI_OPCODE_TEX_LZ
:
1752 args
.level_zero
= true;
1754 case TGSI_OPCODE_TXB
:
1755 case TGSI_OPCODE_TXB2
:
1756 assert(ctx
->type
== PIPE_SHADER_FRAGMENT
);
1758 case TGSI_OPCODE_TXL
:
1759 case TGSI_OPCODE_TXL2
:
1761 case TGSI_OPCODE_TXD
:
1763 case TGSI_OPCODE_TG4
:
1764 args
.opcode
= ac_image_gather4
;
1765 args
.level_zero
= true;
1772 /* The hardware needs special lowering for Gather4 with integer formats. */
1773 LLVMValueRef gather4_int_result_workaround
= NULL
;
1775 if (ctx
->screen
->info
.chip_class
<= VI
&&
1776 opcode
== TGSI_OPCODE_TG4
) {
1777 assert(inst
->Texture
.ReturnType
!= TGSI_RETURN_TYPE_UNKNOWN
);
1779 if (inst
->Texture
.ReturnType
== TGSI_RETURN_TYPE_SINT
||
1780 inst
->Texture
.ReturnType
== TGSI_RETURN_TYPE_UINT
) {
1781 gather4_int_result_workaround
=
1782 si_lower_gather4_integer(ctx
, &args
, target
,
1783 inst
->Texture
.ReturnType
);
1787 args
.attributes
= AC_FUNC_ATTR_READNONE
;
1788 LLVMValueRef result
= ac_build_image_opcode(&ctx
->ac
, &args
);
1790 if (gather4_int_result_workaround
) {
1791 result
= si_fix_gather4_integer_result(ctx
, result
,
1792 inst
->Texture
.ReturnType
,
1793 gather4_int_result_workaround
);
1796 emit_data
->output
[emit_data
->chan
] = result
;
1799 static void si_llvm_emit_txqs(
1800 const struct lp_build_tgsi_action
*action
,
1801 struct lp_build_tgsi_context
*bld_base
,
1802 struct lp_build_emit_data
*emit_data
)
1804 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1805 LLVMValueRef res
, samples
;
1806 LLVMValueRef res_ptr
, samp_ptr
, fmask_ptr
= NULL
;
1808 tex_fetch_ptrs(bld_base
, emit_data
, &res_ptr
, &samp_ptr
, &fmask_ptr
);
1810 /* Read the samples from the descriptor directly. */
1811 res
= LLVMBuildBitCast(ctx
->ac
.builder
, res_ptr
, ctx
->v8i32
, "");
1812 samples
= LLVMBuildExtractElement(ctx
->ac
.builder
, res
,
1813 LLVMConstInt(ctx
->i32
, 3, 0), "");
1814 samples
= LLVMBuildLShr(ctx
->ac
.builder
, samples
,
1815 LLVMConstInt(ctx
->i32
, 16, 0), "");
1816 samples
= LLVMBuildAnd(ctx
->ac
.builder
, samples
,
1817 LLVMConstInt(ctx
->i32
, 0xf, 0), "");
1818 samples
= LLVMBuildShl(ctx
->ac
.builder
, ctx
->i32_1
,
1821 emit_data
->output
[emit_data
->chan
] = samples
;
1824 static void si_llvm_emit_fbfetch(const struct lp_build_tgsi_action
*action
,
1825 struct lp_build_tgsi_context
*bld_base
,
1826 struct lp_build_emit_data
*emit_data
)
1828 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1829 struct ac_image_args args
= {};
1830 LLVMValueRef ptr
, image
, fmask
;
1832 /* Ignore src0, because KHR_blend_func_extended disallows multiple render
1836 /* Load the image descriptor. */
1837 STATIC_ASSERT(SI_PS_IMAGE_COLORBUF0
% 2 == 0);
1838 ptr
= LLVMGetParam(ctx
->main_fn
, ctx
->param_rw_buffers
);
1839 ptr
= LLVMBuildPointerCast(ctx
->ac
.builder
, ptr
,
1840 ac_array_in_const32_addr_space(ctx
->v8i32
), "");
1841 image
= ac_build_load_to_sgpr(&ctx
->ac
, ptr
,
1842 LLVMConstInt(ctx
->i32
, SI_PS_IMAGE_COLORBUF0
/ 2, 0));
1846 args
.coords
[chan
++] = si_unpack_param(ctx
, SI_PARAM_POS_FIXED_PT
, 0, 16);
1848 if (!ctx
->shader
->key
.mono
.u
.ps
.fbfetch_is_1D
)
1849 args
.coords
[chan
++] = si_unpack_param(ctx
, SI_PARAM_POS_FIXED_PT
, 16, 16);
1851 /* Get the current render target layer index. */
1852 if (ctx
->shader
->key
.mono
.u
.ps
.fbfetch_layered
)
1853 args
.coords
[chan
++] = si_unpack_param(ctx
, SI_PARAM_ANCILLARY
, 16, 11);
1855 if (ctx
->shader
->key
.mono
.u
.ps
.fbfetch_msaa
)
1856 args
.coords
[chan
++] = si_get_sample_id(ctx
);
1858 if (ctx
->shader
->key
.mono
.u
.ps
.fbfetch_msaa
) {
1859 fmask
= ac_build_load_to_sgpr(&ctx
->ac
, ptr
,
1860 LLVMConstInt(ctx
->i32
, SI_PS_IMAGE_COLORBUF0_FMASK
/ 2, 0));
1862 ac_apply_fmask_to_sample(&ctx
->ac
, fmask
, args
.coords
, false);
1865 args
.opcode
= ac_image_load
;
1866 args
.resource
= image
;
1868 if (ctx
->shader
->key
.mono
.u
.ps
.fbfetch_msaa
)
1869 args
.dim
= ctx
->shader
->key
.mono
.u
.ps
.fbfetch_layered
?
1870 ac_image_2darraymsaa
: ac_image_2dmsaa
;
1871 else if (ctx
->shader
->key
.mono
.u
.ps
.fbfetch_is_1D
)
1872 args
.dim
= ctx
->shader
->key
.mono
.u
.ps
.fbfetch_layered
?
1873 ac_image_1darray
: ac_image_1d
;
1875 args
.dim
= ctx
->shader
->key
.mono
.u
.ps
.fbfetch_layered
?
1876 ac_image_2darray
: ac_image_2d
;
1878 emit_data
->output
[emit_data
->chan
] =
1879 ac_build_image_opcode(&ctx
->ac
, &args
);
1882 static const struct lp_build_tgsi_action tex_action
= {
1883 .fetch_args
= tex_fetch_args
,
1884 .emit
= build_tex_intrinsic
,
1888 * Setup actions for TGSI memory opcode, including texture opcodes.
1890 void si_shader_context_init_mem(struct si_shader_context
*ctx
)
1892 struct lp_build_tgsi_context
*bld_base
;
1893 struct lp_build_tgsi_action tmpl
= {};
1895 bld_base
= &ctx
->bld_base
;
1897 bld_base
->op_actions
[TGSI_OPCODE_TEX
] = tex_action
;
1898 bld_base
->op_actions
[TGSI_OPCODE_TEX_LZ
] = tex_action
;
1899 bld_base
->op_actions
[TGSI_OPCODE_TEX2
] = tex_action
;
1900 bld_base
->op_actions
[TGSI_OPCODE_TXB
] = tex_action
;
1901 bld_base
->op_actions
[TGSI_OPCODE_TXB2
] = tex_action
;
1902 bld_base
->op_actions
[TGSI_OPCODE_TXD
] = tex_action
;
1903 bld_base
->op_actions
[TGSI_OPCODE_TXF
] = tex_action
;
1904 bld_base
->op_actions
[TGSI_OPCODE_TXF_LZ
] = tex_action
;
1905 bld_base
->op_actions
[TGSI_OPCODE_TXL
] = tex_action
;
1906 bld_base
->op_actions
[TGSI_OPCODE_TXL2
] = tex_action
;
1907 bld_base
->op_actions
[TGSI_OPCODE_TXP
] = tex_action
;
1908 bld_base
->op_actions
[TGSI_OPCODE_TXQ
].fetch_args
= txq_fetch_args
;
1909 bld_base
->op_actions
[TGSI_OPCODE_TXQ
].emit
= txq_emit
;
1910 bld_base
->op_actions
[TGSI_OPCODE_TG4
] = tex_action
;
1911 bld_base
->op_actions
[TGSI_OPCODE_LODQ
] = tex_action
;
1912 bld_base
->op_actions
[TGSI_OPCODE_TXQS
].emit
= si_llvm_emit_txqs
;
1914 bld_base
->op_actions
[TGSI_OPCODE_FBFETCH
].emit
= si_llvm_emit_fbfetch
;
1916 bld_base
->op_actions
[TGSI_OPCODE_LOAD
].fetch_args
= load_fetch_args
;
1917 bld_base
->op_actions
[TGSI_OPCODE_LOAD
].emit
= load_emit
;
1918 bld_base
->op_actions
[TGSI_OPCODE_STORE
].fetch_args
= store_fetch_args
;
1919 bld_base
->op_actions
[TGSI_OPCODE_STORE
].emit
= store_emit
;
1920 bld_base
->op_actions
[TGSI_OPCODE_RESQ
].fetch_args
= resq_fetch_args
;
1921 bld_base
->op_actions
[TGSI_OPCODE_RESQ
].emit
= resq_emit
;
1923 tmpl
.fetch_args
= atomic_fetch_args
;
1924 tmpl
.emit
= atomic_emit
;
1925 bld_base
->op_actions
[TGSI_OPCODE_ATOMUADD
] = tmpl
;
1926 bld_base
->op_actions
[TGSI_OPCODE_ATOMUADD
].intr_name
= "add";
1927 bld_base
->op_actions
[TGSI_OPCODE_ATOMXCHG
] = tmpl
;
1928 bld_base
->op_actions
[TGSI_OPCODE_ATOMXCHG
].intr_name
= "swap";
1929 bld_base
->op_actions
[TGSI_OPCODE_ATOMCAS
] = tmpl
;
1930 bld_base
->op_actions
[TGSI_OPCODE_ATOMCAS
].intr_name
= "cmpswap";
1931 bld_base
->op_actions
[TGSI_OPCODE_ATOMAND
] = tmpl
;
1932 bld_base
->op_actions
[TGSI_OPCODE_ATOMAND
].intr_name
= "and";
1933 bld_base
->op_actions
[TGSI_OPCODE_ATOMOR
] = tmpl
;
1934 bld_base
->op_actions
[TGSI_OPCODE_ATOMOR
].intr_name
= "or";
1935 bld_base
->op_actions
[TGSI_OPCODE_ATOMXOR
] = tmpl
;
1936 bld_base
->op_actions
[TGSI_OPCODE_ATOMXOR
].intr_name
= "xor";
1937 bld_base
->op_actions
[TGSI_OPCODE_ATOMUMIN
] = tmpl
;
1938 bld_base
->op_actions
[TGSI_OPCODE_ATOMUMIN
].intr_name
= "umin";
1939 bld_base
->op_actions
[TGSI_OPCODE_ATOMUMAX
] = tmpl
;
1940 bld_base
->op_actions
[TGSI_OPCODE_ATOMUMAX
].intr_name
= "umax";
1941 bld_base
->op_actions
[TGSI_OPCODE_ATOMIMIN
] = tmpl
;
1942 bld_base
->op_actions
[TGSI_OPCODE_ATOMIMIN
].intr_name
= "smin";
1943 bld_base
->op_actions
[TGSI_OPCODE_ATOMIMAX
] = tmpl
;
1944 bld_base
->op_actions
[TGSI_OPCODE_ATOMIMAX
].intr_name
= "smax";