2 * Copyright 2017 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "si_shader_internal.h"
28 #include "tgsi/tgsi_build.h"
29 #include "tgsi/tgsi_util.h"
30 #include "ac_llvm_util.h"
33 * Given a v8i32 resource descriptor for a buffer, extract the size of the
34 * buffer in number of elements and return it as an i32.
36 static LLVMValueRef
get_buffer_size(
37 struct lp_build_tgsi_context
*bld_base
,
38 LLVMValueRef descriptor
)
40 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
41 LLVMBuilderRef builder
= ctx
->ac
.builder
;
43 LLVMBuildExtractElement(builder
, descriptor
,
44 LLVMConstInt(ctx
->i32
, 2, 0), "");
46 if (ctx
->screen
->info
.chip_class
== VI
) {
47 /* On VI, the descriptor contains the size in bytes,
48 * but TXQ must return the size in elements.
49 * The stride is always non-zero for resources using TXQ.
52 LLVMBuildExtractElement(builder
, descriptor
,
54 stride
= LLVMBuildLShr(builder
, stride
,
55 LLVMConstInt(ctx
->i32
, 16, 0), "");
56 stride
= LLVMBuildAnd(builder
, stride
,
57 LLVMConstInt(ctx
->i32
, 0x3FFF, 0), "");
59 size
= LLVMBuildUDiv(builder
, size
, stride
, "");
66 shader_buffer_fetch_rsrc(struct si_shader_context
*ctx
,
67 const struct tgsi_full_src_register
*reg
,
72 if (!reg
->Register
.Indirect
) {
73 index
= LLVMConstInt(ctx
->i32
, reg
->Register
.Index
, false);
75 index
= si_get_indirect_index(ctx
, ®
->Indirect
,
76 1, reg
->Register
.Index
);
80 return ctx
->abi
.load_ubo(&ctx
->abi
, index
);
82 return ctx
->abi
.load_ssbo(&ctx
->abi
, index
, false);
85 static enum ac_image_dim
86 ac_texture_dim_from_tgsi_target(struct si_screen
*screen
, enum tgsi_texture_type target
)
90 case TGSI_TEXTURE_SHADOW1D
:
91 if (screen
->info
.chip_class
>= GFX9
)
95 case TGSI_TEXTURE_SHADOW2D
:
96 case TGSI_TEXTURE_RECT
:
97 case TGSI_TEXTURE_SHADOWRECT
:
101 case TGSI_TEXTURE_CUBE
:
102 case TGSI_TEXTURE_SHADOWCUBE
:
103 case TGSI_TEXTURE_CUBE_ARRAY
:
104 case TGSI_TEXTURE_SHADOWCUBE_ARRAY
:
105 return ac_image_cube
;
106 case TGSI_TEXTURE_1D_ARRAY
:
107 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
108 if (screen
->info
.chip_class
>= GFX9
)
109 return ac_image_2darray
;
110 return ac_image_1darray
;
111 case TGSI_TEXTURE_2D_ARRAY
:
112 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
113 return ac_image_2darray
;
114 case TGSI_TEXTURE_2D_MSAA
:
115 return ac_image_2dmsaa
;
116 case TGSI_TEXTURE_2D_ARRAY_MSAA
:
117 return ac_image_2darraymsaa
;
119 unreachable("unhandled texture type");
123 static enum ac_image_dim
124 ac_image_dim_from_tgsi_target(struct si_screen
*screen
, enum tgsi_texture_type target
)
126 enum ac_image_dim dim
= ac_texture_dim_from_tgsi_target(screen
, target
);
128 /* Match the resource type set in the descriptor. */
129 if (dim
== ac_image_cube
||
130 (screen
->info
.chip_class
<= VI
&& dim
== ac_image_3d
))
131 dim
= ac_image_2darray
;
132 else if (target
== TGSI_TEXTURE_2D
&& screen
->info
.chip_class
>= GFX9
) {
133 /* When a single layer of a 3D texture is bound, the shader
134 * will refer to a 2D target, but the descriptor has a 3D type.
135 * Since the HW ignores BASE_ARRAY in this case, we need to
136 * send 3 coordinates. This doesn't hurt when the underlying
146 * Given a 256-bit resource descriptor, force the DCC enable bit to off.
148 * At least on Tonga, executing image stores on images with DCC enabled and
149 * non-trivial can eventually lead to lockups. This can occur when an
150 * application binds an image as read-only but then uses a shader that writes
151 * to it. The OpenGL spec allows almost arbitrarily bad behavior (including
152 * program termination) in this case, but it doesn't cost much to be a bit
153 * nicer: disabling DCC in the shader still leads to undefined results but
156 static LLVMValueRef
force_dcc_off(struct si_shader_context
*ctx
,
159 if (ctx
->screen
->info
.chip_class
<= CIK
) {
162 LLVMValueRef i32_6
= LLVMConstInt(ctx
->i32
, 6, 0);
163 LLVMValueRef i32_C
= LLVMConstInt(ctx
->i32
, C_008F28_COMPRESSION_EN
, 0);
166 tmp
= LLVMBuildExtractElement(ctx
->ac
.builder
, rsrc
, i32_6
, "");
167 tmp
= LLVMBuildAnd(ctx
->ac
.builder
, tmp
, i32_C
, "");
168 return LLVMBuildInsertElement(ctx
->ac
.builder
, rsrc
, tmp
, i32_6
, "");
172 LLVMValueRef
si_load_image_desc(struct si_shader_context
*ctx
,
173 LLVMValueRef list
, LLVMValueRef index
,
174 enum ac_descriptor_type desc_type
, bool dcc_off
)
176 LLVMBuilderRef builder
= ctx
->ac
.builder
;
179 if (desc_type
== AC_DESC_BUFFER
) {
180 index
= LLVMBuildMul(builder
, index
,
181 LLVMConstInt(ctx
->i32
, 2, 0), "");
182 index
= LLVMBuildAdd(builder
, index
,
184 list
= LLVMBuildPointerCast(builder
, list
,
185 ac_array_in_const32_addr_space(ctx
->v4i32
), "");
187 assert(desc_type
== AC_DESC_IMAGE
);
190 rsrc
= ac_build_load_to_sgpr(&ctx
->ac
, list
, index
);
191 if (desc_type
== AC_DESC_IMAGE
&& dcc_off
)
192 rsrc
= force_dcc_off(ctx
, rsrc
);
197 * Load the resource descriptor for \p image.
201 struct lp_build_tgsi_context
*bld_base
,
202 const struct tgsi_full_src_register
*image
,
203 bool is_store
, unsigned target
,
206 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
207 LLVMValueRef rsrc_ptr
= LLVMGetParam(ctx
->main_fn
,
208 ctx
->param_samplers_and_images
);
210 bool dcc_off
= is_store
;
212 if (!image
->Register
.Indirect
) {
213 const struct tgsi_shader_info
*info
= bld_base
->info
;
214 unsigned images_writemask
= info
->images_store
|
217 index
= LLVMConstInt(ctx
->i32
,
218 si_get_image_slot(image
->Register
.Index
), 0);
220 if (images_writemask
& (1 << image
->Register
.Index
))
223 /* From the GL_ARB_shader_image_load_store extension spec:
225 * If a shader performs an image load, store, or atomic
226 * operation using an image variable declared as an array,
227 * and if the index used to select an individual element is
228 * negative or greater than or equal to the size of the
229 * array, the results of the operation are undefined but may
230 * not lead to termination.
232 index
= si_get_bounded_indirect_index(ctx
, &image
->Indirect
,
233 image
->Register
.Index
,
235 index
= LLVMBuildSub(ctx
->ac
.builder
,
236 LLVMConstInt(ctx
->i32
, SI_NUM_IMAGES
- 1, 0),
240 if (image
->Register
.File
!= TGSI_FILE_IMAGE
) {
241 /* Bindless descriptors are accessible from a different pair of
244 rsrc_ptr
= LLVMGetParam(ctx
->main_fn
,
245 ctx
->param_bindless_samplers_and_images
);
246 index
= lp_build_emit_fetch_src(bld_base
, image
,
247 TGSI_TYPE_UNSIGNED
, 0);
249 /* For simplicity, bindless image descriptors use fixed
250 * 16-dword slots for now.
252 index
= LLVMBuildMul(ctx
->ac
.builder
, index
,
253 LLVMConstInt(ctx
->i32
, 2, 0), "");
256 *rsrc
= si_load_image_desc(ctx
, rsrc_ptr
, index
,
257 target
== TGSI_TEXTURE_BUFFER
? AC_DESC_BUFFER
: AC_DESC_IMAGE
,
261 static void image_fetch_coords(
262 struct lp_build_tgsi_context
*bld_base
,
263 const struct tgsi_full_instruction
*inst
,
264 unsigned src
, LLVMValueRef desc
,
265 LLVMValueRef
*coords
)
267 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
268 LLVMBuilderRef builder
= ctx
->ac
.builder
;
269 unsigned target
= inst
->Memory
.Texture
;
270 unsigned num_coords
= tgsi_util_get_texture_coord_dim(target
);
274 if (target
== TGSI_TEXTURE_2D_MSAA
||
275 target
== TGSI_TEXTURE_2D_ARRAY_MSAA
) {
276 /* Need the sample index as well. */
280 for (chan
= 0; chan
< num_coords
; ++chan
) {
281 tmp
= lp_build_emit_fetch(bld_base
, inst
, src
, chan
);
282 tmp
= ac_to_integer(&ctx
->ac
, tmp
);
286 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
287 /* 1D textures are allocated and used as 2D on GFX9. */
288 if (target
== TGSI_TEXTURE_1D
) {
289 coords
[1] = ctx
->i32_0
;
290 } else if (target
== TGSI_TEXTURE_1D_ARRAY
) {
291 coords
[2] = coords
[1];
292 coords
[1] = ctx
->i32_0
;
293 } else if (target
== TGSI_TEXTURE_2D
) {
294 /* The hw can't bind a slice of a 3D image as a 2D
295 * image, because it ignores BASE_ARRAY if the target
296 * is 3D. The workaround is to read BASE_ARRAY and set
297 * it as the 3rd address operand for all 2D images.
299 LLVMValueRef first_layer
, const5
, mask
;
301 const5
= LLVMConstInt(ctx
->i32
, 5, 0);
302 mask
= LLVMConstInt(ctx
->i32
, S_008F24_BASE_ARRAY(~0), 0);
303 first_layer
= LLVMBuildExtractElement(builder
, desc
, const5
, "");
304 first_layer
= LLVMBuildAnd(builder
, first_layer
, mask
, "");
306 coords
[2] = first_layer
;
312 * Append the resource and indexing arguments for buffer intrinsics.
314 * \param rsrc the v4i32 buffer resource
315 * \param index index into the buffer (stride-based)
316 * \param offset byte offset into the buffer
318 static void buffer_append_args(
319 struct si_shader_context
*ctx
,
320 struct lp_build_emit_data
*emit_data
,
327 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
328 LLVMValueRef i1false
= LLVMConstInt(ctx
->i1
, 0, 0);
329 LLVMValueRef i1true
= LLVMConstInt(ctx
->i1
, 1, 0);
331 emit_data
->args
[emit_data
->arg_count
++] = rsrc
;
332 emit_data
->args
[emit_data
->arg_count
++] = index
; /* vindex */
333 emit_data
->args
[emit_data
->arg_count
++] = offset
; /* voffset */
335 emit_data
->args
[emit_data
->arg_count
++] =
337 inst
->Memory
.Qualifier
& (TGSI_MEMORY_COHERENT
| TGSI_MEMORY_VOLATILE
) ?
338 i1true
: i1false
; /* glc */
340 emit_data
->args
[emit_data
->arg_count
++] = i1false
; /* slc */
343 static void load_fetch_args(
344 struct lp_build_tgsi_context
* bld_base
,
345 struct lp_build_emit_data
* emit_data
)
347 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
348 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
349 unsigned target
= inst
->Memory
.Texture
;
352 emit_data
->dst_type
= ctx
->v4f32
;
354 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
||
355 inst
->Src
[0].Register
.File
== TGSI_FILE_CONSTBUF
) {
359 bool ubo
= inst
->Src
[0].Register
.File
== TGSI_FILE_CONSTBUF
;
360 rsrc
= shader_buffer_fetch_rsrc(ctx
, &inst
->Src
[0], ubo
);
362 tmp
= lp_build_emit_fetch(bld_base
, inst
, 1, 0);
363 offset
= ac_to_integer(&ctx
->ac
, tmp
);
365 buffer_append_args(ctx
, emit_data
, rsrc
, ctx
->i32_0
,
366 offset
, false, false);
367 } else if (inst
->Src
[0].Register
.File
== TGSI_FILE_IMAGE
||
368 tgsi_is_bindless_image_file(inst
->Src
[0].Register
.File
)) {
369 image_fetch_rsrc(bld_base
, &inst
->Src
[0], false, target
, &rsrc
);
370 image_fetch_coords(bld_base
, inst
, 1, rsrc
, &emit_data
->args
[1]);
372 if (target
== TGSI_TEXTURE_BUFFER
) {
373 buffer_append_args(ctx
, emit_data
, rsrc
, emit_data
->args
[1],
374 ctx
->i32_0
, false, false);
376 emit_data
->args
[0] = rsrc
;
381 static void load_emit_buffer(struct si_shader_context
*ctx
,
382 struct lp_build_emit_data
*emit_data
,
383 bool can_speculate
, bool allow_smem
)
385 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
386 uint writemask
= inst
->Dst
[0].Register
.WriteMask
;
387 uint count
= util_last_bit(writemask
);
388 LLVMValueRef
*args
= emit_data
->args
;
390 /* Don't use SMEM for shader buffer loads, because LLVM doesn't
391 * select SMEM for SI.load.const with a non-constant offset, and
392 * constant offsets practically don't exist with shader buffers.
394 * Also, SI.load.const doesn't use inst_offset when it's lowered
395 * to VMEM, so we just end up with more VALU instructions in the end
398 * TODO: Remove this line once LLVM can select SMEM with a non-constant
399 * offset, and can derive inst_offset when VMEM is selected.
400 * After that, si_memory_barrier should invalidate sL1 for shader
404 assert(LLVMConstIntGetZExtValue(args
[1]) == 0); /* vindex */
405 emit_data
->output
[emit_data
->chan
] =
406 ac_build_buffer_load(&ctx
->ac
, args
[0], count
, NULL
,
408 LLVMConstIntGetZExtValue(args
[3]),
409 LLVMConstIntGetZExtValue(args
[4]),
410 can_speculate
, allow_smem
);
413 static LLVMValueRef
get_memory_ptr(struct si_shader_context
*ctx
,
414 const struct tgsi_full_instruction
*inst
,
415 LLVMTypeRef type
, int arg
)
417 LLVMBuilderRef builder
= ctx
->ac
.builder
;
418 LLVMValueRef offset
, ptr
;
421 offset
= lp_build_emit_fetch(&ctx
->bld_base
, inst
, arg
, 0);
422 offset
= ac_to_integer(&ctx
->ac
, offset
);
425 ptr
= LLVMBuildGEP(builder
, ptr
, &offset
, 1, "");
426 addr_space
= LLVMGetPointerAddressSpace(LLVMTypeOf(ptr
));
427 ptr
= LLVMBuildBitCast(builder
, ptr
, LLVMPointerType(type
, addr_space
), "");
432 static void load_emit_memory(
433 struct si_shader_context
*ctx
,
434 struct lp_build_emit_data
*emit_data
)
436 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
437 unsigned writemask
= inst
->Dst
[0].Register
.WriteMask
;
438 LLVMValueRef channels
[4], ptr
, derived_ptr
, index
;
441 ptr
= get_memory_ptr(ctx
, inst
, ctx
->f32
, 1);
443 for (chan
= 0; chan
< 4; ++chan
) {
444 if (!(writemask
& (1 << chan
))) {
445 channels
[chan
] = LLVMGetUndef(ctx
->f32
);
449 index
= LLVMConstInt(ctx
->i32
, chan
, 0);
450 derived_ptr
= LLVMBuildGEP(ctx
->ac
.builder
, ptr
, &index
, 1, "");
451 channels
[chan
] = LLVMBuildLoad(ctx
->ac
.builder
, derived_ptr
, "");
453 emit_data
->output
[emit_data
->chan
] = ac_build_gather_values(&ctx
->ac
, channels
, 4);
457 * Return true if the memory accessed by a LOAD or STORE instruction is
458 * read-only or write-only, respectively.
460 * \param shader_buffers_reverse_access_mask
461 * For LOAD, set this to (store | atomic) slot usage in the shader.
462 * For STORE, set this to (load | atomic) slot usage in the shader.
463 * \param images_reverse_access_mask Same as above, but for images.
465 static bool is_oneway_access_only(const struct tgsi_full_instruction
*inst
,
466 const struct tgsi_shader_info
*info
,
467 unsigned shader_buffers_reverse_access_mask
,
468 unsigned images_reverse_access_mask
)
470 /* RESTRICT means NOALIAS.
471 * If there are no writes, we can assume the accessed memory is read-only.
472 * If there are no reads, we can assume the accessed memory is write-only.
474 if (inst
->Memory
.Qualifier
& TGSI_MEMORY_RESTRICT
) {
475 unsigned reverse_access_mask
;
477 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
) {
478 reverse_access_mask
= shader_buffers_reverse_access_mask
;
479 } else if (inst
->Memory
.Texture
== TGSI_TEXTURE_BUFFER
) {
480 reverse_access_mask
= info
->images_buffers
&
481 images_reverse_access_mask
;
483 reverse_access_mask
= ~info
->images_buffers
&
484 images_reverse_access_mask
;
487 if (inst
->Src
[0].Register
.Indirect
) {
488 if (!reverse_access_mask
)
491 if (!(reverse_access_mask
&
492 (1u << inst
->Src
[0].Register
.Index
)))
497 /* If there are no buffer writes (for both shader buffers & image
498 * buffers), it implies that buffer memory is read-only.
499 * If there are no buffer reads (for both shader buffers & image
500 * buffers), it implies that buffer memory is write-only.
502 * Same for the case when there are no writes/reads for non-buffer
505 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
||
506 (inst
->Memory
.Texture
== TGSI_TEXTURE_BUFFER
&&
507 (inst
->Src
[0].Register
.File
== TGSI_FILE_IMAGE
||
508 tgsi_is_bindless_image_file(inst
->Src
[0].Register
.File
)))) {
509 if (!shader_buffers_reverse_access_mask
&&
510 !(info
->images_buffers
& images_reverse_access_mask
))
513 if (!(~info
->images_buffers
& images_reverse_access_mask
))
519 static void load_emit(
520 const struct lp_build_tgsi_action
*action
,
521 struct lp_build_tgsi_context
*bld_base
,
522 struct lp_build_emit_data
*emit_data
)
524 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
525 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
526 const struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
527 bool can_speculate
= false;
529 if (inst
->Src
[0].Register
.File
== TGSI_FILE_MEMORY
) {
530 load_emit_memory(ctx
, emit_data
);
534 if (inst
->Src
[0].Register
.File
== TGSI_FILE_CONSTBUF
) {
535 load_emit_buffer(ctx
, emit_data
, true, true);
539 if (inst
->Memory
.Qualifier
& TGSI_MEMORY_VOLATILE
)
540 ac_build_waitcnt(&ctx
->ac
, VM_CNT
);
542 can_speculate
= !(inst
->Memory
.Qualifier
& TGSI_MEMORY_VOLATILE
) &&
543 is_oneway_access_only(inst
, info
,
544 info
->shader_buffers_store
|
545 info
->shader_buffers_atomic
,
547 info
->images_atomic
);
549 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
) {
550 load_emit_buffer(ctx
, emit_data
, can_speculate
, false);
554 if (inst
->Memory
.Texture
== TGSI_TEXTURE_BUFFER
) {
555 unsigned num_channels
= util_last_bit(inst
->Dst
[0].Register
.WriteMask
);
556 LLVMValueRef result
=
557 ac_build_buffer_load_format(&ctx
->ac
,
562 LLVMConstIntGetZExtValue(emit_data
->args
[3]),
564 emit_data
->output
[emit_data
->chan
] =
565 ac_build_expand_to_vec4(&ctx
->ac
, result
, num_channels
);
567 struct ac_image_args args
= {};
568 args
.opcode
= ac_image_load
;
569 args
.resource
= emit_data
->args
[0];
570 memcpy(args
.coords
, &emit_data
->args
[1], sizeof(args
.coords
));
571 args
.dim
= ac_image_dim_from_tgsi_target(ctx
->screen
, inst
->Memory
.Texture
);
572 if (inst
->Memory
.Qualifier
& (TGSI_MEMORY_COHERENT
| TGSI_MEMORY_VOLATILE
))
573 args
.cache_policy
= ac_glc
;
574 args
.attributes
= ac_get_load_intr_attribs(can_speculate
);
577 emit_data
->output
[emit_data
->chan
] =
578 ac_build_image_opcode(&ctx
->ac
, &args
);
582 static void store_fetch_args(
583 struct lp_build_tgsi_context
* bld_base
,
584 struct lp_build_emit_data
* emit_data
)
586 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
587 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
588 struct tgsi_full_src_register memory
;
589 LLVMValueRef chans
[4];
594 emit_data
->dst_type
= ctx
->voidt
;
596 for (chan
= 0; chan
< 4; ++chan
) {
597 chans
[chan
] = lp_build_emit_fetch(bld_base
, inst
, 1, chan
);
599 data
= ac_build_gather_values(&ctx
->ac
, chans
, 4);
601 emit_data
->args
[emit_data
->arg_count
++] = data
;
603 memory
= tgsi_full_src_register_from_dst(&inst
->Dst
[0]);
605 if (inst
->Dst
[0].Register
.File
== TGSI_FILE_BUFFER
) {
609 rsrc
= shader_buffer_fetch_rsrc(ctx
, &memory
, false);
611 tmp
= lp_build_emit_fetch(bld_base
, inst
, 0, 0);
612 offset
= ac_to_integer(&ctx
->ac
, tmp
);
614 buffer_append_args(ctx
, emit_data
, rsrc
, ctx
->i32_0
,
615 offset
, false, false);
616 } else if (inst
->Dst
[0].Register
.File
== TGSI_FILE_IMAGE
||
617 tgsi_is_bindless_image_file(inst
->Dst
[0].Register
.File
)) {
618 unsigned target
= inst
->Memory
.Texture
;
620 /* 8bit/16bit TC L1 write corruption bug on SI.
621 * All store opcodes not aligned to a dword are affected.
623 * The only way to get unaligned stores in radeonsi is through
626 bool force_glc
= ctx
->screen
->info
.chip_class
== SI
;
628 image_fetch_rsrc(bld_base
, &memory
, true, target
, &rsrc
);
629 image_fetch_coords(bld_base
, inst
, 0, rsrc
, &emit_data
->args
[2]);
631 if (target
== TGSI_TEXTURE_BUFFER
) {
632 buffer_append_args(ctx
, emit_data
, rsrc
, emit_data
->args
[2],
633 ctx
->i32_0
, false, force_glc
);
635 emit_data
->args
[1] = rsrc
;
640 static void store_emit_buffer(
641 struct si_shader_context
*ctx
,
642 struct lp_build_emit_data
*emit_data
,
643 bool writeonly_memory
)
645 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
646 LLVMBuilderRef builder
= ctx
->ac
.builder
;
647 LLVMValueRef base_data
= emit_data
->args
[0];
648 LLVMValueRef base_offset
= emit_data
->args
[3];
649 unsigned writemask
= inst
->Dst
[0].Register
.WriteMask
;
651 /* If this is write-only, don't keep data in L1 to prevent
652 * evicting L1 cache lines that may be needed by other
655 if (writeonly_memory
)
656 emit_data
->args
[4] = LLVMConstInt(ctx
->i1
, 1, 0); /* GLC = 1 */
660 const char *intrinsic_name
;
665 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
667 /* Due to an LLVM limitation, split 3-element writes
668 * into a 2-element and a 1-element write. */
670 writemask
|= 1 << (start
+ 2);
676 intrinsic_name
= "llvm.amdgcn.buffer.store.v4f32";
677 } else if (count
== 2) {
678 LLVMTypeRef v2f32
= LLVMVectorType(ctx
->f32
, 2);
680 tmp
= LLVMBuildExtractElement(
682 LLVMConstInt(ctx
->i32
, start
, 0), "");
683 data
= LLVMBuildInsertElement(
684 builder
, LLVMGetUndef(v2f32
), tmp
,
687 tmp
= LLVMBuildExtractElement(
689 LLVMConstInt(ctx
->i32
, start
+ 1, 0), "");
690 data
= LLVMBuildInsertElement(
691 builder
, data
, tmp
, ctx
->i32_1
, "");
693 intrinsic_name
= "llvm.amdgcn.buffer.store.v2f32";
696 data
= LLVMBuildExtractElement(
698 LLVMConstInt(ctx
->i32
, start
, 0), "");
699 intrinsic_name
= "llvm.amdgcn.buffer.store.f32";
702 offset
= base_offset
;
704 offset
= LLVMBuildAdd(
706 LLVMConstInt(ctx
->i32
, start
* 4, 0), "");
709 emit_data
->args
[0] = data
;
710 emit_data
->args
[3] = offset
;
713 &ctx
->ac
, intrinsic_name
, emit_data
->dst_type
,
714 emit_data
->args
, emit_data
->arg_count
,
715 ac_get_store_intr_attribs(writeonly_memory
));
719 static void store_emit_memory(
720 struct si_shader_context
*ctx
,
721 struct lp_build_emit_data
*emit_data
)
723 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
724 LLVMBuilderRef builder
= ctx
->ac
.builder
;
725 unsigned writemask
= inst
->Dst
[0].Register
.WriteMask
;
726 LLVMValueRef ptr
, derived_ptr
, data
, index
;
729 ptr
= get_memory_ptr(ctx
, inst
, ctx
->f32
, 0);
731 for (chan
= 0; chan
< 4; ++chan
) {
732 if (!(writemask
& (1 << chan
))) {
735 data
= lp_build_emit_fetch(&ctx
->bld_base
, inst
, 1, chan
);
736 index
= LLVMConstInt(ctx
->i32
, chan
, 0);
737 derived_ptr
= LLVMBuildGEP(builder
, ptr
, &index
, 1, "");
738 LLVMBuildStore(builder
, data
, derived_ptr
);
742 static void store_emit(
743 const struct lp_build_tgsi_action
*action
,
744 struct lp_build_tgsi_context
*bld_base
,
745 struct lp_build_emit_data
*emit_data
)
747 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
748 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
749 const struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
750 unsigned target
= inst
->Memory
.Texture
;
751 bool writeonly_memory
= false;
753 if (inst
->Dst
[0].Register
.File
== TGSI_FILE_MEMORY
) {
754 store_emit_memory(ctx
, emit_data
);
758 if (inst
->Memory
.Qualifier
& TGSI_MEMORY_VOLATILE
)
759 ac_build_waitcnt(&ctx
->ac
, VM_CNT
);
761 writeonly_memory
= is_oneway_access_only(inst
, info
,
762 info
->shader_buffers_load
|
763 info
->shader_buffers_atomic
,
765 info
->images_atomic
);
767 if (inst
->Dst
[0].Register
.File
== TGSI_FILE_BUFFER
) {
768 store_emit_buffer(ctx
, emit_data
, writeonly_memory
);
772 if (target
== TGSI_TEXTURE_BUFFER
) {
773 /* If this is write-only, don't keep data in L1 to prevent
774 * evicting L1 cache lines that may be needed by other
777 if (writeonly_memory
)
778 emit_data
->args
[4] = LLVMConstInt(ctx
->i1
, 1, 0); /* GLC = 1 */
780 emit_data
->output
[emit_data
->chan
] = ac_build_intrinsic(
781 &ctx
->ac
, "llvm.amdgcn.buffer.store.format.v4f32",
782 emit_data
->dst_type
, emit_data
->args
,
783 emit_data
->arg_count
,
784 ac_get_store_intr_attribs(writeonly_memory
));
786 struct ac_image_args args
= {};
787 args
.opcode
= ac_image_store
;
788 args
.data
[0] = emit_data
->args
[0];
789 args
.resource
= emit_data
->args
[1];
790 memcpy(args
.coords
, &emit_data
->args
[2], sizeof(args
.coords
));
791 args
.dim
= ac_image_dim_from_tgsi_target(ctx
->screen
, inst
->Memory
.Texture
);
792 args
.attributes
= ac_get_store_intr_attribs(writeonly_memory
);
795 /* Workaround for 8bit/16bit TC L1 write corruption bug on SI.
796 * All store opcodes not aligned to a dword are affected.
798 if (ctx
->screen
->info
.chip_class
== SI
||
799 /* If this is write-only, don't keep data in L1 to prevent
800 * evicting L1 cache lines that may be needed by other
803 inst
->Memory
.Qualifier
& (TGSI_MEMORY_COHERENT
| TGSI_MEMORY_VOLATILE
))
804 args
.cache_policy
= ac_glc
;
806 emit_data
->output
[emit_data
->chan
] =
807 ac_build_image_opcode(&ctx
->ac
, &args
);
811 static void atomic_fetch_args(
812 struct lp_build_tgsi_context
* bld_base
,
813 struct lp_build_emit_data
* emit_data
)
815 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
816 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
817 LLVMValueRef data1
, data2
;
821 emit_data
->dst_type
= ctx
->f32
;
823 tmp
= lp_build_emit_fetch(bld_base
, inst
, 2, 0);
824 data1
= ac_to_integer(&ctx
->ac
, tmp
);
826 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
) {
827 tmp
= lp_build_emit_fetch(bld_base
, inst
, 3, 0);
828 data2
= ac_to_integer(&ctx
->ac
, tmp
);
831 /* llvm.amdgcn.image/buffer.atomic.cmpswap reflect the hardware order
832 * of arguments, which is reversed relative to TGSI (and GLSL)
834 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
)
835 emit_data
->args
[emit_data
->arg_count
++] = data2
;
836 emit_data
->args
[emit_data
->arg_count
++] = data1
;
838 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
) {
841 rsrc
= shader_buffer_fetch_rsrc(ctx
, &inst
->Src
[0], false);
843 tmp
= lp_build_emit_fetch(bld_base
, inst
, 1, 0);
844 offset
= ac_to_integer(&ctx
->ac
, tmp
);
846 buffer_append_args(ctx
, emit_data
, rsrc
, ctx
->i32_0
,
847 offset
, true, false);
848 } else if (inst
->Src
[0].Register
.File
== TGSI_FILE_IMAGE
||
849 tgsi_is_bindless_image_file(inst
->Src
[0].Register
.File
)) {
850 unsigned target
= inst
->Memory
.Texture
;
852 image_fetch_rsrc(bld_base
, &inst
->Src
[0], true, target
, &rsrc
);
853 image_fetch_coords(bld_base
, inst
, 1, rsrc
,
854 &emit_data
->args
[emit_data
->arg_count
+ 1]);
856 if (target
== TGSI_TEXTURE_BUFFER
) {
857 buffer_append_args(ctx
, emit_data
, rsrc
,
858 emit_data
->args
[emit_data
->arg_count
+ 1],
859 ctx
->i32_0
, true, false);
861 emit_data
->args
[emit_data
->arg_count
] = rsrc
;
866 static void atomic_emit_memory(struct si_shader_context
*ctx
,
867 struct lp_build_emit_data
*emit_data
) {
868 LLVMBuilderRef builder
= ctx
->ac
.builder
;
869 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
870 LLVMValueRef ptr
, result
, arg
;
872 ptr
= get_memory_ptr(ctx
, inst
, ctx
->i32
, 1);
874 arg
= lp_build_emit_fetch(&ctx
->bld_base
, inst
, 2, 0);
875 arg
= ac_to_integer(&ctx
->ac
, arg
);
877 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
) {
878 LLVMValueRef new_data
;
879 new_data
= lp_build_emit_fetch(&ctx
->bld_base
,
882 new_data
= ac_to_integer(&ctx
->ac
, new_data
);
884 result
= LLVMBuildAtomicCmpXchg(builder
, ptr
, arg
, new_data
,
885 LLVMAtomicOrderingSequentiallyConsistent
,
886 LLVMAtomicOrderingSequentiallyConsistent
,
889 result
= LLVMBuildExtractValue(builder
, result
, 0, "");
891 LLVMAtomicRMWBinOp op
;
893 switch(inst
->Instruction
.Opcode
) {
894 case TGSI_OPCODE_ATOMUADD
:
895 op
= LLVMAtomicRMWBinOpAdd
;
897 case TGSI_OPCODE_ATOMXCHG
:
898 op
= LLVMAtomicRMWBinOpXchg
;
900 case TGSI_OPCODE_ATOMAND
:
901 op
= LLVMAtomicRMWBinOpAnd
;
903 case TGSI_OPCODE_ATOMOR
:
904 op
= LLVMAtomicRMWBinOpOr
;
906 case TGSI_OPCODE_ATOMXOR
:
907 op
= LLVMAtomicRMWBinOpXor
;
909 case TGSI_OPCODE_ATOMUMIN
:
910 op
= LLVMAtomicRMWBinOpUMin
;
912 case TGSI_OPCODE_ATOMUMAX
:
913 op
= LLVMAtomicRMWBinOpUMax
;
915 case TGSI_OPCODE_ATOMIMIN
:
916 op
= LLVMAtomicRMWBinOpMin
;
918 case TGSI_OPCODE_ATOMIMAX
:
919 op
= LLVMAtomicRMWBinOpMax
;
922 unreachable("unknown atomic opcode");
925 result
= LLVMBuildAtomicRMW(builder
, op
, ptr
, arg
,
926 LLVMAtomicOrderingSequentiallyConsistent
,
929 emit_data
->output
[emit_data
->chan
] = LLVMBuildBitCast(builder
, result
, emit_data
->dst_type
, "");
932 static void atomic_emit(
933 const struct lp_build_tgsi_action
*action
,
934 struct lp_build_tgsi_context
*bld_base
,
935 struct lp_build_emit_data
*emit_data
)
937 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
938 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
941 if (inst
->Src
[0].Register
.File
== TGSI_FILE_MEMORY
) {
942 atomic_emit_memory(ctx
, emit_data
);
946 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
||
947 inst
->Memory
.Texture
== TGSI_TEXTURE_BUFFER
) {
948 char intrinsic_name
[40];
949 snprintf(intrinsic_name
, sizeof(intrinsic_name
),
950 "llvm.amdgcn.buffer.atomic.%s", action
->intr_name
);
951 tmp
= ac_build_intrinsic(
952 &ctx
->ac
, intrinsic_name
, ctx
->i32
,
953 emit_data
->args
, emit_data
->arg_count
, 0);
954 emit_data
->output
[emit_data
->chan
] = ac_to_float(&ctx
->ac
, tmp
);
956 unsigned num_data
= inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
? 2 : 1;
957 struct ac_image_args args
= {};
959 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
) {
960 args
.opcode
= ac_image_atomic_cmpswap
;
962 args
.opcode
= ac_image_atomic
;
963 switch (inst
->Instruction
.Opcode
) {
964 case TGSI_OPCODE_ATOMXCHG
: args
.atomic
= ac_atomic_swap
; break;
965 case TGSI_OPCODE_ATOMUADD
: args
.atomic
= ac_atomic_add
; break;
966 case TGSI_OPCODE_ATOMAND
: args
.atomic
= ac_atomic_and
; break;
967 case TGSI_OPCODE_ATOMOR
: args
.atomic
= ac_atomic_or
; break;
968 case TGSI_OPCODE_ATOMXOR
: args
.atomic
= ac_atomic_xor
; break;
969 case TGSI_OPCODE_ATOMUMIN
: args
.atomic
= ac_atomic_umin
; break;
970 case TGSI_OPCODE_ATOMUMAX
: args
.atomic
= ac_atomic_umax
; break;
971 case TGSI_OPCODE_ATOMIMIN
: args
.atomic
= ac_atomic_smin
; break;
972 case TGSI_OPCODE_ATOMIMAX
: args
.atomic
= ac_atomic_smax
; break;
973 default: unreachable("unhandled image atomic");
977 for (unsigned i
= 0; i
< num_data
; ++i
)
978 args
.data
[i
] = emit_data
->args
[i
];
980 args
.resource
= emit_data
->args
[num_data
];
981 memcpy(args
.coords
, &emit_data
->args
[num_data
+ 1], sizeof(args
.coords
));
982 args
.dim
= ac_image_dim_from_tgsi_target(ctx
->screen
, inst
->Memory
.Texture
);
984 emit_data
->output
[emit_data
->chan
] =
985 ac_to_float(&ctx
->ac
, ac_build_image_opcode(&ctx
->ac
, &args
));
989 static void set_tex_fetch_args(struct si_shader_context
*ctx
,
990 struct lp_build_emit_data
*emit_data
,
991 struct ac_image_args
*args
,
994 args
->dim
= ac_texture_dim_from_tgsi_target(ctx
->screen
, target
);
995 args
->unorm
= target
== TGSI_TEXTURE_RECT
||
996 target
== TGSI_TEXTURE_SHADOWRECT
;
998 /* Ugly, but we seem to have no other choice right now. */
999 STATIC_ASSERT(sizeof(*args
) <= sizeof(emit_data
->args
));
1000 memcpy(emit_data
->args
, args
, sizeof(*args
));
1003 static LLVMValueRef
fix_resinfo(struct si_shader_context
*ctx
,
1004 unsigned target
, LLVMValueRef out
)
1006 LLVMBuilderRef builder
= ctx
->ac
.builder
;
1008 /* 1D textures are allocated and used as 2D on GFX9. */
1009 if (ctx
->screen
->info
.chip_class
>= GFX9
&&
1010 (target
== TGSI_TEXTURE_1D_ARRAY
||
1011 target
== TGSI_TEXTURE_SHADOW1D_ARRAY
)) {
1012 LLVMValueRef layers
=
1013 LLVMBuildExtractElement(builder
, out
,
1014 LLVMConstInt(ctx
->i32
, 2, 0), "");
1015 out
= LLVMBuildInsertElement(builder
, out
, layers
,
1019 /* Divide the number of layers by 6 to get the number of cubes. */
1020 if (target
== TGSI_TEXTURE_CUBE_ARRAY
||
1021 target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
1022 LLVMValueRef imm2
= LLVMConstInt(ctx
->i32
, 2, 0);
1024 LLVMValueRef z
= LLVMBuildExtractElement(builder
, out
, imm2
, "");
1025 z
= LLVMBuildSDiv(builder
, z
, LLVMConstInt(ctx
->i32
, 6, 0), "");
1027 out
= LLVMBuildInsertElement(builder
, out
, z
, imm2
, "");
1032 static void resq_fetch_args(
1033 struct lp_build_tgsi_context
* bld_base
,
1034 struct lp_build_emit_data
* emit_data
)
1036 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1037 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
1038 const struct tgsi_full_src_register
*reg
= &inst
->Src
[0];
1040 emit_data
->dst_type
= ctx
->v4i32
;
1042 if (reg
->Register
.File
== TGSI_FILE_BUFFER
) {
1043 emit_data
->args
[0] = shader_buffer_fetch_rsrc(ctx
, reg
, false);
1044 emit_data
->arg_count
= 1;
1045 } else if (inst
->Memory
.Texture
== TGSI_TEXTURE_BUFFER
) {
1046 image_fetch_rsrc(bld_base
, reg
, false, inst
->Memory
.Texture
,
1047 &emit_data
->args
[0]);
1048 emit_data
->arg_count
= 1;
1050 struct ac_image_args args
= {};
1051 unsigned image_target
;
1053 if (inst
->Memory
.Texture
== TGSI_TEXTURE_3D
)
1054 image_target
= TGSI_TEXTURE_2D_ARRAY
;
1056 image_target
= inst
->Memory
.Texture
;
1058 image_fetch_rsrc(bld_base
, reg
, false, inst
->Memory
.Texture
,
1060 args
.lod
= ctx
->i32_0
;
1062 set_tex_fetch_args(ctx
, emit_data
, &args
, image_target
);
1066 static void resq_emit(
1067 const struct lp_build_tgsi_action
*action
,
1068 struct lp_build_tgsi_context
*bld_base
,
1069 struct lp_build_emit_data
*emit_data
)
1071 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1072 LLVMBuilderRef builder
= ctx
->ac
.builder
;
1073 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
1076 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
) {
1077 out
= LLVMBuildExtractElement(builder
, emit_data
->args
[0],
1078 LLVMConstInt(ctx
->i32
, 2, 0), "");
1079 } else if (inst
->Memory
.Texture
== TGSI_TEXTURE_BUFFER
) {
1080 out
= get_buffer_size(bld_base
, emit_data
->args
[0]);
1082 struct ac_image_args args
;
1084 memcpy(&args
, emit_data
->args
, sizeof(args
)); /* ugly */
1085 args
.opcode
= ac_image_get_resinfo
;
1086 out
= ac_build_image_opcode(&ctx
->ac
, &args
);
1088 out
= fix_resinfo(ctx
, inst
->Memory
.Texture
, out
);
1091 emit_data
->output
[emit_data
->chan
] = out
;
1095 * Load an image view, fmask view. or sampler state descriptor.
1097 LLVMValueRef
si_load_sampler_desc(struct si_shader_context
*ctx
,
1098 LLVMValueRef list
, LLVMValueRef index
,
1099 enum ac_descriptor_type type
)
1101 LLVMBuilderRef builder
= ctx
->ac
.builder
;
1105 /* The image is at [0:7]. */
1106 index
= LLVMBuildMul(builder
, index
, LLVMConstInt(ctx
->i32
, 2, 0), "");
1108 case AC_DESC_BUFFER
:
1109 /* The buffer is in [4:7]. */
1110 index
= LLVMBuildMul(builder
, index
, LLVMConstInt(ctx
->i32
, 4, 0), "");
1111 index
= LLVMBuildAdd(builder
, index
, ctx
->i32_1
, "");
1112 list
= LLVMBuildPointerCast(builder
, list
,
1113 ac_array_in_const32_addr_space(ctx
->v4i32
), "");
1116 /* The FMASK is at [8:15]. */
1117 index
= LLVMBuildMul(builder
, index
, LLVMConstInt(ctx
->i32
, 2, 0), "");
1118 index
= LLVMBuildAdd(builder
, index
, ctx
->i32_1
, "");
1120 case AC_DESC_SAMPLER
:
1121 /* The sampler state is at [12:15]. */
1122 index
= LLVMBuildMul(builder
, index
, LLVMConstInt(ctx
->i32
, 4, 0), "");
1123 index
= LLVMBuildAdd(builder
, index
, LLVMConstInt(ctx
->i32
, 3, 0), "");
1124 list
= LLVMBuildPointerCast(builder
, list
,
1125 ac_array_in_const32_addr_space(ctx
->v4i32
), "");
1129 return ac_build_load_to_sgpr(&ctx
->ac
, list
, index
);
1132 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
1135 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
1136 * filtering manually. The driver sets img7 to a mask clearing
1137 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
1138 * s_and_b32 samp0, samp0, img7
1141 * The ANISO_OVERRIDE sampler field enables this fix in TA.
1143 static LLVMValueRef
sici_fix_sampler_aniso(struct si_shader_context
*ctx
,
1144 LLVMValueRef res
, LLVMValueRef samp
)
1146 LLVMValueRef img7
, samp0
;
1148 if (ctx
->screen
->info
.chip_class
>= VI
)
1151 img7
= LLVMBuildExtractElement(ctx
->ac
.builder
, res
,
1152 LLVMConstInt(ctx
->i32
, 7, 0), "");
1153 samp0
= LLVMBuildExtractElement(ctx
->ac
.builder
, samp
,
1155 samp0
= LLVMBuildAnd(ctx
->ac
.builder
, samp0
, img7
, "");
1156 return LLVMBuildInsertElement(ctx
->ac
.builder
, samp
, samp0
,
1160 static void tex_fetch_ptrs(
1161 struct lp_build_tgsi_context
*bld_base
,
1162 struct lp_build_emit_data
*emit_data
,
1163 LLVMValueRef
*res_ptr
, LLVMValueRef
*samp_ptr
, LLVMValueRef
*fmask_ptr
)
1165 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1166 LLVMValueRef list
= LLVMGetParam(ctx
->main_fn
, ctx
->param_samplers_and_images
);
1167 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
1168 const struct tgsi_full_src_register
*reg
;
1169 unsigned target
= inst
->Texture
.Texture
;
1170 unsigned sampler_src
;
1173 sampler_src
= emit_data
->inst
->Instruction
.NumSrcRegs
- 1;
1174 reg
= &emit_data
->inst
->Src
[sampler_src
];
1176 if (reg
->Register
.Indirect
) {
1177 index
= si_get_bounded_indirect_index(ctx
,
1179 reg
->Register
.Index
,
1181 index
= LLVMBuildAdd(ctx
->ac
.builder
, index
,
1182 LLVMConstInt(ctx
->i32
, SI_NUM_IMAGES
/ 2, 0), "");
1184 index
= LLVMConstInt(ctx
->i32
,
1185 si_get_sampler_slot(reg
->Register
.Index
), 0);
1188 if (reg
->Register
.File
!= TGSI_FILE_SAMPLER
) {
1189 /* Bindless descriptors are accessible from a different pair of
1190 * user SGPR indices.
1192 list
= LLVMGetParam(ctx
->main_fn
,
1193 ctx
->param_bindless_samplers_and_images
);
1194 index
= lp_build_emit_fetch_src(bld_base
, reg
,
1195 TGSI_TYPE_UNSIGNED
, 0);
1198 if (target
== TGSI_TEXTURE_BUFFER
)
1199 *res_ptr
= si_load_sampler_desc(ctx
, list
, index
, AC_DESC_BUFFER
);
1201 *res_ptr
= si_load_sampler_desc(ctx
, list
, index
, AC_DESC_IMAGE
);
1208 if (target
== TGSI_TEXTURE_2D_MSAA
||
1209 target
== TGSI_TEXTURE_2D_ARRAY_MSAA
) {
1211 *fmask_ptr
= si_load_sampler_desc(ctx
, list
, index
,
1213 } else if (target
!= TGSI_TEXTURE_BUFFER
) {
1215 *samp_ptr
= si_load_sampler_desc(ctx
, list
, index
,
1217 *samp_ptr
= sici_fix_sampler_aniso(ctx
, *res_ptr
, *samp_ptr
);
1222 static void txq_emit(const struct lp_build_tgsi_action
*action
,
1223 struct lp_build_tgsi_context
*bld_base
,
1224 struct lp_build_emit_data
*emit_data
)
1226 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1227 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
1228 unsigned target
= inst
->Texture
.Texture
;
1229 struct ac_image_args args
= {};
1231 tex_fetch_ptrs(bld_base
, emit_data
, &args
.resource
, NULL
, NULL
);
1233 if (target
== TGSI_TEXTURE_BUFFER
) {
1234 /* Read the size from the buffer descriptor directly. */
1235 emit_data
->output
[emit_data
->chan
] =
1236 get_buffer_size(bld_base
, args
.resource
);
1240 args
.opcode
= ac_image_get_resinfo
;
1241 args
.dim
= ac_texture_dim_from_tgsi_target(ctx
->screen
, target
);
1242 args
.lod
= lp_build_emit_fetch(bld_base
, inst
, 0, TGSI_CHAN_X
);
1245 LLVMValueRef result
= ac_build_image_opcode(&ctx
->ac
, &args
);
1247 emit_data
->output
[emit_data
->chan
] = fix_resinfo(ctx
, target
, result
);
1250 /* Gather4 should follow the same rules as bilinear filtering, but the hardware
1251 * incorrectly forces nearest filtering if the texture format is integer.
1252 * The only effect it has on Gather4, which always returns 4 texels for
1253 * bilinear filtering, is that the final coordinates are off by 0.5 of
1256 * The workaround is to subtract 0.5 from the unnormalized coordinates,
1257 * or (0.5 / size) from the normalized coordinates.
1259 * However, cube textures with 8_8_8_8 data formats require a different
1260 * workaround of overriding the num format to USCALED/SSCALED. This would lose
1261 * precision in 32-bit data formats, so it needs to be applied dynamically at
1262 * runtime. In this case, return an i1 value that indicates whether the
1263 * descriptor was overridden (and hence a fixup of the sampler result is needed).
1266 si_lower_gather4_integer(struct si_shader_context
*ctx
,
1267 struct ac_image_args
*args
,
1269 enum tgsi_return_type return_type
)
1271 LLVMBuilderRef builder
= ctx
->ac
.builder
;
1272 LLVMValueRef wa_8888
= NULL
;
1273 LLVMValueRef half_texel
[2];
1275 assert(return_type
== TGSI_RETURN_TYPE_SINT
||
1276 return_type
== TGSI_RETURN_TYPE_UINT
);
1278 if (target
== TGSI_TEXTURE_CUBE
||
1279 target
== TGSI_TEXTURE_CUBE_ARRAY
) {
1280 LLVMValueRef formats
;
1281 LLVMValueRef data_format
;
1282 LLVMValueRef wa_formats
;
1284 formats
= LLVMBuildExtractElement(builder
, args
->resource
, ctx
->i32_1
, "");
1286 data_format
= LLVMBuildLShr(builder
, formats
,
1287 LLVMConstInt(ctx
->i32
, 20, false), "");
1288 data_format
= LLVMBuildAnd(builder
, data_format
,
1289 LLVMConstInt(ctx
->i32
, (1u << 6) - 1, false), "");
1290 wa_8888
= LLVMBuildICmp(
1291 builder
, LLVMIntEQ
, data_format
,
1292 LLVMConstInt(ctx
->i32
, V_008F14_IMG_DATA_FORMAT_8_8_8_8
, false),
1295 uint32_t wa_num_format
=
1296 return_type
== TGSI_RETURN_TYPE_UINT
?
1297 S_008F14_NUM_FORMAT_GFX6(V_008F14_IMG_NUM_FORMAT_USCALED
) :
1298 S_008F14_NUM_FORMAT_GFX6(V_008F14_IMG_NUM_FORMAT_SSCALED
);
1299 wa_formats
= LLVMBuildAnd(builder
, formats
,
1300 LLVMConstInt(ctx
->i32
, C_008F14_NUM_FORMAT_GFX6
, false),
1302 wa_formats
= LLVMBuildOr(builder
, wa_formats
,
1303 LLVMConstInt(ctx
->i32
, wa_num_format
, false), "");
1305 formats
= LLVMBuildSelect(builder
, wa_8888
, wa_formats
, formats
, "");
1306 args
->resource
= LLVMBuildInsertElement(
1307 builder
, args
->resource
, formats
, ctx
->i32_1
, "");
1310 if (target
== TGSI_TEXTURE_RECT
||
1311 target
== TGSI_TEXTURE_SHADOWRECT
) {
1313 half_texel
[0] = half_texel
[1] = LLVMConstReal(ctx
->f32
, -0.5);
1315 struct ac_image_args resinfo
= {};
1316 struct lp_build_if_state if_ctx
;
1319 /* Skip the texture size query entirely if we don't need it. */
1320 lp_build_if(&if_ctx
, &ctx
->gallivm
, LLVMBuildNot(builder
, wa_8888
, ""));
1323 /* Query the texture size. */
1324 resinfo
.opcode
= ac_image_get_resinfo
;
1325 resinfo
.dim
= ac_texture_dim_from_tgsi_target(ctx
->screen
, target
);
1326 resinfo
.resource
= args
->resource
;
1327 resinfo
.sampler
= args
->sampler
;
1328 resinfo
.lod
= ctx
->ac
.i32_0
;
1329 resinfo
.dmask
= 0xf;
1331 LLVMValueRef texsize
=
1332 fix_resinfo(ctx
, target
,
1333 ac_build_image_opcode(&ctx
->ac
, &resinfo
));
1335 /* Compute -0.5 / size. */
1336 for (unsigned c
= 0; c
< 2; c
++) {
1338 LLVMBuildExtractElement(builder
, texsize
,
1339 LLVMConstInt(ctx
->i32
, c
, 0), "");
1340 half_texel
[c
] = LLVMBuildUIToFP(builder
, half_texel
[c
], ctx
->f32
, "");
1341 half_texel
[c
] = ac_build_fdiv(&ctx
->ac
, ctx
->ac
.f32_1
, half_texel
[c
]);
1342 half_texel
[c
] = LLVMBuildFMul(builder
, half_texel
[c
],
1343 LLVMConstReal(ctx
->f32
, -0.5), "");
1347 lp_build_endif(&if_ctx
);
1349 LLVMBasicBlockRef bb
[2] = { if_ctx
.true_block
, if_ctx
.entry_block
};
1351 for (unsigned c
= 0; c
< 2; c
++) {
1352 LLVMValueRef values
[2] = { half_texel
[c
], ctx
->ac
.f32_0
};
1353 half_texel
[c
] = ac_build_phi(&ctx
->ac
, ctx
->f32
, 2,
1359 for (unsigned c
= 0; c
< 2; c
++) {
1361 tmp
= ac_to_float(&ctx
->ac
, args
->coords
[c
]);
1362 tmp
= LLVMBuildFAdd(builder
, tmp
, half_texel
[c
], "");
1363 args
->coords
[c
] = ac_to_integer(&ctx
->ac
, tmp
);
1369 /* The second half of the cube texture 8_8_8_8 integer workaround: adjust the
1370 * result after the gather operation.
1373 si_fix_gather4_integer_result(struct si_shader_context
*ctx
,
1374 LLVMValueRef result
,
1375 enum tgsi_return_type return_type
,
1378 LLVMBuilderRef builder
= ctx
->ac
.builder
;
1380 assert(return_type
== TGSI_RETURN_TYPE_SINT
||
1381 return_type
== TGSI_RETURN_TYPE_UINT
);
1383 for (unsigned chan
= 0; chan
< 4; ++chan
) {
1384 LLVMValueRef chanv
= LLVMConstInt(ctx
->i32
, chan
, false);
1386 LLVMValueRef wa_value
;
1388 value
= LLVMBuildExtractElement(builder
, result
, chanv
, "");
1390 if (return_type
== TGSI_RETURN_TYPE_UINT
)
1391 wa_value
= LLVMBuildFPToUI(builder
, value
, ctx
->i32
, "");
1393 wa_value
= LLVMBuildFPToSI(builder
, value
, ctx
->i32
, "");
1394 wa_value
= ac_to_float(&ctx
->ac
, wa_value
);
1395 value
= LLVMBuildSelect(builder
, wa
, wa_value
, value
, "");
1397 result
= LLVMBuildInsertElement(builder
, result
, value
, chanv
, "");
1403 static void build_tex_intrinsic(const struct lp_build_tgsi_action
*action
,
1404 struct lp_build_tgsi_context
*bld_base
,
1405 struct lp_build_emit_data
*emit_data
)
1407 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1408 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
1409 unsigned opcode
= inst
->Instruction
.Opcode
;
1410 unsigned target
= inst
->Texture
.Texture
;
1411 struct ac_image_args args
= {};
1412 int ref_pos
= tgsi_util_get_shadow_ref_src_index(target
);
1414 bool has_offset
= inst
->Texture
.NumOffsets
> 0;
1415 LLVMValueRef fmask_ptr
= NULL
;
1417 tex_fetch_ptrs(bld_base
, emit_data
, &args
.resource
, &args
.sampler
, &fmask_ptr
);
1419 if (target
== TGSI_TEXTURE_BUFFER
) {
1420 LLVMValueRef vindex
= lp_build_emit_fetch(bld_base
, inst
, 0, TGSI_CHAN_X
);
1421 unsigned num_channels
=
1422 util_last_bit(inst
->Dst
[0].Register
.WriteMask
);
1423 LLVMValueRef result
=
1424 ac_build_buffer_load_format(&ctx
->ac
,
1428 num_channels
, false, true);
1429 emit_data
->output
[emit_data
->chan
] =
1430 ac_build_expand_to_vec4(&ctx
->ac
, result
, num_channels
);
1434 /* Fetch and project texture coordinates */
1435 args
.coords
[3] = lp_build_emit_fetch(bld_base
, inst
, 0, TGSI_CHAN_W
);
1436 for (chan
= 0; chan
< 3; chan
++) {
1437 args
.coords
[chan
] = lp_build_emit_fetch(bld_base
, inst
, 0, chan
);
1438 if (opcode
== TGSI_OPCODE_TXP
)
1439 args
.coords
[chan
] = ac_build_fdiv(&ctx
->ac
,
1440 args
.coords
[chan
], args
.coords
[3]);
1443 if (opcode
== TGSI_OPCODE_TXP
)
1444 args
.coords
[3] = ctx
->ac
.f32_1
;
1448 opcode
!= TGSI_OPCODE_TXF
&&
1449 opcode
!= TGSI_OPCODE_TXF_LZ
) {
1450 /* The offsets are six-bit signed integers packed like this:
1451 * X=[5:0], Y=[13:8], and Z=[21:16].
1453 LLVMValueRef offset
[3], pack
;
1455 assert(inst
->Texture
.NumOffsets
== 1);
1457 for (chan
= 0; chan
< 3; chan
++) {
1458 offset
[chan
] = lp_build_emit_fetch_texoffset(bld_base
, inst
, 0, chan
);
1459 offset
[chan
] = LLVMBuildAnd(ctx
->ac
.builder
, offset
[chan
],
1460 LLVMConstInt(ctx
->i32
, 0x3f, 0), "");
1462 offset
[chan
] = LLVMBuildShl(ctx
->ac
.builder
, offset
[chan
],
1463 LLVMConstInt(ctx
->i32
, chan
*8, 0), "");
1466 pack
= LLVMBuildOr(ctx
->ac
.builder
, offset
[0], offset
[1], "");
1467 pack
= LLVMBuildOr(ctx
->ac
.builder
, pack
, offset
[2], "");
1471 /* Pack LOD bias value */
1472 if (opcode
== TGSI_OPCODE_TXB
)
1473 args
.bias
= args
.coords
[3];
1474 if (opcode
== TGSI_OPCODE_TXB2
)
1475 args
.bias
= lp_build_emit_fetch(bld_base
, inst
, 1, TGSI_CHAN_X
);
1477 /* Pack depth comparison value */
1478 if (tgsi_is_shadow_target(target
) && opcode
!= TGSI_OPCODE_LODQ
) {
1481 if (target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
1482 z
= lp_build_emit_fetch(bld_base
, inst
, 1, TGSI_CHAN_X
);
1484 assert(ref_pos
>= 0);
1485 z
= args
.coords
[ref_pos
];
1488 /* Section 8.23.1 (Depth Texture Comparison Mode) of the
1489 * OpenGL 4.5 spec says:
1491 * "If the texture’s internal format indicates a fixed-point
1492 * depth texture, then D_t and D_ref are clamped to the
1493 * range [0, 1]; otherwise no clamping is performed."
1495 * TC-compatible HTILE promotes Z16 and Z24 to Z32_FLOAT,
1496 * so the depth comparison value isn't clamped for Z16 and
1497 * Z24 anymore. Do it manually here.
1499 if (ctx
->screen
->info
.chip_class
>= VI
) {
1500 LLVMValueRef upgraded
;
1501 LLVMValueRef clamped
;
1502 upgraded
= LLVMBuildExtractElement(ctx
->ac
.builder
, args
.sampler
,
1503 LLVMConstInt(ctx
->i32
, 3, false), "");
1504 upgraded
= LLVMBuildLShr(ctx
->ac
.builder
, upgraded
,
1505 LLVMConstInt(ctx
->i32
, 29, false), "");
1506 upgraded
= LLVMBuildTrunc(ctx
->ac
.builder
, upgraded
, ctx
->i1
, "");
1507 clamped
= ac_build_clamp(&ctx
->ac
, z
);
1508 z
= LLVMBuildSelect(ctx
->ac
.builder
, upgraded
, clamped
, z
, "");
1514 /* Pack user derivatives */
1515 if (opcode
== TGSI_OPCODE_TXD
) {
1516 int param
, num_src_deriv_channels
, num_dst_deriv_channels
;
1519 case TGSI_TEXTURE_3D
:
1520 num_src_deriv_channels
= 3;
1521 num_dst_deriv_channels
= 3;
1523 case TGSI_TEXTURE_2D
:
1524 case TGSI_TEXTURE_SHADOW2D
:
1525 case TGSI_TEXTURE_RECT
:
1526 case TGSI_TEXTURE_SHADOWRECT
:
1527 case TGSI_TEXTURE_2D_ARRAY
:
1528 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
1529 num_src_deriv_channels
= 2;
1530 num_dst_deriv_channels
= 2;
1532 case TGSI_TEXTURE_CUBE
:
1533 case TGSI_TEXTURE_SHADOWCUBE
:
1534 case TGSI_TEXTURE_CUBE_ARRAY
:
1535 case TGSI_TEXTURE_SHADOWCUBE_ARRAY
:
1536 /* Cube derivatives will be converted to 2D. */
1537 num_src_deriv_channels
= 3;
1538 num_dst_deriv_channels
= 3;
1540 case TGSI_TEXTURE_1D
:
1541 case TGSI_TEXTURE_SHADOW1D
:
1542 case TGSI_TEXTURE_1D_ARRAY
:
1543 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
1544 num_src_deriv_channels
= 1;
1546 /* 1D textures are allocated and used as 2D on GFX9. */
1547 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
1548 num_dst_deriv_channels
= 2;
1550 num_dst_deriv_channels
= 1;
1554 unreachable("invalid target");
1557 for (param
= 0; param
< 2; param
++) {
1558 for (chan
= 0; chan
< num_src_deriv_channels
; chan
++)
1559 args
.derivs
[param
* num_dst_deriv_channels
+ chan
] =
1560 lp_build_emit_fetch(bld_base
, inst
, param
+1, chan
);
1562 /* Fill in the rest with zeros. */
1563 for (chan
= num_src_deriv_channels
;
1564 chan
< num_dst_deriv_channels
; chan
++)
1565 args
.derivs
[param
* num_dst_deriv_channels
+ chan
] =
1570 if (target
== TGSI_TEXTURE_CUBE
||
1571 target
== TGSI_TEXTURE_CUBE_ARRAY
||
1572 target
== TGSI_TEXTURE_SHADOWCUBE
||
1573 target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
1574 ac_prepare_cube_coords(&ctx
->ac
,
1575 opcode
== TGSI_OPCODE_TXD
,
1576 target
== TGSI_TEXTURE_CUBE_ARRAY
||
1577 target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
,
1578 opcode
== TGSI_OPCODE_LODQ
,
1579 args
.coords
, args
.derivs
);
1580 } else if (tgsi_is_array_sampler(target
) &&
1581 opcode
!= TGSI_OPCODE_TXF
&&
1582 opcode
!= TGSI_OPCODE_TXF_LZ
&&
1583 ctx
->screen
->info
.chip_class
<= VI
) {
1584 unsigned array_coord
= target
== TGSI_TEXTURE_1D_ARRAY
? 1 : 2;
1585 args
.coords
[array_coord
] =
1586 ac_build_intrinsic(&ctx
->ac
, "llvm.rint.f32", ctx
->f32
,
1587 &args
.coords
[array_coord
], 1, 0);
1590 /* 1D textures are allocated and used as 2D on GFX9. */
1591 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
1592 LLVMValueRef filler
;
1594 /* Use 0.5, so that we don't sample the border color. */
1595 if (opcode
== TGSI_OPCODE_TXF
||
1596 opcode
== TGSI_OPCODE_TXF_LZ
)
1597 filler
= ctx
->i32_0
;
1599 filler
= LLVMConstReal(ctx
->f32
, 0.5);
1601 if (target
== TGSI_TEXTURE_1D
||
1602 target
== TGSI_TEXTURE_SHADOW1D
) {
1603 args
.coords
[1] = filler
;
1604 } else if (target
== TGSI_TEXTURE_1D_ARRAY
||
1605 target
== TGSI_TEXTURE_SHADOW1D_ARRAY
) {
1606 args
.coords
[2] = args
.coords
[1];
1607 args
.coords
[1] = filler
;
1611 /* Pack LOD or sample index */
1612 if (opcode
== TGSI_OPCODE_TXL
)
1613 args
.lod
= args
.coords
[3];
1614 else if (opcode
== TGSI_OPCODE_TXL2
)
1615 args
.lod
= lp_build_emit_fetch(bld_base
, inst
, 1, TGSI_CHAN_X
);
1616 else if (opcode
== TGSI_OPCODE_TXF
) {
1617 if (target
== TGSI_TEXTURE_2D_MSAA
) {
1618 /* No LOD, but move sample index into the right place. */
1619 args
.coords
[2] = args
.coords
[3];
1620 } else if (target
!= TGSI_TEXTURE_2D_ARRAY_MSAA
) {
1621 args
.lod
= args
.coords
[3];
1625 if (target
== TGSI_TEXTURE_2D_MSAA
||
1626 target
== TGSI_TEXTURE_2D_ARRAY_MSAA
) {
1627 ac_apply_fmask_to_sample(&ctx
->ac
, fmask_ptr
, args
.coords
,
1628 target
== TGSI_TEXTURE_2D_ARRAY_MSAA
);
1631 if (opcode
== TGSI_OPCODE_TXF
||
1632 opcode
== TGSI_OPCODE_TXF_LZ
) {
1633 /* add tex offsets */
1634 if (inst
->Texture
.NumOffsets
) {
1635 const struct tgsi_texture_offset
*off
= inst
->TexOffsets
;
1637 assert(inst
->Texture
.NumOffsets
== 1);
1640 case TGSI_TEXTURE_3D
:
1642 LLVMBuildAdd(ctx
->ac
.builder
, args
.coords
[2],
1643 ctx
->imms
[off
->Index
* TGSI_NUM_CHANNELS
+ off
->SwizzleZ
], "");
1645 case TGSI_TEXTURE_2D
:
1646 case TGSI_TEXTURE_SHADOW2D
:
1647 case TGSI_TEXTURE_RECT
:
1648 case TGSI_TEXTURE_SHADOWRECT
:
1649 case TGSI_TEXTURE_2D_ARRAY
:
1650 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
1652 LLVMBuildAdd(ctx
->ac
.builder
, args
.coords
[1],
1653 ctx
->imms
[off
->Index
* TGSI_NUM_CHANNELS
+ off
->SwizzleY
], "");
1655 case TGSI_TEXTURE_1D
:
1656 case TGSI_TEXTURE_SHADOW1D
:
1657 case TGSI_TEXTURE_1D_ARRAY
:
1658 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
1660 LLVMBuildAdd(ctx
->ac
.builder
, args
.coords
[0],
1661 ctx
->imms
[off
->Index
* TGSI_NUM_CHANNELS
+ off
->SwizzleX
], "");
1663 /* texture offsets do not apply to other texture targets */
1668 if (opcode
== TGSI_OPCODE_TG4
) {
1669 unsigned gather_comp
= 0;
1671 /* DMASK was repurposed for GATHER4. 4 components are always
1672 * returned and DMASK works like a swizzle - it selects
1673 * the component to fetch. The only valid DMASK values are
1674 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
1675 * (red,red,red,red) etc.) The ISA document doesn't mention
1679 /* Get the component index from src1.x for Gather4. */
1680 if (!tgsi_is_shadow_target(target
)) {
1681 LLVMValueRef comp_imm
;
1682 struct tgsi_src_register src1
= inst
->Src
[1].Register
;
1684 assert(src1
.File
== TGSI_FILE_IMMEDIATE
);
1686 comp_imm
= ctx
->imms
[src1
.Index
* TGSI_NUM_CHANNELS
+ src1
.SwizzleX
];
1687 gather_comp
= LLVMConstIntGetZExtValue(comp_imm
);
1688 gather_comp
= CLAMP(gather_comp
, 0, 3);
1691 args
.dmask
= 1 << gather_comp
;
1696 args
.dim
= ac_texture_dim_from_tgsi_target(ctx
->screen
, target
);
1697 args
.unorm
= target
== TGSI_TEXTURE_RECT
||
1698 target
== TGSI_TEXTURE_SHADOWRECT
;
1699 args
.opcode
= ac_image_sample
;
1702 case TGSI_OPCODE_TXF
:
1703 case TGSI_OPCODE_TXF_LZ
:
1704 args
.opcode
= opcode
== TGSI_OPCODE_TXF_LZ
||
1705 target
== TGSI_TEXTURE_2D_MSAA
||
1706 target
== TGSI_TEXTURE_2D_ARRAY_MSAA
?
1707 ac_image_load
: ac_image_load_mip
;
1709 case TGSI_OPCODE_LODQ
:
1710 args
.opcode
= ac_image_get_lod
;
1712 case TGSI_OPCODE_TEX
:
1713 case TGSI_OPCODE_TEX2
:
1714 case TGSI_OPCODE_TXP
:
1715 if (ctx
->type
!= PIPE_SHADER_FRAGMENT
)
1716 args
.level_zero
= true;
1718 case TGSI_OPCODE_TEX_LZ
:
1719 args
.level_zero
= true;
1721 case TGSI_OPCODE_TXB
:
1722 case TGSI_OPCODE_TXB2
:
1723 assert(ctx
->type
== PIPE_SHADER_FRAGMENT
);
1725 case TGSI_OPCODE_TXL
:
1726 case TGSI_OPCODE_TXL2
:
1728 case TGSI_OPCODE_TXD
:
1730 case TGSI_OPCODE_TG4
:
1731 args
.opcode
= ac_image_gather4
;
1732 args
.level_zero
= true;
1739 /* The hardware needs special lowering for Gather4 with integer formats. */
1740 LLVMValueRef gather4_int_result_workaround
= NULL
;
1742 if (ctx
->screen
->info
.chip_class
<= VI
&&
1743 opcode
== TGSI_OPCODE_TG4
) {
1744 assert(inst
->Texture
.ReturnType
!= TGSI_RETURN_TYPE_UNKNOWN
);
1746 if (inst
->Texture
.ReturnType
== TGSI_RETURN_TYPE_SINT
||
1747 inst
->Texture
.ReturnType
== TGSI_RETURN_TYPE_UINT
) {
1748 gather4_int_result_workaround
=
1749 si_lower_gather4_integer(ctx
, &args
, target
,
1750 inst
->Texture
.ReturnType
);
1754 args
.attributes
= AC_FUNC_ATTR_READNONE
;
1755 LLVMValueRef result
= ac_build_image_opcode(&ctx
->ac
, &args
);
1757 if (gather4_int_result_workaround
) {
1758 result
= si_fix_gather4_integer_result(ctx
, result
,
1759 inst
->Texture
.ReturnType
,
1760 gather4_int_result_workaround
);
1763 emit_data
->output
[emit_data
->chan
] = result
;
1766 static void si_llvm_emit_txqs(
1767 const struct lp_build_tgsi_action
*action
,
1768 struct lp_build_tgsi_context
*bld_base
,
1769 struct lp_build_emit_data
*emit_data
)
1771 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1772 LLVMValueRef res
, samples
;
1773 LLVMValueRef res_ptr
, samp_ptr
, fmask_ptr
= NULL
;
1775 tex_fetch_ptrs(bld_base
, emit_data
, &res_ptr
, &samp_ptr
, &fmask_ptr
);
1777 /* Read the samples from the descriptor directly. */
1778 res
= LLVMBuildBitCast(ctx
->ac
.builder
, res_ptr
, ctx
->v8i32
, "");
1779 samples
= LLVMBuildExtractElement(ctx
->ac
.builder
, res
,
1780 LLVMConstInt(ctx
->i32
, 3, 0), "");
1781 samples
= LLVMBuildLShr(ctx
->ac
.builder
, samples
,
1782 LLVMConstInt(ctx
->i32
, 16, 0), "");
1783 samples
= LLVMBuildAnd(ctx
->ac
.builder
, samples
,
1784 LLVMConstInt(ctx
->i32
, 0xf, 0), "");
1785 samples
= LLVMBuildShl(ctx
->ac
.builder
, ctx
->i32_1
,
1788 emit_data
->output
[emit_data
->chan
] = samples
;
1791 static void si_llvm_emit_fbfetch(const struct lp_build_tgsi_action
*action
,
1792 struct lp_build_tgsi_context
*bld_base
,
1793 struct lp_build_emit_data
*emit_data
)
1795 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1796 struct ac_image_args args
= {};
1797 LLVMValueRef ptr
, image
, fmask
;
1799 /* Ignore src0, because KHR_blend_func_extended disallows multiple render
1803 /* Load the image descriptor. */
1804 STATIC_ASSERT(SI_PS_IMAGE_COLORBUF0
% 2 == 0);
1805 ptr
= LLVMGetParam(ctx
->main_fn
, ctx
->param_rw_buffers
);
1806 ptr
= LLVMBuildPointerCast(ctx
->ac
.builder
, ptr
,
1807 ac_array_in_const32_addr_space(ctx
->v8i32
), "");
1808 image
= ac_build_load_to_sgpr(&ctx
->ac
, ptr
,
1809 LLVMConstInt(ctx
->i32
, SI_PS_IMAGE_COLORBUF0
/ 2, 0));
1813 args
.coords
[chan
++] = si_unpack_param(ctx
, SI_PARAM_POS_FIXED_PT
, 0, 16);
1815 if (!ctx
->shader
->key
.mono
.u
.ps
.fbfetch_is_1D
)
1816 args
.coords
[chan
++] = si_unpack_param(ctx
, SI_PARAM_POS_FIXED_PT
, 16, 16);
1818 /* Get the current render target layer index. */
1819 if (ctx
->shader
->key
.mono
.u
.ps
.fbfetch_layered
)
1820 args
.coords
[chan
++] = si_unpack_param(ctx
, SI_PARAM_ANCILLARY
, 16, 11);
1822 if (ctx
->shader
->key
.mono
.u
.ps
.fbfetch_msaa
)
1823 args
.coords
[chan
++] = si_get_sample_id(ctx
);
1825 if (ctx
->shader
->key
.mono
.u
.ps
.fbfetch_msaa
) {
1826 fmask
= ac_build_load_to_sgpr(&ctx
->ac
, ptr
,
1827 LLVMConstInt(ctx
->i32
, SI_PS_IMAGE_COLORBUF0_FMASK
/ 2, 0));
1829 ac_apply_fmask_to_sample(&ctx
->ac
, fmask
, args
.coords
,
1830 ctx
->shader
->key
.mono
.u
.ps
.fbfetch_layered
);
1833 args
.opcode
= ac_image_load
;
1834 args
.resource
= image
;
1836 if (ctx
->shader
->key
.mono
.u
.ps
.fbfetch_msaa
)
1837 args
.dim
= ctx
->shader
->key
.mono
.u
.ps
.fbfetch_layered
?
1838 ac_image_2darraymsaa
: ac_image_2dmsaa
;
1839 else if (ctx
->shader
->key
.mono
.u
.ps
.fbfetch_is_1D
)
1840 args
.dim
= ctx
->shader
->key
.mono
.u
.ps
.fbfetch_layered
?
1841 ac_image_1darray
: ac_image_1d
;
1843 args
.dim
= ctx
->shader
->key
.mono
.u
.ps
.fbfetch_layered
?
1844 ac_image_2darray
: ac_image_2d
;
1846 emit_data
->output
[emit_data
->chan
] =
1847 ac_build_image_opcode(&ctx
->ac
, &args
);
1851 * Setup actions for TGSI memory opcode, including texture opcodes.
1853 void si_shader_context_init_mem(struct si_shader_context
*ctx
)
1855 struct lp_build_tgsi_context
*bld_base
;
1856 struct lp_build_tgsi_action tmpl
= {};
1858 bld_base
= &ctx
->bld_base
;
1860 bld_base
->op_actions
[TGSI_OPCODE_TEX
].emit
= build_tex_intrinsic
;
1861 bld_base
->op_actions
[TGSI_OPCODE_TEX_LZ
].emit
= build_tex_intrinsic
;
1862 bld_base
->op_actions
[TGSI_OPCODE_TEX2
].emit
= build_tex_intrinsic
;
1863 bld_base
->op_actions
[TGSI_OPCODE_TXB
].emit
= build_tex_intrinsic
;
1864 bld_base
->op_actions
[TGSI_OPCODE_TXB2
].emit
= build_tex_intrinsic
;
1865 bld_base
->op_actions
[TGSI_OPCODE_TXD
].emit
= build_tex_intrinsic
;
1866 bld_base
->op_actions
[TGSI_OPCODE_TXF
].emit
= build_tex_intrinsic
;
1867 bld_base
->op_actions
[TGSI_OPCODE_TXF_LZ
].emit
= build_tex_intrinsic
;
1868 bld_base
->op_actions
[TGSI_OPCODE_TXL
].emit
= build_tex_intrinsic
;
1869 bld_base
->op_actions
[TGSI_OPCODE_TXL2
].emit
= build_tex_intrinsic
;
1870 bld_base
->op_actions
[TGSI_OPCODE_TXP
].emit
= build_tex_intrinsic
;
1871 bld_base
->op_actions
[TGSI_OPCODE_TXQ
].emit
= txq_emit
;
1872 bld_base
->op_actions
[TGSI_OPCODE_TG4
].emit
= build_tex_intrinsic
;
1873 bld_base
->op_actions
[TGSI_OPCODE_LODQ
].emit
= build_tex_intrinsic
;
1874 bld_base
->op_actions
[TGSI_OPCODE_TXQS
].emit
= si_llvm_emit_txqs
;
1876 bld_base
->op_actions
[TGSI_OPCODE_FBFETCH
].emit
= si_llvm_emit_fbfetch
;
1878 bld_base
->op_actions
[TGSI_OPCODE_LOAD
].fetch_args
= load_fetch_args
;
1879 bld_base
->op_actions
[TGSI_OPCODE_LOAD
].emit
= load_emit
;
1880 bld_base
->op_actions
[TGSI_OPCODE_STORE
].fetch_args
= store_fetch_args
;
1881 bld_base
->op_actions
[TGSI_OPCODE_STORE
].emit
= store_emit
;
1882 bld_base
->op_actions
[TGSI_OPCODE_RESQ
].fetch_args
= resq_fetch_args
;
1883 bld_base
->op_actions
[TGSI_OPCODE_RESQ
].emit
= resq_emit
;
1885 tmpl
.fetch_args
= atomic_fetch_args
;
1886 tmpl
.emit
= atomic_emit
;
1887 bld_base
->op_actions
[TGSI_OPCODE_ATOMUADD
] = tmpl
;
1888 bld_base
->op_actions
[TGSI_OPCODE_ATOMUADD
].intr_name
= "add";
1889 bld_base
->op_actions
[TGSI_OPCODE_ATOMXCHG
] = tmpl
;
1890 bld_base
->op_actions
[TGSI_OPCODE_ATOMXCHG
].intr_name
= "swap";
1891 bld_base
->op_actions
[TGSI_OPCODE_ATOMCAS
] = tmpl
;
1892 bld_base
->op_actions
[TGSI_OPCODE_ATOMCAS
].intr_name
= "cmpswap";
1893 bld_base
->op_actions
[TGSI_OPCODE_ATOMAND
] = tmpl
;
1894 bld_base
->op_actions
[TGSI_OPCODE_ATOMAND
].intr_name
= "and";
1895 bld_base
->op_actions
[TGSI_OPCODE_ATOMOR
] = tmpl
;
1896 bld_base
->op_actions
[TGSI_OPCODE_ATOMOR
].intr_name
= "or";
1897 bld_base
->op_actions
[TGSI_OPCODE_ATOMXOR
] = tmpl
;
1898 bld_base
->op_actions
[TGSI_OPCODE_ATOMXOR
].intr_name
= "xor";
1899 bld_base
->op_actions
[TGSI_OPCODE_ATOMUMIN
] = tmpl
;
1900 bld_base
->op_actions
[TGSI_OPCODE_ATOMUMIN
].intr_name
= "umin";
1901 bld_base
->op_actions
[TGSI_OPCODE_ATOMUMAX
] = tmpl
;
1902 bld_base
->op_actions
[TGSI_OPCODE_ATOMUMAX
].intr_name
= "umax";
1903 bld_base
->op_actions
[TGSI_OPCODE_ATOMIMIN
] = tmpl
;
1904 bld_base
->op_actions
[TGSI_OPCODE_ATOMIMIN
].intr_name
= "smin";
1905 bld_base
->op_actions
[TGSI_OPCODE_ATOMIMAX
] = tmpl
;
1906 bld_base
->op_actions
[TGSI_OPCODE_ATOMIMAX
].intr_name
= "smax";