2 * Copyright 2017 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "si_shader_internal.h"
28 #include "gallivm/lp_bld_arit.h"
29 #include "gallivm/lp_bld_intr.h"
30 #include "tgsi/tgsi_build.h"
31 #include "tgsi/tgsi_util.h"
32 #include "ac_llvm_util.h"
34 static void build_tex_intrinsic(const struct lp_build_tgsi_action
*action
,
35 struct lp_build_tgsi_context
*bld_base
,
36 struct lp_build_emit_data
*emit_data
);
38 static const struct lp_build_tgsi_action tex_action
;
41 * Given a v8i32 resource descriptor for a buffer, extract the size of the
42 * buffer in number of elements and return it as an i32.
44 static LLVMValueRef
get_buffer_size(
45 struct lp_build_tgsi_context
*bld_base
,
46 LLVMValueRef descriptor
)
48 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
49 LLVMBuilderRef builder
= ctx
->ac
.builder
;
51 LLVMBuildExtractElement(builder
, descriptor
,
52 LLVMConstInt(ctx
->i32
, 2, 0), "");
54 if (ctx
->screen
->info
.chip_class
== VI
) {
55 /* On VI, the descriptor contains the size in bytes,
56 * but TXQ must return the size in elements.
57 * The stride is always non-zero for resources using TXQ.
60 LLVMBuildExtractElement(builder
, descriptor
,
62 stride
= LLVMBuildLShr(builder
, stride
,
63 LLVMConstInt(ctx
->i32
, 16, 0), "");
64 stride
= LLVMBuildAnd(builder
, stride
,
65 LLVMConstInt(ctx
->i32
, 0x3FFF, 0), "");
67 size
= LLVMBuildUDiv(builder
, size
, stride
, "");
74 shader_buffer_fetch_rsrc(struct si_shader_context
*ctx
,
75 const struct tgsi_full_src_register
*reg
,
80 if (!reg
->Register
.Indirect
) {
81 index
= LLVMConstInt(ctx
->i32
, reg
->Register
.Index
, false);
83 index
= si_get_indirect_index(ctx
, ®
->Indirect
,
84 1, reg
->Register
.Index
);
88 return ctx
->abi
.load_ubo(&ctx
->abi
, index
);
90 return ctx
->abi
.load_ssbo(&ctx
->abi
, index
, false);
93 static enum ac_image_dim
94 ac_texture_dim_from_tgsi_target(struct si_screen
*screen
, enum tgsi_texture_type target
)
98 case TGSI_TEXTURE_SHADOW1D
:
99 if (screen
->info
.chip_class
>= GFX9
)
102 case TGSI_TEXTURE_2D
:
103 case TGSI_TEXTURE_SHADOW2D
:
104 case TGSI_TEXTURE_RECT
:
105 case TGSI_TEXTURE_SHADOWRECT
:
107 case TGSI_TEXTURE_3D
:
109 case TGSI_TEXTURE_CUBE
:
110 case TGSI_TEXTURE_SHADOWCUBE
:
111 case TGSI_TEXTURE_CUBE_ARRAY
:
112 case TGSI_TEXTURE_SHADOWCUBE_ARRAY
:
113 return ac_image_cube
;
114 case TGSI_TEXTURE_1D_ARRAY
:
115 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
116 if (screen
->info
.chip_class
>= GFX9
)
117 return ac_image_2darray
;
118 return ac_image_1darray
;
119 case TGSI_TEXTURE_2D_ARRAY
:
120 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
121 return ac_image_2darray
;
122 case TGSI_TEXTURE_2D_MSAA
:
123 return ac_image_2dmsaa
;
124 case TGSI_TEXTURE_2D_ARRAY_MSAA
:
125 return ac_image_2darraymsaa
;
127 unreachable("unhandled texture type");
131 static enum ac_image_dim
132 ac_image_dim_from_tgsi_target(struct si_screen
*screen
, enum tgsi_texture_type target
)
134 enum ac_image_dim dim
= ac_texture_dim_from_tgsi_target(screen
, target
);
136 /* Match the resource type set in the descriptor. */
137 if (dim
== ac_image_cube
||
138 (screen
->info
.chip_class
<= VI
&& dim
== ac_image_3d
))
139 dim
= ac_image_2darray
;
140 else if (target
== TGSI_TEXTURE_2D
&& screen
->info
.chip_class
>= GFX9
) {
141 /* When a single layer of a 3D texture is bound, the shader
142 * will refer to a 2D target, but the descriptor has a 3D type.
143 * Since the HW ignores BASE_ARRAY in this case, we need to
144 * send 3 coordinates. This doesn't hurt when the underlying
154 * Given a 256-bit resource descriptor, force the DCC enable bit to off.
156 * At least on Tonga, executing image stores on images with DCC enabled and
157 * non-trivial can eventually lead to lockups. This can occur when an
158 * application binds an image as read-only but then uses a shader that writes
159 * to it. The OpenGL spec allows almost arbitrarily bad behavior (including
160 * program termination) in this case, but it doesn't cost much to be a bit
161 * nicer: disabling DCC in the shader still leads to undefined results but
164 static LLVMValueRef
force_dcc_off(struct si_shader_context
*ctx
,
167 if (ctx
->screen
->info
.chip_class
<= CIK
) {
170 LLVMValueRef i32_6
= LLVMConstInt(ctx
->i32
, 6, 0);
171 LLVMValueRef i32_C
= LLVMConstInt(ctx
->i32
, C_008F28_COMPRESSION_EN
, 0);
174 tmp
= LLVMBuildExtractElement(ctx
->ac
.builder
, rsrc
, i32_6
, "");
175 tmp
= LLVMBuildAnd(ctx
->ac
.builder
, tmp
, i32_C
, "");
176 return LLVMBuildInsertElement(ctx
->ac
.builder
, rsrc
, tmp
, i32_6
, "");
180 LLVMValueRef
si_load_image_desc(struct si_shader_context
*ctx
,
181 LLVMValueRef list
, LLVMValueRef index
,
182 enum ac_descriptor_type desc_type
, bool dcc_off
)
184 LLVMBuilderRef builder
= ctx
->ac
.builder
;
187 if (desc_type
== AC_DESC_BUFFER
) {
188 index
= LLVMBuildMul(builder
, index
,
189 LLVMConstInt(ctx
->i32
, 2, 0), "");
190 index
= LLVMBuildAdd(builder
, index
,
192 list
= LLVMBuildPointerCast(builder
, list
,
193 ac_array_in_const32_addr_space(ctx
->v4i32
), "");
195 assert(desc_type
== AC_DESC_IMAGE
);
198 rsrc
= ac_build_load_to_sgpr(&ctx
->ac
, list
, index
);
199 if (desc_type
== AC_DESC_IMAGE
&& dcc_off
)
200 rsrc
= force_dcc_off(ctx
, rsrc
);
205 * Load the resource descriptor for \p image.
209 struct lp_build_tgsi_context
*bld_base
,
210 const struct tgsi_full_src_register
*image
,
211 bool is_store
, unsigned target
,
214 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
215 LLVMValueRef rsrc_ptr
= LLVMGetParam(ctx
->main_fn
,
216 ctx
->param_samplers_and_images
);
218 bool dcc_off
= is_store
;
220 if (!image
->Register
.Indirect
) {
221 const struct tgsi_shader_info
*info
= bld_base
->info
;
222 unsigned images_writemask
= info
->images_store
|
225 index
= LLVMConstInt(ctx
->i32
,
226 si_get_image_slot(image
->Register
.Index
), 0);
228 if (images_writemask
& (1 << image
->Register
.Index
))
231 /* From the GL_ARB_shader_image_load_store extension spec:
233 * If a shader performs an image load, store, or atomic
234 * operation using an image variable declared as an array,
235 * and if the index used to select an individual element is
236 * negative or greater than or equal to the size of the
237 * array, the results of the operation are undefined but may
238 * not lead to termination.
240 index
= si_get_bounded_indirect_index(ctx
, &image
->Indirect
,
241 image
->Register
.Index
,
243 index
= LLVMBuildSub(ctx
->ac
.builder
,
244 LLVMConstInt(ctx
->i32
, SI_NUM_IMAGES
- 1, 0),
248 if (image
->Register
.File
!= TGSI_FILE_IMAGE
) {
249 /* Bindless descriptors are accessible from a different pair of
252 rsrc_ptr
= LLVMGetParam(ctx
->main_fn
,
253 ctx
->param_bindless_samplers_and_images
);
254 index
= lp_build_emit_fetch_src(bld_base
, image
,
255 TGSI_TYPE_UNSIGNED
, 0);
257 /* For simplicity, bindless image descriptors use fixed
258 * 16-dword slots for now.
260 index
= LLVMBuildMul(ctx
->ac
.builder
, index
,
261 LLVMConstInt(ctx
->i32
, 2, 0), "");
264 *rsrc
= si_load_image_desc(ctx
, rsrc_ptr
, index
,
265 target
== TGSI_TEXTURE_BUFFER
? AC_DESC_BUFFER
: AC_DESC_IMAGE
,
269 static void image_fetch_coords(
270 struct lp_build_tgsi_context
*bld_base
,
271 const struct tgsi_full_instruction
*inst
,
272 unsigned src
, LLVMValueRef desc
,
273 LLVMValueRef
*coords
)
275 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
276 LLVMBuilderRef builder
= ctx
->ac
.builder
;
277 unsigned target
= inst
->Memory
.Texture
;
278 unsigned num_coords
= tgsi_util_get_texture_coord_dim(target
);
282 if (target
== TGSI_TEXTURE_2D_MSAA
||
283 target
== TGSI_TEXTURE_2D_ARRAY_MSAA
) {
284 /* Need the sample index as well. */
288 for (chan
= 0; chan
< num_coords
; ++chan
) {
289 tmp
= lp_build_emit_fetch(bld_base
, inst
, src
, chan
);
290 tmp
= ac_to_integer(&ctx
->ac
, tmp
);
294 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
295 /* 1D textures are allocated and used as 2D on GFX9. */
296 if (target
== TGSI_TEXTURE_1D
) {
297 coords
[1] = ctx
->i32_0
;
298 } else if (target
== TGSI_TEXTURE_1D_ARRAY
) {
299 coords
[2] = coords
[1];
300 coords
[1] = ctx
->i32_0
;
301 } else if (target
== TGSI_TEXTURE_2D
) {
302 /* The hw can't bind a slice of a 3D image as a 2D
303 * image, because it ignores BASE_ARRAY if the target
304 * is 3D. The workaround is to read BASE_ARRAY and set
305 * it as the 3rd address operand for all 2D images.
307 LLVMValueRef first_layer
, const5
, mask
;
309 const5
= LLVMConstInt(ctx
->i32
, 5, 0);
310 mask
= LLVMConstInt(ctx
->i32
, S_008F24_BASE_ARRAY(~0), 0);
311 first_layer
= LLVMBuildExtractElement(builder
, desc
, const5
, "");
312 first_layer
= LLVMBuildAnd(builder
, first_layer
, mask
, "");
314 coords
[2] = first_layer
;
320 * Append the resource and indexing arguments for buffer intrinsics.
322 * \param rsrc the v4i32 buffer resource
323 * \param index index into the buffer (stride-based)
324 * \param offset byte offset into the buffer
326 static void buffer_append_args(
327 struct si_shader_context
*ctx
,
328 struct lp_build_emit_data
*emit_data
,
335 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
336 LLVMValueRef i1false
= LLVMConstInt(ctx
->i1
, 0, 0);
337 LLVMValueRef i1true
= LLVMConstInt(ctx
->i1
, 1, 0);
339 emit_data
->args
[emit_data
->arg_count
++] = rsrc
;
340 emit_data
->args
[emit_data
->arg_count
++] = index
; /* vindex */
341 emit_data
->args
[emit_data
->arg_count
++] = offset
; /* voffset */
343 emit_data
->args
[emit_data
->arg_count
++] =
345 inst
->Memory
.Qualifier
& (TGSI_MEMORY_COHERENT
| TGSI_MEMORY_VOLATILE
) ?
346 i1true
: i1false
; /* glc */
348 emit_data
->args
[emit_data
->arg_count
++] = i1false
; /* slc */
351 static void load_fetch_args(
352 struct lp_build_tgsi_context
* bld_base
,
353 struct lp_build_emit_data
* emit_data
)
355 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
356 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
357 unsigned target
= inst
->Memory
.Texture
;
360 emit_data
->dst_type
= ctx
->v4f32
;
362 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
||
363 inst
->Src
[0].Register
.File
== TGSI_FILE_CONSTBUF
) {
367 bool ubo
= inst
->Src
[0].Register
.File
== TGSI_FILE_CONSTBUF
;
368 rsrc
= shader_buffer_fetch_rsrc(ctx
, &inst
->Src
[0], ubo
);
370 tmp
= lp_build_emit_fetch(bld_base
, inst
, 1, 0);
371 offset
= ac_to_integer(&ctx
->ac
, tmp
);
373 buffer_append_args(ctx
, emit_data
, rsrc
, ctx
->i32_0
,
374 offset
, false, false);
375 } else if (inst
->Src
[0].Register
.File
== TGSI_FILE_IMAGE
||
376 tgsi_is_bindless_image_file(inst
->Src
[0].Register
.File
)) {
377 image_fetch_rsrc(bld_base
, &inst
->Src
[0], false, target
, &rsrc
);
378 image_fetch_coords(bld_base
, inst
, 1, rsrc
, &emit_data
->args
[1]);
380 if (target
== TGSI_TEXTURE_BUFFER
) {
381 buffer_append_args(ctx
, emit_data
, rsrc
, emit_data
->args
[1],
382 ctx
->i32_0
, false, false);
384 emit_data
->args
[0] = rsrc
;
389 static void load_emit_buffer(struct si_shader_context
*ctx
,
390 struct lp_build_emit_data
*emit_data
,
391 bool can_speculate
, bool allow_smem
)
393 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
394 uint writemask
= inst
->Dst
[0].Register
.WriteMask
;
395 uint count
= util_last_bit(writemask
);
396 LLVMValueRef
*args
= emit_data
->args
;
398 /* Don't use SMEM for shader buffer loads, because LLVM doesn't
399 * select SMEM for SI.load.const with a non-constant offset, and
400 * constant offsets practically don't exist with shader buffers.
402 * Also, SI.load.const doesn't use inst_offset when it's lowered
403 * to VMEM, so we just end up with more VALU instructions in the end
406 * TODO: Remove this line once LLVM can select SMEM with a non-constant
407 * offset, and can derive inst_offset when VMEM is selected.
408 * After that, si_memory_barrier should invalidate sL1 for shader
412 assert(LLVMConstIntGetZExtValue(args
[1]) == 0); /* vindex */
413 emit_data
->output
[emit_data
->chan
] =
414 ac_build_buffer_load(&ctx
->ac
, args
[0], count
, NULL
,
416 LLVMConstIntGetZExtValue(args
[3]),
417 LLVMConstIntGetZExtValue(args
[4]),
418 can_speculate
, allow_smem
);
421 static LLVMValueRef
get_memory_ptr(struct si_shader_context
*ctx
,
422 const struct tgsi_full_instruction
*inst
,
423 LLVMTypeRef type
, int arg
)
425 LLVMBuilderRef builder
= ctx
->ac
.builder
;
426 LLVMValueRef offset
, ptr
;
429 offset
= lp_build_emit_fetch(&ctx
->bld_base
, inst
, arg
, 0);
430 offset
= ac_to_integer(&ctx
->ac
, offset
);
433 ptr
= LLVMBuildGEP(builder
, ptr
, &offset
, 1, "");
434 addr_space
= LLVMGetPointerAddressSpace(LLVMTypeOf(ptr
));
435 ptr
= LLVMBuildBitCast(builder
, ptr
, LLVMPointerType(type
, addr_space
), "");
440 static void load_emit_memory(
441 struct si_shader_context
*ctx
,
442 struct lp_build_emit_data
*emit_data
)
444 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
445 unsigned writemask
= inst
->Dst
[0].Register
.WriteMask
;
446 LLVMValueRef channels
[4], ptr
, derived_ptr
, index
;
449 ptr
= get_memory_ptr(ctx
, inst
, ctx
->f32
, 1);
451 for (chan
= 0; chan
< 4; ++chan
) {
452 if (!(writemask
& (1 << chan
))) {
453 channels
[chan
] = LLVMGetUndef(ctx
->f32
);
457 index
= LLVMConstInt(ctx
->i32
, chan
, 0);
458 derived_ptr
= LLVMBuildGEP(ctx
->ac
.builder
, ptr
, &index
, 1, "");
459 channels
[chan
] = LLVMBuildLoad(ctx
->ac
.builder
, derived_ptr
, "");
461 emit_data
->output
[emit_data
->chan
] = ac_build_gather_values(&ctx
->ac
, channels
, 4);
465 * Return true if the memory accessed by a LOAD or STORE instruction is
466 * read-only or write-only, respectively.
468 * \param shader_buffers_reverse_access_mask
469 * For LOAD, set this to (store | atomic) slot usage in the shader.
470 * For STORE, set this to (load | atomic) slot usage in the shader.
471 * \param images_reverse_access_mask Same as above, but for images.
473 static bool is_oneway_access_only(const struct tgsi_full_instruction
*inst
,
474 const struct tgsi_shader_info
*info
,
475 unsigned shader_buffers_reverse_access_mask
,
476 unsigned images_reverse_access_mask
)
478 /* RESTRICT means NOALIAS.
479 * If there are no writes, we can assume the accessed memory is read-only.
480 * If there are no reads, we can assume the accessed memory is write-only.
482 if (inst
->Memory
.Qualifier
& TGSI_MEMORY_RESTRICT
) {
483 unsigned reverse_access_mask
;
485 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
) {
486 reverse_access_mask
= shader_buffers_reverse_access_mask
;
487 } else if (inst
->Memory
.Texture
== TGSI_TEXTURE_BUFFER
) {
488 reverse_access_mask
= info
->images_buffers
&
489 images_reverse_access_mask
;
491 reverse_access_mask
= ~info
->images_buffers
&
492 images_reverse_access_mask
;
495 if (inst
->Src
[0].Register
.Indirect
) {
496 if (!reverse_access_mask
)
499 if (!(reverse_access_mask
&
500 (1u << inst
->Src
[0].Register
.Index
)))
505 /* If there are no buffer writes (for both shader buffers & image
506 * buffers), it implies that buffer memory is read-only.
507 * If there are no buffer reads (for both shader buffers & image
508 * buffers), it implies that buffer memory is write-only.
510 * Same for the case when there are no writes/reads for non-buffer
513 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
||
514 (inst
->Memory
.Texture
== TGSI_TEXTURE_BUFFER
&&
515 (inst
->Src
[0].Register
.File
== TGSI_FILE_IMAGE
||
516 tgsi_is_bindless_image_file(inst
->Src
[0].Register
.File
)))) {
517 if (!shader_buffers_reverse_access_mask
&&
518 !(info
->images_buffers
& images_reverse_access_mask
))
521 if (!(~info
->images_buffers
& images_reverse_access_mask
))
527 static void load_emit(
528 const struct lp_build_tgsi_action
*action
,
529 struct lp_build_tgsi_context
*bld_base
,
530 struct lp_build_emit_data
*emit_data
)
532 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
533 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
534 const struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
535 bool can_speculate
= false;
537 if (inst
->Src
[0].Register
.File
== TGSI_FILE_MEMORY
) {
538 load_emit_memory(ctx
, emit_data
);
542 if (inst
->Src
[0].Register
.File
== TGSI_FILE_CONSTBUF
) {
543 load_emit_buffer(ctx
, emit_data
, true, true);
547 if (inst
->Memory
.Qualifier
& TGSI_MEMORY_VOLATILE
)
548 ac_build_waitcnt(&ctx
->ac
, VM_CNT
);
550 can_speculate
= !(inst
->Memory
.Qualifier
& TGSI_MEMORY_VOLATILE
) &&
551 is_oneway_access_only(inst
, info
,
552 info
->shader_buffers_store
|
553 info
->shader_buffers_atomic
,
555 info
->images_atomic
);
557 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
) {
558 load_emit_buffer(ctx
, emit_data
, can_speculate
, false);
562 if (inst
->Memory
.Texture
== TGSI_TEXTURE_BUFFER
) {
563 unsigned num_channels
= util_last_bit(inst
->Dst
[0].Register
.WriteMask
);
564 LLVMValueRef result
=
565 ac_build_buffer_load_format(&ctx
->ac
,
570 LLVMConstIntGetZExtValue(emit_data
->args
[3]),
572 emit_data
->output
[emit_data
->chan
] =
573 ac_build_expand_to_vec4(&ctx
->ac
, result
, num_channels
);
575 struct ac_image_args args
= {};
576 args
.opcode
= ac_image_load
;
577 args
.resource
= emit_data
->args
[0];
578 memcpy(args
.coords
, &emit_data
->args
[1], sizeof(args
.coords
));
579 args
.dim
= ac_image_dim_from_tgsi_target(ctx
->screen
, inst
->Memory
.Texture
);
580 if (inst
->Memory
.Qualifier
& (TGSI_MEMORY_COHERENT
| TGSI_MEMORY_VOLATILE
))
581 args
.cache_policy
= ac_glc
;
582 args
.attributes
= ac_get_load_intr_attribs(can_speculate
);
585 emit_data
->output
[emit_data
->chan
] =
586 ac_build_image_opcode(&ctx
->ac
, &args
);
590 static void store_fetch_args(
591 struct lp_build_tgsi_context
* bld_base
,
592 struct lp_build_emit_data
* emit_data
)
594 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
595 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
596 struct tgsi_full_src_register memory
;
597 LLVMValueRef chans
[4];
602 emit_data
->dst_type
= ctx
->voidt
;
604 for (chan
= 0; chan
< 4; ++chan
) {
605 chans
[chan
] = lp_build_emit_fetch(bld_base
, inst
, 1, chan
);
607 data
= ac_build_gather_values(&ctx
->ac
, chans
, 4);
609 emit_data
->args
[emit_data
->arg_count
++] = data
;
611 memory
= tgsi_full_src_register_from_dst(&inst
->Dst
[0]);
613 if (inst
->Dst
[0].Register
.File
== TGSI_FILE_BUFFER
) {
617 rsrc
= shader_buffer_fetch_rsrc(ctx
, &memory
, false);
619 tmp
= lp_build_emit_fetch(bld_base
, inst
, 0, 0);
620 offset
= ac_to_integer(&ctx
->ac
, tmp
);
622 buffer_append_args(ctx
, emit_data
, rsrc
, ctx
->i32_0
,
623 offset
, false, false);
624 } else if (inst
->Dst
[0].Register
.File
== TGSI_FILE_IMAGE
||
625 tgsi_is_bindless_image_file(inst
->Dst
[0].Register
.File
)) {
626 unsigned target
= inst
->Memory
.Texture
;
628 /* 8bit/16bit TC L1 write corruption bug on SI.
629 * All store opcodes not aligned to a dword are affected.
631 * The only way to get unaligned stores in radeonsi is through
634 bool force_glc
= ctx
->screen
->info
.chip_class
== SI
;
636 image_fetch_rsrc(bld_base
, &memory
, true, target
, &rsrc
);
637 image_fetch_coords(bld_base
, inst
, 0, rsrc
, &emit_data
->args
[2]);
639 if (target
== TGSI_TEXTURE_BUFFER
) {
640 buffer_append_args(ctx
, emit_data
, rsrc
, emit_data
->args
[2],
641 ctx
->i32_0
, false, force_glc
);
643 emit_data
->args
[1] = rsrc
;
648 static void store_emit_buffer(
649 struct si_shader_context
*ctx
,
650 struct lp_build_emit_data
*emit_data
,
651 bool writeonly_memory
)
653 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
654 LLVMBuilderRef builder
= ctx
->ac
.builder
;
655 LLVMValueRef base_data
= emit_data
->args
[0];
656 LLVMValueRef base_offset
= emit_data
->args
[3];
657 unsigned writemask
= inst
->Dst
[0].Register
.WriteMask
;
661 const char *intrinsic_name
;
666 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
668 /* Due to an LLVM limitation, split 3-element writes
669 * into a 2-element and a 1-element write. */
671 writemask
|= 1 << (start
+ 2);
677 intrinsic_name
= "llvm.amdgcn.buffer.store.v4f32";
678 } else if (count
== 2) {
679 LLVMTypeRef v2f32
= LLVMVectorType(ctx
->f32
, 2);
681 tmp
= LLVMBuildExtractElement(
683 LLVMConstInt(ctx
->i32
, start
, 0), "");
684 data
= LLVMBuildInsertElement(
685 builder
, LLVMGetUndef(v2f32
), tmp
,
688 tmp
= LLVMBuildExtractElement(
690 LLVMConstInt(ctx
->i32
, start
+ 1, 0), "");
691 data
= LLVMBuildInsertElement(
692 builder
, data
, tmp
, ctx
->i32_1
, "");
694 intrinsic_name
= "llvm.amdgcn.buffer.store.v2f32";
697 data
= LLVMBuildExtractElement(
699 LLVMConstInt(ctx
->i32
, start
, 0), "");
700 intrinsic_name
= "llvm.amdgcn.buffer.store.f32";
703 offset
= base_offset
;
705 offset
= LLVMBuildAdd(
707 LLVMConstInt(ctx
->i32
, start
* 4, 0), "");
710 emit_data
->args
[0] = data
;
711 emit_data
->args
[3] = offset
;
714 builder
, intrinsic_name
, emit_data
->dst_type
,
715 emit_data
->args
, emit_data
->arg_count
,
716 ac_get_store_intr_attribs(writeonly_memory
));
720 static void store_emit_memory(
721 struct si_shader_context
*ctx
,
722 struct lp_build_emit_data
*emit_data
)
724 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
725 LLVMBuilderRef builder
= ctx
->ac
.builder
;
726 unsigned writemask
= inst
->Dst
[0].Register
.WriteMask
;
727 LLVMValueRef ptr
, derived_ptr
, data
, index
;
730 ptr
= get_memory_ptr(ctx
, inst
, ctx
->f32
, 0);
732 for (chan
= 0; chan
< 4; ++chan
) {
733 if (!(writemask
& (1 << chan
))) {
736 data
= lp_build_emit_fetch(&ctx
->bld_base
, inst
, 1, chan
);
737 index
= LLVMConstInt(ctx
->i32
, chan
, 0);
738 derived_ptr
= LLVMBuildGEP(builder
, ptr
, &index
, 1, "");
739 LLVMBuildStore(builder
, data
, derived_ptr
);
743 static void store_emit(
744 const struct lp_build_tgsi_action
*action
,
745 struct lp_build_tgsi_context
*bld_base
,
746 struct lp_build_emit_data
*emit_data
)
748 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
749 LLVMBuilderRef builder
= ctx
->ac
.builder
;
750 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
751 const struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
752 unsigned target
= inst
->Memory
.Texture
;
753 bool writeonly_memory
= false;
755 if (inst
->Dst
[0].Register
.File
== TGSI_FILE_MEMORY
) {
756 store_emit_memory(ctx
, emit_data
);
760 if (inst
->Memory
.Qualifier
& TGSI_MEMORY_VOLATILE
)
761 ac_build_waitcnt(&ctx
->ac
, VM_CNT
);
763 writeonly_memory
= is_oneway_access_only(inst
, info
,
764 info
->shader_buffers_load
|
765 info
->shader_buffers_atomic
,
767 info
->images_atomic
);
769 if (inst
->Dst
[0].Register
.File
== TGSI_FILE_BUFFER
) {
770 store_emit_buffer(ctx
, emit_data
, writeonly_memory
);
774 if (target
== TGSI_TEXTURE_BUFFER
) {
775 emit_data
->output
[emit_data
->chan
] = lp_build_intrinsic(
776 builder
, "llvm.amdgcn.buffer.store.format.v4f32",
777 emit_data
->dst_type
, emit_data
->args
,
778 emit_data
->arg_count
,
779 ac_get_store_intr_attribs(writeonly_memory
));
781 struct ac_image_args args
= {};
782 args
.opcode
= ac_image_store
;
783 args
.data
[0] = emit_data
->args
[0];
784 args
.resource
= emit_data
->args
[1];
785 memcpy(args
.coords
, &emit_data
->args
[2], sizeof(args
.coords
));
786 args
.dim
= ac_image_dim_from_tgsi_target(ctx
->screen
, inst
->Memory
.Texture
);
787 args
.attributes
= ac_get_store_intr_attribs(writeonly_memory
);
790 /* Workaround for 8bit/16bit TC L1 write corruption bug on SI.
791 * All store opcodes not aligned to a dword are affected.
793 bool force_glc
= ctx
->screen
->info
.chip_class
== SI
;
795 inst
->Memory
.Qualifier
& (TGSI_MEMORY_COHERENT
| TGSI_MEMORY_VOLATILE
))
796 args
.cache_policy
= ac_glc
;
798 emit_data
->output
[emit_data
->chan
] =
799 ac_build_image_opcode(&ctx
->ac
, &args
);
803 static void atomic_fetch_args(
804 struct lp_build_tgsi_context
* bld_base
,
805 struct lp_build_emit_data
* emit_data
)
807 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
808 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
809 LLVMValueRef data1
, data2
;
813 emit_data
->dst_type
= ctx
->f32
;
815 tmp
= lp_build_emit_fetch(bld_base
, inst
, 2, 0);
816 data1
= ac_to_integer(&ctx
->ac
, tmp
);
818 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
) {
819 tmp
= lp_build_emit_fetch(bld_base
, inst
, 3, 0);
820 data2
= ac_to_integer(&ctx
->ac
, tmp
);
823 /* llvm.amdgcn.image/buffer.atomic.cmpswap reflect the hardware order
824 * of arguments, which is reversed relative to TGSI (and GLSL)
826 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
)
827 emit_data
->args
[emit_data
->arg_count
++] = data2
;
828 emit_data
->args
[emit_data
->arg_count
++] = data1
;
830 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
) {
833 rsrc
= shader_buffer_fetch_rsrc(ctx
, &inst
->Src
[0], false);
835 tmp
= lp_build_emit_fetch(bld_base
, inst
, 1, 0);
836 offset
= ac_to_integer(&ctx
->ac
, tmp
);
838 buffer_append_args(ctx
, emit_data
, rsrc
, ctx
->i32_0
,
839 offset
, true, false);
840 } else if (inst
->Src
[0].Register
.File
== TGSI_FILE_IMAGE
||
841 tgsi_is_bindless_image_file(inst
->Src
[0].Register
.File
)) {
842 unsigned target
= inst
->Memory
.Texture
;
844 image_fetch_rsrc(bld_base
, &inst
->Src
[0], true, target
, &rsrc
);
845 image_fetch_coords(bld_base
, inst
, 1, rsrc
,
846 &emit_data
->args
[emit_data
->arg_count
+ 1]);
848 if (target
== TGSI_TEXTURE_BUFFER
) {
849 buffer_append_args(ctx
, emit_data
, rsrc
,
850 emit_data
->args
[emit_data
->arg_count
+ 1],
851 ctx
->i32_0
, true, false);
853 emit_data
->args
[emit_data
->arg_count
] = rsrc
;
858 static void atomic_emit_memory(struct si_shader_context
*ctx
,
859 struct lp_build_emit_data
*emit_data
) {
860 LLVMBuilderRef builder
= ctx
->ac
.builder
;
861 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
862 LLVMValueRef ptr
, result
, arg
;
864 ptr
= get_memory_ptr(ctx
, inst
, ctx
->i32
, 1);
866 arg
= lp_build_emit_fetch(&ctx
->bld_base
, inst
, 2, 0);
867 arg
= ac_to_integer(&ctx
->ac
, arg
);
869 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
) {
870 LLVMValueRef new_data
;
871 new_data
= lp_build_emit_fetch(&ctx
->bld_base
,
874 new_data
= ac_to_integer(&ctx
->ac
, new_data
);
876 result
= LLVMBuildAtomicCmpXchg(builder
, ptr
, arg
, new_data
,
877 LLVMAtomicOrderingSequentiallyConsistent
,
878 LLVMAtomicOrderingSequentiallyConsistent
,
881 result
= LLVMBuildExtractValue(builder
, result
, 0, "");
883 LLVMAtomicRMWBinOp op
;
885 switch(inst
->Instruction
.Opcode
) {
886 case TGSI_OPCODE_ATOMUADD
:
887 op
= LLVMAtomicRMWBinOpAdd
;
889 case TGSI_OPCODE_ATOMXCHG
:
890 op
= LLVMAtomicRMWBinOpXchg
;
892 case TGSI_OPCODE_ATOMAND
:
893 op
= LLVMAtomicRMWBinOpAnd
;
895 case TGSI_OPCODE_ATOMOR
:
896 op
= LLVMAtomicRMWBinOpOr
;
898 case TGSI_OPCODE_ATOMXOR
:
899 op
= LLVMAtomicRMWBinOpXor
;
901 case TGSI_OPCODE_ATOMUMIN
:
902 op
= LLVMAtomicRMWBinOpUMin
;
904 case TGSI_OPCODE_ATOMUMAX
:
905 op
= LLVMAtomicRMWBinOpUMax
;
907 case TGSI_OPCODE_ATOMIMIN
:
908 op
= LLVMAtomicRMWBinOpMin
;
910 case TGSI_OPCODE_ATOMIMAX
:
911 op
= LLVMAtomicRMWBinOpMax
;
914 unreachable("unknown atomic opcode");
917 result
= LLVMBuildAtomicRMW(builder
, op
, ptr
, arg
,
918 LLVMAtomicOrderingSequentiallyConsistent
,
921 emit_data
->output
[emit_data
->chan
] = LLVMBuildBitCast(builder
, result
, emit_data
->dst_type
, "");
924 static void atomic_emit(
925 const struct lp_build_tgsi_action
*action
,
926 struct lp_build_tgsi_context
*bld_base
,
927 struct lp_build_emit_data
*emit_data
)
929 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
930 LLVMBuilderRef builder
= ctx
->ac
.builder
;
931 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
934 if (inst
->Src
[0].Register
.File
== TGSI_FILE_MEMORY
) {
935 atomic_emit_memory(ctx
, emit_data
);
939 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
||
940 inst
->Memory
.Texture
== TGSI_TEXTURE_BUFFER
) {
941 char intrinsic_name
[40];
942 snprintf(intrinsic_name
, sizeof(intrinsic_name
),
943 "llvm.amdgcn.buffer.atomic.%s", action
->intr_name
);
944 tmp
= lp_build_intrinsic(
945 builder
, intrinsic_name
, ctx
->i32
,
946 emit_data
->args
, emit_data
->arg_count
, 0);
947 emit_data
->output
[emit_data
->chan
] = ac_to_float(&ctx
->ac
, tmp
);
949 unsigned num_data
= inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
? 2 : 1;
950 struct ac_image_args args
= {};
952 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
) {
953 args
.opcode
= ac_image_atomic_cmpswap
;
955 args
.opcode
= ac_image_atomic
;
956 switch (inst
->Instruction
.Opcode
) {
957 case TGSI_OPCODE_ATOMXCHG
: args
.atomic
= ac_atomic_swap
; break;
958 case TGSI_OPCODE_ATOMUADD
: args
.atomic
= ac_atomic_add
; break;
959 case TGSI_OPCODE_ATOMAND
: args
.atomic
= ac_atomic_and
; break;
960 case TGSI_OPCODE_ATOMOR
: args
.atomic
= ac_atomic_or
; break;
961 case TGSI_OPCODE_ATOMXOR
: args
.atomic
= ac_atomic_xor
; break;
962 case TGSI_OPCODE_ATOMUMIN
: args
.atomic
= ac_atomic_umin
; break;
963 case TGSI_OPCODE_ATOMUMAX
: args
.atomic
= ac_atomic_umax
; break;
964 case TGSI_OPCODE_ATOMIMIN
: args
.atomic
= ac_atomic_smin
; break;
965 case TGSI_OPCODE_ATOMIMAX
: args
.atomic
= ac_atomic_smax
; break;
966 default: unreachable("unhandled image atomic");
970 for (unsigned i
= 0; i
< num_data
; ++i
)
971 args
.data
[i
] = emit_data
->args
[i
];
973 args
.resource
= emit_data
->args
[num_data
];
974 memcpy(args
.coords
, &emit_data
->args
[num_data
+ 1], sizeof(args
.coords
));
975 args
.dim
= ac_image_dim_from_tgsi_target(ctx
->screen
, inst
->Memory
.Texture
);
977 emit_data
->output
[emit_data
->chan
] =
978 ac_to_float(&ctx
->ac
, ac_build_image_opcode(&ctx
->ac
, &args
));
982 static void set_tex_fetch_args(struct si_shader_context
*ctx
,
983 struct lp_build_emit_data
*emit_data
,
984 struct ac_image_args
*args
,
987 args
->dim
= ac_texture_dim_from_tgsi_target(ctx
->screen
, target
);
988 args
->unorm
= target
== TGSI_TEXTURE_RECT
||
989 target
== TGSI_TEXTURE_SHADOWRECT
;
991 /* Ugly, but we seem to have no other choice right now. */
992 STATIC_ASSERT(sizeof(*args
) <= sizeof(emit_data
->args
));
993 memcpy(emit_data
->args
, args
, sizeof(*args
));
996 static LLVMValueRef
fix_resinfo(struct si_shader_context
*ctx
,
997 unsigned target
, LLVMValueRef out
)
999 LLVMBuilderRef builder
= ctx
->ac
.builder
;
1001 /* 1D textures are allocated and used as 2D on GFX9. */
1002 if (ctx
->screen
->info
.chip_class
>= GFX9
&&
1003 (target
== TGSI_TEXTURE_1D_ARRAY
||
1004 target
== TGSI_TEXTURE_SHADOW1D_ARRAY
)) {
1005 LLVMValueRef layers
=
1006 LLVMBuildExtractElement(builder
, out
,
1007 LLVMConstInt(ctx
->i32
, 2, 0), "");
1008 out
= LLVMBuildInsertElement(builder
, out
, layers
,
1012 /* Divide the number of layers by 6 to get the number of cubes. */
1013 if (target
== TGSI_TEXTURE_CUBE_ARRAY
||
1014 target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
1015 LLVMValueRef imm2
= LLVMConstInt(ctx
->i32
, 2, 0);
1017 LLVMValueRef z
= LLVMBuildExtractElement(builder
, out
, imm2
, "");
1018 z
= LLVMBuildSDiv(builder
, z
, LLVMConstInt(ctx
->i32
, 6, 0), "");
1020 out
= LLVMBuildInsertElement(builder
, out
, z
, imm2
, "");
1025 static void resq_fetch_args(
1026 struct lp_build_tgsi_context
* bld_base
,
1027 struct lp_build_emit_data
* emit_data
)
1029 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1030 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
1031 const struct tgsi_full_src_register
*reg
= &inst
->Src
[0];
1033 emit_data
->dst_type
= ctx
->v4i32
;
1035 if (reg
->Register
.File
== TGSI_FILE_BUFFER
) {
1036 emit_data
->args
[0] = shader_buffer_fetch_rsrc(ctx
, reg
, false);
1037 emit_data
->arg_count
= 1;
1038 } else if (inst
->Memory
.Texture
== TGSI_TEXTURE_BUFFER
) {
1039 image_fetch_rsrc(bld_base
, reg
, false, inst
->Memory
.Texture
,
1040 &emit_data
->args
[0]);
1041 emit_data
->arg_count
= 1;
1043 struct ac_image_args args
= {};
1044 unsigned image_target
;
1046 if (inst
->Memory
.Texture
== TGSI_TEXTURE_3D
)
1047 image_target
= TGSI_TEXTURE_2D_ARRAY
;
1049 image_target
= inst
->Memory
.Texture
;
1051 image_fetch_rsrc(bld_base
, reg
, false, inst
->Memory
.Texture
,
1053 args
.lod
= ctx
->i32_0
;
1055 set_tex_fetch_args(ctx
, emit_data
, &args
, image_target
);
1059 static void resq_emit(
1060 const struct lp_build_tgsi_action
*action
,
1061 struct lp_build_tgsi_context
*bld_base
,
1062 struct lp_build_emit_data
*emit_data
)
1064 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1065 LLVMBuilderRef builder
= ctx
->ac
.builder
;
1066 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
1069 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
) {
1070 out
= LLVMBuildExtractElement(builder
, emit_data
->args
[0],
1071 LLVMConstInt(ctx
->i32
, 2, 0), "");
1072 } else if (inst
->Memory
.Texture
== TGSI_TEXTURE_BUFFER
) {
1073 out
= get_buffer_size(bld_base
, emit_data
->args
[0]);
1075 struct ac_image_args args
;
1077 memcpy(&args
, emit_data
->args
, sizeof(args
)); /* ugly */
1078 args
.opcode
= ac_image_get_resinfo
;
1079 out
= ac_build_image_opcode(&ctx
->ac
, &args
);
1081 out
= fix_resinfo(ctx
, inst
->Memory
.Texture
, out
);
1084 emit_data
->output
[emit_data
->chan
] = out
;
1088 * Load an image view, fmask view. or sampler state descriptor.
1090 LLVMValueRef
si_load_sampler_desc(struct si_shader_context
*ctx
,
1091 LLVMValueRef list
, LLVMValueRef index
,
1092 enum ac_descriptor_type type
)
1094 LLVMBuilderRef builder
= ctx
->ac
.builder
;
1098 /* The image is at [0:7]. */
1099 index
= LLVMBuildMul(builder
, index
, LLVMConstInt(ctx
->i32
, 2, 0), "");
1101 case AC_DESC_BUFFER
:
1102 /* The buffer is in [4:7]. */
1103 index
= LLVMBuildMul(builder
, index
, LLVMConstInt(ctx
->i32
, 4, 0), "");
1104 index
= LLVMBuildAdd(builder
, index
, ctx
->i32_1
, "");
1105 list
= LLVMBuildPointerCast(builder
, list
,
1106 ac_array_in_const32_addr_space(ctx
->v4i32
), "");
1109 /* The FMASK is at [8:15]. */
1110 index
= LLVMBuildMul(builder
, index
, LLVMConstInt(ctx
->i32
, 2, 0), "");
1111 index
= LLVMBuildAdd(builder
, index
, ctx
->i32_1
, "");
1113 case AC_DESC_SAMPLER
:
1114 /* The sampler state is at [12:15]. */
1115 index
= LLVMBuildMul(builder
, index
, LLVMConstInt(ctx
->i32
, 4, 0), "");
1116 index
= LLVMBuildAdd(builder
, index
, LLVMConstInt(ctx
->i32
, 3, 0), "");
1117 list
= LLVMBuildPointerCast(builder
, list
,
1118 ac_array_in_const32_addr_space(ctx
->v4i32
), "");
1122 return ac_build_load_to_sgpr(&ctx
->ac
, list
, index
);
1125 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
1128 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
1129 * filtering manually. The driver sets img7 to a mask clearing
1130 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
1131 * s_and_b32 samp0, samp0, img7
1134 * The ANISO_OVERRIDE sampler field enables this fix in TA.
1136 static LLVMValueRef
sici_fix_sampler_aniso(struct si_shader_context
*ctx
,
1137 LLVMValueRef res
, LLVMValueRef samp
)
1139 LLVMValueRef img7
, samp0
;
1141 if (ctx
->screen
->info
.chip_class
>= VI
)
1144 img7
= LLVMBuildExtractElement(ctx
->ac
.builder
, res
,
1145 LLVMConstInt(ctx
->i32
, 7, 0), "");
1146 samp0
= LLVMBuildExtractElement(ctx
->ac
.builder
, samp
,
1148 samp0
= LLVMBuildAnd(ctx
->ac
.builder
, samp0
, img7
, "");
1149 return LLVMBuildInsertElement(ctx
->ac
.builder
, samp
, samp0
,
1153 static void tex_fetch_ptrs(
1154 struct lp_build_tgsi_context
*bld_base
,
1155 struct lp_build_emit_data
*emit_data
,
1156 LLVMValueRef
*res_ptr
, LLVMValueRef
*samp_ptr
, LLVMValueRef
*fmask_ptr
)
1158 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1159 LLVMValueRef list
= LLVMGetParam(ctx
->main_fn
, ctx
->param_samplers_and_images
);
1160 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
1161 const struct tgsi_full_src_register
*reg
;
1162 unsigned target
= inst
->Texture
.Texture
;
1163 unsigned sampler_src
;
1166 sampler_src
= emit_data
->inst
->Instruction
.NumSrcRegs
- 1;
1167 reg
= &emit_data
->inst
->Src
[sampler_src
];
1169 if (reg
->Register
.Indirect
) {
1170 index
= si_get_bounded_indirect_index(ctx
,
1172 reg
->Register
.Index
,
1174 index
= LLVMBuildAdd(ctx
->ac
.builder
, index
,
1175 LLVMConstInt(ctx
->i32
, SI_NUM_IMAGES
/ 2, 0), "");
1177 index
= LLVMConstInt(ctx
->i32
,
1178 si_get_sampler_slot(reg
->Register
.Index
), 0);
1181 if (reg
->Register
.File
!= TGSI_FILE_SAMPLER
) {
1182 /* Bindless descriptors are accessible from a different pair of
1183 * user SGPR indices.
1185 list
= LLVMGetParam(ctx
->main_fn
,
1186 ctx
->param_bindless_samplers_and_images
);
1187 index
= lp_build_emit_fetch_src(bld_base
, reg
,
1188 TGSI_TYPE_UNSIGNED
, 0);
1191 if (target
== TGSI_TEXTURE_BUFFER
)
1192 *res_ptr
= si_load_sampler_desc(ctx
, list
, index
, AC_DESC_BUFFER
);
1194 *res_ptr
= si_load_sampler_desc(ctx
, list
, index
, AC_DESC_IMAGE
);
1201 if (target
== TGSI_TEXTURE_2D_MSAA
||
1202 target
== TGSI_TEXTURE_2D_ARRAY_MSAA
) {
1204 *fmask_ptr
= si_load_sampler_desc(ctx
, list
, index
,
1206 } else if (target
!= TGSI_TEXTURE_BUFFER
) {
1208 *samp_ptr
= si_load_sampler_desc(ctx
, list
, index
,
1210 *samp_ptr
= sici_fix_sampler_aniso(ctx
, *res_ptr
, *samp_ptr
);
1215 static void txq_fetch_args(
1216 struct lp_build_tgsi_context
*bld_base
,
1217 struct lp_build_emit_data
*emit_data
)
1219 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1220 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
1221 unsigned target
= inst
->Texture
.Texture
;
1222 struct ac_image_args args
= {};
1224 tex_fetch_ptrs(bld_base
, emit_data
, &args
.resource
, NULL
, NULL
);
1226 if (target
== TGSI_TEXTURE_BUFFER
) {
1227 /* Read the size from the buffer descriptor directly. */
1228 emit_data
->args
[0] = get_buffer_size(bld_base
, args
.resource
);
1232 /* Textures - set the mip level. */
1233 args
.lod
= lp_build_emit_fetch(bld_base
, inst
, 0, TGSI_CHAN_X
);
1236 set_tex_fetch_args(ctx
, emit_data
, &args
, target
);
1239 static void txq_emit(const struct lp_build_tgsi_action
*action
,
1240 struct lp_build_tgsi_context
*bld_base
,
1241 struct lp_build_emit_data
*emit_data
)
1243 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1244 struct ac_image_args args
;
1245 unsigned target
= emit_data
->inst
->Texture
.Texture
;
1247 if (target
== TGSI_TEXTURE_BUFFER
) {
1248 /* Just return the buffer size. */
1249 emit_data
->output
[emit_data
->chan
] = emit_data
->args
[0];
1253 memcpy(&args
, emit_data
->args
, sizeof(args
)); /* ugly */
1255 args
.opcode
= ac_image_get_resinfo
;
1256 LLVMValueRef result
= ac_build_image_opcode(&ctx
->ac
, &args
);
1258 emit_data
->output
[emit_data
->chan
] = fix_resinfo(ctx
, target
, result
);
1261 static void tex_fetch_args(
1262 struct lp_build_tgsi_context
*bld_base
,
1263 struct lp_build_emit_data
*emit_data
)
1265 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1266 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
1267 unsigned opcode
= inst
->Instruction
.Opcode
;
1268 unsigned target
= inst
->Texture
.Texture
;
1269 struct ac_image_args args
= {};
1270 int ref_pos
= tgsi_util_get_shadow_ref_src_index(target
);
1272 bool has_offset
= inst
->Texture
.NumOffsets
> 0;
1273 LLVMValueRef fmask_ptr
= NULL
;
1275 tex_fetch_ptrs(bld_base
, emit_data
, &args
.resource
, &args
.sampler
, &fmask_ptr
);
1277 if (target
== TGSI_TEXTURE_BUFFER
) {
1278 emit_data
->dst_type
= ctx
->v4f32
;
1279 emit_data
->args
[0] = args
.resource
;
1280 emit_data
->args
[1] = ctx
->i32_0
;
1281 emit_data
->args
[2] = lp_build_emit_fetch(bld_base
, emit_data
->inst
, 0, TGSI_CHAN_X
);
1282 emit_data
->arg_count
= 3;
1286 /* Fetch and project texture coordinates */
1287 args
.coords
[3] = lp_build_emit_fetch(bld_base
, emit_data
->inst
, 0, TGSI_CHAN_W
);
1288 for (chan
= 0; chan
< 3; chan
++) {
1289 args
.coords
[chan
] = lp_build_emit_fetch(bld_base
,
1292 if (opcode
== TGSI_OPCODE_TXP
)
1293 args
.coords
[chan
] = lp_build_emit_llvm_binary(
1294 bld_base
, TGSI_OPCODE_DIV
,
1295 args
.coords
[chan
], args
.coords
[3]);
1298 if (opcode
== TGSI_OPCODE_TXP
)
1299 args
.coords
[3] = ctx
->ac
.f32_1
;
1303 opcode
!= TGSI_OPCODE_TXF
&&
1304 opcode
!= TGSI_OPCODE_TXF_LZ
) {
1305 /* The offsets are six-bit signed integers packed like this:
1306 * X=[5:0], Y=[13:8], and Z=[21:16].
1308 LLVMValueRef offset
[3], pack
;
1310 assert(inst
->Texture
.NumOffsets
== 1);
1312 for (chan
= 0; chan
< 3; chan
++) {
1313 offset
[chan
] = lp_build_emit_fetch_texoffset(bld_base
,
1314 emit_data
->inst
, 0, chan
);
1315 offset
[chan
] = LLVMBuildAnd(ctx
->ac
.builder
, offset
[chan
],
1316 LLVMConstInt(ctx
->i32
, 0x3f, 0), "");
1318 offset
[chan
] = LLVMBuildShl(ctx
->ac
.builder
, offset
[chan
],
1319 LLVMConstInt(ctx
->i32
, chan
*8, 0), "");
1322 pack
= LLVMBuildOr(ctx
->ac
.builder
, offset
[0], offset
[1], "");
1323 pack
= LLVMBuildOr(ctx
->ac
.builder
, pack
, offset
[2], "");
1327 /* Pack LOD bias value */
1328 if (opcode
== TGSI_OPCODE_TXB
)
1329 args
.bias
= args
.coords
[3];
1330 if (opcode
== TGSI_OPCODE_TXB2
)
1331 args
.bias
= lp_build_emit_fetch(bld_base
, inst
, 1, TGSI_CHAN_X
);
1333 /* Pack depth comparison value */
1334 if (tgsi_is_shadow_target(target
) && opcode
!= TGSI_OPCODE_LODQ
) {
1337 if (target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
1338 z
= lp_build_emit_fetch(bld_base
, inst
, 1, TGSI_CHAN_X
);
1340 assert(ref_pos
>= 0);
1341 z
= args
.coords
[ref_pos
];
1344 /* Section 8.23.1 (Depth Texture Comparison Mode) of the
1345 * OpenGL 4.5 spec says:
1347 * "If the texture’s internal format indicates a fixed-point
1348 * depth texture, then D_t and D_ref are clamped to the
1349 * range [0, 1]; otherwise no clamping is performed."
1351 * TC-compatible HTILE promotes Z16 and Z24 to Z32_FLOAT,
1352 * so the depth comparison value isn't clamped for Z16 and
1353 * Z24 anymore. Do it manually here.
1355 if (ctx
->screen
->info
.chip_class
>= VI
) {
1356 LLVMValueRef upgraded
;
1357 LLVMValueRef clamped
;
1358 upgraded
= LLVMBuildExtractElement(ctx
->ac
.builder
, args
.sampler
,
1359 LLVMConstInt(ctx
->i32
, 3, false), "");
1360 upgraded
= LLVMBuildLShr(ctx
->ac
.builder
, upgraded
,
1361 LLVMConstInt(ctx
->i32
, 29, false), "");
1362 upgraded
= LLVMBuildTrunc(ctx
->ac
.builder
, upgraded
, ctx
->i1
, "");
1363 clamped
= ac_build_clamp(&ctx
->ac
, z
);
1364 z
= LLVMBuildSelect(ctx
->ac
.builder
, upgraded
, clamped
, z
, "");
1370 /* Pack user derivatives */
1371 if (opcode
== TGSI_OPCODE_TXD
) {
1372 int param
, num_src_deriv_channels
, num_dst_deriv_channels
;
1375 case TGSI_TEXTURE_3D
:
1376 num_src_deriv_channels
= 3;
1377 num_dst_deriv_channels
= 3;
1379 case TGSI_TEXTURE_2D
:
1380 case TGSI_TEXTURE_SHADOW2D
:
1381 case TGSI_TEXTURE_RECT
:
1382 case TGSI_TEXTURE_SHADOWRECT
:
1383 case TGSI_TEXTURE_2D_ARRAY
:
1384 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
1385 num_src_deriv_channels
= 2;
1386 num_dst_deriv_channels
= 2;
1388 case TGSI_TEXTURE_CUBE
:
1389 case TGSI_TEXTURE_SHADOWCUBE
:
1390 case TGSI_TEXTURE_CUBE_ARRAY
:
1391 case TGSI_TEXTURE_SHADOWCUBE_ARRAY
:
1392 /* Cube derivatives will be converted to 2D. */
1393 num_src_deriv_channels
= 3;
1394 num_dst_deriv_channels
= 3;
1396 case TGSI_TEXTURE_1D
:
1397 case TGSI_TEXTURE_SHADOW1D
:
1398 case TGSI_TEXTURE_1D_ARRAY
:
1399 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
1400 num_src_deriv_channels
= 1;
1402 /* 1D textures are allocated and used as 2D on GFX9. */
1403 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
1404 num_dst_deriv_channels
= 2;
1406 num_dst_deriv_channels
= 1;
1410 unreachable("invalid target");
1413 for (param
= 0; param
< 2; param
++) {
1414 for (chan
= 0; chan
< num_src_deriv_channels
; chan
++)
1415 args
.derivs
[param
* num_dst_deriv_channels
+ chan
] =
1416 lp_build_emit_fetch(bld_base
, inst
, param
+1, chan
);
1418 /* Fill in the rest with zeros. */
1419 for (chan
= num_src_deriv_channels
;
1420 chan
< num_dst_deriv_channels
; chan
++)
1421 args
.derivs
[param
* num_dst_deriv_channels
+ chan
] =
1426 if (target
== TGSI_TEXTURE_CUBE
||
1427 target
== TGSI_TEXTURE_CUBE_ARRAY
||
1428 target
== TGSI_TEXTURE_SHADOWCUBE
||
1429 target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
1430 ac_prepare_cube_coords(&ctx
->ac
,
1431 opcode
== TGSI_OPCODE_TXD
,
1432 target
== TGSI_TEXTURE_CUBE_ARRAY
||
1433 target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
,
1434 opcode
== TGSI_OPCODE_LODQ
,
1435 args
.coords
, args
.derivs
);
1436 } else if (tgsi_is_array_sampler(target
) &&
1437 opcode
!= TGSI_OPCODE_TXF
&&
1438 opcode
!= TGSI_OPCODE_TXF_LZ
&&
1439 ctx
->screen
->info
.chip_class
<= VI
) {
1440 unsigned array_coord
= target
== TGSI_TEXTURE_1D_ARRAY
? 1 : 2;
1441 args
.coords
[array_coord
] =
1442 ac_build_intrinsic(&ctx
->ac
, "llvm.rint.f32", ctx
->f32
,
1443 &args
.coords
[array_coord
], 1, 0);
1446 /* 1D textures are allocated and used as 2D on GFX9. */
1447 if (ctx
->screen
->info
.chip_class
>= GFX9
) {
1448 LLVMValueRef filler
;
1450 /* Use 0.5, so that we don't sample the border color. */
1451 if (opcode
== TGSI_OPCODE_TXF
||
1452 opcode
== TGSI_OPCODE_TXF_LZ
)
1453 filler
= ctx
->i32_0
;
1455 filler
= LLVMConstReal(ctx
->f32
, 0.5);
1457 if (target
== TGSI_TEXTURE_1D
||
1458 target
== TGSI_TEXTURE_SHADOW1D
) {
1459 args
.coords
[1] = filler
;
1460 } else if (target
== TGSI_TEXTURE_1D_ARRAY
||
1461 target
== TGSI_TEXTURE_SHADOW1D_ARRAY
) {
1462 args
.coords
[2] = args
.coords
[1];
1463 args
.coords
[1] = filler
;
1467 /* Pack LOD or sample index */
1468 if (opcode
== TGSI_OPCODE_TXL
)
1469 args
.lod
= args
.coords
[3];
1470 else if (opcode
== TGSI_OPCODE_TXL2
)
1471 args
.lod
= lp_build_emit_fetch(bld_base
, inst
, 1, TGSI_CHAN_X
);
1472 else if (opcode
== TGSI_OPCODE_TXF
) {
1473 if (target
== TGSI_TEXTURE_2D_MSAA
) {
1474 /* No LOD, but move sample index into the right place. */
1475 args
.coords
[2] = args
.coords
[3];
1476 } else if (target
!= TGSI_TEXTURE_2D_ARRAY_MSAA
) {
1477 args
.lod
= args
.coords
[3];
1481 if (target
== TGSI_TEXTURE_2D_MSAA
||
1482 target
== TGSI_TEXTURE_2D_ARRAY_MSAA
) {
1483 ac_apply_fmask_to_sample(&ctx
->ac
, fmask_ptr
, args
.coords
,
1484 target
== TGSI_TEXTURE_2D_ARRAY_MSAA
);
1487 if (opcode
== TGSI_OPCODE_TXF
||
1488 opcode
== TGSI_OPCODE_TXF_LZ
) {
1489 /* add tex offsets */
1490 if (inst
->Texture
.NumOffsets
) {
1491 struct lp_build_context
*uint_bld
= &bld_base
->uint_bld
;
1492 const struct tgsi_texture_offset
*off
= inst
->TexOffsets
;
1494 assert(inst
->Texture
.NumOffsets
== 1);
1497 case TGSI_TEXTURE_3D
:
1498 args
.coords
[2] = lp_build_add(uint_bld
, args
.coords
[2],
1499 ctx
->imms
[off
->Index
* TGSI_NUM_CHANNELS
+ off
->SwizzleZ
]);
1501 case TGSI_TEXTURE_2D
:
1502 case TGSI_TEXTURE_SHADOW2D
:
1503 case TGSI_TEXTURE_RECT
:
1504 case TGSI_TEXTURE_SHADOWRECT
:
1505 case TGSI_TEXTURE_2D_ARRAY
:
1506 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
1508 lp_build_add(uint_bld
, args
.coords
[1],
1509 ctx
->imms
[off
->Index
* TGSI_NUM_CHANNELS
+ off
->SwizzleY
]);
1511 case TGSI_TEXTURE_1D
:
1512 case TGSI_TEXTURE_SHADOW1D
:
1513 case TGSI_TEXTURE_1D_ARRAY
:
1514 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
1516 lp_build_add(uint_bld
, args
.coords
[0],
1517 ctx
->imms
[off
->Index
* TGSI_NUM_CHANNELS
+ off
->SwizzleX
]);
1519 /* texture offsets do not apply to other texture targets */
1526 if (opcode
== TGSI_OPCODE_TG4
) {
1527 unsigned gather_comp
= 0;
1529 /* DMASK was repurposed for GATHER4. 4 components are always
1530 * returned and DMASK works like a swizzle - it selects
1531 * the component to fetch. The only valid DMASK values are
1532 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
1533 * (red,red,red,red) etc.) The ISA document doesn't mention
1537 /* Get the component index from src1.x for Gather4. */
1538 if (!tgsi_is_shadow_target(target
)) {
1539 LLVMValueRef comp_imm
;
1540 struct tgsi_src_register src1
= inst
->Src
[1].Register
;
1542 assert(src1
.File
== TGSI_FILE_IMMEDIATE
);
1544 comp_imm
= ctx
->imms
[src1
.Index
* TGSI_NUM_CHANNELS
+ src1
.SwizzleX
];
1545 gather_comp
= LLVMConstIntGetZExtValue(comp_imm
);
1546 gather_comp
= CLAMP(gather_comp
, 0, 3);
1549 args
.dmask
= 1 << gather_comp
;
1552 set_tex_fetch_args(ctx
, emit_data
, &args
, target
);
1555 /* Gather4 should follow the same rules as bilinear filtering, but the hardware
1556 * incorrectly forces nearest filtering if the texture format is integer.
1557 * The only effect it has on Gather4, which always returns 4 texels for
1558 * bilinear filtering, is that the final coordinates are off by 0.5 of
1561 * The workaround is to subtract 0.5 from the unnormalized coordinates,
1562 * or (0.5 / size) from the normalized coordinates.
1564 * However, cube textures with 8_8_8_8 data formats require a different
1565 * workaround of overriding the num format to USCALED/SSCALED. This would lose
1566 * precision in 32-bit data formats, so it needs to be applied dynamically at
1567 * runtime. In this case, return an i1 value that indicates whether the
1568 * descriptor was overridden (and hence a fixup of the sampler result is needed).
1571 si_lower_gather4_integer(struct si_shader_context
*ctx
,
1572 struct ac_image_args
*args
,
1574 enum tgsi_return_type return_type
)
1576 LLVMBuilderRef builder
= ctx
->ac
.builder
;
1577 LLVMValueRef wa_8888
= NULL
;
1578 LLVMValueRef half_texel
[2];
1580 assert(return_type
== TGSI_RETURN_TYPE_SINT
||
1581 return_type
== TGSI_RETURN_TYPE_UINT
);
1583 if (target
== TGSI_TEXTURE_CUBE
||
1584 target
== TGSI_TEXTURE_CUBE_ARRAY
) {
1585 LLVMValueRef formats
;
1586 LLVMValueRef data_format
;
1587 LLVMValueRef wa_formats
;
1589 formats
= LLVMBuildExtractElement(builder
, args
->resource
, ctx
->i32_1
, "");
1591 data_format
= LLVMBuildLShr(builder
, formats
,
1592 LLVMConstInt(ctx
->i32
, 20, false), "");
1593 data_format
= LLVMBuildAnd(builder
, data_format
,
1594 LLVMConstInt(ctx
->i32
, (1u << 6) - 1, false), "");
1595 wa_8888
= LLVMBuildICmp(
1596 builder
, LLVMIntEQ
, data_format
,
1597 LLVMConstInt(ctx
->i32
, V_008F14_IMG_DATA_FORMAT_8_8_8_8
, false),
1600 uint32_t wa_num_format
=
1601 return_type
== TGSI_RETURN_TYPE_UINT
?
1602 S_008F14_NUM_FORMAT_GFX6(V_008F14_IMG_NUM_FORMAT_USCALED
) :
1603 S_008F14_NUM_FORMAT_GFX6(V_008F14_IMG_NUM_FORMAT_SSCALED
);
1604 wa_formats
= LLVMBuildAnd(builder
, formats
,
1605 LLVMConstInt(ctx
->i32
, C_008F14_NUM_FORMAT_GFX6
, false),
1607 wa_formats
= LLVMBuildOr(builder
, wa_formats
,
1608 LLVMConstInt(ctx
->i32
, wa_num_format
, false), "");
1610 formats
= LLVMBuildSelect(builder
, wa_8888
, wa_formats
, formats
, "");
1611 args
->resource
= LLVMBuildInsertElement(
1612 builder
, args
->resource
, formats
, ctx
->i32_1
, "");
1615 if (target
== TGSI_TEXTURE_RECT
||
1616 target
== TGSI_TEXTURE_SHADOWRECT
) {
1618 half_texel
[0] = half_texel
[1] = LLVMConstReal(ctx
->f32
, -0.5);
1620 struct tgsi_full_instruction txq_inst
= {};
1621 struct ac_image_args txq_args
= {};
1622 struct lp_build_emit_data txq_emit_data
= {};
1623 struct lp_build_if_state if_ctx
;
1626 /* Skip the texture size query entirely if we don't need it. */
1627 lp_build_if(&if_ctx
, &ctx
->gallivm
, LLVMBuildNot(builder
, wa_8888
, ""));
1630 /* Query the texture size. */
1631 txq_inst
.Texture
.Texture
= target
;
1632 txq_emit_data
.inst
= &txq_inst
;
1633 txq_emit_data
.dst_type
= ctx
->v4i32
;
1634 txq_args
.resource
= args
->resource
;
1635 txq_args
.sampler
= args
->sampler
;
1636 txq_args
.lod
= ctx
->ac
.i32_0
;
1637 txq_args
.dmask
= 0xf;
1638 set_tex_fetch_args(ctx
, &txq_emit_data
, &txq_args
, target
);
1639 txq_emit(NULL
, &ctx
->bld_base
, &txq_emit_data
);
1641 /* Compute -0.5 / size. */
1642 for (unsigned c
= 0; c
< 2; c
++) {
1644 LLVMBuildExtractElement(builder
, txq_emit_data
.output
[0],
1645 LLVMConstInt(ctx
->i32
, c
, 0), "");
1646 half_texel
[c
] = LLVMBuildUIToFP(builder
, half_texel
[c
], ctx
->f32
, "");
1648 lp_build_emit_llvm_unary(&ctx
->bld_base
,
1649 TGSI_OPCODE_RCP
, half_texel
[c
]);
1650 half_texel
[c
] = LLVMBuildFMul(builder
, half_texel
[c
],
1651 LLVMConstReal(ctx
->f32
, -0.5), "");
1655 lp_build_endif(&if_ctx
);
1657 LLVMBasicBlockRef bb
[2] = { if_ctx
.true_block
, if_ctx
.entry_block
};
1659 for (unsigned c
= 0; c
< 2; c
++) {
1660 LLVMValueRef values
[2] = { half_texel
[c
], ctx
->ac
.f32_0
};
1661 half_texel
[c
] = ac_build_phi(&ctx
->ac
, ctx
->f32
, 2,
1667 for (unsigned c
= 0; c
< 2; c
++) {
1669 tmp
= ac_to_float(&ctx
->ac
, args
->coords
[c
]);
1670 tmp
= LLVMBuildFAdd(builder
, tmp
, half_texel
[c
], "");
1671 args
->coords
[c
] = ac_to_integer(&ctx
->ac
, tmp
);
1677 /* The second half of the cube texture 8_8_8_8 integer workaround: adjust the
1678 * result after the gather operation.
1681 si_fix_gather4_integer_result(struct si_shader_context
*ctx
,
1682 LLVMValueRef result
,
1683 enum tgsi_return_type return_type
,
1686 LLVMBuilderRef builder
= ctx
->ac
.builder
;
1688 assert(return_type
== TGSI_RETURN_TYPE_SINT
||
1689 return_type
== TGSI_RETURN_TYPE_UINT
);
1691 for (unsigned chan
= 0; chan
< 4; ++chan
) {
1692 LLVMValueRef chanv
= LLVMConstInt(ctx
->i32
, chan
, false);
1694 LLVMValueRef wa_value
;
1696 value
= LLVMBuildExtractElement(builder
, result
, chanv
, "");
1698 if (return_type
== TGSI_RETURN_TYPE_UINT
)
1699 wa_value
= LLVMBuildFPToUI(builder
, value
, ctx
->i32
, "");
1701 wa_value
= LLVMBuildFPToSI(builder
, value
, ctx
->i32
, "");
1702 wa_value
= ac_to_float(&ctx
->ac
, wa_value
);
1703 value
= LLVMBuildSelect(builder
, wa
, wa_value
, value
, "");
1705 result
= LLVMBuildInsertElement(builder
, result
, value
, chanv
, "");
1711 static void build_tex_intrinsic(const struct lp_build_tgsi_action
*action
,
1712 struct lp_build_tgsi_context
*bld_base
,
1713 struct lp_build_emit_data
*emit_data
)
1715 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1716 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
1717 struct ac_image_args args
;
1718 unsigned opcode
= inst
->Instruction
.Opcode
;
1719 unsigned target
= inst
->Texture
.Texture
;
1721 if (target
== TGSI_TEXTURE_BUFFER
) {
1722 unsigned num_channels
=
1723 util_last_bit(inst
->Dst
[0].Register
.WriteMask
);
1724 LLVMValueRef result
=
1725 ac_build_buffer_load_format(&ctx
->ac
,
1729 num_channels
, false, true);
1730 emit_data
->output
[emit_data
->chan
] =
1731 ac_build_expand_to_vec4(&ctx
->ac
, result
, num_channels
);
1735 memcpy(&args
, emit_data
->args
, sizeof(args
)); /* ugly */
1737 args
.opcode
= ac_image_sample
;
1740 case TGSI_OPCODE_TXF
:
1741 case TGSI_OPCODE_TXF_LZ
:
1742 args
.opcode
= opcode
== TGSI_OPCODE_TXF_LZ
||
1743 target
== TGSI_TEXTURE_2D_MSAA
||
1744 target
== TGSI_TEXTURE_2D_ARRAY_MSAA
?
1745 ac_image_load
: ac_image_load_mip
;
1747 case TGSI_OPCODE_LODQ
:
1748 args
.opcode
= ac_image_get_lod
;
1750 case TGSI_OPCODE_TEX
:
1751 case TGSI_OPCODE_TEX2
:
1752 case TGSI_OPCODE_TXP
:
1753 if (ctx
->type
!= PIPE_SHADER_FRAGMENT
)
1754 args
.level_zero
= true;
1756 case TGSI_OPCODE_TEX_LZ
:
1757 args
.level_zero
= true;
1759 case TGSI_OPCODE_TXB
:
1760 case TGSI_OPCODE_TXB2
:
1761 assert(ctx
->type
== PIPE_SHADER_FRAGMENT
);
1763 case TGSI_OPCODE_TXL
:
1764 case TGSI_OPCODE_TXL2
:
1766 case TGSI_OPCODE_TXD
:
1768 case TGSI_OPCODE_TG4
:
1769 args
.opcode
= ac_image_gather4
;
1770 args
.level_zero
= true;
1777 /* The hardware needs special lowering for Gather4 with integer formats. */
1778 LLVMValueRef gather4_int_result_workaround
= NULL
;
1780 if (ctx
->screen
->info
.chip_class
<= VI
&&
1781 opcode
== TGSI_OPCODE_TG4
) {
1782 assert(inst
->Texture
.ReturnType
!= TGSI_RETURN_TYPE_UNKNOWN
);
1784 if (inst
->Texture
.ReturnType
== TGSI_RETURN_TYPE_SINT
||
1785 inst
->Texture
.ReturnType
== TGSI_RETURN_TYPE_UINT
) {
1786 gather4_int_result_workaround
=
1787 si_lower_gather4_integer(ctx
, &args
, target
,
1788 inst
->Texture
.ReturnType
);
1792 args
.attributes
= AC_FUNC_ATTR_READNONE
;
1793 LLVMValueRef result
= ac_build_image_opcode(&ctx
->ac
, &args
);
1795 if (gather4_int_result_workaround
) {
1796 result
= si_fix_gather4_integer_result(ctx
, result
,
1797 inst
->Texture
.ReturnType
,
1798 gather4_int_result_workaround
);
1801 emit_data
->output
[emit_data
->chan
] = result
;
1804 static void si_llvm_emit_txqs(
1805 const struct lp_build_tgsi_action
*action
,
1806 struct lp_build_tgsi_context
*bld_base
,
1807 struct lp_build_emit_data
*emit_data
)
1809 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1810 LLVMValueRef res
, samples
;
1811 LLVMValueRef res_ptr
, samp_ptr
, fmask_ptr
= NULL
;
1813 tex_fetch_ptrs(bld_base
, emit_data
, &res_ptr
, &samp_ptr
, &fmask_ptr
);
1815 /* Read the samples from the descriptor directly. */
1816 res
= LLVMBuildBitCast(ctx
->ac
.builder
, res_ptr
, ctx
->v8i32
, "");
1817 samples
= LLVMBuildExtractElement(ctx
->ac
.builder
, res
,
1818 LLVMConstInt(ctx
->i32
, 3, 0), "");
1819 samples
= LLVMBuildLShr(ctx
->ac
.builder
, samples
,
1820 LLVMConstInt(ctx
->i32
, 16, 0), "");
1821 samples
= LLVMBuildAnd(ctx
->ac
.builder
, samples
,
1822 LLVMConstInt(ctx
->i32
, 0xf, 0), "");
1823 samples
= LLVMBuildShl(ctx
->ac
.builder
, ctx
->i32_1
,
1826 emit_data
->output
[emit_data
->chan
] = samples
;
1829 static void si_llvm_emit_fbfetch(const struct lp_build_tgsi_action
*action
,
1830 struct lp_build_tgsi_context
*bld_base
,
1831 struct lp_build_emit_data
*emit_data
)
1833 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1834 struct ac_image_args args
= {};
1835 LLVMValueRef ptr
, image
, fmask
;
1837 /* Ignore src0, because KHR_blend_func_extended disallows multiple render
1841 /* Load the image descriptor. */
1842 STATIC_ASSERT(SI_PS_IMAGE_COLORBUF0
% 2 == 0);
1843 ptr
= LLVMGetParam(ctx
->main_fn
, ctx
->param_rw_buffers
);
1844 ptr
= LLVMBuildPointerCast(ctx
->ac
.builder
, ptr
,
1845 ac_array_in_const32_addr_space(ctx
->v8i32
), "");
1846 image
= ac_build_load_to_sgpr(&ctx
->ac
, ptr
,
1847 LLVMConstInt(ctx
->i32
, SI_PS_IMAGE_COLORBUF0
/ 2, 0));
1851 args
.coords
[chan
++] = si_unpack_param(ctx
, SI_PARAM_POS_FIXED_PT
, 0, 16);
1853 if (!ctx
->shader
->key
.mono
.u
.ps
.fbfetch_is_1D
)
1854 args
.coords
[chan
++] = si_unpack_param(ctx
, SI_PARAM_POS_FIXED_PT
, 16, 16);
1856 /* Get the current render target layer index. */
1857 if (ctx
->shader
->key
.mono
.u
.ps
.fbfetch_layered
)
1858 args
.coords
[chan
++] = si_unpack_param(ctx
, SI_PARAM_ANCILLARY
, 16, 11);
1860 if (ctx
->shader
->key
.mono
.u
.ps
.fbfetch_msaa
)
1861 args
.coords
[chan
++] = si_get_sample_id(ctx
);
1863 if (ctx
->shader
->key
.mono
.u
.ps
.fbfetch_msaa
) {
1864 fmask
= ac_build_load_to_sgpr(&ctx
->ac
, ptr
,
1865 LLVMConstInt(ctx
->i32
, SI_PS_IMAGE_COLORBUF0_FMASK
/ 2, 0));
1867 ac_apply_fmask_to_sample(&ctx
->ac
, fmask
, args
.coords
,
1868 ctx
->shader
->key
.mono
.u
.ps
.fbfetch_layered
);
1871 args
.opcode
= ac_image_load
;
1872 args
.resource
= image
;
1874 if (ctx
->shader
->key
.mono
.u
.ps
.fbfetch_msaa
)
1875 args
.dim
= ctx
->shader
->key
.mono
.u
.ps
.fbfetch_layered
?
1876 ac_image_2darraymsaa
: ac_image_2dmsaa
;
1877 else if (ctx
->shader
->key
.mono
.u
.ps
.fbfetch_is_1D
)
1878 args
.dim
= ctx
->shader
->key
.mono
.u
.ps
.fbfetch_layered
?
1879 ac_image_1darray
: ac_image_1d
;
1881 args
.dim
= ctx
->shader
->key
.mono
.u
.ps
.fbfetch_layered
?
1882 ac_image_2darray
: ac_image_2d
;
1884 emit_data
->output
[emit_data
->chan
] =
1885 ac_build_image_opcode(&ctx
->ac
, &args
);
1888 static const struct lp_build_tgsi_action tex_action
= {
1889 .fetch_args
= tex_fetch_args
,
1890 .emit
= build_tex_intrinsic
,
1894 * Setup actions for TGSI memory opcode, including texture opcodes.
1896 void si_shader_context_init_mem(struct si_shader_context
*ctx
)
1898 struct lp_build_tgsi_context
*bld_base
;
1899 struct lp_build_tgsi_action tmpl
= {};
1901 bld_base
= &ctx
->bld_base
;
1903 bld_base
->op_actions
[TGSI_OPCODE_TEX
] = tex_action
;
1904 bld_base
->op_actions
[TGSI_OPCODE_TEX_LZ
] = tex_action
;
1905 bld_base
->op_actions
[TGSI_OPCODE_TEX2
] = tex_action
;
1906 bld_base
->op_actions
[TGSI_OPCODE_TXB
] = tex_action
;
1907 bld_base
->op_actions
[TGSI_OPCODE_TXB2
] = tex_action
;
1908 bld_base
->op_actions
[TGSI_OPCODE_TXD
] = tex_action
;
1909 bld_base
->op_actions
[TGSI_OPCODE_TXF
] = tex_action
;
1910 bld_base
->op_actions
[TGSI_OPCODE_TXF_LZ
] = tex_action
;
1911 bld_base
->op_actions
[TGSI_OPCODE_TXL
] = tex_action
;
1912 bld_base
->op_actions
[TGSI_OPCODE_TXL2
] = tex_action
;
1913 bld_base
->op_actions
[TGSI_OPCODE_TXP
] = tex_action
;
1914 bld_base
->op_actions
[TGSI_OPCODE_TXQ
].fetch_args
= txq_fetch_args
;
1915 bld_base
->op_actions
[TGSI_OPCODE_TXQ
].emit
= txq_emit
;
1916 bld_base
->op_actions
[TGSI_OPCODE_TG4
] = tex_action
;
1917 bld_base
->op_actions
[TGSI_OPCODE_LODQ
] = tex_action
;
1918 bld_base
->op_actions
[TGSI_OPCODE_TXQS
].emit
= si_llvm_emit_txqs
;
1920 bld_base
->op_actions
[TGSI_OPCODE_FBFETCH
].emit
= si_llvm_emit_fbfetch
;
1922 bld_base
->op_actions
[TGSI_OPCODE_LOAD
].fetch_args
= load_fetch_args
;
1923 bld_base
->op_actions
[TGSI_OPCODE_LOAD
].emit
= load_emit
;
1924 bld_base
->op_actions
[TGSI_OPCODE_STORE
].fetch_args
= store_fetch_args
;
1925 bld_base
->op_actions
[TGSI_OPCODE_STORE
].emit
= store_emit
;
1926 bld_base
->op_actions
[TGSI_OPCODE_RESQ
].fetch_args
= resq_fetch_args
;
1927 bld_base
->op_actions
[TGSI_OPCODE_RESQ
].emit
= resq_emit
;
1929 tmpl
.fetch_args
= atomic_fetch_args
;
1930 tmpl
.emit
= atomic_emit
;
1931 bld_base
->op_actions
[TGSI_OPCODE_ATOMUADD
] = tmpl
;
1932 bld_base
->op_actions
[TGSI_OPCODE_ATOMUADD
].intr_name
= "add";
1933 bld_base
->op_actions
[TGSI_OPCODE_ATOMXCHG
] = tmpl
;
1934 bld_base
->op_actions
[TGSI_OPCODE_ATOMXCHG
].intr_name
= "swap";
1935 bld_base
->op_actions
[TGSI_OPCODE_ATOMCAS
] = tmpl
;
1936 bld_base
->op_actions
[TGSI_OPCODE_ATOMCAS
].intr_name
= "cmpswap";
1937 bld_base
->op_actions
[TGSI_OPCODE_ATOMAND
] = tmpl
;
1938 bld_base
->op_actions
[TGSI_OPCODE_ATOMAND
].intr_name
= "and";
1939 bld_base
->op_actions
[TGSI_OPCODE_ATOMOR
] = tmpl
;
1940 bld_base
->op_actions
[TGSI_OPCODE_ATOMOR
].intr_name
= "or";
1941 bld_base
->op_actions
[TGSI_OPCODE_ATOMXOR
] = tmpl
;
1942 bld_base
->op_actions
[TGSI_OPCODE_ATOMXOR
].intr_name
= "xor";
1943 bld_base
->op_actions
[TGSI_OPCODE_ATOMUMIN
] = tmpl
;
1944 bld_base
->op_actions
[TGSI_OPCODE_ATOMUMIN
].intr_name
= "umin";
1945 bld_base
->op_actions
[TGSI_OPCODE_ATOMUMAX
] = tmpl
;
1946 bld_base
->op_actions
[TGSI_OPCODE_ATOMUMAX
].intr_name
= "umax";
1947 bld_base
->op_actions
[TGSI_OPCODE_ATOMIMIN
] = tmpl
;
1948 bld_base
->op_actions
[TGSI_OPCODE_ATOMIMIN
].intr_name
= "smin";
1949 bld_base
->op_actions
[TGSI_OPCODE_ATOMIMAX
] = tmpl
;
1950 bld_base
->op_actions
[TGSI_OPCODE_ATOMIMAX
].intr_name
= "smax";