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radeonsi: use structured buffer intrinsics for image views
[mesa.git] / src / gallium / drivers / radeonsi / si_shader_tgsi_mem.c
1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_shader_internal.h"
26 #include "si_pipe.h"
27 #include "sid.h"
28 #include "tgsi/tgsi_build.h"
29 #include "tgsi/tgsi_util.h"
30 #include "ac_llvm_util.h"
31
32 static void tex_fetch_ptrs(struct lp_build_tgsi_context *bld_base,
33 struct lp_build_emit_data *emit_data,
34 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
35 LLVMValueRef *fmask_ptr);
36
37 /**
38 * Given a v8i32 resource descriptor for a buffer, extract the size of the
39 * buffer in number of elements and return it as an i32.
40 */
41 static LLVMValueRef get_buffer_size(
42 struct lp_build_tgsi_context *bld_base,
43 LLVMValueRef descriptor)
44 {
45 struct si_shader_context *ctx = si_shader_context(bld_base);
46 LLVMBuilderRef builder = ctx->ac.builder;
47 LLVMValueRef size =
48 LLVMBuildExtractElement(builder, descriptor,
49 LLVMConstInt(ctx->i32, 2, 0), "");
50
51 if (ctx->screen->info.chip_class == VI) {
52 /* On VI, the descriptor contains the size in bytes,
53 * but TXQ must return the size in elements.
54 * The stride is always non-zero for resources using TXQ.
55 */
56 LLVMValueRef stride =
57 LLVMBuildExtractElement(builder, descriptor,
58 ctx->i32_1, "");
59 stride = LLVMBuildLShr(builder, stride,
60 LLVMConstInt(ctx->i32, 16, 0), "");
61 stride = LLVMBuildAnd(builder, stride,
62 LLVMConstInt(ctx->i32, 0x3FFF, 0), "");
63
64 size = LLVMBuildUDiv(builder, size, stride, "");
65 }
66
67 return size;
68 }
69
70 static LLVMValueRef
71 shader_buffer_fetch_rsrc(struct si_shader_context *ctx,
72 const struct tgsi_full_src_register *reg,
73 bool ubo)
74 {
75 LLVMValueRef index;
76
77 if (!reg->Register.Indirect) {
78 index = LLVMConstInt(ctx->i32, reg->Register.Index, false);
79 } else {
80 index = si_get_indirect_index(ctx, &reg->Indirect,
81 1, reg->Register.Index);
82 }
83
84 if (ubo)
85 return ctx->abi.load_ubo(&ctx->abi, index);
86 else
87 return ctx->abi.load_ssbo(&ctx->abi, index, false);
88 }
89
90 static enum ac_image_dim
91 ac_texture_dim_from_tgsi_target(struct si_screen *screen, enum tgsi_texture_type target)
92 {
93 switch (target) {
94 case TGSI_TEXTURE_1D:
95 case TGSI_TEXTURE_SHADOW1D:
96 if (screen->info.chip_class >= GFX9)
97 return ac_image_2d;
98 return ac_image_1d;
99 case TGSI_TEXTURE_2D:
100 case TGSI_TEXTURE_SHADOW2D:
101 case TGSI_TEXTURE_RECT:
102 case TGSI_TEXTURE_SHADOWRECT:
103 return ac_image_2d;
104 case TGSI_TEXTURE_3D:
105 return ac_image_3d;
106 case TGSI_TEXTURE_CUBE:
107 case TGSI_TEXTURE_SHADOWCUBE:
108 case TGSI_TEXTURE_CUBE_ARRAY:
109 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
110 return ac_image_cube;
111 case TGSI_TEXTURE_1D_ARRAY:
112 case TGSI_TEXTURE_SHADOW1D_ARRAY:
113 if (screen->info.chip_class >= GFX9)
114 return ac_image_2darray;
115 return ac_image_1darray;
116 case TGSI_TEXTURE_2D_ARRAY:
117 case TGSI_TEXTURE_SHADOW2D_ARRAY:
118 return ac_image_2darray;
119 case TGSI_TEXTURE_2D_MSAA:
120 return ac_image_2dmsaa;
121 case TGSI_TEXTURE_2D_ARRAY_MSAA:
122 return ac_image_2darraymsaa;
123 default:
124 unreachable("unhandled texture type");
125 }
126 }
127
128 static enum ac_image_dim
129 ac_image_dim_from_tgsi_target(struct si_screen *screen, enum tgsi_texture_type target)
130 {
131 enum ac_image_dim dim = ac_texture_dim_from_tgsi_target(screen, target);
132
133 /* Match the resource type set in the descriptor. */
134 if (dim == ac_image_cube ||
135 (screen->info.chip_class <= VI && dim == ac_image_3d))
136 dim = ac_image_2darray;
137 else if (target == TGSI_TEXTURE_2D && screen->info.chip_class >= GFX9) {
138 /* When a single layer of a 3D texture is bound, the shader
139 * will refer to a 2D target, but the descriptor has a 3D type.
140 * Since the HW ignores BASE_ARRAY in this case, we need to
141 * send 3 coordinates. This doesn't hurt when the underlying
142 * texture is non-3D.
143 */
144 dim = ac_image_3d;
145 }
146
147 return dim;
148 }
149
150 /**
151 * Given a 256-bit resource descriptor, force the DCC enable bit to off.
152 *
153 * At least on Tonga, executing image stores on images with DCC enabled and
154 * non-trivial can eventually lead to lockups. This can occur when an
155 * application binds an image as read-only but then uses a shader that writes
156 * to it. The OpenGL spec allows almost arbitrarily bad behavior (including
157 * program termination) in this case, but it doesn't cost much to be a bit
158 * nicer: disabling DCC in the shader still leads to undefined results but
159 * avoids the lockup.
160 */
161 static LLVMValueRef force_dcc_off(struct si_shader_context *ctx,
162 LLVMValueRef rsrc)
163 {
164 if (ctx->screen->info.chip_class <= CIK) {
165 return rsrc;
166 } else {
167 LLVMValueRef i32_6 = LLVMConstInt(ctx->i32, 6, 0);
168 LLVMValueRef i32_C = LLVMConstInt(ctx->i32, C_008F28_COMPRESSION_EN, 0);
169 LLVMValueRef tmp;
170
171 tmp = LLVMBuildExtractElement(ctx->ac.builder, rsrc, i32_6, "");
172 tmp = LLVMBuildAnd(ctx->ac.builder, tmp, i32_C, "");
173 return LLVMBuildInsertElement(ctx->ac.builder, rsrc, tmp, i32_6, "");
174 }
175 }
176
177 LLVMValueRef si_load_image_desc(struct si_shader_context *ctx,
178 LLVMValueRef list, LLVMValueRef index,
179 enum ac_descriptor_type desc_type, bool dcc_off,
180 bool bindless)
181 {
182 LLVMBuilderRef builder = ctx->ac.builder;
183 LLVMValueRef rsrc;
184
185 if (desc_type == AC_DESC_BUFFER) {
186 index = ac_build_imad(&ctx->ac, index, LLVMConstInt(ctx->i32, 2, 0),
187 ctx->i32_1);
188 list = LLVMBuildPointerCast(builder, list,
189 ac_array_in_const32_addr_space(ctx->v4i32), "");
190 } else {
191 assert(desc_type == AC_DESC_IMAGE);
192 }
193
194 if (bindless)
195 rsrc = ac_build_load_to_sgpr_uint_wraparound(&ctx->ac, list, index);
196 else
197 rsrc = ac_build_load_to_sgpr(&ctx->ac, list, index);
198
199 if (desc_type == AC_DESC_IMAGE && dcc_off)
200 rsrc = force_dcc_off(ctx, rsrc);
201 return rsrc;
202 }
203
204 /**
205 * Load the resource descriptor for \p image.
206 */
207 static void
208 image_fetch_rsrc(
209 struct lp_build_tgsi_context *bld_base,
210 const struct tgsi_full_src_register *image,
211 bool is_store, unsigned target,
212 LLVMValueRef *rsrc)
213 {
214 struct si_shader_context *ctx = si_shader_context(bld_base);
215 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
216 ctx->param_samplers_and_images);
217 LLVMValueRef index;
218 bool dcc_off = is_store;
219
220 if (!image->Register.Indirect) {
221 const struct tgsi_shader_info *info = bld_base->info;
222 unsigned images_writemask = info->images_store |
223 info->images_atomic;
224
225 index = LLVMConstInt(ctx->i32,
226 si_get_image_slot(image->Register.Index), 0);
227
228 if (images_writemask & (1 << image->Register.Index))
229 dcc_off = true;
230 } else {
231 /* From the GL_ARB_shader_image_load_store extension spec:
232 *
233 * If a shader performs an image load, store, or atomic
234 * operation using an image variable declared as an array,
235 * and if the index used to select an individual element is
236 * negative or greater than or equal to the size of the
237 * array, the results of the operation are undefined but may
238 * not lead to termination.
239 */
240 index = si_get_bounded_indirect_index(ctx, &image->Indirect,
241 image->Register.Index,
242 ctx->num_images);
243 index = LLVMBuildSub(ctx->ac.builder,
244 LLVMConstInt(ctx->i32, SI_NUM_IMAGES - 1, 0),
245 index, "");
246 }
247
248 bool bindless = false;
249
250 if (image->Register.File != TGSI_FILE_IMAGE) {
251 /* Bindless descriptors are accessible from a different pair of
252 * user SGPR indices.
253 */
254 rsrc_ptr = LLVMGetParam(ctx->main_fn,
255 ctx->param_bindless_samplers_and_images);
256 index = lp_build_emit_fetch_src(bld_base, image,
257 TGSI_TYPE_UNSIGNED, 0);
258
259 /* For simplicity, bindless image descriptors use fixed
260 * 16-dword slots for now.
261 */
262 index = LLVMBuildMul(ctx->ac.builder, index,
263 LLVMConstInt(ctx->i32, 2, 0), "");
264 bindless = true;
265 }
266
267 *rsrc = si_load_image_desc(ctx, rsrc_ptr, index,
268 target == TGSI_TEXTURE_BUFFER ? AC_DESC_BUFFER : AC_DESC_IMAGE,
269 dcc_off, bindless);
270 }
271
272 static void image_fetch_coords(
273 struct lp_build_tgsi_context *bld_base,
274 const struct tgsi_full_instruction *inst,
275 unsigned src, LLVMValueRef desc,
276 LLVMValueRef *coords)
277 {
278 struct si_shader_context *ctx = si_shader_context(bld_base);
279 LLVMBuilderRef builder = ctx->ac.builder;
280 unsigned target = inst->Memory.Texture;
281 unsigned num_coords = tgsi_util_get_texture_coord_dim(target);
282 LLVMValueRef tmp;
283 int chan;
284
285 if (target == TGSI_TEXTURE_2D_MSAA ||
286 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
287 /* Need the sample index as well. */
288 num_coords++;
289 }
290
291 for (chan = 0; chan < num_coords; ++chan) {
292 tmp = lp_build_emit_fetch(bld_base, inst, src, chan);
293 tmp = ac_to_integer(&ctx->ac, tmp);
294 coords[chan] = tmp;
295 }
296
297 if (ctx->screen->info.chip_class >= GFX9) {
298 /* 1D textures are allocated and used as 2D on GFX9. */
299 if (target == TGSI_TEXTURE_1D) {
300 coords[1] = ctx->i32_0;
301 } else if (target == TGSI_TEXTURE_1D_ARRAY) {
302 coords[2] = coords[1];
303 coords[1] = ctx->i32_0;
304 } else if (target == TGSI_TEXTURE_2D) {
305 /* The hw can't bind a slice of a 3D image as a 2D
306 * image, because it ignores BASE_ARRAY if the target
307 * is 3D. The workaround is to read BASE_ARRAY and set
308 * it as the 3rd address operand for all 2D images.
309 */
310 LLVMValueRef first_layer, const5, mask;
311
312 const5 = LLVMConstInt(ctx->i32, 5, 0);
313 mask = LLVMConstInt(ctx->i32, S_008F24_BASE_ARRAY(~0), 0);
314 first_layer = LLVMBuildExtractElement(builder, desc, const5, "");
315 first_layer = LLVMBuildAnd(builder, first_layer, mask, "");
316
317 coords[2] = first_layer;
318 }
319 }
320 }
321
322 static unsigned get_cache_policy(struct si_shader_context *ctx,
323 const struct tgsi_full_instruction *inst,
324 bool atomic, bool may_store_unaligned,
325 bool writeonly_memory)
326 {
327 unsigned cache_policy = 0;
328
329 if (!atomic &&
330 /* SI has a TC L1 bug causing corruption of 8bit/16bit stores.
331 * All store opcodes not aligned to a dword are affected.
332 * The only way to get unaligned stores in radeonsi is through
333 * shader images. */
334 ((may_store_unaligned && ctx->screen->info.chip_class == SI) ||
335 /* If this is write-only, don't keep data in L1 to prevent
336 * evicting L1 cache lines that may be needed by other
337 * instructions. */
338 writeonly_memory ||
339 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE)))
340 cache_policy |= ac_glc;
341
342 if (inst->Memory.Qualifier & TGSI_MEMORY_STREAM_CACHE_POLICY)
343 cache_policy |= ac_slc;
344
345 return cache_policy;
346 }
347
348 static LLVMValueRef get_memory_ptr(struct si_shader_context *ctx,
349 const struct tgsi_full_instruction *inst,
350 LLVMTypeRef type, int arg)
351 {
352 LLVMBuilderRef builder = ctx->ac.builder;
353 LLVMValueRef offset, ptr;
354 int addr_space;
355
356 offset = lp_build_emit_fetch(&ctx->bld_base, inst, arg, 0);
357 offset = ac_to_integer(&ctx->ac, offset);
358
359 ptr = ctx->ac.lds;
360 ptr = LLVMBuildGEP(builder, ptr, &offset, 1, "");
361 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
362 ptr = LLVMBuildBitCast(builder, ptr, LLVMPointerType(type, addr_space), "");
363
364 return ptr;
365 }
366
367 static void load_emit_memory(
368 struct si_shader_context *ctx,
369 struct lp_build_emit_data *emit_data)
370 {
371 const struct tgsi_full_instruction *inst = emit_data->inst;
372 unsigned writemask = inst->Dst[0].Register.WriteMask;
373 LLVMValueRef channels[4], ptr, derived_ptr, index;
374 int chan;
375
376 ptr = get_memory_ptr(ctx, inst, ctx->f32, 1);
377
378 for (chan = 0; chan < 4; ++chan) {
379 if (!(writemask & (1 << chan))) {
380 channels[chan] = LLVMGetUndef(ctx->f32);
381 continue;
382 }
383
384 index = LLVMConstInt(ctx->i32, chan, 0);
385 derived_ptr = LLVMBuildGEP(ctx->ac.builder, ptr, &index, 1, "");
386 channels[chan] = LLVMBuildLoad(ctx->ac.builder, derived_ptr, "");
387 }
388 emit_data->output[emit_data->chan] = ac_build_gather_values(&ctx->ac, channels, 4);
389 }
390
391 /**
392 * Return true if the memory accessed by a LOAD or STORE instruction is
393 * read-only or write-only, respectively.
394 *
395 * \param shader_buffers_reverse_access_mask
396 * For LOAD, set this to (store | atomic) slot usage in the shader.
397 * For STORE, set this to (load | atomic) slot usage in the shader.
398 * \param images_reverse_access_mask Same as above, but for images.
399 */
400 static bool is_oneway_access_only(const struct tgsi_full_instruction *inst,
401 const struct tgsi_shader_info *info,
402 unsigned shader_buffers_reverse_access_mask,
403 unsigned images_reverse_access_mask)
404 {
405 /* RESTRICT means NOALIAS.
406 * If there are no writes, we can assume the accessed memory is read-only.
407 * If there are no reads, we can assume the accessed memory is write-only.
408 */
409 if (inst->Memory.Qualifier & TGSI_MEMORY_RESTRICT) {
410 unsigned reverse_access_mask;
411
412 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
413 reverse_access_mask = shader_buffers_reverse_access_mask;
414 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
415 reverse_access_mask = info->images_buffers &
416 images_reverse_access_mask;
417 } else {
418 reverse_access_mask = ~info->images_buffers &
419 images_reverse_access_mask;
420 }
421
422 if (inst->Src[0].Register.Indirect) {
423 if (!reverse_access_mask)
424 return true;
425 } else {
426 if (!(reverse_access_mask &
427 (1u << inst->Src[0].Register.Index)))
428 return true;
429 }
430 }
431
432 /* If there are no buffer writes (for both shader buffers & image
433 * buffers), it implies that buffer memory is read-only.
434 * If there are no buffer reads (for both shader buffers & image
435 * buffers), it implies that buffer memory is write-only.
436 *
437 * Same for the case when there are no writes/reads for non-buffer
438 * images.
439 */
440 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
441 (inst->Memory.Texture == TGSI_TEXTURE_BUFFER &&
442 (inst->Src[0].Register.File == TGSI_FILE_IMAGE ||
443 tgsi_is_bindless_image_file(inst->Src[0].Register.File)))) {
444 if (!shader_buffers_reverse_access_mask &&
445 !(info->images_buffers & images_reverse_access_mask))
446 return true;
447 } else {
448 if (!(~info->images_buffers & images_reverse_access_mask))
449 return true;
450 }
451 return false;
452 }
453
454 static void load_emit(
455 const struct lp_build_tgsi_action *action,
456 struct lp_build_tgsi_context *bld_base,
457 struct lp_build_emit_data *emit_data)
458 {
459 struct si_shader_context *ctx = si_shader_context(bld_base);
460 const struct tgsi_full_instruction * inst = emit_data->inst;
461 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
462 bool can_speculate = false;
463 LLVMValueRef vindex = ctx->i32_0;
464 LLVMValueRef voffset = ctx->i32_0;
465 struct ac_image_args args = {};
466
467 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
468 load_emit_memory(ctx, emit_data);
469 return;
470 }
471
472 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
473 inst->Src[0].Register.File == TGSI_FILE_CONSTBUF) {
474 bool ubo = inst->Src[0].Register.File == TGSI_FILE_CONSTBUF;
475 args.resource = shader_buffer_fetch_rsrc(ctx, &inst->Src[0], ubo);
476 voffset = ac_to_integer(&ctx->ac, lp_build_emit_fetch(bld_base, inst, 1, 0));
477 } else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE ||
478 tgsi_is_bindless_image_file(inst->Src[0].Register.File)) {
479 unsigned target = inst->Memory.Texture;
480
481 image_fetch_rsrc(bld_base, &inst->Src[0], false, target, &args.resource);
482 image_fetch_coords(bld_base, inst, 1, args.resource, args.coords);
483 vindex = args.coords[0]; /* for buffers only */
484 }
485
486 if (inst->Src[0].Register.File == TGSI_FILE_CONSTBUF) {
487 emit_data->output[emit_data->chan] =
488 ac_build_buffer_load(&ctx->ac, args.resource,
489 util_last_bit(inst->Dst[0].Register.WriteMask),
490 NULL, voffset, NULL, 0, 0, 0, true, true);
491 return;
492 }
493
494 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
495 ac_build_waitcnt(&ctx->ac, VM_CNT);
496
497 can_speculate = !(inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE) &&
498 is_oneway_access_only(inst, info,
499 info->shader_buffers_store |
500 info->shader_buffers_atomic,
501 info->images_store |
502 info->images_atomic);
503 args.cache_policy = get_cache_policy(ctx, inst, false, false, false);
504
505 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
506 /* Don't use SMEM for shader buffer loads, because LLVM doesn't
507 * select SMEM for SI.load.const with a non-constant offset, and
508 * constant offsets practically don't exist with shader buffers.
509 *
510 * Also, SI.load.const doesn't use inst_offset when it's lowered
511 * to VMEM, so we just end up with more VALU instructions in the end
512 * and no benefit.
513 *
514 * TODO: Remove this line once LLVM can select SMEM with a non-constant
515 * offset, and can derive inst_offset when VMEM is selected.
516 * After that, si_memory_barrier should invalidate sL1 for shader
517 * buffers.
518 */
519 emit_data->output[emit_data->chan] =
520 ac_build_buffer_load(&ctx->ac, args.resource,
521 util_last_bit(inst->Dst[0].Register.WriteMask),
522 NULL, voffset, NULL, 0,
523 !!(args.cache_policy & ac_glc),
524 !!(args.cache_policy & ac_slc),
525 can_speculate, false);
526 return;
527 }
528
529 if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
530 unsigned num_channels = util_last_bit(inst->Dst[0].Register.WriteMask);
531 LLVMValueRef result =
532 ac_build_buffer_load_format(&ctx->ac,
533 args.resource,
534 vindex,
535 ctx->i32_0,
536 num_channels,
537 !!(args.cache_policy & ac_glc),
538 can_speculate);
539 emit_data->output[emit_data->chan] =
540 ac_build_expand_to_vec4(&ctx->ac, result, num_channels);
541 } else {
542 args.opcode = ac_image_load;
543 args.dim = ac_image_dim_from_tgsi_target(ctx->screen, inst->Memory.Texture);
544 args.attributes = ac_get_load_intr_attribs(can_speculate);
545 args.dmask = 0xf;
546
547 emit_data->output[emit_data->chan] =
548 ac_build_image_opcode(&ctx->ac, &args);
549 }
550 }
551
552 static void store_emit_buffer(struct si_shader_context *ctx,
553 LLVMValueRef resource,
554 unsigned writemask,
555 LLVMValueRef value,
556 LLVMValueRef voffset,
557 unsigned cache_policy,
558 bool writeonly_memory)
559 {
560 LLVMBuilderRef builder = ctx->ac.builder;
561 LLVMValueRef base_data = value;
562 LLVMValueRef base_offset = voffset;
563
564 while (writemask) {
565 int start, count;
566 const char *intrinsic_name;
567 LLVMValueRef data, voff;
568
569 u_bit_scan_consecutive_range(&writemask, &start, &count);
570
571 /* Due to an LLVM limitation, split 3-element writes
572 * into a 2-element and a 1-element write. */
573 if (count == 3) {
574 writemask |= 1 << (start + 2);
575 count = 2;
576 }
577
578 if (count == 4) {
579 data = base_data;
580 intrinsic_name = "llvm.amdgcn.buffer.store.v4f32";
581 } else if (count == 2) {
582 LLVMValueRef values[2] = {
583 LLVMBuildExtractElement(builder, base_data,
584 LLVMConstInt(ctx->i32, start, 0), ""),
585 LLVMBuildExtractElement(builder, base_data,
586 LLVMConstInt(ctx->i32, start + 1, 0), ""),
587 };
588
589 data = ac_build_gather_values(&ctx->ac, values, 2);
590 intrinsic_name = "llvm.amdgcn.buffer.store.v2f32";
591 } else {
592 assert(count == 1);
593 data = LLVMBuildExtractElement(
594 builder, base_data,
595 LLVMConstInt(ctx->i32, start, 0), "");
596 intrinsic_name = "llvm.amdgcn.buffer.store.f32";
597 }
598
599 voff = base_offset;
600 if (start != 0) {
601 voff = LLVMBuildAdd(
602 builder, voff,
603 LLVMConstInt(ctx->i32, start * 4, 0), "");
604 }
605
606 LLVMValueRef args[] = {
607 data,
608 resource,
609 ctx->i32_0, /* vindex */
610 voff,
611 LLVMConstInt(ctx->i1, !!(cache_policy & ac_glc), 0),
612 LLVMConstInt(ctx->i1, !!(cache_policy & ac_slc), 0),
613 };
614 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->voidt, args, 6,
615 ac_get_store_intr_attribs(writeonly_memory));
616 }
617 }
618
619 static void store_emit_memory(
620 struct si_shader_context *ctx,
621 struct lp_build_emit_data *emit_data)
622 {
623 const struct tgsi_full_instruction *inst = emit_data->inst;
624 LLVMBuilderRef builder = ctx->ac.builder;
625 unsigned writemask = inst->Dst[0].Register.WriteMask;
626 LLVMValueRef ptr, derived_ptr, data, index;
627 int chan;
628
629 ptr = get_memory_ptr(ctx, inst, ctx->f32, 0);
630
631 for (chan = 0; chan < 4; ++chan) {
632 if (!(writemask & (1 << chan))) {
633 continue;
634 }
635 data = lp_build_emit_fetch(&ctx->bld_base, inst, 1, chan);
636 index = LLVMConstInt(ctx->i32, chan, 0);
637 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
638 LLVMBuildStore(builder, data, derived_ptr);
639 }
640 }
641
642 static void store_emit(
643 const struct lp_build_tgsi_action *action,
644 struct lp_build_tgsi_context *bld_base,
645 struct lp_build_emit_data *emit_data)
646 {
647 struct si_shader_context *ctx = si_shader_context(bld_base);
648 const struct tgsi_full_instruction * inst = emit_data->inst;
649 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
650 struct tgsi_full_src_register resource_reg =
651 tgsi_full_src_register_from_dst(&inst->Dst[0]);
652 unsigned target = inst->Memory.Texture;
653 bool writeonly_memory = is_oneway_access_only(inst, info,
654 info->shader_buffers_load |
655 info->shader_buffers_atomic,
656 info->images_load |
657 info->images_atomic);
658 bool is_image = inst->Dst[0].Register.File == TGSI_FILE_IMAGE ||
659 tgsi_is_bindless_image_file(inst->Dst[0].Register.File);
660 LLVMValueRef chans[4], value;
661 LLVMValueRef vindex = ctx->i32_0;
662 LLVMValueRef voffset = ctx->i32_0;
663 struct ac_image_args args = {};
664
665 if (inst->Dst[0].Register.File == TGSI_FILE_MEMORY) {
666 store_emit_memory(ctx, emit_data);
667 return;
668 }
669
670 for (unsigned chan = 0; chan < 4; ++chan)
671 chans[chan] = lp_build_emit_fetch(bld_base, inst, 1, chan);
672
673 value = ac_build_gather_values(&ctx->ac, chans, 4);
674
675 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
676 args.resource = shader_buffer_fetch_rsrc(ctx, &resource_reg, false);
677 voffset = ac_to_integer(&ctx->ac, lp_build_emit_fetch(bld_base, inst, 0, 0));
678 } else if (is_image) {
679 image_fetch_rsrc(bld_base, &resource_reg, true, target, &args.resource);
680 image_fetch_coords(bld_base, inst, 0, args.resource, args.coords);
681 vindex = args.coords[0]; /* for buffers only */
682 } else {
683 unreachable("unexpected register file");
684 }
685
686 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
687 ac_build_waitcnt(&ctx->ac, VM_CNT);
688
689 args.cache_policy = get_cache_policy(ctx, inst,
690 false, /* atomic */
691 is_image, /* may_store_unaligned */
692 writeonly_memory);
693
694 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
695 store_emit_buffer(ctx, args.resource, inst->Dst[0].Register.WriteMask,
696 value, voffset, args.cache_policy, writeonly_memory);
697 return;
698 }
699
700 if (target == TGSI_TEXTURE_BUFFER) {
701 LLVMValueRef buf_args[6] = {
702 value,
703 args.resource,
704 vindex,
705 ctx->i32_0, /* voffset */
706 };
707
708 if (HAVE_LLVM >= 0x0800) {
709 buf_args[4] = ctx->i32_0; /* soffset */
710 buf_args[5] = LLVMConstInt(ctx->i1, args.cache_policy, 0);
711 } else {
712 buf_args[4] = LLVMConstInt(ctx->i1, !!(args.cache_policy & ac_glc), 0);
713 buf_args[5] = LLVMConstInt(ctx->i1, !!(args.cache_policy & ac_slc), 0);
714 }
715
716 emit_data->output[emit_data->chan] = ac_build_intrinsic(
717 &ctx->ac,
718 HAVE_LLVM >= 0x0800 ? "llvm.amdgcn.struct.buffer.store.format.v4f32" :
719 "llvm.amdgcn.buffer.store.format.v4f32",
720 ctx->voidt, buf_args, 6,
721 ac_get_store_intr_attribs(writeonly_memory));
722 } else {
723 args.opcode = ac_image_store;
724 args.data[0] = value;
725 args.dim = ac_image_dim_from_tgsi_target(ctx->screen, inst->Memory.Texture);
726 args.attributes = ac_get_store_intr_attribs(writeonly_memory);
727 args.dmask = 0xf;
728
729 emit_data->output[emit_data->chan] =
730 ac_build_image_opcode(&ctx->ac, &args);
731 }
732 }
733
734 static void atomic_emit_memory(struct si_shader_context *ctx,
735 struct lp_build_emit_data *emit_data) {
736 LLVMBuilderRef builder = ctx->ac.builder;
737 const struct tgsi_full_instruction * inst = emit_data->inst;
738 LLVMValueRef ptr, result, arg;
739
740 ptr = get_memory_ptr(ctx, inst, ctx->i32, 1);
741
742 arg = lp_build_emit_fetch(&ctx->bld_base, inst, 2, 0);
743 arg = ac_to_integer(&ctx->ac, arg);
744
745 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
746 LLVMValueRef new_data;
747 new_data = lp_build_emit_fetch(&ctx->bld_base,
748 inst, 3, 0);
749
750 new_data = ac_to_integer(&ctx->ac, new_data);
751
752 result = LLVMBuildAtomicCmpXchg(builder, ptr, arg, new_data,
753 LLVMAtomicOrderingSequentiallyConsistent,
754 LLVMAtomicOrderingSequentiallyConsistent,
755 false);
756
757 result = LLVMBuildExtractValue(builder, result, 0, "");
758 } else {
759 LLVMAtomicRMWBinOp op;
760
761 switch(inst->Instruction.Opcode) {
762 case TGSI_OPCODE_ATOMUADD:
763 op = LLVMAtomicRMWBinOpAdd;
764 break;
765 case TGSI_OPCODE_ATOMXCHG:
766 op = LLVMAtomicRMWBinOpXchg;
767 break;
768 case TGSI_OPCODE_ATOMAND:
769 op = LLVMAtomicRMWBinOpAnd;
770 break;
771 case TGSI_OPCODE_ATOMOR:
772 op = LLVMAtomicRMWBinOpOr;
773 break;
774 case TGSI_OPCODE_ATOMXOR:
775 op = LLVMAtomicRMWBinOpXor;
776 break;
777 case TGSI_OPCODE_ATOMUMIN:
778 op = LLVMAtomicRMWBinOpUMin;
779 break;
780 case TGSI_OPCODE_ATOMUMAX:
781 op = LLVMAtomicRMWBinOpUMax;
782 break;
783 case TGSI_OPCODE_ATOMIMIN:
784 op = LLVMAtomicRMWBinOpMin;
785 break;
786 case TGSI_OPCODE_ATOMIMAX:
787 op = LLVMAtomicRMWBinOpMax;
788 break;
789 default:
790 unreachable("unknown atomic opcode");
791 }
792
793 result = LLVMBuildAtomicRMW(builder, op, ptr, arg,
794 LLVMAtomicOrderingSequentiallyConsistent,
795 false);
796 }
797 emit_data->output[emit_data->chan] =
798 LLVMBuildBitCast(builder, result, ctx->f32, "");
799 }
800
801 static void atomic_emit(
802 const struct lp_build_tgsi_action *action,
803 struct lp_build_tgsi_context *bld_base,
804 struct lp_build_emit_data *emit_data)
805 {
806 struct si_shader_context *ctx = si_shader_context(bld_base);
807 const struct tgsi_full_instruction * inst = emit_data->inst;
808 struct ac_image_args args = {};
809 unsigned num_data = 0;
810 LLVMValueRef vindex = ctx->i32_0;
811 LLVMValueRef voffset = ctx->i32_0;
812
813 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
814 atomic_emit_memory(ctx, emit_data);
815 return;
816 }
817
818 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
819 /* llvm.amdgcn.image/buffer.atomic.cmpswap reflect the hardware order
820 * of arguments, which is reversed relative to TGSI (and GLSL)
821 */
822 args.data[num_data++] =
823 ac_to_integer(&ctx->ac, lp_build_emit_fetch(bld_base, inst, 3, 0));
824 }
825
826 args.data[num_data++] =
827 ac_to_integer(&ctx->ac, lp_build_emit_fetch(bld_base, inst, 2, 0));
828 args.cache_policy = get_cache_policy(ctx, inst, true, false, false);
829
830 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
831 args.resource = shader_buffer_fetch_rsrc(ctx, &inst->Src[0], false);
832 voffset = ac_to_integer(&ctx->ac, lp_build_emit_fetch(bld_base, inst, 1, 0));
833 } else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE ||
834 tgsi_is_bindless_image_file(inst->Src[0].Register.File)) {
835 image_fetch_rsrc(bld_base, &inst->Src[0], true,
836 inst->Memory.Texture, &args.resource);
837 image_fetch_coords(bld_base, inst, 1, args.resource, args.coords);
838 vindex = args.coords[0]; /* for buffers only */
839 }
840
841 if (HAVE_LLVM >= 0x0800 &&
842 inst->Src[0].Register.File != TGSI_FILE_BUFFER &&
843 inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
844 LLVMValueRef buf_args[7];
845 unsigned num_args = 0;
846
847 buf_args[num_args++] = args.data[0];
848 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
849 buf_args[num_args++] = args.data[1];
850
851 buf_args[num_args++] = args.resource;
852 buf_args[num_args++] = vindex;
853 buf_args[num_args++] = voffset;
854 buf_args[num_args++] = ctx->i32_0; /* soffset */
855 buf_args[num_args++] = LLVMConstInt(ctx->i32, args.cache_policy & ac_slc, 0);
856
857 char intrinsic_name[64];
858 snprintf(intrinsic_name, sizeof(intrinsic_name),
859 "llvm.amdgcn.struct.buffer.atomic.%s", action->intr_name);
860 emit_data->output[emit_data->chan] =
861 ac_to_float(&ctx->ac,
862 ac_build_intrinsic(&ctx->ac, intrinsic_name,
863 ctx->i32, buf_args, num_args, 0));
864 return;
865 }
866
867 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
868 (HAVE_LLVM < 0x0800 &&
869 inst->Memory.Texture == TGSI_TEXTURE_BUFFER)) {
870 LLVMValueRef buf_args[7];
871 unsigned num_args = 0;
872
873 buf_args[num_args++] = args.data[0];
874 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
875 buf_args[num_args++] = args.data[1];
876
877 buf_args[num_args++] = args.resource;
878 buf_args[num_args++] = vindex;
879 buf_args[num_args++] = voffset;
880 buf_args[num_args++] = args.cache_policy & ac_slc ? ctx->i1true : ctx->i1false;
881
882 char intrinsic_name[40];
883 snprintf(intrinsic_name, sizeof(intrinsic_name),
884 "llvm.amdgcn.buffer.atomic.%s", action->intr_name);
885 emit_data->output[emit_data->chan] =
886 ac_to_float(&ctx->ac,
887 ac_build_intrinsic(&ctx->ac, intrinsic_name,
888 ctx->i32, buf_args, num_args, 0));
889 } else {
890 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
891 args.opcode = ac_image_atomic_cmpswap;
892 } else {
893 args.opcode = ac_image_atomic;
894 switch (inst->Instruction.Opcode) {
895 case TGSI_OPCODE_ATOMXCHG: args.atomic = ac_atomic_swap; break;
896 case TGSI_OPCODE_ATOMUADD: args.atomic = ac_atomic_add; break;
897 case TGSI_OPCODE_ATOMAND: args.atomic = ac_atomic_and; break;
898 case TGSI_OPCODE_ATOMOR: args.atomic = ac_atomic_or; break;
899 case TGSI_OPCODE_ATOMXOR: args.atomic = ac_atomic_xor; break;
900 case TGSI_OPCODE_ATOMUMIN: args.atomic = ac_atomic_umin; break;
901 case TGSI_OPCODE_ATOMUMAX: args.atomic = ac_atomic_umax; break;
902 case TGSI_OPCODE_ATOMIMIN: args.atomic = ac_atomic_smin; break;
903 case TGSI_OPCODE_ATOMIMAX: args.atomic = ac_atomic_smax; break;
904 default: unreachable("unhandled image atomic");
905 }
906 }
907
908 args.dim = ac_image_dim_from_tgsi_target(ctx->screen, inst->Memory.Texture);
909 emit_data->output[emit_data->chan] =
910 ac_to_float(&ctx->ac, ac_build_image_opcode(&ctx->ac, &args));
911 }
912 }
913
914 static LLVMValueRef fix_resinfo(struct si_shader_context *ctx,
915 unsigned target, LLVMValueRef out)
916 {
917 LLVMBuilderRef builder = ctx->ac.builder;
918
919 /* 1D textures are allocated and used as 2D on GFX9. */
920 if (ctx->screen->info.chip_class >= GFX9 &&
921 (target == TGSI_TEXTURE_1D_ARRAY ||
922 target == TGSI_TEXTURE_SHADOW1D_ARRAY)) {
923 LLVMValueRef layers =
924 LLVMBuildExtractElement(builder, out,
925 LLVMConstInt(ctx->i32, 2, 0), "");
926 out = LLVMBuildInsertElement(builder, out, layers,
927 ctx->i32_1, "");
928 }
929
930 /* Divide the number of layers by 6 to get the number of cubes. */
931 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
932 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
933 LLVMValueRef imm2 = LLVMConstInt(ctx->i32, 2, 0);
934
935 LLVMValueRef z = LLVMBuildExtractElement(builder, out, imm2, "");
936 z = LLVMBuildSDiv(builder, z, LLVMConstInt(ctx->i32, 6, 0), "");
937
938 out = LLVMBuildInsertElement(builder, out, z, imm2, "");
939 }
940 return out;
941 }
942
943 static void resq_emit(
944 const struct lp_build_tgsi_action *action,
945 struct lp_build_tgsi_context *bld_base,
946 struct lp_build_emit_data *emit_data)
947 {
948 struct si_shader_context *ctx = si_shader_context(bld_base);
949 LLVMBuilderRef builder = ctx->ac.builder;
950 const struct tgsi_full_instruction *inst = emit_data->inst;
951 const struct tgsi_full_src_register *reg =
952 &inst->Src[inst->Instruction.Opcode == TGSI_OPCODE_TXQ ? 1 : 0];
953
954 if (reg->Register.File == TGSI_FILE_BUFFER) {
955 LLVMValueRef rsrc = shader_buffer_fetch_rsrc(ctx, reg, false);
956
957 emit_data->output[emit_data->chan] =
958 LLVMBuildExtractElement(builder, rsrc,
959 LLVMConstInt(ctx->i32, 2, 0), "");
960 return;
961 }
962
963 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ &&
964 inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
965 LLVMValueRef rsrc;
966
967 tex_fetch_ptrs(bld_base, emit_data, &rsrc, NULL, NULL);
968 /* Read the size from the buffer descriptor directly. */
969 emit_data->output[emit_data->chan] =
970 get_buffer_size(bld_base, rsrc);
971 return;
972 }
973
974 if (inst->Instruction.Opcode == TGSI_OPCODE_RESQ &&
975 inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
976 LLVMValueRef rsrc;
977
978 image_fetch_rsrc(bld_base, reg, false, inst->Memory.Texture, &rsrc);
979 emit_data->output[emit_data->chan] =
980 get_buffer_size(bld_base, rsrc);
981 return;
982 }
983
984 unsigned target;
985
986 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ) {
987 target = inst->Texture.Texture;
988 } else {
989 if (inst->Memory.Texture == TGSI_TEXTURE_3D)
990 target = TGSI_TEXTURE_2D_ARRAY;
991 else
992 target = inst->Memory.Texture;
993 }
994
995 struct ac_image_args args = {};
996 args.opcode = ac_image_get_resinfo;
997 args.dim = ac_texture_dim_from_tgsi_target(ctx->screen, target);
998 args.dmask = 0xf;
999
1000 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ) {
1001 tex_fetch_ptrs(bld_base, emit_data, &args.resource, NULL, NULL);
1002 args.lod = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
1003 } else {
1004 image_fetch_rsrc(bld_base, reg, false, target, &args.resource);
1005 args.lod = ctx->i32_0;
1006 }
1007
1008 emit_data->output[emit_data->chan] =
1009 fix_resinfo(ctx, target, ac_build_image_opcode(&ctx->ac, &args));
1010 }
1011
1012 /**
1013 * Load an image view, fmask view. or sampler state descriptor.
1014 */
1015 LLVMValueRef si_load_sampler_desc(struct si_shader_context *ctx,
1016 LLVMValueRef list, LLVMValueRef index,
1017 enum ac_descriptor_type type)
1018 {
1019 LLVMBuilderRef builder = ctx->ac.builder;
1020
1021 switch (type) {
1022 case AC_DESC_IMAGE:
1023 /* The image is at [0:7]. */
1024 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
1025 break;
1026 case AC_DESC_BUFFER:
1027 /* The buffer is in [4:7]. */
1028 index = ac_build_imad(&ctx->ac, index, LLVMConstInt(ctx->i32, 4, 0),
1029 ctx->i32_1);
1030 list = LLVMBuildPointerCast(builder, list,
1031 ac_array_in_const32_addr_space(ctx->v4i32), "");
1032 break;
1033 case AC_DESC_FMASK:
1034 /* The FMASK is at [8:15]. */
1035 index = ac_build_imad(&ctx->ac, index, LLVMConstInt(ctx->i32, 2, 0),
1036 ctx->i32_1);
1037 break;
1038 case AC_DESC_SAMPLER:
1039 /* The sampler state is at [12:15]. */
1040 index = ac_build_imad(&ctx->ac, index, LLVMConstInt(ctx->i32, 4, 0),
1041 LLVMConstInt(ctx->i32, 3, 0));
1042 list = LLVMBuildPointerCast(builder, list,
1043 ac_array_in_const32_addr_space(ctx->v4i32), "");
1044 break;
1045 }
1046
1047 return ac_build_load_to_sgpr(&ctx->ac, list, index);
1048 }
1049
1050 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
1051 *
1052 * SI-CI:
1053 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
1054 * filtering manually. The driver sets img7 to a mask clearing
1055 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
1056 * s_and_b32 samp0, samp0, img7
1057 *
1058 * VI:
1059 * The ANISO_OVERRIDE sampler field enables this fix in TA.
1060 */
1061 static LLVMValueRef sici_fix_sampler_aniso(struct si_shader_context *ctx,
1062 LLVMValueRef res, LLVMValueRef samp)
1063 {
1064 LLVMValueRef img7, samp0;
1065
1066 if (ctx->screen->info.chip_class >= VI)
1067 return samp;
1068
1069 img7 = LLVMBuildExtractElement(ctx->ac.builder, res,
1070 LLVMConstInt(ctx->i32, 7, 0), "");
1071 samp0 = LLVMBuildExtractElement(ctx->ac.builder, samp,
1072 ctx->i32_0, "");
1073 samp0 = LLVMBuildAnd(ctx->ac.builder, samp0, img7, "");
1074 return LLVMBuildInsertElement(ctx->ac.builder, samp, samp0,
1075 ctx->i32_0, "");
1076 }
1077
1078 static void tex_fetch_ptrs(struct lp_build_tgsi_context *bld_base,
1079 struct lp_build_emit_data *emit_data,
1080 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
1081 LLVMValueRef *fmask_ptr)
1082 {
1083 struct si_shader_context *ctx = si_shader_context(bld_base);
1084 LLVMValueRef list = LLVMGetParam(ctx->main_fn, ctx->param_samplers_and_images);
1085 const struct tgsi_full_instruction *inst = emit_data->inst;
1086 const struct tgsi_full_src_register *reg;
1087 unsigned target = inst->Texture.Texture;
1088 unsigned sampler_src;
1089 LLVMValueRef index;
1090
1091 sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
1092 reg = &emit_data->inst->Src[sampler_src];
1093
1094 if (reg->Register.Indirect) {
1095 index = si_get_bounded_indirect_index(ctx,
1096 &reg->Indirect,
1097 reg->Register.Index,
1098 ctx->num_samplers);
1099 index = LLVMBuildAdd(ctx->ac.builder, index,
1100 LLVMConstInt(ctx->i32, SI_NUM_IMAGES / 2, 0), "");
1101 } else {
1102 index = LLVMConstInt(ctx->i32,
1103 si_get_sampler_slot(reg->Register.Index), 0);
1104 }
1105
1106 if (reg->Register.File != TGSI_FILE_SAMPLER) {
1107 /* Bindless descriptors are accessible from a different pair of
1108 * user SGPR indices.
1109 */
1110 list = LLVMGetParam(ctx->main_fn,
1111 ctx->param_bindless_samplers_and_images);
1112 index = lp_build_emit_fetch_src(bld_base, reg,
1113 TGSI_TYPE_UNSIGNED, 0);
1114
1115 /* Since bindless handle arithmetic can contain an unsigned integer
1116 * wraparound and si_load_sampler_desc assumes there isn't any,
1117 * use GEP without "inbounds" (inside ac_build_pointer_add)
1118 * to prevent incorrect code generation and hangs.
1119 */
1120 index = LLVMBuildMul(ctx->ac.builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
1121 list = ac_build_pointer_add(&ctx->ac, list, index);
1122 index = ctx->i32_0;
1123 }
1124
1125 if (target == TGSI_TEXTURE_BUFFER)
1126 *res_ptr = si_load_sampler_desc(ctx, list, index, AC_DESC_BUFFER);
1127 else
1128 *res_ptr = si_load_sampler_desc(ctx, list, index, AC_DESC_IMAGE);
1129
1130 if (samp_ptr)
1131 *samp_ptr = NULL;
1132 if (fmask_ptr)
1133 *fmask_ptr = NULL;
1134
1135 if (target == TGSI_TEXTURE_2D_MSAA ||
1136 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
1137 if (fmask_ptr)
1138 *fmask_ptr = si_load_sampler_desc(ctx, list, index,
1139 AC_DESC_FMASK);
1140 } else if (target != TGSI_TEXTURE_BUFFER) {
1141 if (samp_ptr) {
1142 *samp_ptr = si_load_sampler_desc(ctx, list, index,
1143 AC_DESC_SAMPLER);
1144 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
1145 }
1146 }
1147 }
1148
1149 /* Gather4 should follow the same rules as bilinear filtering, but the hardware
1150 * incorrectly forces nearest filtering if the texture format is integer.
1151 * The only effect it has on Gather4, which always returns 4 texels for
1152 * bilinear filtering, is that the final coordinates are off by 0.5 of
1153 * the texel size.
1154 *
1155 * The workaround is to subtract 0.5 from the unnormalized coordinates,
1156 * or (0.5 / size) from the normalized coordinates.
1157 *
1158 * However, cube textures with 8_8_8_8 data formats require a different
1159 * workaround of overriding the num format to USCALED/SSCALED. This would lose
1160 * precision in 32-bit data formats, so it needs to be applied dynamically at
1161 * runtime. In this case, return an i1 value that indicates whether the
1162 * descriptor was overridden (and hence a fixup of the sampler result is needed).
1163 */
1164 static LLVMValueRef
1165 si_lower_gather4_integer(struct si_shader_context *ctx,
1166 struct ac_image_args *args,
1167 unsigned target,
1168 enum tgsi_return_type return_type)
1169 {
1170 LLVMBuilderRef builder = ctx->ac.builder;
1171 LLVMValueRef wa_8888 = NULL;
1172 LLVMValueRef half_texel[2];
1173
1174 assert(return_type == TGSI_RETURN_TYPE_SINT ||
1175 return_type == TGSI_RETURN_TYPE_UINT);
1176
1177 if (target == TGSI_TEXTURE_CUBE ||
1178 target == TGSI_TEXTURE_CUBE_ARRAY) {
1179 LLVMValueRef formats;
1180 LLVMValueRef data_format;
1181 LLVMValueRef wa_formats;
1182
1183 formats = LLVMBuildExtractElement(builder, args->resource, ctx->i32_1, "");
1184
1185 data_format = LLVMBuildLShr(builder, formats,
1186 LLVMConstInt(ctx->i32, 20, false), "");
1187 data_format = LLVMBuildAnd(builder, data_format,
1188 LLVMConstInt(ctx->i32, (1u << 6) - 1, false), "");
1189 wa_8888 = LLVMBuildICmp(
1190 builder, LLVMIntEQ, data_format,
1191 LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false),
1192 "");
1193
1194 uint32_t wa_num_format =
1195 return_type == TGSI_RETURN_TYPE_UINT ?
1196 S_008F14_NUM_FORMAT_GFX6(V_008F14_IMG_NUM_FORMAT_USCALED) :
1197 S_008F14_NUM_FORMAT_GFX6(V_008F14_IMG_NUM_FORMAT_SSCALED);
1198 wa_formats = LLVMBuildAnd(builder, formats,
1199 LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false),
1200 "");
1201 wa_formats = LLVMBuildOr(builder, wa_formats,
1202 LLVMConstInt(ctx->i32, wa_num_format, false), "");
1203
1204 formats = LLVMBuildSelect(builder, wa_8888, wa_formats, formats, "");
1205 args->resource = LLVMBuildInsertElement(
1206 builder, args->resource, formats, ctx->i32_1, "");
1207 }
1208
1209 if (target == TGSI_TEXTURE_RECT ||
1210 target == TGSI_TEXTURE_SHADOWRECT) {
1211 assert(!wa_8888);
1212 half_texel[0] = half_texel[1] = LLVMConstReal(ctx->f32, -0.5);
1213 } else {
1214 struct ac_image_args resinfo = {};
1215 struct lp_build_if_state if_ctx;
1216
1217 if (wa_8888) {
1218 /* Skip the texture size query entirely if we don't need it. */
1219 lp_build_if(&if_ctx, &ctx->gallivm, LLVMBuildNot(builder, wa_8888, ""));
1220 }
1221
1222 /* Query the texture size. */
1223 resinfo.opcode = ac_image_get_resinfo;
1224 resinfo.dim = ac_texture_dim_from_tgsi_target(ctx->screen, target);
1225 resinfo.resource = args->resource;
1226 resinfo.sampler = args->sampler;
1227 resinfo.lod = ctx->ac.i32_0;
1228 resinfo.dmask = 0xf;
1229
1230 LLVMValueRef texsize =
1231 fix_resinfo(ctx, target,
1232 ac_build_image_opcode(&ctx->ac, &resinfo));
1233
1234 /* Compute -0.5 / size. */
1235 for (unsigned c = 0; c < 2; c++) {
1236 half_texel[c] =
1237 LLVMBuildExtractElement(builder, texsize,
1238 LLVMConstInt(ctx->i32, c, 0), "");
1239 half_texel[c] = LLVMBuildUIToFP(builder, half_texel[c], ctx->f32, "");
1240 half_texel[c] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, half_texel[c]);
1241 half_texel[c] = LLVMBuildFMul(builder, half_texel[c],
1242 LLVMConstReal(ctx->f32, -0.5), "");
1243 }
1244
1245 if (wa_8888) {
1246 lp_build_endif(&if_ctx);
1247
1248 LLVMBasicBlockRef bb[2] = { if_ctx.true_block, if_ctx.entry_block };
1249
1250 for (unsigned c = 0; c < 2; c++) {
1251 LLVMValueRef values[2] = { half_texel[c], ctx->ac.f32_0 };
1252 half_texel[c] = ac_build_phi(&ctx->ac, ctx->f32, 2,
1253 values, bb);
1254 }
1255 }
1256 }
1257
1258 for (unsigned c = 0; c < 2; c++) {
1259 LLVMValueRef tmp;
1260 tmp = ac_to_float(&ctx->ac, args->coords[c]);
1261 tmp = LLVMBuildFAdd(builder, tmp, half_texel[c], "");
1262 args->coords[c] = ac_to_integer(&ctx->ac, tmp);
1263 }
1264
1265 return wa_8888;
1266 }
1267
1268 /* The second half of the cube texture 8_8_8_8 integer workaround: adjust the
1269 * result after the gather operation.
1270 */
1271 static LLVMValueRef
1272 si_fix_gather4_integer_result(struct si_shader_context *ctx,
1273 LLVMValueRef result,
1274 enum tgsi_return_type return_type,
1275 LLVMValueRef wa)
1276 {
1277 LLVMBuilderRef builder = ctx->ac.builder;
1278
1279 assert(return_type == TGSI_RETURN_TYPE_SINT ||
1280 return_type == TGSI_RETURN_TYPE_UINT);
1281
1282 for (unsigned chan = 0; chan < 4; ++chan) {
1283 LLVMValueRef chanv = LLVMConstInt(ctx->i32, chan, false);
1284 LLVMValueRef value;
1285 LLVMValueRef wa_value;
1286
1287 value = LLVMBuildExtractElement(builder, result, chanv, "");
1288
1289 if (return_type == TGSI_RETURN_TYPE_UINT)
1290 wa_value = LLVMBuildFPToUI(builder, value, ctx->i32, "");
1291 else
1292 wa_value = LLVMBuildFPToSI(builder, value, ctx->i32, "");
1293 wa_value = ac_to_float(&ctx->ac, wa_value);
1294 value = LLVMBuildSelect(builder, wa, wa_value, value, "");
1295
1296 result = LLVMBuildInsertElement(builder, result, value, chanv, "");
1297 }
1298
1299 return result;
1300 }
1301
1302 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
1303 struct lp_build_tgsi_context *bld_base,
1304 struct lp_build_emit_data *emit_data)
1305 {
1306 struct si_shader_context *ctx = si_shader_context(bld_base);
1307 const struct tgsi_full_instruction *inst = emit_data->inst;
1308 unsigned opcode = inst->Instruction.Opcode;
1309 unsigned target = inst->Texture.Texture;
1310 struct ac_image_args args = {};
1311 int ref_pos = tgsi_util_get_shadow_ref_src_index(target);
1312 unsigned chan;
1313 bool has_offset = inst->Texture.NumOffsets > 0;
1314 LLVMValueRef fmask_ptr = NULL;
1315
1316 tex_fetch_ptrs(bld_base, emit_data, &args.resource, &args.sampler, &fmask_ptr);
1317
1318 if (target == TGSI_TEXTURE_BUFFER) {
1319 LLVMValueRef vindex = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
1320 unsigned num_channels =
1321 util_last_bit(inst->Dst[0].Register.WriteMask);
1322 LLVMValueRef result =
1323 ac_build_buffer_load_format(&ctx->ac,
1324 args.resource,
1325 vindex,
1326 ctx->i32_0,
1327 num_channels, false, true);
1328 emit_data->output[emit_data->chan] =
1329 ac_build_expand_to_vec4(&ctx->ac, result, num_channels);
1330 return;
1331 }
1332
1333 /* Fetch and project texture coordinates */
1334 args.coords[3] = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_W);
1335 for (chan = 0; chan < 3; chan++) {
1336 args.coords[chan] = lp_build_emit_fetch(bld_base, inst, 0, chan);
1337 if (opcode == TGSI_OPCODE_TXP)
1338 args.coords[chan] = ac_build_fdiv(&ctx->ac,
1339 args.coords[chan], args.coords[3]);
1340 }
1341
1342 if (opcode == TGSI_OPCODE_TXP)
1343 args.coords[3] = ctx->ac.f32_1;
1344
1345 /* Pack offsets. */
1346 if (has_offset &&
1347 opcode != TGSI_OPCODE_TXF &&
1348 opcode != TGSI_OPCODE_TXF_LZ) {
1349 /* The offsets are six-bit signed integers packed like this:
1350 * X=[5:0], Y=[13:8], and Z=[21:16].
1351 */
1352 LLVMValueRef offset[3], pack;
1353
1354 assert(inst->Texture.NumOffsets == 1);
1355
1356 for (chan = 0; chan < 3; chan++) {
1357 offset[chan] = lp_build_emit_fetch_texoffset(bld_base, inst, 0, chan);
1358 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
1359 LLVMConstInt(ctx->i32, 0x3f, 0), "");
1360 if (chan)
1361 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
1362 LLVMConstInt(ctx->i32, chan*8, 0), "");
1363 }
1364
1365 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
1366 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
1367 args.offset = pack;
1368 }
1369
1370 /* Pack LOD bias value */
1371 if (opcode == TGSI_OPCODE_TXB)
1372 args.bias = args.coords[3];
1373 if (opcode == TGSI_OPCODE_TXB2)
1374 args.bias = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
1375
1376 /* Pack depth comparison value */
1377 if (tgsi_is_shadow_target(target) && opcode != TGSI_OPCODE_LODQ) {
1378 LLVMValueRef z;
1379
1380 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
1381 z = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
1382 } else {
1383 assert(ref_pos >= 0);
1384 z = args.coords[ref_pos];
1385 }
1386
1387 /* Section 8.23.1 (Depth Texture Comparison Mode) of the
1388 * OpenGL 4.5 spec says:
1389 *
1390 * "If the texture’s internal format indicates a fixed-point
1391 * depth texture, then D_t and D_ref are clamped to the
1392 * range [0, 1]; otherwise no clamping is performed."
1393 *
1394 * TC-compatible HTILE promotes Z16 and Z24 to Z32_FLOAT,
1395 * so the depth comparison value isn't clamped for Z16 and
1396 * Z24 anymore. Do it manually here.
1397 */
1398 if (ctx->screen->info.chip_class >= VI) {
1399 LLVMValueRef upgraded;
1400 LLVMValueRef clamped;
1401 upgraded = LLVMBuildExtractElement(ctx->ac.builder, args.sampler,
1402 LLVMConstInt(ctx->i32, 3, false), "");
1403 upgraded = LLVMBuildLShr(ctx->ac.builder, upgraded,
1404 LLVMConstInt(ctx->i32, 29, false), "");
1405 upgraded = LLVMBuildTrunc(ctx->ac.builder, upgraded, ctx->i1, "");
1406 clamped = ac_build_clamp(&ctx->ac, z);
1407 z = LLVMBuildSelect(ctx->ac.builder, upgraded, clamped, z, "");
1408 }
1409
1410 args.compare = z;
1411 }
1412
1413 /* Pack user derivatives */
1414 if (opcode == TGSI_OPCODE_TXD) {
1415 int param, num_src_deriv_channels, num_dst_deriv_channels;
1416
1417 switch (target) {
1418 case TGSI_TEXTURE_3D:
1419 num_src_deriv_channels = 3;
1420 num_dst_deriv_channels = 3;
1421 break;
1422 case TGSI_TEXTURE_2D:
1423 case TGSI_TEXTURE_SHADOW2D:
1424 case TGSI_TEXTURE_RECT:
1425 case TGSI_TEXTURE_SHADOWRECT:
1426 case TGSI_TEXTURE_2D_ARRAY:
1427 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1428 num_src_deriv_channels = 2;
1429 num_dst_deriv_channels = 2;
1430 break;
1431 case TGSI_TEXTURE_CUBE:
1432 case TGSI_TEXTURE_SHADOWCUBE:
1433 case TGSI_TEXTURE_CUBE_ARRAY:
1434 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
1435 /* Cube derivatives will be converted to 2D. */
1436 num_src_deriv_channels = 3;
1437 num_dst_deriv_channels = 3;
1438 break;
1439 case TGSI_TEXTURE_1D:
1440 case TGSI_TEXTURE_SHADOW1D:
1441 case TGSI_TEXTURE_1D_ARRAY:
1442 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1443 num_src_deriv_channels = 1;
1444
1445 /* 1D textures are allocated and used as 2D on GFX9. */
1446 if (ctx->screen->info.chip_class >= GFX9) {
1447 num_dst_deriv_channels = 2;
1448 } else {
1449 num_dst_deriv_channels = 1;
1450 }
1451 break;
1452 default:
1453 unreachable("invalid target");
1454 }
1455
1456 for (param = 0; param < 2; param++) {
1457 for (chan = 0; chan < num_src_deriv_channels; chan++)
1458 args.derivs[param * num_dst_deriv_channels + chan] =
1459 lp_build_emit_fetch(bld_base, inst, param+1, chan);
1460
1461 /* Fill in the rest with zeros. */
1462 for (chan = num_src_deriv_channels;
1463 chan < num_dst_deriv_channels; chan++)
1464 args.derivs[param * num_dst_deriv_channels + chan] =
1465 ctx->ac.f32_0;
1466 }
1467 }
1468
1469 if (target == TGSI_TEXTURE_CUBE ||
1470 target == TGSI_TEXTURE_CUBE_ARRAY ||
1471 target == TGSI_TEXTURE_SHADOWCUBE ||
1472 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
1473 ac_prepare_cube_coords(&ctx->ac,
1474 opcode == TGSI_OPCODE_TXD,
1475 target == TGSI_TEXTURE_CUBE_ARRAY ||
1476 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY,
1477 opcode == TGSI_OPCODE_LODQ,
1478 args.coords, args.derivs);
1479 } else if (tgsi_is_array_sampler(target) &&
1480 opcode != TGSI_OPCODE_TXF &&
1481 opcode != TGSI_OPCODE_TXF_LZ &&
1482 ctx->screen->info.chip_class <= VI) {
1483 unsigned array_coord = target == TGSI_TEXTURE_1D_ARRAY ? 1 : 2;
1484 args.coords[array_coord] = ac_build_round(&ctx->ac, args.coords[array_coord]);
1485 }
1486
1487 /* 1D textures are allocated and used as 2D on GFX9. */
1488 if (ctx->screen->info.chip_class >= GFX9) {
1489 LLVMValueRef filler;
1490
1491 /* Use 0.5, so that we don't sample the border color. */
1492 if (opcode == TGSI_OPCODE_TXF ||
1493 opcode == TGSI_OPCODE_TXF_LZ)
1494 filler = ctx->i32_0;
1495 else
1496 filler = LLVMConstReal(ctx->f32, 0.5);
1497
1498 if (target == TGSI_TEXTURE_1D ||
1499 target == TGSI_TEXTURE_SHADOW1D) {
1500 args.coords[1] = filler;
1501 } else if (target == TGSI_TEXTURE_1D_ARRAY ||
1502 target == TGSI_TEXTURE_SHADOW1D_ARRAY) {
1503 args.coords[2] = args.coords[1];
1504 args.coords[1] = filler;
1505 }
1506 }
1507
1508 /* Pack LOD or sample index */
1509 if (opcode == TGSI_OPCODE_TXL)
1510 args.lod = args.coords[3];
1511 else if (opcode == TGSI_OPCODE_TXL2)
1512 args.lod = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
1513 else if (opcode == TGSI_OPCODE_TXF) {
1514 if (target == TGSI_TEXTURE_2D_MSAA) {
1515 /* No LOD, but move sample index into the right place. */
1516 args.coords[2] = args.coords[3];
1517 } else if (target != TGSI_TEXTURE_2D_ARRAY_MSAA) {
1518 args.lod = args.coords[3];
1519 }
1520 }
1521
1522 if (target == TGSI_TEXTURE_2D_MSAA ||
1523 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
1524 ac_apply_fmask_to_sample(&ctx->ac, fmask_ptr, args.coords,
1525 target == TGSI_TEXTURE_2D_ARRAY_MSAA);
1526 }
1527
1528 if (opcode == TGSI_OPCODE_TXF ||
1529 opcode == TGSI_OPCODE_TXF_LZ) {
1530 /* add tex offsets */
1531 if (inst->Texture.NumOffsets) {
1532 const struct tgsi_texture_offset *off = inst->TexOffsets;
1533
1534 assert(inst->Texture.NumOffsets == 1);
1535
1536 switch (target) {
1537 case TGSI_TEXTURE_3D:
1538 args.coords[2] =
1539 LLVMBuildAdd(ctx->ac.builder, args.coords[2],
1540 ctx->imms[off->Index * TGSI_NUM_CHANNELS + off->SwizzleZ], "");
1541 /* fall through */
1542 case TGSI_TEXTURE_2D:
1543 case TGSI_TEXTURE_SHADOW2D:
1544 case TGSI_TEXTURE_RECT:
1545 case TGSI_TEXTURE_SHADOWRECT:
1546 case TGSI_TEXTURE_2D_ARRAY:
1547 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1548 args.coords[1] =
1549 LLVMBuildAdd(ctx->ac.builder, args.coords[1],
1550 ctx->imms[off->Index * TGSI_NUM_CHANNELS + off->SwizzleY], "");
1551 /* fall through */
1552 case TGSI_TEXTURE_1D:
1553 case TGSI_TEXTURE_SHADOW1D:
1554 case TGSI_TEXTURE_1D_ARRAY:
1555 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1556 args.coords[0] =
1557 LLVMBuildAdd(ctx->ac.builder, args.coords[0],
1558 ctx->imms[off->Index * TGSI_NUM_CHANNELS + off->SwizzleX], "");
1559 break;
1560 /* texture offsets do not apply to other texture targets */
1561 }
1562 }
1563 }
1564
1565 if (opcode == TGSI_OPCODE_TG4) {
1566 unsigned gather_comp = 0;
1567
1568 /* DMASK was repurposed for GATHER4. 4 components are always
1569 * returned and DMASK works like a swizzle - it selects
1570 * the component to fetch. The only valid DMASK values are
1571 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
1572 * (red,red,red,red) etc.) The ISA document doesn't mention
1573 * this.
1574 */
1575
1576 /* Get the component index from src1.x for Gather4. */
1577 if (!tgsi_is_shadow_target(target)) {
1578 LLVMValueRef comp_imm;
1579 struct tgsi_src_register src1 = inst->Src[1].Register;
1580
1581 assert(src1.File == TGSI_FILE_IMMEDIATE);
1582
1583 comp_imm = ctx->imms[src1.Index * TGSI_NUM_CHANNELS + src1.SwizzleX];
1584 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
1585 gather_comp = CLAMP(gather_comp, 0, 3);
1586 }
1587
1588 args.dmask = 1 << gather_comp;
1589 } else {
1590 args.dmask = 0xf;
1591 }
1592
1593 args.dim = ac_texture_dim_from_tgsi_target(ctx->screen, target);
1594 args.unorm = target == TGSI_TEXTURE_RECT ||
1595 target == TGSI_TEXTURE_SHADOWRECT;
1596 args.opcode = ac_image_sample;
1597
1598 switch (opcode) {
1599 case TGSI_OPCODE_TXF:
1600 case TGSI_OPCODE_TXF_LZ:
1601 args.opcode = opcode == TGSI_OPCODE_TXF_LZ ||
1602 target == TGSI_TEXTURE_2D_MSAA ||
1603 target == TGSI_TEXTURE_2D_ARRAY_MSAA ?
1604 ac_image_load : ac_image_load_mip;
1605 break;
1606 case TGSI_OPCODE_LODQ:
1607 args.opcode = ac_image_get_lod;
1608 break;
1609 case TGSI_OPCODE_TEX:
1610 case TGSI_OPCODE_TEX2:
1611 case TGSI_OPCODE_TXP:
1612 if (ctx->type != PIPE_SHADER_FRAGMENT)
1613 args.level_zero = true;
1614 break;
1615 case TGSI_OPCODE_TEX_LZ:
1616 args.level_zero = true;
1617 break;
1618 case TGSI_OPCODE_TXB:
1619 case TGSI_OPCODE_TXB2:
1620 assert(ctx->type == PIPE_SHADER_FRAGMENT);
1621 break;
1622 case TGSI_OPCODE_TXL:
1623 case TGSI_OPCODE_TXL2:
1624 break;
1625 case TGSI_OPCODE_TXD:
1626 break;
1627 case TGSI_OPCODE_TG4:
1628 args.opcode = ac_image_gather4;
1629 args.level_zero = true;
1630 break;
1631 default:
1632 assert(0);
1633 return;
1634 }
1635
1636 /* The hardware needs special lowering for Gather4 with integer formats. */
1637 LLVMValueRef gather4_int_result_workaround = NULL;
1638
1639 if (ctx->screen->info.chip_class <= VI &&
1640 opcode == TGSI_OPCODE_TG4) {
1641 assert(inst->Texture.ReturnType != TGSI_RETURN_TYPE_UNKNOWN);
1642
1643 if (inst->Texture.ReturnType == TGSI_RETURN_TYPE_SINT ||
1644 inst->Texture.ReturnType == TGSI_RETURN_TYPE_UINT) {
1645 gather4_int_result_workaround =
1646 si_lower_gather4_integer(ctx, &args, target,
1647 inst->Texture.ReturnType);
1648 }
1649 }
1650
1651 args.attributes = AC_FUNC_ATTR_READNONE;
1652 LLVMValueRef result = ac_build_image_opcode(&ctx->ac, &args);
1653
1654 if (gather4_int_result_workaround) {
1655 result = si_fix_gather4_integer_result(ctx, result,
1656 inst->Texture.ReturnType,
1657 gather4_int_result_workaround);
1658 }
1659
1660 emit_data->output[emit_data->chan] = result;
1661 }
1662
1663 static void si_llvm_emit_txqs(
1664 const struct lp_build_tgsi_action *action,
1665 struct lp_build_tgsi_context *bld_base,
1666 struct lp_build_emit_data *emit_data)
1667 {
1668 struct si_shader_context *ctx = si_shader_context(bld_base);
1669 LLVMValueRef res, samples;
1670 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
1671
1672 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
1673
1674 /* Read the samples from the descriptor directly. */
1675 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->v8i32, "");
1676 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
1677 LLVMConstInt(ctx->i32, 3, 0), "");
1678 samples = LLVMBuildLShr(ctx->ac.builder, samples,
1679 LLVMConstInt(ctx->i32, 16, 0), "");
1680 samples = LLVMBuildAnd(ctx->ac.builder, samples,
1681 LLVMConstInt(ctx->i32, 0xf, 0), "");
1682 samples = LLVMBuildShl(ctx->ac.builder, ctx->i32_1,
1683 samples, "");
1684
1685 emit_data->output[emit_data->chan] = samples;
1686 }
1687
1688 static void si_llvm_emit_fbfetch(const struct lp_build_tgsi_action *action,
1689 struct lp_build_tgsi_context *bld_base,
1690 struct lp_build_emit_data *emit_data)
1691 {
1692 struct si_shader_context *ctx = si_shader_context(bld_base);
1693 struct ac_image_args args = {};
1694 LLVMValueRef ptr, image, fmask;
1695
1696 /* Ignore src0, because KHR_blend_func_extended disallows multiple render
1697 * targets.
1698 */
1699
1700 /* Load the image descriptor. */
1701 STATIC_ASSERT(SI_PS_IMAGE_COLORBUF0 % 2 == 0);
1702 ptr = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
1703 ptr = LLVMBuildPointerCast(ctx->ac.builder, ptr,
1704 ac_array_in_const32_addr_space(ctx->v8i32), "");
1705 image = ac_build_load_to_sgpr(&ctx->ac, ptr,
1706 LLVMConstInt(ctx->i32, SI_PS_IMAGE_COLORBUF0 / 2, 0));
1707
1708 unsigned chan = 0;
1709
1710 args.coords[chan++] = si_unpack_param(ctx, SI_PARAM_POS_FIXED_PT, 0, 16);
1711
1712 if (!ctx->shader->key.mono.u.ps.fbfetch_is_1D)
1713 args.coords[chan++] = si_unpack_param(ctx, SI_PARAM_POS_FIXED_PT, 16, 16);
1714
1715 /* Get the current render target layer index. */
1716 if (ctx->shader->key.mono.u.ps.fbfetch_layered)
1717 args.coords[chan++] = si_unpack_param(ctx, SI_PARAM_ANCILLARY, 16, 11);
1718
1719 if (ctx->shader->key.mono.u.ps.fbfetch_msaa)
1720 args.coords[chan++] = si_get_sample_id(ctx);
1721
1722 if (ctx->shader->key.mono.u.ps.fbfetch_msaa) {
1723 fmask = ac_build_load_to_sgpr(&ctx->ac, ptr,
1724 LLVMConstInt(ctx->i32, SI_PS_IMAGE_COLORBUF0_FMASK / 2, 0));
1725
1726 ac_apply_fmask_to_sample(&ctx->ac, fmask, args.coords,
1727 ctx->shader->key.mono.u.ps.fbfetch_layered);
1728 }
1729
1730 args.opcode = ac_image_load;
1731 args.resource = image;
1732 args.dmask = 0xf;
1733 if (ctx->shader->key.mono.u.ps.fbfetch_msaa)
1734 args.dim = ctx->shader->key.mono.u.ps.fbfetch_layered ?
1735 ac_image_2darraymsaa : ac_image_2dmsaa;
1736 else if (ctx->shader->key.mono.u.ps.fbfetch_is_1D)
1737 args.dim = ctx->shader->key.mono.u.ps.fbfetch_layered ?
1738 ac_image_1darray : ac_image_1d;
1739 else
1740 args.dim = ctx->shader->key.mono.u.ps.fbfetch_layered ?
1741 ac_image_2darray : ac_image_2d;
1742
1743 emit_data->output[emit_data->chan] =
1744 ac_build_image_opcode(&ctx->ac, &args);
1745 }
1746
1747 /**
1748 * Setup actions for TGSI memory opcode, including texture opcodes.
1749 */
1750 void si_shader_context_init_mem(struct si_shader_context *ctx)
1751 {
1752 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
1753
1754 bld_base->op_actions[TGSI_OPCODE_TEX].emit = build_tex_intrinsic;
1755 bld_base->op_actions[TGSI_OPCODE_TEX_LZ].emit = build_tex_intrinsic;
1756 bld_base->op_actions[TGSI_OPCODE_TEX2].emit = build_tex_intrinsic;
1757 bld_base->op_actions[TGSI_OPCODE_TXB].emit = build_tex_intrinsic;
1758 bld_base->op_actions[TGSI_OPCODE_TXB2].emit = build_tex_intrinsic;
1759 bld_base->op_actions[TGSI_OPCODE_TXD].emit = build_tex_intrinsic;
1760 bld_base->op_actions[TGSI_OPCODE_TXF].emit = build_tex_intrinsic;
1761 bld_base->op_actions[TGSI_OPCODE_TXF_LZ].emit = build_tex_intrinsic;
1762 bld_base->op_actions[TGSI_OPCODE_TXL].emit = build_tex_intrinsic;
1763 bld_base->op_actions[TGSI_OPCODE_TXL2].emit = build_tex_intrinsic;
1764 bld_base->op_actions[TGSI_OPCODE_TXP].emit = build_tex_intrinsic;
1765 bld_base->op_actions[TGSI_OPCODE_TXQ].emit = resq_emit;
1766 bld_base->op_actions[TGSI_OPCODE_TG4].emit = build_tex_intrinsic;
1767 bld_base->op_actions[TGSI_OPCODE_LODQ].emit = build_tex_intrinsic;
1768 bld_base->op_actions[TGSI_OPCODE_TXQS].emit = si_llvm_emit_txqs;
1769
1770 bld_base->op_actions[TGSI_OPCODE_FBFETCH].emit = si_llvm_emit_fbfetch;
1771
1772 bld_base->op_actions[TGSI_OPCODE_LOAD].emit = load_emit;
1773 bld_base->op_actions[TGSI_OPCODE_STORE].emit = store_emit;
1774 bld_base->op_actions[TGSI_OPCODE_RESQ].emit = resq_emit;
1775
1776 bld_base->op_actions[TGSI_OPCODE_ATOMUADD].emit = atomic_emit;
1777 bld_base->op_actions[TGSI_OPCODE_ATOMUADD].intr_name = "add";
1778 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG].emit = atomic_emit;
1779 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG].intr_name = "swap";
1780 bld_base->op_actions[TGSI_OPCODE_ATOMCAS].emit = atomic_emit;
1781 bld_base->op_actions[TGSI_OPCODE_ATOMCAS].intr_name = "cmpswap";
1782 bld_base->op_actions[TGSI_OPCODE_ATOMAND].emit = atomic_emit;
1783 bld_base->op_actions[TGSI_OPCODE_ATOMAND].intr_name = "and";
1784 bld_base->op_actions[TGSI_OPCODE_ATOMOR].emit = atomic_emit;
1785 bld_base->op_actions[TGSI_OPCODE_ATOMOR].intr_name = "or";
1786 bld_base->op_actions[TGSI_OPCODE_ATOMXOR].emit = atomic_emit;
1787 bld_base->op_actions[TGSI_OPCODE_ATOMXOR].intr_name = "xor";
1788 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN].emit = atomic_emit;
1789 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN].intr_name = "umin";
1790 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX].emit = atomic_emit;
1791 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX].intr_name = "umax";
1792 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN].emit = atomic_emit;
1793 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN].intr_name = "smin";
1794 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX].emit = atomic_emit;
1795 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX].intr_name = "smax";
1796 }