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radeonsi/nir: implement ac_shader_abi::load_sampler_desc
[mesa.git] / src / gallium / drivers / radeonsi / si_shader_tgsi_mem.c
1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "si_shader_internal.h"
25 #include "si_pipe.h"
26 #include "sid.h"
27 #include "gallivm/lp_bld_arit.h"
28 #include "gallivm/lp_bld_gather.h"
29 #include "gallivm/lp_bld_intr.h"
30 #include "tgsi/tgsi_build.h"
31 #include "tgsi/tgsi_parse.h"
32 #include "tgsi/tgsi_util.h"
33
34 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
35 struct lp_build_tgsi_context *bld_base,
36 struct lp_build_emit_data *emit_data);
37
38 static const struct lp_build_tgsi_action tex_action;
39
40 /**
41 * Given a v8i32 resource descriptor for a buffer, extract the size of the
42 * buffer in number of elements and return it as an i32.
43 */
44 static LLVMValueRef get_buffer_size(
45 struct lp_build_tgsi_context *bld_base,
46 LLVMValueRef descriptor)
47 {
48 struct si_shader_context *ctx = si_shader_context(bld_base);
49 struct gallivm_state *gallivm = &ctx->gallivm;
50 LLVMBuilderRef builder = gallivm->builder;
51 LLVMValueRef size =
52 LLVMBuildExtractElement(builder, descriptor,
53 LLVMConstInt(ctx->i32, 2, 0), "");
54
55 if (ctx->screen->b.chip_class == VI) {
56 /* On VI, the descriptor contains the size in bytes,
57 * but TXQ must return the size in elements.
58 * The stride is always non-zero for resources using TXQ.
59 */
60 LLVMValueRef stride =
61 LLVMBuildExtractElement(builder, descriptor,
62 ctx->i32_1, "");
63 stride = LLVMBuildLShr(builder, stride,
64 LLVMConstInt(ctx->i32, 16, 0), "");
65 stride = LLVMBuildAnd(builder, stride,
66 LLVMConstInt(ctx->i32, 0x3FFF, 0), "");
67
68 size = LLVMBuildUDiv(builder, size, stride, "");
69 }
70
71 return size;
72 }
73
74 static LLVMValueRef
75 shader_buffer_fetch_rsrc(struct si_shader_context *ctx,
76 const struct tgsi_full_src_register *reg)
77 {
78 LLVMValueRef index;
79 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
80 ctx->param_const_and_shader_buffers);
81
82 if (!reg->Register.Indirect) {
83 index = LLVMConstInt(ctx->i32,
84 si_get_shaderbuf_slot(reg->Register.Index), 0);
85 } else {
86 index = si_get_bounded_indirect_index(ctx, &reg->Indirect,
87 reg->Register.Index,
88 ctx->num_shader_buffers);
89 index = LLVMBuildSub(ctx->gallivm.builder,
90 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS - 1, 0),
91 index, "");
92 }
93
94 return ac_build_indexed_load_const(&ctx->ac, rsrc_ptr, index);
95 }
96
97 static bool tgsi_is_array_sampler(unsigned target)
98 {
99 return target == TGSI_TEXTURE_1D_ARRAY ||
100 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
101 target == TGSI_TEXTURE_2D_ARRAY ||
102 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
103 target == TGSI_TEXTURE_CUBE_ARRAY ||
104 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY ||
105 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
106 }
107
108 static bool tgsi_is_array_image(unsigned target)
109 {
110 return target == TGSI_TEXTURE_3D ||
111 target == TGSI_TEXTURE_CUBE ||
112 target == TGSI_TEXTURE_1D_ARRAY ||
113 target == TGSI_TEXTURE_2D_ARRAY ||
114 target == TGSI_TEXTURE_CUBE_ARRAY ||
115 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
116 }
117
118 /**
119 * Given a 256-bit resource descriptor, force the DCC enable bit to off.
120 *
121 * At least on Tonga, executing image stores on images with DCC enabled and
122 * non-trivial can eventually lead to lockups. This can occur when an
123 * application binds an image as read-only but then uses a shader that writes
124 * to it. The OpenGL spec allows almost arbitrarily bad behavior (including
125 * program termination) in this case, but it doesn't cost much to be a bit
126 * nicer: disabling DCC in the shader still leads to undefined results but
127 * avoids the lockup.
128 */
129 static LLVMValueRef force_dcc_off(struct si_shader_context *ctx,
130 LLVMValueRef rsrc)
131 {
132 if (ctx->screen->b.chip_class <= CIK) {
133 return rsrc;
134 } else {
135 LLVMBuilderRef builder = ctx->gallivm.builder;
136 LLVMValueRef i32_6 = LLVMConstInt(ctx->i32, 6, 0);
137 LLVMValueRef i32_C = LLVMConstInt(ctx->i32, C_008F28_COMPRESSION_EN, 0);
138 LLVMValueRef tmp;
139
140 tmp = LLVMBuildExtractElement(builder, rsrc, i32_6, "");
141 tmp = LLVMBuildAnd(builder, tmp, i32_C, "");
142 return LLVMBuildInsertElement(builder, rsrc, tmp, i32_6, "");
143 }
144 }
145
146 static LLVMValueRef load_image_desc(struct si_shader_context *ctx,
147 LLVMValueRef list, LLVMValueRef index,
148 unsigned target)
149 {
150 LLVMBuilderRef builder = ctx->gallivm.builder;
151
152 if (target == TGSI_TEXTURE_BUFFER) {
153 index = LLVMBuildMul(builder, index,
154 LLVMConstInt(ctx->i32, 2, 0), "");
155 index = LLVMBuildAdd(builder, index,
156 ctx->i32_1, "");
157 list = LLVMBuildPointerCast(builder, list,
158 si_const_array(ctx->v4i32, 0), "");
159 }
160
161 return ac_build_indexed_load_const(&ctx->ac, list, index);
162 }
163
164 /**
165 * Load the resource descriptor for \p image.
166 */
167 static void
168 image_fetch_rsrc(
169 struct lp_build_tgsi_context *bld_base,
170 const struct tgsi_full_src_register *image,
171 bool is_store, unsigned target,
172 LLVMValueRef *rsrc)
173 {
174 struct si_shader_context *ctx = si_shader_context(bld_base);
175 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
176 ctx->param_samplers_and_images);
177 LLVMValueRef index;
178 bool dcc_off = is_store;
179
180 if (!image->Register.Indirect) {
181 const struct tgsi_shader_info *info = bld_base->info;
182 unsigned images_writemask = info->images_store |
183 info->images_atomic;
184
185 index = LLVMConstInt(ctx->i32,
186 si_get_image_slot(image->Register.Index), 0);
187
188 if (images_writemask & (1 << image->Register.Index))
189 dcc_off = true;
190 } else {
191 /* From the GL_ARB_shader_image_load_store extension spec:
192 *
193 * If a shader performs an image load, store, or atomic
194 * operation using an image variable declared as an array,
195 * and if the index used to select an individual element is
196 * negative or greater than or equal to the size of the
197 * array, the results of the operation are undefined but may
198 * not lead to termination.
199 */
200 index = si_get_bounded_indirect_index(ctx, &image->Indirect,
201 image->Register.Index,
202 ctx->num_images);
203 index = LLVMBuildSub(ctx->gallivm.builder,
204 LLVMConstInt(ctx->i32, SI_NUM_IMAGES - 1, 0),
205 index, "");
206 }
207
208 if (image->Register.File != TGSI_FILE_IMAGE) {
209 struct gallivm_state *gallivm = &ctx->gallivm;
210 LLVMBuilderRef builder = gallivm->builder;
211
212 LLVMValueRef ptr =
213 lp_build_emit_fetch_src(bld_base, image,
214 TGSI_TYPE_UNSIGNED64, 0);
215 rsrc_ptr = LLVMBuildIntToPtr(builder, ptr,
216 si_const_array(ctx->v8i32, 0), "");
217 index = LLVMConstInt(ctx->i32, 0, 0);
218 }
219
220 *rsrc = load_image_desc(ctx, rsrc_ptr, index, target);
221 if (dcc_off && target != TGSI_TEXTURE_BUFFER)
222 *rsrc = force_dcc_off(ctx, *rsrc);
223 }
224
225 static LLVMValueRef image_fetch_coords(
226 struct lp_build_tgsi_context *bld_base,
227 const struct tgsi_full_instruction *inst,
228 unsigned src, LLVMValueRef desc)
229 {
230 struct si_shader_context *ctx = si_shader_context(bld_base);
231 struct gallivm_state *gallivm = &ctx->gallivm;
232 LLVMBuilderRef builder = gallivm->builder;
233 unsigned target = inst->Memory.Texture;
234 unsigned num_coords = tgsi_util_get_texture_coord_dim(target);
235 LLVMValueRef coords[4];
236 LLVMValueRef tmp;
237 int chan;
238
239 for (chan = 0; chan < num_coords; ++chan) {
240 tmp = lp_build_emit_fetch(bld_base, inst, src, chan);
241 tmp = LLVMBuildBitCast(builder, tmp, ctx->i32, "");
242 coords[chan] = tmp;
243 }
244
245 if (ctx->screen->b.chip_class >= GFX9) {
246 /* 1D textures are allocated and used as 2D on GFX9. */
247 if (target == TGSI_TEXTURE_1D) {
248 coords[1] = ctx->i32_0;
249 num_coords++;
250 } else if (target == TGSI_TEXTURE_1D_ARRAY) {
251 coords[2] = coords[1];
252 coords[1] = ctx->i32_0;
253 num_coords++;
254 } else if (target == TGSI_TEXTURE_2D) {
255 /* The hw can't bind a slice of a 3D image as a 2D
256 * image, because it ignores BASE_ARRAY if the target
257 * is 3D. The workaround is to read BASE_ARRAY and set
258 * it as the 3rd address operand for all 2D images.
259 */
260 LLVMValueRef first_layer, const5, mask;
261
262 const5 = LLVMConstInt(ctx->i32, 5, 0);
263 mask = LLVMConstInt(ctx->i32, S_008F24_BASE_ARRAY(~0), 0);
264 first_layer = LLVMBuildExtractElement(builder, desc, const5, "");
265 first_layer = LLVMBuildAnd(builder, first_layer, mask, "");
266
267 coords[2] = first_layer;
268 num_coords++;
269 }
270 }
271
272 if (num_coords == 1)
273 return coords[0];
274
275 if (num_coords == 3) {
276 /* LLVM has difficulties lowering 3-element vectors. */
277 coords[3] = bld_base->uint_bld.undef;
278 num_coords = 4;
279 }
280
281 return lp_build_gather_values(gallivm, coords, num_coords);
282 }
283
284 /**
285 * Append the extra mode bits that are used by image load and store.
286 */
287 static void image_append_args(
288 struct si_shader_context *ctx,
289 struct lp_build_emit_data * emit_data,
290 unsigned target,
291 bool atomic,
292 bool force_glc)
293 {
294 const struct tgsi_full_instruction *inst = emit_data->inst;
295 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
296 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
297 LLVMValueRef r128 = i1false;
298 LLVMValueRef da = tgsi_is_array_image(target) ? i1true : i1false;
299 LLVMValueRef glc =
300 force_glc ||
301 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE) ?
302 i1true : i1false;
303 LLVMValueRef slc = i1false;
304 LLVMValueRef lwe = i1false;
305
306 if (atomic || (HAVE_LLVM <= 0x0309)) {
307 emit_data->args[emit_data->arg_count++] = r128;
308 emit_data->args[emit_data->arg_count++] = da;
309 if (!atomic) {
310 emit_data->args[emit_data->arg_count++] = glc;
311 }
312 emit_data->args[emit_data->arg_count++] = slc;
313 return;
314 }
315
316 /* HAVE_LLVM >= 0x0400 */
317 emit_data->args[emit_data->arg_count++] = glc;
318 emit_data->args[emit_data->arg_count++] = slc;
319 emit_data->args[emit_data->arg_count++] = lwe;
320 emit_data->args[emit_data->arg_count++] = da;
321 }
322
323 /**
324 * Append the resource and indexing arguments for buffer intrinsics.
325 *
326 * \param rsrc the v4i32 buffer resource
327 * \param index index into the buffer (stride-based)
328 * \param offset byte offset into the buffer
329 */
330 static void buffer_append_args(
331 struct si_shader_context *ctx,
332 struct lp_build_emit_data *emit_data,
333 LLVMValueRef rsrc,
334 LLVMValueRef index,
335 LLVMValueRef offset,
336 bool atomic,
337 bool force_glc)
338 {
339 const struct tgsi_full_instruction *inst = emit_data->inst;
340 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
341 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
342
343 emit_data->args[emit_data->arg_count++] = rsrc;
344 emit_data->args[emit_data->arg_count++] = index; /* vindex */
345 emit_data->args[emit_data->arg_count++] = offset; /* voffset */
346 if (!atomic) {
347 emit_data->args[emit_data->arg_count++] =
348 force_glc ||
349 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE) ?
350 i1true : i1false; /* glc */
351 }
352 emit_data->args[emit_data->arg_count++] = i1false; /* slc */
353 }
354
355 static void load_fetch_args(
356 struct lp_build_tgsi_context * bld_base,
357 struct lp_build_emit_data * emit_data)
358 {
359 struct si_shader_context *ctx = si_shader_context(bld_base);
360 struct gallivm_state *gallivm = &ctx->gallivm;
361 const struct tgsi_full_instruction * inst = emit_data->inst;
362 unsigned target = inst->Memory.Texture;
363 LLVMValueRef rsrc;
364
365 emit_data->dst_type = ctx->v4f32;
366
367 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
368 LLVMBuilderRef builder = gallivm->builder;
369 LLVMValueRef offset;
370 LLVMValueRef tmp;
371
372 rsrc = shader_buffer_fetch_rsrc(ctx, &inst->Src[0]);
373
374 tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
375 offset = LLVMBuildBitCast(builder, tmp, ctx->i32, "");
376
377 buffer_append_args(ctx, emit_data, rsrc, ctx->i32_0,
378 offset, false, false);
379 } else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE ||
380 tgsi_is_bindless_image_file(inst->Src[0].Register.File)) {
381 LLVMValueRef coords;
382
383 image_fetch_rsrc(bld_base, &inst->Src[0], false, target, &rsrc);
384 coords = image_fetch_coords(bld_base, inst, 1, rsrc);
385
386 if (target == TGSI_TEXTURE_BUFFER) {
387 buffer_append_args(ctx, emit_data, rsrc, coords,
388 ctx->i32_0, false, false);
389 } else {
390 emit_data->args[0] = coords;
391 emit_data->args[1] = rsrc;
392 emit_data->args[2] = LLVMConstInt(ctx->i32, 15, 0); /* dmask */
393 emit_data->arg_count = 3;
394
395 image_append_args(ctx, emit_data, target, false, false);
396 }
397 }
398 }
399
400 static unsigned get_load_intr_attribs(bool can_speculate)
401 {
402 /* READNONE means writes can't affect it, while READONLY means that
403 * writes can affect it. */
404 return can_speculate && HAVE_LLVM >= 0x0400 ?
405 LP_FUNC_ATTR_READNONE :
406 LP_FUNC_ATTR_READONLY;
407 }
408
409 static unsigned get_store_intr_attribs(bool writeonly_memory)
410 {
411 return writeonly_memory && HAVE_LLVM >= 0x0400 ?
412 LP_FUNC_ATTR_INACCESSIBLE_MEM_ONLY :
413 LP_FUNC_ATTR_WRITEONLY;
414 }
415
416 static void load_emit_buffer(struct si_shader_context *ctx,
417 struct lp_build_emit_data *emit_data,
418 bool can_speculate)
419 {
420 const struct tgsi_full_instruction *inst = emit_data->inst;
421 uint writemask = inst->Dst[0].Register.WriteMask;
422 uint count = util_last_bit(writemask);
423 LLVMValueRef *args = emit_data->args;
424
425 /* Don't use SMEM for shader buffer loads, because LLVM doesn't
426 * select SMEM for SI.load.const with a non-constant offset, and
427 * constant offsets practically don't exist with shader buffers.
428 *
429 * Also, SI.load.const doesn't use inst_offset when it's lowered
430 * to VMEM, so we just end up with more VALU instructions in the end
431 * and no benefit.
432 *
433 * TODO: Remove this line once LLVM can select SMEM with a non-constant
434 * offset, and can derive inst_offset when VMEM is selected.
435 * After that, si_memory_barrier should invalidate sL1 for shader
436 * buffers.
437 */
438
439 assert(LLVMConstIntGetZExtValue(args[1]) == 0); /* vindex */
440 emit_data->output[emit_data->chan] =
441 ac_build_buffer_load(&ctx->ac, args[0], count, NULL,
442 args[2], NULL, 0,
443 LLVMConstIntGetZExtValue(args[3]),
444 LLVMConstIntGetZExtValue(args[4]),
445 can_speculate, false);
446 }
447
448 static LLVMValueRef get_memory_ptr(struct si_shader_context *ctx,
449 const struct tgsi_full_instruction *inst,
450 LLVMTypeRef type, int arg)
451 {
452 struct gallivm_state *gallivm = &ctx->gallivm;
453 LLVMBuilderRef builder = gallivm->builder;
454 LLVMValueRef offset, ptr;
455 int addr_space;
456
457 offset = lp_build_emit_fetch(&ctx->bld_base, inst, arg, 0);
458 offset = LLVMBuildBitCast(builder, offset, ctx->i32, "");
459
460 ptr = ctx->shared_memory;
461 ptr = LLVMBuildGEP(builder, ptr, &offset, 1, "");
462 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
463 ptr = LLVMBuildBitCast(builder, ptr, LLVMPointerType(type, addr_space), "");
464
465 return ptr;
466 }
467
468 static void load_emit_memory(
469 struct si_shader_context *ctx,
470 struct lp_build_emit_data *emit_data)
471 {
472 const struct tgsi_full_instruction *inst = emit_data->inst;
473 struct gallivm_state *gallivm = &ctx->gallivm;
474 LLVMBuilderRef builder = gallivm->builder;
475 unsigned writemask = inst->Dst[0].Register.WriteMask;
476 LLVMValueRef channels[4], ptr, derived_ptr, index;
477 int chan;
478
479 ptr = get_memory_ptr(ctx, inst, ctx->f32, 1);
480
481 for (chan = 0; chan < 4; ++chan) {
482 if (!(writemask & (1 << chan))) {
483 channels[chan] = LLVMGetUndef(ctx->f32);
484 continue;
485 }
486
487 index = LLVMConstInt(ctx->i32, chan, 0);
488 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
489 channels[chan] = LLVMBuildLoad(builder, derived_ptr, "");
490 }
491 emit_data->output[emit_data->chan] = lp_build_gather_values(gallivm, channels, 4);
492 }
493
494 /**
495 * Return true if the memory accessed by a LOAD or STORE instruction is
496 * read-only or write-only, respectively.
497 *
498 * \param shader_buffers_reverse_access_mask
499 * For LOAD, set this to (store | atomic) slot usage in the shader.
500 * For STORE, set this to (load | atomic) slot usage in the shader.
501 * \param images_reverse_access_mask Same as above, but for images.
502 */
503 static bool is_oneway_access_only(const struct tgsi_full_instruction *inst,
504 const struct tgsi_shader_info *info,
505 unsigned shader_buffers_reverse_access_mask,
506 unsigned images_reverse_access_mask)
507 {
508 /* RESTRICT means NOALIAS.
509 * If there are no writes, we can assume the accessed memory is read-only.
510 * If there are no reads, we can assume the accessed memory is write-only.
511 */
512 if (inst->Memory.Qualifier & TGSI_MEMORY_RESTRICT) {
513 unsigned reverse_access_mask;
514
515 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
516 reverse_access_mask = shader_buffers_reverse_access_mask;
517 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
518 reverse_access_mask = info->images_buffers &
519 images_reverse_access_mask;
520 } else {
521 reverse_access_mask = ~info->images_buffers &
522 images_reverse_access_mask;
523 }
524
525 if (inst->Src[0].Register.Indirect) {
526 if (!reverse_access_mask)
527 return true;
528 } else {
529 if (!(reverse_access_mask &
530 (1u << inst->Src[0].Register.Index)))
531 return true;
532 }
533 }
534
535 /* If there are no buffer writes (for both shader buffers & image
536 * buffers), it implies that buffer memory is read-only.
537 * If there are no buffer reads (for both shader buffers & image
538 * buffers), it implies that buffer memory is write-only.
539 *
540 * Same for the case when there are no writes/reads for non-buffer
541 * images.
542 */
543 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
544 (inst->Memory.Texture == TGSI_TEXTURE_BUFFER &&
545 (inst->Src[0].Register.File == TGSI_FILE_IMAGE ||
546 tgsi_is_bindless_image_file(inst->Src[0].Register.File)))) {
547 if (!shader_buffers_reverse_access_mask &&
548 !(info->images_buffers & images_reverse_access_mask))
549 return true;
550 } else {
551 if (!(~info->images_buffers & images_reverse_access_mask))
552 return true;
553 }
554 return false;
555 }
556
557 static void load_emit(
558 const struct lp_build_tgsi_action *action,
559 struct lp_build_tgsi_context *bld_base,
560 struct lp_build_emit_data *emit_data)
561 {
562 struct si_shader_context *ctx = si_shader_context(bld_base);
563 struct gallivm_state *gallivm = &ctx->gallivm;
564 LLVMBuilderRef builder = gallivm->builder;
565 const struct tgsi_full_instruction * inst = emit_data->inst;
566 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
567 char intrinsic_name[64];
568 bool can_speculate = false;
569
570 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
571 load_emit_memory(ctx, emit_data);
572 return;
573 }
574
575 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
576 si_emit_waitcnt(ctx, VM_CNT);
577
578 can_speculate = !(inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE) &&
579 is_oneway_access_only(inst, info,
580 info->shader_buffers_store |
581 info->shader_buffers_atomic,
582 info->images_store |
583 info->images_atomic);
584
585 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
586 load_emit_buffer(ctx, emit_data, can_speculate);
587 return;
588 }
589
590 if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
591 emit_data->output[emit_data->chan] =
592 lp_build_intrinsic(
593 builder, "llvm.amdgcn.buffer.load.format.v4f32", emit_data->dst_type,
594 emit_data->args, emit_data->arg_count,
595 get_load_intr_attribs(can_speculate));
596 } else {
597 ac_get_image_intr_name("llvm.amdgcn.image.load",
598 emit_data->dst_type, /* vdata */
599 LLVMTypeOf(emit_data->args[0]), /* coords */
600 LLVMTypeOf(emit_data->args[1]), /* rsrc */
601 intrinsic_name, sizeof(intrinsic_name));
602
603 emit_data->output[emit_data->chan] =
604 lp_build_intrinsic(
605 builder, intrinsic_name, emit_data->dst_type,
606 emit_data->args, emit_data->arg_count,
607 get_load_intr_attribs(can_speculate));
608 }
609 }
610
611 static void store_fetch_args(
612 struct lp_build_tgsi_context * bld_base,
613 struct lp_build_emit_data * emit_data)
614 {
615 struct si_shader_context *ctx = si_shader_context(bld_base);
616 struct gallivm_state *gallivm = &ctx->gallivm;
617 LLVMBuilderRef builder = gallivm->builder;
618 const struct tgsi_full_instruction * inst = emit_data->inst;
619 struct tgsi_full_src_register memory;
620 LLVMValueRef chans[4];
621 LLVMValueRef data;
622 LLVMValueRef rsrc;
623 unsigned chan;
624
625 emit_data->dst_type = LLVMVoidTypeInContext(gallivm->context);
626
627 for (chan = 0; chan < 4; ++chan) {
628 chans[chan] = lp_build_emit_fetch(bld_base, inst, 1, chan);
629 }
630 data = lp_build_gather_values(gallivm, chans, 4);
631
632 emit_data->args[emit_data->arg_count++] = data;
633
634 memory = tgsi_full_src_register_from_dst(&inst->Dst[0]);
635
636 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
637 LLVMValueRef offset;
638 LLVMValueRef tmp;
639
640 rsrc = shader_buffer_fetch_rsrc(ctx, &memory);
641
642 tmp = lp_build_emit_fetch(bld_base, inst, 0, 0);
643 offset = LLVMBuildBitCast(builder, tmp, ctx->i32, "");
644
645 buffer_append_args(ctx, emit_data, rsrc, ctx->i32_0,
646 offset, false, false);
647 } else if (inst->Dst[0].Register.File == TGSI_FILE_IMAGE ||
648 tgsi_is_bindless_image_file(inst->Dst[0].Register.File)) {
649 unsigned target = inst->Memory.Texture;
650 LLVMValueRef coords;
651
652 /* 8bit/16bit TC L1 write corruption bug on SI.
653 * All store opcodes not aligned to a dword are affected.
654 *
655 * The only way to get unaligned stores in radeonsi is through
656 * shader images.
657 */
658 bool force_glc = ctx->screen->b.chip_class == SI;
659
660 image_fetch_rsrc(bld_base, &memory, true, target, &rsrc);
661 coords = image_fetch_coords(bld_base, inst, 0, rsrc);
662
663 if (target == TGSI_TEXTURE_BUFFER) {
664 buffer_append_args(ctx, emit_data, rsrc, coords,
665 ctx->i32_0, false, force_glc);
666 } else {
667 emit_data->args[1] = coords;
668 emit_data->args[2] = rsrc;
669 emit_data->args[3] = LLVMConstInt(ctx->i32, 15, 0); /* dmask */
670 emit_data->arg_count = 4;
671
672 image_append_args(ctx, emit_data, target, false, force_glc);
673 }
674 }
675 }
676
677 static void store_emit_buffer(
678 struct si_shader_context *ctx,
679 struct lp_build_emit_data *emit_data,
680 bool writeonly_memory)
681 {
682 const struct tgsi_full_instruction *inst = emit_data->inst;
683 struct gallivm_state *gallivm = &ctx->gallivm;
684 LLVMBuilderRef builder = gallivm->builder;
685 LLVMValueRef base_data = emit_data->args[0];
686 LLVMValueRef base_offset = emit_data->args[3];
687 unsigned writemask = inst->Dst[0].Register.WriteMask;
688
689 while (writemask) {
690 int start, count;
691 const char *intrinsic_name;
692 LLVMValueRef data;
693 LLVMValueRef offset;
694 LLVMValueRef tmp;
695
696 u_bit_scan_consecutive_range(&writemask, &start, &count);
697
698 /* Due to an LLVM limitation, split 3-element writes
699 * into a 2-element and a 1-element write. */
700 if (count == 3) {
701 writemask |= 1 << (start + 2);
702 count = 2;
703 }
704
705 if (count == 4) {
706 data = base_data;
707 intrinsic_name = "llvm.amdgcn.buffer.store.v4f32";
708 } else if (count == 2) {
709 LLVMTypeRef v2f32 = LLVMVectorType(ctx->f32, 2);
710
711 tmp = LLVMBuildExtractElement(
712 builder, base_data,
713 LLVMConstInt(ctx->i32, start, 0), "");
714 data = LLVMBuildInsertElement(
715 builder, LLVMGetUndef(v2f32), tmp,
716 ctx->i32_0, "");
717
718 tmp = LLVMBuildExtractElement(
719 builder, base_data,
720 LLVMConstInt(ctx->i32, start + 1, 0), "");
721 data = LLVMBuildInsertElement(
722 builder, data, tmp, ctx->i32_1, "");
723
724 intrinsic_name = "llvm.amdgcn.buffer.store.v2f32";
725 } else {
726 assert(count == 1);
727 data = LLVMBuildExtractElement(
728 builder, base_data,
729 LLVMConstInt(ctx->i32, start, 0), "");
730 intrinsic_name = "llvm.amdgcn.buffer.store.f32";
731 }
732
733 offset = base_offset;
734 if (start != 0) {
735 offset = LLVMBuildAdd(
736 builder, offset,
737 LLVMConstInt(ctx->i32, start * 4, 0), "");
738 }
739
740 emit_data->args[0] = data;
741 emit_data->args[3] = offset;
742
743 lp_build_intrinsic(
744 builder, intrinsic_name, emit_data->dst_type,
745 emit_data->args, emit_data->arg_count,
746 get_store_intr_attribs(writeonly_memory));
747 }
748 }
749
750 static void store_emit_memory(
751 struct si_shader_context *ctx,
752 struct lp_build_emit_data *emit_data)
753 {
754 const struct tgsi_full_instruction *inst = emit_data->inst;
755 struct gallivm_state *gallivm = &ctx->gallivm;
756 LLVMBuilderRef builder = gallivm->builder;
757 unsigned writemask = inst->Dst[0].Register.WriteMask;
758 LLVMValueRef ptr, derived_ptr, data, index;
759 int chan;
760
761 ptr = get_memory_ptr(ctx, inst, ctx->f32, 0);
762
763 for (chan = 0; chan < 4; ++chan) {
764 if (!(writemask & (1 << chan))) {
765 continue;
766 }
767 data = lp_build_emit_fetch(&ctx->bld_base, inst, 1, chan);
768 index = LLVMConstInt(ctx->i32, chan, 0);
769 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
770 LLVMBuildStore(builder, data, derived_ptr);
771 }
772 }
773
774 static void store_emit(
775 const struct lp_build_tgsi_action *action,
776 struct lp_build_tgsi_context *bld_base,
777 struct lp_build_emit_data *emit_data)
778 {
779 struct si_shader_context *ctx = si_shader_context(bld_base);
780 struct gallivm_state *gallivm = &ctx->gallivm;
781 LLVMBuilderRef builder = gallivm->builder;
782 const struct tgsi_full_instruction * inst = emit_data->inst;
783 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
784 unsigned target = inst->Memory.Texture;
785 char intrinsic_name[64];
786 bool writeonly_memory = false;
787
788 if (inst->Dst[0].Register.File == TGSI_FILE_MEMORY) {
789 store_emit_memory(ctx, emit_data);
790 return;
791 }
792
793 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
794 si_emit_waitcnt(ctx, VM_CNT);
795
796 writeonly_memory = is_oneway_access_only(inst, info,
797 info->shader_buffers_load |
798 info->shader_buffers_atomic,
799 info->images_load |
800 info->images_atomic);
801
802 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
803 store_emit_buffer(ctx, emit_data, writeonly_memory);
804 return;
805 }
806
807 if (target == TGSI_TEXTURE_BUFFER) {
808 emit_data->output[emit_data->chan] = lp_build_intrinsic(
809 builder, "llvm.amdgcn.buffer.store.format.v4f32",
810 emit_data->dst_type, emit_data->args,
811 emit_data->arg_count,
812 get_store_intr_attribs(writeonly_memory));
813 } else {
814 ac_get_image_intr_name("llvm.amdgcn.image.store",
815 LLVMTypeOf(emit_data->args[0]), /* vdata */
816 LLVMTypeOf(emit_data->args[1]), /* coords */
817 LLVMTypeOf(emit_data->args[2]), /* rsrc */
818 intrinsic_name, sizeof(intrinsic_name));
819
820 emit_data->output[emit_data->chan] =
821 lp_build_intrinsic(
822 builder, intrinsic_name, emit_data->dst_type,
823 emit_data->args, emit_data->arg_count,
824 get_store_intr_attribs(writeonly_memory));
825 }
826 }
827
828 static void atomic_fetch_args(
829 struct lp_build_tgsi_context * bld_base,
830 struct lp_build_emit_data * emit_data)
831 {
832 struct si_shader_context *ctx = si_shader_context(bld_base);
833 struct gallivm_state *gallivm = &ctx->gallivm;
834 LLVMBuilderRef builder = gallivm->builder;
835 const struct tgsi_full_instruction * inst = emit_data->inst;
836 LLVMValueRef data1, data2;
837 LLVMValueRef rsrc;
838 LLVMValueRef tmp;
839
840 emit_data->dst_type = ctx->f32;
841
842 tmp = lp_build_emit_fetch(bld_base, inst, 2, 0);
843 data1 = LLVMBuildBitCast(builder, tmp, ctx->i32, "");
844
845 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
846 tmp = lp_build_emit_fetch(bld_base, inst, 3, 0);
847 data2 = LLVMBuildBitCast(builder, tmp, ctx->i32, "");
848 }
849
850 /* llvm.amdgcn.image/buffer.atomic.cmpswap reflect the hardware order
851 * of arguments, which is reversed relative to TGSI (and GLSL)
852 */
853 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
854 emit_data->args[emit_data->arg_count++] = data2;
855 emit_data->args[emit_data->arg_count++] = data1;
856
857 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
858 LLVMValueRef offset;
859
860 rsrc = shader_buffer_fetch_rsrc(ctx, &inst->Src[0]);
861
862 tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
863 offset = LLVMBuildBitCast(builder, tmp, ctx->i32, "");
864
865 buffer_append_args(ctx, emit_data, rsrc, ctx->i32_0,
866 offset, true, false);
867 } else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE ||
868 tgsi_is_bindless_image_file(inst->Src[0].Register.File)) {
869 unsigned target = inst->Memory.Texture;
870 LLVMValueRef coords;
871
872 image_fetch_rsrc(bld_base, &inst->Src[0], true, target, &rsrc);
873 coords = image_fetch_coords(bld_base, inst, 1, rsrc);
874
875 if (target == TGSI_TEXTURE_BUFFER) {
876 buffer_append_args(ctx, emit_data, rsrc, coords,
877 ctx->i32_0, true, false);
878 } else {
879 emit_data->args[emit_data->arg_count++] = coords;
880 emit_data->args[emit_data->arg_count++] = rsrc;
881
882 image_append_args(ctx, emit_data, target, true, false);
883 }
884 }
885 }
886
887 static void atomic_emit_memory(struct si_shader_context *ctx,
888 struct lp_build_emit_data *emit_data) {
889 struct gallivm_state *gallivm = &ctx->gallivm;
890 LLVMBuilderRef builder = gallivm->builder;
891 const struct tgsi_full_instruction * inst = emit_data->inst;
892 LLVMValueRef ptr, result, arg;
893
894 ptr = get_memory_ptr(ctx, inst, ctx->i32, 1);
895
896 arg = lp_build_emit_fetch(&ctx->bld_base, inst, 2, 0);
897 arg = LLVMBuildBitCast(builder, arg, ctx->i32, "");
898
899 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
900 LLVMValueRef new_data;
901 new_data = lp_build_emit_fetch(&ctx->bld_base,
902 inst, 3, 0);
903
904 new_data = LLVMBuildBitCast(builder, new_data, ctx->i32, "");
905
906 result = LLVMBuildAtomicCmpXchg(builder, ptr, arg, new_data,
907 LLVMAtomicOrderingSequentiallyConsistent,
908 LLVMAtomicOrderingSequentiallyConsistent,
909 false);
910
911 result = LLVMBuildExtractValue(builder, result, 0, "");
912 } else {
913 LLVMAtomicRMWBinOp op;
914
915 switch(inst->Instruction.Opcode) {
916 case TGSI_OPCODE_ATOMUADD:
917 op = LLVMAtomicRMWBinOpAdd;
918 break;
919 case TGSI_OPCODE_ATOMXCHG:
920 op = LLVMAtomicRMWBinOpXchg;
921 break;
922 case TGSI_OPCODE_ATOMAND:
923 op = LLVMAtomicRMWBinOpAnd;
924 break;
925 case TGSI_OPCODE_ATOMOR:
926 op = LLVMAtomicRMWBinOpOr;
927 break;
928 case TGSI_OPCODE_ATOMXOR:
929 op = LLVMAtomicRMWBinOpXor;
930 break;
931 case TGSI_OPCODE_ATOMUMIN:
932 op = LLVMAtomicRMWBinOpUMin;
933 break;
934 case TGSI_OPCODE_ATOMUMAX:
935 op = LLVMAtomicRMWBinOpUMax;
936 break;
937 case TGSI_OPCODE_ATOMIMIN:
938 op = LLVMAtomicRMWBinOpMin;
939 break;
940 case TGSI_OPCODE_ATOMIMAX:
941 op = LLVMAtomicRMWBinOpMax;
942 break;
943 default:
944 unreachable("unknown atomic opcode");
945 }
946
947 result = LLVMBuildAtomicRMW(builder, op, ptr, arg,
948 LLVMAtomicOrderingSequentiallyConsistent,
949 false);
950 }
951 emit_data->output[emit_data->chan] = LLVMBuildBitCast(builder, result, emit_data->dst_type, "");
952 }
953
954 static void atomic_emit(
955 const struct lp_build_tgsi_action *action,
956 struct lp_build_tgsi_context *bld_base,
957 struct lp_build_emit_data *emit_data)
958 {
959 struct si_shader_context *ctx = si_shader_context(bld_base);
960 struct gallivm_state *gallivm = &ctx->gallivm;
961 LLVMBuilderRef builder = gallivm->builder;
962 const struct tgsi_full_instruction * inst = emit_data->inst;
963 char intrinsic_name[40];
964 LLVMValueRef tmp;
965
966 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
967 atomic_emit_memory(ctx, emit_data);
968 return;
969 }
970
971 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
972 inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
973 snprintf(intrinsic_name, sizeof(intrinsic_name),
974 "llvm.amdgcn.buffer.atomic.%s", action->intr_name);
975 } else {
976 LLVMValueRef coords;
977 char coords_type[8];
978
979 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
980 coords = emit_data->args[2];
981 else
982 coords = emit_data->args[1];
983
984 ac_build_type_name_for_intr(LLVMTypeOf(coords), coords_type, sizeof(coords_type));
985 snprintf(intrinsic_name, sizeof(intrinsic_name),
986 "llvm.amdgcn.image.atomic.%s.%s",
987 action->intr_name, coords_type);
988 }
989
990 tmp = lp_build_intrinsic(
991 builder, intrinsic_name, ctx->i32,
992 emit_data->args, emit_data->arg_count, 0);
993 emit_data->output[emit_data->chan] =
994 LLVMBuildBitCast(builder, tmp, ctx->f32, "");
995 }
996
997 static void set_tex_fetch_args(struct si_shader_context *ctx,
998 struct lp_build_emit_data *emit_data,
999 unsigned target,
1000 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
1001 LLVMValueRef *param, unsigned count,
1002 unsigned dmask)
1003 {
1004 struct gallivm_state *gallivm = &ctx->gallivm;
1005 struct ac_image_args args = {};
1006
1007 /* Pad to power of two vector */
1008 while (count < util_next_power_of_two(count))
1009 param[count++] = LLVMGetUndef(ctx->i32);
1010
1011 if (count > 1)
1012 args.addr = lp_build_gather_values(gallivm, param, count);
1013 else
1014 args.addr = param[0];
1015
1016 args.resource = res_ptr;
1017 args.sampler = samp_ptr;
1018 args.dmask = dmask;
1019 args.unorm = target == TGSI_TEXTURE_RECT ||
1020 target == TGSI_TEXTURE_SHADOWRECT;
1021 args.da = tgsi_is_array_sampler(target);
1022
1023 /* Ugly, but we seem to have no other choice right now. */
1024 STATIC_ASSERT(sizeof(args) <= sizeof(emit_data->args));
1025 memcpy(emit_data->args, &args, sizeof(args));
1026 }
1027
1028 static LLVMValueRef fix_resinfo(struct si_shader_context *ctx,
1029 unsigned target, LLVMValueRef out)
1030 {
1031 LLVMBuilderRef builder = ctx->gallivm.builder;
1032
1033 /* 1D textures are allocated and used as 2D on GFX9. */
1034 if (ctx->screen->b.chip_class >= GFX9 &&
1035 (target == TGSI_TEXTURE_1D_ARRAY ||
1036 target == TGSI_TEXTURE_SHADOW1D_ARRAY)) {
1037 LLVMValueRef layers =
1038 LLVMBuildExtractElement(builder, out,
1039 LLVMConstInt(ctx->i32, 2, 0), "");
1040 out = LLVMBuildInsertElement(builder, out, layers,
1041 ctx->i32_1, "");
1042 }
1043
1044 /* Divide the number of layers by 6 to get the number of cubes. */
1045 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
1046 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
1047 LLVMValueRef imm2 = LLVMConstInt(ctx->i32, 2, 0);
1048
1049 LLVMValueRef z = LLVMBuildExtractElement(builder, out, imm2, "");
1050 z = LLVMBuildSDiv(builder, z, LLVMConstInt(ctx->i32, 6, 0), "");
1051
1052 out = LLVMBuildInsertElement(builder, out, z, imm2, "");
1053 }
1054 return out;
1055 }
1056
1057 static void resq_fetch_args(
1058 struct lp_build_tgsi_context * bld_base,
1059 struct lp_build_emit_data * emit_data)
1060 {
1061 struct si_shader_context *ctx = si_shader_context(bld_base);
1062 const struct tgsi_full_instruction *inst = emit_data->inst;
1063 const struct tgsi_full_src_register *reg = &inst->Src[0];
1064
1065 emit_data->dst_type = ctx->v4i32;
1066
1067 if (reg->Register.File == TGSI_FILE_BUFFER) {
1068 emit_data->args[0] = shader_buffer_fetch_rsrc(ctx, reg);
1069 emit_data->arg_count = 1;
1070 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
1071 image_fetch_rsrc(bld_base, reg, false, inst->Memory.Texture,
1072 &emit_data->args[0]);
1073 emit_data->arg_count = 1;
1074 } else {
1075 LLVMValueRef res_ptr;
1076 unsigned image_target;
1077
1078 if (inst->Memory.Texture == TGSI_TEXTURE_3D)
1079 image_target = TGSI_TEXTURE_2D_ARRAY;
1080 else
1081 image_target = inst->Memory.Texture;
1082
1083 image_fetch_rsrc(bld_base, reg, false, inst->Memory.Texture,
1084 &res_ptr);
1085 set_tex_fetch_args(ctx, emit_data, image_target,
1086 res_ptr, NULL, &ctx->i32_0, 1,
1087 0xf);
1088 }
1089 }
1090
1091 static void resq_emit(
1092 const struct lp_build_tgsi_action *action,
1093 struct lp_build_tgsi_context *bld_base,
1094 struct lp_build_emit_data *emit_data)
1095 {
1096 struct si_shader_context *ctx = si_shader_context(bld_base);
1097 struct gallivm_state *gallivm = &ctx->gallivm;
1098 LLVMBuilderRef builder = gallivm->builder;
1099 const struct tgsi_full_instruction *inst = emit_data->inst;
1100 LLVMValueRef out;
1101
1102 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
1103 out = LLVMBuildExtractElement(builder, emit_data->args[0],
1104 LLVMConstInt(ctx->i32, 2, 0), "");
1105 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
1106 out = get_buffer_size(bld_base, emit_data->args[0]);
1107 } else {
1108 struct ac_image_args args;
1109
1110 memcpy(&args, emit_data->args, sizeof(args)); /* ugly */
1111 args.opcode = ac_image_get_resinfo;
1112 out = ac_build_image_opcode(&ctx->ac, &args);
1113
1114 out = fix_resinfo(ctx, inst->Memory.Texture, out);
1115 }
1116
1117 emit_data->output[emit_data->chan] = out;
1118 }
1119
1120 /**
1121 * Load an image view, fmask view. or sampler state descriptor.
1122 */
1123 LLVMValueRef si_load_sampler_desc(struct si_shader_context *ctx,
1124 LLVMValueRef list, LLVMValueRef index,
1125 enum ac_descriptor_type type)
1126 {
1127 struct gallivm_state *gallivm = &ctx->gallivm;
1128 LLVMBuilderRef builder = gallivm->builder;
1129
1130 switch (type) {
1131 case AC_DESC_IMAGE:
1132 /* The image is at [0:7]. */
1133 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
1134 break;
1135 case AC_DESC_BUFFER:
1136 /* The buffer is in [4:7]. */
1137 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 4, 0), "");
1138 index = LLVMBuildAdd(builder, index, ctx->i32_1, "");
1139 list = LLVMBuildPointerCast(builder, list,
1140 si_const_array(ctx->v4i32, 0), "");
1141 break;
1142 case AC_DESC_FMASK:
1143 /* The FMASK is at [8:15]. */
1144 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
1145 index = LLVMBuildAdd(builder, index, ctx->i32_1, "");
1146 break;
1147 case AC_DESC_SAMPLER:
1148 /* The sampler state is at [12:15]. */
1149 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 4, 0), "");
1150 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 3, 0), "");
1151 list = LLVMBuildPointerCast(builder, list,
1152 si_const_array(ctx->v4i32, 0), "");
1153 break;
1154 }
1155
1156 return ac_build_indexed_load_const(&ctx->ac, list, index);
1157 }
1158
1159 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
1160 *
1161 * SI-CI:
1162 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
1163 * filtering manually. The driver sets img7 to a mask clearing
1164 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
1165 * s_and_b32 samp0, samp0, img7
1166 *
1167 * VI:
1168 * The ANISO_OVERRIDE sampler field enables this fix in TA.
1169 */
1170 static LLVMValueRef sici_fix_sampler_aniso(struct si_shader_context *ctx,
1171 LLVMValueRef res, LLVMValueRef samp)
1172 {
1173 LLVMBuilderRef builder = ctx->gallivm.builder;
1174 LLVMValueRef img7, samp0;
1175
1176 if (ctx->screen->b.chip_class >= VI)
1177 return samp;
1178
1179 img7 = LLVMBuildExtractElement(builder, res,
1180 LLVMConstInt(ctx->i32, 7, 0), "");
1181 samp0 = LLVMBuildExtractElement(builder, samp,
1182 ctx->i32_0, "");
1183 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
1184 return LLVMBuildInsertElement(builder, samp, samp0,
1185 ctx->i32_0, "");
1186 }
1187
1188 static void tex_fetch_ptrs(
1189 struct lp_build_tgsi_context *bld_base,
1190 struct lp_build_emit_data *emit_data,
1191 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr, LLVMValueRef *fmask_ptr)
1192 {
1193 struct si_shader_context *ctx = si_shader_context(bld_base);
1194 LLVMValueRef list = LLVMGetParam(ctx->main_fn, ctx->param_samplers_and_images);
1195 const struct tgsi_full_instruction *inst = emit_data->inst;
1196 const struct tgsi_full_src_register *reg;
1197 unsigned target = inst->Texture.Texture;
1198 unsigned sampler_src;
1199 LLVMValueRef index;
1200
1201 sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
1202 reg = &emit_data->inst->Src[sampler_src];
1203
1204 if (reg->Register.Indirect) {
1205 index = si_get_bounded_indirect_index(ctx,
1206 &reg->Indirect,
1207 reg->Register.Index,
1208 ctx->num_samplers);
1209 index = LLVMBuildAdd(ctx->gallivm.builder, index,
1210 LLVMConstInt(ctx->i32, SI_NUM_IMAGES / 2, 0), "");
1211 } else {
1212 index = LLVMConstInt(ctx->i32,
1213 si_get_sampler_slot(reg->Register.Index), 0);
1214 }
1215
1216 if (reg->Register.File != TGSI_FILE_SAMPLER) {
1217 struct gallivm_state *gallivm = &ctx->gallivm;
1218 LLVMBuilderRef builder = gallivm->builder;
1219
1220 LLVMValueRef ptr =
1221 lp_build_emit_fetch_src(bld_base, reg,
1222 TGSI_TYPE_UNSIGNED64, 0);
1223 list = LLVMBuildIntToPtr(builder, ptr,
1224 si_const_array(ctx->v8i32, 0), "");
1225 index = LLVMConstInt(ctx->i32, 0, 0);
1226 }
1227
1228 if (target == TGSI_TEXTURE_BUFFER)
1229 *res_ptr = si_load_sampler_desc(ctx, list, index, AC_DESC_BUFFER);
1230 else
1231 *res_ptr = si_load_sampler_desc(ctx, list, index, AC_DESC_IMAGE);
1232
1233 if (samp_ptr)
1234 *samp_ptr = NULL;
1235 if (fmask_ptr)
1236 *fmask_ptr = NULL;
1237
1238 if (target == TGSI_TEXTURE_2D_MSAA ||
1239 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
1240 if (fmask_ptr)
1241 *fmask_ptr = si_load_sampler_desc(ctx, list, index,
1242 AC_DESC_FMASK);
1243 } else if (target != TGSI_TEXTURE_BUFFER) {
1244 if (samp_ptr) {
1245 *samp_ptr = si_load_sampler_desc(ctx, list, index,
1246 AC_DESC_SAMPLER);
1247 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
1248 }
1249 }
1250 }
1251
1252 static void txq_fetch_args(
1253 struct lp_build_tgsi_context *bld_base,
1254 struct lp_build_emit_data *emit_data)
1255 {
1256 struct si_shader_context *ctx = si_shader_context(bld_base);
1257 const struct tgsi_full_instruction *inst = emit_data->inst;
1258 unsigned target = inst->Texture.Texture;
1259 LLVMValueRef res_ptr;
1260 LLVMValueRef address;
1261
1262 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, NULL, NULL);
1263
1264 if (target == TGSI_TEXTURE_BUFFER) {
1265 /* Read the size from the buffer descriptor directly. */
1266 emit_data->args[0] = get_buffer_size(bld_base, res_ptr);
1267 return;
1268 }
1269
1270 /* Textures - set the mip level. */
1271 address = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
1272
1273 set_tex_fetch_args(ctx, emit_data, target, res_ptr,
1274 NULL, &address, 1, 0xf);
1275 }
1276
1277 static void txq_emit(const struct lp_build_tgsi_action *action,
1278 struct lp_build_tgsi_context *bld_base,
1279 struct lp_build_emit_data *emit_data)
1280 {
1281 struct si_shader_context *ctx = si_shader_context(bld_base);
1282 struct ac_image_args args;
1283 unsigned target = emit_data->inst->Texture.Texture;
1284
1285 if (target == TGSI_TEXTURE_BUFFER) {
1286 /* Just return the buffer size. */
1287 emit_data->output[emit_data->chan] = emit_data->args[0];
1288 return;
1289 }
1290
1291 memcpy(&args, emit_data->args, sizeof(args)); /* ugly */
1292
1293 args.opcode = ac_image_get_resinfo;
1294 LLVMValueRef result = ac_build_image_opcode(&ctx->ac, &args);
1295
1296 emit_data->output[emit_data->chan] = fix_resinfo(ctx, target, result);
1297 }
1298
1299 static void tex_fetch_args(
1300 struct lp_build_tgsi_context *bld_base,
1301 struct lp_build_emit_data *emit_data)
1302 {
1303 struct si_shader_context *ctx = si_shader_context(bld_base);
1304 struct gallivm_state *gallivm = &ctx->gallivm;
1305 const struct tgsi_full_instruction *inst = emit_data->inst;
1306 unsigned opcode = inst->Instruction.Opcode;
1307 unsigned target = inst->Texture.Texture;
1308 LLVMValueRef coords[5], derivs[6];
1309 LLVMValueRef address[16];
1310 unsigned num_coords = tgsi_util_get_texture_coord_dim(target);
1311 int ref_pos = tgsi_util_get_shadow_ref_src_index(target);
1312 unsigned count = 0;
1313 unsigned chan;
1314 unsigned num_deriv_channels = 0;
1315 bool has_offset = inst->Texture.NumOffsets > 0;
1316 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
1317 unsigned dmask = 0xf;
1318
1319 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
1320
1321 if (target == TGSI_TEXTURE_BUFFER) {
1322 emit_data->dst_type = ctx->v4f32;
1323 emit_data->args[0] = res_ptr;
1324 emit_data->args[1] = ctx->i32_0;
1325 emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
1326 emit_data->arg_count = 3;
1327 return;
1328 }
1329
1330 /* Fetch and project texture coordinates */
1331 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
1332 for (chan = 0; chan < 3; chan++ ) {
1333 coords[chan] = lp_build_emit_fetch(bld_base,
1334 emit_data->inst, 0,
1335 chan);
1336 if (opcode == TGSI_OPCODE_TXP)
1337 coords[chan] = lp_build_emit_llvm_binary(bld_base,
1338 TGSI_OPCODE_DIV,
1339 coords[chan],
1340 coords[3]);
1341 }
1342
1343 if (opcode == TGSI_OPCODE_TXP)
1344 coords[3] = bld_base->base.one;
1345
1346 /* Pack offsets. */
1347 if (has_offset &&
1348 opcode != TGSI_OPCODE_TXF &&
1349 opcode != TGSI_OPCODE_TXF_LZ) {
1350 /* The offsets are six-bit signed integers packed like this:
1351 * X=[5:0], Y=[13:8], and Z=[21:16].
1352 */
1353 LLVMValueRef offset[3], pack;
1354
1355 assert(inst->Texture.NumOffsets == 1);
1356
1357 for (chan = 0; chan < 3; chan++) {
1358 offset[chan] = lp_build_emit_fetch_texoffset(bld_base,
1359 emit_data->inst, 0, chan);
1360 offset[chan] = LLVMBuildAnd(gallivm->builder, offset[chan],
1361 LLVMConstInt(ctx->i32, 0x3f, 0), "");
1362 if (chan)
1363 offset[chan] = LLVMBuildShl(gallivm->builder, offset[chan],
1364 LLVMConstInt(ctx->i32, chan*8, 0), "");
1365 }
1366
1367 pack = LLVMBuildOr(gallivm->builder, offset[0], offset[1], "");
1368 pack = LLVMBuildOr(gallivm->builder, pack, offset[2], "");
1369 address[count++] = pack;
1370 }
1371
1372 /* Pack LOD bias value */
1373 if (opcode == TGSI_OPCODE_TXB)
1374 address[count++] = coords[3];
1375 if (opcode == TGSI_OPCODE_TXB2)
1376 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
1377
1378 /* Pack depth comparison value */
1379 if (tgsi_is_shadow_target(target) && opcode != TGSI_OPCODE_LODQ) {
1380 LLVMValueRef z;
1381
1382 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
1383 z = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
1384 } else {
1385 assert(ref_pos >= 0);
1386 z = coords[ref_pos];
1387 }
1388
1389 /* TC-compatible HTILE promotes Z16 and Z24 to Z32_FLOAT,
1390 * so the depth comparison value isn't clamped for Z16 and
1391 * Z24 anymore. Do it manually here.
1392 *
1393 * It's unnecessary if the original texture format was
1394 * Z32_FLOAT, but we don't know that here.
1395 */
1396 if (ctx->screen->b.chip_class == VI)
1397 z = ac_build_clamp(&ctx->ac, z);
1398
1399 address[count++] = z;
1400 }
1401
1402 /* Pack user derivatives */
1403 if (opcode == TGSI_OPCODE_TXD) {
1404 int param, num_src_deriv_channels, num_dst_deriv_channels;
1405
1406 switch (target) {
1407 case TGSI_TEXTURE_3D:
1408 num_src_deriv_channels = 3;
1409 num_dst_deriv_channels = 3;
1410 num_deriv_channels = 3;
1411 break;
1412 case TGSI_TEXTURE_2D:
1413 case TGSI_TEXTURE_SHADOW2D:
1414 case TGSI_TEXTURE_RECT:
1415 case TGSI_TEXTURE_SHADOWRECT:
1416 case TGSI_TEXTURE_2D_ARRAY:
1417 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1418 num_src_deriv_channels = 2;
1419 num_dst_deriv_channels = 2;
1420 num_deriv_channels = 2;
1421 break;
1422 case TGSI_TEXTURE_CUBE:
1423 case TGSI_TEXTURE_SHADOWCUBE:
1424 case TGSI_TEXTURE_CUBE_ARRAY:
1425 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
1426 /* Cube derivatives will be converted to 2D. */
1427 num_src_deriv_channels = 3;
1428 num_dst_deriv_channels = 3;
1429 num_deriv_channels = 2;
1430 break;
1431 case TGSI_TEXTURE_1D:
1432 case TGSI_TEXTURE_SHADOW1D:
1433 case TGSI_TEXTURE_1D_ARRAY:
1434 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1435 num_src_deriv_channels = 1;
1436
1437 /* 1D textures are allocated and used as 2D on GFX9. */
1438 if (ctx->screen->b.chip_class >= GFX9) {
1439 num_dst_deriv_channels = 2;
1440 num_deriv_channels = 2;
1441 } else {
1442 num_dst_deriv_channels = 1;
1443 num_deriv_channels = 1;
1444 }
1445 break;
1446 default:
1447 unreachable("invalid target");
1448 }
1449
1450 for (param = 0; param < 2; param++) {
1451 for (chan = 0; chan < num_src_deriv_channels; chan++)
1452 derivs[param * num_dst_deriv_channels + chan] =
1453 lp_build_emit_fetch(bld_base, inst, param+1, chan);
1454
1455 /* Fill in the rest with zeros. */
1456 for (chan = num_src_deriv_channels;
1457 chan < num_dst_deriv_channels; chan++)
1458 derivs[param * num_dst_deriv_channels + chan] =
1459 bld_base->base.zero;
1460 }
1461 }
1462
1463 if (target == TGSI_TEXTURE_CUBE ||
1464 target == TGSI_TEXTURE_CUBE_ARRAY ||
1465 target == TGSI_TEXTURE_SHADOWCUBE ||
1466 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
1467 ac_prepare_cube_coords(&ctx->ac,
1468 opcode == TGSI_OPCODE_TXD,
1469 target == TGSI_TEXTURE_CUBE_ARRAY ||
1470 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY,
1471 coords, derivs);
1472
1473 if (opcode == TGSI_OPCODE_TXD)
1474 for (int i = 0; i < num_deriv_channels * 2; i++)
1475 address[count++] = derivs[i];
1476
1477 /* Pack texture coordinates */
1478 address[count++] = coords[0];
1479 if (num_coords > 1)
1480 address[count++] = coords[1];
1481 if (num_coords > 2)
1482 address[count++] = coords[2];
1483
1484 /* 1D textures are allocated and used as 2D on GFX9. */
1485 if (ctx->screen->b.chip_class >= GFX9) {
1486 LLVMValueRef filler;
1487
1488 /* Use 0.5, so that we don't sample the border color. */
1489 if (opcode == TGSI_OPCODE_TXF ||
1490 opcode == TGSI_OPCODE_TXF_LZ)
1491 filler = ctx->i32_0;
1492 else
1493 filler = LLVMConstReal(ctx->f32, 0.5);
1494
1495 if (target == TGSI_TEXTURE_1D ||
1496 target == TGSI_TEXTURE_SHADOW1D) {
1497 address[count++] = filler;
1498 } else if (target == TGSI_TEXTURE_1D_ARRAY ||
1499 target == TGSI_TEXTURE_SHADOW1D_ARRAY) {
1500 address[count] = address[count - 1];
1501 address[count - 1] = filler;
1502 count++;
1503 }
1504 }
1505
1506 /* Pack LOD or sample index */
1507 if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
1508 address[count++] = coords[3];
1509 else if (opcode == TGSI_OPCODE_TXL2)
1510 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
1511
1512 if (count > 16) {
1513 assert(!"Cannot handle more than 16 texture address parameters");
1514 count = 16;
1515 }
1516
1517 for (chan = 0; chan < count; chan++ ) {
1518 address[chan] = LLVMBuildBitCast(gallivm->builder,
1519 address[chan], ctx->i32, "");
1520 }
1521
1522 /* Adjust the sample index according to FMASK.
1523 *
1524 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
1525 * which is the identity mapping. Each nibble says which physical sample
1526 * should be fetched to get that sample.
1527 *
1528 * For example, 0x11111100 means there are only 2 samples stored and
1529 * the second sample covers 3/4 of the pixel. When reading samples 0
1530 * and 1, return physical sample 0 (determined by the first two 0s
1531 * in FMASK), otherwise return physical sample 1.
1532 *
1533 * The sample index should be adjusted as follows:
1534 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
1535 */
1536 if (target == TGSI_TEXTURE_2D_MSAA ||
1537 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
1538 struct lp_build_emit_data txf_emit_data = *emit_data;
1539 LLVMValueRef txf_address[4];
1540 /* We only need .xy for non-arrays, and .xyz for arrays. */
1541 unsigned txf_count = target == TGSI_TEXTURE_2D_MSAA ? 2 : 3;
1542 struct tgsi_full_instruction inst = {};
1543
1544 memcpy(txf_address, address, sizeof(txf_address));
1545
1546 /* Read FMASK using TXF_LZ. */
1547 inst.Instruction.Opcode = TGSI_OPCODE_TXF_LZ;
1548 inst.Texture.Texture = target;
1549 txf_emit_data.inst = &inst;
1550 txf_emit_data.chan = 0;
1551 set_tex_fetch_args(ctx, &txf_emit_data,
1552 target, fmask_ptr, NULL,
1553 txf_address, txf_count, 0xf);
1554 build_tex_intrinsic(&tex_action, bld_base, &txf_emit_data);
1555
1556 /* Initialize some constants. */
1557 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, 0);
1558 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xF, 0);
1559
1560 /* Apply the formula. */
1561 LLVMValueRef fmask =
1562 LLVMBuildExtractElement(gallivm->builder,
1563 txf_emit_data.output[0],
1564 ctx->i32_0, "");
1565
1566 unsigned sample_chan = txf_count; /* the sample index is last */
1567
1568 LLVMValueRef sample_index4 =
1569 LLVMBuildMul(gallivm->builder, address[sample_chan], four, "");
1570
1571 LLVMValueRef shifted_fmask =
1572 LLVMBuildLShr(gallivm->builder, fmask, sample_index4, "");
1573
1574 LLVMValueRef final_sample =
1575 LLVMBuildAnd(gallivm->builder, shifted_fmask, F, "");
1576
1577 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
1578 * resource descriptor is 0 (invalid),
1579 */
1580 LLVMValueRef fmask_desc =
1581 LLVMBuildBitCast(gallivm->builder, fmask_ptr,
1582 ctx->v8i32, "");
1583
1584 LLVMValueRef fmask_word1 =
1585 LLVMBuildExtractElement(gallivm->builder, fmask_desc,
1586 ctx->i32_1, "");
1587
1588 LLVMValueRef word1_is_nonzero =
1589 LLVMBuildICmp(gallivm->builder, LLVMIntNE,
1590 fmask_word1, ctx->i32_0, "");
1591
1592 /* Replace the MSAA sample index. */
1593 address[sample_chan] =
1594 LLVMBuildSelect(gallivm->builder, word1_is_nonzero,
1595 final_sample, address[sample_chan], "");
1596 }
1597
1598 if (opcode == TGSI_OPCODE_TXF ||
1599 opcode == TGSI_OPCODE_TXF_LZ) {
1600 /* add tex offsets */
1601 if (inst->Texture.NumOffsets) {
1602 struct lp_build_context *uint_bld = &bld_base->uint_bld;
1603 const struct tgsi_texture_offset *off = inst->TexOffsets;
1604
1605 assert(inst->Texture.NumOffsets == 1);
1606
1607 switch (target) {
1608 case TGSI_TEXTURE_3D:
1609 address[2] = lp_build_add(uint_bld, address[2],
1610 ctx->imms[off->Index * TGSI_NUM_CHANNELS + off->SwizzleZ]);
1611 /* fall through */
1612 case TGSI_TEXTURE_2D:
1613 case TGSI_TEXTURE_SHADOW2D:
1614 case TGSI_TEXTURE_RECT:
1615 case TGSI_TEXTURE_SHADOWRECT:
1616 case TGSI_TEXTURE_2D_ARRAY:
1617 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1618 address[1] =
1619 lp_build_add(uint_bld, address[1],
1620 ctx->imms[off->Index * TGSI_NUM_CHANNELS + off->SwizzleY]);
1621 /* fall through */
1622 case TGSI_TEXTURE_1D:
1623 case TGSI_TEXTURE_SHADOW1D:
1624 case TGSI_TEXTURE_1D_ARRAY:
1625 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1626 address[0] =
1627 lp_build_add(uint_bld, address[0],
1628 ctx->imms[off->Index * TGSI_NUM_CHANNELS + off->SwizzleX]);
1629 break;
1630 /* texture offsets do not apply to other texture targets */
1631 }
1632 }
1633 }
1634
1635 if (opcode == TGSI_OPCODE_TG4) {
1636 unsigned gather_comp = 0;
1637
1638 /* DMASK was repurposed for GATHER4. 4 components are always
1639 * returned and DMASK works like a swizzle - it selects
1640 * the component to fetch. The only valid DMASK values are
1641 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
1642 * (red,red,red,red) etc.) The ISA document doesn't mention
1643 * this.
1644 */
1645
1646 /* Get the component index from src1.x for Gather4. */
1647 if (!tgsi_is_shadow_target(target)) {
1648 LLVMValueRef comp_imm;
1649 struct tgsi_src_register src1 = inst->Src[1].Register;
1650
1651 assert(src1.File == TGSI_FILE_IMMEDIATE);
1652
1653 comp_imm = ctx->imms[src1.Index * TGSI_NUM_CHANNELS + src1.SwizzleX];
1654 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
1655 gather_comp = CLAMP(gather_comp, 0, 3);
1656 }
1657
1658 dmask = 1 << gather_comp;
1659 }
1660
1661 set_tex_fetch_args(ctx, emit_data, target, res_ptr,
1662 samp_ptr, address, count, dmask);
1663 }
1664
1665 /* Gather4 should follow the same rules as bilinear filtering, but the hardware
1666 * incorrectly forces nearest filtering if the texture format is integer.
1667 * The only effect it has on Gather4, which always returns 4 texels for
1668 * bilinear filtering, is that the final coordinates are off by 0.5 of
1669 * the texel size.
1670 *
1671 * The workaround is to subtract 0.5 from the unnormalized coordinates,
1672 * or (0.5 / size) from the normalized coordinates.
1673 */
1674 static void si_lower_gather4_integer(struct si_shader_context *ctx,
1675 struct ac_image_args *args,
1676 unsigned target)
1677 {
1678 LLVMBuilderRef builder = ctx->gallivm.builder;
1679 LLVMValueRef coord = args->addr;
1680 LLVMValueRef half_texel[2];
1681 /* Texture coordinates start after:
1682 * {offset, bias, z-compare, derivatives}
1683 * Only the offset and z-compare can occur here.
1684 */
1685 unsigned coord_vgpr_index = (int)args->offset + (int)args->compare;
1686 int c;
1687
1688 if (target == TGSI_TEXTURE_RECT ||
1689 target == TGSI_TEXTURE_SHADOWRECT) {
1690 half_texel[0] = half_texel[1] = LLVMConstReal(ctx->f32, -0.5);
1691 } else {
1692 struct tgsi_full_instruction txq_inst = {};
1693 struct lp_build_emit_data txq_emit_data = {};
1694
1695 /* Query the texture size. */
1696 txq_inst.Texture.Texture = target;
1697 txq_emit_data.inst = &txq_inst;
1698 txq_emit_data.dst_type = ctx->v4i32;
1699 set_tex_fetch_args(ctx, &txq_emit_data, target,
1700 args->resource, NULL, &ctx->i32_0,
1701 1, 0xf);
1702 txq_emit(NULL, &ctx->bld_base, &txq_emit_data);
1703
1704 /* Compute -0.5 / size. */
1705 for (c = 0; c < 2; c++) {
1706 half_texel[c] =
1707 LLVMBuildExtractElement(builder, txq_emit_data.output[0],
1708 LLVMConstInt(ctx->i32, c, 0), "");
1709 half_texel[c] = LLVMBuildUIToFP(builder, half_texel[c], ctx->f32, "");
1710 half_texel[c] =
1711 lp_build_emit_llvm_unary(&ctx->bld_base,
1712 TGSI_OPCODE_RCP, half_texel[c]);
1713 half_texel[c] = LLVMBuildFMul(builder, half_texel[c],
1714 LLVMConstReal(ctx->f32, -0.5), "");
1715 }
1716 }
1717
1718 for (c = 0; c < 2; c++) {
1719 LLVMValueRef tmp;
1720 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
1721
1722 tmp = LLVMBuildExtractElement(builder, coord, index, "");
1723 tmp = LLVMBuildBitCast(builder, tmp, ctx->f32, "");
1724 tmp = LLVMBuildFAdd(builder, tmp, half_texel[c], "");
1725 tmp = LLVMBuildBitCast(builder, tmp, ctx->i32, "");
1726 coord = LLVMBuildInsertElement(builder, coord, tmp, index, "");
1727 }
1728
1729 args->addr = coord;
1730 }
1731
1732 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
1733 struct lp_build_tgsi_context *bld_base,
1734 struct lp_build_emit_data *emit_data)
1735 {
1736 struct si_shader_context *ctx = si_shader_context(bld_base);
1737 const struct tgsi_full_instruction *inst = emit_data->inst;
1738 struct ac_image_args args;
1739 unsigned opcode = inst->Instruction.Opcode;
1740 unsigned target = inst->Texture.Texture;
1741
1742 if (target == TGSI_TEXTURE_BUFFER) {
1743 emit_data->output[emit_data->chan] =
1744 ac_build_buffer_load_format(&ctx->ac,
1745 emit_data->args[0],
1746 emit_data->args[2],
1747 emit_data->args[1],
1748 true);
1749 return;
1750 }
1751
1752 memcpy(&args, emit_data->args, sizeof(args)); /* ugly */
1753
1754 args.opcode = ac_image_sample;
1755 args.compare = tgsi_is_shadow_target(target);
1756 args.offset = inst->Texture.NumOffsets > 0;
1757
1758 switch (opcode) {
1759 case TGSI_OPCODE_TXF:
1760 case TGSI_OPCODE_TXF_LZ:
1761 args.opcode = opcode == TGSI_OPCODE_TXF_LZ ||
1762 target == TGSI_TEXTURE_2D_MSAA ||
1763 target == TGSI_TEXTURE_2D_ARRAY_MSAA ?
1764 ac_image_load : ac_image_load_mip;
1765 args.compare = false;
1766 args.offset = false;
1767 break;
1768 case TGSI_OPCODE_LODQ:
1769 args.opcode = ac_image_get_lod;
1770 args.compare = false;
1771 args.offset = false;
1772 break;
1773 case TGSI_OPCODE_TEX:
1774 case TGSI_OPCODE_TEX2:
1775 case TGSI_OPCODE_TXP:
1776 if (ctx->type != PIPE_SHADER_FRAGMENT)
1777 args.level_zero = true;
1778 break;
1779 case TGSI_OPCODE_TEX_LZ:
1780 args.level_zero = true;
1781 break;
1782 case TGSI_OPCODE_TXB:
1783 case TGSI_OPCODE_TXB2:
1784 assert(ctx->type == PIPE_SHADER_FRAGMENT);
1785 args.bias = true;
1786 break;
1787 case TGSI_OPCODE_TXL:
1788 case TGSI_OPCODE_TXL2:
1789 args.lod = true;
1790 break;
1791 case TGSI_OPCODE_TXD:
1792 args.deriv = true;
1793 break;
1794 case TGSI_OPCODE_TG4:
1795 args.opcode = ac_image_gather4;
1796 args.level_zero = true;
1797 break;
1798 default:
1799 assert(0);
1800 return;
1801 }
1802
1803 /* The hardware needs special lowering for Gather4 with integer formats. */
1804 if (ctx->screen->b.chip_class <= VI &&
1805 opcode == TGSI_OPCODE_TG4) {
1806 assert(inst->Texture.ReturnType != TGSI_RETURN_TYPE_UNKNOWN);
1807
1808 if (inst->Texture.ReturnType == TGSI_RETURN_TYPE_SINT ||
1809 inst->Texture.ReturnType == TGSI_RETURN_TYPE_UINT)
1810 si_lower_gather4_integer(ctx, &args, target);
1811 }
1812
1813 emit_data->output[emit_data->chan] =
1814 ac_build_image_opcode(&ctx->ac, &args);
1815 }
1816
1817 static void si_llvm_emit_txqs(
1818 const struct lp_build_tgsi_action *action,
1819 struct lp_build_tgsi_context *bld_base,
1820 struct lp_build_emit_data *emit_data)
1821 {
1822 struct si_shader_context *ctx = si_shader_context(bld_base);
1823 struct gallivm_state *gallivm = &ctx->gallivm;
1824 LLVMBuilderRef builder = gallivm->builder;
1825 LLVMValueRef res, samples;
1826 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
1827
1828 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
1829
1830
1831 /* Read the samples from the descriptor directly. */
1832 res = LLVMBuildBitCast(builder, res_ptr, ctx->v8i32, "");
1833 samples = LLVMBuildExtractElement(
1834 builder, res,
1835 LLVMConstInt(ctx->i32, 3, 0), "");
1836 samples = LLVMBuildLShr(builder, samples,
1837 LLVMConstInt(ctx->i32, 16, 0), "");
1838 samples = LLVMBuildAnd(builder, samples,
1839 LLVMConstInt(ctx->i32, 0xf, 0), "");
1840 samples = LLVMBuildShl(builder, ctx->i32_1,
1841 samples, "");
1842
1843 emit_data->output[emit_data->chan] = samples;
1844 }
1845
1846 static const struct lp_build_tgsi_action tex_action = {
1847 .fetch_args = tex_fetch_args,
1848 .emit = build_tex_intrinsic,
1849 };
1850
1851 /**
1852 * Setup actions for TGSI memory opcode, including texture opcodes.
1853 */
1854 void si_shader_context_init_mem(struct si_shader_context *ctx)
1855 {
1856 struct lp_build_tgsi_context *bld_base;
1857 struct lp_build_tgsi_action tmpl = {};
1858
1859 bld_base = &ctx->bld_base;
1860
1861 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
1862 bld_base->op_actions[TGSI_OPCODE_TEX_LZ] = tex_action;
1863 bld_base->op_actions[TGSI_OPCODE_TEX2] = tex_action;
1864 bld_base->op_actions[TGSI_OPCODE_TXB] = tex_action;
1865 bld_base->op_actions[TGSI_OPCODE_TXB2] = tex_action;
1866 bld_base->op_actions[TGSI_OPCODE_TXD] = tex_action;
1867 bld_base->op_actions[TGSI_OPCODE_TXF] = tex_action;
1868 bld_base->op_actions[TGSI_OPCODE_TXF_LZ] = tex_action;
1869 bld_base->op_actions[TGSI_OPCODE_TXL] = tex_action;
1870 bld_base->op_actions[TGSI_OPCODE_TXL2] = tex_action;
1871 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
1872 bld_base->op_actions[TGSI_OPCODE_TXQ].fetch_args = txq_fetch_args;
1873 bld_base->op_actions[TGSI_OPCODE_TXQ].emit = txq_emit;
1874 bld_base->op_actions[TGSI_OPCODE_TG4] = tex_action;
1875 bld_base->op_actions[TGSI_OPCODE_LODQ] = tex_action;
1876 bld_base->op_actions[TGSI_OPCODE_TXQS].emit = si_llvm_emit_txqs;
1877
1878 bld_base->op_actions[TGSI_OPCODE_LOAD].fetch_args = load_fetch_args;
1879 bld_base->op_actions[TGSI_OPCODE_LOAD].emit = load_emit;
1880 bld_base->op_actions[TGSI_OPCODE_STORE].fetch_args = store_fetch_args;
1881 bld_base->op_actions[TGSI_OPCODE_STORE].emit = store_emit;
1882 bld_base->op_actions[TGSI_OPCODE_RESQ].fetch_args = resq_fetch_args;
1883 bld_base->op_actions[TGSI_OPCODE_RESQ].emit = resq_emit;
1884
1885 tmpl.fetch_args = atomic_fetch_args;
1886 tmpl.emit = atomic_emit;
1887 bld_base->op_actions[TGSI_OPCODE_ATOMUADD] = tmpl;
1888 bld_base->op_actions[TGSI_OPCODE_ATOMUADD].intr_name = "add";
1889 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG] = tmpl;
1890 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG].intr_name = "swap";
1891 bld_base->op_actions[TGSI_OPCODE_ATOMCAS] = tmpl;
1892 bld_base->op_actions[TGSI_OPCODE_ATOMCAS].intr_name = "cmpswap";
1893 bld_base->op_actions[TGSI_OPCODE_ATOMAND] = tmpl;
1894 bld_base->op_actions[TGSI_OPCODE_ATOMAND].intr_name = "and";
1895 bld_base->op_actions[TGSI_OPCODE_ATOMOR] = tmpl;
1896 bld_base->op_actions[TGSI_OPCODE_ATOMOR].intr_name = "or";
1897 bld_base->op_actions[TGSI_OPCODE_ATOMXOR] = tmpl;
1898 bld_base->op_actions[TGSI_OPCODE_ATOMXOR].intr_name = "xor";
1899 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN] = tmpl;
1900 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN].intr_name = "umin";
1901 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX] = tmpl;
1902 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX].intr_name = "umax";
1903 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN] = tmpl;
1904 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN].intr_name = "smin";
1905 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX] = tmpl;
1906 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX].intr_name = "smax";
1907 }