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radeonsi: inline resq_fetch_args
[mesa.git] / src / gallium / drivers / radeonsi / si_shader_tgsi_mem.c
1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_shader_internal.h"
26 #include "si_pipe.h"
27 #include "sid.h"
28 #include "tgsi/tgsi_build.h"
29 #include "tgsi/tgsi_util.h"
30 #include "ac_llvm_util.h"
31
32 /**
33 * Given a v8i32 resource descriptor for a buffer, extract the size of the
34 * buffer in number of elements and return it as an i32.
35 */
36 static LLVMValueRef get_buffer_size(
37 struct lp_build_tgsi_context *bld_base,
38 LLVMValueRef descriptor)
39 {
40 struct si_shader_context *ctx = si_shader_context(bld_base);
41 LLVMBuilderRef builder = ctx->ac.builder;
42 LLVMValueRef size =
43 LLVMBuildExtractElement(builder, descriptor,
44 LLVMConstInt(ctx->i32, 2, 0), "");
45
46 if (ctx->screen->info.chip_class == VI) {
47 /* On VI, the descriptor contains the size in bytes,
48 * but TXQ must return the size in elements.
49 * The stride is always non-zero for resources using TXQ.
50 */
51 LLVMValueRef stride =
52 LLVMBuildExtractElement(builder, descriptor,
53 ctx->i32_1, "");
54 stride = LLVMBuildLShr(builder, stride,
55 LLVMConstInt(ctx->i32, 16, 0), "");
56 stride = LLVMBuildAnd(builder, stride,
57 LLVMConstInt(ctx->i32, 0x3FFF, 0), "");
58
59 size = LLVMBuildUDiv(builder, size, stride, "");
60 }
61
62 return size;
63 }
64
65 static LLVMValueRef
66 shader_buffer_fetch_rsrc(struct si_shader_context *ctx,
67 const struct tgsi_full_src_register *reg,
68 bool ubo)
69 {
70 LLVMValueRef index;
71
72 if (!reg->Register.Indirect) {
73 index = LLVMConstInt(ctx->i32, reg->Register.Index, false);
74 } else {
75 index = si_get_indirect_index(ctx, &reg->Indirect,
76 1, reg->Register.Index);
77 }
78
79 if (ubo)
80 return ctx->abi.load_ubo(&ctx->abi, index);
81 else
82 return ctx->abi.load_ssbo(&ctx->abi, index, false);
83 }
84
85 static enum ac_image_dim
86 ac_texture_dim_from_tgsi_target(struct si_screen *screen, enum tgsi_texture_type target)
87 {
88 switch (target) {
89 case TGSI_TEXTURE_1D:
90 case TGSI_TEXTURE_SHADOW1D:
91 if (screen->info.chip_class >= GFX9)
92 return ac_image_2d;
93 return ac_image_1d;
94 case TGSI_TEXTURE_2D:
95 case TGSI_TEXTURE_SHADOW2D:
96 case TGSI_TEXTURE_RECT:
97 case TGSI_TEXTURE_SHADOWRECT:
98 return ac_image_2d;
99 case TGSI_TEXTURE_3D:
100 return ac_image_3d;
101 case TGSI_TEXTURE_CUBE:
102 case TGSI_TEXTURE_SHADOWCUBE:
103 case TGSI_TEXTURE_CUBE_ARRAY:
104 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
105 return ac_image_cube;
106 case TGSI_TEXTURE_1D_ARRAY:
107 case TGSI_TEXTURE_SHADOW1D_ARRAY:
108 if (screen->info.chip_class >= GFX9)
109 return ac_image_2darray;
110 return ac_image_1darray;
111 case TGSI_TEXTURE_2D_ARRAY:
112 case TGSI_TEXTURE_SHADOW2D_ARRAY:
113 return ac_image_2darray;
114 case TGSI_TEXTURE_2D_MSAA:
115 return ac_image_2dmsaa;
116 case TGSI_TEXTURE_2D_ARRAY_MSAA:
117 return ac_image_2darraymsaa;
118 default:
119 unreachable("unhandled texture type");
120 }
121 }
122
123 static enum ac_image_dim
124 ac_image_dim_from_tgsi_target(struct si_screen *screen, enum tgsi_texture_type target)
125 {
126 enum ac_image_dim dim = ac_texture_dim_from_tgsi_target(screen, target);
127
128 /* Match the resource type set in the descriptor. */
129 if (dim == ac_image_cube ||
130 (screen->info.chip_class <= VI && dim == ac_image_3d))
131 dim = ac_image_2darray;
132 else if (target == TGSI_TEXTURE_2D && screen->info.chip_class >= GFX9) {
133 /* When a single layer of a 3D texture is bound, the shader
134 * will refer to a 2D target, but the descriptor has a 3D type.
135 * Since the HW ignores BASE_ARRAY in this case, we need to
136 * send 3 coordinates. This doesn't hurt when the underlying
137 * texture is non-3D.
138 */
139 dim = ac_image_3d;
140 }
141
142 return dim;
143 }
144
145 /**
146 * Given a 256-bit resource descriptor, force the DCC enable bit to off.
147 *
148 * At least on Tonga, executing image stores on images with DCC enabled and
149 * non-trivial can eventually lead to lockups. This can occur when an
150 * application binds an image as read-only but then uses a shader that writes
151 * to it. The OpenGL spec allows almost arbitrarily bad behavior (including
152 * program termination) in this case, but it doesn't cost much to be a bit
153 * nicer: disabling DCC in the shader still leads to undefined results but
154 * avoids the lockup.
155 */
156 static LLVMValueRef force_dcc_off(struct si_shader_context *ctx,
157 LLVMValueRef rsrc)
158 {
159 if (ctx->screen->info.chip_class <= CIK) {
160 return rsrc;
161 } else {
162 LLVMValueRef i32_6 = LLVMConstInt(ctx->i32, 6, 0);
163 LLVMValueRef i32_C = LLVMConstInt(ctx->i32, C_008F28_COMPRESSION_EN, 0);
164 LLVMValueRef tmp;
165
166 tmp = LLVMBuildExtractElement(ctx->ac.builder, rsrc, i32_6, "");
167 tmp = LLVMBuildAnd(ctx->ac.builder, tmp, i32_C, "");
168 return LLVMBuildInsertElement(ctx->ac.builder, rsrc, tmp, i32_6, "");
169 }
170 }
171
172 LLVMValueRef si_load_image_desc(struct si_shader_context *ctx,
173 LLVMValueRef list, LLVMValueRef index,
174 enum ac_descriptor_type desc_type, bool dcc_off)
175 {
176 LLVMBuilderRef builder = ctx->ac.builder;
177 LLVMValueRef rsrc;
178
179 if (desc_type == AC_DESC_BUFFER) {
180 index = LLVMBuildMul(builder, index,
181 LLVMConstInt(ctx->i32, 2, 0), "");
182 index = LLVMBuildAdd(builder, index,
183 ctx->i32_1, "");
184 list = LLVMBuildPointerCast(builder, list,
185 ac_array_in_const32_addr_space(ctx->v4i32), "");
186 } else {
187 assert(desc_type == AC_DESC_IMAGE);
188 }
189
190 rsrc = ac_build_load_to_sgpr(&ctx->ac, list, index);
191 if (desc_type == AC_DESC_IMAGE && dcc_off)
192 rsrc = force_dcc_off(ctx, rsrc);
193 return rsrc;
194 }
195
196 /**
197 * Load the resource descriptor for \p image.
198 */
199 static void
200 image_fetch_rsrc(
201 struct lp_build_tgsi_context *bld_base,
202 const struct tgsi_full_src_register *image,
203 bool is_store, unsigned target,
204 LLVMValueRef *rsrc)
205 {
206 struct si_shader_context *ctx = si_shader_context(bld_base);
207 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
208 ctx->param_samplers_and_images);
209 LLVMValueRef index;
210 bool dcc_off = is_store;
211
212 if (!image->Register.Indirect) {
213 const struct tgsi_shader_info *info = bld_base->info;
214 unsigned images_writemask = info->images_store |
215 info->images_atomic;
216
217 index = LLVMConstInt(ctx->i32,
218 si_get_image_slot(image->Register.Index), 0);
219
220 if (images_writemask & (1 << image->Register.Index))
221 dcc_off = true;
222 } else {
223 /* From the GL_ARB_shader_image_load_store extension spec:
224 *
225 * If a shader performs an image load, store, or atomic
226 * operation using an image variable declared as an array,
227 * and if the index used to select an individual element is
228 * negative or greater than or equal to the size of the
229 * array, the results of the operation are undefined but may
230 * not lead to termination.
231 */
232 index = si_get_bounded_indirect_index(ctx, &image->Indirect,
233 image->Register.Index,
234 ctx->num_images);
235 index = LLVMBuildSub(ctx->ac.builder,
236 LLVMConstInt(ctx->i32, SI_NUM_IMAGES - 1, 0),
237 index, "");
238 }
239
240 if (image->Register.File != TGSI_FILE_IMAGE) {
241 /* Bindless descriptors are accessible from a different pair of
242 * user SGPR indices.
243 */
244 rsrc_ptr = LLVMGetParam(ctx->main_fn,
245 ctx->param_bindless_samplers_and_images);
246 index = lp_build_emit_fetch_src(bld_base, image,
247 TGSI_TYPE_UNSIGNED, 0);
248
249 /* For simplicity, bindless image descriptors use fixed
250 * 16-dword slots for now.
251 */
252 index = LLVMBuildMul(ctx->ac.builder, index,
253 LLVMConstInt(ctx->i32, 2, 0), "");
254 }
255
256 *rsrc = si_load_image_desc(ctx, rsrc_ptr, index,
257 target == TGSI_TEXTURE_BUFFER ? AC_DESC_BUFFER : AC_DESC_IMAGE,
258 dcc_off);
259 }
260
261 static void image_fetch_coords(
262 struct lp_build_tgsi_context *bld_base,
263 const struct tgsi_full_instruction *inst,
264 unsigned src, LLVMValueRef desc,
265 LLVMValueRef *coords)
266 {
267 struct si_shader_context *ctx = si_shader_context(bld_base);
268 LLVMBuilderRef builder = ctx->ac.builder;
269 unsigned target = inst->Memory.Texture;
270 unsigned num_coords = tgsi_util_get_texture_coord_dim(target);
271 LLVMValueRef tmp;
272 int chan;
273
274 if (target == TGSI_TEXTURE_2D_MSAA ||
275 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
276 /* Need the sample index as well. */
277 num_coords++;
278 }
279
280 for (chan = 0; chan < num_coords; ++chan) {
281 tmp = lp_build_emit_fetch(bld_base, inst, src, chan);
282 tmp = ac_to_integer(&ctx->ac, tmp);
283 coords[chan] = tmp;
284 }
285
286 if (ctx->screen->info.chip_class >= GFX9) {
287 /* 1D textures are allocated and used as 2D on GFX9. */
288 if (target == TGSI_TEXTURE_1D) {
289 coords[1] = ctx->i32_0;
290 } else if (target == TGSI_TEXTURE_1D_ARRAY) {
291 coords[2] = coords[1];
292 coords[1] = ctx->i32_0;
293 } else if (target == TGSI_TEXTURE_2D) {
294 /* The hw can't bind a slice of a 3D image as a 2D
295 * image, because it ignores BASE_ARRAY if the target
296 * is 3D. The workaround is to read BASE_ARRAY and set
297 * it as the 3rd address operand for all 2D images.
298 */
299 LLVMValueRef first_layer, const5, mask;
300
301 const5 = LLVMConstInt(ctx->i32, 5, 0);
302 mask = LLVMConstInt(ctx->i32, S_008F24_BASE_ARRAY(~0), 0);
303 first_layer = LLVMBuildExtractElement(builder, desc, const5, "");
304 first_layer = LLVMBuildAnd(builder, first_layer, mask, "");
305
306 coords[2] = first_layer;
307 }
308 }
309 }
310
311 /**
312 * Append the resource and indexing arguments for buffer intrinsics.
313 *
314 * \param rsrc the v4i32 buffer resource
315 * \param index index into the buffer (stride-based)
316 * \param offset byte offset into the buffer
317 */
318 static void buffer_append_args(
319 struct si_shader_context *ctx,
320 struct lp_build_emit_data *emit_data,
321 LLVMValueRef rsrc,
322 LLVMValueRef index,
323 LLVMValueRef offset,
324 bool atomic,
325 bool force_glc)
326 {
327 const struct tgsi_full_instruction *inst = emit_data->inst;
328 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
329 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
330
331 emit_data->args[emit_data->arg_count++] = rsrc;
332 emit_data->args[emit_data->arg_count++] = index; /* vindex */
333 emit_data->args[emit_data->arg_count++] = offset; /* voffset */
334 if (!atomic) {
335 emit_data->args[emit_data->arg_count++] =
336 force_glc ||
337 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE) ?
338 i1true : i1false; /* glc */
339 }
340 emit_data->args[emit_data->arg_count++] = i1false; /* slc */
341 }
342
343 static void load_fetch_args(
344 struct lp_build_tgsi_context * bld_base,
345 struct lp_build_emit_data * emit_data)
346 {
347 struct si_shader_context *ctx = si_shader_context(bld_base);
348 const struct tgsi_full_instruction * inst = emit_data->inst;
349 unsigned target = inst->Memory.Texture;
350 LLVMValueRef rsrc;
351
352 emit_data->dst_type = ctx->v4f32;
353
354 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
355 inst->Src[0].Register.File == TGSI_FILE_CONSTBUF) {
356 LLVMValueRef offset;
357 LLVMValueRef tmp;
358
359 bool ubo = inst->Src[0].Register.File == TGSI_FILE_CONSTBUF;
360 rsrc = shader_buffer_fetch_rsrc(ctx, &inst->Src[0], ubo);
361
362 tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
363 offset = ac_to_integer(&ctx->ac, tmp);
364
365 buffer_append_args(ctx, emit_data, rsrc, ctx->i32_0,
366 offset, false, false);
367 } else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE ||
368 tgsi_is_bindless_image_file(inst->Src[0].Register.File)) {
369 image_fetch_rsrc(bld_base, &inst->Src[0], false, target, &rsrc);
370 image_fetch_coords(bld_base, inst, 1, rsrc, &emit_data->args[1]);
371
372 if (target == TGSI_TEXTURE_BUFFER) {
373 buffer_append_args(ctx, emit_data, rsrc, emit_data->args[1],
374 ctx->i32_0, false, false);
375 } else {
376 emit_data->args[0] = rsrc;
377 }
378 }
379 }
380
381 static void load_emit_buffer(struct si_shader_context *ctx,
382 struct lp_build_emit_data *emit_data,
383 bool can_speculate, bool allow_smem)
384 {
385 const struct tgsi_full_instruction *inst = emit_data->inst;
386 uint writemask = inst->Dst[0].Register.WriteMask;
387 uint count = util_last_bit(writemask);
388 LLVMValueRef *args = emit_data->args;
389
390 /* Don't use SMEM for shader buffer loads, because LLVM doesn't
391 * select SMEM for SI.load.const with a non-constant offset, and
392 * constant offsets practically don't exist with shader buffers.
393 *
394 * Also, SI.load.const doesn't use inst_offset when it's lowered
395 * to VMEM, so we just end up with more VALU instructions in the end
396 * and no benefit.
397 *
398 * TODO: Remove this line once LLVM can select SMEM with a non-constant
399 * offset, and can derive inst_offset when VMEM is selected.
400 * After that, si_memory_barrier should invalidate sL1 for shader
401 * buffers.
402 */
403
404 assert(LLVMConstIntGetZExtValue(args[1]) == 0); /* vindex */
405 emit_data->output[emit_data->chan] =
406 ac_build_buffer_load(&ctx->ac, args[0], count, NULL,
407 args[2], NULL, 0,
408 LLVMConstIntGetZExtValue(args[3]),
409 LLVMConstIntGetZExtValue(args[4]),
410 can_speculate, allow_smem);
411 }
412
413 static LLVMValueRef get_memory_ptr(struct si_shader_context *ctx,
414 const struct tgsi_full_instruction *inst,
415 LLVMTypeRef type, int arg)
416 {
417 LLVMBuilderRef builder = ctx->ac.builder;
418 LLVMValueRef offset, ptr;
419 int addr_space;
420
421 offset = lp_build_emit_fetch(&ctx->bld_base, inst, arg, 0);
422 offset = ac_to_integer(&ctx->ac, offset);
423
424 ptr = ctx->ac.lds;
425 ptr = LLVMBuildGEP(builder, ptr, &offset, 1, "");
426 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
427 ptr = LLVMBuildBitCast(builder, ptr, LLVMPointerType(type, addr_space), "");
428
429 return ptr;
430 }
431
432 static void load_emit_memory(
433 struct si_shader_context *ctx,
434 struct lp_build_emit_data *emit_data)
435 {
436 const struct tgsi_full_instruction *inst = emit_data->inst;
437 unsigned writemask = inst->Dst[0].Register.WriteMask;
438 LLVMValueRef channels[4], ptr, derived_ptr, index;
439 int chan;
440
441 ptr = get_memory_ptr(ctx, inst, ctx->f32, 1);
442
443 for (chan = 0; chan < 4; ++chan) {
444 if (!(writemask & (1 << chan))) {
445 channels[chan] = LLVMGetUndef(ctx->f32);
446 continue;
447 }
448
449 index = LLVMConstInt(ctx->i32, chan, 0);
450 derived_ptr = LLVMBuildGEP(ctx->ac.builder, ptr, &index, 1, "");
451 channels[chan] = LLVMBuildLoad(ctx->ac.builder, derived_ptr, "");
452 }
453 emit_data->output[emit_data->chan] = ac_build_gather_values(&ctx->ac, channels, 4);
454 }
455
456 /**
457 * Return true if the memory accessed by a LOAD or STORE instruction is
458 * read-only or write-only, respectively.
459 *
460 * \param shader_buffers_reverse_access_mask
461 * For LOAD, set this to (store | atomic) slot usage in the shader.
462 * For STORE, set this to (load | atomic) slot usage in the shader.
463 * \param images_reverse_access_mask Same as above, but for images.
464 */
465 static bool is_oneway_access_only(const struct tgsi_full_instruction *inst,
466 const struct tgsi_shader_info *info,
467 unsigned shader_buffers_reverse_access_mask,
468 unsigned images_reverse_access_mask)
469 {
470 /* RESTRICT means NOALIAS.
471 * If there are no writes, we can assume the accessed memory is read-only.
472 * If there are no reads, we can assume the accessed memory is write-only.
473 */
474 if (inst->Memory.Qualifier & TGSI_MEMORY_RESTRICT) {
475 unsigned reverse_access_mask;
476
477 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
478 reverse_access_mask = shader_buffers_reverse_access_mask;
479 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
480 reverse_access_mask = info->images_buffers &
481 images_reverse_access_mask;
482 } else {
483 reverse_access_mask = ~info->images_buffers &
484 images_reverse_access_mask;
485 }
486
487 if (inst->Src[0].Register.Indirect) {
488 if (!reverse_access_mask)
489 return true;
490 } else {
491 if (!(reverse_access_mask &
492 (1u << inst->Src[0].Register.Index)))
493 return true;
494 }
495 }
496
497 /* If there are no buffer writes (for both shader buffers & image
498 * buffers), it implies that buffer memory is read-only.
499 * If there are no buffer reads (for both shader buffers & image
500 * buffers), it implies that buffer memory is write-only.
501 *
502 * Same for the case when there are no writes/reads for non-buffer
503 * images.
504 */
505 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
506 (inst->Memory.Texture == TGSI_TEXTURE_BUFFER &&
507 (inst->Src[0].Register.File == TGSI_FILE_IMAGE ||
508 tgsi_is_bindless_image_file(inst->Src[0].Register.File)))) {
509 if (!shader_buffers_reverse_access_mask &&
510 !(info->images_buffers & images_reverse_access_mask))
511 return true;
512 } else {
513 if (!(~info->images_buffers & images_reverse_access_mask))
514 return true;
515 }
516 return false;
517 }
518
519 static void load_emit(
520 const struct lp_build_tgsi_action *action,
521 struct lp_build_tgsi_context *bld_base,
522 struct lp_build_emit_data *emit_data)
523 {
524 struct si_shader_context *ctx = si_shader_context(bld_base);
525 const struct tgsi_full_instruction * inst = emit_data->inst;
526 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
527 bool can_speculate = false;
528
529 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
530 load_emit_memory(ctx, emit_data);
531 return;
532 }
533
534 if (inst->Src[0].Register.File == TGSI_FILE_CONSTBUF) {
535 load_emit_buffer(ctx, emit_data, true, true);
536 return;
537 }
538
539 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
540 ac_build_waitcnt(&ctx->ac, VM_CNT);
541
542 can_speculate = !(inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE) &&
543 is_oneway_access_only(inst, info,
544 info->shader_buffers_store |
545 info->shader_buffers_atomic,
546 info->images_store |
547 info->images_atomic);
548
549 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
550 load_emit_buffer(ctx, emit_data, can_speculate, false);
551 return;
552 }
553
554 if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
555 unsigned num_channels = util_last_bit(inst->Dst[0].Register.WriteMask);
556 LLVMValueRef result =
557 ac_build_buffer_load_format(&ctx->ac,
558 emit_data->args[0],
559 emit_data->args[1],
560 emit_data->args[2],
561 num_channels,
562 LLVMConstIntGetZExtValue(emit_data->args[3]),
563 can_speculate);
564 emit_data->output[emit_data->chan] =
565 ac_build_expand_to_vec4(&ctx->ac, result, num_channels);
566 } else {
567 struct ac_image_args args = {};
568 args.opcode = ac_image_load;
569 args.resource = emit_data->args[0];
570 memcpy(args.coords, &emit_data->args[1], sizeof(args.coords));
571 args.dim = ac_image_dim_from_tgsi_target(ctx->screen, inst->Memory.Texture);
572 if (inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE))
573 args.cache_policy = ac_glc;
574 args.attributes = ac_get_load_intr_attribs(can_speculate);
575 args.dmask = 0xf;
576
577 emit_data->output[emit_data->chan] =
578 ac_build_image_opcode(&ctx->ac, &args);
579 }
580 }
581
582 static void store_fetch_args(
583 struct lp_build_tgsi_context * bld_base,
584 struct lp_build_emit_data * emit_data)
585 {
586 struct si_shader_context *ctx = si_shader_context(bld_base);
587 const struct tgsi_full_instruction * inst = emit_data->inst;
588 struct tgsi_full_src_register memory;
589 LLVMValueRef chans[4];
590 LLVMValueRef data;
591 LLVMValueRef rsrc;
592 unsigned chan;
593
594 emit_data->dst_type = ctx->voidt;
595
596 for (chan = 0; chan < 4; ++chan) {
597 chans[chan] = lp_build_emit_fetch(bld_base, inst, 1, chan);
598 }
599 data = ac_build_gather_values(&ctx->ac, chans, 4);
600
601 emit_data->args[emit_data->arg_count++] = data;
602
603 memory = tgsi_full_src_register_from_dst(&inst->Dst[0]);
604
605 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
606 LLVMValueRef offset;
607 LLVMValueRef tmp;
608
609 rsrc = shader_buffer_fetch_rsrc(ctx, &memory, false);
610
611 tmp = lp_build_emit_fetch(bld_base, inst, 0, 0);
612 offset = ac_to_integer(&ctx->ac, tmp);
613
614 buffer_append_args(ctx, emit_data, rsrc, ctx->i32_0,
615 offset, false, false);
616 } else if (inst->Dst[0].Register.File == TGSI_FILE_IMAGE ||
617 tgsi_is_bindless_image_file(inst->Dst[0].Register.File)) {
618 unsigned target = inst->Memory.Texture;
619
620 /* 8bit/16bit TC L1 write corruption bug on SI.
621 * All store opcodes not aligned to a dword are affected.
622 *
623 * The only way to get unaligned stores in radeonsi is through
624 * shader images.
625 */
626 bool force_glc = ctx->screen->info.chip_class == SI;
627
628 image_fetch_rsrc(bld_base, &memory, true, target, &rsrc);
629 image_fetch_coords(bld_base, inst, 0, rsrc, &emit_data->args[2]);
630
631 if (target == TGSI_TEXTURE_BUFFER) {
632 buffer_append_args(ctx, emit_data, rsrc, emit_data->args[2],
633 ctx->i32_0, false, force_glc);
634 } else {
635 emit_data->args[1] = rsrc;
636 }
637 }
638 }
639
640 static void store_emit_buffer(
641 struct si_shader_context *ctx,
642 struct lp_build_emit_data *emit_data,
643 bool writeonly_memory)
644 {
645 const struct tgsi_full_instruction *inst = emit_data->inst;
646 LLVMBuilderRef builder = ctx->ac.builder;
647 LLVMValueRef base_data = emit_data->args[0];
648 LLVMValueRef base_offset = emit_data->args[3];
649 unsigned writemask = inst->Dst[0].Register.WriteMask;
650
651 /* If this is write-only, don't keep data in L1 to prevent
652 * evicting L1 cache lines that may be needed by other
653 * instructions.
654 */
655 if (writeonly_memory)
656 emit_data->args[4] = LLVMConstInt(ctx->i1, 1, 0); /* GLC = 1 */
657
658 while (writemask) {
659 int start, count;
660 const char *intrinsic_name;
661 LLVMValueRef data;
662 LLVMValueRef offset;
663 LLVMValueRef tmp;
664
665 u_bit_scan_consecutive_range(&writemask, &start, &count);
666
667 /* Due to an LLVM limitation, split 3-element writes
668 * into a 2-element and a 1-element write. */
669 if (count == 3) {
670 writemask |= 1 << (start + 2);
671 count = 2;
672 }
673
674 if (count == 4) {
675 data = base_data;
676 intrinsic_name = "llvm.amdgcn.buffer.store.v4f32";
677 } else if (count == 2) {
678 LLVMTypeRef v2f32 = LLVMVectorType(ctx->f32, 2);
679
680 tmp = LLVMBuildExtractElement(
681 builder, base_data,
682 LLVMConstInt(ctx->i32, start, 0), "");
683 data = LLVMBuildInsertElement(
684 builder, LLVMGetUndef(v2f32), tmp,
685 ctx->i32_0, "");
686
687 tmp = LLVMBuildExtractElement(
688 builder, base_data,
689 LLVMConstInt(ctx->i32, start + 1, 0), "");
690 data = LLVMBuildInsertElement(
691 builder, data, tmp, ctx->i32_1, "");
692
693 intrinsic_name = "llvm.amdgcn.buffer.store.v2f32";
694 } else {
695 assert(count == 1);
696 data = LLVMBuildExtractElement(
697 builder, base_data,
698 LLVMConstInt(ctx->i32, start, 0), "");
699 intrinsic_name = "llvm.amdgcn.buffer.store.f32";
700 }
701
702 offset = base_offset;
703 if (start != 0) {
704 offset = LLVMBuildAdd(
705 builder, offset,
706 LLVMConstInt(ctx->i32, start * 4, 0), "");
707 }
708
709 emit_data->args[0] = data;
710 emit_data->args[3] = offset;
711
712 ac_build_intrinsic(
713 &ctx->ac, intrinsic_name, emit_data->dst_type,
714 emit_data->args, emit_data->arg_count,
715 ac_get_store_intr_attribs(writeonly_memory));
716 }
717 }
718
719 static void store_emit_memory(
720 struct si_shader_context *ctx,
721 struct lp_build_emit_data *emit_data)
722 {
723 const struct tgsi_full_instruction *inst = emit_data->inst;
724 LLVMBuilderRef builder = ctx->ac.builder;
725 unsigned writemask = inst->Dst[0].Register.WriteMask;
726 LLVMValueRef ptr, derived_ptr, data, index;
727 int chan;
728
729 ptr = get_memory_ptr(ctx, inst, ctx->f32, 0);
730
731 for (chan = 0; chan < 4; ++chan) {
732 if (!(writemask & (1 << chan))) {
733 continue;
734 }
735 data = lp_build_emit_fetch(&ctx->bld_base, inst, 1, chan);
736 index = LLVMConstInt(ctx->i32, chan, 0);
737 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
738 LLVMBuildStore(builder, data, derived_ptr);
739 }
740 }
741
742 static void store_emit(
743 const struct lp_build_tgsi_action *action,
744 struct lp_build_tgsi_context *bld_base,
745 struct lp_build_emit_data *emit_data)
746 {
747 struct si_shader_context *ctx = si_shader_context(bld_base);
748 const struct tgsi_full_instruction * inst = emit_data->inst;
749 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
750 unsigned target = inst->Memory.Texture;
751 bool writeonly_memory = false;
752
753 if (inst->Dst[0].Register.File == TGSI_FILE_MEMORY) {
754 store_emit_memory(ctx, emit_data);
755 return;
756 }
757
758 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
759 ac_build_waitcnt(&ctx->ac, VM_CNT);
760
761 writeonly_memory = is_oneway_access_only(inst, info,
762 info->shader_buffers_load |
763 info->shader_buffers_atomic,
764 info->images_load |
765 info->images_atomic);
766
767 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
768 store_emit_buffer(ctx, emit_data, writeonly_memory);
769 return;
770 }
771
772 if (target == TGSI_TEXTURE_BUFFER) {
773 /* If this is write-only, don't keep data in L1 to prevent
774 * evicting L1 cache lines that may be needed by other
775 * instructions.
776 */
777 if (writeonly_memory)
778 emit_data->args[4] = LLVMConstInt(ctx->i1, 1, 0); /* GLC = 1 */
779
780 emit_data->output[emit_data->chan] = ac_build_intrinsic(
781 &ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32",
782 emit_data->dst_type, emit_data->args,
783 emit_data->arg_count,
784 ac_get_store_intr_attribs(writeonly_memory));
785 } else {
786 struct ac_image_args args = {};
787 args.opcode = ac_image_store;
788 args.data[0] = emit_data->args[0];
789 args.resource = emit_data->args[1];
790 memcpy(args.coords, &emit_data->args[2], sizeof(args.coords));
791 args.dim = ac_image_dim_from_tgsi_target(ctx->screen, inst->Memory.Texture);
792 args.attributes = ac_get_store_intr_attribs(writeonly_memory);
793 args.dmask = 0xf;
794
795 /* Workaround for 8bit/16bit TC L1 write corruption bug on SI.
796 * All store opcodes not aligned to a dword are affected.
797 */
798 if (ctx->screen->info.chip_class == SI ||
799 /* If this is write-only, don't keep data in L1 to prevent
800 * evicting L1 cache lines that may be needed by other
801 * instructions. */
802 writeonly_memory ||
803 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE))
804 args.cache_policy = ac_glc;
805
806 emit_data->output[emit_data->chan] =
807 ac_build_image_opcode(&ctx->ac, &args);
808 }
809 }
810
811 static void atomic_fetch_args(
812 struct lp_build_tgsi_context * bld_base,
813 struct lp_build_emit_data * emit_data)
814 {
815 struct si_shader_context *ctx = si_shader_context(bld_base);
816 const struct tgsi_full_instruction * inst = emit_data->inst;
817 LLVMValueRef data1, data2;
818 LLVMValueRef rsrc;
819 LLVMValueRef tmp;
820
821 emit_data->dst_type = ctx->f32;
822
823 tmp = lp_build_emit_fetch(bld_base, inst, 2, 0);
824 data1 = ac_to_integer(&ctx->ac, tmp);
825
826 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
827 tmp = lp_build_emit_fetch(bld_base, inst, 3, 0);
828 data2 = ac_to_integer(&ctx->ac, tmp);
829 }
830
831 /* llvm.amdgcn.image/buffer.atomic.cmpswap reflect the hardware order
832 * of arguments, which is reversed relative to TGSI (and GLSL)
833 */
834 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
835 emit_data->args[emit_data->arg_count++] = data2;
836 emit_data->args[emit_data->arg_count++] = data1;
837
838 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
839 LLVMValueRef offset;
840
841 rsrc = shader_buffer_fetch_rsrc(ctx, &inst->Src[0], false);
842
843 tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
844 offset = ac_to_integer(&ctx->ac, tmp);
845
846 buffer_append_args(ctx, emit_data, rsrc, ctx->i32_0,
847 offset, true, false);
848 } else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE ||
849 tgsi_is_bindless_image_file(inst->Src[0].Register.File)) {
850 unsigned target = inst->Memory.Texture;
851
852 image_fetch_rsrc(bld_base, &inst->Src[0], true, target, &rsrc);
853 image_fetch_coords(bld_base, inst, 1, rsrc,
854 &emit_data->args[emit_data->arg_count + 1]);
855
856 if (target == TGSI_TEXTURE_BUFFER) {
857 buffer_append_args(ctx, emit_data, rsrc,
858 emit_data->args[emit_data->arg_count + 1],
859 ctx->i32_0, true, false);
860 } else {
861 emit_data->args[emit_data->arg_count] = rsrc;
862 }
863 }
864 }
865
866 static void atomic_emit_memory(struct si_shader_context *ctx,
867 struct lp_build_emit_data *emit_data) {
868 LLVMBuilderRef builder = ctx->ac.builder;
869 const struct tgsi_full_instruction * inst = emit_data->inst;
870 LLVMValueRef ptr, result, arg;
871
872 ptr = get_memory_ptr(ctx, inst, ctx->i32, 1);
873
874 arg = lp_build_emit_fetch(&ctx->bld_base, inst, 2, 0);
875 arg = ac_to_integer(&ctx->ac, arg);
876
877 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
878 LLVMValueRef new_data;
879 new_data = lp_build_emit_fetch(&ctx->bld_base,
880 inst, 3, 0);
881
882 new_data = ac_to_integer(&ctx->ac, new_data);
883
884 result = LLVMBuildAtomicCmpXchg(builder, ptr, arg, new_data,
885 LLVMAtomicOrderingSequentiallyConsistent,
886 LLVMAtomicOrderingSequentiallyConsistent,
887 false);
888
889 result = LLVMBuildExtractValue(builder, result, 0, "");
890 } else {
891 LLVMAtomicRMWBinOp op;
892
893 switch(inst->Instruction.Opcode) {
894 case TGSI_OPCODE_ATOMUADD:
895 op = LLVMAtomicRMWBinOpAdd;
896 break;
897 case TGSI_OPCODE_ATOMXCHG:
898 op = LLVMAtomicRMWBinOpXchg;
899 break;
900 case TGSI_OPCODE_ATOMAND:
901 op = LLVMAtomicRMWBinOpAnd;
902 break;
903 case TGSI_OPCODE_ATOMOR:
904 op = LLVMAtomicRMWBinOpOr;
905 break;
906 case TGSI_OPCODE_ATOMXOR:
907 op = LLVMAtomicRMWBinOpXor;
908 break;
909 case TGSI_OPCODE_ATOMUMIN:
910 op = LLVMAtomicRMWBinOpUMin;
911 break;
912 case TGSI_OPCODE_ATOMUMAX:
913 op = LLVMAtomicRMWBinOpUMax;
914 break;
915 case TGSI_OPCODE_ATOMIMIN:
916 op = LLVMAtomicRMWBinOpMin;
917 break;
918 case TGSI_OPCODE_ATOMIMAX:
919 op = LLVMAtomicRMWBinOpMax;
920 break;
921 default:
922 unreachable("unknown atomic opcode");
923 }
924
925 result = LLVMBuildAtomicRMW(builder, op, ptr, arg,
926 LLVMAtomicOrderingSequentiallyConsistent,
927 false);
928 }
929 emit_data->output[emit_data->chan] = LLVMBuildBitCast(builder, result, emit_data->dst_type, "");
930 }
931
932 static void atomic_emit(
933 const struct lp_build_tgsi_action *action,
934 struct lp_build_tgsi_context *bld_base,
935 struct lp_build_emit_data *emit_data)
936 {
937 struct si_shader_context *ctx = si_shader_context(bld_base);
938 const struct tgsi_full_instruction * inst = emit_data->inst;
939 LLVMValueRef tmp;
940
941 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
942 atomic_emit_memory(ctx, emit_data);
943 return;
944 }
945
946 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
947 inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
948 char intrinsic_name[40];
949 snprintf(intrinsic_name, sizeof(intrinsic_name),
950 "llvm.amdgcn.buffer.atomic.%s", action->intr_name);
951 tmp = ac_build_intrinsic(
952 &ctx->ac, intrinsic_name, ctx->i32,
953 emit_data->args, emit_data->arg_count, 0);
954 emit_data->output[emit_data->chan] = ac_to_float(&ctx->ac, tmp);
955 } else {
956 unsigned num_data = inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS ? 2 : 1;
957 struct ac_image_args args = {};
958
959 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
960 args.opcode = ac_image_atomic_cmpswap;
961 } else {
962 args.opcode = ac_image_atomic;
963 switch (inst->Instruction.Opcode) {
964 case TGSI_OPCODE_ATOMXCHG: args.atomic = ac_atomic_swap; break;
965 case TGSI_OPCODE_ATOMUADD: args.atomic = ac_atomic_add; break;
966 case TGSI_OPCODE_ATOMAND: args.atomic = ac_atomic_and; break;
967 case TGSI_OPCODE_ATOMOR: args.atomic = ac_atomic_or; break;
968 case TGSI_OPCODE_ATOMXOR: args.atomic = ac_atomic_xor; break;
969 case TGSI_OPCODE_ATOMUMIN: args.atomic = ac_atomic_umin; break;
970 case TGSI_OPCODE_ATOMUMAX: args.atomic = ac_atomic_umax; break;
971 case TGSI_OPCODE_ATOMIMIN: args.atomic = ac_atomic_smin; break;
972 case TGSI_OPCODE_ATOMIMAX: args.atomic = ac_atomic_smax; break;
973 default: unreachable("unhandled image atomic");
974 }
975 }
976
977 for (unsigned i = 0; i < num_data; ++i)
978 args.data[i] = emit_data->args[i];
979
980 args.resource = emit_data->args[num_data];
981 memcpy(args.coords, &emit_data->args[num_data + 1], sizeof(args.coords));
982 args.dim = ac_image_dim_from_tgsi_target(ctx->screen, inst->Memory.Texture);
983
984 emit_data->output[emit_data->chan] =
985 ac_to_float(&ctx->ac, ac_build_image_opcode(&ctx->ac, &args));
986 }
987 }
988
989 static LLVMValueRef fix_resinfo(struct si_shader_context *ctx,
990 unsigned target, LLVMValueRef out)
991 {
992 LLVMBuilderRef builder = ctx->ac.builder;
993
994 /* 1D textures are allocated and used as 2D on GFX9. */
995 if (ctx->screen->info.chip_class >= GFX9 &&
996 (target == TGSI_TEXTURE_1D_ARRAY ||
997 target == TGSI_TEXTURE_SHADOW1D_ARRAY)) {
998 LLVMValueRef layers =
999 LLVMBuildExtractElement(builder, out,
1000 LLVMConstInt(ctx->i32, 2, 0), "");
1001 out = LLVMBuildInsertElement(builder, out, layers,
1002 ctx->i32_1, "");
1003 }
1004
1005 /* Divide the number of layers by 6 to get the number of cubes. */
1006 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
1007 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
1008 LLVMValueRef imm2 = LLVMConstInt(ctx->i32, 2, 0);
1009
1010 LLVMValueRef z = LLVMBuildExtractElement(builder, out, imm2, "");
1011 z = LLVMBuildSDiv(builder, z, LLVMConstInt(ctx->i32, 6, 0), "");
1012
1013 out = LLVMBuildInsertElement(builder, out, z, imm2, "");
1014 }
1015 return out;
1016 }
1017
1018 static void resq_emit(
1019 const struct lp_build_tgsi_action *action,
1020 struct lp_build_tgsi_context *bld_base,
1021 struct lp_build_emit_data *emit_data)
1022 {
1023 struct si_shader_context *ctx = si_shader_context(bld_base);
1024 LLVMBuilderRef builder = ctx->ac.builder;
1025 const struct tgsi_full_instruction *inst = emit_data->inst;
1026 const struct tgsi_full_src_register *reg = &inst->Src[0];
1027
1028 if (reg->Register.File == TGSI_FILE_BUFFER) {
1029 LLVMValueRef rsrc = shader_buffer_fetch_rsrc(ctx, reg, false);
1030
1031 emit_data->output[emit_data->chan] =
1032 LLVMBuildExtractElement(builder, rsrc,
1033 LLVMConstInt(ctx->i32, 2, 0), "");
1034 return;
1035 }
1036
1037 /* Images */
1038 if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
1039 LLVMValueRef rsrc;
1040
1041 image_fetch_rsrc(bld_base, reg, false, inst->Memory.Texture, &rsrc);
1042 emit_data->output[emit_data->chan] =
1043 get_buffer_size(bld_base, rsrc);
1044 return;
1045 }
1046
1047 struct ac_image_args args = {};
1048 unsigned image_target;
1049
1050 if (inst->Memory.Texture == TGSI_TEXTURE_3D)
1051 image_target = TGSI_TEXTURE_2D_ARRAY;
1052 else
1053 image_target = inst->Memory.Texture;
1054
1055 image_fetch_rsrc(bld_base, reg, false, inst->Memory.Texture,
1056 &args.resource);
1057 args.opcode = ac_image_get_resinfo;
1058 args.dim = ac_texture_dim_from_tgsi_target(ctx->screen, image_target);
1059 args.lod = ctx->i32_0;
1060 args.dmask = 0xf;
1061
1062 emit_data->output[emit_data->chan] =
1063 fix_resinfo(ctx, inst->Memory.Texture,
1064 ac_build_image_opcode(&ctx->ac, &args));
1065 }
1066
1067 /**
1068 * Load an image view, fmask view. or sampler state descriptor.
1069 */
1070 LLVMValueRef si_load_sampler_desc(struct si_shader_context *ctx,
1071 LLVMValueRef list, LLVMValueRef index,
1072 enum ac_descriptor_type type)
1073 {
1074 LLVMBuilderRef builder = ctx->ac.builder;
1075
1076 switch (type) {
1077 case AC_DESC_IMAGE:
1078 /* The image is at [0:7]. */
1079 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
1080 break;
1081 case AC_DESC_BUFFER:
1082 /* The buffer is in [4:7]. */
1083 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 4, 0), "");
1084 index = LLVMBuildAdd(builder, index, ctx->i32_1, "");
1085 list = LLVMBuildPointerCast(builder, list,
1086 ac_array_in_const32_addr_space(ctx->v4i32), "");
1087 break;
1088 case AC_DESC_FMASK:
1089 /* The FMASK is at [8:15]. */
1090 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
1091 index = LLVMBuildAdd(builder, index, ctx->i32_1, "");
1092 break;
1093 case AC_DESC_SAMPLER:
1094 /* The sampler state is at [12:15]. */
1095 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 4, 0), "");
1096 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 3, 0), "");
1097 list = LLVMBuildPointerCast(builder, list,
1098 ac_array_in_const32_addr_space(ctx->v4i32), "");
1099 break;
1100 }
1101
1102 return ac_build_load_to_sgpr(&ctx->ac, list, index);
1103 }
1104
1105 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
1106 *
1107 * SI-CI:
1108 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
1109 * filtering manually. The driver sets img7 to a mask clearing
1110 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
1111 * s_and_b32 samp0, samp0, img7
1112 *
1113 * VI:
1114 * The ANISO_OVERRIDE sampler field enables this fix in TA.
1115 */
1116 static LLVMValueRef sici_fix_sampler_aniso(struct si_shader_context *ctx,
1117 LLVMValueRef res, LLVMValueRef samp)
1118 {
1119 LLVMValueRef img7, samp0;
1120
1121 if (ctx->screen->info.chip_class >= VI)
1122 return samp;
1123
1124 img7 = LLVMBuildExtractElement(ctx->ac.builder, res,
1125 LLVMConstInt(ctx->i32, 7, 0), "");
1126 samp0 = LLVMBuildExtractElement(ctx->ac.builder, samp,
1127 ctx->i32_0, "");
1128 samp0 = LLVMBuildAnd(ctx->ac.builder, samp0, img7, "");
1129 return LLVMBuildInsertElement(ctx->ac.builder, samp, samp0,
1130 ctx->i32_0, "");
1131 }
1132
1133 static void tex_fetch_ptrs(
1134 struct lp_build_tgsi_context *bld_base,
1135 struct lp_build_emit_data *emit_data,
1136 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr, LLVMValueRef *fmask_ptr)
1137 {
1138 struct si_shader_context *ctx = si_shader_context(bld_base);
1139 LLVMValueRef list = LLVMGetParam(ctx->main_fn, ctx->param_samplers_and_images);
1140 const struct tgsi_full_instruction *inst = emit_data->inst;
1141 const struct tgsi_full_src_register *reg;
1142 unsigned target = inst->Texture.Texture;
1143 unsigned sampler_src;
1144 LLVMValueRef index;
1145
1146 sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
1147 reg = &emit_data->inst->Src[sampler_src];
1148
1149 if (reg->Register.Indirect) {
1150 index = si_get_bounded_indirect_index(ctx,
1151 &reg->Indirect,
1152 reg->Register.Index,
1153 ctx->num_samplers);
1154 index = LLVMBuildAdd(ctx->ac.builder, index,
1155 LLVMConstInt(ctx->i32, SI_NUM_IMAGES / 2, 0), "");
1156 } else {
1157 index = LLVMConstInt(ctx->i32,
1158 si_get_sampler_slot(reg->Register.Index), 0);
1159 }
1160
1161 if (reg->Register.File != TGSI_FILE_SAMPLER) {
1162 /* Bindless descriptors are accessible from a different pair of
1163 * user SGPR indices.
1164 */
1165 list = LLVMGetParam(ctx->main_fn,
1166 ctx->param_bindless_samplers_and_images);
1167 index = lp_build_emit_fetch_src(bld_base, reg,
1168 TGSI_TYPE_UNSIGNED, 0);
1169 }
1170
1171 if (target == TGSI_TEXTURE_BUFFER)
1172 *res_ptr = si_load_sampler_desc(ctx, list, index, AC_DESC_BUFFER);
1173 else
1174 *res_ptr = si_load_sampler_desc(ctx, list, index, AC_DESC_IMAGE);
1175
1176 if (samp_ptr)
1177 *samp_ptr = NULL;
1178 if (fmask_ptr)
1179 *fmask_ptr = NULL;
1180
1181 if (target == TGSI_TEXTURE_2D_MSAA ||
1182 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
1183 if (fmask_ptr)
1184 *fmask_ptr = si_load_sampler_desc(ctx, list, index,
1185 AC_DESC_FMASK);
1186 } else if (target != TGSI_TEXTURE_BUFFER) {
1187 if (samp_ptr) {
1188 *samp_ptr = si_load_sampler_desc(ctx, list, index,
1189 AC_DESC_SAMPLER);
1190 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
1191 }
1192 }
1193 }
1194
1195 static void txq_emit(const struct lp_build_tgsi_action *action,
1196 struct lp_build_tgsi_context *bld_base,
1197 struct lp_build_emit_data *emit_data)
1198 {
1199 struct si_shader_context *ctx = si_shader_context(bld_base);
1200 const struct tgsi_full_instruction *inst = emit_data->inst;
1201 unsigned target = inst->Texture.Texture;
1202 struct ac_image_args args = {};
1203
1204 tex_fetch_ptrs(bld_base, emit_data, &args.resource, NULL, NULL);
1205
1206 if (target == TGSI_TEXTURE_BUFFER) {
1207 /* Read the size from the buffer descriptor directly. */
1208 emit_data->output[emit_data->chan] =
1209 get_buffer_size(bld_base, args.resource);
1210 return;
1211 }
1212
1213 args.opcode = ac_image_get_resinfo;
1214 args.dim = ac_texture_dim_from_tgsi_target(ctx->screen, target);
1215 args.lod = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
1216 args.dmask = 0xf;
1217
1218 LLVMValueRef result = ac_build_image_opcode(&ctx->ac, &args);
1219
1220 emit_data->output[emit_data->chan] = fix_resinfo(ctx, target, result);
1221 }
1222
1223 /* Gather4 should follow the same rules as bilinear filtering, but the hardware
1224 * incorrectly forces nearest filtering if the texture format is integer.
1225 * The only effect it has on Gather4, which always returns 4 texels for
1226 * bilinear filtering, is that the final coordinates are off by 0.5 of
1227 * the texel size.
1228 *
1229 * The workaround is to subtract 0.5 from the unnormalized coordinates,
1230 * or (0.5 / size) from the normalized coordinates.
1231 *
1232 * However, cube textures with 8_8_8_8 data formats require a different
1233 * workaround of overriding the num format to USCALED/SSCALED. This would lose
1234 * precision in 32-bit data formats, so it needs to be applied dynamically at
1235 * runtime. In this case, return an i1 value that indicates whether the
1236 * descriptor was overridden (and hence a fixup of the sampler result is needed).
1237 */
1238 static LLVMValueRef
1239 si_lower_gather4_integer(struct si_shader_context *ctx,
1240 struct ac_image_args *args,
1241 unsigned target,
1242 enum tgsi_return_type return_type)
1243 {
1244 LLVMBuilderRef builder = ctx->ac.builder;
1245 LLVMValueRef wa_8888 = NULL;
1246 LLVMValueRef half_texel[2];
1247
1248 assert(return_type == TGSI_RETURN_TYPE_SINT ||
1249 return_type == TGSI_RETURN_TYPE_UINT);
1250
1251 if (target == TGSI_TEXTURE_CUBE ||
1252 target == TGSI_TEXTURE_CUBE_ARRAY) {
1253 LLVMValueRef formats;
1254 LLVMValueRef data_format;
1255 LLVMValueRef wa_formats;
1256
1257 formats = LLVMBuildExtractElement(builder, args->resource, ctx->i32_1, "");
1258
1259 data_format = LLVMBuildLShr(builder, formats,
1260 LLVMConstInt(ctx->i32, 20, false), "");
1261 data_format = LLVMBuildAnd(builder, data_format,
1262 LLVMConstInt(ctx->i32, (1u << 6) - 1, false), "");
1263 wa_8888 = LLVMBuildICmp(
1264 builder, LLVMIntEQ, data_format,
1265 LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false),
1266 "");
1267
1268 uint32_t wa_num_format =
1269 return_type == TGSI_RETURN_TYPE_UINT ?
1270 S_008F14_NUM_FORMAT_GFX6(V_008F14_IMG_NUM_FORMAT_USCALED) :
1271 S_008F14_NUM_FORMAT_GFX6(V_008F14_IMG_NUM_FORMAT_SSCALED);
1272 wa_formats = LLVMBuildAnd(builder, formats,
1273 LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false),
1274 "");
1275 wa_formats = LLVMBuildOr(builder, wa_formats,
1276 LLVMConstInt(ctx->i32, wa_num_format, false), "");
1277
1278 formats = LLVMBuildSelect(builder, wa_8888, wa_formats, formats, "");
1279 args->resource = LLVMBuildInsertElement(
1280 builder, args->resource, formats, ctx->i32_1, "");
1281 }
1282
1283 if (target == TGSI_TEXTURE_RECT ||
1284 target == TGSI_TEXTURE_SHADOWRECT) {
1285 assert(!wa_8888);
1286 half_texel[0] = half_texel[1] = LLVMConstReal(ctx->f32, -0.5);
1287 } else {
1288 struct ac_image_args resinfo = {};
1289 struct lp_build_if_state if_ctx;
1290
1291 if (wa_8888) {
1292 /* Skip the texture size query entirely if we don't need it. */
1293 lp_build_if(&if_ctx, &ctx->gallivm, LLVMBuildNot(builder, wa_8888, ""));
1294 }
1295
1296 /* Query the texture size. */
1297 resinfo.opcode = ac_image_get_resinfo;
1298 resinfo.dim = ac_texture_dim_from_tgsi_target(ctx->screen, target);
1299 resinfo.resource = args->resource;
1300 resinfo.sampler = args->sampler;
1301 resinfo.lod = ctx->ac.i32_0;
1302 resinfo.dmask = 0xf;
1303
1304 LLVMValueRef texsize =
1305 fix_resinfo(ctx, target,
1306 ac_build_image_opcode(&ctx->ac, &resinfo));
1307
1308 /* Compute -0.5 / size. */
1309 for (unsigned c = 0; c < 2; c++) {
1310 half_texel[c] =
1311 LLVMBuildExtractElement(builder, texsize,
1312 LLVMConstInt(ctx->i32, c, 0), "");
1313 half_texel[c] = LLVMBuildUIToFP(builder, half_texel[c], ctx->f32, "");
1314 half_texel[c] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, half_texel[c]);
1315 half_texel[c] = LLVMBuildFMul(builder, half_texel[c],
1316 LLVMConstReal(ctx->f32, -0.5), "");
1317 }
1318
1319 if (wa_8888) {
1320 lp_build_endif(&if_ctx);
1321
1322 LLVMBasicBlockRef bb[2] = { if_ctx.true_block, if_ctx.entry_block };
1323
1324 for (unsigned c = 0; c < 2; c++) {
1325 LLVMValueRef values[2] = { half_texel[c], ctx->ac.f32_0 };
1326 half_texel[c] = ac_build_phi(&ctx->ac, ctx->f32, 2,
1327 values, bb);
1328 }
1329 }
1330 }
1331
1332 for (unsigned c = 0; c < 2; c++) {
1333 LLVMValueRef tmp;
1334 tmp = ac_to_float(&ctx->ac, args->coords[c]);
1335 tmp = LLVMBuildFAdd(builder, tmp, half_texel[c], "");
1336 args->coords[c] = ac_to_integer(&ctx->ac, tmp);
1337 }
1338
1339 return wa_8888;
1340 }
1341
1342 /* The second half of the cube texture 8_8_8_8 integer workaround: adjust the
1343 * result after the gather operation.
1344 */
1345 static LLVMValueRef
1346 si_fix_gather4_integer_result(struct si_shader_context *ctx,
1347 LLVMValueRef result,
1348 enum tgsi_return_type return_type,
1349 LLVMValueRef wa)
1350 {
1351 LLVMBuilderRef builder = ctx->ac.builder;
1352
1353 assert(return_type == TGSI_RETURN_TYPE_SINT ||
1354 return_type == TGSI_RETURN_TYPE_UINT);
1355
1356 for (unsigned chan = 0; chan < 4; ++chan) {
1357 LLVMValueRef chanv = LLVMConstInt(ctx->i32, chan, false);
1358 LLVMValueRef value;
1359 LLVMValueRef wa_value;
1360
1361 value = LLVMBuildExtractElement(builder, result, chanv, "");
1362
1363 if (return_type == TGSI_RETURN_TYPE_UINT)
1364 wa_value = LLVMBuildFPToUI(builder, value, ctx->i32, "");
1365 else
1366 wa_value = LLVMBuildFPToSI(builder, value, ctx->i32, "");
1367 wa_value = ac_to_float(&ctx->ac, wa_value);
1368 value = LLVMBuildSelect(builder, wa, wa_value, value, "");
1369
1370 result = LLVMBuildInsertElement(builder, result, value, chanv, "");
1371 }
1372
1373 return result;
1374 }
1375
1376 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
1377 struct lp_build_tgsi_context *bld_base,
1378 struct lp_build_emit_data *emit_data)
1379 {
1380 struct si_shader_context *ctx = si_shader_context(bld_base);
1381 const struct tgsi_full_instruction *inst = emit_data->inst;
1382 unsigned opcode = inst->Instruction.Opcode;
1383 unsigned target = inst->Texture.Texture;
1384 struct ac_image_args args = {};
1385 int ref_pos = tgsi_util_get_shadow_ref_src_index(target);
1386 unsigned chan;
1387 bool has_offset = inst->Texture.NumOffsets > 0;
1388 LLVMValueRef fmask_ptr = NULL;
1389
1390 tex_fetch_ptrs(bld_base, emit_data, &args.resource, &args.sampler, &fmask_ptr);
1391
1392 if (target == TGSI_TEXTURE_BUFFER) {
1393 LLVMValueRef vindex = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
1394 unsigned num_channels =
1395 util_last_bit(inst->Dst[0].Register.WriteMask);
1396 LLVMValueRef result =
1397 ac_build_buffer_load_format(&ctx->ac,
1398 args.resource,
1399 vindex,
1400 ctx->i32_0,
1401 num_channels, false, true);
1402 emit_data->output[emit_data->chan] =
1403 ac_build_expand_to_vec4(&ctx->ac, result, num_channels);
1404 return;
1405 }
1406
1407 /* Fetch and project texture coordinates */
1408 args.coords[3] = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_W);
1409 for (chan = 0; chan < 3; chan++) {
1410 args.coords[chan] = lp_build_emit_fetch(bld_base, inst, 0, chan);
1411 if (opcode == TGSI_OPCODE_TXP)
1412 args.coords[chan] = ac_build_fdiv(&ctx->ac,
1413 args.coords[chan], args.coords[3]);
1414 }
1415
1416 if (opcode == TGSI_OPCODE_TXP)
1417 args.coords[3] = ctx->ac.f32_1;
1418
1419 /* Pack offsets. */
1420 if (has_offset &&
1421 opcode != TGSI_OPCODE_TXF &&
1422 opcode != TGSI_OPCODE_TXF_LZ) {
1423 /* The offsets are six-bit signed integers packed like this:
1424 * X=[5:0], Y=[13:8], and Z=[21:16].
1425 */
1426 LLVMValueRef offset[3], pack;
1427
1428 assert(inst->Texture.NumOffsets == 1);
1429
1430 for (chan = 0; chan < 3; chan++) {
1431 offset[chan] = lp_build_emit_fetch_texoffset(bld_base, inst, 0, chan);
1432 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
1433 LLVMConstInt(ctx->i32, 0x3f, 0), "");
1434 if (chan)
1435 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
1436 LLVMConstInt(ctx->i32, chan*8, 0), "");
1437 }
1438
1439 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
1440 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
1441 args.offset = pack;
1442 }
1443
1444 /* Pack LOD bias value */
1445 if (opcode == TGSI_OPCODE_TXB)
1446 args.bias = args.coords[3];
1447 if (opcode == TGSI_OPCODE_TXB2)
1448 args.bias = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
1449
1450 /* Pack depth comparison value */
1451 if (tgsi_is_shadow_target(target) && opcode != TGSI_OPCODE_LODQ) {
1452 LLVMValueRef z;
1453
1454 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
1455 z = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
1456 } else {
1457 assert(ref_pos >= 0);
1458 z = args.coords[ref_pos];
1459 }
1460
1461 /* Section 8.23.1 (Depth Texture Comparison Mode) of the
1462 * OpenGL 4.5 spec says:
1463 *
1464 * "If the texture’s internal format indicates a fixed-point
1465 * depth texture, then D_t and D_ref are clamped to the
1466 * range [0, 1]; otherwise no clamping is performed."
1467 *
1468 * TC-compatible HTILE promotes Z16 and Z24 to Z32_FLOAT,
1469 * so the depth comparison value isn't clamped for Z16 and
1470 * Z24 anymore. Do it manually here.
1471 */
1472 if (ctx->screen->info.chip_class >= VI) {
1473 LLVMValueRef upgraded;
1474 LLVMValueRef clamped;
1475 upgraded = LLVMBuildExtractElement(ctx->ac.builder, args.sampler,
1476 LLVMConstInt(ctx->i32, 3, false), "");
1477 upgraded = LLVMBuildLShr(ctx->ac.builder, upgraded,
1478 LLVMConstInt(ctx->i32, 29, false), "");
1479 upgraded = LLVMBuildTrunc(ctx->ac.builder, upgraded, ctx->i1, "");
1480 clamped = ac_build_clamp(&ctx->ac, z);
1481 z = LLVMBuildSelect(ctx->ac.builder, upgraded, clamped, z, "");
1482 }
1483
1484 args.compare = z;
1485 }
1486
1487 /* Pack user derivatives */
1488 if (opcode == TGSI_OPCODE_TXD) {
1489 int param, num_src_deriv_channels, num_dst_deriv_channels;
1490
1491 switch (target) {
1492 case TGSI_TEXTURE_3D:
1493 num_src_deriv_channels = 3;
1494 num_dst_deriv_channels = 3;
1495 break;
1496 case TGSI_TEXTURE_2D:
1497 case TGSI_TEXTURE_SHADOW2D:
1498 case TGSI_TEXTURE_RECT:
1499 case TGSI_TEXTURE_SHADOWRECT:
1500 case TGSI_TEXTURE_2D_ARRAY:
1501 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1502 num_src_deriv_channels = 2;
1503 num_dst_deriv_channels = 2;
1504 break;
1505 case TGSI_TEXTURE_CUBE:
1506 case TGSI_TEXTURE_SHADOWCUBE:
1507 case TGSI_TEXTURE_CUBE_ARRAY:
1508 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
1509 /* Cube derivatives will be converted to 2D. */
1510 num_src_deriv_channels = 3;
1511 num_dst_deriv_channels = 3;
1512 break;
1513 case TGSI_TEXTURE_1D:
1514 case TGSI_TEXTURE_SHADOW1D:
1515 case TGSI_TEXTURE_1D_ARRAY:
1516 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1517 num_src_deriv_channels = 1;
1518
1519 /* 1D textures are allocated and used as 2D on GFX9. */
1520 if (ctx->screen->info.chip_class >= GFX9) {
1521 num_dst_deriv_channels = 2;
1522 } else {
1523 num_dst_deriv_channels = 1;
1524 }
1525 break;
1526 default:
1527 unreachable("invalid target");
1528 }
1529
1530 for (param = 0; param < 2; param++) {
1531 for (chan = 0; chan < num_src_deriv_channels; chan++)
1532 args.derivs[param * num_dst_deriv_channels + chan] =
1533 lp_build_emit_fetch(bld_base, inst, param+1, chan);
1534
1535 /* Fill in the rest with zeros. */
1536 for (chan = num_src_deriv_channels;
1537 chan < num_dst_deriv_channels; chan++)
1538 args.derivs[param * num_dst_deriv_channels + chan] =
1539 ctx->ac.f32_0;
1540 }
1541 }
1542
1543 if (target == TGSI_TEXTURE_CUBE ||
1544 target == TGSI_TEXTURE_CUBE_ARRAY ||
1545 target == TGSI_TEXTURE_SHADOWCUBE ||
1546 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
1547 ac_prepare_cube_coords(&ctx->ac,
1548 opcode == TGSI_OPCODE_TXD,
1549 target == TGSI_TEXTURE_CUBE_ARRAY ||
1550 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY,
1551 opcode == TGSI_OPCODE_LODQ,
1552 args.coords, args.derivs);
1553 } else if (tgsi_is_array_sampler(target) &&
1554 opcode != TGSI_OPCODE_TXF &&
1555 opcode != TGSI_OPCODE_TXF_LZ &&
1556 ctx->screen->info.chip_class <= VI) {
1557 unsigned array_coord = target == TGSI_TEXTURE_1D_ARRAY ? 1 : 2;
1558 args.coords[array_coord] =
1559 ac_build_intrinsic(&ctx->ac, "llvm.rint.f32", ctx->f32,
1560 &args.coords[array_coord], 1, 0);
1561 }
1562
1563 /* 1D textures are allocated and used as 2D on GFX9. */
1564 if (ctx->screen->info.chip_class >= GFX9) {
1565 LLVMValueRef filler;
1566
1567 /* Use 0.5, so that we don't sample the border color. */
1568 if (opcode == TGSI_OPCODE_TXF ||
1569 opcode == TGSI_OPCODE_TXF_LZ)
1570 filler = ctx->i32_0;
1571 else
1572 filler = LLVMConstReal(ctx->f32, 0.5);
1573
1574 if (target == TGSI_TEXTURE_1D ||
1575 target == TGSI_TEXTURE_SHADOW1D) {
1576 args.coords[1] = filler;
1577 } else if (target == TGSI_TEXTURE_1D_ARRAY ||
1578 target == TGSI_TEXTURE_SHADOW1D_ARRAY) {
1579 args.coords[2] = args.coords[1];
1580 args.coords[1] = filler;
1581 }
1582 }
1583
1584 /* Pack LOD or sample index */
1585 if (opcode == TGSI_OPCODE_TXL)
1586 args.lod = args.coords[3];
1587 else if (opcode == TGSI_OPCODE_TXL2)
1588 args.lod = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
1589 else if (opcode == TGSI_OPCODE_TXF) {
1590 if (target == TGSI_TEXTURE_2D_MSAA) {
1591 /* No LOD, but move sample index into the right place. */
1592 args.coords[2] = args.coords[3];
1593 } else if (target != TGSI_TEXTURE_2D_ARRAY_MSAA) {
1594 args.lod = args.coords[3];
1595 }
1596 }
1597
1598 if (target == TGSI_TEXTURE_2D_MSAA ||
1599 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
1600 ac_apply_fmask_to_sample(&ctx->ac, fmask_ptr, args.coords,
1601 target == TGSI_TEXTURE_2D_ARRAY_MSAA);
1602 }
1603
1604 if (opcode == TGSI_OPCODE_TXF ||
1605 opcode == TGSI_OPCODE_TXF_LZ) {
1606 /* add tex offsets */
1607 if (inst->Texture.NumOffsets) {
1608 const struct tgsi_texture_offset *off = inst->TexOffsets;
1609
1610 assert(inst->Texture.NumOffsets == 1);
1611
1612 switch (target) {
1613 case TGSI_TEXTURE_3D:
1614 args.coords[2] =
1615 LLVMBuildAdd(ctx->ac.builder, args.coords[2],
1616 ctx->imms[off->Index * TGSI_NUM_CHANNELS + off->SwizzleZ], "");
1617 /* fall through */
1618 case TGSI_TEXTURE_2D:
1619 case TGSI_TEXTURE_SHADOW2D:
1620 case TGSI_TEXTURE_RECT:
1621 case TGSI_TEXTURE_SHADOWRECT:
1622 case TGSI_TEXTURE_2D_ARRAY:
1623 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1624 args.coords[1] =
1625 LLVMBuildAdd(ctx->ac.builder, args.coords[1],
1626 ctx->imms[off->Index * TGSI_NUM_CHANNELS + off->SwizzleY], "");
1627 /* fall through */
1628 case TGSI_TEXTURE_1D:
1629 case TGSI_TEXTURE_SHADOW1D:
1630 case TGSI_TEXTURE_1D_ARRAY:
1631 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1632 args.coords[0] =
1633 LLVMBuildAdd(ctx->ac.builder, args.coords[0],
1634 ctx->imms[off->Index * TGSI_NUM_CHANNELS + off->SwizzleX], "");
1635 break;
1636 /* texture offsets do not apply to other texture targets */
1637 }
1638 }
1639 }
1640
1641 if (opcode == TGSI_OPCODE_TG4) {
1642 unsigned gather_comp = 0;
1643
1644 /* DMASK was repurposed for GATHER4. 4 components are always
1645 * returned and DMASK works like a swizzle - it selects
1646 * the component to fetch. The only valid DMASK values are
1647 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
1648 * (red,red,red,red) etc.) The ISA document doesn't mention
1649 * this.
1650 */
1651
1652 /* Get the component index from src1.x for Gather4. */
1653 if (!tgsi_is_shadow_target(target)) {
1654 LLVMValueRef comp_imm;
1655 struct tgsi_src_register src1 = inst->Src[1].Register;
1656
1657 assert(src1.File == TGSI_FILE_IMMEDIATE);
1658
1659 comp_imm = ctx->imms[src1.Index * TGSI_NUM_CHANNELS + src1.SwizzleX];
1660 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
1661 gather_comp = CLAMP(gather_comp, 0, 3);
1662 }
1663
1664 args.dmask = 1 << gather_comp;
1665 } else {
1666 args.dmask = 0xf;
1667 }
1668
1669 args.dim = ac_texture_dim_from_tgsi_target(ctx->screen, target);
1670 args.unorm = target == TGSI_TEXTURE_RECT ||
1671 target == TGSI_TEXTURE_SHADOWRECT;
1672 args.opcode = ac_image_sample;
1673
1674 switch (opcode) {
1675 case TGSI_OPCODE_TXF:
1676 case TGSI_OPCODE_TXF_LZ:
1677 args.opcode = opcode == TGSI_OPCODE_TXF_LZ ||
1678 target == TGSI_TEXTURE_2D_MSAA ||
1679 target == TGSI_TEXTURE_2D_ARRAY_MSAA ?
1680 ac_image_load : ac_image_load_mip;
1681 break;
1682 case TGSI_OPCODE_LODQ:
1683 args.opcode = ac_image_get_lod;
1684 break;
1685 case TGSI_OPCODE_TEX:
1686 case TGSI_OPCODE_TEX2:
1687 case TGSI_OPCODE_TXP:
1688 if (ctx->type != PIPE_SHADER_FRAGMENT)
1689 args.level_zero = true;
1690 break;
1691 case TGSI_OPCODE_TEX_LZ:
1692 args.level_zero = true;
1693 break;
1694 case TGSI_OPCODE_TXB:
1695 case TGSI_OPCODE_TXB2:
1696 assert(ctx->type == PIPE_SHADER_FRAGMENT);
1697 break;
1698 case TGSI_OPCODE_TXL:
1699 case TGSI_OPCODE_TXL2:
1700 break;
1701 case TGSI_OPCODE_TXD:
1702 break;
1703 case TGSI_OPCODE_TG4:
1704 args.opcode = ac_image_gather4;
1705 args.level_zero = true;
1706 break;
1707 default:
1708 assert(0);
1709 return;
1710 }
1711
1712 /* The hardware needs special lowering for Gather4 with integer formats. */
1713 LLVMValueRef gather4_int_result_workaround = NULL;
1714
1715 if (ctx->screen->info.chip_class <= VI &&
1716 opcode == TGSI_OPCODE_TG4) {
1717 assert(inst->Texture.ReturnType != TGSI_RETURN_TYPE_UNKNOWN);
1718
1719 if (inst->Texture.ReturnType == TGSI_RETURN_TYPE_SINT ||
1720 inst->Texture.ReturnType == TGSI_RETURN_TYPE_UINT) {
1721 gather4_int_result_workaround =
1722 si_lower_gather4_integer(ctx, &args, target,
1723 inst->Texture.ReturnType);
1724 }
1725 }
1726
1727 args.attributes = AC_FUNC_ATTR_READNONE;
1728 LLVMValueRef result = ac_build_image_opcode(&ctx->ac, &args);
1729
1730 if (gather4_int_result_workaround) {
1731 result = si_fix_gather4_integer_result(ctx, result,
1732 inst->Texture.ReturnType,
1733 gather4_int_result_workaround);
1734 }
1735
1736 emit_data->output[emit_data->chan] = result;
1737 }
1738
1739 static void si_llvm_emit_txqs(
1740 const struct lp_build_tgsi_action *action,
1741 struct lp_build_tgsi_context *bld_base,
1742 struct lp_build_emit_data *emit_data)
1743 {
1744 struct si_shader_context *ctx = si_shader_context(bld_base);
1745 LLVMValueRef res, samples;
1746 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
1747
1748 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
1749
1750 /* Read the samples from the descriptor directly. */
1751 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->v8i32, "");
1752 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
1753 LLVMConstInt(ctx->i32, 3, 0), "");
1754 samples = LLVMBuildLShr(ctx->ac.builder, samples,
1755 LLVMConstInt(ctx->i32, 16, 0), "");
1756 samples = LLVMBuildAnd(ctx->ac.builder, samples,
1757 LLVMConstInt(ctx->i32, 0xf, 0), "");
1758 samples = LLVMBuildShl(ctx->ac.builder, ctx->i32_1,
1759 samples, "");
1760
1761 emit_data->output[emit_data->chan] = samples;
1762 }
1763
1764 static void si_llvm_emit_fbfetch(const struct lp_build_tgsi_action *action,
1765 struct lp_build_tgsi_context *bld_base,
1766 struct lp_build_emit_data *emit_data)
1767 {
1768 struct si_shader_context *ctx = si_shader_context(bld_base);
1769 struct ac_image_args args = {};
1770 LLVMValueRef ptr, image, fmask;
1771
1772 /* Ignore src0, because KHR_blend_func_extended disallows multiple render
1773 * targets.
1774 */
1775
1776 /* Load the image descriptor. */
1777 STATIC_ASSERT(SI_PS_IMAGE_COLORBUF0 % 2 == 0);
1778 ptr = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
1779 ptr = LLVMBuildPointerCast(ctx->ac.builder, ptr,
1780 ac_array_in_const32_addr_space(ctx->v8i32), "");
1781 image = ac_build_load_to_sgpr(&ctx->ac, ptr,
1782 LLVMConstInt(ctx->i32, SI_PS_IMAGE_COLORBUF0 / 2, 0));
1783
1784 unsigned chan = 0;
1785
1786 args.coords[chan++] = si_unpack_param(ctx, SI_PARAM_POS_FIXED_PT, 0, 16);
1787
1788 if (!ctx->shader->key.mono.u.ps.fbfetch_is_1D)
1789 args.coords[chan++] = si_unpack_param(ctx, SI_PARAM_POS_FIXED_PT, 16, 16);
1790
1791 /* Get the current render target layer index. */
1792 if (ctx->shader->key.mono.u.ps.fbfetch_layered)
1793 args.coords[chan++] = si_unpack_param(ctx, SI_PARAM_ANCILLARY, 16, 11);
1794
1795 if (ctx->shader->key.mono.u.ps.fbfetch_msaa)
1796 args.coords[chan++] = si_get_sample_id(ctx);
1797
1798 if (ctx->shader->key.mono.u.ps.fbfetch_msaa) {
1799 fmask = ac_build_load_to_sgpr(&ctx->ac, ptr,
1800 LLVMConstInt(ctx->i32, SI_PS_IMAGE_COLORBUF0_FMASK / 2, 0));
1801
1802 ac_apply_fmask_to_sample(&ctx->ac, fmask, args.coords,
1803 ctx->shader->key.mono.u.ps.fbfetch_layered);
1804 }
1805
1806 args.opcode = ac_image_load;
1807 args.resource = image;
1808 args.dmask = 0xf;
1809 if (ctx->shader->key.mono.u.ps.fbfetch_msaa)
1810 args.dim = ctx->shader->key.mono.u.ps.fbfetch_layered ?
1811 ac_image_2darraymsaa : ac_image_2dmsaa;
1812 else if (ctx->shader->key.mono.u.ps.fbfetch_is_1D)
1813 args.dim = ctx->shader->key.mono.u.ps.fbfetch_layered ?
1814 ac_image_1darray : ac_image_1d;
1815 else
1816 args.dim = ctx->shader->key.mono.u.ps.fbfetch_layered ?
1817 ac_image_2darray : ac_image_2d;
1818
1819 emit_data->output[emit_data->chan] =
1820 ac_build_image_opcode(&ctx->ac, &args);
1821 }
1822
1823 /**
1824 * Setup actions for TGSI memory opcode, including texture opcodes.
1825 */
1826 void si_shader_context_init_mem(struct si_shader_context *ctx)
1827 {
1828 struct lp_build_tgsi_context *bld_base;
1829 struct lp_build_tgsi_action tmpl = {};
1830
1831 bld_base = &ctx->bld_base;
1832
1833 bld_base->op_actions[TGSI_OPCODE_TEX].emit = build_tex_intrinsic;
1834 bld_base->op_actions[TGSI_OPCODE_TEX_LZ].emit = build_tex_intrinsic;
1835 bld_base->op_actions[TGSI_OPCODE_TEX2].emit = build_tex_intrinsic;
1836 bld_base->op_actions[TGSI_OPCODE_TXB].emit = build_tex_intrinsic;
1837 bld_base->op_actions[TGSI_OPCODE_TXB2].emit = build_tex_intrinsic;
1838 bld_base->op_actions[TGSI_OPCODE_TXD].emit = build_tex_intrinsic;
1839 bld_base->op_actions[TGSI_OPCODE_TXF].emit = build_tex_intrinsic;
1840 bld_base->op_actions[TGSI_OPCODE_TXF_LZ].emit = build_tex_intrinsic;
1841 bld_base->op_actions[TGSI_OPCODE_TXL].emit = build_tex_intrinsic;
1842 bld_base->op_actions[TGSI_OPCODE_TXL2].emit = build_tex_intrinsic;
1843 bld_base->op_actions[TGSI_OPCODE_TXP].emit = build_tex_intrinsic;
1844 bld_base->op_actions[TGSI_OPCODE_TXQ].emit = txq_emit;
1845 bld_base->op_actions[TGSI_OPCODE_TG4].emit = build_tex_intrinsic;
1846 bld_base->op_actions[TGSI_OPCODE_LODQ].emit = build_tex_intrinsic;
1847 bld_base->op_actions[TGSI_OPCODE_TXQS].emit = si_llvm_emit_txqs;
1848
1849 bld_base->op_actions[TGSI_OPCODE_FBFETCH].emit = si_llvm_emit_fbfetch;
1850
1851 bld_base->op_actions[TGSI_OPCODE_LOAD].fetch_args = load_fetch_args;
1852 bld_base->op_actions[TGSI_OPCODE_LOAD].emit = load_emit;
1853 bld_base->op_actions[TGSI_OPCODE_STORE].fetch_args = store_fetch_args;
1854 bld_base->op_actions[TGSI_OPCODE_STORE].emit = store_emit;
1855 bld_base->op_actions[TGSI_OPCODE_RESQ].emit = resq_emit;
1856
1857 tmpl.fetch_args = atomic_fetch_args;
1858 tmpl.emit = atomic_emit;
1859 bld_base->op_actions[TGSI_OPCODE_ATOMUADD] = tmpl;
1860 bld_base->op_actions[TGSI_OPCODE_ATOMUADD].intr_name = "add";
1861 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG] = tmpl;
1862 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG].intr_name = "swap";
1863 bld_base->op_actions[TGSI_OPCODE_ATOMCAS] = tmpl;
1864 bld_base->op_actions[TGSI_OPCODE_ATOMCAS].intr_name = "cmpswap";
1865 bld_base->op_actions[TGSI_OPCODE_ATOMAND] = tmpl;
1866 bld_base->op_actions[TGSI_OPCODE_ATOMAND].intr_name = "and";
1867 bld_base->op_actions[TGSI_OPCODE_ATOMOR] = tmpl;
1868 bld_base->op_actions[TGSI_OPCODE_ATOMOR].intr_name = "or";
1869 bld_base->op_actions[TGSI_OPCODE_ATOMXOR] = tmpl;
1870 bld_base->op_actions[TGSI_OPCODE_ATOMXOR].intr_name = "xor";
1871 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN] = tmpl;
1872 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN].intr_name = "umin";
1873 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX] = tmpl;
1874 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX].intr_name = "umax";
1875 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN] = tmpl;
1876 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN].intr_name = "smin";
1877 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX] = tmpl;
1878 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX].intr_name = "smax";
1879 }