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radeonsi: don't use emit_data->args in atomic_emit
[mesa.git] / src / gallium / drivers / radeonsi / si_shader_tgsi_mem.c
1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_shader_internal.h"
26 #include "si_pipe.h"
27 #include "sid.h"
28 #include "tgsi/tgsi_build.h"
29 #include "tgsi/tgsi_util.h"
30 #include "ac_llvm_util.h"
31
32 static void tex_fetch_ptrs(struct lp_build_tgsi_context *bld_base,
33 struct lp_build_emit_data *emit_data,
34 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
35 LLVMValueRef *fmask_ptr);
36
37 /**
38 * Given a v8i32 resource descriptor for a buffer, extract the size of the
39 * buffer in number of elements and return it as an i32.
40 */
41 static LLVMValueRef get_buffer_size(
42 struct lp_build_tgsi_context *bld_base,
43 LLVMValueRef descriptor)
44 {
45 struct si_shader_context *ctx = si_shader_context(bld_base);
46 LLVMBuilderRef builder = ctx->ac.builder;
47 LLVMValueRef size =
48 LLVMBuildExtractElement(builder, descriptor,
49 LLVMConstInt(ctx->i32, 2, 0), "");
50
51 if (ctx->screen->info.chip_class == VI) {
52 /* On VI, the descriptor contains the size in bytes,
53 * but TXQ must return the size in elements.
54 * The stride is always non-zero for resources using TXQ.
55 */
56 LLVMValueRef stride =
57 LLVMBuildExtractElement(builder, descriptor,
58 ctx->i32_1, "");
59 stride = LLVMBuildLShr(builder, stride,
60 LLVMConstInt(ctx->i32, 16, 0), "");
61 stride = LLVMBuildAnd(builder, stride,
62 LLVMConstInt(ctx->i32, 0x3FFF, 0), "");
63
64 size = LLVMBuildUDiv(builder, size, stride, "");
65 }
66
67 return size;
68 }
69
70 static LLVMValueRef
71 shader_buffer_fetch_rsrc(struct si_shader_context *ctx,
72 const struct tgsi_full_src_register *reg,
73 bool ubo)
74 {
75 LLVMValueRef index;
76
77 if (!reg->Register.Indirect) {
78 index = LLVMConstInt(ctx->i32, reg->Register.Index, false);
79 } else {
80 index = si_get_indirect_index(ctx, &reg->Indirect,
81 1, reg->Register.Index);
82 }
83
84 if (ubo)
85 return ctx->abi.load_ubo(&ctx->abi, index);
86 else
87 return ctx->abi.load_ssbo(&ctx->abi, index, false);
88 }
89
90 static enum ac_image_dim
91 ac_texture_dim_from_tgsi_target(struct si_screen *screen, enum tgsi_texture_type target)
92 {
93 switch (target) {
94 case TGSI_TEXTURE_1D:
95 case TGSI_TEXTURE_SHADOW1D:
96 if (screen->info.chip_class >= GFX9)
97 return ac_image_2d;
98 return ac_image_1d;
99 case TGSI_TEXTURE_2D:
100 case TGSI_TEXTURE_SHADOW2D:
101 case TGSI_TEXTURE_RECT:
102 case TGSI_TEXTURE_SHADOWRECT:
103 return ac_image_2d;
104 case TGSI_TEXTURE_3D:
105 return ac_image_3d;
106 case TGSI_TEXTURE_CUBE:
107 case TGSI_TEXTURE_SHADOWCUBE:
108 case TGSI_TEXTURE_CUBE_ARRAY:
109 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
110 return ac_image_cube;
111 case TGSI_TEXTURE_1D_ARRAY:
112 case TGSI_TEXTURE_SHADOW1D_ARRAY:
113 if (screen->info.chip_class >= GFX9)
114 return ac_image_2darray;
115 return ac_image_1darray;
116 case TGSI_TEXTURE_2D_ARRAY:
117 case TGSI_TEXTURE_SHADOW2D_ARRAY:
118 return ac_image_2darray;
119 case TGSI_TEXTURE_2D_MSAA:
120 return ac_image_2dmsaa;
121 case TGSI_TEXTURE_2D_ARRAY_MSAA:
122 return ac_image_2darraymsaa;
123 default:
124 unreachable("unhandled texture type");
125 }
126 }
127
128 static enum ac_image_dim
129 ac_image_dim_from_tgsi_target(struct si_screen *screen, enum tgsi_texture_type target)
130 {
131 enum ac_image_dim dim = ac_texture_dim_from_tgsi_target(screen, target);
132
133 /* Match the resource type set in the descriptor. */
134 if (dim == ac_image_cube ||
135 (screen->info.chip_class <= VI && dim == ac_image_3d))
136 dim = ac_image_2darray;
137 else if (target == TGSI_TEXTURE_2D && screen->info.chip_class >= GFX9) {
138 /* When a single layer of a 3D texture is bound, the shader
139 * will refer to a 2D target, but the descriptor has a 3D type.
140 * Since the HW ignores BASE_ARRAY in this case, we need to
141 * send 3 coordinates. This doesn't hurt when the underlying
142 * texture is non-3D.
143 */
144 dim = ac_image_3d;
145 }
146
147 return dim;
148 }
149
150 /**
151 * Given a 256-bit resource descriptor, force the DCC enable bit to off.
152 *
153 * At least on Tonga, executing image stores on images with DCC enabled and
154 * non-trivial can eventually lead to lockups. This can occur when an
155 * application binds an image as read-only but then uses a shader that writes
156 * to it. The OpenGL spec allows almost arbitrarily bad behavior (including
157 * program termination) in this case, but it doesn't cost much to be a bit
158 * nicer: disabling DCC in the shader still leads to undefined results but
159 * avoids the lockup.
160 */
161 static LLVMValueRef force_dcc_off(struct si_shader_context *ctx,
162 LLVMValueRef rsrc)
163 {
164 if (ctx->screen->info.chip_class <= CIK) {
165 return rsrc;
166 } else {
167 LLVMValueRef i32_6 = LLVMConstInt(ctx->i32, 6, 0);
168 LLVMValueRef i32_C = LLVMConstInt(ctx->i32, C_008F28_COMPRESSION_EN, 0);
169 LLVMValueRef tmp;
170
171 tmp = LLVMBuildExtractElement(ctx->ac.builder, rsrc, i32_6, "");
172 tmp = LLVMBuildAnd(ctx->ac.builder, tmp, i32_C, "");
173 return LLVMBuildInsertElement(ctx->ac.builder, rsrc, tmp, i32_6, "");
174 }
175 }
176
177 LLVMValueRef si_load_image_desc(struct si_shader_context *ctx,
178 LLVMValueRef list, LLVMValueRef index,
179 enum ac_descriptor_type desc_type, bool dcc_off)
180 {
181 LLVMBuilderRef builder = ctx->ac.builder;
182 LLVMValueRef rsrc;
183
184 if (desc_type == AC_DESC_BUFFER) {
185 index = LLVMBuildMul(builder, index,
186 LLVMConstInt(ctx->i32, 2, 0), "");
187 index = LLVMBuildAdd(builder, index,
188 ctx->i32_1, "");
189 list = LLVMBuildPointerCast(builder, list,
190 ac_array_in_const32_addr_space(ctx->v4i32), "");
191 } else {
192 assert(desc_type == AC_DESC_IMAGE);
193 }
194
195 rsrc = ac_build_load_to_sgpr(&ctx->ac, list, index);
196 if (desc_type == AC_DESC_IMAGE && dcc_off)
197 rsrc = force_dcc_off(ctx, rsrc);
198 return rsrc;
199 }
200
201 /**
202 * Load the resource descriptor for \p image.
203 */
204 static void
205 image_fetch_rsrc(
206 struct lp_build_tgsi_context *bld_base,
207 const struct tgsi_full_src_register *image,
208 bool is_store, unsigned target,
209 LLVMValueRef *rsrc)
210 {
211 struct si_shader_context *ctx = si_shader_context(bld_base);
212 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
213 ctx->param_samplers_and_images);
214 LLVMValueRef index;
215 bool dcc_off = is_store;
216
217 if (!image->Register.Indirect) {
218 const struct tgsi_shader_info *info = bld_base->info;
219 unsigned images_writemask = info->images_store |
220 info->images_atomic;
221
222 index = LLVMConstInt(ctx->i32,
223 si_get_image_slot(image->Register.Index), 0);
224
225 if (images_writemask & (1 << image->Register.Index))
226 dcc_off = true;
227 } else {
228 /* From the GL_ARB_shader_image_load_store extension spec:
229 *
230 * If a shader performs an image load, store, or atomic
231 * operation using an image variable declared as an array,
232 * and if the index used to select an individual element is
233 * negative or greater than or equal to the size of the
234 * array, the results of the operation are undefined but may
235 * not lead to termination.
236 */
237 index = si_get_bounded_indirect_index(ctx, &image->Indirect,
238 image->Register.Index,
239 ctx->num_images);
240 index = LLVMBuildSub(ctx->ac.builder,
241 LLVMConstInt(ctx->i32, SI_NUM_IMAGES - 1, 0),
242 index, "");
243 }
244
245 if (image->Register.File != TGSI_FILE_IMAGE) {
246 /* Bindless descriptors are accessible from a different pair of
247 * user SGPR indices.
248 */
249 rsrc_ptr = LLVMGetParam(ctx->main_fn,
250 ctx->param_bindless_samplers_and_images);
251 index = lp_build_emit_fetch_src(bld_base, image,
252 TGSI_TYPE_UNSIGNED, 0);
253
254 /* For simplicity, bindless image descriptors use fixed
255 * 16-dword slots for now.
256 */
257 index = LLVMBuildMul(ctx->ac.builder, index,
258 LLVMConstInt(ctx->i32, 2, 0), "");
259 }
260
261 *rsrc = si_load_image_desc(ctx, rsrc_ptr, index,
262 target == TGSI_TEXTURE_BUFFER ? AC_DESC_BUFFER : AC_DESC_IMAGE,
263 dcc_off);
264 }
265
266 static void image_fetch_coords(
267 struct lp_build_tgsi_context *bld_base,
268 const struct tgsi_full_instruction *inst,
269 unsigned src, LLVMValueRef desc,
270 LLVMValueRef *coords)
271 {
272 struct si_shader_context *ctx = si_shader_context(bld_base);
273 LLVMBuilderRef builder = ctx->ac.builder;
274 unsigned target = inst->Memory.Texture;
275 unsigned num_coords = tgsi_util_get_texture_coord_dim(target);
276 LLVMValueRef tmp;
277 int chan;
278
279 if (target == TGSI_TEXTURE_2D_MSAA ||
280 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
281 /* Need the sample index as well. */
282 num_coords++;
283 }
284
285 for (chan = 0; chan < num_coords; ++chan) {
286 tmp = lp_build_emit_fetch(bld_base, inst, src, chan);
287 tmp = ac_to_integer(&ctx->ac, tmp);
288 coords[chan] = tmp;
289 }
290
291 if (ctx->screen->info.chip_class >= GFX9) {
292 /* 1D textures are allocated and used as 2D on GFX9. */
293 if (target == TGSI_TEXTURE_1D) {
294 coords[1] = ctx->i32_0;
295 } else if (target == TGSI_TEXTURE_1D_ARRAY) {
296 coords[2] = coords[1];
297 coords[1] = ctx->i32_0;
298 } else if (target == TGSI_TEXTURE_2D) {
299 /* The hw can't bind a slice of a 3D image as a 2D
300 * image, because it ignores BASE_ARRAY if the target
301 * is 3D. The workaround is to read BASE_ARRAY and set
302 * it as the 3rd address operand for all 2D images.
303 */
304 LLVMValueRef first_layer, const5, mask;
305
306 const5 = LLVMConstInt(ctx->i32, 5, 0);
307 mask = LLVMConstInt(ctx->i32, S_008F24_BASE_ARRAY(~0), 0);
308 first_layer = LLVMBuildExtractElement(builder, desc, const5, "");
309 first_layer = LLVMBuildAnd(builder, first_layer, mask, "");
310
311 coords[2] = first_layer;
312 }
313 }
314 }
315
316 /**
317 * Append the resource and indexing arguments for buffer intrinsics.
318 *
319 * \param rsrc the v4i32 buffer resource
320 * \param index index into the buffer (stride-based)
321 * \param offset byte offset into the buffer
322 */
323 static void buffer_append_args(
324 struct si_shader_context *ctx,
325 struct lp_build_emit_data *emit_data,
326 LLVMValueRef rsrc,
327 LLVMValueRef index,
328 LLVMValueRef offset,
329 bool atomic,
330 bool force_glc)
331 {
332 const struct tgsi_full_instruction *inst = emit_data->inst;
333 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
334 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
335
336 emit_data->args[emit_data->arg_count++] = rsrc;
337 emit_data->args[emit_data->arg_count++] = index; /* vindex */
338 emit_data->args[emit_data->arg_count++] = offset; /* voffset */
339 if (!atomic) {
340 emit_data->args[emit_data->arg_count++] =
341 force_glc ||
342 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE) ?
343 i1true : i1false; /* glc */
344 }
345 emit_data->args[emit_data->arg_count++] = i1false; /* slc */
346 }
347
348 static unsigned get_cache_policy(struct si_shader_context *ctx,
349 const struct tgsi_full_instruction *inst,
350 bool atomic, bool force_glc)
351 {
352 unsigned cache_policy = 0;
353
354 if (!atomic &&
355 (force_glc ||
356 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE)))
357 cache_policy |= ac_glc;
358
359 return cache_policy;
360 }
361
362 static void load_emit_buffer(struct si_shader_context *ctx,
363 struct lp_build_emit_data *emit_data,
364 bool can_speculate, bool allow_smem)
365 {
366 const struct tgsi_full_instruction *inst = emit_data->inst;
367 uint writemask = inst->Dst[0].Register.WriteMask;
368 uint count = util_last_bit(writemask);
369 LLVMValueRef *args = emit_data->args;
370
371 /* Don't use SMEM for shader buffer loads, because LLVM doesn't
372 * select SMEM for SI.load.const with a non-constant offset, and
373 * constant offsets practically don't exist with shader buffers.
374 *
375 * Also, SI.load.const doesn't use inst_offset when it's lowered
376 * to VMEM, so we just end up with more VALU instructions in the end
377 * and no benefit.
378 *
379 * TODO: Remove this line once LLVM can select SMEM with a non-constant
380 * offset, and can derive inst_offset when VMEM is selected.
381 * After that, si_memory_barrier should invalidate sL1 for shader
382 * buffers.
383 */
384
385 assert(LLVMConstIntGetZExtValue(args[1]) == 0); /* vindex */
386 emit_data->output[emit_data->chan] =
387 ac_build_buffer_load(&ctx->ac, args[0], count, NULL,
388 args[2], NULL, 0,
389 LLVMConstIntGetZExtValue(args[3]),
390 LLVMConstIntGetZExtValue(args[4]),
391 can_speculate, allow_smem);
392 }
393
394 static LLVMValueRef get_memory_ptr(struct si_shader_context *ctx,
395 const struct tgsi_full_instruction *inst,
396 LLVMTypeRef type, int arg)
397 {
398 LLVMBuilderRef builder = ctx->ac.builder;
399 LLVMValueRef offset, ptr;
400 int addr_space;
401
402 offset = lp_build_emit_fetch(&ctx->bld_base, inst, arg, 0);
403 offset = ac_to_integer(&ctx->ac, offset);
404
405 ptr = ctx->ac.lds;
406 ptr = LLVMBuildGEP(builder, ptr, &offset, 1, "");
407 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
408 ptr = LLVMBuildBitCast(builder, ptr, LLVMPointerType(type, addr_space), "");
409
410 return ptr;
411 }
412
413 static void load_emit_memory(
414 struct si_shader_context *ctx,
415 struct lp_build_emit_data *emit_data)
416 {
417 const struct tgsi_full_instruction *inst = emit_data->inst;
418 unsigned writemask = inst->Dst[0].Register.WriteMask;
419 LLVMValueRef channels[4], ptr, derived_ptr, index;
420 int chan;
421
422 ptr = get_memory_ptr(ctx, inst, ctx->f32, 1);
423
424 for (chan = 0; chan < 4; ++chan) {
425 if (!(writemask & (1 << chan))) {
426 channels[chan] = LLVMGetUndef(ctx->f32);
427 continue;
428 }
429
430 index = LLVMConstInt(ctx->i32, chan, 0);
431 derived_ptr = LLVMBuildGEP(ctx->ac.builder, ptr, &index, 1, "");
432 channels[chan] = LLVMBuildLoad(ctx->ac.builder, derived_ptr, "");
433 }
434 emit_data->output[emit_data->chan] = ac_build_gather_values(&ctx->ac, channels, 4);
435 }
436
437 /**
438 * Return true if the memory accessed by a LOAD or STORE instruction is
439 * read-only or write-only, respectively.
440 *
441 * \param shader_buffers_reverse_access_mask
442 * For LOAD, set this to (store | atomic) slot usage in the shader.
443 * For STORE, set this to (load | atomic) slot usage in the shader.
444 * \param images_reverse_access_mask Same as above, but for images.
445 */
446 static bool is_oneway_access_only(const struct tgsi_full_instruction *inst,
447 const struct tgsi_shader_info *info,
448 unsigned shader_buffers_reverse_access_mask,
449 unsigned images_reverse_access_mask)
450 {
451 /* RESTRICT means NOALIAS.
452 * If there are no writes, we can assume the accessed memory is read-only.
453 * If there are no reads, we can assume the accessed memory is write-only.
454 */
455 if (inst->Memory.Qualifier & TGSI_MEMORY_RESTRICT) {
456 unsigned reverse_access_mask;
457
458 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
459 reverse_access_mask = shader_buffers_reverse_access_mask;
460 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
461 reverse_access_mask = info->images_buffers &
462 images_reverse_access_mask;
463 } else {
464 reverse_access_mask = ~info->images_buffers &
465 images_reverse_access_mask;
466 }
467
468 if (inst->Src[0].Register.Indirect) {
469 if (!reverse_access_mask)
470 return true;
471 } else {
472 if (!(reverse_access_mask &
473 (1u << inst->Src[0].Register.Index)))
474 return true;
475 }
476 }
477
478 /* If there are no buffer writes (for both shader buffers & image
479 * buffers), it implies that buffer memory is read-only.
480 * If there are no buffer reads (for both shader buffers & image
481 * buffers), it implies that buffer memory is write-only.
482 *
483 * Same for the case when there are no writes/reads for non-buffer
484 * images.
485 */
486 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
487 (inst->Memory.Texture == TGSI_TEXTURE_BUFFER &&
488 (inst->Src[0].Register.File == TGSI_FILE_IMAGE ||
489 tgsi_is_bindless_image_file(inst->Src[0].Register.File)))) {
490 if (!shader_buffers_reverse_access_mask &&
491 !(info->images_buffers & images_reverse_access_mask))
492 return true;
493 } else {
494 if (!(~info->images_buffers & images_reverse_access_mask))
495 return true;
496 }
497 return false;
498 }
499
500 static void load_emit(
501 const struct lp_build_tgsi_action *action,
502 struct lp_build_tgsi_context *bld_base,
503 struct lp_build_emit_data *emit_data)
504 {
505 struct si_shader_context *ctx = si_shader_context(bld_base);
506 const struct tgsi_full_instruction * inst = emit_data->inst;
507 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
508 bool can_speculate = false;
509
510 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
511 load_emit_memory(ctx, emit_data);
512 return;
513 }
514
515 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
516 inst->Src[0].Register.File == TGSI_FILE_CONSTBUF) {
517 LLVMValueRef offset, tmp, rsrc;
518
519 bool ubo = inst->Src[0].Register.File == TGSI_FILE_CONSTBUF;
520 rsrc = shader_buffer_fetch_rsrc(ctx, &inst->Src[0], ubo);
521
522 tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
523 offset = ac_to_integer(&ctx->ac, tmp);
524
525 buffer_append_args(ctx, emit_data, rsrc, ctx->i32_0,
526 offset, false, false);
527 } else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE ||
528 tgsi_is_bindless_image_file(inst->Src[0].Register.File)) {
529 LLVMValueRef rsrc;
530 unsigned target = inst->Memory.Texture;
531
532 image_fetch_rsrc(bld_base, &inst->Src[0], false, target, &rsrc);
533 image_fetch_coords(bld_base, inst, 1, rsrc, &emit_data->args[1]);
534
535 if (target == TGSI_TEXTURE_BUFFER) {
536 buffer_append_args(ctx, emit_data, rsrc, emit_data->args[1],
537 ctx->i32_0, false, false);
538 } else {
539 emit_data->args[0] = rsrc;
540 }
541 }
542
543 if (inst->Src[0].Register.File == TGSI_FILE_CONSTBUF) {
544 load_emit_buffer(ctx, emit_data, true, true);
545 return;
546 }
547
548 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
549 ac_build_waitcnt(&ctx->ac, VM_CNT);
550
551 can_speculate = !(inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE) &&
552 is_oneway_access_only(inst, info,
553 info->shader_buffers_store |
554 info->shader_buffers_atomic,
555 info->images_store |
556 info->images_atomic);
557
558 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
559 load_emit_buffer(ctx, emit_data, can_speculate, false);
560 return;
561 }
562
563 if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
564 unsigned num_channels = util_last_bit(inst->Dst[0].Register.WriteMask);
565 LLVMValueRef result =
566 ac_build_buffer_load_format(&ctx->ac,
567 emit_data->args[0],
568 emit_data->args[1],
569 emit_data->args[2],
570 num_channels,
571 LLVMConstIntGetZExtValue(emit_data->args[3]),
572 can_speculate);
573 emit_data->output[emit_data->chan] =
574 ac_build_expand_to_vec4(&ctx->ac, result, num_channels);
575 } else {
576 struct ac_image_args args = {};
577 args.opcode = ac_image_load;
578 args.resource = emit_data->args[0];
579 memcpy(args.coords, &emit_data->args[1], sizeof(args.coords));
580 args.dim = ac_image_dim_from_tgsi_target(ctx->screen, inst->Memory.Texture);
581 if (inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE))
582 args.cache_policy = ac_glc;
583 args.attributes = ac_get_load_intr_attribs(can_speculate);
584 args.dmask = 0xf;
585
586 emit_data->output[emit_data->chan] =
587 ac_build_image_opcode(&ctx->ac, &args);
588 }
589 }
590
591 static void store_emit_buffer(
592 struct si_shader_context *ctx,
593 struct lp_build_emit_data *emit_data,
594 bool writeonly_memory)
595 {
596 const struct tgsi_full_instruction *inst = emit_data->inst;
597 LLVMBuilderRef builder = ctx->ac.builder;
598 LLVMValueRef base_data = emit_data->args[0];
599 LLVMValueRef base_offset = emit_data->args[3];
600 unsigned writemask = inst->Dst[0].Register.WriteMask;
601
602 /* If this is write-only, don't keep data in L1 to prevent
603 * evicting L1 cache lines that may be needed by other
604 * instructions.
605 */
606 if (writeonly_memory)
607 emit_data->args[4] = LLVMConstInt(ctx->i1, 1, 0); /* GLC = 1 */
608
609 while (writemask) {
610 int start, count;
611 const char *intrinsic_name;
612 LLVMValueRef data;
613 LLVMValueRef offset;
614 LLVMValueRef tmp;
615
616 u_bit_scan_consecutive_range(&writemask, &start, &count);
617
618 /* Due to an LLVM limitation, split 3-element writes
619 * into a 2-element and a 1-element write. */
620 if (count == 3) {
621 writemask |= 1 << (start + 2);
622 count = 2;
623 }
624
625 if (count == 4) {
626 data = base_data;
627 intrinsic_name = "llvm.amdgcn.buffer.store.v4f32";
628 } else if (count == 2) {
629 LLVMTypeRef v2f32 = LLVMVectorType(ctx->f32, 2);
630
631 tmp = LLVMBuildExtractElement(
632 builder, base_data,
633 LLVMConstInt(ctx->i32, start, 0), "");
634 data = LLVMBuildInsertElement(
635 builder, LLVMGetUndef(v2f32), tmp,
636 ctx->i32_0, "");
637
638 tmp = LLVMBuildExtractElement(
639 builder, base_data,
640 LLVMConstInt(ctx->i32, start + 1, 0), "");
641 data = LLVMBuildInsertElement(
642 builder, data, tmp, ctx->i32_1, "");
643
644 intrinsic_name = "llvm.amdgcn.buffer.store.v2f32";
645 } else {
646 assert(count == 1);
647 data = LLVMBuildExtractElement(
648 builder, base_data,
649 LLVMConstInt(ctx->i32, start, 0), "");
650 intrinsic_name = "llvm.amdgcn.buffer.store.f32";
651 }
652
653 offset = base_offset;
654 if (start != 0) {
655 offset = LLVMBuildAdd(
656 builder, offset,
657 LLVMConstInt(ctx->i32, start * 4, 0), "");
658 }
659
660 emit_data->args[0] = data;
661 emit_data->args[3] = offset;
662
663 ac_build_intrinsic(
664 &ctx->ac, intrinsic_name, ctx->voidt,
665 emit_data->args, emit_data->arg_count,
666 ac_get_store_intr_attribs(writeonly_memory));
667 }
668 }
669
670 static void store_emit_memory(
671 struct si_shader_context *ctx,
672 struct lp_build_emit_data *emit_data)
673 {
674 const struct tgsi_full_instruction *inst = emit_data->inst;
675 LLVMBuilderRef builder = ctx->ac.builder;
676 unsigned writemask = inst->Dst[0].Register.WriteMask;
677 LLVMValueRef ptr, derived_ptr, data, index;
678 int chan;
679
680 ptr = get_memory_ptr(ctx, inst, ctx->f32, 0);
681
682 for (chan = 0; chan < 4; ++chan) {
683 if (!(writemask & (1 << chan))) {
684 continue;
685 }
686 data = lp_build_emit_fetch(&ctx->bld_base, inst, 1, chan);
687 index = LLVMConstInt(ctx->i32, chan, 0);
688 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
689 LLVMBuildStore(builder, data, derived_ptr);
690 }
691 }
692
693 static void store_emit(
694 const struct lp_build_tgsi_action *action,
695 struct lp_build_tgsi_context *bld_base,
696 struct lp_build_emit_data *emit_data)
697 {
698 struct si_shader_context *ctx = si_shader_context(bld_base);
699 const struct tgsi_full_instruction * inst = emit_data->inst;
700 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
701 struct tgsi_full_src_register resource_reg =
702 tgsi_full_src_register_from_dst(&inst->Dst[0]);
703 unsigned target = inst->Memory.Texture;
704 bool writeonly_memory = false;
705 LLVMValueRef chans[4], rsrc;
706
707 if (inst->Dst[0].Register.File == TGSI_FILE_MEMORY) {
708 store_emit_memory(ctx, emit_data);
709 return;
710 }
711
712 for (unsigned chan = 0; chan < 4; ++chan)
713 chans[chan] = lp_build_emit_fetch(bld_base, inst, 1, chan);
714
715 emit_data->args[emit_data->arg_count++] =
716 ac_build_gather_values(&ctx->ac, chans, 4);
717
718 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
719 LLVMValueRef offset, tmp;
720
721 rsrc = shader_buffer_fetch_rsrc(ctx, &resource_reg, false);
722
723 tmp = lp_build_emit_fetch(bld_base, inst, 0, 0);
724 offset = ac_to_integer(&ctx->ac, tmp);
725
726 buffer_append_args(ctx, emit_data, rsrc, ctx->i32_0,
727 offset, false, false);
728 } else if (inst->Dst[0].Register.File == TGSI_FILE_IMAGE ||
729 tgsi_is_bindless_image_file(inst->Dst[0].Register.File)) {
730 /* 8bit/16bit TC L1 write corruption bug on SI.
731 * All store opcodes not aligned to a dword are affected.
732 *
733 * The only way to get unaligned stores in radeonsi is through
734 * shader images.
735 */
736 bool force_glc = ctx->screen->info.chip_class == SI;
737
738 image_fetch_rsrc(bld_base, &resource_reg, true, target, &rsrc);
739 image_fetch_coords(bld_base, inst, 0, rsrc, &emit_data->args[2]);
740
741 if (target == TGSI_TEXTURE_BUFFER) {
742 buffer_append_args(ctx, emit_data, rsrc, emit_data->args[2],
743 ctx->i32_0, false, force_glc);
744 } else {
745 emit_data->args[1] = rsrc;
746 }
747 }
748
749 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
750 ac_build_waitcnt(&ctx->ac, VM_CNT);
751
752 writeonly_memory = is_oneway_access_only(inst, info,
753 info->shader_buffers_load |
754 info->shader_buffers_atomic,
755 info->images_load |
756 info->images_atomic);
757
758 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
759 store_emit_buffer(ctx, emit_data, writeonly_memory);
760 return;
761 }
762
763 if (target == TGSI_TEXTURE_BUFFER) {
764 /* If this is write-only, don't keep data in L1 to prevent
765 * evicting L1 cache lines that may be needed by other
766 * instructions.
767 */
768 if (writeonly_memory)
769 emit_data->args[4] = LLVMConstInt(ctx->i1, 1, 0); /* GLC = 1 */
770
771 emit_data->output[emit_data->chan] = ac_build_intrinsic(
772 &ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32",
773 ctx->voidt, emit_data->args,
774 emit_data->arg_count,
775 ac_get_store_intr_attribs(writeonly_memory));
776 } else {
777 struct ac_image_args args = {};
778 args.opcode = ac_image_store;
779 args.data[0] = emit_data->args[0];
780 args.resource = emit_data->args[1];
781 memcpy(args.coords, &emit_data->args[2], sizeof(args.coords));
782 args.dim = ac_image_dim_from_tgsi_target(ctx->screen, inst->Memory.Texture);
783 args.attributes = ac_get_store_intr_attribs(writeonly_memory);
784 args.dmask = 0xf;
785
786 /* Workaround for 8bit/16bit TC L1 write corruption bug on SI.
787 * All store opcodes not aligned to a dword are affected.
788 */
789 if (ctx->screen->info.chip_class == SI ||
790 /* If this is write-only, don't keep data in L1 to prevent
791 * evicting L1 cache lines that may be needed by other
792 * instructions. */
793 writeonly_memory ||
794 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE))
795 args.cache_policy = ac_glc;
796
797 emit_data->output[emit_data->chan] =
798 ac_build_image_opcode(&ctx->ac, &args);
799 }
800 }
801
802 static void atomic_emit_memory(struct si_shader_context *ctx,
803 struct lp_build_emit_data *emit_data) {
804 LLVMBuilderRef builder = ctx->ac.builder;
805 const struct tgsi_full_instruction * inst = emit_data->inst;
806 LLVMValueRef ptr, result, arg;
807
808 ptr = get_memory_ptr(ctx, inst, ctx->i32, 1);
809
810 arg = lp_build_emit_fetch(&ctx->bld_base, inst, 2, 0);
811 arg = ac_to_integer(&ctx->ac, arg);
812
813 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
814 LLVMValueRef new_data;
815 new_data = lp_build_emit_fetch(&ctx->bld_base,
816 inst, 3, 0);
817
818 new_data = ac_to_integer(&ctx->ac, new_data);
819
820 result = LLVMBuildAtomicCmpXchg(builder, ptr, arg, new_data,
821 LLVMAtomicOrderingSequentiallyConsistent,
822 LLVMAtomicOrderingSequentiallyConsistent,
823 false);
824
825 result = LLVMBuildExtractValue(builder, result, 0, "");
826 } else {
827 LLVMAtomicRMWBinOp op;
828
829 switch(inst->Instruction.Opcode) {
830 case TGSI_OPCODE_ATOMUADD:
831 op = LLVMAtomicRMWBinOpAdd;
832 break;
833 case TGSI_OPCODE_ATOMXCHG:
834 op = LLVMAtomicRMWBinOpXchg;
835 break;
836 case TGSI_OPCODE_ATOMAND:
837 op = LLVMAtomicRMWBinOpAnd;
838 break;
839 case TGSI_OPCODE_ATOMOR:
840 op = LLVMAtomicRMWBinOpOr;
841 break;
842 case TGSI_OPCODE_ATOMXOR:
843 op = LLVMAtomicRMWBinOpXor;
844 break;
845 case TGSI_OPCODE_ATOMUMIN:
846 op = LLVMAtomicRMWBinOpUMin;
847 break;
848 case TGSI_OPCODE_ATOMUMAX:
849 op = LLVMAtomicRMWBinOpUMax;
850 break;
851 case TGSI_OPCODE_ATOMIMIN:
852 op = LLVMAtomicRMWBinOpMin;
853 break;
854 case TGSI_OPCODE_ATOMIMAX:
855 op = LLVMAtomicRMWBinOpMax;
856 break;
857 default:
858 unreachable("unknown atomic opcode");
859 }
860
861 result = LLVMBuildAtomicRMW(builder, op, ptr, arg,
862 LLVMAtomicOrderingSequentiallyConsistent,
863 false);
864 }
865 emit_data->output[emit_data->chan] =
866 LLVMBuildBitCast(builder, result, ctx->f32, "");
867 }
868
869 static void atomic_emit(
870 const struct lp_build_tgsi_action *action,
871 struct lp_build_tgsi_context *bld_base,
872 struct lp_build_emit_data *emit_data)
873 {
874 struct si_shader_context *ctx = si_shader_context(bld_base);
875 const struct tgsi_full_instruction * inst = emit_data->inst;
876 struct ac_image_args args = {};
877 unsigned num_data = 0;
878 LLVMValueRef vindex = ctx->i32_0;
879 LLVMValueRef voffset = ctx->i32_0;
880
881 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
882 atomic_emit_memory(ctx, emit_data);
883 return;
884 }
885
886 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
887 /* llvm.amdgcn.image/buffer.atomic.cmpswap reflect the hardware order
888 * of arguments, which is reversed relative to TGSI (and GLSL)
889 */
890 args.data[num_data++] =
891 ac_to_integer(&ctx->ac, lp_build_emit_fetch(bld_base, inst, 3, 0));
892 }
893
894 args.data[num_data++] =
895 ac_to_integer(&ctx->ac, lp_build_emit_fetch(bld_base, inst, 2, 0));
896 args.cache_policy = get_cache_policy(ctx, inst, true, false);
897
898 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
899 args.resource = shader_buffer_fetch_rsrc(ctx, &inst->Src[0], false);
900 voffset = ac_to_integer(&ctx->ac, lp_build_emit_fetch(bld_base, inst, 1, 0));
901 } else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE ||
902 tgsi_is_bindless_image_file(inst->Src[0].Register.File)) {
903 image_fetch_rsrc(bld_base, &inst->Src[0], true,
904 inst->Memory.Texture, &args.resource);
905 image_fetch_coords(bld_base, inst, 1, args.resource, args.coords);
906 vindex = args.coords[0]; /* for buffers only */
907 }
908
909 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
910 inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
911 LLVMValueRef buf_args[7];
912 unsigned num_args = 0;
913
914 buf_args[num_args++] = args.data[0];
915 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
916 buf_args[num_args++] = args.data[1];
917
918 buf_args[num_args++] = args.resource;
919 buf_args[num_args++] = vindex;
920 buf_args[num_args++] = voffset;
921 buf_args[num_args++] = args.cache_policy & ac_slc ? ctx->i1true : ctx->i1false;
922
923 char intrinsic_name[40];
924 snprintf(intrinsic_name, sizeof(intrinsic_name),
925 "llvm.amdgcn.buffer.atomic.%s", action->intr_name);
926 emit_data->output[emit_data->chan] =
927 ac_to_float(&ctx->ac,
928 ac_build_intrinsic(&ctx->ac, intrinsic_name,
929 ctx->i32, buf_args, num_args, 0));
930 } else {
931 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
932 args.opcode = ac_image_atomic_cmpswap;
933 } else {
934 args.opcode = ac_image_atomic;
935 switch (inst->Instruction.Opcode) {
936 case TGSI_OPCODE_ATOMXCHG: args.atomic = ac_atomic_swap; break;
937 case TGSI_OPCODE_ATOMUADD: args.atomic = ac_atomic_add; break;
938 case TGSI_OPCODE_ATOMAND: args.atomic = ac_atomic_and; break;
939 case TGSI_OPCODE_ATOMOR: args.atomic = ac_atomic_or; break;
940 case TGSI_OPCODE_ATOMXOR: args.atomic = ac_atomic_xor; break;
941 case TGSI_OPCODE_ATOMUMIN: args.atomic = ac_atomic_umin; break;
942 case TGSI_OPCODE_ATOMUMAX: args.atomic = ac_atomic_umax; break;
943 case TGSI_OPCODE_ATOMIMIN: args.atomic = ac_atomic_smin; break;
944 case TGSI_OPCODE_ATOMIMAX: args.atomic = ac_atomic_smax; break;
945 default: unreachable("unhandled image atomic");
946 }
947 }
948
949 args.dim = ac_image_dim_from_tgsi_target(ctx->screen, inst->Memory.Texture);
950 emit_data->output[emit_data->chan] =
951 ac_to_float(&ctx->ac, ac_build_image_opcode(&ctx->ac, &args));
952 }
953 }
954
955 static LLVMValueRef fix_resinfo(struct si_shader_context *ctx,
956 unsigned target, LLVMValueRef out)
957 {
958 LLVMBuilderRef builder = ctx->ac.builder;
959
960 /* 1D textures are allocated and used as 2D on GFX9. */
961 if (ctx->screen->info.chip_class >= GFX9 &&
962 (target == TGSI_TEXTURE_1D_ARRAY ||
963 target == TGSI_TEXTURE_SHADOW1D_ARRAY)) {
964 LLVMValueRef layers =
965 LLVMBuildExtractElement(builder, out,
966 LLVMConstInt(ctx->i32, 2, 0), "");
967 out = LLVMBuildInsertElement(builder, out, layers,
968 ctx->i32_1, "");
969 }
970
971 /* Divide the number of layers by 6 to get the number of cubes. */
972 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
973 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
974 LLVMValueRef imm2 = LLVMConstInt(ctx->i32, 2, 0);
975
976 LLVMValueRef z = LLVMBuildExtractElement(builder, out, imm2, "");
977 z = LLVMBuildSDiv(builder, z, LLVMConstInt(ctx->i32, 6, 0), "");
978
979 out = LLVMBuildInsertElement(builder, out, z, imm2, "");
980 }
981 return out;
982 }
983
984 static void resq_emit(
985 const struct lp_build_tgsi_action *action,
986 struct lp_build_tgsi_context *bld_base,
987 struct lp_build_emit_data *emit_data)
988 {
989 struct si_shader_context *ctx = si_shader_context(bld_base);
990 LLVMBuilderRef builder = ctx->ac.builder;
991 const struct tgsi_full_instruction *inst = emit_data->inst;
992 const struct tgsi_full_src_register *reg =
993 &inst->Src[inst->Instruction.Opcode == TGSI_OPCODE_TXQ ? 1 : 0];
994
995 if (reg->Register.File == TGSI_FILE_BUFFER) {
996 LLVMValueRef rsrc = shader_buffer_fetch_rsrc(ctx, reg, false);
997
998 emit_data->output[emit_data->chan] =
999 LLVMBuildExtractElement(builder, rsrc,
1000 LLVMConstInt(ctx->i32, 2, 0), "");
1001 return;
1002 }
1003
1004 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ &&
1005 inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
1006 LLVMValueRef rsrc;
1007
1008 tex_fetch_ptrs(bld_base, emit_data, &rsrc, NULL, NULL);
1009 /* Read the size from the buffer descriptor directly. */
1010 emit_data->output[emit_data->chan] =
1011 get_buffer_size(bld_base, rsrc);
1012 return;
1013 }
1014
1015 if (inst->Instruction.Opcode == TGSI_OPCODE_RESQ &&
1016 inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
1017 LLVMValueRef rsrc;
1018
1019 image_fetch_rsrc(bld_base, reg, false, inst->Memory.Texture, &rsrc);
1020 emit_data->output[emit_data->chan] =
1021 get_buffer_size(bld_base, rsrc);
1022 return;
1023 }
1024
1025 unsigned target;
1026
1027 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ) {
1028 target = inst->Texture.Texture;
1029 } else {
1030 if (inst->Memory.Texture == TGSI_TEXTURE_3D)
1031 target = TGSI_TEXTURE_2D_ARRAY;
1032 else
1033 target = inst->Memory.Texture;
1034 }
1035
1036 struct ac_image_args args = {};
1037 args.opcode = ac_image_get_resinfo;
1038 args.dim = ac_texture_dim_from_tgsi_target(ctx->screen, target);
1039 args.dmask = 0xf;
1040
1041 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ) {
1042 tex_fetch_ptrs(bld_base, emit_data, &args.resource, NULL, NULL);
1043 args.lod = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
1044 } else {
1045 image_fetch_rsrc(bld_base, reg, false, target, &args.resource);
1046 args.lod = ctx->i32_0;
1047 }
1048
1049 emit_data->output[emit_data->chan] =
1050 fix_resinfo(ctx, target, ac_build_image_opcode(&ctx->ac, &args));
1051 }
1052
1053 /**
1054 * Load an image view, fmask view. or sampler state descriptor.
1055 */
1056 LLVMValueRef si_load_sampler_desc(struct si_shader_context *ctx,
1057 LLVMValueRef list, LLVMValueRef index,
1058 enum ac_descriptor_type type)
1059 {
1060 LLVMBuilderRef builder = ctx->ac.builder;
1061
1062 switch (type) {
1063 case AC_DESC_IMAGE:
1064 /* The image is at [0:7]. */
1065 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
1066 break;
1067 case AC_DESC_BUFFER:
1068 /* The buffer is in [4:7]. */
1069 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 4, 0), "");
1070 index = LLVMBuildAdd(builder, index, ctx->i32_1, "");
1071 list = LLVMBuildPointerCast(builder, list,
1072 ac_array_in_const32_addr_space(ctx->v4i32), "");
1073 break;
1074 case AC_DESC_FMASK:
1075 /* The FMASK is at [8:15]. */
1076 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
1077 index = LLVMBuildAdd(builder, index, ctx->i32_1, "");
1078 break;
1079 case AC_DESC_SAMPLER:
1080 /* The sampler state is at [12:15]. */
1081 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 4, 0), "");
1082 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 3, 0), "");
1083 list = LLVMBuildPointerCast(builder, list,
1084 ac_array_in_const32_addr_space(ctx->v4i32), "");
1085 break;
1086 }
1087
1088 return ac_build_load_to_sgpr(&ctx->ac, list, index);
1089 }
1090
1091 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
1092 *
1093 * SI-CI:
1094 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
1095 * filtering manually. The driver sets img7 to a mask clearing
1096 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
1097 * s_and_b32 samp0, samp0, img7
1098 *
1099 * VI:
1100 * The ANISO_OVERRIDE sampler field enables this fix in TA.
1101 */
1102 static LLVMValueRef sici_fix_sampler_aniso(struct si_shader_context *ctx,
1103 LLVMValueRef res, LLVMValueRef samp)
1104 {
1105 LLVMValueRef img7, samp0;
1106
1107 if (ctx->screen->info.chip_class >= VI)
1108 return samp;
1109
1110 img7 = LLVMBuildExtractElement(ctx->ac.builder, res,
1111 LLVMConstInt(ctx->i32, 7, 0), "");
1112 samp0 = LLVMBuildExtractElement(ctx->ac.builder, samp,
1113 ctx->i32_0, "");
1114 samp0 = LLVMBuildAnd(ctx->ac.builder, samp0, img7, "");
1115 return LLVMBuildInsertElement(ctx->ac.builder, samp, samp0,
1116 ctx->i32_0, "");
1117 }
1118
1119 static void tex_fetch_ptrs(struct lp_build_tgsi_context *bld_base,
1120 struct lp_build_emit_data *emit_data,
1121 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
1122 LLVMValueRef *fmask_ptr)
1123 {
1124 struct si_shader_context *ctx = si_shader_context(bld_base);
1125 LLVMValueRef list = LLVMGetParam(ctx->main_fn, ctx->param_samplers_and_images);
1126 const struct tgsi_full_instruction *inst = emit_data->inst;
1127 const struct tgsi_full_src_register *reg;
1128 unsigned target = inst->Texture.Texture;
1129 unsigned sampler_src;
1130 LLVMValueRef index;
1131
1132 sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
1133 reg = &emit_data->inst->Src[sampler_src];
1134
1135 if (reg->Register.Indirect) {
1136 index = si_get_bounded_indirect_index(ctx,
1137 &reg->Indirect,
1138 reg->Register.Index,
1139 ctx->num_samplers);
1140 index = LLVMBuildAdd(ctx->ac.builder, index,
1141 LLVMConstInt(ctx->i32, SI_NUM_IMAGES / 2, 0), "");
1142 } else {
1143 index = LLVMConstInt(ctx->i32,
1144 si_get_sampler_slot(reg->Register.Index), 0);
1145 }
1146
1147 if (reg->Register.File != TGSI_FILE_SAMPLER) {
1148 /* Bindless descriptors are accessible from a different pair of
1149 * user SGPR indices.
1150 */
1151 list = LLVMGetParam(ctx->main_fn,
1152 ctx->param_bindless_samplers_and_images);
1153 index = lp_build_emit_fetch_src(bld_base, reg,
1154 TGSI_TYPE_UNSIGNED, 0);
1155 }
1156
1157 if (target == TGSI_TEXTURE_BUFFER)
1158 *res_ptr = si_load_sampler_desc(ctx, list, index, AC_DESC_BUFFER);
1159 else
1160 *res_ptr = si_load_sampler_desc(ctx, list, index, AC_DESC_IMAGE);
1161
1162 if (samp_ptr)
1163 *samp_ptr = NULL;
1164 if (fmask_ptr)
1165 *fmask_ptr = NULL;
1166
1167 if (target == TGSI_TEXTURE_2D_MSAA ||
1168 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
1169 if (fmask_ptr)
1170 *fmask_ptr = si_load_sampler_desc(ctx, list, index,
1171 AC_DESC_FMASK);
1172 } else if (target != TGSI_TEXTURE_BUFFER) {
1173 if (samp_ptr) {
1174 *samp_ptr = si_load_sampler_desc(ctx, list, index,
1175 AC_DESC_SAMPLER);
1176 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
1177 }
1178 }
1179 }
1180
1181 /* Gather4 should follow the same rules as bilinear filtering, but the hardware
1182 * incorrectly forces nearest filtering if the texture format is integer.
1183 * The only effect it has on Gather4, which always returns 4 texels for
1184 * bilinear filtering, is that the final coordinates are off by 0.5 of
1185 * the texel size.
1186 *
1187 * The workaround is to subtract 0.5 from the unnormalized coordinates,
1188 * or (0.5 / size) from the normalized coordinates.
1189 *
1190 * However, cube textures with 8_8_8_8 data formats require a different
1191 * workaround of overriding the num format to USCALED/SSCALED. This would lose
1192 * precision in 32-bit data formats, so it needs to be applied dynamically at
1193 * runtime. In this case, return an i1 value that indicates whether the
1194 * descriptor was overridden (and hence a fixup of the sampler result is needed).
1195 */
1196 static LLVMValueRef
1197 si_lower_gather4_integer(struct si_shader_context *ctx,
1198 struct ac_image_args *args,
1199 unsigned target,
1200 enum tgsi_return_type return_type)
1201 {
1202 LLVMBuilderRef builder = ctx->ac.builder;
1203 LLVMValueRef wa_8888 = NULL;
1204 LLVMValueRef half_texel[2];
1205
1206 assert(return_type == TGSI_RETURN_TYPE_SINT ||
1207 return_type == TGSI_RETURN_TYPE_UINT);
1208
1209 if (target == TGSI_TEXTURE_CUBE ||
1210 target == TGSI_TEXTURE_CUBE_ARRAY) {
1211 LLVMValueRef formats;
1212 LLVMValueRef data_format;
1213 LLVMValueRef wa_formats;
1214
1215 formats = LLVMBuildExtractElement(builder, args->resource, ctx->i32_1, "");
1216
1217 data_format = LLVMBuildLShr(builder, formats,
1218 LLVMConstInt(ctx->i32, 20, false), "");
1219 data_format = LLVMBuildAnd(builder, data_format,
1220 LLVMConstInt(ctx->i32, (1u << 6) - 1, false), "");
1221 wa_8888 = LLVMBuildICmp(
1222 builder, LLVMIntEQ, data_format,
1223 LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false),
1224 "");
1225
1226 uint32_t wa_num_format =
1227 return_type == TGSI_RETURN_TYPE_UINT ?
1228 S_008F14_NUM_FORMAT_GFX6(V_008F14_IMG_NUM_FORMAT_USCALED) :
1229 S_008F14_NUM_FORMAT_GFX6(V_008F14_IMG_NUM_FORMAT_SSCALED);
1230 wa_formats = LLVMBuildAnd(builder, formats,
1231 LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false),
1232 "");
1233 wa_formats = LLVMBuildOr(builder, wa_formats,
1234 LLVMConstInt(ctx->i32, wa_num_format, false), "");
1235
1236 formats = LLVMBuildSelect(builder, wa_8888, wa_formats, formats, "");
1237 args->resource = LLVMBuildInsertElement(
1238 builder, args->resource, formats, ctx->i32_1, "");
1239 }
1240
1241 if (target == TGSI_TEXTURE_RECT ||
1242 target == TGSI_TEXTURE_SHADOWRECT) {
1243 assert(!wa_8888);
1244 half_texel[0] = half_texel[1] = LLVMConstReal(ctx->f32, -0.5);
1245 } else {
1246 struct ac_image_args resinfo = {};
1247 struct lp_build_if_state if_ctx;
1248
1249 if (wa_8888) {
1250 /* Skip the texture size query entirely if we don't need it. */
1251 lp_build_if(&if_ctx, &ctx->gallivm, LLVMBuildNot(builder, wa_8888, ""));
1252 }
1253
1254 /* Query the texture size. */
1255 resinfo.opcode = ac_image_get_resinfo;
1256 resinfo.dim = ac_texture_dim_from_tgsi_target(ctx->screen, target);
1257 resinfo.resource = args->resource;
1258 resinfo.sampler = args->sampler;
1259 resinfo.lod = ctx->ac.i32_0;
1260 resinfo.dmask = 0xf;
1261
1262 LLVMValueRef texsize =
1263 fix_resinfo(ctx, target,
1264 ac_build_image_opcode(&ctx->ac, &resinfo));
1265
1266 /* Compute -0.5 / size. */
1267 for (unsigned c = 0; c < 2; c++) {
1268 half_texel[c] =
1269 LLVMBuildExtractElement(builder, texsize,
1270 LLVMConstInt(ctx->i32, c, 0), "");
1271 half_texel[c] = LLVMBuildUIToFP(builder, half_texel[c], ctx->f32, "");
1272 half_texel[c] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, half_texel[c]);
1273 half_texel[c] = LLVMBuildFMul(builder, half_texel[c],
1274 LLVMConstReal(ctx->f32, -0.5), "");
1275 }
1276
1277 if (wa_8888) {
1278 lp_build_endif(&if_ctx);
1279
1280 LLVMBasicBlockRef bb[2] = { if_ctx.true_block, if_ctx.entry_block };
1281
1282 for (unsigned c = 0; c < 2; c++) {
1283 LLVMValueRef values[2] = { half_texel[c], ctx->ac.f32_0 };
1284 half_texel[c] = ac_build_phi(&ctx->ac, ctx->f32, 2,
1285 values, bb);
1286 }
1287 }
1288 }
1289
1290 for (unsigned c = 0; c < 2; c++) {
1291 LLVMValueRef tmp;
1292 tmp = ac_to_float(&ctx->ac, args->coords[c]);
1293 tmp = LLVMBuildFAdd(builder, tmp, half_texel[c], "");
1294 args->coords[c] = ac_to_integer(&ctx->ac, tmp);
1295 }
1296
1297 return wa_8888;
1298 }
1299
1300 /* The second half of the cube texture 8_8_8_8 integer workaround: adjust the
1301 * result after the gather operation.
1302 */
1303 static LLVMValueRef
1304 si_fix_gather4_integer_result(struct si_shader_context *ctx,
1305 LLVMValueRef result,
1306 enum tgsi_return_type return_type,
1307 LLVMValueRef wa)
1308 {
1309 LLVMBuilderRef builder = ctx->ac.builder;
1310
1311 assert(return_type == TGSI_RETURN_TYPE_SINT ||
1312 return_type == TGSI_RETURN_TYPE_UINT);
1313
1314 for (unsigned chan = 0; chan < 4; ++chan) {
1315 LLVMValueRef chanv = LLVMConstInt(ctx->i32, chan, false);
1316 LLVMValueRef value;
1317 LLVMValueRef wa_value;
1318
1319 value = LLVMBuildExtractElement(builder, result, chanv, "");
1320
1321 if (return_type == TGSI_RETURN_TYPE_UINT)
1322 wa_value = LLVMBuildFPToUI(builder, value, ctx->i32, "");
1323 else
1324 wa_value = LLVMBuildFPToSI(builder, value, ctx->i32, "");
1325 wa_value = ac_to_float(&ctx->ac, wa_value);
1326 value = LLVMBuildSelect(builder, wa, wa_value, value, "");
1327
1328 result = LLVMBuildInsertElement(builder, result, value, chanv, "");
1329 }
1330
1331 return result;
1332 }
1333
1334 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
1335 struct lp_build_tgsi_context *bld_base,
1336 struct lp_build_emit_data *emit_data)
1337 {
1338 struct si_shader_context *ctx = si_shader_context(bld_base);
1339 const struct tgsi_full_instruction *inst = emit_data->inst;
1340 unsigned opcode = inst->Instruction.Opcode;
1341 unsigned target = inst->Texture.Texture;
1342 struct ac_image_args args = {};
1343 int ref_pos = tgsi_util_get_shadow_ref_src_index(target);
1344 unsigned chan;
1345 bool has_offset = inst->Texture.NumOffsets > 0;
1346 LLVMValueRef fmask_ptr = NULL;
1347
1348 tex_fetch_ptrs(bld_base, emit_data, &args.resource, &args.sampler, &fmask_ptr);
1349
1350 if (target == TGSI_TEXTURE_BUFFER) {
1351 LLVMValueRef vindex = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
1352 unsigned num_channels =
1353 util_last_bit(inst->Dst[0].Register.WriteMask);
1354 LLVMValueRef result =
1355 ac_build_buffer_load_format(&ctx->ac,
1356 args.resource,
1357 vindex,
1358 ctx->i32_0,
1359 num_channels, false, true);
1360 emit_data->output[emit_data->chan] =
1361 ac_build_expand_to_vec4(&ctx->ac, result, num_channels);
1362 return;
1363 }
1364
1365 /* Fetch and project texture coordinates */
1366 args.coords[3] = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_W);
1367 for (chan = 0; chan < 3; chan++) {
1368 args.coords[chan] = lp_build_emit_fetch(bld_base, inst, 0, chan);
1369 if (opcode == TGSI_OPCODE_TXP)
1370 args.coords[chan] = ac_build_fdiv(&ctx->ac,
1371 args.coords[chan], args.coords[3]);
1372 }
1373
1374 if (opcode == TGSI_OPCODE_TXP)
1375 args.coords[3] = ctx->ac.f32_1;
1376
1377 /* Pack offsets. */
1378 if (has_offset &&
1379 opcode != TGSI_OPCODE_TXF &&
1380 opcode != TGSI_OPCODE_TXF_LZ) {
1381 /* The offsets are six-bit signed integers packed like this:
1382 * X=[5:0], Y=[13:8], and Z=[21:16].
1383 */
1384 LLVMValueRef offset[3], pack;
1385
1386 assert(inst->Texture.NumOffsets == 1);
1387
1388 for (chan = 0; chan < 3; chan++) {
1389 offset[chan] = lp_build_emit_fetch_texoffset(bld_base, inst, 0, chan);
1390 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
1391 LLVMConstInt(ctx->i32, 0x3f, 0), "");
1392 if (chan)
1393 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
1394 LLVMConstInt(ctx->i32, chan*8, 0), "");
1395 }
1396
1397 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
1398 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
1399 args.offset = pack;
1400 }
1401
1402 /* Pack LOD bias value */
1403 if (opcode == TGSI_OPCODE_TXB)
1404 args.bias = args.coords[3];
1405 if (opcode == TGSI_OPCODE_TXB2)
1406 args.bias = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
1407
1408 /* Pack depth comparison value */
1409 if (tgsi_is_shadow_target(target) && opcode != TGSI_OPCODE_LODQ) {
1410 LLVMValueRef z;
1411
1412 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
1413 z = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
1414 } else {
1415 assert(ref_pos >= 0);
1416 z = args.coords[ref_pos];
1417 }
1418
1419 /* Section 8.23.1 (Depth Texture Comparison Mode) of the
1420 * OpenGL 4.5 spec says:
1421 *
1422 * "If the texture’s internal format indicates a fixed-point
1423 * depth texture, then D_t and D_ref are clamped to the
1424 * range [0, 1]; otherwise no clamping is performed."
1425 *
1426 * TC-compatible HTILE promotes Z16 and Z24 to Z32_FLOAT,
1427 * so the depth comparison value isn't clamped for Z16 and
1428 * Z24 anymore. Do it manually here.
1429 */
1430 if (ctx->screen->info.chip_class >= VI) {
1431 LLVMValueRef upgraded;
1432 LLVMValueRef clamped;
1433 upgraded = LLVMBuildExtractElement(ctx->ac.builder, args.sampler,
1434 LLVMConstInt(ctx->i32, 3, false), "");
1435 upgraded = LLVMBuildLShr(ctx->ac.builder, upgraded,
1436 LLVMConstInt(ctx->i32, 29, false), "");
1437 upgraded = LLVMBuildTrunc(ctx->ac.builder, upgraded, ctx->i1, "");
1438 clamped = ac_build_clamp(&ctx->ac, z);
1439 z = LLVMBuildSelect(ctx->ac.builder, upgraded, clamped, z, "");
1440 }
1441
1442 args.compare = z;
1443 }
1444
1445 /* Pack user derivatives */
1446 if (opcode == TGSI_OPCODE_TXD) {
1447 int param, num_src_deriv_channels, num_dst_deriv_channels;
1448
1449 switch (target) {
1450 case TGSI_TEXTURE_3D:
1451 num_src_deriv_channels = 3;
1452 num_dst_deriv_channels = 3;
1453 break;
1454 case TGSI_TEXTURE_2D:
1455 case TGSI_TEXTURE_SHADOW2D:
1456 case TGSI_TEXTURE_RECT:
1457 case TGSI_TEXTURE_SHADOWRECT:
1458 case TGSI_TEXTURE_2D_ARRAY:
1459 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1460 num_src_deriv_channels = 2;
1461 num_dst_deriv_channels = 2;
1462 break;
1463 case TGSI_TEXTURE_CUBE:
1464 case TGSI_TEXTURE_SHADOWCUBE:
1465 case TGSI_TEXTURE_CUBE_ARRAY:
1466 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
1467 /* Cube derivatives will be converted to 2D. */
1468 num_src_deriv_channels = 3;
1469 num_dst_deriv_channels = 3;
1470 break;
1471 case TGSI_TEXTURE_1D:
1472 case TGSI_TEXTURE_SHADOW1D:
1473 case TGSI_TEXTURE_1D_ARRAY:
1474 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1475 num_src_deriv_channels = 1;
1476
1477 /* 1D textures are allocated and used as 2D on GFX9. */
1478 if (ctx->screen->info.chip_class >= GFX9) {
1479 num_dst_deriv_channels = 2;
1480 } else {
1481 num_dst_deriv_channels = 1;
1482 }
1483 break;
1484 default:
1485 unreachable("invalid target");
1486 }
1487
1488 for (param = 0; param < 2; param++) {
1489 for (chan = 0; chan < num_src_deriv_channels; chan++)
1490 args.derivs[param * num_dst_deriv_channels + chan] =
1491 lp_build_emit_fetch(bld_base, inst, param+1, chan);
1492
1493 /* Fill in the rest with zeros. */
1494 for (chan = num_src_deriv_channels;
1495 chan < num_dst_deriv_channels; chan++)
1496 args.derivs[param * num_dst_deriv_channels + chan] =
1497 ctx->ac.f32_0;
1498 }
1499 }
1500
1501 if (target == TGSI_TEXTURE_CUBE ||
1502 target == TGSI_TEXTURE_CUBE_ARRAY ||
1503 target == TGSI_TEXTURE_SHADOWCUBE ||
1504 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
1505 ac_prepare_cube_coords(&ctx->ac,
1506 opcode == TGSI_OPCODE_TXD,
1507 target == TGSI_TEXTURE_CUBE_ARRAY ||
1508 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY,
1509 opcode == TGSI_OPCODE_LODQ,
1510 args.coords, args.derivs);
1511 } else if (tgsi_is_array_sampler(target) &&
1512 opcode != TGSI_OPCODE_TXF &&
1513 opcode != TGSI_OPCODE_TXF_LZ &&
1514 ctx->screen->info.chip_class <= VI) {
1515 unsigned array_coord = target == TGSI_TEXTURE_1D_ARRAY ? 1 : 2;
1516 args.coords[array_coord] =
1517 ac_build_intrinsic(&ctx->ac, "llvm.rint.f32", ctx->f32,
1518 &args.coords[array_coord], 1, 0);
1519 }
1520
1521 /* 1D textures are allocated and used as 2D on GFX9. */
1522 if (ctx->screen->info.chip_class >= GFX9) {
1523 LLVMValueRef filler;
1524
1525 /* Use 0.5, so that we don't sample the border color. */
1526 if (opcode == TGSI_OPCODE_TXF ||
1527 opcode == TGSI_OPCODE_TXF_LZ)
1528 filler = ctx->i32_0;
1529 else
1530 filler = LLVMConstReal(ctx->f32, 0.5);
1531
1532 if (target == TGSI_TEXTURE_1D ||
1533 target == TGSI_TEXTURE_SHADOW1D) {
1534 args.coords[1] = filler;
1535 } else if (target == TGSI_TEXTURE_1D_ARRAY ||
1536 target == TGSI_TEXTURE_SHADOW1D_ARRAY) {
1537 args.coords[2] = args.coords[1];
1538 args.coords[1] = filler;
1539 }
1540 }
1541
1542 /* Pack LOD or sample index */
1543 if (opcode == TGSI_OPCODE_TXL)
1544 args.lod = args.coords[3];
1545 else if (opcode == TGSI_OPCODE_TXL2)
1546 args.lod = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
1547 else if (opcode == TGSI_OPCODE_TXF) {
1548 if (target == TGSI_TEXTURE_2D_MSAA) {
1549 /* No LOD, but move sample index into the right place. */
1550 args.coords[2] = args.coords[3];
1551 } else if (target != TGSI_TEXTURE_2D_ARRAY_MSAA) {
1552 args.lod = args.coords[3];
1553 }
1554 }
1555
1556 if (target == TGSI_TEXTURE_2D_MSAA ||
1557 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
1558 ac_apply_fmask_to_sample(&ctx->ac, fmask_ptr, args.coords,
1559 target == TGSI_TEXTURE_2D_ARRAY_MSAA);
1560 }
1561
1562 if (opcode == TGSI_OPCODE_TXF ||
1563 opcode == TGSI_OPCODE_TXF_LZ) {
1564 /* add tex offsets */
1565 if (inst->Texture.NumOffsets) {
1566 const struct tgsi_texture_offset *off = inst->TexOffsets;
1567
1568 assert(inst->Texture.NumOffsets == 1);
1569
1570 switch (target) {
1571 case TGSI_TEXTURE_3D:
1572 args.coords[2] =
1573 LLVMBuildAdd(ctx->ac.builder, args.coords[2],
1574 ctx->imms[off->Index * TGSI_NUM_CHANNELS + off->SwizzleZ], "");
1575 /* fall through */
1576 case TGSI_TEXTURE_2D:
1577 case TGSI_TEXTURE_SHADOW2D:
1578 case TGSI_TEXTURE_RECT:
1579 case TGSI_TEXTURE_SHADOWRECT:
1580 case TGSI_TEXTURE_2D_ARRAY:
1581 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1582 args.coords[1] =
1583 LLVMBuildAdd(ctx->ac.builder, args.coords[1],
1584 ctx->imms[off->Index * TGSI_NUM_CHANNELS + off->SwizzleY], "");
1585 /* fall through */
1586 case TGSI_TEXTURE_1D:
1587 case TGSI_TEXTURE_SHADOW1D:
1588 case TGSI_TEXTURE_1D_ARRAY:
1589 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1590 args.coords[0] =
1591 LLVMBuildAdd(ctx->ac.builder, args.coords[0],
1592 ctx->imms[off->Index * TGSI_NUM_CHANNELS + off->SwizzleX], "");
1593 break;
1594 /* texture offsets do not apply to other texture targets */
1595 }
1596 }
1597 }
1598
1599 if (opcode == TGSI_OPCODE_TG4) {
1600 unsigned gather_comp = 0;
1601
1602 /* DMASK was repurposed for GATHER4. 4 components are always
1603 * returned and DMASK works like a swizzle - it selects
1604 * the component to fetch. The only valid DMASK values are
1605 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
1606 * (red,red,red,red) etc.) The ISA document doesn't mention
1607 * this.
1608 */
1609
1610 /* Get the component index from src1.x for Gather4. */
1611 if (!tgsi_is_shadow_target(target)) {
1612 LLVMValueRef comp_imm;
1613 struct tgsi_src_register src1 = inst->Src[1].Register;
1614
1615 assert(src1.File == TGSI_FILE_IMMEDIATE);
1616
1617 comp_imm = ctx->imms[src1.Index * TGSI_NUM_CHANNELS + src1.SwizzleX];
1618 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
1619 gather_comp = CLAMP(gather_comp, 0, 3);
1620 }
1621
1622 args.dmask = 1 << gather_comp;
1623 } else {
1624 args.dmask = 0xf;
1625 }
1626
1627 args.dim = ac_texture_dim_from_tgsi_target(ctx->screen, target);
1628 args.unorm = target == TGSI_TEXTURE_RECT ||
1629 target == TGSI_TEXTURE_SHADOWRECT;
1630 args.opcode = ac_image_sample;
1631
1632 switch (opcode) {
1633 case TGSI_OPCODE_TXF:
1634 case TGSI_OPCODE_TXF_LZ:
1635 args.opcode = opcode == TGSI_OPCODE_TXF_LZ ||
1636 target == TGSI_TEXTURE_2D_MSAA ||
1637 target == TGSI_TEXTURE_2D_ARRAY_MSAA ?
1638 ac_image_load : ac_image_load_mip;
1639 break;
1640 case TGSI_OPCODE_LODQ:
1641 args.opcode = ac_image_get_lod;
1642 break;
1643 case TGSI_OPCODE_TEX:
1644 case TGSI_OPCODE_TEX2:
1645 case TGSI_OPCODE_TXP:
1646 if (ctx->type != PIPE_SHADER_FRAGMENT)
1647 args.level_zero = true;
1648 break;
1649 case TGSI_OPCODE_TEX_LZ:
1650 args.level_zero = true;
1651 break;
1652 case TGSI_OPCODE_TXB:
1653 case TGSI_OPCODE_TXB2:
1654 assert(ctx->type == PIPE_SHADER_FRAGMENT);
1655 break;
1656 case TGSI_OPCODE_TXL:
1657 case TGSI_OPCODE_TXL2:
1658 break;
1659 case TGSI_OPCODE_TXD:
1660 break;
1661 case TGSI_OPCODE_TG4:
1662 args.opcode = ac_image_gather4;
1663 args.level_zero = true;
1664 break;
1665 default:
1666 assert(0);
1667 return;
1668 }
1669
1670 /* The hardware needs special lowering for Gather4 with integer formats. */
1671 LLVMValueRef gather4_int_result_workaround = NULL;
1672
1673 if (ctx->screen->info.chip_class <= VI &&
1674 opcode == TGSI_OPCODE_TG4) {
1675 assert(inst->Texture.ReturnType != TGSI_RETURN_TYPE_UNKNOWN);
1676
1677 if (inst->Texture.ReturnType == TGSI_RETURN_TYPE_SINT ||
1678 inst->Texture.ReturnType == TGSI_RETURN_TYPE_UINT) {
1679 gather4_int_result_workaround =
1680 si_lower_gather4_integer(ctx, &args, target,
1681 inst->Texture.ReturnType);
1682 }
1683 }
1684
1685 args.attributes = AC_FUNC_ATTR_READNONE;
1686 LLVMValueRef result = ac_build_image_opcode(&ctx->ac, &args);
1687
1688 if (gather4_int_result_workaround) {
1689 result = si_fix_gather4_integer_result(ctx, result,
1690 inst->Texture.ReturnType,
1691 gather4_int_result_workaround);
1692 }
1693
1694 emit_data->output[emit_data->chan] = result;
1695 }
1696
1697 static void si_llvm_emit_txqs(
1698 const struct lp_build_tgsi_action *action,
1699 struct lp_build_tgsi_context *bld_base,
1700 struct lp_build_emit_data *emit_data)
1701 {
1702 struct si_shader_context *ctx = si_shader_context(bld_base);
1703 LLVMValueRef res, samples;
1704 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
1705
1706 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
1707
1708 /* Read the samples from the descriptor directly. */
1709 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->v8i32, "");
1710 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
1711 LLVMConstInt(ctx->i32, 3, 0), "");
1712 samples = LLVMBuildLShr(ctx->ac.builder, samples,
1713 LLVMConstInt(ctx->i32, 16, 0), "");
1714 samples = LLVMBuildAnd(ctx->ac.builder, samples,
1715 LLVMConstInt(ctx->i32, 0xf, 0), "");
1716 samples = LLVMBuildShl(ctx->ac.builder, ctx->i32_1,
1717 samples, "");
1718
1719 emit_data->output[emit_data->chan] = samples;
1720 }
1721
1722 static void si_llvm_emit_fbfetch(const struct lp_build_tgsi_action *action,
1723 struct lp_build_tgsi_context *bld_base,
1724 struct lp_build_emit_data *emit_data)
1725 {
1726 struct si_shader_context *ctx = si_shader_context(bld_base);
1727 struct ac_image_args args = {};
1728 LLVMValueRef ptr, image, fmask;
1729
1730 /* Ignore src0, because KHR_blend_func_extended disallows multiple render
1731 * targets.
1732 */
1733
1734 /* Load the image descriptor. */
1735 STATIC_ASSERT(SI_PS_IMAGE_COLORBUF0 % 2 == 0);
1736 ptr = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
1737 ptr = LLVMBuildPointerCast(ctx->ac.builder, ptr,
1738 ac_array_in_const32_addr_space(ctx->v8i32), "");
1739 image = ac_build_load_to_sgpr(&ctx->ac, ptr,
1740 LLVMConstInt(ctx->i32, SI_PS_IMAGE_COLORBUF0 / 2, 0));
1741
1742 unsigned chan = 0;
1743
1744 args.coords[chan++] = si_unpack_param(ctx, SI_PARAM_POS_FIXED_PT, 0, 16);
1745
1746 if (!ctx->shader->key.mono.u.ps.fbfetch_is_1D)
1747 args.coords[chan++] = si_unpack_param(ctx, SI_PARAM_POS_FIXED_PT, 16, 16);
1748
1749 /* Get the current render target layer index. */
1750 if (ctx->shader->key.mono.u.ps.fbfetch_layered)
1751 args.coords[chan++] = si_unpack_param(ctx, SI_PARAM_ANCILLARY, 16, 11);
1752
1753 if (ctx->shader->key.mono.u.ps.fbfetch_msaa)
1754 args.coords[chan++] = si_get_sample_id(ctx);
1755
1756 if (ctx->shader->key.mono.u.ps.fbfetch_msaa) {
1757 fmask = ac_build_load_to_sgpr(&ctx->ac, ptr,
1758 LLVMConstInt(ctx->i32, SI_PS_IMAGE_COLORBUF0_FMASK / 2, 0));
1759
1760 ac_apply_fmask_to_sample(&ctx->ac, fmask, args.coords,
1761 ctx->shader->key.mono.u.ps.fbfetch_layered);
1762 }
1763
1764 args.opcode = ac_image_load;
1765 args.resource = image;
1766 args.dmask = 0xf;
1767 if (ctx->shader->key.mono.u.ps.fbfetch_msaa)
1768 args.dim = ctx->shader->key.mono.u.ps.fbfetch_layered ?
1769 ac_image_2darraymsaa : ac_image_2dmsaa;
1770 else if (ctx->shader->key.mono.u.ps.fbfetch_is_1D)
1771 args.dim = ctx->shader->key.mono.u.ps.fbfetch_layered ?
1772 ac_image_1darray : ac_image_1d;
1773 else
1774 args.dim = ctx->shader->key.mono.u.ps.fbfetch_layered ?
1775 ac_image_2darray : ac_image_2d;
1776
1777 emit_data->output[emit_data->chan] =
1778 ac_build_image_opcode(&ctx->ac, &args);
1779 }
1780
1781 /**
1782 * Setup actions for TGSI memory opcode, including texture opcodes.
1783 */
1784 void si_shader_context_init_mem(struct si_shader_context *ctx)
1785 {
1786 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
1787
1788 bld_base->op_actions[TGSI_OPCODE_TEX].emit = build_tex_intrinsic;
1789 bld_base->op_actions[TGSI_OPCODE_TEX_LZ].emit = build_tex_intrinsic;
1790 bld_base->op_actions[TGSI_OPCODE_TEX2].emit = build_tex_intrinsic;
1791 bld_base->op_actions[TGSI_OPCODE_TXB].emit = build_tex_intrinsic;
1792 bld_base->op_actions[TGSI_OPCODE_TXB2].emit = build_tex_intrinsic;
1793 bld_base->op_actions[TGSI_OPCODE_TXD].emit = build_tex_intrinsic;
1794 bld_base->op_actions[TGSI_OPCODE_TXF].emit = build_tex_intrinsic;
1795 bld_base->op_actions[TGSI_OPCODE_TXF_LZ].emit = build_tex_intrinsic;
1796 bld_base->op_actions[TGSI_OPCODE_TXL].emit = build_tex_intrinsic;
1797 bld_base->op_actions[TGSI_OPCODE_TXL2].emit = build_tex_intrinsic;
1798 bld_base->op_actions[TGSI_OPCODE_TXP].emit = build_tex_intrinsic;
1799 bld_base->op_actions[TGSI_OPCODE_TXQ].emit = resq_emit;
1800 bld_base->op_actions[TGSI_OPCODE_TG4].emit = build_tex_intrinsic;
1801 bld_base->op_actions[TGSI_OPCODE_LODQ].emit = build_tex_intrinsic;
1802 bld_base->op_actions[TGSI_OPCODE_TXQS].emit = si_llvm_emit_txqs;
1803
1804 bld_base->op_actions[TGSI_OPCODE_FBFETCH].emit = si_llvm_emit_fbfetch;
1805
1806 bld_base->op_actions[TGSI_OPCODE_LOAD].emit = load_emit;
1807 bld_base->op_actions[TGSI_OPCODE_STORE].emit = store_emit;
1808 bld_base->op_actions[TGSI_OPCODE_RESQ].emit = resq_emit;
1809
1810 bld_base->op_actions[TGSI_OPCODE_ATOMUADD].emit = atomic_emit;
1811 bld_base->op_actions[TGSI_OPCODE_ATOMUADD].intr_name = "add";
1812 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG].emit = atomic_emit;
1813 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG].intr_name = "swap";
1814 bld_base->op_actions[TGSI_OPCODE_ATOMCAS].emit = atomic_emit;
1815 bld_base->op_actions[TGSI_OPCODE_ATOMCAS].intr_name = "cmpswap";
1816 bld_base->op_actions[TGSI_OPCODE_ATOMAND].emit = atomic_emit;
1817 bld_base->op_actions[TGSI_OPCODE_ATOMAND].intr_name = "and";
1818 bld_base->op_actions[TGSI_OPCODE_ATOMOR].emit = atomic_emit;
1819 bld_base->op_actions[TGSI_OPCODE_ATOMOR].intr_name = "or";
1820 bld_base->op_actions[TGSI_OPCODE_ATOMXOR].emit = atomic_emit;
1821 bld_base->op_actions[TGSI_OPCODE_ATOMXOR].intr_name = "xor";
1822 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN].emit = atomic_emit;
1823 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN].intr_name = "umin";
1824 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX].emit = atomic_emit;
1825 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX].intr_name = "umax";
1826 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN].emit = atomic_emit;
1827 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN].intr_name = "smin";
1828 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX].emit = atomic_emit;
1829 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX].intr_name = "smax";
1830 }