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radeonsi: fix GPU hangs with bindless textures and LLVM 7.0
[mesa.git] / src / gallium / drivers / radeonsi / si_shader_tgsi_mem.c
1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_shader_internal.h"
26 #include "si_pipe.h"
27 #include "sid.h"
28 #include "tgsi/tgsi_build.h"
29 #include "tgsi/tgsi_util.h"
30 #include "ac_llvm_util.h"
31
32 static void tex_fetch_ptrs(struct lp_build_tgsi_context *bld_base,
33 struct lp_build_emit_data *emit_data,
34 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
35 LLVMValueRef *fmask_ptr);
36
37 /**
38 * Given a v8i32 resource descriptor for a buffer, extract the size of the
39 * buffer in number of elements and return it as an i32.
40 */
41 static LLVMValueRef get_buffer_size(
42 struct lp_build_tgsi_context *bld_base,
43 LLVMValueRef descriptor)
44 {
45 struct si_shader_context *ctx = si_shader_context(bld_base);
46 LLVMBuilderRef builder = ctx->ac.builder;
47 LLVMValueRef size =
48 LLVMBuildExtractElement(builder, descriptor,
49 LLVMConstInt(ctx->i32, 2, 0), "");
50
51 if (ctx->screen->info.chip_class == VI) {
52 /* On VI, the descriptor contains the size in bytes,
53 * but TXQ must return the size in elements.
54 * The stride is always non-zero for resources using TXQ.
55 */
56 LLVMValueRef stride =
57 LLVMBuildExtractElement(builder, descriptor,
58 ctx->i32_1, "");
59 stride = LLVMBuildLShr(builder, stride,
60 LLVMConstInt(ctx->i32, 16, 0), "");
61 stride = LLVMBuildAnd(builder, stride,
62 LLVMConstInt(ctx->i32, 0x3FFF, 0), "");
63
64 size = LLVMBuildUDiv(builder, size, stride, "");
65 }
66
67 return size;
68 }
69
70 static LLVMValueRef
71 shader_buffer_fetch_rsrc(struct si_shader_context *ctx,
72 const struct tgsi_full_src_register *reg,
73 bool ubo)
74 {
75 LLVMValueRef index;
76
77 if (!reg->Register.Indirect) {
78 index = LLVMConstInt(ctx->i32, reg->Register.Index, false);
79 } else {
80 index = si_get_indirect_index(ctx, &reg->Indirect,
81 1, reg->Register.Index);
82 }
83
84 if (ubo)
85 return ctx->abi.load_ubo(&ctx->abi, index);
86 else
87 return ctx->abi.load_ssbo(&ctx->abi, index, false);
88 }
89
90 static enum ac_image_dim
91 ac_texture_dim_from_tgsi_target(struct si_screen *screen, enum tgsi_texture_type target)
92 {
93 switch (target) {
94 case TGSI_TEXTURE_1D:
95 case TGSI_TEXTURE_SHADOW1D:
96 if (screen->info.chip_class >= GFX9)
97 return ac_image_2d;
98 return ac_image_1d;
99 case TGSI_TEXTURE_2D:
100 case TGSI_TEXTURE_SHADOW2D:
101 case TGSI_TEXTURE_RECT:
102 case TGSI_TEXTURE_SHADOWRECT:
103 return ac_image_2d;
104 case TGSI_TEXTURE_3D:
105 return ac_image_3d;
106 case TGSI_TEXTURE_CUBE:
107 case TGSI_TEXTURE_SHADOWCUBE:
108 case TGSI_TEXTURE_CUBE_ARRAY:
109 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
110 return ac_image_cube;
111 case TGSI_TEXTURE_1D_ARRAY:
112 case TGSI_TEXTURE_SHADOW1D_ARRAY:
113 if (screen->info.chip_class >= GFX9)
114 return ac_image_2darray;
115 return ac_image_1darray;
116 case TGSI_TEXTURE_2D_ARRAY:
117 case TGSI_TEXTURE_SHADOW2D_ARRAY:
118 return ac_image_2darray;
119 case TGSI_TEXTURE_2D_MSAA:
120 return ac_image_2dmsaa;
121 case TGSI_TEXTURE_2D_ARRAY_MSAA:
122 return ac_image_2darraymsaa;
123 default:
124 unreachable("unhandled texture type");
125 }
126 }
127
128 static enum ac_image_dim
129 ac_image_dim_from_tgsi_target(struct si_screen *screen, enum tgsi_texture_type target)
130 {
131 enum ac_image_dim dim = ac_texture_dim_from_tgsi_target(screen, target);
132
133 /* Match the resource type set in the descriptor. */
134 if (dim == ac_image_cube ||
135 (screen->info.chip_class <= VI && dim == ac_image_3d))
136 dim = ac_image_2darray;
137 else if (target == TGSI_TEXTURE_2D && screen->info.chip_class >= GFX9) {
138 /* When a single layer of a 3D texture is bound, the shader
139 * will refer to a 2D target, but the descriptor has a 3D type.
140 * Since the HW ignores BASE_ARRAY in this case, we need to
141 * send 3 coordinates. This doesn't hurt when the underlying
142 * texture is non-3D.
143 */
144 dim = ac_image_3d;
145 }
146
147 return dim;
148 }
149
150 /**
151 * Given a 256-bit resource descriptor, force the DCC enable bit to off.
152 *
153 * At least on Tonga, executing image stores on images with DCC enabled and
154 * non-trivial can eventually lead to lockups. This can occur when an
155 * application binds an image as read-only but then uses a shader that writes
156 * to it. The OpenGL spec allows almost arbitrarily bad behavior (including
157 * program termination) in this case, but it doesn't cost much to be a bit
158 * nicer: disabling DCC in the shader still leads to undefined results but
159 * avoids the lockup.
160 */
161 static LLVMValueRef force_dcc_off(struct si_shader_context *ctx,
162 LLVMValueRef rsrc)
163 {
164 if (ctx->screen->info.chip_class <= CIK) {
165 return rsrc;
166 } else {
167 LLVMValueRef i32_6 = LLVMConstInt(ctx->i32, 6, 0);
168 LLVMValueRef i32_C = LLVMConstInt(ctx->i32, C_008F28_COMPRESSION_EN, 0);
169 LLVMValueRef tmp;
170
171 tmp = LLVMBuildExtractElement(ctx->ac.builder, rsrc, i32_6, "");
172 tmp = LLVMBuildAnd(ctx->ac.builder, tmp, i32_C, "");
173 return LLVMBuildInsertElement(ctx->ac.builder, rsrc, tmp, i32_6, "");
174 }
175 }
176
177 LLVMValueRef si_load_image_desc(struct si_shader_context *ctx,
178 LLVMValueRef list, LLVMValueRef index,
179 enum ac_descriptor_type desc_type, bool dcc_off,
180 bool bindless)
181 {
182 LLVMBuilderRef builder = ctx->ac.builder;
183 LLVMValueRef rsrc;
184
185 if (desc_type == AC_DESC_BUFFER) {
186 index = ac_build_imad(&ctx->ac, index, LLVMConstInt(ctx->i32, 2, 0),
187 ctx->i32_1);
188 list = LLVMBuildPointerCast(builder, list,
189 ac_array_in_const32_addr_space(ctx->v4i32), "");
190 } else {
191 assert(desc_type == AC_DESC_IMAGE);
192 }
193
194 if (bindless)
195 rsrc = ac_build_load_to_sgpr_uint_wraparound(&ctx->ac, list, index);
196 else
197 rsrc = ac_build_load_to_sgpr(&ctx->ac, list, index);
198
199 if (desc_type == AC_DESC_IMAGE && dcc_off)
200 rsrc = force_dcc_off(ctx, rsrc);
201 return rsrc;
202 }
203
204 /**
205 * Load the resource descriptor for \p image.
206 */
207 static void
208 image_fetch_rsrc(
209 struct lp_build_tgsi_context *bld_base,
210 const struct tgsi_full_src_register *image,
211 bool is_store, unsigned target,
212 LLVMValueRef *rsrc)
213 {
214 struct si_shader_context *ctx = si_shader_context(bld_base);
215 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
216 ctx->param_samplers_and_images);
217 LLVMValueRef index;
218 bool dcc_off = is_store;
219
220 if (!image->Register.Indirect) {
221 const struct tgsi_shader_info *info = bld_base->info;
222 unsigned images_writemask = info->images_store |
223 info->images_atomic;
224
225 index = LLVMConstInt(ctx->i32,
226 si_get_image_slot(image->Register.Index), 0);
227
228 if (images_writemask & (1 << image->Register.Index))
229 dcc_off = true;
230 } else {
231 /* From the GL_ARB_shader_image_load_store extension spec:
232 *
233 * If a shader performs an image load, store, or atomic
234 * operation using an image variable declared as an array,
235 * and if the index used to select an individual element is
236 * negative or greater than or equal to the size of the
237 * array, the results of the operation are undefined but may
238 * not lead to termination.
239 */
240 index = si_get_bounded_indirect_index(ctx, &image->Indirect,
241 image->Register.Index,
242 ctx->num_images);
243 index = LLVMBuildSub(ctx->ac.builder,
244 LLVMConstInt(ctx->i32, SI_NUM_IMAGES - 1, 0),
245 index, "");
246 }
247
248 bool bindless = false;
249
250 if (image->Register.File != TGSI_FILE_IMAGE) {
251 /* Bindless descriptors are accessible from a different pair of
252 * user SGPR indices.
253 */
254 rsrc_ptr = LLVMGetParam(ctx->main_fn,
255 ctx->param_bindless_samplers_and_images);
256 index = lp_build_emit_fetch_src(bld_base, image,
257 TGSI_TYPE_UNSIGNED, 0);
258
259 /* For simplicity, bindless image descriptors use fixed
260 * 16-dword slots for now.
261 */
262 index = LLVMBuildMul(ctx->ac.builder, index,
263 LLVMConstInt(ctx->i32, 2, 0), "");
264 bindless = true;
265 }
266
267 *rsrc = si_load_image_desc(ctx, rsrc_ptr, index,
268 target == TGSI_TEXTURE_BUFFER ? AC_DESC_BUFFER : AC_DESC_IMAGE,
269 dcc_off, bindless);
270 }
271
272 static void image_fetch_coords(
273 struct lp_build_tgsi_context *bld_base,
274 const struct tgsi_full_instruction *inst,
275 unsigned src, LLVMValueRef desc,
276 LLVMValueRef *coords)
277 {
278 struct si_shader_context *ctx = si_shader_context(bld_base);
279 LLVMBuilderRef builder = ctx->ac.builder;
280 unsigned target = inst->Memory.Texture;
281 unsigned num_coords = tgsi_util_get_texture_coord_dim(target);
282 LLVMValueRef tmp;
283 int chan;
284
285 if (target == TGSI_TEXTURE_2D_MSAA ||
286 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
287 /* Need the sample index as well. */
288 num_coords++;
289 }
290
291 for (chan = 0; chan < num_coords; ++chan) {
292 tmp = lp_build_emit_fetch(bld_base, inst, src, chan);
293 tmp = ac_to_integer(&ctx->ac, tmp);
294 coords[chan] = tmp;
295 }
296
297 if (ctx->screen->info.chip_class >= GFX9) {
298 /* 1D textures are allocated and used as 2D on GFX9. */
299 if (target == TGSI_TEXTURE_1D) {
300 coords[1] = ctx->i32_0;
301 } else if (target == TGSI_TEXTURE_1D_ARRAY) {
302 coords[2] = coords[1];
303 coords[1] = ctx->i32_0;
304 } else if (target == TGSI_TEXTURE_2D) {
305 /* The hw can't bind a slice of a 3D image as a 2D
306 * image, because it ignores BASE_ARRAY if the target
307 * is 3D. The workaround is to read BASE_ARRAY and set
308 * it as the 3rd address operand for all 2D images.
309 */
310 LLVMValueRef first_layer, const5, mask;
311
312 const5 = LLVMConstInt(ctx->i32, 5, 0);
313 mask = LLVMConstInt(ctx->i32, S_008F24_BASE_ARRAY(~0), 0);
314 first_layer = LLVMBuildExtractElement(builder, desc, const5, "");
315 first_layer = LLVMBuildAnd(builder, first_layer, mask, "");
316
317 coords[2] = first_layer;
318 }
319 }
320 }
321
322 static unsigned get_cache_policy(struct si_shader_context *ctx,
323 const struct tgsi_full_instruction *inst,
324 bool atomic, bool may_store_unaligned,
325 bool writeonly_memory)
326 {
327 unsigned cache_policy = 0;
328
329 if (!atomic &&
330 /* SI has a TC L1 bug causing corruption of 8bit/16bit stores.
331 * All store opcodes not aligned to a dword are affected.
332 * The only way to get unaligned stores in radeonsi is through
333 * shader images. */
334 ((may_store_unaligned && ctx->screen->info.chip_class == SI) ||
335 /* If this is write-only, don't keep data in L1 to prevent
336 * evicting L1 cache lines that may be needed by other
337 * instructions. */
338 writeonly_memory ||
339 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE)))
340 cache_policy |= ac_glc;
341
342 if (inst->Memory.Qualifier & TGSI_MEMORY_STREAM_CACHE_POLICY)
343 cache_policy |= ac_slc;
344
345 return cache_policy;
346 }
347
348 static LLVMValueRef get_memory_ptr(struct si_shader_context *ctx,
349 const struct tgsi_full_instruction *inst,
350 LLVMTypeRef type, int arg)
351 {
352 LLVMBuilderRef builder = ctx->ac.builder;
353 LLVMValueRef offset, ptr;
354 int addr_space;
355
356 offset = lp_build_emit_fetch(&ctx->bld_base, inst, arg, 0);
357 offset = ac_to_integer(&ctx->ac, offset);
358
359 ptr = ctx->ac.lds;
360 ptr = LLVMBuildGEP(builder, ptr, &offset, 1, "");
361 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
362 ptr = LLVMBuildBitCast(builder, ptr, LLVMPointerType(type, addr_space), "");
363
364 return ptr;
365 }
366
367 static void load_emit_memory(
368 struct si_shader_context *ctx,
369 struct lp_build_emit_data *emit_data)
370 {
371 const struct tgsi_full_instruction *inst = emit_data->inst;
372 unsigned writemask = inst->Dst[0].Register.WriteMask;
373 LLVMValueRef channels[4], ptr, derived_ptr, index;
374 int chan;
375
376 ptr = get_memory_ptr(ctx, inst, ctx->f32, 1);
377
378 for (chan = 0; chan < 4; ++chan) {
379 if (!(writemask & (1 << chan))) {
380 channels[chan] = LLVMGetUndef(ctx->f32);
381 continue;
382 }
383
384 index = LLVMConstInt(ctx->i32, chan, 0);
385 derived_ptr = LLVMBuildGEP(ctx->ac.builder, ptr, &index, 1, "");
386 channels[chan] = LLVMBuildLoad(ctx->ac.builder, derived_ptr, "");
387 }
388 emit_data->output[emit_data->chan] = ac_build_gather_values(&ctx->ac, channels, 4);
389 }
390
391 /**
392 * Return true if the memory accessed by a LOAD or STORE instruction is
393 * read-only or write-only, respectively.
394 *
395 * \param shader_buffers_reverse_access_mask
396 * For LOAD, set this to (store | atomic) slot usage in the shader.
397 * For STORE, set this to (load | atomic) slot usage in the shader.
398 * \param images_reverse_access_mask Same as above, but for images.
399 */
400 static bool is_oneway_access_only(const struct tgsi_full_instruction *inst,
401 const struct tgsi_shader_info *info,
402 unsigned shader_buffers_reverse_access_mask,
403 unsigned images_reverse_access_mask)
404 {
405 /* RESTRICT means NOALIAS.
406 * If there are no writes, we can assume the accessed memory is read-only.
407 * If there are no reads, we can assume the accessed memory is write-only.
408 */
409 if (inst->Memory.Qualifier & TGSI_MEMORY_RESTRICT) {
410 unsigned reverse_access_mask;
411
412 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
413 reverse_access_mask = shader_buffers_reverse_access_mask;
414 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
415 reverse_access_mask = info->images_buffers &
416 images_reverse_access_mask;
417 } else {
418 reverse_access_mask = ~info->images_buffers &
419 images_reverse_access_mask;
420 }
421
422 if (inst->Src[0].Register.Indirect) {
423 if (!reverse_access_mask)
424 return true;
425 } else {
426 if (!(reverse_access_mask &
427 (1u << inst->Src[0].Register.Index)))
428 return true;
429 }
430 }
431
432 /* If there are no buffer writes (for both shader buffers & image
433 * buffers), it implies that buffer memory is read-only.
434 * If there are no buffer reads (for both shader buffers & image
435 * buffers), it implies that buffer memory is write-only.
436 *
437 * Same for the case when there are no writes/reads for non-buffer
438 * images.
439 */
440 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
441 (inst->Memory.Texture == TGSI_TEXTURE_BUFFER &&
442 (inst->Src[0].Register.File == TGSI_FILE_IMAGE ||
443 tgsi_is_bindless_image_file(inst->Src[0].Register.File)))) {
444 if (!shader_buffers_reverse_access_mask &&
445 !(info->images_buffers & images_reverse_access_mask))
446 return true;
447 } else {
448 if (!(~info->images_buffers & images_reverse_access_mask))
449 return true;
450 }
451 return false;
452 }
453
454 static void load_emit(
455 const struct lp_build_tgsi_action *action,
456 struct lp_build_tgsi_context *bld_base,
457 struct lp_build_emit_data *emit_data)
458 {
459 struct si_shader_context *ctx = si_shader_context(bld_base);
460 const struct tgsi_full_instruction * inst = emit_data->inst;
461 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
462 bool can_speculate = false;
463 LLVMValueRef vindex = ctx->i32_0;
464 LLVMValueRef voffset = ctx->i32_0;
465 struct ac_image_args args = {};
466
467 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
468 load_emit_memory(ctx, emit_data);
469 return;
470 }
471
472 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
473 inst->Src[0].Register.File == TGSI_FILE_CONSTBUF) {
474 bool ubo = inst->Src[0].Register.File == TGSI_FILE_CONSTBUF;
475 args.resource = shader_buffer_fetch_rsrc(ctx, &inst->Src[0], ubo);
476 voffset = ac_to_integer(&ctx->ac, lp_build_emit_fetch(bld_base, inst, 1, 0));
477 } else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE ||
478 tgsi_is_bindless_image_file(inst->Src[0].Register.File)) {
479 unsigned target = inst->Memory.Texture;
480
481 image_fetch_rsrc(bld_base, &inst->Src[0], false, target, &args.resource);
482 image_fetch_coords(bld_base, inst, 1, args.resource, args.coords);
483 vindex = args.coords[0]; /* for buffers only */
484 }
485
486 if (inst->Src[0].Register.File == TGSI_FILE_CONSTBUF) {
487 emit_data->output[emit_data->chan] =
488 ac_build_buffer_load(&ctx->ac, args.resource,
489 util_last_bit(inst->Dst[0].Register.WriteMask),
490 NULL, voffset, NULL, 0, 0, 0, true, true);
491 return;
492 }
493
494 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
495 ac_build_waitcnt(&ctx->ac, VM_CNT);
496
497 can_speculate = !(inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE) &&
498 is_oneway_access_only(inst, info,
499 info->shader_buffers_store |
500 info->shader_buffers_atomic,
501 info->images_store |
502 info->images_atomic);
503 args.cache_policy = get_cache_policy(ctx, inst, false, false, false);
504
505 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
506 /* Don't use SMEM for shader buffer loads, because LLVM doesn't
507 * select SMEM for SI.load.const with a non-constant offset, and
508 * constant offsets practically don't exist with shader buffers.
509 *
510 * Also, SI.load.const doesn't use inst_offset when it's lowered
511 * to VMEM, so we just end up with more VALU instructions in the end
512 * and no benefit.
513 *
514 * TODO: Remove this line once LLVM can select SMEM with a non-constant
515 * offset, and can derive inst_offset when VMEM is selected.
516 * After that, si_memory_barrier should invalidate sL1 for shader
517 * buffers.
518 */
519 emit_data->output[emit_data->chan] =
520 ac_build_buffer_load(&ctx->ac, args.resource,
521 util_last_bit(inst->Dst[0].Register.WriteMask),
522 NULL, voffset, NULL, 0,
523 !!(args.cache_policy & ac_glc),
524 !!(args.cache_policy & ac_slc),
525 can_speculate, false);
526 return;
527 }
528
529 if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
530 unsigned num_channels = util_last_bit(inst->Dst[0].Register.WriteMask);
531 LLVMValueRef result =
532 ac_build_buffer_load_format(&ctx->ac,
533 args.resource,
534 vindex,
535 ctx->i32_0,
536 num_channels,
537 !!(args.cache_policy & ac_glc),
538 can_speculate);
539 emit_data->output[emit_data->chan] =
540 ac_build_expand_to_vec4(&ctx->ac, result, num_channels);
541 } else {
542 args.opcode = ac_image_load;
543 args.dim = ac_image_dim_from_tgsi_target(ctx->screen, inst->Memory.Texture);
544 args.attributes = ac_get_load_intr_attribs(can_speculate);
545 args.dmask = 0xf;
546
547 emit_data->output[emit_data->chan] =
548 ac_build_image_opcode(&ctx->ac, &args);
549 }
550 }
551
552 static void store_emit_buffer(struct si_shader_context *ctx,
553 LLVMValueRef resource,
554 unsigned writemask,
555 LLVMValueRef value,
556 LLVMValueRef voffset,
557 unsigned cache_policy,
558 bool writeonly_memory)
559 {
560 LLVMBuilderRef builder = ctx->ac.builder;
561 LLVMValueRef base_data = value;
562 LLVMValueRef base_offset = voffset;
563
564 while (writemask) {
565 int start, count;
566 const char *intrinsic_name;
567 LLVMValueRef data, voff;
568
569 u_bit_scan_consecutive_range(&writemask, &start, &count);
570
571 /* Due to an LLVM limitation, split 3-element writes
572 * into a 2-element and a 1-element write. */
573 if (count == 3) {
574 writemask |= 1 << (start + 2);
575 count = 2;
576 }
577
578 if (count == 4) {
579 data = base_data;
580 intrinsic_name = "llvm.amdgcn.buffer.store.v4f32";
581 } else if (count == 2) {
582 LLVMValueRef values[2] = {
583 LLVMBuildExtractElement(builder, base_data,
584 LLVMConstInt(ctx->i32, start, 0), ""),
585 LLVMBuildExtractElement(builder, base_data,
586 LLVMConstInt(ctx->i32, start + 1, 0), ""),
587 };
588
589 data = ac_build_gather_values(&ctx->ac, values, 2);
590 intrinsic_name = "llvm.amdgcn.buffer.store.v2f32";
591 } else {
592 assert(count == 1);
593 data = LLVMBuildExtractElement(
594 builder, base_data,
595 LLVMConstInt(ctx->i32, start, 0), "");
596 intrinsic_name = "llvm.amdgcn.buffer.store.f32";
597 }
598
599 voff = base_offset;
600 if (start != 0) {
601 voff = LLVMBuildAdd(
602 builder, voff,
603 LLVMConstInt(ctx->i32, start * 4, 0), "");
604 }
605
606 LLVMValueRef args[] = {
607 data,
608 resource,
609 ctx->i32_0, /* vindex */
610 voff,
611 LLVMConstInt(ctx->i1, !!(cache_policy & ac_glc), 0),
612 LLVMConstInt(ctx->i1, !!(cache_policy & ac_slc), 0),
613 };
614 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->voidt, args, 6,
615 ac_get_store_intr_attribs(writeonly_memory));
616 }
617 }
618
619 static void store_emit_memory(
620 struct si_shader_context *ctx,
621 struct lp_build_emit_data *emit_data)
622 {
623 const struct tgsi_full_instruction *inst = emit_data->inst;
624 LLVMBuilderRef builder = ctx->ac.builder;
625 unsigned writemask = inst->Dst[0].Register.WriteMask;
626 LLVMValueRef ptr, derived_ptr, data, index;
627 int chan;
628
629 ptr = get_memory_ptr(ctx, inst, ctx->f32, 0);
630
631 for (chan = 0; chan < 4; ++chan) {
632 if (!(writemask & (1 << chan))) {
633 continue;
634 }
635 data = lp_build_emit_fetch(&ctx->bld_base, inst, 1, chan);
636 index = LLVMConstInt(ctx->i32, chan, 0);
637 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
638 LLVMBuildStore(builder, data, derived_ptr);
639 }
640 }
641
642 static void store_emit(
643 const struct lp_build_tgsi_action *action,
644 struct lp_build_tgsi_context *bld_base,
645 struct lp_build_emit_data *emit_data)
646 {
647 struct si_shader_context *ctx = si_shader_context(bld_base);
648 const struct tgsi_full_instruction * inst = emit_data->inst;
649 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
650 struct tgsi_full_src_register resource_reg =
651 tgsi_full_src_register_from_dst(&inst->Dst[0]);
652 unsigned target = inst->Memory.Texture;
653 bool writeonly_memory = is_oneway_access_only(inst, info,
654 info->shader_buffers_load |
655 info->shader_buffers_atomic,
656 info->images_load |
657 info->images_atomic);
658 bool is_image = inst->Dst[0].Register.File == TGSI_FILE_IMAGE ||
659 tgsi_is_bindless_image_file(inst->Dst[0].Register.File);
660 LLVMValueRef chans[4], value;
661 LLVMValueRef vindex = ctx->i32_0;
662 LLVMValueRef voffset = ctx->i32_0;
663 struct ac_image_args args = {};
664
665 if (inst->Dst[0].Register.File == TGSI_FILE_MEMORY) {
666 store_emit_memory(ctx, emit_data);
667 return;
668 }
669
670 for (unsigned chan = 0; chan < 4; ++chan)
671 chans[chan] = lp_build_emit_fetch(bld_base, inst, 1, chan);
672
673 value = ac_build_gather_values(&ctx->ac, chans, 4);
674
675 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
676 args.resource = shader_buffer_fetch_rsrc(ctx, &resource_reg, false);
677 voffset = ac_to_integer(&ctx->ac, lp_build_emit_fetch(bld_base, inst, 0, 0));
678 } else if (is_image) {
679 image_fetch_rsrc(bld_base, &resource_reg, true, target, &args.resource);
680 image_fetch_coords(bld_base, inst, 0, args.resource, args.coords);
681 vindex = args.coords[0]; /* for buffers only */
682 } else {
683 unreachable("unexpected register file");
684 }
685
686 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
687 ac_build_waitcnt(&ctx->ac, VM_CNT);
688
689 args.cache_policy = get_cache_policy(ctx, inst,
690 false, /* atomic */
691 is_image, /* may_store_unaligned */
692 writeonly_memory);
693
694 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
695 store_emit_buffer(ctx, args.resource, inst->Dst[0].Register.WriteMask,
696 value, voffset, args.cache_policy, writeonly_memory);
697 return;
698 }
699
700 if (target == TGSI_TEXTURE_BUFFER) {
701 LLVMValueRef buf_args[] = {
702 value,
703 args.resource,
704 vindex,
705 ctx->i32_0, /* voffset */
706 LLVMConstInt(ctx->i1, !!(args.cache_policy & ac_glc), 0),
707 LLVMConstInt(ctx->i1, !!(args.cache_policy & ac_slc), 0),
708 };
709
710 emit_data->output[emit_data->chan] = ac_build_intrinsic(
711 &ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32",
712 ctx->voidt, buf_args, 6,
713 ac_get_store_intr_attribs(writeonly_memory));
714 } else {
715 args.opcode = ac_image_store;
716 args.data[0] = value;
717 args.dim = ac_image_dim_from_tgsi_target(ctx->screen, inst->Memory.Texture);
718 args.attributes = ac_get_store_intr_attribs(writeonly_memory);
719 args.dmask = 0xf;
720
721 emit_data->output[emit_data->chan] =
722 ac_build_image_opcode(&ctx->ac, &args);
723 }
724 }
725
726 static void atomic_emit_memory(struct si_shader_context *ctx,
727 struct lp_build_emit_data *emit_data) {
728 LLVMBuilderRef builder = ctx->ac.builder;
729 const struct tgsi_full_instruction * inst = emit_data->inst;
730 LLVMValueRef ptr, result, arg;
731
732 ptr = get_memory_ptr(ctx, inst, ctx->i32, 1);
733
734 arg = lp_build_emit_fetch(&ctx->bld_base, inst, 2, 0);
735 arg = ac_to_integer(&ctx->ac, arg);
736
737 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
738 LLVMValueRef new_data;
739 new_data = lp_build_emit_fetch(&ctx->bld_base,
740 inst, 3, 0);
741
742 new_data = ac_to_integer(&ctx->ac, new_data);
743
744 result = LLVMBuildAtomicCmpXchg(builder, ptr, arg, new_data,
745 LLVMAtomicOrderingSequentiallyConsistent,
746 LLVMAtomicOrderingSequentiallyConsistent,
747 false);
748
749 result = LLVMBuildExtractValue(builder, result, 0, "");
750 } else {
751 LLVMAtomicRMWBinOp op;
752
753 switch(inst->Instruction.Opcode) {
754 case TGSI_OPCODE_ATOMUADD:
755 op = LLVMAtomicRMWBinOpAdd;
756 break;
757 case TGSI_OPCODE_ATOMXCHG:
758 op = LLVMAtomicRMWBinOpXchg;
759 break;
760 case TGSI_OPCODE_ATOMAND:
761 op = LLVMAtomicRMWBinOpAnd;
762 break;
763 case TGSI_OPCODE_ATOMOR:
764 op = LLVMAtomicRMWBinOpOr;
765 break;
766 case TGSI_OPCODE_ATOMXOR:
767 op = LLVMAtomicRMWBinOpXor;
768 break;
769 case TGSI_OPCODE_ATOMUMIN:
770 op = LLVMAtomicRMWBinOpUMin;
771 break;
772 case TGSI_OPCODE_ATOMUMAX:
773 op = LLVMAtomicRMWBinOpUMax;
774 break;
775 case TGSI_OPCODE_ATOMIMIN:
776 op = LLVMAtomicRMWBinOpMin;
777 break;
778 case TGSI_OPCODE_ATOMIMAX:
779 op = LLVMAtomicRMWBinOpMax;
780 break;
781 default:
782 unreachable("unknown atomic opcode");
783 }
784
785 result = LLVMBuildAtomicRMW(builder, op, ptr, arg,
786 LLVMAtomicOrderingSequentiallyConsistent,
787 false);
788 }
789 emit_data->output[emit_data->chan] =
790 LLVMBuildBitCast(builder, result, ctx->f32, "");
791 }
792
793 static void atomic_emit(
794 const struct lp_build_tgsi_action *action,
795 struct lp_build_tgsi_context *bld_base,
796 struct lp_build_emit_data *emit_data)
797 {
798 struct si_shader_context *ctx = si_shader_context(bld_base);
799 const struct tgsi_full_instruction * inst = emit_data->inst;
800 struct ac_image_args args = {};
801 unsigned num_data = 0;
802 LLVMValueRef vindex = ctx->i32_0;
803 LLVMValueRef voffset = ctx->i32_0;
804
805 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
806 atomic_emit_memory(ctx, emit_data);
807 return;
808 }
809
810 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
811 /* llvm.amdgcn.image/buffer.atomic.cmpswap reflect the hardware order
812 * of arguments, which is reversed relative to TGSI (and GLSL)
813 */
814 args.data[num_data++] =
815 ac_to_integer(&ctx->ac, lp_build_emit_fetch(bld_base, inst, 3, 0));
816 }
817
818 args.data[num_data++] =
819 ac_to_integer(&ctx->ac, lp_build_emit_fetch(bld_base, inst, 2, 0));
820 args.cache_policy = get_cache_policy(ctx, inst, true, false, false);
821
822 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
823 args.resource = shader_buffer_fetch_rsrc(ctx, &inst->Src[0], false);
824 voffset = ac_to_integer(&ctx->ac, lp_build_emit_fetch(bld_base, inst, 1, 0));
825 } else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE ||
826 tgsi_is_bindless_image_file(inst->Src[0].Register.File)) {
827 image_fetch_rsrc(bld_base, &inst->Src[0], true,
828 inst->Memory.Texture, &args.resource);
829 image_fetch_coords(bld_base, inst, 1, args.resource, args.coords);
830 vindex = args.coords[0]; /* for buffers only */
831 }
832
833 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
834 inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
835 LLVMValueRef buf_args[7];
836 unsigned num_args = 0;
837
838 buf_args[num_args++] = args.data[0];
839 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
840 buf_args[num_args++] = args.data[1];
841
842 buf_args[num_args++] = args.resource;
843 buf_args[num_args++] = vindex;
844 buf_args[num_args++] = voffset;
845 buf_args[num_args++] = args.cache_policy & ac_slc ? ctx->i1true : ctx->i1false;
846
847 char intrinsic_name[40];
848 snprintf(intrinsic_name, sizeof(intrinsic_name),
849 "llvm.amdgcn.buffer.atomic.%s", action->intr_name);
850 emit_data->output[emit_data->chan] =
851 ac_to_float(&ctx->ac,
852 ac_build_intrinsic(&ctx->ac, intrinsic_name,
853 ctx->i32, buf_args, num_args, 0));
854 } else {
855 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
856 args.opcode = ac_image_atomic_cmpswap;
857 } else {
858 args.opcode = ac_image_atomic;
859 switch (inst->Instruction.Opcode) {
860 case TGSI_OPCODE_ATOMXCHG: args.atomic = ac_atomic_swap; break;
861 case TGSI_OPCODE_ATOMUADD: args.atomic = ac_atomic_add; break;
862 case TGSI_OPCODE_ATOMAND: args.atomic = ac_atomic_and; break;
863 case TGSI_OPCODE_ATOMOR: args.atomic = ac_atomic_or; break;
864 case TGSI_OPCODE_ATOMXOR: args.atomic = ac_atomic_xor; break;
865 case TGSI_OPCODE_ATOMUMIN: args.atomic = ac_atomic_umin; break;
866 case TGSI_OPCODE_ATOMUMAX: args.atomic = ac_atomic_umax; break;
867 case TGSI_OPCODE_ATOMIMIN: args.atomic = ac_atomic_smin; break;
868 case TGSI_OPCODE_ATOMIMAX: args.atomic = ac_atomic_smax; break;
869 default: unreachable("unhandled image atomic");
870 }
871 }
872
873 args.dim = ac_image_dim_from_tgsi_target(ctx->screen, inst->Memory.Texture);
874 emit_data->output[emit_data->chan] =
875 ac_to_float(&ctx->ac, ac_build_image_opcode(&ctx->ac, &args));
876 }
877 }
878
879 static LLVMValueRef fix_resinfo(struct si_shader_context *ctx,
880 unsigned target, LLVMValueRef out)
881 {
882 LLVMBuilderRef builder = ctx->ac.builder;
883
884 /* 1D textures are allocated and used as 2D on GFX9. */
885 if (ctx->screen->info.chip_class >= GFX9 &&
886 (target == TGSI_TEXTURE_1D_ARRAY ||
887 target == TGSI_TEXTURE_SHADOW1D_ARRAY)) {
888 LLVMValueRef layers =
889 LLVMBuildExtractElement(builder, out,
890 LLVMConstInt(ctx->i32, 2, 0), "");
891 out = LLVMBuildInsertElement(builder, out, layers,
892 ctx->i32_1, "");
893 }
894
895 /* Divide the number of layers by 6 to get the number of cubes. */
896 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
897 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
898 LLVMValueRef imm2 = LLVMConstInt(ctx->i32, 2, 0);
899
900 LLVMValueRef z = LLVMBuildExtractElement(builder, out, imm2, "");
901 z = LLVMBuildSDiv(builder, z, LLVMConstInt(ctx->i32, 6, 0), "");
902
903 out = LLVMBuildInsertElement(builder, out, z, imm2, "");
904 }
905 return out;
906 }
907
908 static void resq_emit(
909 const struct lp_build_tgsi_action *action,
910 struct lp_build_tgsi_context *bld_base,
911 struct lp_build_emit_data *emit_data)
912 {
913 struct si_shader_context *ctx = si_shader_context(bld_base);
914 LLVMBuilderRef builder = ctx->ac.builder;
915 const struct tgsi_full_instruction *inst = emit_data->inst;
916 const struct tgsi_full_src_register *reg =
917 &inst->Src[inst->Instruction.Opcode == TGSI_OPCODE_TXQ ? 1 : 0];
918
919 if (reg->Register.File == TGSI_FILE_BUFFER) {
920 LLVMValueRef rsrc = shader_buffer_fetch_rsrc(ctx, reg, false);
921
922 emit_data->output[emit_data->chan] =
923 LLVMBuildExtractElement(builder, rsrc,
924 LLVMConstInt(ctx->i32, 2, 0), "");
925 return;
926 }
927
928 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ &&
929 inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
930 LLVMValueRef rsrc;
931
932 tex_fetch_ptrs(bld_base, emit_data, &rsrc, NULL, NULL);
933 /* Read the size from the buffer descriptor directly. */
934 emit_data->output[emit_data->chan] =
935 get_buffer_size(bld_base, rsrc);
936 return;
937 }
938
939 if (inst->Instruction.Opcode == TGSI_OPCODE_RESQ &&
940 inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
941 LLVMValueRef rsrc;
942
943 image_fetch_rsrc(bld_base, reg, false, inst->Memory.Texture, &rsrc);
944 emit_data->output[emit_data->chan] =
945 get_buffer_size(bld_base, rsrc);
946 return;
947 }
948
949 unsigned target;
950
951 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ) {
952 target = inst->Texture.Texture;
953 } else {
954 if (inst->Memory.Texture == TGSI_TEXTURE_3D)
955 target = TGSI_TEXTURE_2D_ARRAY;
956 else
957 target = inst->Memory.Texture;
958 }
959
960 struct ac_image_args args = {};
961 args.opcode = ac_image_get_resinfo;
962 args.dim = ac_texture_dim_from_tgsi_target(ctx->screen, target);
963 args.dmask = 0xf;
964
965 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ) {
966 tex_fetch_ptrs(bld_base, emit_data, &args.resource, NULL, NULL);
967 args.lod = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
968 } else {
969 image_fetch_rsrc(bld_base, reg, false, target, &args.resource);
970 args.lod = ctx->i32_0;
971 }
972
973 emit_data->output[emit_data->chan] =
974 fix_resinfo(ctx, target, ac_build_image_opcode(&ctx->ac, &args));
975 }
976
977 /**
978 * Load an image view, fmask view. or sampler state descriptor.
979 */
980 LLVMValueRef si_load_sampler_desc(struct si_shader_context *ctx,
981 LLVMValueRef list, LLVMValueRef index,
982 enum ac_descriptor_type type)
983 {
984 LLVMBuilderRef builder = ctx->ac.builder;
985
986 switch (type) {
987 case AC_DESC_IMAGE:
988 /* The image is at [0:7]. */
989 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
990 break;
991 case AC_DESC_BUFFER:
992 /* The buffer is in [4:7]. */
993 index = ac_build_imad(&ctx->ac, index, LLVMConstInt(ctx->i32, 4, 0),
994 ctx->i32_1);
995 list = LLVMBuildPointerCast(builder, list,
996 ac_array_in_const32_addr_space(ctx->v4i32), "");
997 break;
998 case AC_DESC_FMASK:
999 /* The FMASK is at [8:15]. */
1000 index = ac_build_imad(&ctx->ac, index, LLVMConstInt(ctx->i32, 2, 0),
1001 ctx->i32_1);
1002 break;
1003 case AC_DESC_SAMPLER:
1004 /* The sampler state is at [12:15]. */
1005 index = ac_build_imad(&ctx->ac, index, LLVMConstInt(ctx->i32, 4, 0),
1006 LLVMConstInt(ctx->i32, 3, 0));
1007 list = LLVMBuildPointerCast(builder, list,
1008 ac_array_in_const32_addr_space(ctx->v4i32), "");
1009 break;
1010 }
1011
1012 return ac_build_load_to_sgpr(&ctx->ac, list, index);
1013 }
1014
1015 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
1016 *
1017 * SI-CI:
1018 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
1019 * filtering manually. The driver sets img7 to a mask clearing
1020 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
1021 * s_and_b32 samp0, samp0, img7
1022 *
1023 * VI:
1024 * The ANISO_OVERRIDE sampler field enables this fix in TA.
1025 */
1026 static LLVMValueRef sici_fix_sampler_aniso(struct si_shader_context *ctx,
1027 LLVMValueRef res, LLVMValueRef samp)
1028 {
1029 LLVMValueRef img7, samp0;
1030
1031 if (ctx->screen->info.chip_class >= VI)
1032 return samp;
1033
1034 img7 = LLVMBuildExtractElement(ctx->ac.builder, res,
1035 LLVMConstInt(ctx->i32, 7, 0), "");
1036 samp0 = LLVMBuildExtractElement(ctx->ac.builder, samp,
1037 ctx->i32_0, "");
1038 samp0 = LLVMBuildAnd(ctx->ac.builder, samp0, img7, "");
1039 return LLVMBuildInsertElement(ctx->ac.builder, samp, samp0,
1040 ctx->i32_0, "");
1041 }
1042
1043 static void tex_fetch_ptrs(struct lp_build_tgsi_context *bld_base,
1044 struct lp_build_emit_data *emit_data,
1045 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
1046 LLVMValueRef *fmask_ptr)
1047 {
1048 struct si_shader_context *ctx = si_shader_context(bld_base);
1049 LLVMValueRef list = LLVMGetParam(ctx->main_fn, ctx->param_samplers_and_images);
1050 const struct tgsi_full_instruction *inst = emit_data->inst;
1051 const struct tgsi_full_src_register *reg;
1052 unsigned target = inst->Texture.Texture;
1053 unsigned sampler_src;
1054 LLVMValueRef index;
1055
1056 sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
1057 reg = &emit_data->inst->Src[sampler_src];
1058
1059 if (reg->Register.Indirect) {
1060 index = si_get_bounded_indirect_index(ctx,
1061 &reg->Indirect,
1062 reg->Register.Index,
1063 ctx->num_samplers);
1064 index = LLVMBuildAdd(ctx->ac.builder, index,
1065 LLVMConstInt(ctx->i32, SI_NUM_IMAGES / 2, 0), "");
1066 } else {
1067 index = LLVMConstInt(ctx->i32,
1068 si_get_sampler_slot(reg->Register.Index), 0);
1069 }
1070
1071 if (reg->Register.File != TGSI_FILE_SAMPLER) {
1072 /* Bindless descriptors are accessible from a different pair of
1073 * user SGPR indices.
1074 */
1075 list = LLVMGetParam(ctx->main_fn,
1076 ctx->param_bindless_samplers_and_images);
1077 index = lp_build_emit_fetch_src(bld_base, reg,
1078 TGSI_TYPE_UNSIGNED, 0);
1079
1080 /* Since bindless handle arithmetic can contain an unsigned integer
1081 * wraparound and si_load_sampler_desc assumes there isn't any,
1082 * use GEP without "inbounds" (inside ac_build_pointer_add)
1083 * to prevent incorrect code generation and hangs.
1084 */
1085 index = LLVMBuildMul(ctx->ac.builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
1086 list = ac_build_pointer_add(&ctx->ac, list, index);
1087 index = ctx->i32_0;
1088 }
1089
1090 if (target == TGSI_TEXTURE_BUFFER)
1091 *res_ptr = si_load_sampler_desc(ctx, list, index, AC_DESC_BUFFER);
1092 else
1093 *res_ptr = si_load_sampler_desc(ctx, list, index, AC_DESC_IMAGE);
1094
1095 if (samp_ptr)
1096 *samp_ptr = NULL;
1097 if (fmask_ptr)
1098 *fmask_ptr = NULL;
1099
1100 if (target == TGSI_TEXTURE_2D_MSAA ||
1101 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
1102 if (fmask_ptr)
1103 *fmask_ptr = si_load_sampler_desc(ctx, list, index,
1104 AC_DESC_FMASK);
1105 } else if (target != TGSI_TEXTURE_BUFFER) {
1106 if (samp_ptr) {
1107 *samp_ptr = si_load_sampler_desc(ctx, list, index,
1108 AC_DESC_SAMPLER);
1109 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
1110 }
1111 }
1112 }
1113
1114 /* Gather4 should follow the same rules as bilinear filtering, but the hardware
1115 * incorrectly forces nearest filtering if the texture format is integer.
1116 * The only effect it has on Gather4, which always returns 4 texels for
1117 * bilinear filtering, is that the final coordinates are off by 0.5 of
1118 * the texel size.
1119 *
1120 * The workaround is to subtract 0.5 from the unnormalized coordinates,
1121 * or (0.5 / size) from the normalized coordinates.
1122 *
1123 * However, cube textures with 8_8_8_8 data formats require a different
1124 * workaround of overriding the num format to USCALED/SSCALED. This would lose
1125 * precision in 32-bit data formats, so it needs to be applied dynamically at
1126 * runtime. In this case, return an i1 value that indicates whether the
1127 * descriptor was overridden (and hence a fixup of the sampler result is needed).
1128 */
1129 static LLVMValueRef
1130 si_lower_gather4_integer(struct si_shader_context *ctx,
1131 struct ac_image_args *args,
1132 unsigned target,
1133 enum tgsi_return_type return_type)
1134 {
1135 LLVMBuilderRef builder = ctx->ac.builder;
1136 LLVMValueRef wa_8888 = NULL;
1137 LLVMValueRef half_texel[2];
1138
1139 assert(return_type == TGSI_RETURN_TYPE_SINT ||
1140 return_type == TGSI_RETURN_TYPE_UINT);
1141
1142 if (target == TGSI_TEXTURE_CUBE ||
1143 target == TGSI_TEXTURE_CUBE_ARRAY) {
1144 LLVMValueRef formats;
1145 LLVMValueRef data_format;
1146 LLVMValueRef wa_formats;
1147
1148 formats = LLVMBuildExtractElement(builder, args->resource, ctx->i32_1, "");
1149
1150 data_format = LLVMBuildLShr(builder, formats,
1151 LLVMConstInt(ctx->i32, 20, false), "");
1152 data_format = LLVMBuildAnd(builder, data_format,
1153 LLVMConstInt(ctx->i32, (1u << 6) - 1, false), "");
1154 wa_8888 = LLVMBuildICmp(
1155 builder, LLVMIntEQ, data_format,
1156 LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false),
1157 "");
1158
1159 uint32_t wa_num_format =
1160 return_type == TGSI_RETURN_TYPE_UINT ?
1161 S_008F14_NUM_FORMAT_GFX6(V_008F14_IMG_NUM_FORMAT_USCALED) :
1162 S_008F14_NUM_FORMAT_GFX6(V_008F14_IMG_NUM_FORMAT_SSCALED);
1163 wa_formats = LLVMBuildAnd(builder, formats,
1164 LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false),
1165 "");
1166 wa_formats = LLVMBuildOr(builder, wa_formats,
1167 LLVMConstInt(ctx->i32, wa_num_format, false), "");
1168
1169 formats = LLVMBuildSelect(builder, wa_8888, wa_formats, formats, "");
1170 args->resource = LLVMBuildInsertElement(
1171 builder, args->resource, formats, ctx->i32_1, "");
1172 }
1173
1174 if (target == TGSI_TEXTURE_RECT ||
1175 target == TGSI_TEXTURE_SHADOWRECT) {
1176 assert(!wa_8888);
1177 half_texel[0] = half_texel[1] = LLVMConstReal(ctx->f32, -0.5);
1178 } else {
1179 struct ac_image_args resinfo = {};
1180 struct lp_build_if_state if_ctx;
1181
1182 if (wa_8888) {
1183 /* Skip the texture size query entirely if we don't need it. */
1184 lp_build_if(&if_ctx, &ctx->gallivm, LLVMBuildNot(builder, wa_8888, ""));
1185 }
1186
1187 /* Query the texture size. */
1188 resinfo.opcode = ac_image_get_resinfo;
1189 resinfo.dim = ac_texture_dim_from_tgsi_target(ctx->screen, target);
1190 resinfo.resource = args->resource;
1191 resinfo.sampler = args->sampler;
1192 resinfo.lod = ctx->ac.i32_0;
1193 resinfo.dmask = 0xf;
1194
1195 LLVMValueRef texsize =
1196 fix_resinfo(ctx, target,
1197 ac_build_image_opcode(&ctx->ac, &resinfo));
1198
1199 /* Compute -0.5 / size. */
1200 for (unsigned c = 0; c < 2; c++) {
1201 half_texel[c] =
1202 LLVMBuildExtractElement(builder, texsize,
1203 LLVMConstInt(ctx->i32, c, 0), "");
1204 half_texel[c] = LLVMBuildUIToFP(builder, half_texel[c], ctx->f32, "");
1205 half_texel[c] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, half_texel[c]);
1206 half_texel[c] = LLVMBuildFMul(builder, half_texel[c],
1207 LLVMConstReal(ctx->f32, -0.5), "");
1208 }
1209
1210 if (wa_8888) {
1211 lp_build_endif(&if_ctx);
1212
1213 LLVMBasicBlockRef bb[2] = { if_ctx.true_block, if_ctx.entry_block };
1214
1215 for (unsigned c = 0; c < 2; c++) {
1216 LLVMValueRef values[2] = { half_texel[c], ctx->ac.f32_0 };
1217 half_texel[c] = ac_build_phi(&ctx->ac, ctx->f32, 2,
1218 values, bb);
1219 }
1220 }
1221 }
1222
1223 for (unsigned c = 0; c < 2; c++) {
1224 LLVMValueRef tmp;
1225 tmp = ac_to_float(&ctx->ac, args->coords[c]);
1226 tmp = LLVMBuildFAdd(builder, tmp, half_texel[c], "");
1227 args->coords[c] = ac_to_integer(&ctx->ac, tmp);
1228 }
1229
1230 return wa_8888;
1231 }
1232
1233 /* The second half of the cube texture 8_8_8_8 integer workaround: adjust the
1234 * result after the gather operation.
1235 */
1236 static LLVMValueRef
1237 si_fix_gather4_integer_result(struct si_shader_context *ctx,
1238 LLVMValueRef result,
1239 enum tgsi_return_type return_type,
1240 LLVMValueRef wa)
1241 {
1242 LLVMBuilderRef builder = ctx->ac.builder;
1243
1244 assert(return_type == TGSI_RETURN_TYPE_SINT ||
1245 return_type == TGSI_RETURN_TYPE_UINT);
1246
1247 for (unsigned chan = 0; chan < 4; ++chan) {
1248 LLVMValueRef chanv = LLVMConstInt(ctx->i32, chan, false);
1249 LLVMValueRef value;
1250 LLVMValueRef wa_value;
1251
1252 value = LLVMBuildExtractElement(builder, result, chanv, "");
1253
1254 if (return_type == TGSI_RETURN_TYPE_UINT)
1255 wa_value = LLVMBuildFPToUI(builder, value, ctx->i32, "");
1256 else
1257 wa_value = LLVMBuildFPToSI(builder, value, ctx->i32, "");
1258 wa_value = ac_to_float(&ctx->ac, wa_value);
1259 value = LLVMBuildSelect(builder, wa, wa_value, value, "");
1260
1261 result = LLVMBuildInsertElement(builder, result, value, chanv, "");
1262 }
1263
1264 return result;
1265 }
1266
1267 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
1268 struct lp_build_tgsi_context *bld_base,
1269 struct lp_build_emit_data *emit_data)
1270 {
1271 struct si_shader_context *ctx = si_shader_context(bld_base);
1272 const struct tgsi_full_instruction *inst = emit_data->inst;
1273 unsigned opcode = inst->Instruction.Opcode;
1274 unsigned target = inst->Texture.Texture;
1275 struct ac_image_args args = {};
1276 int ref_pos = tgsi_util_get_shadow_ref_src_index(target);
1277 unsigned chan;
1278 bool has_offset = inst->Texture.NumOffsets > 0;
1279 LLVMValueRef fmask_ptr = NULL;
1280
1281 tex_fetch_ptrs(bld_base, emit_data, &args.resource, &args.sampler, &fmask_ptr);
1282
1283 if (target == TGSI_TEXTURE_BUFFER) {
1284 LLVMValueRef vindex = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
1285 unsigned num_channels =
1286 util_last_bit(inst->Dst[0].Register.WriteMask);
1287 LLVMValueRef result =
1288 ac_build_buffer_load_format(&ctx->ac,
1289 args.resource,
1290 vindex,
1291 ctx->i32_0,
1292 num_channels, false, true);
1293 emit_data->output[emit_data->chan] =
1294 ac_build_expand_to_vec4(&ctx->ac, result, num_channels);
1295 return;
1296 }
1297
1298 /* Fetch and project texture coordinates */
1299 args.coords[3] = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_W);
1300 for (chan = 0; chan < 3; chan++) {
1301 args.coords[chan] = lp_build_emit_fetch(bld_base, inst, 0, chan);
1302 if (opcode == TGSI_OPCODE_TXP)
1303 args.coords[chan] = ac_build_fdiv(&ctx->ac,
1304 args.coords[chan], args.coords[3]);
1305 }
1306
1307 if (opcode == TGSI_OPCODE_TXP)
1308 args.coords[3] = ctx->ac.f32_1;
1309
1310 /* Pack offsets. */
1311 if (has_offset &&
1312 opcode != TGSI_OPCODE_TXF &&
1313 opcode != TGSI_OPCODE_TXF_LZ) {
1314 /* The offsets are six-bit signed integers packed like this:
1315 * X=[5:0], Y=[13:8], and Z=[21:16].
1316 */
1317 LLVMValueRef offset[3], pack;
1318
1319 assert(inst->Texture.NumOffsets == 1);
1320
1321 for (chan = 0; chan < 3; chan++) {
1322 offset[chan] = lp_build_emit_fetch_texoffset(bld_base, inst, 0, chan);
1323 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
1324 LLVMConstInt(ctx->i32, 0x3f, 0), "");
1325 if (chan)
1326 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
1327 LLVMConstInt(ctx->i32, chan*8, 0), "");
1328 }
1329
1330 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
1331 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
1332 args.offset = pack;
1333 }
1334
1335 /* Pack LOD bias value */
1336 if (opcode == TGSI_OPCODE_TXB)
1337 args.bias = args.coords[3];
1338 if (opcode == TGSI_OPCODE_TXB2)
1339 args.bias = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
1340
1341 /* Pack depth comparison value */
1342 if (tgsi_is_shadow_target(target) && opcode != TGSI_OPCODE_LODQ) {
1343 LLVMValueRef z;
1344
1345 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
1346 z = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
1347 } else {
1348 assert(ref_pos >= 0);
1349 z = args.coords[ref_pos];
1350 }
1351
1352 /* Section 8.23.1 (Depth Texture Comparison Mode) of the
1353 * OpenGL 4.5 spec says:
1354 *
1355 * "If the texture’s internal format indicates a fixed-point
1356 * depth texture, then D_t and D_ref are clamped to the
1357 * range [0, 1]; otherwise no clamping is performed."
1358 *
1359 * TC-compatible HTILE promotes Z16 and Z24 to Z32_FLOAT,
1360 * so the depth comparison value isn't clamped for Z16 and
1361 * Z24 anymore. Do it manually here.
1362 */
1363 if (ctx->screen->info.chip_class >= VI) {
1364 LLVMValueRef upgraded;
1365 LLVMValueRef clamped;
1366 upgraded = LLVMBuildExtractElement(ctx->ac.builder, args.sampler,
1367 LLVMConstInt(ctx->i32, 3, false), "");
1368 upgraded = LLVMBuildLShr(ctx->ac.builder, upgraded,
1369 LLVMConstInt(ctx->i32, 29, false), "");
1370 upgraded = LLVMBuildTrunc(ctx->ac.builder, upgraded, ctx->i1, "");
1371 clamped = ac_build_clamp(&ctx->ac, z);
1372 z = LLVMBuildSelect(ctx->ac.builder, upgraded, clamped, z, "");
1373 }
1374
1375 args.compare = z;
1376 }
1377
1378 /* Pack user derivatives */
1379 if (opcode == TGSI_OPCODE_TXD) {
1380 int param, num_src_deriv_channels, num_dst_deriv_channels;
1381
1382 switch (target) {
1383 case TGSI_TEXTURE_3D:
1384 num_src_deriv_channels = 3;
1385 num_dst_deriv_channels = 3;
1386 break;
1387 case TGSI_TEXTURE_2D:
1388 case TGSI_TEXTURE_SHADOW2D:
1389 case TGSI_TEXTURE_RECT:
1390 case TGSI_TEXTURE_SHADOWRECT:
1391 case TGSI_TEXTURE_2D_ARRAY:
1392 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1393 num_src_deriv_channels = 2;
1394 num_dst_deriv_channels = 2;
1395 break;
1396 case TGSI_TEXTURE_CUBE:
1397 case TGSI_TEXTURE_SHADOWCUBE:
1398 case TGSI_TEXTURE_CUBE_ARRAY:
1399 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
1400 /* Cube derivatives will be converted to 2D. */
1401 num_src_deriv_channels = 3;
1402 num_dst_deriv_channels = 3;
1403 break;
1404 case TGSI_TEXTURE_1D:
1405 case TGSI_TEXTURE_SHADOW1D:
1406 case TGSI_TEXTURE_1D_ARRAY:
1407 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1408 num_src_deriv_channels = 1;
1409
1410 /* 1D textures are allocated and used as 2D on GFX9. */
1411 if (ctx->screen->info.chip_class >= GFX9) {
1412 num_dst_deriv_channels = 2;
1413 } else {
1414 num_dst_deriv_channels = 1;
1415 }
1416 break;
1417 default:
1418 unreachable("invalid target");
1419 }
1420
1421 for (param = 0; param < 2; param++) {
1422 for (chan = 0; chan < num_src_deriv_channels; chan++)
1423 args.derivs[param * num_dst_deriv_channels + chan] =
1424 lp_build_emit_fetch(bld_base, inst, param+1, chan);
1425
1426 /* Fill in the rest with zeros. */
1427 for (chan = num_src_deriv_channels;
1428 chan < num_dst_deriv_channels; chan++)
1429 args.derivs[param * num_dst_deriv_channels + chan] =
1430 ctx->ac.f32_0;
1431 }
1432 }
1433
1434 if (target == TGSI_TEXTURE_CUBE ||
1435 target == TGSI_TEXTURE_CUBE_ARRAY ||
1436 target == TGSI_TEXTURE_SHADOWCUBE ||
1437 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
1438 ac_prepare_cube_coords(&ctx->ac,
1439 opcode == TGSI_OPCODE_TXD,
1440 target == TGSI_TEXTURE_CUBE_ARRAY ||
1441 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY,
1442 opcode == TGSI_OPCODE_LODQ,
1443 args.coords, args.derivs);
1444 } else if (tgsi_is_array_sampler(target) &&
1445 opcode != TGSI_OPCODE_TXF &&
1446 opcode != TGSI_OPCODE_TXF_LZ &&
1447 ctx->screen->info.chip_class <= VI) {
1448 unsigned array_coord = target == TGSI_TEXTURE_1D_ARRAY ? 1 : 2;
1449 args.coords[array_coord] =
1450 ac_build_intrinsic(&ctx->ac, "llvm.rint.f32", ctx->f32,
1451 &args.coords[array_coord], 1, 0);
1452 }
1453
1454 /* 1D textures are allocated and used as 2D on GFX9. */
1455 if (ctx->screen->info.chip_class >= GFX9) {
1456 LLVMValueRef filler;
1457
1458 /* Use 0.5, so that we don't sample the border color. */
1459 if (opcode == TGSI_OPCODE_TXF ||
1460 opcode == TGSI_OPCODE_TXF_LZ)
1461 filler = ctx->i32_0;
1462 else
1463 filler = LLVMConstReal(ctx->f32, 0.5);
1464
1465 if (target == TGSI_TEXTURE_1D ||
1466 target == TGSI_TEXTURE_SHADOW1D) {
1467 args.coords[1] = filler;
1468 } else if (target == TGSI_TEXTURE_1D_ARRAY ||
1469 target == TGSI_TEXTURE_SHADOW1D_ARRAY) {
1470 args.coords[2] = args.coords[1];
1471 args.coords[1] = filler;
1472 }
1473 }
1474
1475 /* Pack LOD or sample index */
1476 if (opcode == TGSI_OPCODE_TXL)
1477 args.lod = args.coords[3];
1478 else if (opcode == TGSI_OPCODE_TXL2)
1479 args.lod = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
1480 else if (opcode == TGSI_OPCODE_TXF) {
1481 if (target == TGSI_TEXTURE_2D_MSAA) {
1482 /* No LOD, but move sample index into the right place. */
1483 args.coords[2] = args.coords[3];
1484 } else if (target != TGSI_TEXTURE_2D_ARRAY_MSAA) {
1485 args.lod = args.coords[3];
1486 }
1487 }
1488
1489 if (target == TGSI_TEXTURE_2D_MSAA ||
1490 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
1491 ac_apply_fmask_to_sample(&ctx->ac, fmask_ptr, args.coords,
1492 target == TGSI_TEXTURE_2D_ARRAY_MSAA);
1493 }
1494
1495 if (opcode == TGSI_OPCODE_TXF ||
1496 opcode == TGSI_OPCODE_TXF_LZ) {
1497 /* add tex offsets */
1498 if (inst->Texture.NumOffsets) {
1499 const struct tgsi_texture_offset *off = inst->TexOffsets;
1500
1501 assert(inst->Texture.NumOffsets == 1);
1502
1503 switch (target) {
1504 case TGSI_TEXTURE_3D:
1505 args.coords[2] =
1506 LLVMBuildAdd(ctx->ac.builder, args.coords[2],
1507 ctx->imms[off->Index * TGSI_NUM_CHANNELS + off->SwizzleZ], "");
1508 /* fall through */
1509 case TGSI_TEXTURE_2D:
1510 case TGSI_TEXTURE_SHADOW2D:
1511 case TGSI_TEXTURE_RECT:
1512 case TGSI_TEXTURE_SHADOWRECT:
1513 case TGSI_TEXTURE_2D_ARRAY:
1514 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1515 args.coords[1] =
1516 LLVMBuildAdd(ctx->ac.builder, args.coords[1],
1517 ctx->imms[off->Index * TGSI_NUM_CHANNELS + off->SwizzleY], "");
1518 /* fall through */
1519 case TGSI_TEXTURE_1D:
1520 case TGSI_TEXTURE_SHADOW1D:
1521 case TGSI_TEXTURE_1D_ARRAY:
1522 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1523 args.coords[0] =
1524 LLVMBuildAdd(ctx->ac.builder, args.coords[0],
1525 ctx->imms[off->Index * TGSI_NUM_CHANNELS + off->SwizzleX], "");
1526 break;
1527 /* texture offsets do not apply to other texture targets */
1528 }
1529 }
1530 }
1531
1532 if (opcode == TGSI_OPCODE_TG4) {
1533 unsigned gather_comp = 0;
1534
1535 /* DMASK was repurposed for GATHER4. 4 components are always
1536 * returned and DMASK works like a swizzle - it selects
1537 * the component to fetch. The only valid DMASK values are
1538 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
1539 * (red,red,red,red) etc.) The ISA document doesn't mention
1540 * this.
1541 */
1542
1543 /* Get the component index from src1.x for Gather4. */
1544 if (!tgsi_is_shadow_target(target)) {
1545 LLVMValueRef comp_imm;
1546 struct tgsi_src_register src1 = inst->Src[1].Register;
1547
1548 assert(src1.File == TGSI_FILE_IMMEDIATE);
1549
1550 comp_imm = ctx->imms[src1.Index * TGSI_NUM_CHANNELS + src1.SwizzleX];
1551 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
1552 gather_comp = CLAMP(gather_comp, 0, 3);
1553 }
1554
1555 args.dmask = 1 << gather_comp;
1556 } else {
1557 args.dmask = 0xf;
1558 }
1559
1560 args.dim = ac_texture_dim_from_tgsi_target(ctx->screen, target);
1561 args.unorm = target == TGSI_TEXTURE_RECT ||
1562 target == TGSI_TEXTURE_SHADOWRECT;
1563 args.opcode = ac_image_sample;
1564
1565 switch (opcode) {
1566 case TGSI_OPCODE_TXF:
1567 case TGSI_OPCODE_TXF_LZ:
1568 args.opcode = opcode == TGSI_OPCODE_TXF_LZ ||
1569 target == TGSI_TEXTURE_2D_MSAA ||
1570 target == TGSI_TEXTURE_2D_ARRAY_MSAA ?
1571 ac_image_load : ac_image_load_mip;
1572 break;
1573 case TGSI_OPCODE_LODQ:
1574 args.opcode = ac_image_get_lod;
1575 break;
1576 case TGSI_OPCODE_TEX:
1577 case TGSI_OPCODE_TEX2:
1578 case TGSI_OPCODE_TXP:
1579 if (ctx->type != PIPE_SHADER_FRAGMENT)
1580 args.level_zero = true;
1581 break;
1582 case TGSI_OPCODE_TEX_LZ:
1583 args.level_zero = true;
1584 break;
1585 case TGSI_OPCODE_TXB:
1586 case TGSI_OPCODE_TXB2:
1587 assert(ctx->type == PIPE_SHADER_FRAGMENT);
1588 break;
1589 case TGSI_OPCODE_TXL:
1590 case TGSI_OPCODE_TXL2:
1591 break;
1592 case TGSI_OPCODE_TXD:
1593 break;
1594 case TGSI_OPCODE_TG4:
1595 args.opcode = ac_image_gather4;
1596 args.level_zero = true;
1597 break;
1598 default:
1599 assert(0);
1600 return;
1601 }
1602
1603 /* The hardware needs special lowering for Gather4 with integer formats. */
1604 LLVMValueRef gather4_int_result_workaround = NULL;
1605
1606 if (ctx->screen->info.chip_class <= VI &&
1607 opcode == TGSI_OPCODE_TG4) {
1608 assert(inst->Texture.ReturnType != TGSI_RETURN_TYPE_UNKNOWN);
1609
1610 if (inst->Texture.ReturnType == TGSI_RETURN_TYPE_SINT ||
1611 inst->Texture.ReturnType == TGSI_RETURN_TYPE_UINT) {
1612 gather4_int_result_workaround =
1613 si_lower_gather4_integer(ctx, &args, target,
1614 inst->Texture.ReturnType);
1615 }
1616 }
1617
1618 args.attributes = AC_FUNC_ATTR_READNONE;
1619 LLVMValueRef result = ac_build_image_opcode(&ctx->ac, &args);
1620
1621 if (gather4_int_result_workaround) {
1622 result = si_fix_gather4_integer_result(ctx, result,
1623 inst->Texture.ReturnType,
1624 gather4_int_result_workaround);
1625 }
1626
1627 emit_data->output[emit_data->chan] = result;
1628 }
1629
1630 static void si_llvm_emit_txqs(
1631 const struct lp_build_tgsi_action *action,
1632 struct lp_build_tgsi_context *bld_base,
1633 struct lp_build_emit_data *emit_data)
1634 {
1635 struct si_shader_context *ctx = si_shader_context(bld_base);
1636 LLVMValueRef res, samples;
1637 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
1638
1639 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
1640
1641 /* Read the samples from the descriptor directly. */
1642 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->v8i32, "");
1643 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
1644 LLVMConstInt(ctx->i32, 3, 0), "");
1645 samples = LLVMBuildLShr(ctx->ac.builder, samples,
1646 LLVMConstInt(ctx->i32, 16, 0), "");
1647 samples = LLVMBuildAnd(ctx->ac.builder, samples,
1648 LLVMConstInt(ctx->i32, 0xf, 0), "");
1649 samples = LLVMBuildShl(ctx->ac.builder, ctx->i32_1,
1650 samples, "");
1651
1652 emit_data->output[emit_data->chan] = samples;
1653 }
1654
1655 static void si_llvm_emit_fbfetch(const struct lp_build_tgsi_action *action,
1656 struct lp_build_tgsi_context *bld_base,
1657 struct lp_build_emit_data *emit_data)
1658 {
1659 struct si_shader_context *ctx = si_shader_context(bld_base);
1660 struct ac_image_args args = {};
1661 LLVMValueRef ptr, image, fmask;
1662
1663 /* Ignore src0, because KHR_blend_func_extended disallows multiple render
1664 * targets.
1665 */
1666
1667 /* Load the image descriptor. */
1668 STATIC_ASSERT(SI_PS_IMAGE_COLORBUF0 % 2 == 0);
1669 ptr = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
1670 ptr = LLVMBuildPointerCast(ctx->ac.builder, ptr,
1671 ac_array_in_const32_addr_space(ctx->v8i32), "");
1672 image = ac_build_load_to_sgpr(&ctx->ac, ptr,
1673 LLVMConstInt(ctx->i32, SI_PS_IMAGE_COLORBUF0 / 2, 0));
1674
1675 unsigned chan = 0;
1676
1677 args.coords[chan++] = si_unpack_param(ctx, SI_PARAM_POS_FIXED_PT, 0, 16);
1678
1679 if (!ctx->shader->key.mono.u.ps.fbfetch_is_1D)
1680 args.coords[chan++] = si_unpack_param(ctx, SI_PARAM_POS_FIXED_PT, 16, 16);
1681
1682 /* Get the current render target layer index. */
1683 if (ctx->shader->key.mono.u.ps.fbfetch_layered)
1684 args.coords[chan++] = si_unpack_param(ctx, SI_PARAM_ANCILLARY, 16, 11);
1685
1686 if (ctx->shader->key.mono.u.ps.fbfetch_msaa)
1687 args.coords[chan++] = si_get_sample_id(ctx);
1688
1689 if (ctx->shader->key.mono.u.ps.fbfetch_msaa) {
1690 fmask = ac_build_load_to_sgpr(&ctx->ac, ptr,
1691 LLVMConstInt(ctx->i32, SI_PS_IMAGE_COLORBUF0_FMASK / 2, 0));
1692
1693 ac_apply_fmask_to_sample(&ctx->ac, fmask, args.coords,
1694 ctx->shader->key.mono.u.ps.fbfetch_layered);
1695 }
1696
1697 args.opcode = ac_image_load;
1698 args.resource = image;
1699 args.dmask = 0xf;
1700 if (ctx->shader->key.mono.u.ps.fbfetch_msaa)
1701 args.dim = ctx->shader->key.mono.u.ps.fbfetch_layered ?
1702 ac_image_2darraymsaa : ac_image_2dmsaa;
1703 else if (ctx->shader->key.mono.u.ps.fbfetch_is_1D)
1704 args.dim = ctx->shader->key.mono.u.ps.fbfetch_layered ?
1705 ac_image_1darray : ac_image_1d;
1706 else
1707 args.dim = ctx->shader->key.mono.u.ps.fbfetch_layered ?
1708 ac_image_2darray : ac_image_2d;
1709
1710 emit_data->output[emit_data->chan] =
1711 ac_build_image_opcode(&ctx->ac, &args);
1712 }
1713
1714 /**
1715 * Setup actions for TGSI memory opcode, including texture opcodes.
1716 */
1717 void si_shader_context_init_mem(struct si_shader_context *ctx)
1718 {
1719 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
1720
1721 bld_base->op_actions[TGSI_OPCODE_TEX].emit = build_tex_intrinsic;
1722 bld_base->op_actions[TGSI_OPCODE_TEX_LZ].emit = build_tex_intrinsic;
1723 bld_base->op_actions[TGSI_OPCODE_TEX2].emit = build_tex_intrinsic;
1724 bld_base->op_actions[TGSI_OPCODE_TXB].emit = build_tex_intrinsic;
1725 bld_base->op_actions[TGSI_OPCODE_TXB2].emit = build_tex_intrinsic;
1726 bld_base->op_actions[TGSI_OPCODE_TXD].emit = build_tex_intrinsic;
1727 bld_base->op_actions[TGSI_OPCODE_TXF].emit = build_tex_intrinsic;
1728 bld_base->op_actions[TGSI_OPCODE_TXF_LZ].emit = build_tex_intrinsic;
1729 bld_base->op_actions[TGSI_OPCODE_TXL].emit = build_tex_intrinsic;
1730 bld_base->op_actions[TGSI_OPCODE_TXL2].emit = build_tex_intrinsic;
1731 bld_base->op_actions[TGSI_OPCODE_TXP].emit = build_tex_intrinsic;
1732 bld_base->op_actions[TGSI_OPCODE_TXQ].emit = resq_emit;
1733 bld_base->op_actions[TGSI_OPCODE_TG4].emit = build_tex_intrinsic;
1734 bld_base->op_actions[TGSI_OPCODE_LODQ].emit = build_tex_intrinsic;
1735 bld_base->op_actions[TGSI_OPCODE_TXQS].emit = si_llvm_emit_txqs;
1736
1737 bld_base->op_actions[TGSI_OPCODE_FBFETCH].emit = si_llvm_emit_fbfetch;
1738
1739 bld_base->op_actions[TGSI_OPCODE_LOAD].emit = load_emit;
1740 bld_base->op_actions[TGSI_OPCODE_STORE].emit = store_emit;
1741 bld_base->op_actions[TGSI_OPCODE_RESQ].emit = resq_emit;
1742
1743 bld_base->op_actions[TGSI_OPCODE_ATOMUADD].emit = atomic_emit;
1744 bld_base->op_actions[TGSI_OPCODE_ATOMUADD].intr_name = "add";
1745 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG].emit = atomic_emit;
1746 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG].intr_name = "swap";
1747 bld_base->op_actions[TGSI_OPCODE_ATOMCAS].emit = atomic_emit;
1748 bld_base->op_actions[TGSI_OPCODE_ATOMCAS].intr_name = "cmpswap";
1749 bld_base->op_actions[TGSI_OPCODE_ATOMAND].emit = atomic_emit;
1750 bld_base->op_actions[TGSI_OPCODE_ATOMAND].intr_name = "and";
1751 bld_base->op_actions[TGSI_OPCODE_ATOMOR].emit = atomic_emit;
1752 bld_base->op_actions[TGSI_OPCODE_ATOMOR].intr_name = "or";
1753 bld_base->op_actions[TGSI_OPCODE_ATOMXOR].emit = atomic_emit;
1754 bld_base->op_actions[TGSI_OPCODE_ATOMXOR].intr_name = "xor";
1755 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN].emit = atomic_emit;
1756 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN].intr_name = "umin";
1757 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX].emit = atomic_emit;
1758 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX].intr_name = "umax";
1759 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN].emit = atomic_emit;
1760 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN].intr_name = "smin";
1761 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX].emit = atomic_emit;
1762 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX].intr_name = "smax";
1763 }