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radeonsi: use slot indexes for bindless handles
[mesa.git] / src / gallium / drivers / radeonsi / si_shader_tgsi_mem.c
1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "si_shader_internal.h"
25 #include "si_pipe.h"
26 #include "sid.h"
27 #include "gallivm/lp_bld_arit.h"
28 #include "gallivm/lp_bld_gather.h"
29 #include "gallivm/lp_bld_intr.h"
30 #include "tgsi/tgsi_build.h"
31 #include "tgsi/tgsi_parse.h"
32 #include "tgsi/tgsi_util.h"
33
34 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
35 struct lp_build_tgsi_context *bld_base,
36 struct lp_build_emit_data *emit_data);
37
38 static const struct lp_build_tgsi_action tex_action;
39
40 /**
41 * Given a v8i32 resource descriptor for a buffer, extract the size of the
42 * buffer in number of elements and return it as an i32.
43 */
44 static LLVMValueRef get_buffer_size(
45 struct lp_build_tgsi_context *bld_base,
46 LLVMValueRef descriptor)
47 {
48 struct si_shader_context *ctx = si_shader_context(bld_base);
49 struct gallivm_state *gallivm = &ctx->gallivm;
50 LLVMBuilderRef builder = gallivm->builder;
51 LLVMValueRef size =
52 LLVMBuildExtractElement(builder, descriptor,
53 LLVMConstInt(ctx->i32, 2, 0), "");
54
55 if (ctx->screen->b.chip_class == VI) {
56 /* On VI, the descriptor contains the size in bytes,
57 * but TXQ must return the size in elements.
58 * The stride is always non-zero for resources using TXQ.
59 */
60 LLVMValueRef stride =
61 LLVMBuildExtractElement(builder, descriptor,
62 ctx->i32_1, "");
63 stride = LLVMBuildLShr(builder, stride,
64 LLVMConstInt(ctx->i32, 16, 0), "");
65 stride = LLVMBuildAnd(builder, stride,
66 LLVMConstInt(ctx->i32, 0x3FFF, 0), "");
67
68 size = LLVMBuildUDiv(builder, size, stride, "");
69 }
70
71 return size;
72 }
73
74 static LLVMValueRef
75 shader_buffer_fetch_rsrc(struct si_shader_context *ctx,
76 const struct tgsi_full_src_register *reg)
77 {
78 LLVMValueRef index;
79
80 if (!reg->Register.Indirect) {
81 index = LLVMConstInt(ctx->i32, reg->Register.Index, false);
82 } else {
83 index = si_get_indirect_index(ctx, &reg->Indirect,
84 reg->Register.Index);
85 }
86
87 return ctx->abi.load_ssbo(&ctx->abi, index, false);
88 }
89
90 static bool tgsi_is_array_sampler(unsigned target)
91 {
92 return target == TGSI_TEXTURE_1D_ARRAY ||
93 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
94 target == TGSI_TEXTURE_2D_ARRAY ||
95 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
96 target == TGSI_TEXTURE_CUBE_ARRAY ||
97 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY ||
98 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
99 }
100
101 static bool tgsi_is_array_image(unsigned target)
102 {
103 return target == TGSI_TEXTURE_3D ||
104 target == TGSI_TEXTURE_CUBE ||
105 target == TGSI_TEXTURE_1D_ARRAY ||
106 target == TGSI_TEXTURE_2D_ARRAY ||
107 target == TGSI_TEXTURE_CUBE_ARRAY ||
108 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
109 }
110
111 /**
112 * Given a 256-bit resource descriptor, force the DCC enable bit to off.
113 *
114 * At least on Tonga, executing image stores on images with DCC enabled and
115 * non-trivial can eventually lead to lockups. This can occur when an
116 * application binds an image as read-only but then uses a shader that writes
117 * to it. The OpenGL spec allows almost arbitrarily bad behavior (including
118 * program termination) in this case, but it doesn't cost much to be a bit
119 * nicer: disabling DCC in the shader still leads to undefined results but
120 * avoids the lockup.
121 */
122 static LLVMValueRef force_dcc_off(struct si_shader_context *ctx,
123 LLVMValueRef rsrc)
124 {
125 if (ctx->screen->b.chip_class <= CIK) {
126 return rsrc;
127 } else {
128 LLVMBuilderRef builder = ctx->gallivm.builder;
129 LLVMValueRef i32_6 = LLVMConstInt(ctx->i32, 6, 0);
130 LLVMValueRef i32_C = LLVMConstInt(ctx->i32, C_008F28_COMPRESSION_EN, 0);
131 LLVMValueRef tmp;
132
133 tmp = LLVMBuildExtractElement(builder, rsrc, i32_6, "");
134 tmp = LLVMBuildAnd(builder, tmp, i32_C, "");
135 return LLVMBuildInsertElement(builder, rsrc, tmp, i32_6, "");
136 }
137 }
138
139 LLVMValueRef si_load_image_desc(struct si_shader_context *ctx,
140 LLVMValueRef list, LLVMValueRef index,
141 enum ac_descriptor_type desc_type, bool dcc_off)
142 {
143 LLVMBuilderRef builder = ctx->gallivm.builder;
144 LLVMValueRef rsrc;
145
146 if (desc_type == AC_DESC_BUFFER) {
147 index = LLVMBuildMul(builder, index,
148 LLVMConstInt(ctx->i32, 2, 0), "");
149 index = LLVMBuildAdd(builder, index,
150 ctx->i32_1, "");
151 list = LLVMBuildPointerCast(builder, list,
152 si_const_array(ctx->v4i32, 0), "");
153 } else {
154 assert(desc_type == AC_DESC_IMAGE);
155 }
156
157 rsrc = ac_build_indexed_load_const(&ctx->ac, list, index);
158 if (dcc_off)
159 rsrc = force_dcc_off(ctx, rsrc);
160 return rsrc;
161 }
162
163 /**
164 * Load the resource descriptor for \p image.
165 */
166 static void
167 image_fetch_rsrc(
168 struct lp_build_tgsi_context *bld_base,
169 const struct tgsi_full_src_register *image,
170 bool is_store, unsigned target,
171 LLVMValueRef *rsrc)
172 {
173 struct si_shader_context *ctx = si_shader_context(bld_base);
174 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
175 ctx->param_samplers_and_images);
176 LLVMValueRef index;
177 bool dcc_off = is_store;
178
179 if (!image->Register.Indirect) {
180 const struct tgsi_shader_info *info = bld_base->info;
181 unsigned images_writemask = info->images_store |
182 info->images_atomic;
183
184 index = LLVMConstInt(ctx->i32,
185 si_get_image_slot(image->Register.Index), 0);
186
187 if (images_writemask & (1 << image->Register.Index))
188 dcc_off = true;
189 } else {
190 /* From the GL_ARB_shader_image_load_store extension spec:
191 *
192 * If a shader performs an image load, store, or atomic
193 * operation using an image variable declared as an array,
194 * and if the index used to select an individual element is
195 * negative or greater than or equal to the size of the
196 * array, the results of the operation are undefined but may
197 * not lead to termination.
198 */
199 index = si_get_bounded_indirect_index(ctx, &image->Indirect,
200 image->Register.Index,
201 ctx->num_images);
202 index = LLVMBuildSub(ctx->gallivm.builder,
203 LLVMConstInt(ctx->i32, SI_NUM_IMAGES - 1, 0),
204 index, "");
205 }
206
207 if (image->Register.File != TGSI_FILE_IMAGE) {
208 /* Bindless descriptors are accessible from a different pair of
209 * user SGPR indices.
210 */
211 struct gallivm_state *gallivm = &ctx->gallivm;
212 LLVMBuilderRef builder = gallivm->builder;
213
214 rsrc_ptr = LLVMGetParam(ctx->main_fn,
215 ctx->param_bindless_samplers_and_images);
216 index = lp_build_emit_fetch_src(bld_base, image,
217 TGSI_TYPE_UNSIGNED, 0);
218
219 /* For simplicity, bindless image descriptors use fixed
220 * 16-dword slots for now.
221 */
222 index = LLVMBuildMul(builder, index,
223 LLVMConstInt(ctx->i32, 2, 0), "");
224 }
225
226 *rsrc = si_load_image_desc(ctx, rsrc_ptr, index,
227 target == TGSI_TEXTURE_BUFFER ? AC_DESC_BUFFER : AC_DESC_IMAGE,
228 dcc_off);
229 }
230
231 static LLVMValueRef image_fetch_coords(
232 struct lp_build_tgsi_context *bld_base,
233 const struct tgsi_full_instruction *inst,
234 unsigned src, LLVMValueRef desc)
235 {
236 struct si_shader_context *ctx = si_shader_context(bld_base);
237 struct gallivm_state *gallivm = &ctx->gallivm;
238 LLVMBuilderRef builder = gallivm->builder;
239 unsigned target = inst->Memory.Texture;
240 unsigned num_coords = tgsi_util_get_texture_coord_dim(target);
241 LLVMValueRef coords[4];
242 LLVMValueRef tmp;
243 int chan;
244
245 for (chan = 0; chan < num_coords; ++chan) {
246 tmp = lp_build_emit_fetch(bld_base, inst, src, chan);
247 tmp = LLVMBuildBitCast(builder, tmp, ctx->i32, "");
248 coords[chan] = tmp;
249 }
250
251 if (ctx->screen->b.chip_class >= GFX9) {
252 /* 1D textures are allocated and used as 2D on GFX9. */
253 if (target == TGSI_TEXTURE_1D) {
254 coords[1] = ctx->i32_0;
255 num_coords++;
256 } else if (target == TGSI_TEXTURE_1D_ARRAY) {
257 coords[2] = coords[1];
258 coords[1] = ctx->i32_0;
259 num_coords++;
260 } else if (target == TGSI_TEXTURE_2D) {
261 /* The hw can't bind a slice of a 3D image as a 2D
262 * image, because it ignores BASE_ARRAY if the target
263 * is 3D. The workaround is to read BASE_ARRAY and set
264 * it as the 3rd address operand for all 2D images.
265 */
266 LLVMValueRef first_layer, const5, mask;
267
268 const5 = LLVMConstInt(ctx->i32, 5, 0);
269 mask = LLVMConstInt(ctx->i32, S_008F24_BASE_ARRAY(~0), 0);
270 first_layer = LLVMBuildExtractElement(builder, desc, const5, "");
271 first_layer = LLVMBuildAnd(builder, first_layer, mask, "");
272
273 coords[2] = first_layer;
274 num_coords++;
275 }
276 }
277
278 if (num_coords == 1)
279 return coords[0];
280
281 if (num_coords == 3) {
282 /* LLVM has difficulties lowering 3-element vectors. */
283 coords[3] = bld_base->uint_bld.undef;
284 num_coords = 4;
285 }
286
287 return lp_build_gather_values(gallivm, coords, num_coords);
288 }
289
290 /**
291 * Append the extra mode bits that are used by image load and store.
292 */
293 static void image_append_args(
294 struct si_shader_context *ctx,
295 struct lp_build_emit_data * emit_data,
296 unsigned target,
297 bool atomic,
298 bool force_glc)
299 {
300 const struct tgsi_full_instruction *inst = emit_data->inst;
301 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
302 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
303 LLVMValueRef r128 = i1false;
304 LLVMValueRef da = tgsi_is_array_image(target) ? i1true : i1false;
305 LLVMValueRef glc =
306 force_glc ||
307 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE) ?
308 i1true : i1false;
309 LLVMValueRef slc = i1false;
310 LLVMValueRef lwe = i1false;
311
312 if (atomic || (HAVE_LLVM <= 0x0309)) {
313 emit_data->args[emit_data->arg_count++] = r128;
314 emit_data->args[emit_data->arg_count++] = da;
315 if (!atomic) {
316 emit_data->args[emit_data->arg_count++] = glc;
317 }
318 emit_data->args[emit_data->arg_count++] = slc;
319 return;
320 }
321
322 /* HAVE_LLVM >= 0x0400 */
323 emit_data->args[emit_data->arg_count++] = glc;
324 emit_data->args[emit_data->arg_count++] = slc;
325 emit_data->args[emit_data->arg_count++] = lwe;
326 emit_data->args[emit_data->arg_count++] = da;
327 }
328
329 /**
330 * Append the resource and indexing arguments for buffer intrinsics.
331 *
332 * \param rsrc the v4i32 buffer resource
333 * \param index index into the buffer (stride-based)
334 * \param offset byte offset into the buffer
335 */
336 static void buffer_append_args(
337 struct si_shader_context *ctx,
338 struct lp_build_emit_data *emit_data,
339 LLVMValueRef rsrc,
340 LLVMValueRef index,
341 LLVMValueRef offset,
342 bool atomic,
343 bool force_glc)
344 {
345 const struct tgsi_full_instruction *inst = emit_data->inst;
346 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
347 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
348
349 emit_data->args[emit_data->arg_count++] = rsrc;
350 emit_data->args[emit_data->arg_count++] = index; /* vindex */
351 emit_data->args[emit_data->arg_count++] = offset; /* voffset */
352 if (!atomic) {
353 emit_data->args[emit_data->arg_count++] =
354 force_glc ||
355 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE) ?
356 i1true : i1false; /* glc */
357 }
358 emit_data->args[emit_data->arg_count++] = i1false; /* slc */
359 }
360
361 static void load_fetch_args(
362 struct lp_build_tgsi_context * bld_base,
363 struct lp_build_emit_data * emit_data)
364 {
365 struct si_shader_context *ctx = si_shader_context(bld_base);
366 struct gallivm_state *gallivm = &ctx->gallivm;
367 const struct tgsi_full_instruction * inst = emit_data->inst;
368 unsigned target = inst->Memory.Texture;
369 LLVMValueRef rsrc;
370
371 emit_data->dst_type = ctx->v4f32;
372
373 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
374 LLVMBuilderRef builder = gallivm->builder;
375 LLVMValueRef offset;
376 LLVMValueRef tmp;
377
378 rsrc = shader_buffer_fetch_rsrc(ctx, &inst->Src[0]);
379
380 tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
381 offset = LLVMBuildBitCast(builder, tmp, ctx->i32, "");
382
383 buffer_append_args(ctx, emit_data, rsrc, ctx->i32_0,
384 offset, false, false);
385 } else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE ||
386 tgsi_is_bindless_image_file(inst->Src[0].Register.File)) {
387 LLVMValueRef coords;
388
389 image_fetch_rsrc(bld_base, &inst->Src[0], false, target, &rsrc);
390 coords = image_fetch_coords(bld_base, inst, 1, rsrc);
391
392 if (target == TGSI_TEXTURE_BUFFER) {
393 buffer_append_args(ctx, emit_data, rsrc, coords,
394 ctx->i32_0, false, false);
395 } else {
396 emit_data->args[0] = coords;
397 emit_data->args[1] = rsrc;
398 emit_data->args[2] = LLVMConstInt(ctx->i32, 15, 0); /* dmask */
399 emit_data->arg_count = 3;
400
401 image_append_args(ctx, emit_data, target, false, false);
402 }
403 }
404 }
405
406 static unsigned get_load_intr_attribs(bool can_speculate)
407 {
408 /* READNONE means writes can't affect it, while READONLY means that
409 * writes can affect it. */
410 return can_speculate && HAVE_LLVM >= 0x0400 ?
411 LP_FUNC_ATTR_READNONE :
412 LP_FUNC_ATTR_READONLY;
413 }
414
415 static unsigned get_store_intr_attribs(bool writeonly_memory)
416 {
417 return writeonly_memory && HAVE_LLVM >= 0x0400 ?
418 LP_FUNC_ATTR_INACCESSIBLE_MEM_ONLY :
419 LP_FUNC_ATTR_WRITEONLY;
420 }
421
422 static void load_emit_buffer(struct si_shader_context *ctx,
423 struct lp_build_emit_data *emit_data,
424 bool can_speculate)
425 {
426 const struct tgsi_full_instruction *inst = emit_data->inst;
427 uint writemask = inst->Dst[0].Register.WriteMask;
428 uint count = util_last_bit(writemask);
429 LLVMValueRef *args = emit_data->args;
430
431 /* Don't use SMEM for shader buffer loads, because LLVM doesn't
432 * select SMEM for SI.load.const with a non-constant offset, and
433 * constant offsets practically don't exist with shader buffers.
434 *
435 * Also, SI.load.const doesn't use inst_offset when it's lowered
436 * to VMEM, so we just end up with more VALU instructions in the end
437 * and no benefit.
438 *
439 * TODO: Remove this line once LLVM can select SMEM with a non-constant
440 * offset, and can derive inst_offset when VMEM is selected.
441 * After that, si_memory_barrier should invalidate sL1 for shader
442 * buffers.
443 */
444
445 assert(LLVMConstIntGetZExtValue(args[1]) == 0); /* vindex */
446 emit_data->output[emit_data->chan] =
447 ac_build_buffer_load(&ctx->ac, args[0], count, NULL,
448 args[2], NULL, 0,
449 LLVMConstIntGetZExtValue(args[3]),
450 LLVMConstIntGetZExtValue(args[4]),
451 can_speculate, false);
452 }
453
454 static LLVMValueRef get_memory_ptr(struct si_shader_context *ctx,
455 const struct tgsi_full_instruction *inst,
456 LLVMTypeRef type, int arg)
457 {
458 struct gallivm_state *gallivm = &ctx->gallivm;
459 LLVMBuilderRef builder = gallivm->builder;
460 LLVMValueRef offset, ptr;
461 int addr_space;
462
463 offset = lp_build_emit_fetch(&ctx->bld_base, inst, arg, 0);
464 offset = LLVMBuildBitCast(builder, offset, ctx->i32, "");
465
466 ptr = ctx->shared_memory;
467 ptr = LLVMBuildGEP(builder, ptr, &offset, 1, "");
468 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
469 ptr = LLVMBuildBitCast(builder, ptr, LLVMPointerType(type, addr_space), "");
470
471 return ptr;
472 }
473
474 static void load_emit_memory(
475 struct si_shader_context *ctx,
476 struct lp_build_emit_data *emit_data)
477 {
478 const struct tgsi_full_instruction *inst = emit_data->inst;
479 struct gallivm_state *gallivm = &ctx->gallivm;
480 LLVMBuilderRef builder = gallivm->builder;
481 unsigned writemask = inst->Dst[0].Register.WriteMask;
482 LLVMValueRef channels[4], ptr, derived_ptr, index;
483 int chan;
484
485 ptr = get_memory_ptr(ctx, inst, ctx->f32, 1);
486
487 for (chan = 0; chan < 4; ++chan) {
488 if (!(writemask & (1 << chan))) {
489 channels[chan] = LLVMGetUndef(ctx->f32);
490 continue;
491 }
492
493 index = LLVMConstInt(ctx->i32, chan, 0);
494 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
495 channels[chan] = LLVMBuildLoad(builder, derived_ptr, "");
496 }
497 emit_data->output[emit_data->chan] = lp_build_gather_values(gallivm, channels, 4);
498 }
499
500 /**
501 * Return true if the memory accessed by a LOAD or STORE instruction is
502 * read-only or write-only, respectively.
503 *
504 * \param shader_buffers_reverse_access_mask
505 * For LOAD, set this to (store | atomic) slot usage in the shader.
506 * For STORE, set this to (load | atomic) slot usage in the shader.
507 * \param images_reverse_access_mask Same as above, but for images.
508 */
509 static bool is_oneway_access_only(const struct tgsi_full_instruction *inst,
510 const struct tgsi_shader_info *info,
511 unsigned shader_buffers_reverse_access_mask,
512 unsigned images_reverse_access_mask)
513 {
514 /* RESTRICT means NOALIAS.
515 * If there are no writes, we can assume the accessed memory is read-only.
516 * If there are no reads, we can assume the accessed memory is write-only.
517 */
518 if (inst->Memory.Qualifier & TGSI_MEMORY_RESTRICT) {
519 unsigned reverse_access_mask;
520
521 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
522 reverse_access_mask = shader_buffers_reverse_access_mask;
523 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
524 reverse_access_mask = info->images_buffers &
525 images_reverse_access_mask;
526 } else {
527 reverse_access_mask = ~info->images_buffers &
528 images_reverse_access_mask;
529 }
530
531 if (inst->Src[0].Register.Indirect) {
532 if (!reverse_access_mask)
533 return true;
534 } else {
535 if (!(reverse_access_mask &
536 (1u << inst->Src[0].Register.Index)))
537 return true;
538 }
539 }
540
541 /* If there are no buffer writes (for both shader buffers & image
542 * buffers), it implies that buffer memory is read-only.
543 * If there are no buffer reads (for both shader buffers & image
544 * buffers), it implies that buffer memory is write-only.
545 *
546 * Same for the case when there are no writes/reads for non-buffer
547 * images.
548 */
549 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
550 (inst->Memory.Texture == TGSI_TEXTURE_BUFFER &&
551 (inst->Src[0].Register.File == TGSI_FILE_IMAGE ||
552 tgsi_is_bindless_image_file(inst->Src[0].Register.File)))) {
553 if (!shader_buffers_reverse_access_mask &&
554 !(info->images_buffers & images_reverse_access_mask))
555 return true;
556 } else {
557 if (!(~info->images_buffers & images_reverse_access_mask))
558 return true;
559 }
560 return false;
561 }
562
563 static void load_emit(
564 const struct lp_build_tgsi_action *action,
565 struct lp_build_tgsi_context *bld_base,
566 struct lp_build_emit_data *emit_data)
567 {
568 struct si_shader_context *ctx = si_shader_context(bld_base);
569 struct gallivm_state *gallivm = &ctx->gallivm;
570 LLVMBuilderRef builder = gallivm->builder;
571 const struct tgsi_full_instruction * inst = emit_data->inst;
572 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
573 char intrinsic_name[64];
574 bool can_speculate = false;
575
576 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
577 load_emit_memory(ctx, emit_data);
578 return;
579 }
580
581 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
582 si_emit_waitcnt(ctx, VM_CNT);
583
584 can_speculate = !(inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE) &&
585 is_oneway_access_only(inst, info,
586 info->shader_buffers_store |
587 info->shader_buffers_atomic,
588 info->images_store |
589 info->images_atomic);
590
591 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
592 load_emit_buffer(ctx, emit_data, can_speculate);
593 return;
594 }
595
596 if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
597 emit_data->output[emit_data->chan] =
598 lp_build_intrinsic(
599 builder, "llvm.amdgcn.buffer.load.format.v4f32", emit_data->dst_type,
600 emit_data->args, emit_data->arg_count,
601 get_load_intr_attribs(can_speculate));
602 } else {
603 ac_get_image_intr_name("llvm.amdgcn.image.load",
604 emit_data->dst_type, /* vdata */
605 LLVMTypeOf(emit_data->args[0]), /* coords */
606 LLVMTypeOf(emit_data->args[1]), /* rsrc */
607 intrinsic_name, sizeof(intrinsic_name));
608
609 emit_data->output[emit_data->chan] =
610 lp_build_intrinsic(
611 builder, intrinsic_name, emit_data->dst_type,
612 emit_data->args, emit_data->arg_count,
613 get_load_intr_attribs(can_speculate));
614 }
615 }
616
617 static void store_fetch_args(
618 struct lp_build_tgsi_context * bld_base,
619 struct lp_build_emit_data * emit_data)
620 {
621 struct si_shader_context *ctx = si_shader_context(bld_base);
622 struct gallivm_state *gallivm = &ctx->gallivm;
623 LLVMBuilderRef builder = gallivm->builder;
624 const struct tgsi_full_instruction * inst = emit_data->inst;
625 struct tgsi_full_src_register memory;
626 LLVMValueRef chans[4];
627 LLVMValueRef data;
628 LLVMValueRef rsrc;
629 unsigned chan;
630
631 emit_data->dst_type = LLVMVoidTypeInContext(gallivm->context);
632
633 for (chan = 0; chan < 4; ++chan) {
634 chans[chan] = lp_build_emit_fetch(bld_base, inst, 1, chan);
635 }
636 data = lp_build_gather_values(gallivm, chans, 4);
637
638 emit_data->args[emit_data->arg_count++] = data;
639
640 memory = tgsi_full_src_register_from_dst(&inst->Dst[0]);
641
642 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
643 LLVMValueRef offset;
644 LLVMValueRef tmp;
645
646 rsrc = shader_buffer_fetch_rsrc(ctx, &memory);
647
648 tmp = lp_build_emit_fetch(bld_base, inst, 0, 0);
649 offset = LLVMBuildBitCast(builder, tmp, ctx->i32, "");
650
651 buffer_append_args(ctx, emit_data, rsrc, ctx->i32_0,
652 offset, false, false);
653 } else if (inst->Dst[0].Register.File == TGSI_FILE_IMAGE ||
654 tgsi_is_bindless_image_file(inst->Dst[0].Register.File)) {
655 unsigned target = inst->Memory.Texture;
656 LLVMValueRef coords;
657
658 /* 8bit/16bit TC L1 write corruption bug on SI.
659 * All store opcodes not aligned to a dword are affected.
660 *
661 * The only way to get unaligned stores in radeonsi is through
662 * shader images.
663 */
664 bool force_glc = ctx->screen->b.chip_class == SI;
665
666 image_fetch_rsrc(bld_base, &memory, true, target, &rsrc);
667 coords = image_fetch_coords(bld_base, inst, 0, rsrc);
668
669 if (target == TGSI_TEXTURE_BUFFER) {
670 buffer_append_args(ctx, emit_data, rsrc, coords,
671 ctx->i32_0, false, force_glc);
672 } else {
673 emit_data->args[1] = coords;
674 emit_data->args[2] = rsrc;
675 emit_data->args[3] = LLVMConstInt(ctx->i32, 15, 0); /* dmask */
676 emit_data->arg_count = 4;
677
678 image_append_args(ctx, emit_data, target, false, force_glc);
679 }
680 }
681 }
682
683 static void store_emit_buffer(
684 struct si_shader_context *ctx,
685 struct lp_build_emit_data *emit_data,
686 bool writeonly_memory)
687 {
688 const struct tgsi_full_instruction *inst = emit_data->inst;
689 struct gallivm_state *gallivm = &ctx->gallivm;
690 LLVMBuilderRef builder = gallivm->builder;
691 LLVMValueRef base_data = emit_data->args[0];
692 LLVMValueRef base_offset = emit_data->args[3];
693 unsigned writemask = inst->Dst[0].Register.WriteMask;
694
695 while (writemask) {
696 int start, count;
697 const char *intrinsic_name;
698 LLVMValueRef data;
699 LLVMValueRef offset;
700 LLVMValueRef tmp;
701
702 u_bit_scan_consecutive_range(&writemask, &start, &count);
703
704 /* Due to an LLVM limitation, split 3-element writes
705 * into a 2-element and a 1-element write. */
706 if (count == 3) {
707 writemask |= 1 << (start + 2);
708 count = 2;
709 }
710
711 if (count == 4) {
712 data = base_data;
713 intrinsic_name = "llvm.amdgcn.buffer.store.v4f32";
714 } else if (count == 2) {
715 LLVMTypeRef v2f32 = LLVMVectorType(ctx->f32, 2);
716
717 tmp = LLVMBuildExtractElement(
718 builder, base_data,
719 LLVMConstInt(ctx->i32, start, 0), "");
720 data = LLVMBuildInsertElement(
721 builder, LLVMGetUndef(v2f32), tmp,
722 ctx->i32_0, "");
723
724 tmp = LLVMBuildExtractElement(
725 builder, base_data,
726 LLVMConstInt(ctx->i32, start + 1, 0), "");
727 data = LLVMBuildInsertElement(
728 builder, data, tmp, ctx->i32_1, "");
729
730 intrinsic_name = "llvm.amdgcn.buffer.store.v2f32";
731 } else {
732 assert(count == 1);
733 data = LLVMBuildExtractElement(
734 builder, base_data,
735 LLVMConstInt(ctx->i32, start, 0), "");
736 intrinsic_name = "llvm.amdgcn.buffer.store.f32";
737 }
738
739 offset = base_offset;
740 if (start != 0) {
741 offset = LLVMBuildAdd(
742 builder, offset,
743 LLVMConstInt(ctx->i32, start * 4, 0), "");
744 }
745
746 emit_data->args[0] = data;
747 emit_data->args[3] = offset;
748
749 lp_build_intrinsic(
750 builder, intrinsic_name, emit_data->dst_type,
751 emit_data->args, emit_data->arg_count,
752 get_store_intr_attribs(writeonly_memory));
753 }
754 }
755
756 static void store_emit_memory(
757 struct si_shader_context *ctx,
758 struct lp_build_emit_data *emit_data)
759 {
760 const struct tgsi_full_instruction *inst = emit_data->inst;
761 struct gallivm_state *gallivm = &ctx->gallivm;
762 LLVMBuilderRef builder = gallivm->builder;
763 unsigned writemask = inst->Dst[0].Register.WriteMask;
764 LLVMValueRef ptr, derived_ptr, data, index;
765 int chan;
766
767 ptr = get_memory_ptr(ctx, inst, ctx->f32, 0);
768
769 for (chan = 0; chan < 4; ++chan) {
770 if (!(writemask & (1 << chan))) {
771 continue;
772 }
773 data = lp_build_emit_fetch(&ctx->bld_base, inst, 1, chan);
774 index = LLVMConstInt(ctx->i32, chan, 0);
775 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
776 LLVMBuildStore(builder, data, derived_ptr);
777 }
778 }
779
780 static void store_emit(
781 const struct lp_build_tgsi_action *action,
782 struct lp_build_tgsi_context *bld_base,
783 struct lp_build_emit_data *emit_data)
784 {
785 struct si_shader_context *ctx = si_shader_context(bld_base);
786 struct gallivm_state *gallivm = &ctx->gallivm;
787 LLVMBuilderRef builder = gallivm->builder;
788 const struct tgsi_full_instruction * inst = emit_data->inst;
789 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
790 unsigned target = inst->Memory.Texture;
791 char intrinsic_name[64];
792 bool writeonly_memory = false;
793
794 if (inst->Dst[0].Register.File == TGSI_FILE_MEMORY) {
795 store_emit_memory(ctx, emit_data);
796 return;
797 }
798
799 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
800 si_emit_waitcnt(ctx, VM_CNT);
801
802 writeonly_memory = is_oneway_access_only(inst, info,
803 info->shader_buffers_load |
804 info->shader_buffers_atomic,
805 info->images_load |
806 info->images_atomic);
807
808 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
809 store_emit_buffer(ctx, emit_data, writeonly_memory);
810 return;
811 }
812
813 if (target == TGSI_TEXTURE_BUFFER) {
814 emit_data->output[emit_data->chan] = lp_build_intrinsic(
815 builder, "llvm.amdgcn.buffer.store.format.v4f32",
816 emit_data->dst_type, emit_data->args,
817 emit_data->arg_count,
818 get_store_intr_attribs(writeonly_memory));
819 } else {
820 ac_get_image_intr_name("llvm.amdgcn.image.store",
821 LLVMTypeOf(emit_data->args[0]), /* vdata */
822 LLVMTypeOf(emit_data->args[1]), /* coords */
823 LLVMTypeOf(emit_data->args[2]), /* rsrc */
824 intrinsic_name, sizeof(intrinsic_name));
825
826 emit_data->output[emit_data->chan] =
827 lp_build_intrinsic(
828 builder, intrinsic_name, emit_data->dst_type,
829 emit_data->args, emit_data->arg_count,
830 get_store_intr_attribs(writeonly_memory));
831 }
832 }
833
834 static void atomic_fetch_args(
835 struct lp_build_tgsi_context * bld_base,
836 struct lp_build_emit_data * emit_data)
837 {
838 struct si_shader_context *ctx = si_shader_context(bld_base);
839 struct gallivm_state *gallivm = &ctx->gallivm;
840 LLVMBuilderRef builder = gallivm->builder;
841 const struct tgsi_full_instruction * inst = emit_data->inst;
842 LLVMValueRef data1, data2;
843 LLVMValueRef rsrc;
844 LLVMValueRef tmp;
845
846 emit_data->dst_type = ctx->f32;
847
848 tmp = lp_build_emit_fetch(bld_base, inst, 2, 0);
849 data1 = LLVMBuildBitCast(builder, tmp, ctx->i32, "");
850
851 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
852 tmp = lp_build_emit_fetch(bld_base, inst, 3, 0);
853 data2 = LLVMBuildBitCast(builder, tmp, ctx->i32, "");
854 }
855
856 /* llvm.amdgcn.image/buffer.atomic.cmpswap reflect the hardware order
857 * of arguments, which is reversed relative to TGSI (and GLSL)
858 */
859 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
860 emit_data->args[emit_data->arg_count++] = data2;
861 emit_data->args[emit_data->arg_count++] = data1;
862
863 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
864 LLVMValueRef offset;
865
866 rsrc = shader_buffer_fetch_rsrc(ctx, &inst->Src[0]);
867
868 tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
869 offset = LLVMBuildBitCast(builder, tmp, ctx->i32, "");
870
871 buffer_append_args(ctx, emit_data, rsrc, ctx->i32_0,
872 offset, true, false);
873 } else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE ||
874 tgsi_is_bindless_image_file(inst->Src[0].Register.File)) {
875 unsigned target = inst->Memory.Texture;
876 LLVMValueRef coords;
877
878 image_fetch_rsrc(bld_base, &inst->Src[0], true, target, &rsrc);
879 coords = image_fetch_coords(bld_base, inst, 1, rsrc);
880
881 if (target == TGSI_TEXTURE_BUFFER) {
882 buffer_append_args(ctx, emit_data, rsrc, coords,
883 ctx->i32_0, true, false);
884 } else {
885 emit_data->args[emit_data->arg_count++] = coords;
886 emit_data->args[emit_data->arg_count++] = rsrc;
887
888 image_append_args(ctx, emit_data, target, true, false);
889 }
890 }
891 }
892
893 static void atomic_emit_memory(struct si_shader_context *ctx,
894 struct lp_build_emit_data *emit_data) {
895 struct gallivm_state *gallivm = &ctx->gallivm;
896 LLVMBuilderRef builder = gallivm->builder;
897 const struct tgsi_full_instruction * inst = emit_data->inst;
898 LLVMValueRef ptr, result, arg;
899
900 ptr = get_memory_ptr(ctx, inst, ctx->i32, 1);
901
902 arg = lp_build_emit_fetch(&ctx->bld_base, inst, 2, 0);
903 arg = LLVMBuildBitCast(builder, arg, ctx->i32, "");
904
905 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
906 LLVMValueRef new_data;
907 new_data = lp_build_emit_fetch(&ctx->bld_base,
908 inst, 3, 0);
909
910 new_data = LLVMBuildBitCast(builder, new_data, ctx->i32, "");
911
912 result = LLVMBuildAtomicCmpXchg(builder, ptr, arg, new_data,
913 LLVMAtomicOrderingSequentiallyConsistent,
914 LLVMAtomicOrderingSequentiallyConsistent,
915 false);
916
917 result = LLVMBuildExtractValue(builder, result, 0, "");
918 } else {
919 LLVMAtomicRMWBinOp op;
920
921 switch(inst->Instruction.Opcode) {
922 case TGSI_OPCODE_ATOMUADD:
923 op = LLVMAtomicRMWBinOpAdd;
924 break;
925 case TGSI_OPCODE_ATOMXCHG:
926 op = LLVMAtomicRMWBinOpXchg;
927 break;
928 case TGSI_OPCODE_ATOMAND:
929 op = LLVMAtomicRMWBinOpAnd;
930 break;
931 case TGSI_OPCODE_ATOMOR:
932 op = LLVMAtomicRMWBinOpOr;
933 break;
934 case TGSI_OPCODE_ATOMXOR:
935 op = LLVMAtomicRMWBinOpXor;
936 break;
937 case TGSI_OPCODE_ATOMUMIN:
938 op = LLVMAtomicRMWBinOpUMin;
939 break;
940 case TGSI_OPCODE_ATOMUMAX:
941 op = LLVMAtomicRMWBinOpUMax;
942 break;
943 case TGSI_OPCODE_ATOMIMIN:
944 op = LLVMAtomicRMWBinOpMin;
945 break;
946 case TGSI_OPCODE_ATOMIMAX:
947 op = LLVMAtomicRMWBinOpMax;
948 break;
949 default:
950 unreachable("unknown atomic opcode");
951 }
952
953 result = LLVMBuildAtomicRMW(builder, op, ptr, arg,
954 LLVMAtomicOrderingSequentiallyConsistent,
955 false);
956 }
957 emit_data->output[emit_data->chan] = LLVMBuildBitCast(builder, result, emit_data->dst_type, "");
958 }
959
960 static void atomic_emit(
961 const struct lp_build_tgsi_action *action,
962 struct lp_build_tgsi_context *bld_base,
963 struct lp_build_emit_data *emit_data)
964 {
965 struct si_shader_context *ctx = si_shader_context(bld_base);
966 struct gallivm_state *gallivm = &ctx->gallivm;
967 LLVMBuilderRef builder = gallivm->builder;
968 const struct tgsi_full_instruction * inst = emit_data->inst;
969 char intrinsic_name[40];
970 LLVMValueRef tmp;
971
972 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
973 atomic_emit_memory(ctx, emit_data);
974 return;
975 }
976
977 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
978 inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
979 snprintf(intrinsic_name, sizeof(intrinsic_name),
980 "llvm.amdgcn.buffer.atomic.%s", action->intr_name);
981 } else {
982 LLVMValueRef coords;
983 char coords_type[8];
984
985 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
986 coords = emit_data->args[2];
987 else
988 coords = emit_data->args[1];
989
990 ac_build_type_name_for_intr(LLVMTypeOf(coords), coords_type, sizeof(coords_type));
991 snprintf(intrinsic_name, sizeof(intrinsic_name),
992 "llvm.amdgcn.image.atomic.%s.%s",
993 action->intr_name, coords_type);
994 }
995
996 tmp = lp_build_intrinsic(
997 builder, intrinsic_name, ctx->i32,
998 emit_data->args, emit_data->arg_count, 0);
999 emit_data->output[emit_data->chan] =
1000 LLVMBuildBitCast(builder, tmp, ctx->f32, "");
1001 }
1002
1003 static void set_tex_fetch_args(struct si_shader_context *ctx,
1004 struct lp_build_emit_data *emit_data,
1005 unsigned target,
1006 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
1007 LLVMValueRef *param, unsigned count,
1008 unsigned dmask)
1009 {
1010 struct gallivm_state *gallivm = &ctx->gallivm;
1011 struct ac_image_args args = {};
1012
1013 /* Pad to power of two vector */
1014 while (count < util_next_power_of_two(count))
1015 param[count++] = LLVMGetUndef(ctx->i32);
1016
1017 if (count > 1)
1018 args.addr = lp_build_gather_values(gallivm, param, count);
1019 else
1020 args.addr = param[0];
1021
1022 args.resource = res_ptr;
1023 args.sampler = samp_ptr;
1024 args.dmask = dmask;
1025 args.unorm = target == TGSI_TEXTURE_RECT ||
1026 target == TGSI_TEXTURE_SHADOWRECT;
1027 args.da = tgsi_is_array_sampler(target);
1028
1029 /* Ugly, but we seem to have no other choice right now. */
1030 STATIC_ASSERT(sizeof(args) <= sizeof(emit_data->args));
1031 memcpy(emit_data->args, &args, sizeof(args));
1032 }
1033
1034 static LLVMValueRef fix_resinfo(struct si_shader_context *ctx,
1035 unsigned target, LLVMValueRef out)
1036 {
1037 LLVMBuilderRef builder = ctx->gallivm.builder;
1038
1039 /* 1D textures are allocated and used as 2D on GFX9. */
1040 if (ctx->screen->b.chip_class >= GFX9 &&
1041 (target == TGSI_TEXTURE_1D_ARRAY ||
1042 target == TGSI_TEXTURE_SHADOW1D_ARRAY)) {
1043 LLVMValueRef layers =
1044 LLVMBuildExtractElement(builder, out,
1045 LLVMConstInt(ctx->i32, 2, 0), "");
1046 out = LLVMBuildInsertElement(builder, out, layers,
1047 ctx->i32_1, "");
1048 }
1049
1050 /* Divide the number of layers by 6 to get the number of cubes. */
1051 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
1052 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
1053 LLVMValueRef imm2 = LLVMConstInt(ctx->i32, 2, 0);
1054
1055 LLVMValueRef z = LLVMBuildExtractElement(builder, out, imm2, "");
1056 z = LLVMBuildSDiv(builder, z, LLVMConstInt(ctx->i32, 6, 0), "");
1057
1058 out = LLVMBuildInsertElement(builder, out, z, imm2, "");
1059 }
1060 return out;
1061 }
1062
1063 static void resq_fetch_args(
1064 struct lp_build_tgsi_context * bld_base,
1065 struct lp_build_emit_data * emit_data)
1066 {
1067 struct si_shader_context *ctx = si_shader_context(bld_base);
1068 const struct tgsi_full_instruction *inst = emit_data->inst;
1069 const struct tgsi_full_src_register *reg = &inst->Src[0];
1070
1071 emit_data->dst_type = ctx->v4i32;
1072
1073 if (reg->Register.File == TGSI_FILE_BUFFER) {
1074 emit_data->args[0] = shader_buffer_fetch_rsrc(ctx, reg);
1075 emit_data->arg_count = 1;
1076 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
1077 image_fetch_rsrc(bld_base, reg, false, inst->Memory.Texture,
1078 &emit_data->args[0]);
1079 emit_data->arg_count = 1;
1080 } else {
1081 LLVMValueRef res_ptr;
1082 unsigned image_target;
1083
1084 if (inst->Memory.Texture == TGSI_TEXTURE_3D)
1085 image_target = TGSI_TEXTURE_2D_ARRAY;
1086 else
1087 image_target = inst->Memory.Texture;
1088
1089 image_fetch_rsrc(bld_base, reg, false, inst->Memory.Texture,
1090 &res_ptr);
1091 set_tex_fetch_args(ctx, emit_data, image_target,
1092 res_ptr, NULL, &ctx->i32_0, 1,
1093 0xf);
1094 }
1095 }
1096
1097 static void resq_emit(
1098 const struct lp_build_tgsi_action *action,
1099 struct lp_build_tgsi_context *bld_base,
1100 struct lp_build_emit_data *emit_data)
1101 {
1102 struct si_shader_context *ctx = si_shader_context(bld_base);
1103 struct gallivm_state *gallivm = &ctx->gallivm;
1104 LLVMBuilderRef builder = gallivm->builder;
1105 const struct tgsi_full_instruction *inst = emit_data->inst;
1106 LLVMValueRef out;
1107
1108 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
1109 out = LLVMBuildExtractElement(builder, emit_data->args[0],
1110 LLVMConstInt(ctx->i32, 2, 0), "");
1111 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
1112 out = get_buffer_size(bld_base, emit_data->args[0]);
1113 } else {
1114 struct ac_image_args args;
1115
1116 memcpy(&args, emit_data->args, sizeof(args)); /* ugly */
1117 args.opcode = ac_image_get_resinfo;
1118 out = ac_build_image_opcode(&ctx->ac, &args);
1119
1120 out = fix_resinfo(ctx, inst->Memory.Texture, out);
1121 }
1122
1123 emit_data->output[emit_data->chan] = out;
1124 }
1125
1126 /**
1127 * Load an image view, fmask view. or sampler state descriptor.
1128 */
1129 LLVMValueRef si_load_sampler_desc(struct si_shader_context *ctx,
1130 LLVMValueRef list, LLVMValueRef index,
1131 enum ac_descriptor_type type)
1132 {
1133 struct gallivm_state *gallivm = &ctx->gallivm;
1134 LLVMBuilderRef builder = gallivm->builder;
1135
1136 switch (type) {
1137 case AC_DESC_IMAGE:
1138 /* The image is at [0:7]. */
1139 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
1140 break;
1141 case AC_DESC_BUFFER:
1142 /* The buffer is in [4:7]. */
1143 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 4, 0), "");
1144 index = LLVMBuildAdd(builder, index, ctx->i32_1, "");
1145 list = LLVMBuildPointerCast(builder, list,
1146 si_const_array(ctx->v4i32, 0), "");
1147 break;
1148 case AC_DESC_FMASK:
1149 /* The FMASK is at [8:15]. */
1150 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
1151 index = LLVMBuildAdd(builder, index, ctx->i32_1, "");
1152 break;
1153 case AC_DESC_SAMPLER:
1154 /* The sampler state is at [12:15]. */
1155 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 4, 0), "");
1156 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 3, 0), "");
1157 list = LLVMBuildPointerCast(builder, list,
1158 si_const_array(ctx->v4i32, 0), "");
1159 break;
1160 }
1161
1162 return ac_build_indexed_load_const(&ctx->ac, list, index);
1163 }
1164
1165 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
1166 *
1167 * SI-CI:
1168 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
1169 * filtering manually. The driver sets img7 to a mask clearing
1170 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
1171 * s_and_b32 samp0, samp0, img7
1172 *
1173 * VI:
1174 * The ANISO_OVERRIDE sampler field enables this fix in TA.
1175 */
1176 static LLVMValueRef sici_fix_sampler_aniso(struct si_shader_context *ctx,
1177 LLVMValueRef res, LLVMValueRef samp)
1178 {
1179 LLVMBuilderRef builder = ctx->gallivm.builder;
1180 LLVMValueRef img7, samp0;
1181
1182 if (ctx->screen->b.chip_class >= VI)
1183 return samp;
1184
1185 img7 = LLVMBuildExtractElement(builder, res,
1186 LLVMConstInt(ctx->i32, 7, 0), "");
1187 samp0 = LLVMBuildExtractElement(builder, samp,
1188 ctx->i32_0, "");
1189 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
1190 return LLVMBuildInsertElement(builder, samp, samp0,
1191 ctx->i32_0, "");
1192 }
1193
1194 static void tex_fetch_ptrs(
1195 struct lp_build_tgsi_context *bld_base,
1196 struct lp_build_emit_data *emit_data,
1197 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr, LLVMValueRef *fmask_ptr)
1198 {
1199 struct si_shader_context *ctx = si_shader_context(bld_base);
1200 LLVMValueRef list = LLVMGetParam(ctx->main_fn, ctx->param_samplers_and_images);
1201 const struct tgsi_full_instruction *inst = emit_data->inst;
1202 const struct tgsi_full_src_register *reg;
1203 unsigned target = inst->Texture.Texture;
1204 unsigned sampler_src;
1205 LLVMValueRef index;
1206
1207 sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
1208 reg = &emit_data->inst->Src[sampler_src];
1209
1210 if (reg->Register.Indirect) {
1211 index = si_get_bounded_indirect_index(ctx,
1212 &reg->Indirect,
1213 reg->Register.Index,
1214 ctx->num_samplers);
1215 index = LLVMBuildAdd(ctx->gallivm.builder, index,
1216 LLVMConstInt(ctx->i32, SI_NUM_IMAGES / 2, 0), "");
1217 } else {
1218 index = LLVMConstInt(ctx->i32,
1219 si_get_sampler_slot(reg->Register.Index), 0);
1220 }
1221
1222 if (reg->Register.File != TGSI_FILE_SAMPLER) {
1223 /* Bindless descriptors are accessible from a different pair of
1224 * user SGPR indices.
1225 */
1226 list = LLVMGetParam(ctx->main_fn,
1227 ctx->param_bindless_samplers_and_images);
1228 index = lp_build_emit_fetch_src(bld_base, reg,
1229 TGSI_TYPE_UNSIGNED, 0);
1230 }
1231
1232 if (target == TGSI_TEXTURE_BUFFER)
1233 *res_ptr = si_load_sampler_desc(ctx, list, index, AC_DESC_BUFFER);
1234 else
1235 *res_ptr = si_load_sampler_desc(ctx, list, index, AC_DESC_IMAGE);
1236
1237 if (samp_ptr)
1238 *samp_ptr = NULL;
1239 if (fmask_ptr)
1240 *fmask_ptr = NULL;
1241
1242 if (target == TGSI_TEXTURE_2D_MSAA ||
1243 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
1244 if (fmask_ptr)
1245 *fmask_ptr = si_load_sampler_desc(ctx, list, index,
1246 AC_DESC_FMASK);
1247 } else if (target != TGSI_TEXTURE_BUFFER) {
1248 if (samp_ptr) {
1249 *samp_ptr = si_load_sampler_desc(ctx, list, index,
1250 AC_DESC_SAMPLER);
1251 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
1252 }
1253 }
1254 }
1255
1256 static void txq_fetch_args(
1257 struct lp_build_tgsi_context *bld_base,
1258 struct lp_build_emit_data *emit_data)
1259 {
1260 struct si_shader_context *ctx = si_shader_context(bld_base);
1261 const struct tgsi_full_instruction *inst = emit_data->inst;
1262 unsigned target = inst->Texture.Texture;
1263 LLVMValueRef res_ptr;
1264 LLVMValueRef address;
1265
1266 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, NULL, NULL);
1267
1268 if (target == TGSI_TEXTURE_BUFFER) {
1269 /* Read the size from the buffer descriptor directly. */
1270 emit_data->args[0] = get_buffer_size(bld_base, res_ptr);
1271 return;
1272 }
1273
1274 /* Textures - set the mip level. */
1275 address = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
1276
1277 set_tex_fetch_args(ctx, emit_data, target, res_ptr,
1278 NULL, &address, 1, 0xf);
1279 }
1280
1281 static void txq_emit(const struct lp_build_tgsi_action *action,
1282 struct lp_build_tgsi_context *bld_base,
1283 struct lp_build_emit_data *emit_data)
1284 {
1285 struct si_shader_context *ctx = si_shader_context(bld_base);
1286 struct ac_image_args args;
1287 unsigned target = emit_data->inst->Texture.Texture;
1288
1289 if (target == TGSI_TEXTURE_BUFFER) {
1290 /* Just return the buffer size. */
1291 emit_data->output[emit_data->chan] = emit_data->args[0];
1292 return;
1293 }
1294
1295 memcpy(&args, emit_data->args, sizeof(args)); /* ugly */
1296
1297 args.opcode = ac_image_get_resinfo;
1298 LLVMValueRef result = ac_build_image_opcode(&ctx->ac, &args);
1299
1300 emit_data->output[emit_data->chan] = fix_resinfo(ctx, target, result);
1301 }
1302
1303 static void tex_fetch_args(
1304 struct lp_build_tgsi_context *bld_base,
1305 struct lp_build_emit_data *emit_data)
1306 {
1307 struct si_shader_context *ctx = si_shader_context(bld_base);
1308 struct gallivm_state *gallivm = &ctx->gallivm;
1309 const struct tgsi_full_instruction *inst = emit_data->inst;
1310 unsigned opcode = inst->Instruction.Opcode;
1311 unsigned target = inst->Texture.Texture;
1312 LLVMValueRef coords[5], derivs[6];
1313 LLVMValueRef address[16];
1314 unsigned num_coords = tgsi_util_get_texture_coord_dim(target);
1315 int ref_pos = tgsi_util_get_shadow_ref_src_index(target);
1316 unsigned count = 0;
1317 unsigned chan;
1318 unsigned num_deriv_channels = 0;
1319 bool has_offset = inst->Texture.NumOffsets > 0;
1320 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
1321 unsigned dmask = 0xf;
1322
1323 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
1324
1325 if (target == TGSI_TEXTURE_BUFFER) {
1326 emit_data->dst_type = ctx->v4f32;
1327 emit_data->args[0] = res_ptr;
1328 emit_data->args[1] = ctx->i32_0;
1329 emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
1330 emit_data->arg_count = 3;
1331 return;
1332 }
1333
1334 /* Fetch and project texture coordinates */
1335 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
1336 for (chan = 0; chan < 3; chan++ ) {
1337 coords[chan] = lp_build_emit_fetch(bld_base,
1338 emit_data->inst, 0,
1339 chan);
1340 if (opcode == TGSI_OPCODE_TXP)
1341 coords[chan] = lp_build_emit_llvm_binary(bld_base,
1342 TGSI_OPCODE_DIV,
1343 coords[chan],
1344 coords[3]);
1345 }
1346
1347 if (opcode == TGSI_OPCODE_TXP)
1348 coords[3] = bld_base->base.one;
1349
1350 /* Pack offsets. */
1351 if (has_offset &&
1352 opcode != TGSI_OPCODE_TXF &&
1353 opcode != TGSI_OPCODE_TXF_LZ) {
1354 /* The offsets are six-bit signed integers packed like this:
1355 * X=[5:0], Y=[13:8], and Z=[21:16].
1356 */
1357 LLVMValueRef offset[3], pack;
1358
1359 assert(inst->Texture.NumOffsets == 1);
1360
1361 for (chan = 0; chan < 3; chan++) {
1362 offset[chan] = lp_build_emit_fetch_texoffset(bld_base,
1363 emit_data->inst, 0, chan);
1364 offset[chan] = LLVMBuildAnd(gallivm->builder, offset[chan],
1365 LLVMConstInt(ctx->i32, 0x3f, 0), "");
1366 if (chan)
1367 offset[chan] = LLVMBuildShl(gallivm->builder, offset[chan],
1368 LLVMConstInt(ctx->i32, chan*8, 0), "");
1369 }
1370
1371 pack = LLVMBuildOr(gallivm->builder, offset[0], offset[1], "");
1372 pack = LLVMBuildOr(gallivm->builder, pack, offset[2], "");
1373 address[count++] = pack;
1374 }
1375
1376 /* Pack LOD bias value */
1377 if (opcode == TGSI_OPCODE_TXB)
1378 address[count++] = coords[3];
1379 if (opcode == TGSI_OPCODE_TXB2)
1380 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
1381
1382 /* Pack depth comparison value */
1383 if (tgsi_is_shadow_target(target) && opcode != TGSI_OPCODE_LODQ) {
1384 LLVMValueRef z;
1385
1386 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
1387 z = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
1388 } else {
1389 assert(ref_pos >= 0);
1390 z = coords[ref_pos];
1391 }
1392
1393 /* TC-compatible HTILE promotes Z16 and Z24 to Z32_FLOAT,
1394 * so the depth comparison value isn't clamped for Z16 and
1395 * Z24 anymore. Do it manually here.
1396 *
1397 * It's unnecessary if the original texture format was
1398 * Z32_FLOAT, but we don't know that here.
1399 */
1400 if (ctx->screen->b.chip_class >= VI)
1401 z = ac_build_clamp(&ctx->ac, z);
1402
1403 address[count++] = z;
1404 }
1405
1406 /* Pack user derivatives */
1407 if (opcode == TGSI_OPCODE_TXD) {
1408 int param, num_src_deriv_channels, num_dst_deriv_channels;
1409
1410 switch (target) {
1411 case TGSI_TEXTURE_3D:
1412 num_src_deriv_channels = 3;
1413 num_dst_deriv_channels = 3;
1414 num_deriv_channels = 3;
1415 break;
1416 case TGSI_TEXTURE_2D:
1417 case TGSI_TEXTURE_SHADOW2D:
1418 case TGSI_TEXTURE_RECT:
1419 case TGSI_TEXTURE_SHADOWRECT:
1420 case TGSI_TEXTURE_2D_ARRAY:
1421 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1422 num_src_deriv_channels = 2;
1423 num_dst_deriv_channels = 2;
1424 num_deriv_channels = 2;
1425 break;
1426 case TGSI_TEXTURE_CUBE:
1427 case TGSI_TEXTURE_SHADOWCUBE:
1428 case TGSI_TEXTURE_CUBE_ARRAY:
1429 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
1430 /* Cube derivatives will be converted to 2D. */
1431 num_src_deriv_channels = 3;
1432 num_dst_deriv_channels = 3;
1433 num_deriv_channels = 2;
1434 break;
1435 case TGSI_TEXTURE_1D:
1436 case TGSI_TEXTURE_SHADOW1D:
1437 case TGSI_TEXTURE_1D_ARRAY:
1438 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1439 num_src_deriv_channels = 1;
1440
1441 /* 1D textures are allocated and used as 2D on GFX9. */
1442 if (ctx->screen->b.chip_class >= GFX9) {
1443 num_dst_deriv_channels = 2;
1444 num_deriv_channels = 2;
1445 } else {
1446 num_dst_deriv_channels = 1;
1447 num_deriv_channels = 1;
1448 }
1449 break;
1450 default:
1451 unreachable("invalid target");
1452 }
1453
1454 for (param = 0; param < 2; param++) {
1455 for (chan = 0; chan < num_src_deriv_channels; chan++)
1456 derivs[param * num_dst_deriv_channels + chan] =
1457 lp_build_emit_fetch(bld_base, inst, param+1, chan);
1458
1459 /* Fill in the rest with zeros. */
1460 for (chan = num_src_deriv_channels;
1461 chan < num_dst_deriv_channels; chan++)
1462 derivs[param * num_dst_deriv_channels + chan] =
1463 bld_base->base.zero;
1464 }
1465 }
1466
1467 if (target == TGSI_TEXTURE_CUBE ||
1468 target == TGSI_TEXTURE_CUBE_ARRAY ||
1469 target == TGSI_TEXTURE_SHADOWCUBE ||
1470 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
1471 ac_prepare_cube_coords(&ctx->ac,
1472 opcode == TGSI_OPCODE_TXD,
1473 target == TGSI_TEXTURE_CUBE_ARRAY ||
1474 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY,
1475 coords, derivs);
1476
1477 if (opcode == TGSI_OPCODE_TXD)
1478 for (int i = 0; i < num_deriv_channels * 2; i++)
1479 address[count++] = derivs[i];
1480
1481 /* Pack texture coordinates */
1482 address[count++] = coords[0];
1483 if (num_coords > 1)
1484 address[count++] = coords[1];
1485 if (num_coords > 2)
1486 address[count++] = coords[2];
1487
1488 /* 1D textures are allocated and used as 2D on GFX9. */
1489 if (ctx->screen->b.chip_class >= GFX9) {
1490 LLVMValueRef filler;
1491
1492 /* Use 0.5, so that we don't sample the border color. */
1493 if (opcode == TGSI_OPCODE_TXF ||
1494 opcode == TGSI_OPCODE_TXF_LZ)
1495 filler = ctx->i32_0;
1496 else
1497 filler = LLVMConstReal(ctx->f32, 0.5);
1498
1499 if (target == TGSI_TEXTURE_1D ||
1500 target == TGSI_TEXTURE_SHADOW1D) {
1501 address[count++] = filler;
1502 } else if (target == TGSI_TEXTURE_1D_ARRAY ||
1503 target == TGSI_TEXTURE_SHADOW1D_ARRAY) {
1504 address[count] = address[count - 1];
1505 address[count - 1] = filler;
1506 count++;
1507 }
1508 }
1509
1510 /* Pack LOD or sample index */
1511 if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
1512 address[count++] = coords[3];
1513 else if (opcode == TGSI_OPCODE_TXL2)
1514 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
1515
1516 if (count > 16) {
1517 assert(!"Cannot handle more than 16 texture address parameters");
1518 count = 16;
1519 }
1520
1521 for (chan = 0; chan < count; chan++ ) {
1522 address[chan] = LLVMBuildBitCast(gallivm->builder,
1523 address[chan], ctx->i32, "");
1524 }
1525
1526 /* Adjust the sample index according to FMASK.
1527 *
1528 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
1529 * which is the identity mapping. Each nibble says which physical sample
1530 * should be fetched to get that sample.
1531 *
1532 * For example, 0x11111100 means there are only 2 samples stored and
1533 * the second sample covers 3/4 of the pixel. When reading samples 0
1534 * and 1, return physical sample 0 (determined by the first two 0s
1535 * in FMASK), otherwise return physical sample 1.
1536 *
1537 * The sample index should be adjusted as follows:
1538 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
1539 */
1540 if (target == TGSI_TEXTURE_2D_MSAA ||
1541 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
1542 struct lp_build_emit_data txf_emit_data = *emit_data;
1543 LLVMValueRef txf_address[4];
1544 /* We only need .xy for non-arrays, and .xyz for arrays. */
1545 unsigned txf_count = target == TGSI_TEXTURE_2D_MSAA ? 2 : 3;
1546 struct tgsi_full_instruction inst = {};
1547
1548 memcpy(txf_address, address, sizeof(txf_address));
1549
1550 /* Read FMASK using TXF_LZ. */
1551 inst.Instruction.Opcode = TGSI_OPCODE_TXF_LZ;
1552 inst.Texture.Texture = target;
1553 txf_emit_data.inst = &inst;
1554 txf_emit_data.chan = 0;
1555 set_tex_fetch_args(ctx, &txf_emit_data,
1556 target, fmask_ptr, NULL,
1557 txf_address, txf_count, 0xf);
1558 build_tex_intrinsic(&tex_action, bld_base, &txf_emit_data);
1559
1560 /* Initialize some constants. */
1561 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, 0);
1562 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xF, 0);
1563
1564 /* Apply the formula. */
1565 LLVMValueRef fmask =
1566 LLVMBuildExtractElement(gallivm->builder,
1567 txf_emit_data.output[0],
1568 ctx->i32_0, "");
1569
1570 unsigned sample_chan = txf_count; /* the sample index is last */
1571
1572 LLVMValueRef sample_index4 =
1573 LLVMBuildMul(gallivm->builder, address[sample_chan], four, "");
1574
1575 LLVMValueRef shifted_fmask =
1576 LLVMBuildLShr(gallivm->builder, fmask, sample_index4, "");
1577
1578 LLVMValueRef final_sample =
1579 LLVMBuildAnd(gallivm->builder, shifted_fmask, F, "");
1580
1581 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
1582 * resource descriptor is 0 (invalid),
1583 */
1584 LLVMValueRef fmask_desc =
1585 LLVMBuildBitCast(gallivm->builder, fmask_ptr,
1586 ctx->v8i32, "");
1587
1588 LLVMValueRef fmask_word1 =
1589 LLVMBuildExtractElement(gallivm->builder, fmask_desc,
1590 ctx->i32_1, "");
1591
1592 LLVMValueRef word1_is_nonzero =
1593 LLVMBuildICmp(gallivm->builder, LLVMIntNE,
1594 fmask_word1, ctx->i32_0, "");
1595
1596 /* Replace the MSAA sample index. */
1597 address[sample_chan] =
1598 LLVMBuildSelect(gallivm->builder, word1_is_nonzero,
1599 final_sample, address[sample_chan], "");
1600 }
1601
1602 if (opcode == TGSI_OPCODE_TXF ||
1603 opcode == TGSI_OPCODE_TXF_LZ) {
1604 /* add tex offsets */
1605 if (inst->Texture.NumOffsets) {
1606 struct lp_build_context *uint_bld = &bld_base->uint_bld;
1607 const struct tgsi_texture_offset *off = inst->TexOffsets;
1608
1609 assert(inst->Texture.NumOffsets == 1);
1610
1611 switch (target) {
1612 case TGSI_TEXTURE_3D:
1613 address[2] = lp_build_add(uint_bld, address[2],
1614 ctx->imms[off->Index * TGSI_NUM_CHANNELS + off->SwizzleZ]);
1615 /* fall through */
1616 case TGSI_TEXTURE_2D:
1617 case TGSI_TEXTURE_SHADOW2D:
1618 case TGSI_TEXTURE_RECT:
1619 case TGSI_TEXTURE_SHADOWRECT:
1620 case TGSI_TEXTURE_2D_ARRAY:
1621 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1622 address[1] =
1623 lp_build_add(uint_bld, address[1],
1624 ctx->imms[off->Index * TGSI_NUM_CHANNELS + off->SwizzleY]);
1625 /* fall through */
1626 case TGSI_TEXTURE_1D:
1627 case TGSI_TEXTURE_SHADOW1D:
1628 case TGSI_TEXTURE_1D_ARRAY:
1629 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1630 address[0] =
1631 lp_build_add(uint_bld, address[0],
1632 ctx->imms[off->Index * TGSI_NUM_CHANNELS + off->SwizzleX]);
1633 break;
1634 /* texture offsets do not apply to other texture targets */
1635 }
1636 }
1637 }
1638
1639 if (opcode == TGSI_OPCODE_TG4) {
1640 unsigned gather_comp = 0;
1641
1642 /* DMASK was repurposed for GATHER4. 4 components are always
1643 * returned and DMASK works like a swizzle - it selects
1644 * the component to fetch. The only valid DMASK values are
1645 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
1646 * (red,red,red,red) etc.) The ISA document doesn't mention
1647 * this.
1648 */
1649
1650 /* Get the component index from src1.x for Gather4. */
1651 if (!tgsi_is_shadow_target(target)) {
1652 LLVMValueRef comp_imm;
1653 struct tgsi_src_register src1 = inst->Src[1].Register;
1654
1655 assert(src1.File == TGSI_FILE_IMMEDIATE);
1656
1657 comp_imm = ctx->imms[src1.Index * TGSI_NUM_CHANNELS + src1.SwizzleX];
1658 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
1659 gather_comp = CLAMP(gather_comp, 0, 3);
1660 }
1661
1662 dmask = 1 << gather_comp;
1663 }
1664
1665 set_tex_fetch_args(ctx, emit_data, target, res_ptr,
1666 samp_ptr, address, count, dmask);
1667 }
1668
1669 /* Gather4 should follow the same rules as bilinear filtering, but the hardware
1670 * incorrectly forces nearest filtering if the texture format is integer.
1671 * The only effect it has on Gather4, which always returns 4 texels for
1672 * bilinear filtering, is that the final coordinates are off by 0.5 of
1673 * the texel size.
1674 *
1675 * The workaround is to subtract 0.5 from the unnormalized coordinates,
1676 * or (0.5 / size) from the normalized coordinates.
1677 */
1678 static void si_lower_gather4_integer(struct si_shader_context *ctx,
1679 struct ac_image_args *args,
1680 unsigned target)
1681 {
1682 LLVMBuilderRef builder = ctx->gallivm.builder;
1683 LLVMValueRef coord = args->addr;
1684 LLVMValueRef half_texel[2];
1685 /* Texture coordinates start after:
1686 * {offset, bias, z-compare, derivatives}
1687 * Only the offset and z-compare can occur here.
1688 */
1689 unsigned coord_vgpr_index = (int)args->offset + (int)args->compare;
1690 int c;
1691
1692 if (target == TGSI_TEXTURE_RECT ||
1693 target == TGSI_TEXTURE_SHADOWRECT) {
1694 half_texel[0] = half_texel[1] = LLVMConstReal(ctx->f32, -0.5);
1695 } else {
1696 struct tgsi_full_instruction txq_inst = {};
1697 struct lp_build_emit_data txq_emit_data = {};
1698
1699 /* Query the texture size. */
1700 txq_inst.Texture.Texture = target;
1701 txq_emit_data.inst = &txq_inst;
1702 txq_emit_data.dst_type = ctx->v4i32;
1703 set_tex_fetch_args(ctx, &txq_emit_data, target,
1704 args->resource, NULL, &ctx->i32_0,
1705 1, 0xf);
1706 txq_emit(NULL, &ctx->bld_base, &txq_emit_data);
1707
1708 /* Compute -0.5 / size. */
1709 for (c = 0; c < 2; c++) {
1710 half_texel[c] =
1711 LLVMBuildExtractElement(builder, txq_emit_data.output[0],
1712 LLVMConstInt(ctx->i32, c, 0), "");
1713 half_texel[c] = LLVMBuildUIToFP(builder, half_texel[c], ctx->f32, "");
1714 half_texel[c] =
1715 lp_build_emit_llvm_unary(&ctx->bld_base,
1716 TGSI_OPCODE_RCP, half_texel[c]);
1717 half_texel[c] = LLVMBuildFMul(builder, half_texel[c],
1718 LLVMConstReal(ctx->f32, -0.5), "");
1719 }
1720 }
1721
1722 for (c = 0; c < 2; c++) {
1723 LLVMValueRef tmp;
1724 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
1725
1726 tmp = LLVMBuildExtractElement(builder, coord, index, "");
1727 tmp = LLVMBuildBitCast(builder, tmp, ctx->f32, "");
1728 tmp = LLVMBuildFAdd(builder, tmp, half_texel[c], "");
1729 tmp = LLVMBuildBitCast(builder, tmp, ctx->i32, "");
1730 coord = LLVMBuildInsertElement(builder, coord, tmp, index, "");
1731 }
1732
1733 args->addr = coord;
1734 }
1735
1736 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
1737 struct lp_build_tgsi_context *bld_base,
1738 struct lp_build_emit_data *emit_data)
1739 {
1740 struct si_shader_context *ctx = si_shader_context(bld_base);
1741 const struct tgsi_full_instruction *inst = emit_data->inst;
1742 struct ac_image_args args;
1743 unsigned opcode = inst->Instruction.Opcode;
1744 unsigned target = inst->Texture.Texture;
1745
1746 if (target == TGSI_TEXTURE_BUFFER) {
1747 emit_data->output[emit_data->chan] =
1748 ac_build_buffer_load_format(&ctx->ac,
1749 emit_data->args[0],
1750 emit_data->args[2],
1751 emit_data->args[1],
1752 true);
1753 return;
1754 }
1755
1756 memcpy(&args, emit_data->args, sizeof(args)); /* ugly */
1757
1758 args.opcode = ac_image_sample;
1759 args.compare = tgsi_is_shadow_target(target);
1760 args.offset = inst->Texture.NumOffsets > 0;
1761
1762 switch (opcode) {
1763 case TGSI_OPCODE_TXF:
1764 case TGSI_OPCODE_TXF_LZ:
1765 args.opcode = opcode == TGSI_OPCODE_TXF_LZ ||
1766 target == TGSI_TEXTURE_2D_MSAA ||
1767 target == TGSI_TEXTURE_2D_ARRAY_MSAA ?
1768 ac_image_load : ac_image_load_mip;
1769 args.compare = false;
1770 args.offset = false;
1771 break;
1772 case TGSI_OPCODE_LODQ:
1773 args.opcode = ac_image_get_lod;
1774 args.compare = false;
1775 args.offset = false;
1776 break;
1777 case TGSI_OPCODE_TEX:
1778 case TGSI_OPCODE_TEX2:
1779 case TGSI_OPCODE_TXP:
1780 if (ctx->type != PIPE_SHADER_FRAGMENT)
1781 args.level_zero = true;
1782 break;
1783 case TGSI_OPCODE_TEX_LZ:
1784 args.level_zero = true;
1785 break;
1786 case TGSI_OPCODE_TXB:
1787 case TGSI_OPCODE_TXB2:
1788 assert(ctx->type == PIPE_SHADER_FRAGMENT);
1789 args.bias = true;
1790 break;
1791 case TGSI_OPCODE_TXL:
1792 case TGSI_OPCODE_TXL2:
1793 args.lod = true;
1794 break;
1795 case TGSI_OPCODE_TXD:
1796 args.deriv = true;
1797 break;
1798 case TGSI_OPCODE_TG4:
1799 args.opcode = ac_image_gather4;
1800 args.level_zero = true;
1801 break;
1802 default:
1803 assert(0);
1804 return;
1805 }
1806
1807 /* The hardware needs special lowering for Gather4 with integer formats. */
1808 if (ctx->screen->b.chip_class <= VI &&
1809 opcode == TGSI_OPCODE_TG4) {
1810 assert(inst->Texture.ReturnType != TGSI_RETURN_TYPE_UNKNOWN);
1811
1812 if (inst->Texture.ReturnType == TGSI_RETURN_TYPE_SINT ||
1813 inst->Texture.ReturnType == TGSI_RETURN_TYPE_UINT)
1814 si_lower_gather4_integer(ctx, &args, target);
1815 }
1816
1817 emit_data->output[emit_data->chan] =
1818 ac_build_image_opcode(&ctx->ac, &args);
1819 }
1820
1821 static void si_llvm_emit_txqs(
1822 const struct lp_build_tgsi_action *action,
1823 struct lp_build_tgsi_context *bld_base,
1824 struct lp_build_emit_data *emit_data)
1825 {
1826 struct si_shader_context *ctx = si_shader_context(bld_base);
1827 struct gallivm_state *gallivm = &ctx->gallivm;
1828 LLVMBuilderRef builder = gallivm->builder;
1829 LLVMValueRef res, samples;
1830 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
1831
1832 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
1833
1834
1835 /* Read the samples from the descriptor directly. */
1836 res = LLVMBuildBitCast(builder, res_ptr, ctx->v8i32, "");
1837 samples = LLVMBuildExtractElement(
1838 builder, res,
1839 LLVMConstInt(ctx->i32, 3, 0), "");
1840 samples = LLVMBuildLShr(builder, samples,
1841 LLVMConstInt(ctx->i32, 16, 0), "");
1842 samples = LLVMBuildAnd(builder, samples,
1843 LLVMConstInt(ctx->i32, 0xf, 0), "");
1844 samples = LLVMBuildShl(builder, ctx->i32_1,
1845 samples, "");
1846
1847 emit_data->output[emit_data->chan] = samples;
1848 }
1849
1850 static const struct lp_build_tgsi_action tex_action = {
1851 .fetch_args = tex_fetch_args,
1852 .emit = build_tex_intrinsic,
1853 };
1854
1855 /**
1856 * Setup actions for TGSI memory opcode, including texture opcodes.
1857 */
1858 void si_shader_context_init_mem(struct si_shader_context *ctx)
1859 {
1860 struct lp_build_tgsi_context *bld_base;
1861 struct lp_build_tgsi_action tmpl = {};
1862
1863 bld_base = &ctx->bld_base;
1864
1865 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
1866 bld_base->op_actions[TGSI_OPCODE_TEX_LZ] = tex_action;
1867 bld_base->op_actions[TGSI_OPCODE_TEX2] = tex_action;
1868 bld_base->op_actions[TGSI_OPCODE_TXB] = tex_action;
1869 bld_base->op_actions[TGSI_OPCODE_TXB2] = tex_action;
1870 bld_base->op_actions[TGSI_OPCODE_TXD] = tex_action;
1871 bld_base->op_actions[TGSI_OPCODE_TXF] = tex_action;
1872 bld_base->op_actions[TGSI_OPCODE_TXF_LZ] = tex_action;
1873 bld_base->op_actions[TGSI_OPCODE_TXL] = tex_action;
1874 bld_base->op_actions[TGSI_OPCODE_TXL2] = tex_action;
1875 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
1876 bld_base->op_actions[TGSI_OPCODE_TXQ].fetch_args = txq_fetch_args;
1877 bld_base->op_actions[TGSI_OPCODE_TXQ].emit = txq_emit;
1878 bld_base->op_actions[TGSI_OPCODE_TG4] = tex_action;
1879 bld_base->op_actions[TGSI_OPCODE_LODQ] = tex_action;
1880 bld_base->op_actions[TGSI_OPCODE_TXQS].emit = si_llvm_emit_txqs;
1881
1882 bld_base->op_actions[TGSI_OPCODE_LOAD].fetch_args = load_fetch_args;
1883 bld_base->op_actions[TGSI_OPCODE_LOAD].emit = load_emit;
1884 bld_base->op_actions[TGSI_OPCODE_STORE].fetch_args = store_fetch_args;
1885 bld_base->op_actions[TGSI_OPCODE_STORE].emit = store_emit;
1886 bld_base->op_actions[TGSI_OPCODE_RESQ].fetch_args = resq_fetch_args;
1887 bld_base->op_actions[TGSI_OPCODE_RESQ].emit = resq_emit;
1888
1889 tmpl.fetch_args = atomic_fetch_args;
1890 tmpl.emit = atomic_emit;
1891 bld_base->op_actions[TGSI_OPCODE_ATOMUADD] = tmpl;
1892 bld_base->op_actions[TGSI_OPCODE_ATOMUADD].intr_name = "add";
1893 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG] = tmpl;
1894 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG].intr_name = "swap";
1895 bld_base->op_actions[TGSI_OPCODE_ATOMCAS] = tmpl;
1896 bld_base->op_actions[TGSI_OPCODE_ATOMCAS].intr_name = "cmpswap";
1897 bld_base->op_actions[TGSI_OPCODE_ATOMAND] = tmpl;
1898 bld_base->op_actions[TGSI_OPCODE_ATOMAND].intr_name = "and";
1899 bld_base->op_actions[TGSI_OPCODE_ATOMOR] = tmpl;
1900 bld_base->op_actions[TGSI_OPCODE_ATOMOR].intr_name = "or";
1901 bld_base->op_actions[TGSI_OPCODE_ATOMXOR] = tmpl;
1902 bld_base->op_actions[TGSI_OPCODE_ATOMXOR].intr_name = "xor";
1903 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN] = tmpl;
1904 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN].intr_name = "umin";
1905 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX] = tmpl;
1906 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX].intr_name = "umax";
1907 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN] = tmpl;
1908 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN].intr_name = "smin";
1909 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX] = tmpl;
1910 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX].intr_name = "smax";
1911 }