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radeonsi: move FMASK shader logic to shared code
[mesa.git] / src / gallium / drivers / radeonsi / si_shader_tgsi_mem.c
1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "si_shader_internal.h"
25 #include "si_pipe.h"
26 #include "sid.h"
27 #include "gallivm/lp_bld_arit.h"
28 #include "gallivm/lp_bld_gather.h"
29 #include "gallivm/lp_bld_intr.h"
30 #include "tgsi/tgsi_build.h"
31 #include "tgsi/tgsi_parse.h"
32 #include "tgsi/tgsi_util.h"
33
34 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
35 struct lp_build_tgsi_context *bld_base,
36 struct lp_build_emit_data *emit_data);
37
38 static const struct lp_build_tgsi_action tex_action;
39
40 /**
41 * Given a v8i32 resource descriptor for a buffer, extract the size of the
42 * buffer in number of elements and return it as an i32.
43 */
44 static LLVMValueRef get_buffer_size(
45 struct lp_build_tgsi_context *bld_base,
46 LLVMValueRef descriptor)
47 {
48 struct si_shader_context *ctx = si_shader_context(bld_base);
49 LLVMBuilderRef builder = ctx->ac.builder;
50 LLVMValueRef size =
51 LLVMBuildExtractElement(builder, descriptor,
52 LLVMConstInt(ctx->i32, 2, 0), "");
53
54 if (ctx->screen->info.chip_class == VI) {
55 /* On VI, the descriptor contains the size in bytes,
56 * but TXQ must return the size in elements.
57 * The stride is always non-zero for resources using TXQ.
58 */
59 LLVMValueRef stride =
60 LLVMBuildExtractElement(builder, descriptor,
61 ctx->i32_1, "");
62 stride = LLVMBuildLShr(builder, stride,
63 LLVMConstInt(ctx->i32, 16, 0), "");
64 stride = LLVMBuildAnd(builder, stride,
65 LLVMConstInt(ctx->i32, 0x3FFF, 0), "");
66
67 size = LLVMBuildUDiv(builder, size, stride, "");
68 }
69
70 return size;
71 }
72
73 static LLVMValueRef
74 shader_buffer_fetch_rsrc(struct si_shader_context *ctx,
75 const struct tgsi_full_src_register *reg,
76 bool ubo)
77 {
78 LLVMValueRef index;
79
80 if (!reg->Register.Indirect) {
81 index = LLVMConstInt(ctx->i32, reg->Register.Index, false);
82 } else {
83 index = si_get_indirect_index(ctx, &reg->Indirect,
84 1, reg->Register.Index);
85 }
86
87 if (ubo)
88 return ctx->abi.load_ubo(&ctx->abi, index);
89 else
90 return ctx->abi.load_ssbo(&ctx->abi, index, false);
91 }
92
93 static bool tgsi_is_array_image(unsigned target)
94 {
95 return target == TGSI_TEXTURE_3D ||
96 target == TGSI_TEXTURE_CUBE ||
97 target == TGSI_TEXTURE_1D_ARRAY ||
98 target == TGSI_TEXTURE_2D_ARRAY ||
99 target == TGSI_TEXTURE_CUBE_ARRAY ||
100 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
101 }
102
103 /**
104 * Given a 256-bit resource descriptor, force the DCC enable bit to off.
105 *
106 * At least on Tonga, executing image stores on images with DCC enabled and
107 * non-trivial can eventually lead to lockups. This can occur when an
108 * application binds an image as read-only but then uses a shader that writes
109 * to it. The OpenGL spec allows almost arbitrarily bad behavior (including
110 * program termination) in this case, but it doesn't cost much to be a bit
111 * nicer: disabling DCC in the shader still leads to undefined results but
112 * avoids the lockup.
113 */
114 static LLVMValueRef force_dcc_off(struct si_shader_context *ctx,
115 LLVMValueRef rsrc)
116 {
117 if (ctx->screen->info.chip_class <= CIK) {
118 return rsrc;
119 } else {
120 LLVMValueRef i32_6 = LLVMConstInt(ctx->i32, 6, 0);
121 LLVMValueRef i32_C = LLVMConstInt(ctx->i32, C_008F28_COMPRESSION_EN, 0);
122 LLVMValueRef tmp;
123
124 tmp = LLVMBuildExtractElement(ctx->ac.builder, rsrc, i32_6, "");
125 tmp = LLVMBuildAnd(ctx->ac.builder, tmp, i32_C, "");
126 return LLVMBuildInsertElement(ctx->ac.builder, rsrc, tmp, i32_6, "");
127 }
128 }
129
130 LLVMValueRef si_load_image_desc(struct si_shader_context *ctx,
131 LLVMValueRef list, LLVMValueRef index,
132 enum ac_descriptor_type desc_type, bool dcc_off)
133 {
134 LLVMBuilderRef builder = ctx->ac.builder;
135 LLVMValueRef rsrc;
136
137 if (desc_type == AC_DESC_BUFFER) {
138 index = LLVMBuildMul(builder, index,
139 LLVMConstInt(ctx->i32, 2, 0), "");
140 index = LLVMBuildAdd(builder, index,
141 ctx->i32_1, "");
142 list = LLVMBuildPointerCast(builder, list,
143 ac_array_in_const32_addr_space(ctx->v4i32), "");
144 } else {
145 assert(desc_type == AC_DESC_IMAGE);
146 }
147
148 rsrc = ac_build_load_to_sgpr(&ctx->ac, list, index);
149 if (desc_type == AC_DESC_IMAGE && dcc_off)
150 rsrc = force_dcc_off(ctx, rsrc);
151 return rsrc;
152 }
153
154 /**
155 * Load the resource descriptor for \p image.
156 */
157 static void
158 image_fetch_rsrc(
159 struct lp_build_tgsi_context *bld_base,
160 const struct tgsi_full_src_register *image,
161 bool is_store, unsigned target,
162 LLVMValueRef *rsrc)
163 {
164 struct si_shader_context *ctx = si_shader_context(bld_base);
165 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
166 ctx->param_samplers_and_images);
167 LLVMValueRef index;
168 bool dcc_off = is_store;
169
170 if (!image->Register.Indirect) {
171 const struct tgsi_shader_info *info = bld_base->info;
172 unsigned images_writemask = info->images_store |
173 info->images_atomic;
174
175 index = LLVMConstInt(ctx->i32,
176 si_get_image_slot(image->Register.Index), 0);
177
178 if (images_writemask & (1 << image->Register.Index))
179 dcc_off = true;
180 } else {
181 /* From the GL_ARB_shader_image_load_store extension spec:
182 *
183 * If a shader performs an image load, store, or atomic
184 * operation using an image variable declared as an array,
185 * and if the index used to select an individual element is
186 * negative or greater than or equal to the size of the
187 * array, the results of the operation are undefined but may
188 * not lead to termination.
189 */
190 index = si_get_bounded_indirect_index(ctx, &image->Indirect,
191 image->Register.Index,
192 ctx->num_images);
193 index = LLVMBuildSub(ctx->ac.builder,
194 LLVMConstInt(ctx->i32, SI_NUM_IMAGES - 1, 0),
195 index, "");
196 }
197
198 if (image->Register.File != TGSI_FILE_IMAGE) {
199 /* Bindless descriptors are accessible from a different pair of
200 * user SGPR indices.
201 */
202 rsrc_ptr = LLVMGetParam(ctx->main_fn,
203 ctx->param_bindless_samplers_and_images);
204 index = lp_build_emit_fetch_src(bld_base, image,
205 TGSI_TYPE_UNSIGNED, 0);
206
207 /* For simplicity, bindless image descriptors use fixed
208 * 16-dword slots for now.
209 */
210 index = LLVMBuildMul(ctx->ac.builder, index,
211 LLVMConstInt(ctx->i32, 2, 0), "");
212 }
213
214 *rsrc = si_load_image_desc(ctx, rsrc_ptr, index,
215 target == TGSI_TEXTURE_BUFFER ? AC_DESC_BUFFER : AC_DESC_IMAGE,
216 dcc_off);
217 }
218
219 static LLVMValueRef image_fetch_coords(
220 struct lp_build_tgsi_context *bld_base,
221 const struct tgsi_full_instruction *inst,
222 unsigned src, LLVMValueRef desc)
223 {
224 struct si_shader_context *ctx = si_shader_context(bld_base);
225 LLVMBuilderRef builder = ctx->ac.builder;
226 unsigned target = inst->Memory.Texture;
227 unsigned num_coords = tgsi_util_get_texture_coord_dim(target);
228 LLVMValueRef coords[4];
229 LLVMValueRef tmp;
230 int chan;
231
232 for (chan = 0; chan < num_coords; ++chan) {
233 tmp = lp_build_emit_fetch(bld_base, inst, src, chan);
234 tmp = ac_to_integer(&ctx->ac, tmp);
235 coords[chan] = tmp;
236 }
237
238 if (ctx->screen->info.chip_class >= GFX9) {
239 /* 1D textures are allocated and used as 2D on GFX9. */
240 if (target == TGSI_TEXTURE_1D) {
241 coords[1] = ctx->i32_0;
242 num_coords++;
243 } else if (target == TGSI_TEXTURE_1D_ARRAY) {
244 coords[2] = coords[1];
245 coords[1] = ctx->i32_0;
246 num_coords++;
247 } else if (target == TGSI_TEXTURE_2D) {
248 /* The hw can't bind a slice of a 3D image as a 2D
249 * image, because it ignores BASE_ARRAY if the target
250 * is 3D. The workaround is to read BASE_ARRAY and set
251 * it as the 3rd address operand for all 2D images.
252 */
253 LLVMValueRef first_layer, const5, mask;
254
255 const5 = LLVMConstInt(ctx->i32, 5, 0);
256 mask = LLVMConstInt(ctx->i32, S_008F24_BASE_ARRAY(~0), 0);
257 first_layer = LLVMBuildExtractElement(builder, desc, const5, "");
258 first_layer = LLVMBuildAnd(builder, first_layer, mask, "");
259
260 coords[2] = first_layer;
261 num_coords++;
262 }
263 }
264
265 if (num_coords == 1)
266 return coords[0];
267
268 if (num_coords == 3) {
269 /* LLVM has difficulties lowering 3-element vectors. */
270 coords[3] = bld_base->uint_bld.undef;
271 num_coords = 4;
272 }
273
274 return lp_build_gather_values(&ctx->gallivm, coords, num_coords);
275 }
276
277 /**
278 * Append the extra mode bits that are used by image load and store.
279 */
280 static void image_append_args(
281 struct si_shader_context *ctx,
282 struct lp_build_emit_data * emit_data,
283 unsigned target,
284 bool atomic,
285 bool force_glc)
286 {
287 const struct tgsi_full_instruction *inst = emit_data->inst;
288 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
289 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
290 LLVMValueRef r128 = i1false;
291 LLVMValueRef da = tgsi_is_array_image(target) ? i1true : i1false;
292 LLVMValueRef glc =
293 force_glc ||
294 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE) ?
295 i1true : i1false;
296 LLVMValueRef slc = i1false;
297 LLVMValueRef lwe = i1false;
298
299 if (atomic) {
300 emit_data->args[emit_data->arg_count++] = r128;
301 emit_data->args[emit_data->arg_count++] = da;
302 if (!atomic) {
303 emit_data->args[emit_data->arg_count++] = glc;
304 }
305 emit_data->args[emit_data->arg_count++] = slc;
306 return;
307 }
308
309 emit_data->args[emit_data->arg_count++] = glc;
310 emit_data->args[emit_data->arg_count++] = slc;
311 emit_data->args[emit_data->arg_count++] = lwe;
312 emit_data->args[emit_data->arg_count++] = da;
313 }
314
315 /**
316 * Append the resource and indexing arguments for buffer intrinsics.
317 *
318 * \param rsrc the v4i32 buffer resource
319 * \param index index into the buffer (stride-based)
320 * \param offset byte offset into the buffer
321 */
322 static void buffer_append_args(
323 struct si_shader_context *ctx,
324 struct lp_build_emit_data *emit_data,
325 LLVMValueRef rsrc,
326 LLVMValueRef index,
327 LLVMValueRef offset,
328 bool atomic,
329 bool force_glc)
330 {
331 const struct tgsi_full_instruction *inst = emit_data->inst;
332 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
333 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
334
335 emit_data->args[emit_data->arg_count++] = rsrc;
336 emit_data->args[emit_data->arg_count++] = index; /* vindex */
337 emit_data->args[emit_data->arg_count++] = offset; /* voffset */
338 if (!atomic) {
339 emit_data->args[emit_data->arg_count++] =
340 force_glc ||
341 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE) ?
342 i1true : i1false; /* glc */
343 }
344 emit_data->args[emit_data->arg_count++] = i1false; /* slc */
345 }
346
347 static void load_fetch_args(
348 struct lp_build_tgsi_context * bld_base,
349 struct lp_build_emit_data * emit_data)
350 {
351 struct si_shader_context *ctx = si_shader_context(bld_base);
352 const struct tgsi_full_instruction * inst = emit_data->inst;
353 unsigned target = inst->Memory.Texture;
354 LLVMValueRef rsrc;
355
356 emit_data->dst_type = ctx->v4f32;
357
358 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
359 inst->Src[0].Register.File == TGSI_FILE_CONSTBUF) {
360 LLVMValueRef offset;
361 LLVMValueRef tmp;
362
363 bool ubo = inst->Src[0].Register.File == TGSI_FILE_CONSTBUF;
364 rsrc = shader_buffer_fetch_rsrc(ctx, &inst->Src[0], ubo);
365
366 tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
367 offset = ac_to_integer(&ctx->ac, tmp);
368
369 buffer_append_args(ctx, emit_data, rsrc, ctx->i32_0,
370 offset, false, false);
371 } else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE ||
372 tgsi_is_bindless_image_file(inst->Src[0].Register.File)) {
373 LLVMValueRef coords;
374
375 image_fetch_rsrc(bld_base, &inst->Src[0], false, target, &rsrc);
376 coords = image_fetch_coords(bld_base, inst, 1, rsrc);
377
378 if (target == TGSI_TEXTURE_BUFFER) {
379 buffer_append_args(ctx, emit_data, rsrc, coords,
380 ctx->i32_0, false, false);
381 } else {
382 emit_data->args[0] = coords;
383 emit_data->args[1] = rsrc;
384 emit_data->args[2] = LLVMConstInt(ctx->i32, 15, 0); /* dmask */
385 emit_data->arg_count = 3;
386
387 image_append_args(ctx, emit_data, target, false, false);
388 }
389 }
390 }
391
392 static void load_emit_buffer(struct si_shader_context *ctx,
393 struct lp_build_emit_data *emit_data,
394 bool can_speculate, bool allow_smem)
395 {
396 const struct tgsi_full_instruction *inst = emit_data->inst;
397 uint writemask = inst->Dst[0].Register.WriteMask;
398 uint count = util_last_bit(writemask);
399 LLVMValueRef *args = emit_data->args;
400
401 /* Don't use SMEM for shader buffer loads, because LLVM doesn't
402 * select SMEM for SI.load.const with a non-constant offset, and
403 * constant offsets practically don't exist with shader buffers.
404 *
405 * Also, SI.load.const doesn't use inst_offset when it's lowered
406 * to VMEM, so we just end up with more VALU instructions in the end
407 * and no benefit.
408 *
409 * TODO: Remove this line once LLVM can select SMEM with a non-constant
410 * offset, and can derive inst_offset when VMEM is selected.
411 * After that, si_memory_barrier should invalidate sL1 for shader
412 * buffers.
413 */
414
415 assert(LLVMConstIntGetZExtValue(args[1]) == 0); /* vindex */
416 emit_data->output[emit_data->chan] =
417 ac_build_buffer_load(&ctx->ac, args[0], count, NULL,
418 args[2], NULL, 0,
419 LLVMConstIntGetZExtValue(args[3]),
420 LLVMConstIntGetZExtValue(args[4]),
421 can_speculate, allow_smem);
422 }
423
424 static LLVMValueRef get_memory_ptr(struct si_shader_context *ctx,
425 const struct tgsi_full_instruction *inst,
426 LLVMTypeRef type, int arg)
427 {
428 LLVMBuilderRef builder = ctx->ac.builder;
429 LLVMValueRef offset, ptr;
430 int addr_space;
431
432 offset = lp_build_emit_fetch(&ctx->bld_base, inst, arg, 0);
433 offset = ac_to_integer(&ctx->ac, offset);
434
435 ptr = ctx->ac.lds;
436 ptr = LLVMBuildGEP(builder, ptr, &offset, 1, "");
437 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
438 ptr = LLVMBuildBitCast(builder, ptr, LLVMPointerType(type, addr_space), "");
439
440 return ptr;
441 }
442
443 static void load_emit_memory(
444 struct si_shader_context *ctx,
445 struct lp_build_emit_data *emit_data)
446 {
447 const struct tgsi_full_instruction *inst = emit_data->inst;
448 unsigned writemask = inst->Dst[0].Register.WriteMask;
449 LLVMValueRef channels[4], ptr, derived_ptr, index;
450 int chan;
451
452 ptr = get_memory_ptr(ctx, inst, ctx->f32, 1);
453
454 for (chan = 0; chan < 4; ++chan) {
455 if (!(writemask & (1 << chan))) {
456 channels[chan] = LLVMGetUndef(ctx->f32);
457 continue;
458 }
459
460 index = LLVMConstInt(ctx->i32, chan, 0);
461 derived_ptr = LLVMBuildGEP(ctx->ac.builder, ptr, &index, 1, "");
462 channels[chan] = LLVMBuildLoad(ctx->ac.builder, derived_ptr, "");
463 }
464 emit_data->output[emit_data->chan] = lp_build_gather_values(&ctx->gallivm, channels, 4);
465 }
466
467 /**
468 * Return true if the memory accessed by a LOAD or STORE instruction is
469 * read-only or write-only, respectively.
470 *
471 * \param shader_buffers_reverse_access_mask
472 * For LOAD, set this to (store | atomic) slot usage in the shader.
473 * For STORE, set this to (load | atomic) slot usage in the shader.
474 * \param images_reverse_access_mask Same as above, but for images.
475 */
476 static bool is_oneway_access_only(const struct tgsi_full_instruction *inst,
477 const struct tgsi_shader_info *info,
478 unsigned shader_buffers_reverse_access_mask,
479 unsigned images_reverse_access_mask)
480 {
481 /* RESTRICT means NOALIAS.
482 * If there are no writes, we can assume the accessed memory is read-only.
483 * If there are no reads, we can assume the accessed memory is write-only.
484 */
485 if (inst->Memory.Qualifier & TGSI_MEMORY_RESTRICT) {
486 unsigned reverse_access_mask;
487
488 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
489 reverse_access_mask = shader_buffers_reverse_access_mask;
490 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
491 reverse_access_mask = info->images_buffers &
492 images_reverse_access_mask;
493 } else {
494 reverse_access_mask = ~info->images_buffers &
495 images_reverse_access_mask;
496 }
497
498 if (inst->Src[0].Register.Indirect) {
499 if (!reverse_access_mask)
500 return true;
501 } else {
502 if (!(reverse_access_mask &
503 (1u << inst->Src[0].Register.Index)))
504 return true;
505 }
506 }
507
508 /* If there are no buffer writes (for both shader buffers & image
509 * buffers), it implies that buffer memory is read-only.
510 * If there are no buffer reads (for both shader buffers & image
511 * buffers), it implies that buffer memory is write-only.
512 *
513 * Same for the case when there are no writes/reads for non-buffer
514 * images.
515 */
516 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
517 (inst->Memory.Texture == TGSI_TEXTURE_BUFFER &&
518 (inst->Src[0].Register.File == TGSI_FILE_IMAGE ||
519 tgsi_is_bindless_image_file(inst->Src[0].Register.File)))) {
520 if (!shader_buffers_reverse_access_mask &&
521 !(info->images_buffers & images_reverse_access_mask))
522 return true;
523 } else {
524 if (!(~info->images_buffers & images_reverse_access_mask))
525 return true;
526 }
527 return false;
528 }
529
530 static void load_emit(
531 const struct lp_build_tgsi_action *action,
532 struct lp_build_tgsi_context *bld_base,
533 struct lp_build_emit_data *emit_data)
534 {
535 struct si_shader_context *ctx = si_shader_context(bld_base);
536 LLVMBuilderRef builder = ctx->ac.builder;
537 const struct tgsi_full_instruction * inst = emit_data->inst;
538 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
539 char intrinsic_name[64];
540 bool can_speculate = false;
541
542 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
543 load_emit_memory(ctx, emit_data);
544 return;
545 }
546
547 if (inst->Src[0].Register.File == TGSI_FILE_CONSTBUF) {
548 load_emit_buffer(ctx, emit_data, true, true);
549 return;
550 }
551
552 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
553 ac_build_waitcnt(&ctx->ac, VM_CNT);
554
555 can_speculate = !(inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE) &&
556 is_oneway_access_only(inst, info,
557 info->shader_buffers_store |
558 info->shader_buffers_atomic,
559 info->images_store |
560 info->images_atomic);
561
562 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
563 load_emit_buffer(ctx, emit_data, can_speculate, false);
564 return;
565 }
566
567 if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
568 unsigned num_channels = util_last_bit(inst->Dst[0].Register.WriteMask);
569 LLVMValueRef result =
570 ac_build_buffer_load_format(&ctx->ac,
571 emit_data->args[0],
572 emit_data->args[1],
573 emit_data->args[2],
574 num_channels,
575 LLVMConstIntGetZExtValue(emit_data->args[3]),
576 can_speculate);
577 emit_data->output[emit_data->chan] =
578 ac_build_expand_to_vec4(&ctx->ac, result, num_channels);
579 } else {
580 ac_get_image_intr_name("llvm.amdgcn.image.load",
581 emit_data->dst_type, /* vdata */
582 LLVMTypeOf(emit_data->args[0]), /* coords */
583 LLVMTypeOf(emit_data->args[1]), /* rsrc */
584 intrinsic_name, sizeof(intrinsic_name));
585
586 emit_data->output[emit_data->chan] =
587 lp_build_intrinsic(
588 builder, intrinsic_name, emit_data->dst_type,
589 emit_data->args, emit_data->arg_count,
590 ac_get_load_intr_attribs(can_speculate));
591 }
592 }
593
594 static void store_fetch_args(
595 struct lp_build_tgsi_context * bld_base,
596 struct lp_build_emit_data * emit_data)
597 {
598 struct si_shader_context *ctx = si_shader_context(bld_base);
599 const struct tgsi_full_instruction * inst = emit_data->inst;
600 struct tgsi_full_src_register memory;
601 LLVMValueRef chans[4];
602 LLVMValueRef data;
603 LLVMValueRef rsrc;
604 unsigned chan;
605
606 emit_data->dst_type = ctx->voidt;
607
608 for (chan = 0; chan < 4; ++chan) {
609 chans[chan] = lp_build_emit_fetch(bld_base, inst, 1, chan);
610 }
611 data = lp_build_gather_values(&ctx->gallivm, chans, 4);
612
613 emit_data->args[emit_data->arg_count++] = data;
614
615 memory = tgsi_full_src_register_from_dst(&inst->Dst[0]);
616
617 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
618 LLVMValueRef offset;
619 LLVMValueRef tmp;
620
621 rsrc = shader_buffer_fetch_rsrc(ctx, &memory, false);
622
623 tmp = lp_build_emit_fetch(bld_base, inst, 0, 0);
624 offset = ac_to_integer(&ctx->ac, tmp);
625
626 buffer_append_args(ctx, emit_data, rsrc, ctx->i32_0,
627 offset, false, false);
628 } else if (inst->Dst[0].Register.File == TGSI_FILE_IMAGE ||
629 tgsi_is_bindless_image_file(inst->Dst[0].Register.File)) {
630 unsigned target = inst->Memory.Texture;
631 LLVMValueRef coords;
632
633 /* 8bit/16bit TC L1 write corruption bug on SI.
634 * All store opcodes not aligned to a dword are affected.
635 *
636 * The only way to get unaligned stores in radeonsi is through
637 * shader images.
638 */
639 bool force_glc = ctx->screen->info.chip_class == SI;
640
641 image_fetch_rsrc(bld_base, &memory, true, target, &rsrc);
642 coords = image_fetch_coords(bld_base, inst, 0, rsrc);
643
644 if (target == TGSI_TEXTURE_BUFFER) {
645 buffer_append_args(ctx, emit_data, rsrc, coords,
646 ctx->i32_0, false, force_glc);
647 } else {
648 emit_data->args[1] = coords;
649 emit_data->args[2] = rsrc;
650 emit_data->args[3] = LLVMConstInt(ctx->i32, 15, 0); /* dmask */
651 emit_data->arg_count = 4;
652
653 image_append_args(ctx, emit_data, target, false, force_glc);
654 }
655 }
656 }
657
658 static void store_emit_buffer(
659 struct si_shader_context *ctx,
660 struct lp_build_emit_data *emit_data,
661 bool writeonly_memory)
662 {
663 const struct tgsi_full_instruction *inst = emit_data->inst;
664 LLVMBuilderRef builder = ctx->ac.builder;
665 LLVMValueRef base_data = emit_data->args[0];
666 LLVMValueRef base_offset = emit_data->args[3];
667 unsigned writemask = inst->Dst[0].Register.WriteMask;
668
669 while (writemask) {
670 int start, count;
671 const char *intrinsic_name;
672 LLVMValueRef data;
673 LLVMValueRef offset;
674 LLVMValueRef tmp;
675
676 u_bit_scan_consecutive_range(&writemask, &start, &count);
677
678 /* Due to an LLVM limitation, split 3-element writes
679 * into a 2-element and a 1-element write. */
680 if (count == 3) {
681 writemask |= 1 << (start + 2);
682 count = 2;
683 }
684
685 if (count == 4) {
686 data = base_data;
687 intrinsic_name = "llvm.amdgcn.buffer.store.v4f32";
688 } else if (count == 2) {
689 LLVMTypeRef v2f32 = LLVMVectorType(ctx->f32, 2);
690
691 tmp = LLVMBuildExtractElement(
692 builder, base_data,
693 LLVMConstInt(ctx->i32, start, 0), "");
694 data = LLVMBuildInsertElement(
695 builder, LLVMGetUndef(v2f32), tmp,
696 ctx->i32_0, "");
697
698 tmp = LLVMBuildExtractElement(
699 builder, base_data,
700 LLVMConstInt(ctx->i32, start + 1, 0), "");
701 data = LLVMBuildInsertElement(
702 builder, data, tmp, ctx->i32_1, "");
703
704 intrinsic_name = "llvm.amdgcn.buffer.store.v2f32";
705 } else {
706 assert(count == 1);
707 data = LLVMBuildExtractElement(
708 builder, base_data,
709 LLVMConstInt(ctx->i32, start, 0), "");
710 intrinsic_name = "llvm.amdgcn.buffer.store.f32";
711 }
712
713 offset = base_offset;
714 if (start != 0) {
715 offset = LLVMBuildAdd(
716 builder, offset,
717 LLVMConstInt(ctx->i32, start * 4, 0), "");
718 }
719
720 emit_data->args[0] = data;
721 emit_data->args[3] = offset;
722
723 lp_build_intrinsic(
724 builder, intrinsic_name, emit_data->dst_type,
725 emit_data->args, emit_data->arg_count,
726 ac_get_store_intr_attribs(writeonly_memory));
727 }
728 }
729
730 static void store_emit_memory(
731 struct si_shader_context *ctx,
732 struct lp_build_emit_data *emit_data)
733 {
734 const struct tgsi_full_instruction *inst = emit_data->inst;
735 LLVMBuilderRef builder = ctx->ac.builder;
736 unsigned writemask = inst->Dst[0].Register.WriteMask;
737 LLVMValueRef ptr, derived_ptr, data, index;
738 int chan;
739
740 ptr = get_memory_ptr(ctx, inst, ctx->f32, 0);
741
742 for (chan = 0; chan < 4; ++chan) {
743 if (!(writemask & (1 << chan))) {
744 continue;
745 }
746 data = lp_build_emit_fetch(&ctx->bld_base, inst, 1, chan);
747 index = LLVMConstInt(ctx->i32, chan, 0);
748 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
749 LLVMBuildStore(builder, data, derived_ptr);
750 }
751 }
752
753 static void store_emit(
754 const struct lp_build_tgsi_action *action,
755 struct lp_build_tgsi_context *bld_base,
756 struct lp_build_emit_data *emit_data)
757 {
758 struct si_shader_context *ctx = si_shader_context(bld_base);
759 LLVMBuilderRef builder = ctx->ac.builder;
760 const struct tgsi_full_instruction * inst = emit_data->inst;
761 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
762 unsigned target = inst->Memory.Texture;
763 char intrinsic_name[64];
764 bool writeonly_memory = false;
765
766 if (inst->Dst[0].Register.File == TGSI_FILE_MEMORY) {
767 store_emit_memory(ctx, emit_data);
768 return;
769 }
770
771 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
772 ac_build_waitcnt(&ctx->ac, VM_CNT);
773
774 writeonly_memory = is_oneway_access_only(inst, info,
775 info->shader_buffers_load |
776 info->shader_buffers_atomic,
777 info->images_load |
778 info->images_atomic);
779
780 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
781 store_emit_buffer(ctx, emit_data, writeonly_memory);
782 return;
783 }
784
785 if (target == TGSI_TEXTURE_BUFFER) {
786 emit_data->output[emit_data->chan] = lp_build_intrinsic(
787 builder, "llvm.amdgcn.buffer.store.format.v4f32",
788 emit_data->dst_type, emit_data->args,
789 emit_data->arg_count,
790 ac_get_store_intr_attribs(writeonly_memory));
791 } else {
792 ac_get_image_intr_name("llvm.amdgcn.image.store",
793 LLVMTypeOf(emit_data->args[0]), /* vdata */
794 LLVMTypeOf(emit_data->args[1]), /* coords */
795 LLVMTypeOf(emit_data->args[2]), /* rsrc */
796 intrinsic_name, sizeof(intrinsic_name));
797
798 emit_data->output[emit_data->chan] =
799 lp_build_intrinsic(
800 builder, intrinsic_name, emit_data->dst_type,
801 emit_data->args, emit_data->arg_count,
802 ac_get_store_intr_attribs(writeonly_memory));
803 }
804 }
805
806 static void atomic_fetch_args(
807 struct lp_build_tgsi_context * bld_base,
808 struct lp_build_emit_data * emit_data)
809 {
810 struct si_shader_context *ctx = si_shader_context(bld_base);
811 const struct tgsi_full_instruction * inst = emit_data->inst;
812 LLVMValueRef data1, data2;
813 LLVMValueRef rsrc;
814 LLVMValueRef tmp;
815
816 emit_data->dst_type = ctx->f32;
817
818 tmp = lp_build_emit_fetch(bld_base, inst, 2, 0);
819 data1 = ac_to_integer(&ctx->ac, tmp);
820
821 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
822 tmp = lp_build_emit_fetch(bld_base, inst, 3, 0);
823 data2 = ac_to_integer(&ctx->ac, tmp);
824 }
825
826 /* llvm.amdgcn.image/buffer.atomic.cmpswap reflect the hardware order
827 * of arguments, which is reversed relative to TGSI (and GLSL)
828 */
829 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
830 emit_data->args[emit_data->arg_count++] = data2;
831 emit_data->args[emit_data->arg_count++] = data1;
832
833 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
834 LLVMValueRef offset;
835
836 rsrc = shader_buffer_fetch_rsrc(ctx, &inst->Src[0], false);
837
838 tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
839 offset = ac_to_integer(&ctx->ac, tmp);
840
841 buffer_append_args(ctx, emit_data, rsrc, ctx->i32_0,
842 offset, true, false);
843 } else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE ||
844 tgsi_is_bindless_image_file(inst->Src[0].Register.File)) {
845 unsigned target = inst->Memory.Texture;
846 LLVMValueRef coords;
847
848 image_fetch_rsrc(bld_base, &inst->Src[0], true, target, &rsrc);
849 coords = image_fetch_coords(bld_base, inst, 1, rsrc);
850
851 if (target == TGSI_TEXTURE_BUFFER) {
852 buffer_append_args(ctx, emit_data, rsrc, coords,
853 ctx->i32_0, true, false);
854 } else {
855 emit_data->args[emit_data->arg_count++] = coords;
856 emit_data->args[emit_data->arg_count++] = rsrc;
857
858 image_append_args(ctx, emit_data, target, true, false);
859 }
860 }
861 }
862
863 static void atomic_emit_memory(struct si_shader_context *ctx,
864 struct lp_build_emit_data *emit_data) {
865 LLVMBuilderRef builder = ctx->ac.builder;
866 const struct tgsi_full_instruction * inst = emit_data->inst;
867 LLVMValueRef ptr, result, arg;
868
869 ptr = get_memory_ptr(ctx, inst, ctx->i32, 1);
870
871 arg = lp_build_emit_fetch(&ctx->bld_base, inst, 2, 0);
872 arg = ac_to_integer(&ctx->ac, arg);
873
874 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
875 LLVMValueRef new_data;
876 new_data = lp_build_emit_fetch(&ctx->bld_base,
877 inst, 3, 0);
878
879 new_data = ac_to_integer(&ctx->ac, new_data);
880
881 result = LLVMBuildAtomicCmpXchg(builder, ptr, arg, new_data,
882 LLVMAtomicOrderingSequentiallyConsistent,
883 LLVMAtomicOrderingSequentiallyConsistent,
884 false);
885
886 result = LLVMBuildExtractValue(builder, result, 0, "");
887 } else {
888 LLVMAtomicRMWBinOp op;
889
890 switch(inst->Instruction.Opcode) {
891 case TGSI_OPCODE_ATOMUADD:
892 op = LLVMAtomicRMWBinOpAdd;
893 break;
894 case TGSI_OPCODE_ATOMXCHG:
895 op = LLVMAtomicRMWBinOpXchg;
896 break;
897 case TGSI_OPCODE_ATOMAND:
898 op = LLVMAtomicRMWBinOpAnd;
899 break;
900 case TGSI_OPCODE_ATOMOR:
901 op = LLVMAtomicRMWBinOpOr;
902 break;
903 case TGSI_OPCODE_ATOMXOR:
904 op = LLVMAtomicRMWBinOpXor;
905 break;
906 case TGSI_OPCODE_ATOMUMIN:
907 op = LLVMAtomicRMWBinOpUMin;
908 break;
909 case TGSI_OPCODE_ATOMUMAX:
910 op = LLVMAtomicRMWBinOpUMax;
911 break;
912 case TGSI_OPCODE_ATOMIMIN:
913 op = LLVMAtomicRMWBinOpMin;
914 break;
915 case TGSI_OPCODE_ATOMIMAX:
916 op = LLVMAtomicRMWBinOpMax;
917 break;
918 default:
919 unreachable("unknown atomic opcode");
920 }
921
922 result = LLVMBuildAtomicRMW(builder, op, ptr, arg,
923 LLVMAtomicOrderingSequentiallyConsistent,
924 false);
925 }
926 emit_data->output[emit_data->chan] = LLVMBuildBitCast(builder, result, emit_data->dst_type, "");
927 }
928
929 static void atomic_emit(
930 const struct lp_build_tgsi_action *action,
931 struct lp_build_tgsi_context *bld_base,
932 struct lp_build_emit_data *emit_data)
933 {
934 struct si_shader_context *ctx = si_shader_context(bld_base);
935 LLVMBuilderRef builder = ctx->ac.builder;
936 const struct tgsi_full_instruction * inst = emit_data->inst;
937 char intrinsic_name[40];
938 LLVMValueRef tmp;
939
940 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
941 atomic_emit_memory(ctx, emit_data);
942 return;
943 }
944
945 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
946 inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
947 snprintf(intrinsic_name, sizeof(intrinsic_name),
948 "llvm.amdgcn.buffer.atomic.%s", action->intr_name);
949 } else {
950 LLVMValueRef coords;
951 char coords_type[8];
952
953 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
954 coords = emit_data->args[2];
955 else
956 coords = emit_data->args[1];
957
958 ac_build_type_name_for_intr(LLVMTypeOf(coords), coords_type, sizeof(coords_type));
959 snprintf(intrinsic_name, sizeof(intrinsic_name),
960 "llvm.amdgcn.image.atomic.%s.%s",
961 action->intr_name, coords_type);
962 }
963
964 tmp = lp_build_intrinsic(
965 builder, intrinsic_name, ctx->i32,
966 emit_data->args, emit_data->arg_count, 0);
967 emit_data->output[emit_data->chan] = ac_to_float(&ctx->ac, tmp);
968 }
969
970 static void set_tex_fetch_args(struct si_shader_context *ctx,
971 struct lp_build_emit_data *emit_data,
972 unsigned target,
973 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
974 LLVMValueRef *param, unsigned count,
975 unsigned dmask)
976 {
977 struct ac_image_args args = {};
978
979 /* Pad to power of two vector */
980 while (count < util_next_power_of_two(count))
981 param[count++] = LLVMGetUndef(ctx->i32);
982
983 if (count > 1)
984 args.addr = lp_build_gather_values(&ctx->gallivm, param, count);
985 else
986 args.addr = param[0];
987
988 args.resource = res_ptr;
989 args.sampler = samp_ptr;
990 args.dmask = dmask;
991 args.unorm = target == TGSI_TEXTURE_RECT ||
992 target == TGSI_TEXTURE_SHADOWRECT;
993 args.da = tgsi_is_array_sampler(target);
994
995 /* Ugly, but we seem to have no other choice right now. */
996 STATIC_ASSERT(sizeof(args) <= sizeof(emit_data->args));
997 memcpy(emit_data->args, &args, sizeof(args));
998 }
999
1000 static LLVMValueRef fix_resinfo(struct si_shader_context *ctx,
1001 unsigned target, LLVMValueRef out)
1002 {
1003 LLVMBuilderRef builder = ctx->ac.builder;
1004
1005 /* 1D textures are allocated and used as 2D on GFX9. */
1006 if (ctx->screen->info.chip_class >= GFX9 &&
1007 (target == TGSI_TEXTURE_1D_ARRAY ||
1008 target == TGSI_TEXTURE_SHADOW1D_ARRAY)) {
1009 LLVMValueRef layers =
1010 LLVMBuildExtractElement(builder, out,
1011 LLVMConstInt(ctx->i32, 2, 0), "");
1012 out = LLVMBuildInsertElement(builder, out, layers,
1013 ctx->i32_1, "");
1014 }
1015
1016 /* Divide the number of layers by 6 to get the number of cubes. */
1017 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
1018 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
1019 LLVMValueRef imm2 = LLVMConstInt(ctx->i32, 2, 0);
1020
1021 LLVMValueRef z = LLVMBuildExtractElement(builder, out, imm2, "");
1022 z = LLVMBuildSDiv(builder, z, LLVMConstInt(ctx->i32, 6, 0), "");
1023
1024 out = LLVMBuildInsertElement(builder, out, z, imm2, "");
1025 }
1026 return out;
1027 }
1028
1029 static void resq_fetch_args(
1030 struct lp_build_tgsi_context * bld_base,
1031 struct lp_build_emit_data * emit_data)
1032 {
1033 struct si_shader_context *ctx = si_shader_context(bld_base);
1034 const struct tgsi_full_instruction *inst = emit_data->inst;
1035 const struct tgsi_full_src_register *reg = &inst->Src[0];
1036
1037 emit_data->dst_type = ctx->v4i32;
1038
1039 if (reg->Register.File == TGSI_FILE_BUFFER) {
1040 emit_data->args[0] = shader_buffer_fetch_rsrc(ctx, reg, false);
1041 emit_data->arg_count = 1;
1042 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
1043 image_fetch_rsrc(bld_base, reg, false, inst->Memory.Texture,
1044 &emit_data->args[0]);
1045 emit_data->arg_count = 1;
1046 } else {
1047 LLVMValueRef res_ptr;
1048 unsigned image_target;
1049
1050 if (inst->Memory.Texture == TGSI_TEXTURE_3D)
1051 image_target = TGSI_TEXTURE_2D_ARRAY;
1052 else
1053 image_target = inst->Memory.Texture;
1054
1055 image_fetch_rsrc(bld_base, reg, false, inst->Memory.Texture,
1056 &res_ptr);
1057 set_tex_fetch_args(ctx, emit_data, image_target,
1058 res_ptr, NULL, &ctx->i32_0, 1,
1059 0xf);
1060 }
1061 }
1062
1063 static void resq_emit(
1064 const struct lp_build_tgsi_action *action,
1065 struct lp_build_tgsi_context *bld_base,
1066 struct lp_build_emit_data *emit_data)
1067 {
1068 struct si_shader_context *ctx = si_shader_context(bld_base);
1069 LLVMBuilderRef builder = ctx->ac.builder;
1070 const struct tgsi_full_instruction *inst = emit_data->inst;
1071 LLVMValueRef out;
1072
1073 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
1074 out = LLVMBuildExtractElement(builder, emit_data->args[0],
1075 LLVMConstInt(ctx->i32, 2, 0), "");
1076 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
1077 out = get_buffer_size(bld_base, emit_data->args[0]);
1078 } else {
1079 struct ac_image_args args;
1080
1081 memcpy(&args, emit_data->args, sizeof(args)); /* ugly */
1082 args.opcode = ac_image_get_resinfo;
1083 out = ac_build_image_opcode(&ctx->ac, &args);
1084
1085 out = fix_resinfo(ctx, inst->Memory.Texture, out);
1086 }
1087
1088 emit_data->output[emit_data->chan] = out;
1089 }
1090
1091 /**
1092 * Load an image view, fmask view. or sampler state descriptor.
1093 */
1094 LLVMValueRef si_load_sampler_desc(struct si_shader_context *ctx,
1095 LLVMValueRef list, LLVMValueRef index,
1096 enum ac_descriptor_type type)
1097 {
1098 LLVMBuilderRef builder = ctx->ac.builder;
1099
1100 switch (type) {
1101 case AC_DESC_IMAGE:
1102 /* The image is at [0:7]. */
1103 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
1104 break;
1105 case AC_DESC_BUFFER:
1106 /* The buffer is in [4:7]. */
1107 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 4, 0), "");
1108 index = LLVMBuildAdd(builder, index, ctx->i32_1, "");
1109 list = LLVMBuildPointerCast(builder, list,
1110 ac_array_in_const32_addr_space(ctx->v4i32), "");
1111 break;
1112 case AC_DESC_FMASK:
1113 /* The FMASK is at [8:15]. */
1114 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
1115 index = LLVMBuildAdd(builder, index, ctx->i32_1, "");
1116 break;
1117 case AC_DESC_SAMPLER:
1118 /* The sampler state is at [12:15]. */
1119 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 4, 0), "");
1120 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 3, 0), "");
1121 list = LLVMBuildPointerCast(builder, list,
1122 ac_array_in_const32_addr_space(ctx->v4i32), "");
1123 break;
1124 }
1125
1126 return ac_build_load_to_sgpr(&ctx->ac, list, index);
1127 }
1128
1129 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
1130 *
1131 * SI-CI:
1132 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
1133 * filtering manually. The driver sets img7 to a mask clearing
1134 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
1135 * s_and_b32 samp0, samp0, img7
1136 *
1137 * VI:
1138 * The ANISO_OVERRIDE sampler field enables this fix in TA.
1139 */
1140 static LLVMValueRef sici_fix_sampler_aniso(struct si_shader_context *ctx,
1141 LLVMValueRef res, LLVMValueRef samp)
1142 {
1143 LLVMValueRef img7, samp0;
1144
1145 if (ctx->screen->info.chip_class >= VI)
1146 return samp;
1147
1148 img7 = LLVMBuildExtractElement(ctx->ac.builder, res,
1149 LLVMConstInt(ctx->i32, 7, 0), "");
1150 samp0 = LLVMBuildExtractElement(ctx->ac.builder, samp,
1151 ctx->i32_0, "");
1152 samp0 = LLVMBuildAnd(ctx->ac.builder, samp0, img7, "");
1153 return LLVMBuildInsertElement(ctx->ac.builder, samp, samp0,
1154 ctx->i32_0, "");
1155 }
1156
1157 static void tex_fetch_ptrs(
1158 struct lp_build_tgsi_context *bld_base,
1159 struct lp_build_emit_data *emit_data,
1160 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr, LLVMValueRef *fmask_ptr)
1161 {
1162 struct si_shader_context *ctx = si_shader_context(bld_base);
1163 LLVMValueRef list = LLVMGetParam(ctx->main_fn, ctx->param_samplers_and_images);
1164 const struct tgsi_full_instruction *inst = emit_data->inst;
1165 const struct tgsi_full_src_register *reg;
1166 unsigned target = inst->Texture.Texture;
1167 unsigned sampler_src;
1168 LLVMValueRef index;
1169
1170 sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
1171 reg = &emit_data->inst->Src[sampler_src];
1172
1173 if (reg->Register.Indirect) {
1174 index = si_get_bounded_indirect_index(ctx,
1175 &reg->Indirect,
1176 reg->Register.Index,
1177 ctx->num_samplers);
1178 index = LLVMBuildAdd(ctx->ac.builder, index,
1179 LLVMConstInt(ctx->i32, SI_NUM_IMAGES / 2, 0), "");
1180 } else {
1181 index = LLVMConstInt(ctx->i32,
1182 si_get_sampler_slot(reg->Register.Index), 0);
1183 }
1184
1185 if (reg->Register.File != TGSI_FILE_SAMPLER) {
1186 /* Bindless descriptors are accessible from a different pair of
1187 * user SGPR indices.
1188 */
1189 list = LLVMGetParam(ctx->main_fn,
1190 ctx->param_bindless_samplers_and_images);
1191 index = lp_build_emit_fetch_src(bld_base, reg,
1192 TGSI_TYPE_UNSIGNED, 0);
1193 }
1194
1195 if (target == TGSI_TEXTURE_BUFFER)
1196 *res_ptr = si_load_sampler_desc(ctx, list, index, AC_DESC_BUFFER);
1197 else
1198 *res_ptr = si_load_sampler_desc(ctx, list, index, AC_DESC_IMAGE);
1199
1200 if (samp_ptr)
1201 *samp_ptr = NULL;
1202 if (fmask_ptr)
1203 *fmask_ptr = NULL;
1204
1205 if (target == TGSI_TEXTURE_2D_MSAA ||
1206 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
1207 if (fmask_ptr)
1208 *fmask_ptr = si_load_sampler_desc(ctx, list, index,
1209 AC_DESC_FMASK);
1210 } else if (target != TGSI_TEXTURE_BUFFER) {
1211 if (samp_ptr) {
1212 *samp_ptr = si_load_sampler_desc(ctx, list, index,
1213 AC_DESC_SAMPLER);
1214 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
1215 }
1216 }
1217 }
1218
1219 static void txq_fetch_args(
1220 struct lp_build_tgsi_context *bld_base,
1221 struct lp_build_emit_data *emit_data)
1222 {
1223 struct si_shader_context *ctx = si_shader_context(bld_base);
1224 const struct tgsi_full_instruction *inst = emit_data->inst;
1225 unsigned target = inst->Texture.Texture;
1226 LLVMValueRef res_ptr;
1227 LLVMValueRef address;
1228
1229 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, NULL, NULL);
1230
1231 if (target == TGSI_TEXTURE_BUFFER) {
1232 /* Read the size from the buffer descriptor directly. */
1233 emit_data->args[0] = get_buffer_size(bld_base, res_ptr);
1234 return;
1235 }
1236
1237 /* Textures - set the mip level. */
1238 address = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
1239
1240 set_tex_fetch_args(ctx, emit_data, target, res_ptr,
1241 NULL, &address, 1, 0xf);
1242 }
1243
1244 static void txq_emit(const struct lp_build_tgsi_action *action,
1245 struct lp_build_tgsi_context *bld_base,
1246 struct lp_build_emit_data *emit_data)
1247 {
1248 struct si_shader_context *ctx = si_shader_context(bld_base);
1249 struct ac_image_args args;
1250 unsigned target = emit_data->inst->Texture.Texture;
1251
1252 if (target == TGSI_TEXTURE_BUFFER) {
1253 /* Just return the buffer size. */
1254 emit_data->output[emit_data->chan] = emit_data->args[0];
1255 return;
1256 }
1257
1258 memcpy(&args, emit_data->args, sizeof(args)); /* ugly */
1259
1260 args.opcode = ac_image_get_resinfo;
1261 LLVMValueRef result = ac_build_image_opcode(&ctx->ac, &args);
1262
1263 emit_data->output[emit_data->chan] = fix_resinfo(ctx, target, result);
1264 }
1265
1266 static void tex_fetch_args(
1267 struct lp_build_tgsi_context *bld_base,
1268 struct lp_build_emit_data *emit_data)
1269 {
1270 struct si_shader_context *ctx = si_shader_context(bld_base);
1271 const struct tgsi_full_instruction *inst = emit_data->inst;
1272 unsigned opcode = inst->Instruction.Opcode;
1273 unsigned target = inst->Texture.Texture;
1274 LLVMValueRef coords[5], derivs[6];
1275 LLVMValueRef address[16];
1276 unsigned num_coords = tgsi_util_get_texture_coord_dim(target);
1277 int ref_pos = tgsi_util_get_shadow_ref_src_index(target);
1278 unsigned count = 0;
1279 unsigned chan;
1280 unsigned num_deriv_channels = 0;
1281 bool has_offset = inst->Texture.NumOffsets > 0;
1282 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
1283 unsigned dmask = 0xf;
1284
1285 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
1286
1287 if (target == TGSI_TEXTURE_BUFFER) {
1288 emit_data->dst_type = ctx->v4f32;
1289 emit_data->args[0] = res_ptr;
1290 emit_data->args[1] = ctx->i32_0;
1291 emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
1292 emit_data->arg_count = 3;
1293 return;
1294 }
1295
1296 /* Fetch and project texture coordinates */
1297 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
1298 for (chan = 0; chan < 3; chan++) {
1299 coords[chan] = lp_build_emit_fetch(bld_base,
1300 emit_data->inst, 0,
1301 chan);
1302 if (opcode == TGSI_OPCODE_TXP)
1303 coords[chan] = lp_build_emit_llvm_binary(bld_base,
1304 TGSI_OPCODE_DIV,
1305 coords[chan],
1306 coords[3]);
1307 }
1308
1309 if (opcode == TGSI_OPCODE_TXP)
1310 coords[3] = ctx->ac.f32_1;
1311
1312 /* Pack offsets. */
1313 if (has_offset &&
1314 opcode != TGSI_OPCODE_TXF &&
1315 opcode != TGSI_OPCODE_TXF_LZ) {
1316 /* The offsets are six-bit signed integers packed like this:
1317 * X=[5:0], Y=[13:8], and Z=[21:16].
1318 */
1319 LLVMValueRef offset[3], pack;
1320
1321 assert(inst->Texture.NumOffsets == 1);
1322
1323 for (chan = 0; chan < 3; chan++) {
1324 offset[chan] = lp_build_emit_fetch_texoffset(bld_base,
1325 emit_data->inst, 0, chan);
1326 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
1327 LLVMConstInt(ctx->i32, 0x3f, 0), "");
1328 if (chan)
1329 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
1330 LLVMConstInt(ctx->i32, chan*8, 0), "");
1331 }
1332
1333 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
1334 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
1335 address[count++] = pack;
1336 }
1337
1338 /* Pack LOD bias value */
1339 if (opcode == TGSI_OPCODE_TXB)
1340 address[count++] = coords[3];
1341 if (opcode == TGSI_OPCODE_TXB2)
1342 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
1343
1344 /* Pack depth comparison value */
1345 if (tgsi_is_shadow_target(target) && opcode != TGSI_OPCODE_LODQ) {
1346 LLVMValueRef z;
1347
1348 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
1349 z = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
1350 } else {
1351 assert(ref_pos >= 0);
1352 z = coords[ref_pos];
1353 }
1354
1355 /* Section 8.23.1 (Depth Texture Comparison Mode) of the
1356 * OpenGL 4.5 spec says:
1357 *
1358 * "If the texture’s internal format indicates a fixed-point
1359 * depth texture, then D_t and D_ref are clamped to the
1360 * range [0, 1]; otherwise no clamping is performed."
1361 *
1362 * TC-compatible HTILE promotes Z16 and Z24 to Z32_FLOAT,
1363 * so the depth comparison value isn't clamped for Z16 and
1364 * Z24 anymore. Do it manually here.
1365 */
1366 if (ctx->screen->info.chip_class >= VI) {
1367 LLVMValueRef upgraded;
1368 LLVMValueRef clamped;
1369 upgraded = LLVMBuildExtractElement(ctx->ac.builder, samp_ptr,
1370 LLVMConstInt(ctx->i32, 3, false), "");
1371 upgraded = LLVMBuildLShr(ctx->ac.builder, upgraded,
1372 LLVMConstInt(ctx->i32, 29, false), "");
1373 upgraded = LLVMBuildTrunc(ctx->ac.builder, upgraded, ctx->i1, "");
1374 clamped = ac_build_clamp(&ctx->ac, z);
1375 z = LLVMBuildSelect(ctx->ac.builder, upgraded, clamped, z, "");
1376 }
1377
1378 address[count++] = z;
1379 }
1380
1381 /* Pack user derivatives */
1382 if (opcode == TGSI_OPCODE_TXD) {
1383 int param, num_src_deriv_channels, num_dst_deriv_channels;
1384
1385 switch (target) {
1386 case TGSI_TEXTURE_3D:
1387 num_src_deriv_channels = 3;
1388 num_dst_deriv_channels = 3;
1389 num_deriv_channels = 3;
1390 break;
1391 case TGSI_TEXTURE_2D:
1392 case TGSI_TEXTURE_SHADOW2D:
1393 case TGSI_TEXTURE_RECT:
1394 case TGSI_TEXTURE_SHADOWRECT:
1395 case TGSI_TEXTURE_2D_ARRAY:
1396 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1397 num_src_deriv_channels = 2;
1398 num_dst_deriv_channels = 2;
1399 num_deriv_channels = 2;
1400 break;
1401 case TGSI_TEXTURE_CUBE:
1402 case TGSI_TEXTURE_SHADOWCUBE:
1403 case TGSI_TEXTURE_CUBE_ARRAY:
1404 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
1405 /* Cube derivatives will be converted to 2D. */
1406 num_src_deriv_channels = 3;
1407 num_dst_deriv_channels = 3;
1408 num_deriv_channels = 2;
1409 break;
1410 case TGSI_TEXTURE_1D:
1411 case TGSI_TEXTURE_SHADOW1D:
1412 case TGSI_TEXTURE_1D_ARRAY:
1413 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1414 num_src_deriv_channels = 1;
1415
1416 /* 1D textures are allocated and used as 2D on GFX9. */
1417 if (ctx->screen->info.chip_class >= GFX9) {
1418 num_dst_deriv_channels = 2;
1419 num_deriv_channels = 2;
1420 } else {
1421 num_dst_deriv_channels = 1;
1422 num_deriv_channels = 1;
1423 }
1424 break;
1425 default:
1426 unreachable("invalid target");
1427 }
1428
1429 for (param = 0; param < 2; param++) {
1430 for (chan = 0; chan < num_src_deriv_channels; chan++)
1431 derivs[param * num_dst_deriv_channels + chan] =
1432 lp_build_emit_fetch(bld_base, inst, param+1, chan);
1433
1434 /* Fill in the rest with zeros. */
1435 for (chan = num_src_deriv_channels;
1436 chan < num_dst_deriv_channels; chan++)
1437 derivs[param * num_dst_deriv_channels + chan] =
1438 ctx->ac.f32_0;
1439 }
1440 }
1441
1442 if (target == TGSI_TEXTURE_CUBE ||
1443 target == TGSI_TEXTURE_CUBE_ARRAY ||
1444 target == TGSI_TEXTURE_SHADOWCUBE ||
1445 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
1446 ac_prepare_cube_coords(&ctx->ac,
1447 opcode == TGSI_OPCODE_TXD,
1448 target == TGSI_TEXTURE_CUBE_ARRAY ||
1449 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY,
1450 opcode == TGSI_OPCODE_LODQ,
1451 coords, derivs);
1452 } else if (tgsi_is_array_sampler(target) &&
1453 opcode != TGSI_OPCODE_TXF &&
1454 opcode != TGSI_OPCODE_TXF_LZ &&
1455 ctx->screen->info.chip_class <= VI) {
1456 unsigned array_coord = target == TGSI_TEXTURE_1D_ARRAY ? 1 : 2;
1457 coords[array_coord] =
1458 ac_build_intrinsic(&ctx->ac, "llvm.rint.f32", ctx->f32,
1459 &coords[array_coord], 1, 0);
1460 }
1461
1462 if (opcode == TGSI_OPCODE_TXD)
1463 for (int i = 0; i < num_deriv_channels * 2; i++)
1464 address[count++] = derivs[i];
1465
1466 /* Pack texture coordinates */
1467 address[count++] = coords[0];
1468 if (num_coords > 1)
1469 address[count++] = coords[1];
1470 if (num_coords > 2)
1471 address[count++] = coords[2];
1472
1473 /* 1D textures are allocated and used as 2D on GFX9. */
1474 if (ctx->screen->info.chip_class >= GFX9) {
1475 LLVMValueRef filler;
1476
1477 /* Use 0.5, so that we don't sample the border color. */
1478 if (opcode == TGSI_OPCODE_TXF ||
1479 opcode == TGSI_OPCODE_TXF_LZ)
1480 filler = ctx->i32_0;
1481 else
1482 filler = LLVMConstReal(ctx->f32, 0.5);
1483
1484 if (target == TGSI_TEXTURE_1D ||
1485 target == TGSI_TEXTURE_SHADOW1D) {
1486 address[count++] = filler;
1487 } else if (target == TGSI_TEXTURE_1D_ARRAY ||
1488 target == TGSI_TEXTURE_SHADOW1D_ARRAY) {
1489 address[count] = address[count - 1];
1490 address[count - 1] = filler;
1491 count++;
1492 }
1493 }
1494
1495 /* Pack LOD or sample index */
1496 if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
1497 address[count++] = coords[3];
1498 else if (opcode == TGSI_OPCODE_TXL2)
1499 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
1500
1501 if (count > 16) {
1502 assert(!"Cannot handle more than 16 texture address parameters");
1503 count = 16;
1504 }
1505
1506 for (chan = 0; chan < count; chan++)
1507 address[chan] = ac_to_integer(&ctx->ac, address[chan]);
1508
1509 if (target == TGSI_TEXTURE_2D_MSAA ||
1510 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
1511 ac_apply_fmask_to_sample(&ctx->ac, fmask_ptr, address,
1512 target == TGSI_TEXTURE_2D_ARRAY_MSAA);
1513 }
1514
1515 if (opcode == TGSI_OPCODE_TXF ||
1516 opcode == TGSI_OPCODE_TXF_LZ) {
1517 /* add tex offsets */
1518 if (inst->Texture.NumOffsets) {
1519 struct lp_build_context *uint_bld = &bld_base->uint_bld;
1520 const struct tgsi_texture_offset *off = inst->TexOffsets;
1521
1522 assert(inst->Texture.NumOffsets == 1);
1523
1524 switch (target) {
1525 case TGSI_TEXTURE_3D:
1526 address[2] = lp_build_add(uint_bld, address[2],
1527 ctx->imms[off->Index * TGSI_NUM_CHANNELS + off->SwizzleZ]);
1528 /* fall through */
1529 case TGSI_TEXTURE_2D:
1530 case TGSI_TEXTURE_SHADOW2D:
1531 case TGSI_TEXTURE_RECT:
1532 case TGSI_TEXTURE_SHADOWRECT:
1533 case TGSI_TEXTURE_2D_ARRAY:
1534 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1535 address[1] =
1536 lp_build_add(uint_bld, address[1],
1537 ctx->imms[off->Index * TGSI_NUM_CHANNELS + off->SwizzleY]);
1538 /* fall through */
1539 case TGSI_TEXTURE_1D:
1540 case TGSI_TEXTURE_SHADOW1D:
1541 case TGSI_TEXTURE_1D_ARRAY:
1542 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1543 address[0] =
1544 lp_build_add(uint_bld, address[0],
1545 ctx->imms[off->Index * TGSI_NUM_CHANNELS + off->SwizzleX]);
1546 break;
1547 /* texture offsets do not apply to other texture targets */
1548 }
1549 }
1550 }
1551
1552 if (opcode == TGSI_OPCODE_TG4) {
1553 unsigned gather_comp = 0;
1554
1555 /* DMASK was repurposed for GATHER4. 4 components are always
1556 * returned and DMASK works like a swizzle - it selects
1557 * the component to fetch. The only valid DMASK values are
1558 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
1559 * (red,red,red,red) etc.) The ISA document doesn't mention
1560 * this.
1561 */
1562
1563 /* Get the component index from src1.x for Gather4. */
1564 if (!tgsi_is_shadow_target(target)) {
1565 LLVMValueRef comp_imm;
1566 struct tgsi_src_register src1 = inst->Src[1].Register;
1567
1568 assert(src1.File == TGSI_FILE_IMMEDIATE);
1569
1570 comp_imm = ctx->imms[src1.Index * TGSI_NUM_CHANNELS + src1.SwizzleX];
1571 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
1572 gather_comp = CLAMP(gather_comp, 0, 3);
1573 }
1574
1575 dmask = 1 << gather_comp;
1576 }
1577
1578 set_tex_fetch_args(ctx, emit_data, target, res_ptr,
1579 samp_ptr, address, count, dmask);
1580 }
1581
1582 /* Gather4 should follow the same rules as bilinear filtering, but the hardware
1583 * incorrectly forces nearest filtering if the texture format is integer.
1584 * The only effect it has on Gather4, which always returns 4 texels for
1585 * bilinear filtering, is that the final coordinates are off by 0.5 of
1586 * the texel size.
1587 *
1588 * The workaround is to subtract 0.5 from the unnormalized coordinates,
1589 * or (0.5 / size) from the normalized coordinates.
1590 *
1591 * However, cube textures with 8_8_8_8 data formats require a different
1592 * workaround of overriding the num format to USCALED/SSCALED. This would lose
1593 * precision in 32-bit data formats, so it needs to be applied dynamically at
1594 * runtime. In this case, return an i1 value that indicates whether the
1595 * descriptor was overridden (and hence a fixup of the sampler result is needed).
1596 */
1597 static LLVMValueRef
1598 si_lower_gather4_integer(struct si_shader_context *ctx,
1599 struct ac_image_args *args,
1600 unsigned target,
1601 enum tgsi_return_type return_type)
1602 {
1603 LLVMBuilderRef builder = ctx->ac.builder;
1604 LLVMValueRef wa_8888 = NULL;
1605 LLVMValueRef coord = args->addr;
1606 LLVMValueRef half_texel[2];
1607 /* Texture coordinates start after:
1608 * {offset, bias, z-compare, derivatives}
1609 * Only the offset and z-compare can occur here.
1610 */
1611 unsigned coord_vgpr_index = (int)args->offset + (int)args->compare;
1612 int c;
1613
1614 assert(return_type == TGSI_RETURN_TYPE_SINT ||
1615 return_type == TGSI_RETURN_TYPE_UINT);
1616
1617 if (target == TGSI_TEXTURE_CUBE ||
1618 target == TGSI_TEXTURE_CUBE_ARRAY) {
1619 LLVMValueRef formats;
1620 LLVMValueRef data_format;
1621 LLVMValueRef wa_formats;
1622
1623 formats = LLVMBuildExtractElement(builder, args->resource, ctx->i32_1, "");
1624
1625 data_format = LLVMBuildLShr(builder, formats,
1626 LLVMConstInt(ctx->i32, 20, false), "");
1627 data_format = LLVMBuildAnd(builder, data_format,
1628 LLVMConstInt(ctx->i32, (1u << 6) - 1, false), "");
1629 wa_8888 = LLVMBuildICmp(
1630 builder, LLVMIntEQ, data_format,
1631 LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false),
1632 "");
1633
1634 uint32_t wa_num_format =
1635 return_type == TGSI_RETURN_TYPE_UINT ?
1636 S_008F14_NUM_FORMAT_GFX6(V_008F14_IMG_NUM_FORMAT_USCALED) :
1637 S_008F14_NUM_FORMAT_GFX6(V_008F14_IMG_NUM_FORMAT_SSCALED);
1638 wa_formats = LLVMBuildAnd(builder, formats,
1639 LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false),
1640 "");
1641 wa_formats = LLVMBuildOr(builder, wa_formats,
1642 LLVMConstInt(ctx->i32, wa_num_format, false), "");
1643
1644 formats = LLVMBuildSelect(builder, wa_8888, wa_formats, formats, "");
1645 args->resource = LLVMBuildInsertElement(
1646 builder, args->resource, formats, ctx->i32_1, "");
1647 }
1648
1649 if (target == TGSI_TEXTURE_RECT ||
1650 target == TGSI_TEXTURE_SHADOWRECT) {
1651 assert(!wa_8888);
1652 half_texel[0] = half_texel[1] = LLVMConstReal(ctx->f32, -0.5);
1653 } else {
1654 struct tgsi_full_instruction txq_inst = {};
1655 struct lp_build_emit_data txq_emit_data = {};
1656 struct lp_build_if_state if_ctx;
1657
1658 if (wa_8888) {
1659 /* Skip the texture size query entirely if we don't need it. */
1660 lp_build_if(&if_ctx, &ctx->gallivm, LLVMBuildNot(builder, wa_8888, ""));
1661 }
1662
1663 /* Query the texture size. */
1664 txq_inst.Texture.Texture = target;
1665 txq_emit_data.inst = &txq_inst;
1666 txq_emit_data.dst_type = ctx->v4i32;
1667 set_tex_fetch_args(ctx, &txq_emit_data, target,
1668 args->resource, NULL, &ctx->i32_0,
1669 1, 0xf);
1670 txq_emit(NULL, &ctx->bld_base, &txq_emit_data);
1671
1672 /* Compute -0.5 / size. */
1673 for (c = 0; c < 2; c++) {
1674 half_texel[c] =
1675 LLVMBuildExtractElement(builder, txq_emit_data.output[0],
1676 LLVMConstInt(ctx->i32, c, 0), "");
1677 half_texel[c] = LLVMBuildUIToFP(builder, half_texel[c], ctx->f32, "");
1678 half_texel[c] =
1679 lp_build_emit_llvm_unary(&ctx->bld_base,
1680 TGSI_OPCODE_RCP, half_texel[c]);
1681 half_texel[c] = LLVMBuildFMul(builder, half_texel[c],
1682 LLVMConstReal(ctx->f32, -0.5), "");
1683 }
1684
1685 if (wa_8888) {
1686 lp_build_endif(&if_ctx);
1687
1688 LLVMBasicBlockRef bb[2] = { if_ctx.true_block, if_ctx.entry_block };
1689
1690 for (c = 0; c < 2; c++) {
1691 LLVMValueRef values[2] = { half_texel[c], ctx->ac.f32_0 };
1692 half_texel[c] = ac_build_phi(&ctx->ac, ctx->f32, 2,
1693 values, bb);
1694 }
1695 }
1696 }
1697
1698 for (c = 0; c < 2; c++) {
1699 LLVMValueRef tmp;
1700 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
1701
1702 tmp = LLVMBuildExtractElement(builder, coord, index, "");
1703 tmp = ac_to_float(&ctx->ac, tmp);
1704 tmp = LLVMBuildFAdd(builder, tmp, half_texel[c], "");
1705 tmp = ac_to_integer(&ctx->ac, tmp);
1706 coord = LLVMBuildInsertElement(builder, coord, tmp, index, "");
1707 }
1708
1709 args->addr = coord;
1710
1711 return wa_8888;
1712 }
1713
1714 /* The second half of the cube texture 8_8_8_8 integer workaround: adjust the
1715 * result after the gather operation.
1716 */
1717 static LLVMValueRef
1718 si_fix_gather4_integer_result(struct si_shader_context *ctx,
1719 LLVMValueRef result,
1720 enum tgsi_return_type return_type,
1721 LLVMValueRef wa)
1722 {
1723 LLVMBuilderRef builder = ctx->ac.builder;
1724
1725 assert(return_type == TGSI_RETURN_TYPE_SINT ||
1726 return_type == TGSI_RETURN_TYPE_UINT);
1727
1728 for (unsigned chan = 0; chan < 4; ++chan) {
1729 LLVMValueRef chanv = LLVMConstInt(ctx->i32, chan, false);
1730 LLVMValueRef value;
1731 LLVMValueRef wa_value;
1732
1733 value = LLVMBuildExtractElement(builder, result, chanv, "");
1734
1735 if (return_type == TGSI_RETURN_TYPE_UINT)
1736 wa_value = LLVMBuildFPToUI(builder, value, ctx->i32, "");
1737 else
1738 wa_value = LLVMBuildFPToSI(builder, value, ctx->i32, "");
1739 wa_value = ac_to_float(&ctx->ac, wa_value);
1740 value = LLVMBuildSelect(builder, wa, wa_value, value, "");
1741
1742 result = LLVMBuildInsertElement(builder, result, value, chanv, "");
1743 }
1744
1745 return result;
1746 }
1747
1748 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
1749 struct lp_build_tgsi_context *bld_base,
1750 struct lp_build_emit_data *emit_data)
1751 {
1752 struct si_shader_context *ctx = si_shader_context(bld_base);
1753 const struct tgsi_full_instruction *inst = emit_data->inst;
1754 struct ac_image_args args;
1755 unsigned opcode = inst->Instruction.Opcode;
1756 unsigned target = inst->Texture.Texture;
1757
1758 if (target == TGSI_TEXTURE_BUFFER) {
1759 unsigned num_channels =
1760 util_last_bit(inst->Dst[0].Register.WriteMask);
1761 LLVMValueRef result =
1762 ac_build_buffer_load_format(&ctx->ac,
1763 emit_data->args[0],
1764 emit_data->args[2],
1765 emit_data->args[1],
1766 num_channels, false, true);
1767 emit_data->output[emit_data->chan] =
1768 ac_build_expand_to_vec4(&ctx->ac, result, num_channels);
1769 return;
1770 }
1771
1772 memcpy(&args, emit_data->args, sizeof(args)); /* ugly */
1773
1774 args.opcode = ac_image_sample;
1775 args.compare = tgsi_is_shadow_target(target);
1776 args.offset = inst->Texture.NumOffsets > 0;
1777
1778 switch (opcode) {
1779 case TGSI_OPCODE_TXF:
1780 case TGSI_OPCODE_TXF_LZ:
1781 args.opcode = opcode == TGSI_OPCODE_TXF_LZ ||
1782 target == TGSI_TEXTURE_2D_MSAA ||
1783 target == TGSI_TEXTURE_2D_ARRAY_MSAA ?
1784 ac_image_load : ac_image_load_mip;
1785 args.compare = false;
1786 args.offset = false;
1787 break;
1788 case TGSI_OPCODE_LODQ:
1789 args.opcode = ac_image_get_lod;
1790 args.compare = false;
1791 args.offset = false;
1792 break;
1793 case TGSI_OPCODE_TEX:
1794 case TGSI_OPCODE_TEX2:
1795 case TGSI_OPCODE_TXP:
1796 if (ctx->type != PIPE_SHADER_FRAGMENT)
1797 args.level_zero = true;
1798 break;
1799 case TGSI_OPCODE_TEX_LZ:
1800 args.level_zero = true;
1801 break;
1802 case TGSI_OPCODE_TXB:
1803 case TGSI_OPCODE_TXB2:
1804 assert(ctx->type == PIPE_SHADER_FRAGMENT);
1805 args.bias = true;
1806 break;
1807 case TGSI_OPCODE_TXL:
1808 case TGSI_OPCODE_TXL2:
1809 args.lod = true;
1810 break;
1811 case TGSI_OPCODE_TXD:
1812 args.deriv = true;
1813 break;
1814 case TGSI_OPCODE_TG4:
1815 args.opcode = ac_image_gather4;
1816 args.level_zero = true;
1817 break;
1818 default:
1819 assert(0);
1820 return;
1821 }
1822
1823 /* The hardware needs special lowering for Gather4 with integer formats. */
1824 LLVMValueRef gather4_int_result_workaround = NULL;
1825
1826 if (ctx->screen->info.chip_class <= VI &&
1827 opcode == TGSI_OPCODE_TG4) {
1828 assert(inst->Texture.ReturnType != TGSI_RETURN_TYPE_UNKNOWN);
1829
1830 if (inst->Texture.ReturnType == TGSI_RETURN_TYPE_SINT ||
1831 inst->Texture.ReturnType == TGSI_RETURN_TYPE_UINT) {
1832 gather4_int_result_workaround =
1833 si_lower_gather4_integer(ctx, &args, target,
1834 inst->Texture.ReturnType);
1835 }
1836 }
1837
1838 LLVMValueRef result =
1839 ac_build_image_opcode(&ctx->ac, &args);
1840
1841 if (gather4_int_result_workaround) {
1842 result = si_fix_gather4_integer_result(ctx, result,
1843 inst->Texture.ReturnType,
1844 gather4_int_result_workaround);
1845 }
1846
1847 emit_data->output[emit_data->chan] = result;
1848 }
1849
1850 static void si_llvm_emit_txqs(
1851 const struct lp_build_tgsi_action *action,
1852 struct lp_build_tgsi_context *bld_base,
1853 struct lp_build_emit_data *emit_data)
1854 {
1855 struct si_shader_context *ctx = si_shader_context(bld_base);
1856 LLVMValueRef res, samples;
1857 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
1858
1859 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
1860
1861
1862 /* Read the samples from the descriptor directly. */
1863 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->v8i32, "");
1864 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
1865 LLVMConstInt(ctx->i32, 3, 0), "");
1866 samples = LLVMBuildLShr(ctx->ac.builder, samples,
1867 LLVMConstInt(ctx->i32, 16, 0), "");
1868 samples = LLVMBuildAnd(ctx->ac.builder, samples,
1869 LLVMConstInt(ctx->i32, 0xf, 0), "");
1870 samples = LLVMBuildShl(ctx->ac.builder, ctx->i32_1,
1871 samples, "");
1872
1873 emit_data->output[emit_data->chan] = samples;
1874 }
1875
1876 static const struct lp_build_tgsi_action tex_action = {
1877 .fetch_args = tex_fetch_args,
1878 .emit = build_tex_intrinsic,
1879 };
1880
1881 /**
1882 * Setup actions for TGSI memory opcode, including texture opcodes.
1883 */
1884 void si_shader_context_init_mem(struct si_shader_context *ctx)
1885 {
1886 struct lp_build_tgsi_context *bld_base;
1887 struct lp_build_tgsi_action tmpl = {};
1888
1889 bld_base = &ctx->bld_base;
1890
1891 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
1892 bld_base->op_actions[TGSI_OPCODE_TEX_LZ] = tex_action;
1893 bld_base->op_actions[TGSI_OPCODE_TEX2] = tex_action;
1894 bld_base->op_actions[TGSI_OPCODE_TXB] = tex_action;
1895 bld_base->op_actions[TGSI_OPCODE_TXB2] = tex_action;
1896 bld_base->op_actions[TGSI_OPCODE_TXD] = tex_action;
1897 bld_base->op_actions[TGSI_OPCODE_TXF] = tex_action;
1898 bld_base->op_actions[TGSI_OPCODE_TXF_LZ] = tex_action;
1899 bld_base->op_actions[TGSI_OPCODE_TXL] = tex_action;
1900 bld_base->op_actions[TGSI_OPCODE_TXL2] = tex_action;
1901 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
1902 bld_base->op_actions[TGSI_OPCODE_TXQ].fetch_args = txq_fetch_args;
1903 bld_base->op_actions[TGSI_OPCODE_TXQ].emit = txq_emit;
1904 bld_base->op_actions[TGSI_OPCODE_TG4] = tex_action;
1905 bld_base->op_actions[TGSI_OPCODE_LODQ] = tex_action;
1906 bld_base->op_actions[TGSI_OPCODE_TXQS].emit = si_llvm_emit_txqs;
1907
1908 bld_base->op_actions[TGSI_OPCODE_LOAD].fetch_args = load_fetch_args;
1909 bld_base->op_actions[TGSI_OPCODE_LOAD].emit = load_emit;
1910 bld_base->op_actions[TGSI_OPCODE_STORE].fetch_args = store_fetch_args;
1911 bld_base->op_actions[TGSI_OPCODE_STORE].emit = store_emit;
1912 bld_base->op_actions[TGSI_OPCODE_RESQ].fetch_args = resq_fetch_args;
1913 bld_base->op_actions[TGSI_OPCODE_RESQ].emit = resq_emit;
1914
1915 tmpl.fetch_args = atomic_fetch_args;
1916 tmpl.emit = atomic_emit;
1917 bld_base->op_actions[TGSI_OPCODE_ATOMUADD] = tmpl;
1918 bld_base->op_actions[TGSI_OPCODE_ATOMUADD].intr_name = "add";
1919 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG] = tmpl;
1920 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG].intr_name = "swap";
1921 bld_base->op_actions[TGSI_OPCODE_ATOMCAS] = tmpl;
1922 bld_base->op_actions[TGSI_OPCODE_ATOMCAS].intr_name = "cmpswap";
1923 bld_base->op_actions[TGSI_OPCODE_ATOMAND] = tmpl;
1924 bld_base->op_actions[TGSI_OPCODE_ATOMAND].intr_name = "and";
1925 bld_base->op_actions[TGSI_OPCODE_ATOMOR] = tmpl;
1926 bld_base->op_actions[TGSI_OPCODE_ATOMOR].intr_name = "or";
1927 bld_base->op_actions[TGSI_OPCODE_ATOMXOR] = tmpl;
1928 bld_base->op_actions[TGSI_OPCODE_ATOMXOR].intr_name = "xor";
1929 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN] = tmpl;
1930 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN].intr_name = "umin";
1931 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX] = tmpl;
1932 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX].intr_name = "umax";
1933 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN] = tmpl;
1934 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN].intr_name = "smin";
1935 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX] = tmpl;
1936 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX].intr_name = "smax";
1937 }