src/gallium/drivers/radeonsi/si_shaderlib_tgsi.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #include "si_pipe.h"
  26 #include "tgsi/tgsi_text.h"
  27 #include "tgsi/tgsi_ureg.h"
  28
  29 void *si_get_blitter_vs(struct si_context *sctx, enum blitter_attrib_type type,
  30                         unsigned num_layers)
  31 {
  32         unsigned vs_blit_property;
  33         void **vs;
  34
  35         switch (type) {
  36         case UTIL_BLITTER_ATTRIB_NONE:
  37                 vs = num_layers > 1 ? &sctx->vs_blit_pos_layered :
  38                                       &sctx->vs_blit_pos;
  39                 vs_blit_property = SI_VS_BLIT_SGPRS_POS;
  40                 break;
  41         case UTIL_BLITTER_ATTRIB_COLOR:
  42                 vs = num_layers > 1 ? &sctx->vs_blit_color_layered :
  43                                       &sctx->vs_blit_color;
  44                 vs_blit_property = SI_VS_BLIT_SGPRS_POS_COLOR;
  45                 break;
  46         case UTIL_BLITTER_ATTRIB_TEXCOORD_XY:
  47         case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW:
  48                 assert(num_layers == 1);
  49                 vs = &sctx->vs_blit_texcoord;
  50                 vs_blit_property = SI_VS_BLIT_SGPRS_POS_TEXCOORD;
  51                 break;
  52         default:
  53                 assert(0);
  54                 return NULL;
  55         }
  56         if (*vs)
  57                 return *vs;
  58
  59         struct ureg_program *ureg = ureg_create(PIPE_SHADER_VERTEX);
  60         if (!ureg)
  61                 return NULL;
  62
  63         /* Tell the shader to load VS inputs from SGPRs: */
  64         ureg_property(ureg, TGSI_PROPERTY_VS_BLIT_SGPRS_AMD, vs_blit_property);
  65         ureg_property(ureg, TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION, true);
  66
  67         /* This is just a pass-through shader with 1-3 MOV instructions. */
  68         ureg_MOV(ureg,
  69                  ureg_DECL_output(ureg, TGSI_SEMANTIC_POSITION, 0),
  70                  ureg_DECL_vs_input(ureg, 0));
  71
  72         if (type != UTIL_BLITTER_ATTRIB_NONE) {
  73                 ureg_MOV(ureg,
  74                          ureg_DECL_output(ureg, TGSI_SEMANTIC_GENERIC, 0),
  75                          ureg_DECL_vs_input(ureg, 1));
  76         }
  77
  78         if (num_layers > 1) {
  79                 struct ureg_src instance_id =
  80                         ureg_DECL_system_value(ureg, TGSI_SEMANTIC_INSTANCEID, 0);
  81                 struct ureg_dst layer =
  82                         ureg_DECL_output(ureg, TGSI_SEMANTIC_LAYER, 0);
  83
  84                 ureg_MOV(ureg, ureg_writemask(layer, TGSI_WRITEMASK_X),
  85                          ureg_scalar(instance_id, TGSI_SWIZZLE_X));
  86         }
  87         ureg_END(ureg);
  88
  89         *vs = ureg_create_shader_and_destroy(ureg, &sctx->b);
  90         return *vs;
  91 }
  92
  93 /**
  94  * This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
  95  * VS passes its outputs to TES directly, so the fixed-function shader only
  96  * has to write TESSOUTER and TESSINNER.
  97  */
  98 void *si_create_fixed_func_tcs(struct si_context *sctx)
  99 {
 100         struct ureg_src outer, inner;
 101         struct ureg_dst tessouter, tessinner;
 102         struct ureg_program *ureg = ureg_create(PIPE_SHADER_TESS_CTRL);
 103
 104         if (!ureg)
 105                 return NULL;
 106
 107         outer = ureg_DECL_system_value(ureg,
 108                                        TGSI_SEMANTIC_TESS_DEFAULT_OUTER_LEVEL, 0);
 109         inner = ureg_DECL_system_value(ureg,
 110                                        TGSI_SEMANTIC_TESS_DEFAULT_INNER_LEVEL, 0);
 111
 112         tessouter = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSOUTER, 0);
 113         tessinner = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSINNER, 0);
 114
 115         ureg_MOV(ureg, tessouter, outer);
 116         ureg_MOV(ureg, tessinner, inner);
 117         ureg_END(ureg);
 118
 119         return ureg_create_shader_and_destroy(ureg, &sctx->b);
 120 }
 121
 122 /* Create a compute shader implementing clear_buffer or copy_buffer. */
 123 void *si_create_dma_compute_shader(struct pipe_context *ctx,
 124                                    unsigned num_dwords_per_thread,
 125                                    bool dst_stream_cache_policy, bool is_copy)
 126 {
 127         struct si_screen *sscreen = (struct si_screen *)ctx->screen;
 128         assert(util_is_power_of_two_nonzero(num_dwords_per_thread));
 129
 130         unsigned store_qualifier = TGSI_MEMORY_COHERENT | TGSI_MEMORY_RESTRICT;
 131         if (dst_stream_cache_policy)
 132                 store_qualifier |= TGSI_MEMORY_STREAM_CACHE_POLICY;
 133
 134         /* Don't cache loads, because there is no reuse. */
 135         unsigned load_qualifier = store_qualifier | TGSI_MEMORY_STREAM_CACHE_POLICY;
 136
 137         unsigned num_mem_ops = MAX2(1, num_dwords_per_thread / 4);
 138         unsigned *inst_dwords = alloca(num_mem_ops * sizeof(unsigned));
 139
 140         for (unsigned i = 0; i < num_mem_ops; i++) {
 141                 if (i*4 < num_dwords_per_thread)
 142                         inst_dwords[i] = MIN2(4, num_dwords_per_thread - i*4);
 143         }
 144
 145         struct ureg_program *ureg = ureg_create(PIPE_SHADER_COMPUTE);
 146         if (!ureg)
 147                 return NULL;
 148
 149         ureg_property(ureg, TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH, sscreen->compute_wave_size);
 150         ureg_property(ureg, TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT, 1);
 151         ureg_property(ureg, TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH, 1);
 152
 153         struct ureg_src value;
 154         if (!is_copy) {
 155                 ureg_property(ureg, TGSI_PROPERTY_CS_USER_DATA_COMPONENTS_AMD, inst_dwords[0]);
 156                 value = ureg_DECL_system_value(ureg, TGSI_SEMANTIC_CS_USER_DATA_AMD, 0);
 157         }
 158
 159         struct ureg_src tid = ureg_DECL_system_value(ureg, TGSI_SEMANTIC_THREAD_ID, 0);
 160         struct ureg_src blk = ureg_DECL_system_value(ureg, TGSI_SEMANTIC_BLOCK_ID, 0);
 161         struct ureg_dst store_addr = ureg_writemask(ureg_DECL_temporary(ureg), TGSI_WRITEMASK_X);
 162         struct ureg_dst load_addr = ureg_writemask(ureg_DECL_temporary(ureg), TGSI_WRITEMASK_X);
 163         struct ureg_dst dstbuf = ureg_dst(ureg_DECL_buffer(ureg, 0, false));
 164         struct ureg_src srcbuf;
 165         struct ureg_src *values = NULL;
 166
 167         if (is_copy) {
 168                 srcbuf = ureg_DECL_buffer(ureg, 1, false);
 169                 values = malloc(num_mem_ops * sizeof(struct ureg_src));
 170         }
 171
 172         /* If there are multiple stores, the first store writes into 0*wavesize+tid,
 173          * the 2nd store writes into 1*wavesize+tid, the 3rd store writes into 2*wavesize+tid, etc.
 174          */
 175         ureg_UMAD(ureg, store_addr, blk,
 176                   ureg_imm1u(ureg, sscreen->compute_wave_size * num_mem_ops), tid);
 177         /* Convert from a "store size unit" into bytes. */
 178         ureg_UMUL(ureg, store_addr, ureg_src(store_addr),
 179                   ureg_imm1u(ureg, 4 * inst_dwords[0]));
 180         ureg_MOV(ureg, load_addr, ureg_src(store_addr));
 181
 182         /* Distance between a load and a store for latency hiding. */
 183         unsigned load_store_distance = is_copy ? 8 : 0;
 184
 185         for (unsigned i = 0; i < num_mem_ops + load_store_distance; i++) {
 186                 int d = i - load_store_distance;
 187
 188                 if (is_copy && i < num_mem_ops) {
 189                         if (i) {
 190                                 ureg_UADD(ureg, load_addr, ureg_src(load_addr),
 191                                           ureg_imm1u(ureg, 4 * inst_dwords[i] *
 192                                                      sscreen->compute_wave_size));
 193                         }
 194
 195                         values[i] = ureg_src(ureg_DECL_temporary(ureg));
 196                         struct ureg_dst dst =
 197                                 ureg_writemask(ureg_dst(values[i]),
 198                                                u_bit_consecutive(0, inst_dwords[i]));
 199                         struct ureg_src srcs[] = {srcbuf, ureg_src(load_addr)};
 200                         ureg_memory_insn(ureg, TGSI_OPCODE_LOAD, &dst, 1, srcs, 2,
 201                                          load_qualifier, TGSI_TEXTURE_BUFFER, 0);
 202                 }
 203
 204                 if (d >= 0) {
 205                         if (d) {
 206                                 ureg_UADD(ureg, store_addr, ureg_src(store_addr),
 207                                           ureg_imm1u(ureg, 4 * inst_dwords[d] *
 208                                                      sscreen->compute_wave_size));
 209                         }
 210
 211                         struct ureg_dst dst =
 212                                 ureg_writemask(dstbuf, u_bit_consecutive(0, inst_dwords[d]));
 213                         struct ureg_src srcs[] =
 214                                 {ureg_src(store_addr), is_copy ? values[d] : value};
 215                         ureg_memory_insn(ureg, TGSI_OPCODE_STORE, &dst, 1, srcs, 2,
 216                                          store_qualifier, TGSI_TEXTURE_BUFFER, 0);
 217                 }
 218         }
 219         ureg_END(ureg);
 220
 221         struct pipe_compute_state state = {};
 222         state.ir_type = PIPE_SHADER_IR_TGSI;
 223         state.prog = ureg_get_tokens(ureg, NULL);
 224
 225         void *cs = ctx->create_compute_state(ctx, &state);
 226         ureg_destroy(ureg);
 227         ureg_free_tokens(state.prog);
 228
 229         free(values);
 230         return cs;
 231 }
 232
 233 /* Create a compute shader that copies DCC from one buffer to another
 234  * where each DCC buffer has a different layout.
 235  *
 236  * image[0]: offset remap table (pairs of <src_offset, dst_offset>),
 237  *           2 pairs are read
 238  * image[1]: DCC source buffer, typed r8_uint
 239  * image[2]: DCC destination buffer, typed r8_uint
 240  */
 241 void *si_create_dcc_retile_cs(struct pipe_context *ctx)
 242 {
 243         struct ureg_program *ureg = ureg_create(PIPE_SHADER_COMPUTE);
 244         if (!ureg)
 245                 return NULL;
 246
 247         ureg_property(ureg, TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH, 64);
 248         ureg_property(ureg, TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT, 1);
 249         ureg_property(ureg, TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH, 1);
 250
 251         /* Compute the global thread ID (in idx). */
 252         struct ureg_src tid = ureg_DECL_system_value(ureg, TGSI_SEMANTIC_THREAD_ID, 0);
 253         struct ureg_src blk = ureg_DECL_system_value(ureg, TGSI_SEMANTIC_BLOCK_ID, 0);
 254         struct ureg_dst idx = ureg_writemask(ureg_DECL_temporary(ureg),
 255                                              TGSI_WRITEMASK_X);
 256         ureg_UMAD(ureg, idx, blk, ureg_imm1u(ureg, 64), tid);
 257
 258         /* Load 2 pairs of offsets for DCC load & store. */
 259         struct ureg_src map = ureg_DECL_image(ureg, 0, TGSI_TEXTURE_BUFFER, 0, false, false);
 260         struct ureg_dst offsets = ureg_DECL_temporary(ureg);
 261         struct ureg_src map_load_args[] = {map, ureg_src(idx)};
 262
 263         ureg_memory_insn(ureg, TGSI_OPCODE_LOAD, &offsets, 1, map_load_args, 2,
 264                          TGSI_MEMORY_RESTRICT, TGSI_TEXTURE_BUFFER, 0);
 265
 266         struct ureg_src dcc_src = ureg_DECL_image(ureg, 1, TGSI_TEXTURE_BUFFER,
 267                                                   0, false, false);
 268         struct ureg_dst dcc_dst = ureg_dst(ureg_DECL_image(ureg, 2, TGSI_TEXTURE_BUFFER,
 269                                                            0, true, false));
 270         struct ureg_dst dcc_value[2];
 271
 272         /* Copy DCC values:
 273          *   dst[offsets.y] = src[offsets.x];
 274          *   dst[offsets.w] = src[offsets.z];
 275          */
 276         for (unsigned i = 0; i < 2; i++) {
 277                 dcc_value[i] = ureg_writemask(ureg_DECL_temporary(ureg), TGSI_WRITEMASK_X);
 278
 279                 struct ureg_src load_args[] =
 280                         {dcc_src, ureg_scalar(ureg_src(offsets), TGSI_SWIZZLE_X + i*2)};
 281                 ureg_memory_insn(ureg, TGSI_OPCODE_LOAD, &dcc_value[i], 1, load_args, 2,
 282                                  TGSI_MEMORY_RESTRICT, TGSI_TEXTURE_BUFFER, 0);
 283         }
 284
 285         dcc_dst = ureg_writemask(dcc_dst, TGSI_WRITEMASK_X);
 286
 287         for (unsigned i = 0; i < 2; i++) {
 288                 struct ureg_src store_args[] = {
 289                         ureg_scalar(ureg_src(offsets), TGSI_SWIZZLE_Y + i*2),
 290                         ureg_src(dcc_value[i])
 291                 };
 292                 ureg_memory_insn(ureg, TGSI_OPCODE_STORE, &dcc_dst, 1, store_args, 2,
 293                                  TGSI_MEMORY_RESTRICT, TGSI_TEXTURE_BUFFER, 0);
 294         }
 295         ureg_END(ureg);
 296
 297         struct pipe_compute_state state = {};
 298         state.ir_type = PIPE_SHADER_IR_TGSI;
 299         state.prog = ureg_get_tokens(ureg, NULL);
 300
 301         void *cs = ctx->create_compute_state(ctx, &state);
 302         ureg_destroy(ureg);
 303         return cs;
 304 }
 305
 306 /* Create the compute shader that is used to collect the results.
 307  *
 308  * One compute grid with a single thread is launched for every query result
 309  * buffer. The thread (optionally) reads a previous summary buffer, then
 310  * accumulates data from the query result buffer, and writes the result either
 311  * to a summary buffer to be consumed by the next grid invocation or to the
 312  * user-supplied buffer.
 313  *
 314  * Data layout:
 315  *
 316  * CONST
 317  *  0.x = end_offset
 318  *  0.y = result_stride
 319  *  0.z = result_count
 320  *  0.w = bit field:
 321  *          1: read previously accumulated values
 322  *          2: write accumulated values for chaining
 323  *          4: write result available
 324  *          8: convert result to boolean (0/1)
 325  *         16: only read one dword and use that as result
 326  *         32: apply timestamp conversion
 327  *         64: store full 64 bits result
 328  *        128: store signed 32 bits result
 329  *        256: SO_OVERFLOW mode: take the difference of two successive half-pairs
 330  *  1.x = fence_offset
 331  *  1.y = pair_stride
 332  *  1.z = pair_count
 333  *
 334  * BUFFER[0] = query result buffer
 335  * BUFFER[1] = previous summary buffer
 336  * BUFFER[2] = next summary buffer or user-supplied buffer
 337  */
 338 void *si_create_query_result_cs(struct si_context *sctx)
 339 {
 340         /* TEMP[0].xy = accumulated result so far
 341          * TEMP[0].z = result not available
 342          *
 343          * TEMP[1].x = current result index
 344          * TEMP[1].y = current pair index
 345          */
 346         static const char text_tmpl[] =
 347                 "COMP\n"
 348                 "PROPERTY CS_FIXED_BLOCK_WIDTH 1\n"
 349                 "PROPERTY CS_FIXED_BLOCK_HEIGHT 1\n"
 350                 "PROPERTY CS_FIXED_BLOCK_DEPTH 1\n"
 351                 "DCL BUFFER[0]\n"
 352                 "DCL BUFFER[1]\n"
 353                 "DCL BUFFER[2]\n"
 354                 "DCL CONST[0][0..1]\n"
 355                 "DCL TEMP[0..5]\n"
 356                 "IMM[0] UINT32 {0, 31, 2147483647, 4294967295}\n"
 357                 "IMM[1] UINT32 {1, 2, 4, 8}\n"
 358                 "IMM[2] UINT32 {16, 32, 64, 128}\n"
 359                 "IMM[3] UINT32 {1000000, 0, %u, 0}\n" /* for timestamp conversion */
 360                 "IMM[4] UINT32 {256, 0, 0, 0}\n"
 361
 362                 "AND TEMP[5], CONST[0][0].wwww, IMM[2].xxxx\n"
 363                 "UIF TEMP[5]\n"
 364                         /* Check result availability. */
 365                         "LOAD TEMP[1].x, BUFFER[0], CONST[0][1].xxxx\n"
 366                         "ISHR TEMP[0].z, TEMP[1].xxxx, IMM[0].yyyy\n"
 367                         "MOV TEMP[1], TEMP[0].zzzz\n"
 368                         "NOT TEMP[0].z, TEMP[0].zzzz\n"
 369
 370                         /* Load result if available. */
 371                         "UIF TEMP[1]\n"
 372                                 "LOAD TEMP[0].xy, BUFFER[0], IMM[0].xxxx\n"
 373                         "ENDIF\n"
 374                 "ELSE\n"
 375                         /* Load previously accumulated result if requested. */
 376                         "MOV TEMP[0], IMM[0].xxxx\n"
 377                         "AND TEMP[4], CONST[0][0].wwww, IMM[1].xxxx\n"
 378                         "UIF TEMP[4]\n"
 379                                 "LOAD TEMP[0].xyz, BUFFER[1], IMM[0].xxxx\n"
 380                         "ENDIF\n"
 381
 382                         "MOV TEMP[1].x, IMM[0].xxxx\n"
 383                         "BGNLOOP\n"
 384                                 /* Break if accumulated result so far is not available. */
 385                                 "UIF TEMP[0].zzzz\n"
 386                                         "BRK\n"
 387                                 "ENDIF\n"
 388
 389                                 /* Break if result_index >= result_count. */
 390                                 "USGE TEMP[5], TEMP[1].xxxx, CONST[0][0].zzzz\n"
 391                                 "UIF TEMP[5]\n"
 392                                         "BRK\n"
 393                                 "ENDIF\n"
 394
 395                                 /* Load fence and check result availability */
 396                                 "UMAD TEMP[5].x, TEMP[1].xxxx, CONST[0][0].yyyy, CONST[0][1].xxxx\n"
 397                                 "LOAD TEMP[5].x, BUFFER[0], TEMP[5].xxxx\n"
 398                                 "ISHR TEMP[0].z, TEMP[5].xxxx, IMM[0].yyyy\n"
 399                                 "NOT TEMP[0].z, TEMP[0].zzzz\n"
 400                                 "UIF TEMP[0].zzzz\n"
 401                                         "BRK\n"
 402                                 "ENDIF\n"
 403
 404                                 "MOV TEMP[1].y, IMM[0].xxxx\n"
 405                                 "BGNLOOP\n"
 406                                         /* Load start and end. */
 407                                         "UMUL TEMP[5].x, TEMP[1].xxxx, CONST[0][0].yyyy\n"
 408                                         "UMAD TEMP[5].x, TEMP[1].yyyy, CONST[0][1].yyyy, TEMP[5].xxxx\n"
 409                                         "LOAD TEMP[2].xy, BUFFER[0], TEMP[5].xxxx\n"
 410
 411                                         "UADD TEMP[5].y, TEMP[5].xxxx, CONST[0][0].xxxx\n"
 412                                         "LOAD TEMP[3].xy, BUFFER[0], TEMP[5].yyyy\n"
 413
 414                                         "U64ADD TEMP[4].xy, TEMP[3], -TEMP[2]\n"
 415
 416                                         "AND TEMP[5].z, CONST[0][0].wwww, IMM[4].xxxx\n"
 417                                         "UIF TEMP[5].zzzz\n"
 418                                                 /* Load second start/end half-pair and
 419                                                  * take the difference
 420                                                  */
 421                                                 "UADD TEMP[5].xy, TEMP[5], IMM[1].wwww\n"
 422                                                 "LOAD TEMP[2].xy, BUFFER[0], TEMP[5].xxxx\n"
 423                                                 "LOAD TEMP[3].xy, BUFFER[0], TEMP[5].yyyy\n"
 424
 425                                                 "U64ADD TEMP[3].xy, TEMP[3], -TEMP[2]\n"
 426                                                 "U64ADD TEMP[4].xy, TEMP[4], -TEMP[3]\n"
 427                                         "ENDIF\n"
 428
 429                                         "U64ADD TEMP[0].xy, TEMP[0], TEMP[4]\n"
 430
 431                                         /* Increment pair index */
 432                                         "UADD TEMP[1].y, TEMP[1].yyyy, IMM[1].xxxx\n"
 433                                         "USGE TEMP[5], TEMP[1].yyyy, CONST[0][1].zzzz\n"
 434                                         "UIF TEMP[5]\n"
 435                                                 "BRK\n"
 436                                         "ENDIF\n"
 437                                 "ENDLOOP\n"
 438
 439                                 /* Increment result index */
 440                                 "UADD TEMP[1].x, TEMP[1].xxxx, IMM[1].xxxx\n"
 441                         "ENDLOOP\n"
 442                 "ENDIF\n"
 443
 444                 "AND TEMP[4], CONST[0][0].wwww, IMM[1].yyyy\n"
 445                 "UIF TEMP[4]\n"
 446                         /* Store accumulated data for chaining. */
 447                         "STORE BUFFER[2].xyz, IMM[0].xxxx, TEMP[0]\n"
 448                 "ELSE\n"
 449                         "AND TEMP[4], CONST[0][0].wwww, IMM[1].zzzz\n"
 450                         "UIF TEMP[4]\n"
 451                                 /* Store result availability. */
 452                                 "NOT TEMP[0].z, TEMP[0]\n"
 453                                 "AND TEMP[0].z, TEMP[0].zzzz, IMM[1].xxxx\n"
 454                                 "STORE BUFFER[2].x, IMM[0].xxxx, TEMP[0].zzzz\n"
 455
 456                                 "AND TEMP[4], CONST[0][0].wwww, IMM[2].zzzz\n"
 457                                 "UIF TEMP[4]\n"
 458                                         "STORE BUFFER[2].y, IMM[0].xxxx, IMM[0].xxxx\n"
 459                                 "ENDIF\n"
 460                         "ELSE\n"
 461                                 /* Store result if it is available. */
 462                                 "NOT TEMP[4], TEMP[0].zzzz\n"
 463                                 "UIF TEMP[4]\n"
 464                                         /* Apply timestamp conversion */
 465                                         "AND TEMP[4], CONST[0][0].wwww, IMM[2].yyyy\n"
 466                                         "UIF TEMP[4]\n"
 467                                                 "U64MUL TEMP[0].xy, TEMP[0], IMM[3].xyxy\n"
 468                                                 "U64DIV TEMP[0].xy, TEMP[0], IMM[3].zwzw\n"
 469                                         "ENDIF\n"
 470
 471                                         /* Convert to boolean */
 472                                         "AND TEMP[4], CONST[0][0].wwww, IMM[1].wwww\n"
 473                                         "UIF TEMP[4]\n"
 474                                                 "U64SNE TEMP[0].x, TEMP[0].xyxy, IMM[4].zwzw\n"
 475                                                 "AND TEMP[0].x, TEMP[0].xxxx, IMM[1].xxxx\n"
 476                                                 "MOV TEMP[0].y, IMM[0].xxxx\n"
 477                                         "ENDIF\n"
 478
 479                                         "AND TEMP[4], CONST[0][0].wwww, IMM[2].zzzz\n"
 480                                         "UIF TEMP[4]\n"
 481                                                 "STORE BUFFER[2].xy, IMM[0].xxxx, TEMP[0].xyxy\n"
 482                                         "ELSE\n"
 483                                                 /* Clamping */
 484                                                 "UIF TEMP[0].yyyy\n"
 485                                                         "MOV TEMP[0].x, IMM[0].wwww\n"
 486                                                 "ENDIF\n"
 487
 488                                                 "AND TEMP[4], CONST[0][0].wwww, IMM[2].wwww\n"
 489                                                 "UIF TEMP[4]\n"
 490                                                         "UMIN TEMP[0].x, TEMP[0].xxxx, IMM[0].zzzz\n"
 491                                                 "ENDIF\n"
 492
 493                                                 "STORE BUFFER[2].x, IMM[0].xxxx, TEMP[0].xxxx\n"
 494                                         "ENDIF\n"
 495                                 "ENDIF\n"
 496                         "ENDIF\n"
 497                 "ENDIF\n"
 498
 499                 "END\n";
 500
 501         char text[sizeof(text_tmpl) + 32];
 502         struct tgsi_token tokens[1024];
 503         struct pipe_compute_state state = {};
 504
 505         /* Hard code the frequency into the shader so that the backend can
 506          * use the full range of optimizations for divide-by-constant.
 507          */
 508         snprintf(text, sizeof(text), text_tmpl,
 509                  sctx->screen->info.clock_crystal_freq);
 510
 511         if (!tgsi_text_translate(text, tokens, ARRAY_SIZE(tokens))) {
 512                 assert(false);
 513                 return NULL;
 514         }
 515
 516         state.ir_type = PIPE_SHADER_IR_TGSI;
 517         state.prog = tokens;
 518
 519         return sctx->b.create_compute_state(&sctx->b, &state);
 520 }
 521
 522 /* Create a compute shader implementing copy_image.
 523  * Luckily, this works with all texture targets except 1D_ARRAY.
 524  */
 525 void *si_create_copy_image_compute_shader(struct pipe_context *ctx)
 526 {
 527         static const char text[] =
 528                 "COMP\n"
 529                 "PROPERTY CS_FIXED_BLOCK_WIDTH 8\n"
 530                 "PROPERTY CS_FIXED_BLOCK_HEIGHT 8\n"
 531                 "PROPERTY CS_FIXED_BLOCK_DEPTH 1\n"
 532                 "DCL SV[0], THREAD_ID\n"
 533                 "DCL SV[1], BLOCK_ID\n"
 534                 "DCL IMAGE[0], 2D_ARRAY, PIPE_FORMAT_R32G32B32A32_FLOAT, WR\n"
 535                 "DCL IMAGE[1], 2D_ARRAY, PIPE_FORMAT_R32G32B32A32_FLOAT, WR\n"
 536                 "DCL CONST[0][0..1]\n" // 0:xyzw 1:xyzw
 537                 "DCL TEMP[0..4], LOCAL\n"
 538                 "IMM[0] UINT32 {8, 1, 0, 0}\n"
 539                 "MOV TEMP[0].xyz, CONST[0][0].xyzw\n"
 540                 "UMAD TEMP[1].xyz, SV[1].xyzz, IMM[0].xxyy, SV[0].xyzz\n"
 541                 "UADD TEMP[2].xyz, TEMP[1].xyzx, TEMP[0].xyzx\n"
 542                 "LOAD TEMP[3], IMAGE[0], TEMP[2].xyzx, 2D_ARRAY, PIPE_FORMAT_R32G32B32A32_FLOAT\n"
 543                 "MOV TEMP[4].xyz, CONST[0][1].xyzw\n"
 544                 "UADD TEMP[2].xyz, TEMP[1].xyzx, TEMP[4].xyzx\n"
 545                 "STORE IMAGE[1], TEMP[2].xyzz, TEMP[3], 2D_ARRAY, PIPE_FORMAT_R32G32B32A32_FLOAT\n"
 546                 "END\n";
 547
 548         struct tgsi_token tokens[1024];
 549         struct pipe_compute_state state = {0};
 550
 551         if (!tgsi_text_translate(text, tokens, ARRAY_SIZE(tokens))) {
 552                 assert(false);
 553                 return NULL;
 554         }
 555
 556         state.ir_type = PIPE_SHADER_IR_TGSI;
 557         state.prog = tokens;
 558
 559         return ctx->create_compute_state(ctx, &state);
 560 }
 561
 562 void *si_create_copy_image_compute_shader_1d_array(struct pipe_context *ctx)
 563 {
 564         static const char text[] =
 565                 "COMP\n"
 566                 "PROPERTY CS_FIXED_BLOCK_WIDTH 64\n"
 567                 "PROPERTY CS_FIXED_BLOCK_HEIGHT 1\n"
 568                 "PROPERTY CS_FIXED_BLOCK_DEPTH 1\n"
 569                 "DCL SV[0], THREAD_ID\n"
 570                 "DCL SV[1], BLOCK_ID\n"
 571                 "DCL IMAGE[0], 1D_ARRAY, PIPE_FORMAT_R32G32B32A32_FLOAT, WR\n"
 572                 "DCL IMAGE[1], 1D_ARRAY, PIPE_FORMAT_R32G32B32A32_FLOAT, WR\n"
 573                 "DCL CONST[0][0..1]\n" // 0:xyzw 1:xyzw
 574                 "DCL TEMP[0..4], LOCAL\n"
 575                 "IMM[0] UINT32 {64, 1, 0, 0}\n"
 576                 "MOV TEMP[0].xy, CONST[0][0].xzzw\n"
 577                 "UMAD TEMP[1].xy, SV[1].xyzz, IMM[0].xyyy, SV[0].xyzz\n"
 578                 "UADD TEMP[2].xy, TEMP[1].xyzx, TEMP[0].xyzx\n"
 579                 "LOAD TEMP[3], IMAGE[0], TEMP[2].xyzx, 1D_ARRAY, PIPE_FORMAT_R32G32B32A32_FLOAT\n"
 580                 "MOV TEMP[4].xy, CONST[0][1].xzzw\n"
 581                 "UADD TEMP[2].xy, TEMP[1].xyzx, TEMP[4].xyzx\n"
 582                 "STORE IMAGE[1], TEMP[2].xyzz, TEMP[3], 1D_ARRAY, PIPE_FORMAT_R32G32B32A32_FLOAT\n"
 583                 "END\n";
 584
 585         struct tgsi_token tokens[1024];
 586         struct pipe_compute_state state = {0};
 587
 588         if (!tgsi_text_translate(text, tokens, ARRAY_SIZE(tokens))) {
 589                 assert(false);
 590                 return NULL;
 591         }
 592
 593         state.ir_type = PIPE_SHADER_IR_TGSI;
 594         state.prog = tokens;
 595
 596         return ctx->create_compute_state(ctx, &state);
 597 }
 598
 599 void *si_clear_render_target_shader(struct pipe_context *ctx)
 600 {
 601         static const char text[] =
 602                 "COMP\n"
 603                 "PROPERTY CS_FIXED_BLOCK_WIDTH 8\n"
 604                 "PROPERTY CS_FIXED_BLOCK_HEIGHT 8\n"
 605                 "PROPERTY CS_FIXED_BLOCK_DEPTH 1\n"
 606                 "DCL SV[0], THREAD_ID\n"
 607                 "DCL SV[1], BLOCK_ID\n"
 608                 "DCL IMAGE[0], 2D_ARRAY, PIPE_FORMAT_R32G32B32A32_FLOAT, WR\n"
 609                 "DCL CONST[0][0..1]\n" // 0:xyzw 1:xyzw
 610                 "DCL TEMP[0..3], LOCAL\n"
 611                 "IMM[0] UINT32 {8, 1, 0, 0}\n"
 612                 "MOV TEMP[0].xyz, CONST[0][0].xyzw\n"
 613                 "UMAD TEMP[1].xyz, SV[1].xyzz, IMM[0].xxyy, SV[0].xyzz\n"
 614                 "UADD TEMP[2].xyz, TEMP[1].xyzx, TEMP[0].xyzx\n"
 615                 "MOV TEMP[3].xyzw, CONST[0][1].xyzw\n"
 616                 "STORE IMAGE[0], TEMP[2].xyzz, TEMP[3], 2D_ARRAY, PIPE_FORMAT_R32G32B32A32_FLOAT\n"
 617                 "END\n";
 618
 619         struct tgsi_token tokens[1024];
 620         struct pipe_compute_state state = {0};
 621
 622         if (!tgsi_text_translate(text, tokens, ARRAY_SIZE(tokens))) {
 623                 assert(false);
 624                 return NULL;
 625         }
 626
 627         state.ir_type = PIPE_SHADER_IR_TGSI;
 628         state.prog = tokens;
 629
 630         return ctx->create_compute_state(ctx, &state);
 631 }
 632
 633 /* TODO: Didn't really test 1D_ARRAY */
 634 void *si_clear_render_target_shader_1d_array(struct pipe_context *ctx)
 635 {
 636         static const char text[] =
 637                 "COMP\n"
 638                 "PROPERTY CS_FIXED_BLOCK_WIDTH 64\n"
 639                 "PROPERTY CS_FIXED_BLOCK_HEIGHT 1\n"
 640                 "PROPERTY CS_FIXED_BLOCK_DEPTH 1\n"
 641                 "DCL SV[0], THREAD_ID\n"
 642                 "DCL SV[1], BLOCK_ID\n"
 643                 "DCL IMAGE[0], 1D_ARRAY, PIPE_FORMAT_R32G32B32A32_FLOAT, WR\n"
 644                 "DCL CONST[0][0..1]\n" // 0:xyzw 1:xyzw
 645                 "DCL TEMP[0..3], LOCAL\n"
 646                 "IMM[0] UINT32 {64, 1, 0, 0}\n"
 647                 "MOV TEMP[0].xy, CONST[0][0].xzzw\n"
 648                 "UMAD TEMP[1].xy, SV[1].xyzz, IMM[0].xyyy, SV[0].xyzz\n"
 649                 "UADD TEMP[2].xy, TEMP[1].xyzx, TEMP[0].xyzx\n"
 650                 "MOV TEMP[3].xyzw, CONST[0][1].xyzw\n"
 651                 "STORE IMAGE[0], TEMP[2].xyzz, TEMP[3], 1D_ARRAY, PIPE_FORMAT_R32G32B32A32_FLOAT\n"
 652                 "END\n";
 653
 654         struct tgsi_token tokens[1024];
 655         struct pipe_compute_state state = {0};
 656
 657         if (!tgsi_text_translate(text, tokens, ARRAY_SIZE(tokens))) {
 658                 assert(false);
 659                 return NULL;
 660         }
 661
 662         state.ir_type = PIPE_SHADER_IR_TGSI;
 663         state.prog = tokens;
 664
 665         return ctx->create_compute_state(ctx, &state);
 666 }
 667
 668 void *si_clear_12bytes_buffer_shader(struct pipe_context *ctx)
 669 {
 670         static const char text[] =
 671                 "COMP\n"
 672                 "PROPERTY CS_FIXED_BLOCK_WIDTH 64\n"
 673                 "PROPERTY CS_FIXED_BLOCK_HEIGHT 1\n"
 674                 "PROPERTY CS_FIXED_BLOCK_DEPTH 1\n"
 675                 "DCL SV[0], THREAD_ID\n"
 676                 "DCL SV[1], BLOCK_ID\n"
 677                 "DCL BUFFER[0]\n"
 678                 "DCL CONST[0][0..0]\n" // 0:xyzw
 679                 "DCL TEMP[0..0]\n"
 680                 "IMM[0] UINT32 {64, 1, 12, 0}\n"
 681                 "UMAD TEMP[0].x, SV[1].xyzz, IMM[0].xyyy, SV[0].xyzz\n"
 682                 "UMUL TEMP[0].x, TEMP[0].xyzz, IMM[0].zzzz\n" //12 bytes
 683                 "STORE BUFFER[0].xyz, TEMP[0].xxxx, CONST[0][0].xyzw\n"
 684                 "END\n";
 685
 686         struct tgsi_token tokens[1024];
 687         struct pipe_compute_state state = {0};
 688
 689         if (!tgsi_text_translate(text, tokens, ARRAY_SIZE(tokens))) {
 690                 assert(false);
 691                 return NULL;
 692         }
 693
 694         state.ir_type = PIPE_SHADER_IR_TGSI;
 695         state.prog = tokens;
 696
 697         return ctx->create_compute_state(ctx, &state);
 698 }
 699
 700
 701 /* Load samples from the image, and copy them to the same image. This looks like
 702  * a no-op, but it's not. Loads use FMASK, while stores don't, so samples are
 703  * reordered to match expanded FMASK.
 704  *
 705  * After the shader finishes, FMASK should be cleared to identity.
 706  */
 707 void *si_create_fmask_expand_cs(struct pipe_context *ctx, unsigned num_samples,
 708                                 bool is_array)
 709 {
 710         enum tgsi_texture_type target = is_array ? TGSI_TEXTURE_2D_ARRAY_MSAA :
 711                                                    TGSI_TEXTURE_2D_MSAA;
 712         struct ureg_program *ureg = ureg_create(PIPE_SHADER_COMPUTE);
 713         if (!ureg)
 714                 return NULL;
 715
 716         ureg_property(ureg, TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH, 8);
 717         ureg_property(ureg, TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT, 8);
 718         ureg_property(ureg, TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH, 1);
 719
 720         /* Compute the image coordinates. */
 721         struct ureg_src image = ureg_DECL_image(ureg, 0, target, 0, true, false);
 722         struct ureg_src tid = ureg_DECL_system_value(ureg, TGSI_SEMANTIC_THREAD_ID, 0);
 723         struct ureg_src blk = ureg_DECL_system_value(ureg, TGSI_SEMANTIC_BLOCK_ID, 0);
 724         struct ureg_dst coord = ureg_writemask(ureg_DECL_temporary(ureg),
 725                                                TGSI_WRITEMASK_XYZW);
 726         ureg_UMAD(ureg, ureg_writemask(coord, TGSI_WRITEMASK_XY),
 727                   ureg_swizzle(blk, 0, 1, 1, 1), ureg_imm2u(ureg, 8, 8),
 728                   ureg_swizzle(tid, 0, 1, 1, 1));
 729         if (is_array) {
 730                 ureg_MOV(ureg, ureg_writemask(coord, TGSI_WRITEMASK_Z),
 731                          ureg_scalar(blk, TGSI_SWIZZLE_Z));
 732         }
 733
 734         /* Load samples, resolving FMASK. */
 735         struct ureg_dst sample[8];
 736         assert(num_samples <= ARRAY_SIZE(sample));
 737
 738         for (unsigned i = 0; i < num_samples; i++) {
 739                 sample[i] = ureg_DECL_temporary(ureg);
 740
 741                 ureg_MOV(ureg, ureg_writemask(coord, TGSI_WRITEMASK_W),
 742                          ureg_imm1u(ureg, i));
 743
 744                 struct ureg_src srcs[] = {image, ureg_src(coord)};
 745                 ureg_memory_insn(ureg, TGSI_OPCODE_LOAD, &sample[i], 1, srcs, 2,
 746                                  TGSI_MEMORY_RESTRICT, target, 0);
 747         }
 748
 749         /* Store samples, ignoring FMASK. */
 750         for (unsigned i = 0; i < num_samples; i++) {
 751                 ureg_MOV(ureg, ureg_writemask(coord, TGSI_WRITEMASK_W),
 752                          ureg_imm1u(ureg, i));
 753
 754                 struct ureg_dst dst_image = ureg_dst(image);
 755                 struct ureg_src srcs[] = {ureg_src(coord), ureg_src(sample[i])};
 756                 ureg_memory_insn(ureg, TGSI_OPCODE_STORE, &dst_image, 1, srcs, 2,
 757                                  TGSI_MEMORY_RESTRICT, target, 0);
 758         }
 759         ureg_END(ureg);
 760
 761         struct pipe_compute_state state = {};
 762         state.ir_type = PIPE_SHADER_IR_TGSI;
 763         state.prog = ureg_get_tokens(ureg, NULL);
 764
 765         void *cs = ctx->create_compute_state(ctx, &state);
 766         ureg_destroy(ureg);
 767         return cs;
 768 }
 769
 770 /* Create the compute shader that is used to collect the results of gfx10+
 771  * shader queries.
 772  *
 773  * One compute grid with a single thread is launched for every query result
 774  * buffer. The thread (optionally) reads a previous summary buffer, then
 775  * accumulates data from the query result buffer, and writes the result either
 776  * to a summary buffer to be consumed by the next grid invocation or to the
 777  * user-supplied buffer.
 778  *
 779  * Data layout:
 780  *
 781  * BUFFER[0] = query result buffer (layout is defined by gfx10_sh_query_buffer_mem)
 782  * BUFFER[1] = previous summary buffer
 783  * BUFFER[2] = next summary buffer or user-supplied buffer
 784  *
 785  * CONST
 786  *  0.x = config; the low 3 bits indicate the mode:
 787  *          0: sum up counts
 788  *          1: determine result availability and write it as a boolean
 789  *          2: SO_OVERFLOW
 790  *          3: SO_ANY_OVERFLOW
 791  *        the remaining bits form a bitfield:
 792  *          8: write result as a 64-bit value
 793  *  0.y = offset in bytes to counts or stream for SO_OVERFLOW mode
 794  *  0.z = chain bit field:
 795  *          1: have previous summary buffer
 796  *          2: write next summary buffer
 797  *  0.w = result_count
 798  */
 799 void *gfx10_create_sh_query_result_cs(struct si_context *sctx)
 800 {
 801         /* TEMP[0].x = accumulated result so far
 802          * TEMP[0].y = result missing
 803          * TEMP[0].z = whether we're in overflow mode
 804          */
 805         static const char text_tmpl[] =
 806                 "COMP\n"
 807                 "PROPERTY CS_FIXED_BLOCK_WIDTH 1\n"
 808                 "PROPERTY CS_FIXED_BLOCK_HEIGHT 1\n"
 809                 "PROPERTY CS_FIXED_BLOCK_DEPTH 1\n"
 810                 "DCL BUFFER[0]\n"
 811                 "DCL BUFFER[1]\n"
 812                 "DCL BUFFER[2]\n"
 813                 "DCL CONST[0][0..0]\n"
 814                 "DCL TEMP[0..5]\n"
 815                 "IMM[0] UINT32 {0, 7, 0, 4294967295}\n"
 816                 "IMM[1] UINT32 {1, 2, 4, 8}\n"
 817                 "IMM[2] UINT32 {16, 32, 64, 128}\n"
 818
 819                 /*
 820                 acc_result = 0;
 821                 acc_missing = 0;
 822                 if (chain & 1) {
 823                         acc_result = buffer[1][0];
 824                         acc_missing = buffer[1][1];
 825                 }
 826                 */
 827                 "MOV TEMP[0].xy, IMM[0].xxxx\n"
 828                 "AND TEMP[5], CONST[0][0].zzzz, IMM[1].xxxx\n"
 829                 "UIF TEMP[5]\n"
 830                         "LOAD TEMP[0].xy, BUFFER[1], IMM[0].xxxx\n"
 831                 "ENDIF\n"
 832
 833                 /*
 834                 is_overflow (TEMP[0].z) = (config & 7) >= 2;
 835                 result_remaining (TEMP[1].x) = (is_overflow && acc_result) ? 0 : result_count;
 836                 base_offset (TEMP[1].y) = 0;
 837                 for (;;) {
 838                         if (!result_remaining)
 839                                 break;
 840                         result_remaining--;
 841                 */
 842                 "AND TEMP[5].x, CONST[0][0].xxxx, IMM[0].yyyy\n"
 843                 "USGE TEMP[0].z, TEMP[5].xxxx, IMM[1].yyyy\n"
 844
 845                 "AND TEMP[5].x, TEMP[0].zzzz, TEMP[0].xxxx\n"
 846                 "UCMP TEMP[1].x, TEMP[5].xxxx, IMM[0].xxxx, CONST[0][0].wwww\n"
 847                 "MOV TEMP[1].y, IMM[0].xxxx\n"
 848
 849                 "BGNLOOP\n"
 850                         "USEQ TEMP[5], TEMP[1].xxxx, IMM[0].xxxx\n"
 851                         "UIF TEMP[5]\n"
 852                                 "BRK\n"
 853                         "ENDIF\n"
 854                         "UADD TEMP[1].x, TEMP[1].xxxx, IMM[0].wwww\n"
 855
 856                         /*
 857                         fence = buffer[0]@(base_offset + 32);
 858                         if (!fence) {
 859                                 acc_missing = ~0u;
 860                                 break;
 861                         }
 862                         */
 863                         "UADD TEMP[5].x, TEMP[1].yyyy, IMM[2].yyyy\n"
 864                         "LOAD TEMP[5].x, BUFFER[0], TEMP[5].xxxx\n"
 865                         "USEQ TEMP[5], TEMP[5].xxxx, IMM[0].xxxx\n"
 866                         "UIF TEMP[5]\n"
 867                                 "MOV TEMP[0].y, TEMP[5].xxxx\n"
 868                                 "BRK\n"
 869                         "ENDIF\n"
 870
 871                         /*
 872                         stream_offset (TEMP[2].x) = base_offset + offset;
 873
 874                         if (!(config & 7)) {
 875                                 acc_result += buffer[0]@stream_offset;
 876                         }
 877                         */
 878                         "UADD TEMP[2].x, TEMP[1].yyyy, CONST[0][0].yyyy\n"
 879
 880                         "AND TEMP[5].x, CONST[0][0].xxxx, IMM[0].yyyy\n"
 881                         "USEQ TEMP[5], TEMP[5].xxxx, IMM[0].xxxx\n"
 882                         "UIF TEMP[5]\n"
 883                                 "LOAD TEMP[5].x, BUFFER[0], TEMP[2].xxxx\n"
 884                                 "UADD TEMP[0].x, TEMP[0].xxxx, TEMP[5].xxxx\n"
 885                         "ENDIF\n"
 886
 887                         /*
 888                         if ((config & 7) >= 2) {
 889                                 count (TEMP[2].y) = (config & 1) ? 4 : 1;
 890                         */
 891                         "AND TEMP[5].x, CONST[0][0].xxxx, IMM[0].yyyy\n"
 892                         "USGE TEMP[5], TEMP[5].xxxx, IMM[1].yyyy\n"
 893                         "UIF TEMP[5]\n"
 894                                 "AND TEMP[5].x, CONST[0][0].xxxx, IMM[1].xxxx\n"
 895                                 "UCMP TEMP[2].y, TEMP[5].xxxx, IMM[1].zzzz, IMM[1].xxxx\n"
 896
 897                                 /*
 898                                 do {
 899                                         generated = buffer[0]@stream_offset;
 900                                         emitted = buffer[0]@(stream_offset + 16);
 901                                         if (generated != emitted) {
 902                                                 acc_result = 1;
 903                                                 result_remaining = 0;
 904                                                 break;
 905                                         }
 906
 907                                         stream_offset += 4;
 908                                 } while (--count);
 909                                 */
 910                                 "BGNLOOP\n"
 911                                         "UADD TEMP[5].x, TEMP[2].xxxx, IMM[2].xxxx\n"
 912                                         "LOAD TEMP[4].x, BUFFER[0], TEMP[2].xxxx\n"
 913                                         "LOAD TEMP[4].y, BUFFER[0], TEMP[5].xxxx\n"
 914                                         "USNE TEMP[5], TEMP[4].xxxx, TEMP[4].yyyy\n"
 915                                         "UIF TEMP[5]\n"
 916                                                 "MOV TEMP[0].x, IMM[1].xxxx\n"
 917                                                 "MOV TEMP[1].y, IMM[0].xxxx\n"
 918                                                 "BRK\n"
 919                                         "ENDIF\n"
 920
 921                                         "UADD TEMP[2].y, TEMP[2].yyyy, IMM[0].wwww\n"
 922                                         "USEQ TEMP[5], TEMP[2].yyyy, IMM[0].xxxx\n"
 923                                         "UIF TEMP[5]\n"
 924                                                 "BRK\n"
 925                                         "ENDIF\n"
 926                                         "UADD TEMP[2].x, TEMP[2].xxxx, IMM[1].zzzz\n"
 927                                 "ENDLOOP\n"
 928                         "ENDIF\n"
 929
 930                 /*
 931                         base_offset += 64;
 932                 } // end outer loop
 933                 */
 934                         "UADD TEMP[1].y, TEMP[1].yyyy, IMM[2].zzzz\n"
 935                 "ENDLOOP\n"
 936
 937                 /*
 938                 if (chain & 2) {
 939                         buffer[2][0] = acc_result;
 940                         buffer[2][1] = acc_missing;
 941                 } else {
 942                 */
 943                 "AND TEMP[5], CONST[0][0].zzzz, IMM[1].yyyy\n"
 944                 "UIF TEMP[5]\n"
 945                         "STORE BUFFER[2].xy, IMM[0].xxxx, TEMP[0]\n"
 946                 "ELSE\n"
 947
 948                         /*
 949                         if ((config & 7) == 1) {
 950                                 acc_result = acc_missing ? 0 : 1;
 951                                 acc_missing = 0;
 952                         }
 953                         */
 954                         "AND TEMP[5], CONST[0][0].xxxx, IMM[0].yyyy\n"
 955                         "USEQ TEMP[5], TEMP[5].xxxx, IMM[1].xxxx\n"
 956                         "UIF TEMP[5]\n"
 957                                 "UCMP TEMP[0].x, TEMP[0].yyyy, IMM[0].xxxx, IMM[1].xxxx\n"
 958                                 "MOV TEMP[0].y, IMM[0].xxxx\n"
 959                         "ENDIF\n"
 960
 961                         /*
 962                         if (!acc_missing) {
 963                                 buffer[2][0] = acc_result;
 964                                 if (config & 8)
 965                                         buffer[2][1] = 0;
 966                         }
 967                         */
 968                         "USEQ TEMP[5], TEMP[0].yyyy, IMM[0].xxxx\n"
 969                         "UIF TEMP[5]\n"
 970                                 "STORE BUFFER[2].x, IMM[0].xxxx, TEMP[0].xxxx\n"
 971
 972                                 "AND TEMP[5], CONST[0][0].xxxx, IMM[1].wwww\n"
 973                                 "UIF TEMP[5]\n"
 974                                         "STORE BUFFER[2].x, IMM[1].zzzz, TEMP[0].yyyy\n"
 975                                 "ENDIF\n"
 976                         "ENDIF\n"
 977                 "ENDIF\n"
 978
 979                 "END\n";
 980
 981         struct tgsi_token tokens[1024];
 982         struct pipe_compute_state state = {};
 983
 984         if (!tgsi_text_translate(text_tmpl, tokens, ARRAY_SIZE(tokens))) {
 985                 assert(false);
 986                 return NULL;
 987         }
 988
 989         state.ir_type = PIPE_SHADER_IR_TGSI;
 990         state.prog = tokens;
 991
 992         return sctx->b.create_compute_state(&sctx->b, &state);
 993 }