2 * Copyright 2018 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "tgsi/tgsi_text.h"
27 #include "tgsi/tgsi_ureg.h"
29 void *si_get_blitter_vs(struct si_context
*sctx
, enum blitter_attrib_type type
,
32 unsigned vs_blit_property
;
36 case UTIL_BLITTER_ATTRIB_NONE
:
37 vs
= num_layers
> 1 ? &sctx
->vs_blit_pos_layered
:
39 vs_blit_property
= SI_VS_BLIT_SGPRS_POS
;
41 case UTIL_BLITTER_ATTRIB_COLOR
:
42 vs
= num_layers
> 1 ? &sctx
->vs_blit_color_layered
:
44 vs_blit_property
= SI_VS_BLIT_SGPRS_POS_COLOR
;
46 case UTIL_BLITTER_ATTRIB_TEXCOORD_XY
:
47 case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW
:
48 assert(num_layers
== 1);
49 vs
= &sctx
->vs_blit_texcoord
;
50 vs_blit_property
= SI_VS_BLIT_SGPRS_POS_TEXCOORD
;
59 struct ureg_program
*ureg
= ureg_create(PIPE_SHADER_VERTEX
);
63 /* Tell the shader to load VS inputs from SGPRs: */
64 ureg_property(ureg
, TGSI_PROPERTY_VS_BLIT_SGPRS_AMD
, vs_blit_property
);
65 ureg_property(ureg
, TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
, true);
67 /* This is just a pass-through shader with 1-3 MOV instructions. */
69 ureg_DECL_output(ureg
, TGSI_SEMANTIC_POSITION
, 0),
70 ureg_DECL_vs_input(ureg
, 0));
72 if (type
!= UTIL_BLITTER_ATTRIB_NONE
) {
74 ureg_DECL_output(ureg
, TGSI_SEMANTIC_GENERIC
, 0),
75 ureg_DECL_vs_input(ureg
, 1));
79 struct ureg_src instance_id
=
80 ureg_DECL_system_value(ureg
, TGSI_SEMANTIC_INSTANCEID
, 0);
81 struct ureg_dst layer
=
82 ureg_DECL_output(ureg
, TGSI_SEMANTIC_LAYER
, 0);
84 ureg_MOV(ureg
, ureg_writemask(layer
, TGSI_WRITEMASK_X
),
85 ureg_scalar(instance_id
, TGSI_SWIZZLE_X
));
89 *vs
= ureg_create_shader_and_destroy(ureg
, &sctx
->b
);
94 * This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
95 * VS passes its outputs to TES directly, so the fixed-function shader only
96 * has to write TESSOUTER and TESSINNER.
98 void *si_create_fixed_func_tcs(struct si_context
*sctx
)
100 struct ureg_src outer
, inner
;
101 struct ureg_dst tessouter
, tessinner
;
102 struct ureg_program
*ureg
= ureg_create(PIPE_SHADER_TESS_CTRL
);
107 outer
= ureg_DECL_system_value(ureg
,
108 TGSI_SEMANTIC_TESS_DEFAULT_OUTER_LEVEL
, 0);
109 inner
= ureg_DECL_system_value(ureg
,
110 TGSI_SEMANTIC_TESS_DEFAULT_INNER_LEVEL
, 0);
112 tessouter
= ureg_DECL_output(ureg
, TGSI_SEMANTIC_TESSOUTER
, 0);
113 tessinner
= ureg_DECL_output(ureg
, TGSI_SEMANTIC_TESSINNER
, 0);
115 ureg_MOV(ureg
, tessouter
, outer
);
116 ureg_MOV(ureg
, tessinner
, inner
);
119 return ureg_create_shader_and_destroy(ureg
, &sctx
->b
);
122 /* Create a compute shader implementing clear_buffer or copy_buffer. */
123 void *si_create_dma_compute_shader(struct pipe_context
*ctx
,
124 unsigned num_dwords_per_thread
,
125 bool dst_stream_cache_policy
, bool is_copy
)
127 struct si_screen
*sscreen
= (struct si_screen
*)ctx
->screen
;
128 assert(util_is_power_of_two_nonzero(num_dwords_per_thread
));
130 unsigned store_qualifier
= TGSI_MEMORY_COHERENT
| TGSI_MEMORY_RESTRICT
;
131 if (dst_stream_cache_policy
)
132 store_qualifier
|= TGSI_MEMORY_STREAM_CACHE_POLICY
;
134 /* Don't cache loads, because there is no reuse. */
135 unsigned load_qualifier
= store_qualifier
| TGSI_MEMORY_STREAM_CACHE_POLICY
;
137 unsigned num_mem_ops
= MAX2(1, num_dwords_per_thread
/ 4);
138 unsigned *inst_dwords
= alloca(num_mem_ops
* sizeof(unsigned));
140 for (unsigned i
= 0; i
< num_mem_ops
; i
++) {
141 if (i
*4 < num_dwords_per_thread
)
142 inst_dwords
[i
] = MIN2(4, num_dwords_per_thread
- i
*4);
145 struct ureg_program
*ureg
= ureg_create(PIPE_SHADER_COMPUTE
);
149 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
, sscreen
->compute_wave_size
);
150 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT
, 1);
151 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH
, 1);
153 struct ureg_src value
;
155 ureg_property(ureg
, TGSI_PROPERTY_CS_USER_DATA_COMPONENTS_AMD
, inst_dwords
[0]);
156 value
= ureg_DECL_system_value(ureg
, TGSI_SEMANTIC_CS_USER_DATA_AMD
, 0);
159 struct ureg_src tid
= ureg_DECL_system_value(ureg
, TGSI_SEMANTIC_THREAD_ID
, 0);
160 struct ureg_src blk
= ureg_DECL_system_value(ureg
, TGSI_SEMANTIC_BLOCK_ID
, 0);
161 struct ureg_dst store_addr
= ureg_writemask(ureg_DECL_temporary(ureg
), TGSI_WRITEMASK_X
);
162 struct ureg_dst load_addr
= ureg_writemask(ureg_DECL_temporary(ureg
), TGSI_WRITEMASK_X
);
163 struct ureg_dst dstbuf
= ureg_dst(ureg_DECL_buffer(ureg
, 0, false));
164 struct ureg_src srcbuf
;
165 struct ureg_src
*values
= NULL
;
168 srcbuf
= ureg_DECL_buffer(ureg
, 1, false);
169 values
= malloc(num_mem_ops
* sizeof(struct ureg_src
));
172 /* If there are multiple stores, the first store writes into 0*wavesize+tid,
173 * the 2nd store writes into 1*wavesize+tid, the 3rd store writes into 2*wavesize+tid, etc.
175 ureg_UMAD(ureg
, store_addr
, blk
,
176 ureg_imm1u(ureg
, sscreen
->compute_wave_size
* num_mem_ops
), tid
);
177 /* Convert from a "store size unit" into bytes. */
178 ureg_UMUL(ureg
, store_addr
, ureg_src(store_addr
),
179 ureg_imm1u(ureg
, 4 * inst_dwords
[0]));
180 ureg_MOV(ureg
, load_addr
, ureg_src(store_addr
));
182 /* Distance between a load and a store for latency hiding. */
183 unsigned load_store_distance
= is_copy
? 8 : 0;
185 for (unsigned i
= 0; i
< num_mem_ops
+ load_store_distance
; i
++) {
186 int d
= i
- load_store_distance
;
188 if (is_copy
&& i
< num_mem_ops
) {
190 ureg_UADD(ureg
, load_addr
, ureg_src(load_addr
),
191 ureg_imm1u(ureg
, 4 * inst_dwords
[i
] *
192 sscreen
->compute_wave_size
));
195 values
[i
] = ureg_src(ureg_DECL_temporary(ureg
));
196 struct ureg_dst dst
=
197 ureg_writemask(ureg_dst(values
[i
]),
198 u_bit_consecutive(0, inst_dwords
[i
]));
199 struct ureg_src srcs
[] = {srcbuf
, ureg_src(load_addr
)};
200 ureg_memory_insn(ureg
, TGSI_OPCODE_LOAD
, &dst
, 1, srcs
, 2,
201 load_qualifier
, TGSI_TEXTURE_BUFFER
, 0);
206 ureg_UADD(ureg
, store_addr
, ureg_src(store_addr
),
207 ureg_imm1u(ureg
, 4 * inst_dwords
[d
] *
208 sscreen
->compute_wave_size
));
211 struct ureg_dst dst
=
212 ureg_writemask(dstbuf
, u_bit_consecutive(0, inst_dwords
[d
]));
213 struct ureg_src srcs
[] =
214 {ureg_src(store_addr
), is_copy
? values
[d
] : value
};
215 ureg_memory_insn(ureg
, TGSI_OPCODE_STORE
, &dst
, 1, srcs
, 2,
216 store_qualifier
, TGSI_TEXTURE_BUFFER
, 0);
221 struct pipe_compute_state state
= {};
222 state
.ir_type
= PIPE_SHADER_IR_TGSI
;
223 state
.prog
= ureg_get_tokens(ureg
, NULL
);
225 void *cs
= ctx
->create_compute_state(ctx
, &state
);
227 ureg_free_tokens(state
.prog
);
233 /* Create a compute shader that copies DCC from one buffer to another
234 * where each DCC buffer has a different layout.
236 * image[0]: offset remap table (pairs of <src_offset, dst_offset>),
238 * image[1]: DCC source buffer, typed r8_uint
239 * image[2]: DCC destination buffer, typed r8_uint
241 void *si_create_dcc_retile_cs(struct pipe_context
*ctx
)
243 struct ureg_program
*ureg
= ureg_create(PIPE_SHADER_COMPUTE
);
247 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
, 64);
248 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT
, 1);
249 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH
, 1);
251 /* Compute the global thread ID (in idx). */
252 struct ureg_src tid
= ureg_DECL_system_value(ureg
, TGSI_SEMANTIC_THREAD_ID
, 0);
253 struct ureg_src blk
= ureg_DECL_system_value(ureg
, TGSI_SEMANTIC_BLOCK_ID
, 0);
254 struct ureg_dst idx
= ureg_writemask(ureg_DECL_temporary(ureg
),
256 ureg_UMAD(ureg
, idx
, blk
, ureg_imm1u(ureg
, 64), tid
);
258 /* Load 2 pairs of offsets for DCC load & store. */
259 struct ureg_src map
= ureg_DECL_image(ureg
, 0, TGSI_TEXTURE_BUFFER
, 0, false, false);
260 struct ureg_dst offsets
= ureg_DECL_temporary(ureg
);
261 struct ureg_src map_load_args
[] = {map
, ureg_src(idx
)};
263 ureg_memory_insn(ureg
, TGSI_OPCODE_LOAD
, &offsets
, 1, map_load_args
, 2,
264 TGSI_MEMORY_RESTRICT
, TGSI_TEXTURE_BUFFER
, 0);
266 struct ureg_src dcc_src
= ureg_DECL_image(ureg
, 1, TGSI_TEXTURE_BUFFER
,
268 struct ureg_dst dcc_dst
= ureg_dst(ureg_DECL_image(ureg
, 2, TGSI_TEXTURE_BUFFER
,
270 struct ureg_dst dcc_value
[2];
273 * dst[offsets.y] = src[offsets.x];
274 * dst[offsets.w] = src[offsets.z];
276 for (unsigned i
= 0; i
< 2; i
++) {
277 dcc_value
[i
] = ureg_writemask(ureg_DECL_temporary(ureg
), TGSI_WRITEMASK_X
);
279 struct ureg_src load_args
[] =
280 {dcc_src
, ureg_scalar(ureg_src(offsets
), TGSI_SWIZZLE_X
+ i
*2)};
281 ureg_memory_insn(ureg
, TGSI_OPCODE_LOAD
, &dcc_value
[i
], 1, load_args
, 2,
282 TGSI_MEMORY_RESTRICT
, TGSI_TEXTURE_BUFFER
, 0);
285 dcc_dst
= ureg_writemask(dcc_dst
, TGSI_WRITEMASK_X
);
287 for (unsigned i
= 0; i
< 2; i
++) {
288 struct ureg_src store_args
[] = {
289 ureg_scalar(ureg_src(offsets
), TGSI_SWIZZLE_Y
+ i
*2),
290 ureg_src(dcc_value
[i
])
292 ureg_memory_insn(ureg
, TGSI_OPCODE_STORE
, &dcc_dst
, 1, store_args
, 2,
293 TGSI_MEMORY_RESTRICT
, TGSI_TEXTURE_BUFFER
, 0);
297 struct pipe_compute_state state
= {};
298 state
.ir_type
= PIPE_SHADER_IR_TGSI
;
299 state
.prog
= ureg_get_tokens(ureg
, NULL
);
301 void *cs
= ctx
->create_compute_state(ctx
, &state
);
306 /* Create the compute shader that is used to collect the results.
308 * One compute grid with a single thread is launched for every query result
309 * buffer. The thread (optionally) reads a previous summary buffer, then
310 * accumulates data from the query result buffer, and writes the result either
311 * to a summary buffer to be consumed by the next grid invocation or to the
312 * user-supplied buffer.
318 * 0.y = result_stride
321 * 1: read previously accumulated values
322 * 2: write accumulated values for chaining
323 * 4: write result available
324 * 8: convert result to boolean (0/1)
325 * 16: only read one dword and use that as result
326 * 32: apply timestamp conversion
327 * 64: store full 64 bits result
328 * 128: store signed 32 bits result
329 * 256: SO_OVERFLOW mode: take the difference of two successive half-pairs
334 * BUFFER[0] = query result buffer
335 * BUFFER[1] = previous summary buffer
336 * BUFFER[2] = next summary buffer or user-supplied buffer
338 void *si_create_query_result_cs(struct si_context
*sctx
)
340 /* TEMP[0].xy = accumulated result so far
341 * TEMP[0].z = result not available
343 * TEMP[1].x = current result index
344 * TEMP[1].y = current pair index
346 static const char text_tmpl
[] =
348 "PROPERTY CS_FIXED_BLOCK_WIDTH 1\n"
349 "PROPERTY CS_FIXED_BLOCK_HEIGHT 1\n"
350 "PROPERTY CS_FIXED_BLOCK_DEPTH 1\n"
354 "DCL CONST[0][0..1]\n"
356 "IMM[0] UINT32 {0, 31, 2147483647, 4294967295}\n"
357 "IMM[1] UINT32 {1, 2, 4, 8}\n"
358 "IMM[2] UINT32 {16, 32, 64, 128}\n"
359 "IMM[3] UINT32 {1000000, 0, %u, 0}\n" /* for timestamp conversion */
360 "IMM[4] UINT32 {256, 0, 0, 0}\n"
362 "AND TEMP[5], CONST[0][0].wwww, IMM[2].xxxx\n"
364 /* Check result availability. */
365 "LOAD TEMP[1].x, BUFFER[0], CONST[0][1].xxxx\n"
366 "ISHR TEMP[0].z, TEMP[1].xxxx, IMM[0].yyyy\n"
367 "MOV TEMP[1], TEMP[0].zzzz\n"
368 "NOT TEMP[0].z, TEMP[0].zzzz\n"
370 /* Load result if available. */
372 "LOAD TEMP[0].xy, BUFFER[0], IMM[0].xxxx\n"
375 /* Load previously accumulated result if requested. */
376 "MOV TEMP[0], IMM[0].xxxx\n"
377 "AND TEMP[4], CONST[0][0].wwww, IMM[1].xxxx\n"
379 "LOAD TEMP[0].xyz, BUFFER[1], IMM[0].xxxx\n"
382 "MOV TEMP[1].x, IMM[0].xxxx\n"
384 /* Break if accumulated result so far is not available. */
389 /* Break if result_index >= result_count. */
390 "USGE TEMP[5], TEMP[1].xxxx, CONST[0][0].zzzz\n"
395 /* Load fence and check result availability */
396 "UMAD TEMP[5].x, TEMP[1].xxxx, CONST[0][0].yyyy, CONST[0][1].xxxx\n"
397 "LOAD TEMP[5].x, BUFFER[0], TEMP[5].xxxx\n"
398 "ISHR TEMP[0].z, TEMP[5].xxxx, IMM[0].yyyy\n"
399 "NOT TEMP[0].z, TEMP[0].zzzz\n"
404 "MOV TEMP[1].y, IMM[0].xxxx\n"
406 /* Load start and end. */
407 "UMUL TEMP[5].x, TEMP[1].xxxx, CONST[0][0].yyyy\n"
408 "UMAD TEMP[5].x, TEMP[1].yyyy, CONST[0][1].yyyy, TEMP[5].xxxx\n"
409 "LOAD TEMP[2].xy, BUFFER[0], TEMP[5].xxxx\n"
411 "UADD TEMP[5].y, TEMP[5].xxxx, CONST[0][0].xxxx\n"
412 "LOAD TEMP[3].xy, BUFFER[0], TEMP[5].yyyy\n"
414 "U64ADD TEMP[4].xy, TEMP[3], -TEMP[2]\n"
416 "AND TEMP[5].z, CONST[0][0].wwww, IMM[4].xxxx\n"
418 /* Load second start/end half-pair and
419 * take the difference
421 "UADD TEMP[5].xy, TEMP[5], IMM[1].wwww\n"
422 "LOAD TEMP[2].xy, BUFFER[0], TEMP[5].xxxx\n"
423 "LOAD TEMP[3].xy, BUFFER[0], TEMP[5].yyyy\n"
425 "U64ADD TEMP[3].xy, TEMP[3], -TEMP[2]\n"
426 "U64ADD TEMP[4].xy, TEMP[4], -TEMP[3]\n"
429 "U64ADD TEMP[0].xy, TEMP[0], TEMP[4]\n"
431 /* Increment pair index */
432 "UADD TEMP[1].y, TEMP[1].yyyy, IMM[1].xxxx\n"
433 "USGE TEMP[5], TEMP[1].yyyy, CONST[0][1].zzzz\n"
439 /* Increment result index */
440 "UADD TEMP[1].x, TEMP[1].xxxx, IMM[1].xxxx\n"
444 "AND TEMP[4], CONST[0][0].wwww, IMM[1].yyyy\n"
446 /* Store accumulated data for chaining. */
447 "STORE BUFFER[2].xyz, IMM[0].xxxx, TEMP[0]\n"
449 "AND TEMP[4], CONST[0][0].wwww, IMM[1].zzzz\n"
451 /* Store result availability. */
452 "NOT TEMP[0].z, TEMP[0]\n"
453 "AND TEMP[0].z, TEMP[0].zzzz, IMM[1].xxxx\n"
454 "STORE BUFFER[2].x, IMM[0].xxxx, TEMP[0].zzzz\n"
456 "AND TEMP[4], CONST[0][0].wwww, IMM[2].zzzz\n"
458 "STORE BUFFER[2].y, IMM[0].xxxx, IMM[0].xxxx\n"
461 /* Store result if it is available. */
462 "NOT TEMP[4], TEMP[0].zzzz\n"
464 /* Apply timestamp conversion */
465 "AND TEMP[4], CONST[0][0].wwww, IMM[2].yyyy\n"
467 "U64MUL TEMP[0].xy, TEMP[0], IMM[3].xyxy\n"
468 "U64DIV TEMP[0].xy, TEMP[0], IMM[3].zwzw\n"
471 /* Convert to boolean */
472 "AND TEMP[4], CONST[0][0].wwww, IMM[1].wwww\n"
474 "U64SNE TEMP[0].x, TEMP[0].xyxy, IMM[4].zwzw\n"
475 "AND TEMP[0].x, TEMP[0].xxxx, IMM[1].xxxx\n"
476 "MOV TEMP[0].y, IMM[0].xxxx\n"
479 "AND TEMP[4], CONST[0][0].wwww, IMM[2].zzzz\n"
481 "STORE BUFFER[2].xy, IMM[0].xxxx, TEMP[0].xyxy\n"
485 "MOV TEMP[0].x, IMM[0].wwww\n"
488 "AND TEMP[4], CONST[0][0].wwww, IMM[2].wwww\n"
490 "UMIN TEMP[0].x, TEMP[0].xxxx, IMM[0].zzzz\n"
493 "STORE BUFFER[2].x, IMM[0].xxxx, TEMP[0].xxxx\n"
501 char text
[sizeof(text_tmpl
) + 32];
502 struct tgsi_token tokens
[1024];
503 struct pipe_compute_state state
= {};
505 /* Hard code the frequency into the shader so that the backend can
506 * use the full range of optimizations for divide-by-constant.
508 snprintf(text
, sizeof(text
), text_tmpl
,
509 sctx
->screen
->info
.clock_crystal_freq
);
511 if (!tgsi_text_translate(text
, tokens
, ARRAY_SIZE(tokens
))) {
516 state
.ir_type
= PIPE_SHADER_IR_TGSI
;
519 return sctx
->b
.create_compute_state(&sctx
->b
, &state
);
522 /* Create a compute shader implementing copy_image.
523 * Luckily, this works with all texture targets except 1D_ARRAY.
525 void *si_create_copy_image_compute_shader(struct pipe_context
*ctx
)
527 static const char text
[] =
529 "PROPERTY CS_FIXED_BLOCK_WIDTH 8\n"
530 "PROPERTY CS_FIXED_BLOCK_HEIGHT 8\n"
531 "PROPERTY CS_FIXED_BLOCK_DEPTH 1\n"
532 "DCL SV[0], THREAD_ID\n"
533 "DCL SV[1], BLOCK_ID\n"
534 "DCL IMAGE[0], 2D_ARRAY, PIPE_FORMAT_R32G32B32A32_FLOAT, WR\n"
535 "DCL IMAGE[1], 2D_ARRAY, PIPE_FORMAT_R32G32B32A32_FLOAT, WR\n"
536 "DCL CONST[0][0..1]\n" // 0:xyzw 1:xyzw
537 "DCL TEMP[0..4], LOCAL\n"
538 "IMM[0] UINT32 {8, 1, 0, 0}\n"
539 "MOV TEMP[0].xyz, CONST[0][0].xyzw\n"
540 "UMAD TEMP[1].xyz, SV[1].xyzz, IMM[0].xxyy, SV[0].xyzz\n"
541 "UADD TEMP[2].xyz, TEMP[1].xyzx, TEMP[0].xyzx\n"
542 "LOAD TEMP[3], IMAGE[0], TEMP[2].xyzx, 2D_ARRAY, PIPE_FORMAT_R32G32B32A32_FLOAT\n"
543 "MOV TEMP[4].xyz, CONST[0][1].xyzw\n"
544 "UADD TEMP[2].xyz, TEMP[1].xyzx, TEMP[4].xyzx\n"
545 "STORE IMAGE[1], TEMP[2].xyzz, TEMP[3], 2D_ARRAY, PIPE_FORMAT_R32G32B32A32_FLOAT\n"
548 struct tgsi_token tokens
[1024];
549 struct pipe_compute_state state
= {0};
551 if (!tgsi_text_translate(text
, tokens
, ARRAY_SIZE(tokens
))) {
556 state
.ir_type
= PIPE_SHADER_IR_TGSI
;
559 return ctx
->create_compute_state(ctx
, &state
);
562 void *si_create_copy_image_compute_shader_1d_array(struct pipe_context
*ctx
)
564 static const char text
[] =
566 "PROPERTY CS_FIXED_BLOCK_WIDTH 64\n"
567 "PROPERTY CS_FIXED_BLOCK_HEIGHT 1\n"
568 "PROPERTY CS_FIXED_BLOCK_DEPTH 1\n"
569 "DCL SV[0], THREAD_ID\n"
570 "DCL SV[1], BLOCK_ID\n"
571 "DCL IMAGE[0], 1D_ARRAY, PIPE_FORMAT_R32G32B32A32_FLOAT, WR\n"
572 "DCL IMAGE[1], 1D_ARRAY, PIPE_FORMAT_R32G32B32A32_FLOAT, WR\n"
573 "DCL CONST[0][0..1]\n" // 0:xyzw 1:xyzw
574 "DCL TEMP[0..4], LOCAL\n"
575 "IMM[0] UINT32 {64, 1, 0, 0}\n"
576 "MOV TEMP[0].xy, CONST[0][0].xzzw\n"
577 "UMAD TEMP[1].xy, SV[1].xyzz, IMM[0].xyyy, SV[0].xyzz\n"
578 "UADD TEMP[2].xy, TEMP[1].xyzx, TEMP[0].xyzx\n"
579 "LOAD TEMP[3], IMAGE[0], TEMP[2].xyzx, 1D_ARRAY, PIPE_FORMAT_R32G32B32A32_FLOAT\n"
580 "MOV TEMP[4].xy, CONST[0][1].xzzw\n"
581 "UADD TEMP[2].xy, TEMP[1].xyzx, TEMP[4].xyzx\n"
582 "STORE IMAGE[1], TEMP[2].xyzz, TEMP[3], 1D_ARRAY, PIPE_FORMAT_R32G32B32A32_FLOAT\n"
585 struct tgsi_token tokens
[1024];
586 struct pipe_compute_state state
= {0};
588 if (!tgsi_text_translate(text
, tokens
, ARRAY_SIZE(tokens
))) {
593 state
.ir_type
= PIPE_SHADER_IR_TGSI
;
596 return ctx
->create_compute_state(ctx
, &state
);
599 void *si_clear_render_target_shader(struct pipe_context
*ctx
)
601 static const char text
[] =
603 "PROPERTY CS_FIXED_BLOCK_WIDTH 8\n"
604 "PROPERTY CS_FIXED_BLOCK_HEIGHT 8\n"
605 "PROPERTY CS_FIXED_BLOCK_DEPTH 1\n"
606 "DCL SV[0], THREAD_ID\n"
607 "DCL SV[1], BLOCK_ID\n"
608 "DCL IMAGE[0], 2D_ARRAY, PIPE_FORMAT_R32G32B32A32_FLOAT, WR\n"
609 "DCL CONST[0][0..1]\n" // 0:xyzw 1:xyzw
610 "DCL TEMP[0..3], LOCAL\n"
611 "IMM[0] UINT32 {8, 1, 0, 0}\n"
612 "MOV TEMP[0].xyz, CONST[0][0].xyzw\n"
613 "UMAD TEMP[1].xyz, SV[1].xyzz, IMM[0].xxyy, SV[0].xyzz\n"
614 "UADD TEMP[2].xyz, TEMP[1].xyzx, TEMP[0].xyzx\n"
615 "MOV TEMP[3].xyzw, CONST[0][1].xyzw\n"
616 "STORE IMAGE[0], TEMP[2].xyzz, TEMP[3], 2D_ARRAY, PIPE_FORMAT_R32G32B32A32_FLOAT\n"
619 struct tgsi_token tokens
[1024];
620 struct pipe_compute_state state
= {0};
622 if (!tgsi_text_translate(text
, tokens
, ARRAY_SIZE(tokens
))) {
627 state
.ir_type
= PIPE_SHADER_IR_TGSI
;
630 return ctx
->create_compute_state(ctx
, &state
);
633 /* TODO: Didn't really test 1D_ARRAY */
634 void *si_clear_render_target_shader_1d_array(struct pipe_context
*ctx
)
636 static const char text
[] =
638 "PROPERTY CS_FIXED_BLOCK_WIDTH 64\n"
639 "PROPERTY CS_FIXED_BLOCK_HEIGHT 1\n"
640 "PROPERTY CS_FIXED_BLOCK_DEPTH 1\n"
641 "DCL SV[0], THREAD_ID\n"
642 "DCL SV[1], BLOCK_ID\n"
643 "DCL IMAGE[0], 1D_ARRAY, PIPE_FORMAT_R32G32B32A32_FLOAT, WR\n"
644 "DCL CONST[0][0..1]\n" // 0:xyzw 1:xyzw
645 "DCL TEMP[0..3], LOCAL\n"
646 "IMM[0] UINT32 {64, 1, 0, 0}\n"
647 "MOV TEMP[0].xy, CONST[0][0].xzzw\n"
648 "UMAD TEMP[1].xy, SV[1].xyzz, IMM[0].xyyy, SV[0].xyzz\n"
649 "UADD TEMP[2].xy, TEMP[1].xyzx, TEMP[0].xyzx\n"
650 "MOV TEMP[3].xyzw, CONST[0][1].xyzw\n"
651 "STORE IMAGE[0], TEMP[2].xyzz, TEMP[3], 1D_ARRAY, PIPE_FORMAT_R32G32B32A32_FLOAT\n"
654 struct tgsi_token tokens
[1024];
655 struct pipe_compute_state state
= {0};
657 if (!tgsi_text_translate(text
, tokens
, ARRAY_SIZE(tokens
))) {
662 state
.ir_type
= PIPE_SHADER_IR_TGSI
;
665 return ctx
->create_compute_state(ctx
, &state
);
668 void *si_clear_12bytes_buffer_shader(struct pipe_context
*ctx
)
670 static const char text
[] =
672 "PROPERTY CS_FIXED_BLOCK_WIDTH 64\n"
673 "PROPERTY CS_FIXED_BLOCK_HEIGHT 1\n"
674 "PROPERTY CS_FIXED_BLOCK_DEPTH 1\n"
675 "DCL SV[0], THREAD_ID\n"
676 "DCL SV[1], BLOCK_ID\n"
678 "DCL CONST[0][0..0]\n" // 0:xyzw
680 "IMM[0] UINT32 {64, 1, 12, 0}\n"
681 "UMAD TEMP[0].x, SV[1].xyzz, IMM[0].xyyy, SV[0].xyzz\n"
682 "UMUL TEMP[0].x, TEMP[0].xyzz, IMM[0].zzzz\n" //12 bytes
683 "STORE BUFFER[0].xyz, TEMP[0].xxxx, CONST[0][0].xyzw\n"
686 struct tgsi_token tokens
[1024];
687 struct pipe_compute_state state
= {0};
689 if (!tgsi_text_translate(text
, tokens
, ARRAY_SIZE(tokens
))) {
694 state
.ir_type
= PIPE_SHADER_IR_TGSI
;
697 return ctx
->create_compute_state(ctx
, &state
);
701 /* Load samples from the image, and copy them to the same image. This looks like
702 * a no-op, but it's not. Loads use FMASK, while stores don't, so samples are
703 * reordered to match expanded FMASK.
705 * After the shader finishes, FMASK should be cleared to identity.
707 void *si_create_fmask_expand_cs(struct pipe_context
*ctx
, unsigned num_samples
,
710 enum tgsi_texture_type target
= is_array
? TGSI_TEXTURE_2D_ARRAY_MSAA
:
711 TGSI_TEXTURE_2D_MSAA
;
712 struct ureg_program
*ureg
= ureg_create(PIPE_SHADER_COMPUTE
);
716 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
, 8);
717 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT
, 8);
718 ureg_property(ureg
, TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH
, 1);
720 /* Compute the image coordinates. */
721 struct ureg_src image
= ureg_DECL_image(ureg
, 0, target
, 0, true, false);
722 struct ureg_src tid
= ureg_DECL_system_value(ureg
, TGSI_SEMANTIC_THREAD_ID
, 0);
723 struct ureg_src blk
= ureg_DECL_system_value(ureg
, TGSI_SEMANTIC_BLOCK_ID
, 0);
724 struct ureg_dst coord
= ureg_writemask(ureg_DECL_temporary(ureg
),
725 TGSI_WRITEMASK_XYZW
);
726 ureg_UMAD(ureg
, ureg_writemask(coord
, TGSI_WRITEMASK_XY
),
727 ureg_swizzle(blk
, 0, 1, 1, 1), ureg_imm2u(ureg
, 8, 8),
728 ureg_swizzle(tid
, 0, 1, 1, 1));
730 ureg_MOV(ureg
, ureg_writemask(coord
, TGSI_WRITEMASK_Z
),
731 ureg_scalar(blk
, TGSI_SWIZZLE_Z
));
734 /* Load samples, resolving FMASK. */
735 struct ureg_dst sample
[8];
736 assert(num_samples
<= ARRAY_SIZE(sample
));
738 for (unsigned i
= 0; i
< num_samples
; i
++) {
739 sample
[i
] = ureg_DECL_temporary(ureg
);
741 ureg_MOV(ureg
, ureg_writemask(coord
, TGSI_WRITEMASK_W
),
742 ureg_imm1u(ureg
, i
));
744 struct ureg_src srcs
[] = {image
, ureg_src(coord
)};
745 ureg_memory_insn(ureg
, TGSI_OPCODE_LOAD
, &sample
[i
], 1, srcs
, 2,
746 TGSI_MEMORY_RESTRICT
, target
, 0);
749 /* Store samples, ignoring FMASK. */
750 for (unsigned i
= 0; i
< num_samples
; i
++) {
751 ureg_MOV(ureg
, ureg_writemask(coord
, TGSI_WRITEMASK_W
),
752 ureg_imm1u(ureg
, i
));
754 struct ureg_dst dst_image
= ureg_dst(image
);
755 struct ureg_src srcs
[] = {ureg_src(coord
), ureg_src(sample
[i
])};
756 ureg_memory_insn(ureg
, TGSI_OPCODE_STORE
, &dst_image
, 1, srcs
, 2,
757 TGSI_MEMORY_RESTRICT
, target
, 0);
761 struct pipe_compute_state state
= {};
762 state
.ir_type
= PIPE_SHADER_IR_TGSI
;
763 state
.prog
= ureg_get_tokens(ureg
, NULL
);
765 void *cs
= ctx
->create_compute_state(ctx
, &state
);
770 /* Create the compute shader that is used to collect the results of gfx10+
773 * One compute grid with a single thread is launched for every query result
774 * buffer. The thread (optionally) reads a previous summary buffer, then
775 * accumulates data from the query result buffer, and writes the result either
776 * to a summary buffer to be consumed by the next grid invocation or to the
777 * user-supplied buffer.
781 * BUFFER[0] = query result buffer (layout is defined by gfx10_sh_query_buffer_mem)
782 * BUFFER[1] = previous summary buffer
783 * BUFFER[2] = next summary buffer or user-supplied buffer
786 * 0.x = config; the low 3 bits indicate the mode:
788 * 1: determine result availability and write it as a boolean
791 * the remaining bits form a bitfield:
792 * 8: write result as a 64-bit value
793 * 0.y = offset in bytes to counts or stream for SO_OVERFLOW mode
794 * 0.z = chain bit field:
795 * 1: have previous summary buffer
796 * 2: write next summary buffer
799 void *gfx10_create_sh_query_result_cs(struct si_context
*sctx
)
801 /* TEMP[0].x = accumulated result so far
802 * TEMP[0].y = result missing
803 * TEMP[0].z = whether we're in overflow mode
805 static const char text_tmpl
[] =
807 "PROPERTY CS_FIXED_BLOCK_WIDTH 1\n"
808 "PROPERTY CS_FIXED_BLOCK_HEIGHT 1\n"
809 "PROPERTY CS_FIXED_BLOCK_DEPTH 1\n"
813 "DCL CONST[0][0..0]\n"
815 "IMM[0] UINT32 {0, 7, 0, 4294967295}\n"
816 "IMM[1] UINT32 {1, 2, 4, 8}\n"
817 "IMM[2] UINT32 {16, 32, 64, 128}\n"
823 acc_result = buffer[1][0];
824 acc_missing = buffer[1][1];
827 "MOV TEMP[0].xy, IMM[0].xxxx\n"
828 "AND TEMP[5], CONST[0][0].zzzz, IMM[1].xxxx\n"
830 "LOAD TEMP[0].xy, BUFFER[1], IMM[0].xxxx\n"
834 is_overflow (TEMP[0].z) = (config & 7) >= 2;
835 result_remaining (TEMP[1].x) = (is_overflow && acc_result) ? 0 : result_count;
836 base_offset (TEMP[1].y) = 0;
838 if (!result_remaining)
842 "AND TEMP[5].x, CONST[0][0].xxxx, IMM[0].yyyy\n"
843 "USGE TEMP[0].z, TEMP[5].xxxx, IMM[1].yyyy\n"
845 "AND TEMP[5].x, TEMP[0].zzzz, TEMP[0].xxxx\n"
846 "UCMP TEMP[1].x, TEMP[5].xxxx, IMM[0].xxxx, CONST[0][0].wwww\n"
847 "MOV TEMP[1].y, IMM[0].xxxx\n"
850 "USEQ TEMP[5], TEMP[1].xxxx, IMM[0].xxxx\n"
854 "UADD TEMP[1].x, TEMP[1].xxxx, IMM[0].wwww\n"
857 fence = buffer[0]@(base_offset + 32);
863 "UADD TEMP[5].x, TEMP[1].yyyy, IMM[2].yyyy\n"
864 "LOAD TEMP[5].x, BUFFER[0], TEMP[5].xxxx\n"
865 "USEQ TEMP[5], TEMP[5].xxxx, IMM[0].xxxx\n"
867 "MOV TEMP[0].y, TEMP[5].xxxx\n"
872 stream_offset (TEMP[2].x) = base_offset + offset;
875 acc_result += buffer[0]@stream_offset;
878 "UADD TEMP[2].x, TEMP[1].yyyy, CONST[0][0].yyyy\n"
880 "AND TEMP[5].x, CONST[0][0].xxxx, IMM[0].yyyy\n"
881 "USEQ TEMP[5], TEMP[5].xxxx, IMM[0].xxxx\n"
883 "LOAD TEMP[5].x, BUFFER[0], TEMP[2].xxxx\n"
884 "UADD TEMP[0].x, TEMP[0].xxxx, TEMP[5].xxxx\n"
888 if ((config & 7) >= 2) {
889 count (TEMP[2].y) = (config & 1) ? 4 : 1;
891 "AND TEMP[5].x, CONST[0][0].xxxx, IMM[0].yyyy\n"
892 "USGE TEMP[5], TEMP[5].xxxx, IMM[1].yyyy\n"
894 "AND TEMP[5].x, CONST[0][0].xxxx, IMM[1].xxxx\n"
895 "UCMP TEMP[2].y, TEMP[5].xxxx, IMM[1].zzzz, IMM[1].xxxx\n"
899 generated = buffer[0]@stream_offset;
900 emitted = buffer[0]@(stream_offset + 16);
901 if (generated != emitted) {
903 result_remaining = 0;
911 "UADD TEMP[5].x, TEMP[2].xxxx, IMM[2].xxxx\n"
912 "LOAD TEMP[4].x, BUFFER[0], TEMP[2].xxxx\n"
913 "LOAD TEMP[4].y, BUFFER[0], TEMP[5].xxxx\n"
914 "USNE TEMP[5], TEMP[4].xxxx, TEMP[4].yyyy\n"
916 "MOV TEMP[0].x, IMM[1].xxxx\n"
917 "MOV TEMP[1].y, IMM[0].xxxx\n"
921 "UADD TEMP[2].y, TEMP[2].yyyy, IMM[0].wwww\n"
922 "USEQ TEMP[5], TEMP[2].yyyy, IMM[0].xxxx\n"
926 "UADD TEMP[2].x, TEMP[2].xxxx, IMM[1].zzzz\n"
934 "UADD TEMP[1].y, TEMP[1].yyyy, IMM[2].zzzz\n"
939 buffer[2][0] = acc_result;
940 buffer[2][1] = acc_missing;
943 "AND TEMP[5], CONST[0][0].zzzz, IMM[1].yyyy\n"
945 "STORE BUFFER[2].xy, IMM[0].xxxx, TEMP[0]\n"
949 if ((config & 7) == 1) {
950 acc_result = acc_missing ? 0 : 1;
954 "AND TEMP[5], CONST[0][0].xxxx, IMM[0].yyyy\n"
955 "USEQ TEMP[5], TEMP[5].xxxx, IMM[1].xxxx\n"
957 "UCMP TEMP[0].x, TEMP[0].yyyy, IMM[0].xxxx, IMM[1].xxxx\n"
958 "MOV TEMP[0].y, IMM[0].xxxx\n"
963 buffer[2][0] = acc_result;
968 "USEQ TEMP[5], TEMP[0].yyyy, IMM[0].xxxx\n"
970 "STORE BUFFER[2].x, IMM[0].xxxx, TEMP[0].xxxx\n"
972 "AND TEMP[5], CONST[0][0].xxxx, IMM[1].wwww\n"
974 "STORE BUFFER[2].x, IMM[1].zzzz, TEMP[0].yyyy\n"
981 struct tgsi_token tokens
[1024];
982 struct pipe_compute_state state
= {};
984 if (!tgsi_text_translate(text_tmpl
, tokens
, ARRAY_SIZE(tokens
))) {
989 state
.ir_type
= PIPE_SHADER_IR_TGSI
;
992 return sctx
->b
.create_compute_state(&sctx
->b
, &state
);