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radeonsi: correct texture memory size for Z32F_S8X24
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "util/u_memory.h"
28 #include "util/u_framebuffer.h"
29 #include "util/u_blitter.h"
30 #include "util/u_helpers.h"
31 #include "util/u_math.h"
32 #include "util/u_pack_color.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "radeonsi_pipe.h"
35 #include "radeonsi_shader.h"
36 #include "si_state.h"
37 #include "sid.h"
38
39 /*
40 * inferred framebuffer and blender state
41 */
42 static void si_update_fb_blend_state(struct r600_context *rctx)
43 {
44 struct si_pm4_state *pm4;
45 struct si_state_blend *blend = rctx->queued.named.blend;
46 uint32_t mask;
47
48 if (blend == NULL)
49 return;
50
51 pm4 = CALLOC_STRUCT(si_pm4_state);
52 if (pm4 == NULL)
53 return;
54
55 mask = (1ULL << ((unsigned)rctx->framebuffer.nr_cbufs * 4)) - 1;
56 mask &= blend->cb_target_mask;
57 si_pm4_set_reg(pm4, R_028238_CB_TARGET_MASK, mask);
58
59 si_pm4_set_state(rctx, fb_blend, pm4);
60 }
61
62 /*
63 * Blender functions
64 */
65
66 static uint32_t si_translate_blend_function(int blend_func)
67 {
68 switch (blend_func) {
69 case PIPE_BLEND_ADD:
70 return V_028780_COMB_DST_PLUS_SRC;
71 case PIPE_BLEND_SUBTRACT:
72 return V_028780_COMB_SRC_MINUS_DST;
73 case PIPE_BLEND_REVERSE_SUBTRACT:
74 return V_028780_COMB_DST_MINUS_SRC;
75 case PIPE_BLEND_MIN:
76 return V_028780_COMB_MIN_DST_SRC;
77 case PIPE_BLEND_MAX:
78 return V_028780_COMB_MAX_DST_SRC;
79 default:
80 R600_ERR("Unknown blend function %d\n", blend_func);
81 assert(0);
82 break;
83 }
84 return 0;
85 }
86
87 static uint32_t si_translate_blend_factor(int blend_fact)
88 {
89 switch (blend_fact) {
90 case PIPE_BLENDFACTOR_ONE:
91 return V_028780_BLEND_ONE;
92 case PIPE_BLENDFACTOR_SRC_COLOR:
93 return V_028780_BLEND_SRC_COLOR;
94 case PIPE_BLENDFACTOR_SRC_ALPHA:
95 return V_028780_BLEND_SRC_ALPHA;
96 case PIPE_BLENDFACTOR_DST_ALPHA:
97 return V_028780_BLEND_DST_ALPHA;
98 case PIPE_BLENDFACTOR_DST_COLOR:
99 return V_028780_BLEND_DST_COLOR;
100 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
101 return V_028780_BLEND_SRC_ALPHA_SATURATE;
102 case PIPE_BLENDFACTOR_CONST_COLOR:
103 return V_028780_BLEND_CONSTANT_COLOR;
104 case PIPE_BLENDFACTOR_CONST_ALPHA:
105 return V_028780_BLEND_CONSTANT_ALPHA;
106 case PIPE_BLENDFACTOR_ZERO:
107 return V_028780_BLEND_ZERO;
108 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
109 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
110 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
111 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
112 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
113 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
114 case PIPE_BLENDFACTOR_INV_DST_COLOR:
115 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
116 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
117 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
118 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
119 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
120 case PIPE_BLENDFACTOR_SRC1_COLOR:
121 return V_028780_BLEND_SRC1_COLOR;
122 case PIPE_BLENDFACTOR_SRC1_ALPHA:
123 return V_028780_BLEND_SRC1_ALPHA;
124 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
125 return V_028780_BLEND_INV_SRC1_COLOR;
126 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
127 return V_028780_BLEND_INV_SRC1_ALPHA;
128 default:
129 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
130 assert(0);
131 break;
132 }
133 return 0;
134 }
135
136 static void *si_create_blend_state(struct pipe_context *ctx,
137 const struct pipe_blend_state *state)
138 {
139 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
140 struct si_pm4_state *pm4 = &blend->pm4;
141
142 uint32_t color_control;
143
144 if (blend == NULL)
145 return NULL;
146
147 color_control = S_028808_MODE(V_028808_CB_NORMAL);
148 if (state->logicop_enable) {
149 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
150 } else {
151 color_control |= S_028808_ROP3(0xcc);
152 }
153 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
154
155 si_pm4_set_reg(pm4, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, ~0);
156 si_pm4_set_reg(pm4, R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, ~0);
157
158 blend->cb_target_mask = 0;
159 for (int i = 0; i < 8; i++) {
160 /* state->rt entries > 0 only written if independent blending */
161 const int j = state->independent_blend_enable ? i : 0;
162
163 unsigned eqRGB = state->rt[j].rgb_func;
164 unsigned srcRGB = state->rt[j].rgb_src_factor;
165 unsigned dstRGB = state->rt[j].rgb_dst_factor;
166 unsigned eqA = state->rt[j].alpha_func;
167 unsigned srcA = state->rt[j].alpha_src_factor;
168 unsigned dstA = state->rt[j].alpha_dst_factor;
169
170 unsigned blend_cntl = 0;
171
172 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
173 blend->cb_target_mask |= state->rt[j].colormask << (4 * i);
174
175 if (!state->rt[j].blend_enable) {
176 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
177 continue;
178 }
179
180 blend_cntl |= S_028780_ENABLE(1);
181 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
182 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
183 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
184
185 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
186 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
187 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
188 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
189 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
190 }
191 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
192 }
193
194 return blend;
195 }
196
197 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
198 {
199 struct r600_context *rctx = (struct r600_context *)ctx;
200 si_pm4_bind_state(rctx, blend, (struct si_state_blend *)state);
201 si_update_fb_blend_state(rctx);
202 }
203
204 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
205 {
206 struct r600_context *rctx = (struct r600_context *)ctx;
207 si_pm4_delete_state(rctx, blend, (struct si_state_blend *)state);
208 }
209
210 static void si_set_blend_color(struct pipe_context *ctx,
211 const struct pipe_blend_color *state)
212 {
213 struct r600_context *rctx = (struct r600_context *)ctx;
214 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
215
216 if (pm4 == NULL)
217 return;
218
219 si_pm4_set_reg(pm4, R_028414_CB_BLEND_RED, fui(state->color[0]));
220 si_pm4_set_reg(pm4, R_028418_CB_BLEND_GREEN, fui(state->color[1]));
221 si_pm4_set_reg(pm4, R_02841C_CB_BLEND_BLUE, fui(state->color[2]));
222 si_pm4_set_reg(pm4, R_028420_CB_BLEND_ALPHA, fui(state->color[3]));
223
224 si_pm4_set_state(rctx, blend_color, pm4);
225 }
226
227 /*
228 * Clipping, scissors and viewport
229 */
230
231 static void si_set_clip_state(struct pipe_context *ctx,
232 const struct pipe_clip_state *state)
233 {
234 struct r600_context *rctx = (struct r600_context *)ctx;
235 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
236
237 if (pm4 == NULL)
238 return;
239
240 for (int i = 0; i < 6; i++) {
241 si_pm4_set_reg(pm4, R_0285BC_PA_CL_UCP_0_X + i * 16,
242 fui(state->ucp[i][0]));
243 si_pm4_set_reg(pm4, R_0285C0_PA_CL_UCP_0_Y + i * 16,
244 fui(state->ucp[i][1]));
245 si_pm4_set_reg(pm4, R_0285C4_PA_CL_UCP_0_Z + i * 16,
246 fui(state->ucp[i][2]));
247 si_pm4_set_reg(pm4, R_0285C8_PA_CL_UCP_0_W + i * 16,
248 fui(state->ucp[i][3]));
249 }
250
251 si_pm4_set_state(rctx, clip, pm4);
252 }
253
254 static void si_set_scissor_state(struct pipe_context *ctx,
255 const struct pipe_scissor_state *state)
256 {
257 struct r600_context *rctx = (struct r600_context *)ctx;
258 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
259 uint32_t tl, br;
260
261 if (pm4 == NULL)
262 return;
263
264 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny);
265 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
266 si_pm4_set_reg(pm4, R_028210_PA_SC_CLIPRECT_0_TL, tl);
267 si_pm4_set_reg(pm4, R_028214_PA_SC_CLIPRECT_0_BR, br);
268 si_pm4_set_reg(pm4, R_028218_PA_SC_CLIPRECT_1_TL, tl);
269 si_pm4_set_reg(pm4, R_02821C_PA_SC_CLIPRECT_1_BR, br);
270 si_pm4_set_reg(pm4, R_028220_PA_SC_CLIPRECT_2_TL, tl);
271 si_pm4_set_reg(pm4, R_028224_PA_SC_CLIPRECT_2_BR, br);
272 si_pm4_set_reg(pm4, R_028228_PA_SC_CLIPRECT_3_TL, tl);
273 si_pm4_set_reg(pm4, R_02822C_PA_SC_CLIPRECT_3_BR, br);
274
275 si_pm4_set_state(rctx, scissor, pm4);
276 }
277
278 static void si_set_viewport_state(struct pipe_context *ctx,
279 const struct pipe_viewport_state *state)
280 {
281 struct r600_context *rctx = (struct r600_context *)ctx;
282 struct si_state_viewport *viewport = CALLOC_STRUCT(si_state_viewport);
283 struct si_pm4_state *pm4 = &viewport->pm4;
284
285 if (viewport == NULL)
286 return;
287
288 viewport->viewport = *state;
289 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000);
290 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000);
291 si_pm4_set_reg(pm4, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
292 si_pm4_set_reg(pm4, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
293 si_pm4_set_reg(pm4, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
294 si_pm4_set_reg(pm4, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
295 si_pm4_set_reg(pm4, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
296 si_pm4_set_reg(pm4, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
297 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
298
299 si_pm4_set_state(rctx, viewport, viewport);
300 }
301
302 /*
303 * inferred state between framebuffer and rasterizer
304 */
305 static void si_update_fb_rs_state(struct r600_context *rctx)
306 {
307 struct si_state_rasterizer *rs = rctx->queued.named.rasterizer;
308 struct si_pm4_state *pm4;
309 unsigned offset_db_fmt_cntl = 0, depth;
310 float offset_units;
311
312 if (!rs || !rctx->framebuffer.zsbuf)
313 return;
314
315 offset_units = rctx->queued.named.rasterizer->offset_units;
316 switch (rctx->framebuffer.zsbuf->texture->format) {
317 case PIPE_FORMAT_Z24X8_UNORM:
318 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
319 depth = -24;
320 offset_units *= 2.0f;
321 break;
322 case PIPE_FORMAT_Z32_FLOAT:
323 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
324 depth = -23;
325 offset_units *= 1.0f;
326 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
327 break;
328 case PIPE_FORMAT_Z16_UNORM:
329 depth = -16;
330 offset_units *= 4.0f;
331 break;
332 default:
333 return;
334 }
335
336 pm4 = CALLOC_STRUCT(si_pm4_state);
337 /* FIXME some of those reg can be computed with cso */
338 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
339 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
340 fui(rctx->queued.named.rasterizer->offset_scale));
341 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units));
342 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
343 fui(rctx->queued.named.rasterizer->offset_scale));
344 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units));
345 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, offset_db_fmt_cntl);
346
347 si_pm4_set_state(rctx, fb_rs, pm4);
348 }
349
350 /*
351 * Rasterizer
352 */
353
354 static uint32_t si_translate_fill(uint32_t func)
355 {
356 switch(func) {
357 case PIPE_POLYGON_MODE_FILL:
358 return V_028814_X_DRAW_TRIANGLES;
359 case PIPE_POLYGON_MODE_LINE:
360 return V_028814_X_DRAW_LINES;
361 case PIPE_POLYGON_MODE_POINT:
362 return V_028814_X_DRAW_POINTS;
363 default:
364 assert(0);
365 return V_028814_X_DRAW_POINTS;
366 }
367 }
368
369 static void *si_create_rs_state(struct pipe_context *ctx,
370 const struct pipe_rasterizer_state *state)
371 {
372 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
373 struct si_pm4_state *pm4 = &rs->pm4;
374 unsigned tmp;
375 unsigned prov_vtx = 1, polygon_dual_mode;
376 unsigned clip_rule;
377 float psize_min, psize_max;
378
379 if (rs == NULL) {
380 return NULL;
381 }
382
383 rs->two_side = state->light_twoside;
384
385 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
386 state->fill_back != PIPE_POLYGON_MODE_FILL);
387
388 if (state->flatshade_first)
389 prov_vtx = 0;
390
391 rs->flatshade = state->flatshade;
392 rs->sprite_coord_enable = state->sprite_coord_enable;
393 rs->pa_sc_line_stipple = state->line_stipple_enable ?
394 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
395 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
396 rs->pa_su_sc_mode_cntl =
397 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
398 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
399 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
400 S_028814_FACE(!state->front_ccw) |
401 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
402 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
403 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
404 S_028814_POLY_MODE(polygon_dual_mode) |
405 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
406 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back));
407 rs->pa_cl_clip_cntl =
408 S_028810_PS_UCP_MODE(3) |
409 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
410 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
411 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
412 rs->pa_cl_vs_out_cntl =
413 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
414 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex);
415
416 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
417
418 /* offset */
419 rs->offset_units = state->offset_units;
420 rs->offset_scale = state->offset_scale * 12.0f;
421
422 /* XXX: Flat shading hangs the GPU */
423 tmp = S_0286D4_FLAT_SHADE_ENA(0);
424 if (state->sprite_coord_enable) {
425 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
426 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
427 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
428 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
429 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1);
430 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
431 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
432 }
433 }
434 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
435
436 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0x00000000);
437 /* point size 12.4 fixed point */
438 tmp = (unsigned)(state->point_size * 8.0);
439 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
440
441 if (state->point_size_per_vertex) {
442 psize_min = util_get_min_point_size(state);
443 psize_max = 8192;
444 } else {
445 /* Force the point size to be as if the vertex output was disabled. */
446 psize_min = state->point_size;
447 psize_max = state->point_size;
448 }
449 /* Divide by two, because 0.5 = 1 pixel. */
450 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
451 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
452 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
453
454 tmp = (unsigned)state->line_width * 8;
455 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
456 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
457 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable));
458
459 si_pm4_set_reg(pm4, R_028BDC_PA_SC_LINE_CNTL, 0x00000400);
460 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
461 S_028BE4_PIX_CENTER(state->gl_rasterization_rules));
462 si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000);
463 si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000);
464 si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000);
465 si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000);
466
467 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
468 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule);
469
470 return rs;
471 }
472
473 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
474 {
475 struct r600_context *rctx = (struct r600_context *)ctx;
476 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
477
478 if (state == NULL)
479 return;
480
481 // TODO
482 rctx->sprite_coord_enable = rs->sprite_coord_enable;
483 rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
484 rctx->pa_su_sc_mode_cntl = rs->pa_su_sc_mode_cntl;
485 rctx->pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
486 rctx->pa_cl_vs_out_cntl = rs->pa_cl_vs_out_cntl;
487
488 si_pm4_bind_state(rctx, rasterizer, rs);
489 si_update_fb_rs_state(rctx);
490 }
491
492 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
493 {
494 struct r600_context *rctx = (struct r600_context *)ctx;
495 si_pm4_delete_state(rctx, rasterizer, (struct si_state_rasterizer *)state);
496 }
497
498 /*
499 * infeered state between dsa and stencil ref
500 */
501 static void si_update_dsa_stencil_ref(struct r600_context *rctx)
502 {
503 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
504 struct pipe_stencil_ref *ref = &rctx->stencil_ref;
505 struct si_state_dsa *dsa = rctx->queued.named.dsa;
506
507 if (pm4 == NULL)
508 return;
509
510 si_pm4_set_reg(pm4, R_028430_DB_STENCILREFMASK,
511 S_028430_STENCILTESTVAL(ref->ref_value[0]) |
512 S_028430_STENCILMASK(dsa->valuemask[0]) |
513 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
514 S_028430_STENCILOPVAL(1));
515 si_pm4_set_reg(pm4, R_028434_DB_STENCILREFMASK_BF,
516 S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
517 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
518 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
519 S_028434_STENCILOPVAL_BF(1));
520
521 si_pm4_set_state(rctx, dsa_stencil_ref, pm4);
522 }
523
524 static void si_set_pipe_stencil_ref(struct pipe_context *ctx,
525 const struct pipe_stencil_ref *state)
526 {
527 struct r600_context *rctx = (struct r600_context *)ctx;
528 rctx->stencil_ref = *state;
529 si_update_dsa_stencil_ref(rctx);
530 }
531
532
533 /*
534 * DSA
535 */
536
537 static uint32_t si_translate_stencil_op(int s_op)
538 {
539 switch (s_op) {
540 case PIPE_STENCIL_OP_KEEP:
541 return V_02842C_STENCIL_KEEP;
542 case PIPE_STENCIL_OP_ZERO:
543 return V_02842C_STENCIL_ZERO;
544 case PIPE_STENCIL_OP_REPLACE:
545 return V_02842C_STENCIL_REPLACE_TEST;
546 case PIPE_STENCIL_OP_INCR:
547 return V_02842C_STENCIL_ADD_CLAMP;
548 case PIPE_STENCIL_OP_DECR:
549 return V_02842C_STENCIL_SUB_CLAMP;
550 case PIPE_STENCIL_OP_INCR_WRAP:
551 return V_02842C_STENCIL_ADD_WRAP;
552 case PIPE_STENCIL_OP_DECR_WRAP:
553 return V_02842C_STENCIL_SUB_WRAP;
554 case PIPE_STENCIL_OP_INVERT:
555 return V_02842C_STENCIL_INVERT;
556 default:
557 R600_ERR("Unknown stencil op %d", s_op);
558 assert(0);
559 break;
560 }
561 return 0;
562 }
563
564 static void *si_create_dsa_state(struct pipe_context *ctx,
565 const struct pipe_depth_stencil_alpha_state *state)
566 {
567 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
568 struct si_pm4_state *pm4 = &dsa->pm4;
569 unsigned db_depth_control;
570 unsigned db_render_override, db_render_control;
571 uint32_t db_stencil_control = 0;
572
573 if (dsa == NULL) {
574 return NULL;
575 }
576
577 dsa->valuemask[0] = state->stencil[0].valuemask;
578 dsa->valuemask[1] = state->stencil[1].valuemask;
579 dsa->writemask[0] = state->stencil[0].writemask;
580 dsa->writemask[1] = state->stencil[1].writemask;
581
582 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
583 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
584 S_028800_ZFUNC(state->depth.func);
585
586 /* stencil */
587 if (state->stencil[0].enabled) {
588 db_depth_control |= S_028800_STENCIL_ENABLE(1);
589 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
590 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
591 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
592 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
593
594 if (state->stencil[1].enabled) {
595 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
596 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
597 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
598 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
599 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
600 }
601 }
602
603 /* alpha */
604 if (state->alpha.enabled) {
605 dsa->alpha_func = state->alpha.func;
606 dsa->alpha_ref = state->alpha.ref_value;
607 } else {
608 dsa->alpha_func = PIPE_FUNC_ALWAYS;
609 }
610
611 /* misc */
612 db_render_control = 0;
613 db_render_override = S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
614 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
615 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
616 /* TODO db_render_override depends on query */
617 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, 0x00000000);
618 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, 0x00000000);
619 si_pm4_set_reg(pm4, R_028028_DB_STENCIL_CLEAR, 0x00000000);
620 si_pm4_set_reg(pm4, R_02802C_DB_DEPTH_CLEAR, 0x3F800000);
621 //si_pm4_set_reg(pm4, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control);
622 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
623 si_pm4_set_reg(pm4, R_028000_DB_RENDER_CONTROL, db_render_control);
624 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
625 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
626 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
627 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
628 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
629 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00);
630 dsa->db_render_override = db_render_override;
631
632 return dsa;
633 }
634
635 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
636 {
637 struct r600_context *rctx = (struct r600_context *)ctx;
638 struct si_state_dsa *dsa = state;
639
640 if (state == NULL)
641 return;
642
643 si_pm4_bind_state(rctx, dsa, dsa);
644 si_update_dsa_stencil_ref(rctx);
645 }
646
647 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
648 {
649 struct r600_context *rctx = (struct r600_context *)ctx;
650 si_pm4_delete_state(rctx, dsa, (struct si_state_dsa *)state);
651 }
652
653 static void *si_create_db_flush_dsa(struct r600_context *rctx)
654 {
655 struct pipe_depth_stencil_alpha_state dsa;
656 struct si_state_dsa *state;
657
658 memset(&dsa, 0, sizeof(dsa));
659
660 state = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
661 si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL,
662 S_028000_DEPTH_COPY(1) |
663 S_028000_STENCIL_COPY(1) |
664 S_028000_COPY_CENTROID(1));
665 return state;
666 }
667
668 /*
669 * format translation
670 */
671 static uint32_t si_translate_colorformat(enum pipe_format format)
672 {
673 switch (format) {
674 /* 8-bit buffers. */
675 case PIPE_FORMAT_A8_UNORM:
676 case PIPE_FORMAT_A8_SNORM:
677 case PIPE_FORMAT_A8_UINT:
678 case PIPE_FORMAT_A8_SINT:
679 case PIPE_FORMAT_I8_UNORM:
680 case PIPE_FORMAT_I8_SNORM:
681 case PIPE_FORMAT_I8_UINT:
682 case PIPE_FORMAT_I8_SINT:
683 case PIPE_FORMAT_L8_UNORM:
684 case PIPE_FORMAT_L8_SNORM:
685 case PIPE_FORMAT_L8_UINT:
686 case PIPE_FORMAT_L8_SINT:
687 case PIPE_FORMAT_L8_SRGB:
688 case PIPE_FORMAT_R8_UNORM:
689 case PIPE_FORMAT_R8_SNORM:
690 case PIPE_FORMAT_R8_UINT:
691 case PIPE_FORMAT_R8_SINT:
692 return V_028C70_COLOR_8;
693
694 /* 16-bit buffers. */
695 case PIPE_FORMAT_B5G6R5_UNORM:
696 return V_028C70_COLOR_5_6_5;
697
698 case PIPE_FORMAT_B5G5R5A1_UNORM:
699 case PIPE_FORMAT_B5G5R5X1_UNORM:
700 return V_028C70_COLOR_1_5_5_5;
701
702 case PIPE_FORMAT_B4G4R4A4_UNORM:
703 case PIPE_FORMAT_B4G4R4X4_UNORM:
704 return V_028C70_COLOR_4_4_4_4;
705
706 case PIPE_FORMAT_L8A8_UNORM:
707 case PIPE_FORMAT_L8A8_SNORM:
708 case PIPE_FORMAT_L8A8_UINT:
709 case PIPE_FORMAT_L8A8_SINT:
710 case PIPE_FORMAT_L8A8_SRGB:
711 case PIPE_FORMAT_R8G8_SNORM:
712 case PIPE_FORMAT_R8G8_UNORM:
713 case PIPE_FORMAT_R8G8_UINT:
714 case PIPE_FORMAT_R8G8_SINT:
715 return V_028C70_COLOR_8_8;
716
717 case PIPE_FORMAT_Z16_UNORM:
718 case PIPE_FORMAT_R16_UNORM:
719 case PIPE_FORMAT_R16_SNORM:
720 case PIPE_FORMAT_R16_UINT:
721 case PIPE_FORMAT_R16_SINT:
722 case PIPE_FORMAT_R16_FLOAT:
723 case PIPE_FORMAT_L16_UNORM:
724 case PIPE_FORMAT_L16_SNORM:
725 case PIPE_FORMAT_L16_FLOAT:
726 case PIPE_FORMAT_I16_UNORM:
727 case PIPE_FORMAT_I16_SNORM:
728 case PIPE_FORMAT_I16_FLOAT:
729 case PIPE_FORMAT_A16_UNORM:
730 case PIPE_FORMAT_A16_SNORM:
731 case PIPE_FORMAT_A16_FLOAT:
732 return V_028C70_COLOR_16;
733
734 /* 32-bit buffers. */
735 case PIPE_FORMAT_A8B8G8R8_SRGB:
736 case PIPE_FORMAT_A8B8G8R8_UNORM:
737 case PIPE_FORMAT_A8R8G8B8_UNORM:
738 case PIPE_FORMAT_B8G8R8A8_SRGB:
739 case PIPE_FORMAT_B8G8R8A8_UNORM:
740 case PIPE_FORMAT_B8G8R8X8_UNORM:
741 case PIPE_FORMAT_R8G8B8A8_SNORM:
742 case PIPE_FORMAT_R8G8B8A8_UNORM:
743 case PIPE_FORMAT_R8G8B8X8_UNORM:
744 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
745 case PIPE_FORMAT_X8B8G8R8_UNORM:
746 case PIPE_FORMAT_X8R8G8B8_UNORM:
747 case PIPE_FORMAT_R8G8B8_UNORM:
748 case PIPE_FORMAT_R8G8B8A8_SSCALED:
749 case PIPE_FORMAT_R8G8B8A8_USCALED:
750 case PIPE_FORMAT_R8G8B8A8_SINT:
751 case PIPE_FORMAT_R8G8B8A8_UINT:
752 return V_028C70_COLOR_8_8_8_8;
753
754 case PIPE_FORMAT_R10G10B10A2_UNORM:
755 case PIPE_FORMAT_R10G10B10X2_SNORM:
756 case PIPE_FORMAT_B10G10R10A2_UNORM:
757 case PIPE_FORMAT_B10G10R10A2_UINT:
758 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
759 return V_028C70_COLOR_2_10_10_10;
760
761 case PIPE_FORMAT_Z24X8_UNORM:
762 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
763 return V_028C70_COLOR_8_24;
764
765 case PIPE_FORMAT_X8Z24_UNORM:
766 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
767 return V_028C70_COLOR_24_8;
768
769 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
770 return V_028C70_COLOR_X24_8_32_FLOAT;
771
772 case PIPE_FORMAT_I32_FLOAT:
773 case PIPE_FORMAT_L32_FLOAT:
774 case PIPE_FORMAT_R32_FLOAT:
775 case PIPE_FORMAT_A32_FLOAT:
776 case PIPE_FORMAT_Z32_FLOAT:
777 return V_028C70_COLOR_32;
778
779 case PIPE_FORMAT_L16A16_UNORM:
780 case PIPE_FORMAT_L16A16_SNORM:
781 case PIPE_FORMAT_L16A16_FLOAT:
782 case PIPE_FORMAT_R16G16_SSCALED:
783 case PIPE_FORMAT_R16G16_UNORM:
784 case PIPE_FORMAT_R16G16_SNORM:
785 case PIPE_FORMAT_R16G16_UINT:
786 case PIPE_FORMAT_R16G16_SINT:
787 case PIPE_FORMAT_R16G16_FLOAT:
788 return V_028C70_COLOR_16_16;
789
790 case PIPE_FORMAT_R11G11B10_FLOAT:
791 return V_028C70_COLOR_10_11_11;
792
793 /* 64-bit buffers. */
794 case PIPE_FORMAT_R16G16B16_USCALED:
795 case PIPE_FORMAT_R16G16B16_SSCALED:
796 case PIPE_FORMAT_R16G16B16A16_UINT:
797 case PIPE_FORMAT_R16G16B16A16_SINT:
798 case PIPE_FORMAT_R16G16B16A16_USCALED:
799 case PIPE_FORMAT_R16G16B16A16_SSCALED:
800 case PIPE_FORMAT_R16G16B16A16_UNORM:
801 case PIPE_FORMAT_R16G16B16A16_SNORM:
802 case PIPE_FORMAT_R16G16B16_FLOAT:
803 case PIPE_FORMAT_R16G16B16A16_FLOAT:
804 return V_028C70_COLOR_16_16_16_16;
805
806 case PIPE_FORMAT_L32A32_FLOAT:
807 case PIPE_FORMAT_R32G32_FLOAT:
808 case PIPE_FORMAT_R32G32_USCALED:
809 case PIPE_FORMAT_R32G32_SSCALED:
810 case PIPE_FORMAT_R32G32_SINT:
811 case PIPE_FORMAT_R32G32_UINT:
812 return V_028C70_COLOR_32_32;
813
814 /* 128-bit buffers. */
815 case PIPE_FORMAT_R32G32B32A32_SNORM:
816 case PIPE_FORMAT_R32G32B32A32_UNORM:
817 case PIPE_FORMAT_R32G32B32A32_SSCALED:
818 case PIPE_FORMAT_R32G32B32A32_USCALED:
819 case PIPE_FORMAT_R32G32B32A32_SINT:
820 case PIPE_FORMAT_R32G32B32A32_UINT:
821 case PIPE_FORMAT_R32G32B32A32_FLOAT:
822 return V_028C70_COLOR_32_32_32_32;
823
824 /* YUV buffers. */
825 case PIPE_FORMAT_UYVY:
826 case PIPE_FORMAT_YUYV:
827 /* 96-bit buffers. */
828 case PIPE_FORMAT_R32G32B32_FLOAT:
829 /* 8-bit buffers. */
830 case PIPE_FORMAT_L4A4_UNORM:
831 case PIPE_FORMAT_R4A4_UNORM:
832 case PIPE_FORMAT_A4R4_UNORM:
833 default:
834 return V_028C70_COLOR_INVALID; /* Unsupported. */
835 }
836 }
837
838 static uint32_t si_translate_colorswap(enum pipe_format format)
839 {
840 switch (format) {
841 /* 8-bit buffers. */
842 case PIPE_FORMAT_L4A4_UNORM:
843 case PIPE_FORMAT_A4R4_UNORM:
844 return V_028C70_SWAP_ALT;
845
846 case PIPE_FORMAT_A8_UNORM:
847 case PIPE_FORMAT_A8_SNORM:
848 case PIPE_FORMAT_A8_UINT:
849 case PIPE_FORMAT_A8_SINT:
850 case PIPE_FORMAT_R4A4_UNORM:
851 return V_028C70_SWAP_ALT_REV;
852 case PIPE_FORMAT_I8_UNORM:
853 case PIPE_FORMAT_I8_SNORM:
854 case PIPE_FORMAT_L8_UNORM:
855 case PIPE_FORMAT_L8_SNORM:
856 case PIPE_FORMAT_I8_UINT:
857 case PIPE_FORMAT_I8_SINT:
858 case PIPE_FORMAT_L8_UINT:
859 case PIPE_FORMAT_L8_SINT:
860 case PIPE_FORMAT_L8_SRGB:
861 case PIPE_FORMAT_R8_UNORM:
862 case PIPE_FORMAT_R8_SNORM:
863 case PIPE_FORMAT_R8_UINT:
864 case PIPE_FORMAT_R8_SINT:
865 return V_028C70_SWAP_STD;
866
867 /* 16-bit buffers. */
868 case PIPE_FORMAT_B5G6R5_UNORM:
869 return V_028C70_SWAP_STD_REV;
870
871 case PIPE_FORMAT_B5G5R5A1_UNORM:
872 case PIPE_FORMAT_B5G5R5X1_UNORM:
873 return V_028C70_SWAP_ALT;
874
875 case PIPE_FORMAT_B4G4R4A4_UNORM:
876 case PIPE_FORMAT_B4G4R4X4_UNORM:
877 return V_028C70_SWAP_ALT;
878
879 case PIPE_FORMAT_Z16_UNORM:
880 return V_028C70_SWAP_STD;
881
882 case PIPE_FORMAT_L8A8_UNORM:
883 case PIPE_FORMAT_L8A8_SNORM:
884 case PIPE_FORMAT_L8A8_UINT:
885 case PIPE_FORMAT_L8A8_SINT:
886 case PIPE_FORMAT_L8A8_SRGB:
887 return V_028C70_SWAP_ALT;
888 case PIPE_FORMAT_R8G8_SNORM:
889 case PIPE_FORMAT_R8G8_UNORM:
890 case PIPE_FORMAT_R8G8_UINT:
891 case PIPE_FORMAT_R8G8_SINT:
892 return V_028C70_SWAP_STD;
893
894 case PIPE_FORMAT_I16_UNORM:
895 case PIPE_FORMAT_I16_SNORM:
896 case PIPE_FORMAT_I16_FLOAT:
897 case PIPE_FORMAT_L16_UNORM:
898 case PIPE_FORMAT_L16_SNORM:
899 case PIPE_FORMAT_L16_FLOAT:
900 case PIPE_FORMAT_R16_UNORM:
901 case PIPE_FORMAT_R16_SNORM:
902 case PIPE_FORMAT_R16_UINT:
903 case PIPE_FORMAT_R16_SINT:
904 case PIPE_FORMAT_R16_FLOAT:
905 return V_028C70_SWAP_STD;
906
907 case PIPE_FORMAT_A16_UNORM:
908 case PIPE_FORMAT_A16_SNORM:
909 case PIPE_FORMAT_A16_FLOAT:
910 return V_028C70_SWAP_ALT_REV;
911
912 /* 32-bit buffers. */
913 case PIPE_FORMAT_A8B8G8R8_SRGB:
914 return V_028C70_SWAP_STD_REV;
915 case PIPE_FORMAT_B8G8R8A8_SRGB:
916 return V_028C70_SWAP_ALT;
917
918 case PIPE_FORMAT_B8G8R8A8_UNORM:
919 case PIPE_FORMAT_B8G8R8X8_UNORM:
920 return V_028C70_SWAP_ALT;
921
922 case PIPE_FORMAT_A8R8G8B8_UNORM:
923 case PIPE_FORMAT_X8R8G8B8_UNORM:
924 return V_028C70_SWAP_ALT_REV;
925 case PIPE_FORMAT_R8G8B8A8_SNORM:
926 case PIPE_FORMAT_R8G8B8A8_UNORM:
927 case PIPE_FORMAT_R8G8B8A8_SSCALED:
928 case PIPE_FORMAT_R8G8B8A8_USCALED:
929 case PIPE_FORMAT_R8G8B8A8_SINT:
930 case PIPE_FORMAT_R8G8B8A8_UINT:
931 case PIPE_FORMAT_R8G8B8X8_UNORM:
932 return V_028C70_SWAP_STD;
933
934 case PIPE_FORMAT_A8B8G8R8_UNORM:
935 case PIPE_FORMAT_X8B8G8R8_UNORM:
936 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
937 return V_028C70_SWAP_STD_REV;
938
939 case PIPE_FORMAT_Z24X8_UNORM:
940 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
941 return V_028C70_SWAP_STD;
942
943 case PIPE_FORMAT_X8Z24_UNORM:
944 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
945 return V_028C70_SWAP_STD;
946
947 case PIPE_FORMAT_R10G10B10A2_UNORM:
948 case PIPE_FORMAT_R10G10B10X2_SNORM:
949 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
950 return V_028C70_SWAP_STD;
951
952 case PIPE_FORMAT_B10G10R10A2_UNORM:
953 case PIPE_FORMAT_B10G10R10A2_UINT:
954 return V_028C70_SWAP_ALT;
955
956 case PIPE_FORMAT_R11G11B10_FLOAT:
957 case PIPE_FORMAT_I32_FLOAT:
958 case PIPE_FORMAT_L32_FLOAT:
959 case PIPE_FORMAT_R32_FLOAT:
960 case PIPE_FORMAT_R32_UINT:
961 case PIPE_FORMAT_R32_SINT:
962 case PIPE_FORMAT_Z32_FLOAT:
963 case PIPE_FORMAT_R16G16_FLOAT:
964 case PIPE_FORMAT_R16G16_UNORM:
965 case PIPE_FORMAT_R16G16_SNORM:
966 case PIPE_FORMAT_R16G16_UINT:
967 case PIPE_FORMAT_R16G16_SINT:
968 return V_028C70_SWAP_STD;
969
970 case PIPE_FORMAT_L16A16_UNORM:
971 case PIPE_FORMAT_L16A16_SNORM:
972 case PIPE_FORMAT_L16A16_FLOAT:
973 return V_028C70_SWAP_ALT;
974
975 case PIPE_FORMAT_A32_FLOAT:
976 return V_028C70_SWAP_ALT_REV;
977
978 /* 64-bit buffers. */
979 case PIPE_FORMAT_R32G32_FLOAT:
980 case PIPE_FORMAT_R32G32_UINT:
981 case PIPE_FORMAT_R32G32_SINT:
982 case PIPE_FORMAT_R16G16B16A16_UNORM:
983 case PIPE_FORMAT_R16G16B16A16_SNORM:
984 case PIPE_FORMAT_R16G16B16A16_USCALED:
985 case PIPE_FORMAT_R16G16B16A16_SSCALED:
986 case PIPE_FORMAT_R16G16B16A16_UINT:
987 case PIPE_FORMAT_R16G16B16A16_SINT:
988 case PIPE_FORMAT_R16G16B16A16_FLOAT:
989 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
990 return V_028C70_SWAP_STD;
991
992 case PIPE_FORMAT_L32A32_FLOAT:
993 return V_028C70_SWAP_ALT;
994
995 /* 128-bit buffers. */
996 case PIPE_FORMAT_R32G32B32A32_FLOAT:
997 case PIPE_FORMAT_R32G32B32A32_SNORM:
998 case PIPE_FORMAT_R32G32B32A32_UNORM:
999 case PIPE_FORMAT_R32G32B32A32_SSCALED:
1000 case PIPE_FORMAT_R32G32B32A32_USCALED:
1001 case PIPE_FORMAT_R32G32B32A32_SINT:
1002 case PIPE_FORMAT_R32G32B32A32_UINT:
1003 return V_028C70_SWAP_STD;
1004 default:
1005 R600_ERR("unsupported colorswap format %d\n", format);
1006 return ~0U;
1007 }
1008 return ~0U;
1009 }
1010
1011 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1012 {
1013 if (R600_BIG_ENDIAN) {
1014 switch(colorformat) {
1015 /* 8-bit buffers. */
1016 case V_028C70_COLOR_8:
1017 return V_028C70_ENDIAN_NONE;
1018
1019 /* 16-bit buffers. */
1020 case V_028C70_COLOR_5_6_5:
1021 case V_028C70_COLOR_1_5_5_5:
1022 case V_028C70_COLOR_4_4_4_4:
1023 case V_028C70_COLOR_16:
1024 case V_028C70_COLOR_8_8:
1025 return V_028C70_ENDIAN_8IN16;
1026
1027 /* 32-bit buffers. */
1028 case V_028C70_COLOR_8_8_8_8:
1029 case V_028C70_COLOR_2_10_10_10:
1030 case V_028C70_COLOR_8_24:
1031 case V_028C70_COLOR_24_8:
1032 case V_028C70_COLOR_16_16:
1033 return V_028C70_ENDIAN_8IN32;
1034
1035 /* 64-bit buffers. */
1036 case V_028C70_COLOR_16_16_16_16:
1037 return V_028C70_ENDIAN_8IN16;
1038
1039 case V_028C70_COLOR_32_32:
1040 return V_028C70_ENDIAN_8IN32;
1041
1042 /* 128-bit buffers. */
1043 case V_028C70_COLOR_32_32_32_32:
1044 return V_028C70_ENDIAN_8IN32;
1045 default:
1046 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1047 }
1048 } else {
1049 return V_028C70_ENDIAN_NONE;
1050 }
1051 }
1052
1053 /* Returns the size in bits of the widest component of a CB format */
1054 static unsigned si_colorformat_max_comp_size(uint32_t colorformat)
1055 {
1056 switch(colorformat) {
1057 case V_028C70_COLOR_4_4_4_4:
1058 return 4;
1059
1060 case V_028C70_COLOR_1_5_5_5:
1061 case V_028C70_COLOR_5_5_5_1:
1062 return 5;
1063
1064 case V_028C70_COLOR_5_6_5:
1065 return 6;
1066
1067 case V_028C70_COLOR_8:
1068 case V_028C70_COLOR_8_8:
1069 case V_028C70_COLOR_8_8_8_8:
1070 return 8;
1071
1072 case V_028C70_COLOR_10_10_10_2:
1073 case V_028C70_COLOR_2_10_10_10:
1074 return 10;
1075
1076 case V_028C70_COLOR_10_11_11:
1077 case V_028C70_COLOR_11_11_10:
1078 return 11;
1079
1080 case V_028C70_COLOR_16:
1081 case V_028C70_COLOR_16_16:
1082 case V_028C70_COLOR_16_16_16_16:
1083 return 16;
1084
1085 case V_028C70_COLOR_8_24:
1086 case V_028C70_COLOR_24_8:
1087 return 24;
1088
1089 case V_028C70_COLOR_32:
1090 case V_028C70_COLOR_32_32:
1091 case V_028C70_COLOR_32_32_32_32:
1092 case V_028C70_COLOR_X24_8_32_FLOAT:
1093 return 32;
1094 }
1095
1096 assert(!"Unknown maximum component size");
1097 return 0;
1098 }
1099
1100 static uint32_t si_translate_dbformat(enum pipe_format format)
1101 {
1102 switch (format) {
1103 //case PIPE_FORMAT_Z16_UNORM:
1104 // return V_028040_Z_16;
1105 case PIPE_FORMAT_Z24X8_UNORM:
1106 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1107 return V_028040_Z_24; /* XXX no longer supported on SI */
1108 case PIPE_FORMAT_Z32_FLOAT:
1109 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1110 return V_028040_Z_32_FLOAT;
1111 default:
1112 return V_028040_Z_INVALID;
1113 }
1114 }
1115
1116 /*
1117 * Texture translation
1118 */
1119
1120 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1121 enum pipe_format format,
1122 const struct util_format_description *desc,
1123 int first_non_void)
1124 {
1125 boolean uniform = TRUE;
1126 int i;
1127
1128 /* Colorspace (return non-RGB formats directly). */
1129 switch (desc->colorspace) {
1130 /* Depth stencil formats */
1131 case UTIL_FORMAT_COLORSPACE_ZS:
1132 switch (format) {
1133 case PIPE_FORMAT_Z16_UNORM:
1134 return V_008F14_IMG_DATA_FORMAT_16;
1135 case PIPE_FORMAT_X24S8_UINT:
1136 case PIPE_FORMAT_Z24X8_UNORM:
1137 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1138 return V_008F14_IMG_DATA_FORMAT_24_8;
1139 case PIPE_FORMAT_S8X24_UINT:
1140 case PIPE_FORMAT_X8Z24_UNORM:
1141 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1142 return V_008F14_IMG_DATA_FORMAT_8_24;
1143 case PIPE_FORMAT_S8_UINT:
1144 return V_008F14_IMG_DATA_FORMAT_8;
1145 case PIPE_FORMAT_Z32_FLOAT:
1146 return V_008F14_IMG_DATA_FORMAT_32;
1147 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1148 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1149 default:
1150 goto out_unknown;
1151 }
1152
1153 case UTIL_FORMAT_COLORSPACE_YUV:
1154 goto out_unknown; /* TODO */
1155
1156 case UTIL_FORMAT_COLORSPACE_SRGB:
1157 break;
1158
1159 default:
1160 break;
1161 }
1162
1163 /* TODO compressed formats */
1164
1165 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1166 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1167 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1168 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1169 }
1170
1171 /* R8G8Bx_SNORM - TODO CxV8U8 */
1172
1173 /* See whether the components are of the same size. */
1174 for (i = 1; i < desc->nr_channels; i++) {
1175 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1176 }
1177
1178 /* Non-uniform formats. */
1179 if (!uniform) {
1180 switch(desc->nr_channels) {
1181 case 3:
1182 if (desc->channel[0].size == 5 &&
1183 desc->channel[1].size == 6 &&
1184 desc->channel[2].size == 5) {
1185 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1186 }
1187 goto out_unknown;
1188 case 4:
1189 if (desc->channel[0].size == 5 &&
1190 desc->channel[1].size == 5 &&
1191 desc->channel[2].size == 5 &&
1192 desc->channel[3].size == 1) {
1193 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1194 }
1195 if (desc->channel[0].size == 10 &&
1196 desc->channel[1].size == 10 &&
1197 desc->channel[2].size == 10 &&
1198 desc->channel[3].size == 2) {
1199 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1200 }
1201 goto out_unknown;
1202 }
1203 goto out_unknown;
1204 }
1205
1206 if (first_non_void < 0 || first_non_void > 3)
1207 goto out_unknown;
1208
1209 /* uniform formats */
1210 switch (desc->channel[first_non_void].size) {
1211 case 4:
1212 switch (desc->nr_channels) {
1213 #if 0 /* Not supported for render targets */
1214 case 2:
1215 return V_008F14_IMG_DATA_FORMAT_4_4;
1216 #endif
1217 case 4:
1218 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1219 }
1220 break;
1221 case 8:
1222 switch (desc->nr_channels) {
1223 case 1:
1224 return V_008F14_IMG_DATA_FORMAT_8;
1225 case 2:
1226 return V_008F14_IMG_DATA_FORMAT_8_8;
1227 case 4:
1228 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1229 }
1230 break;
1231 case 16:
1232 switch (desc->nr_channels) {
1233 case 1:
1234 return V_008F14_IMG_DATA_FORMAT_16;
1235 case 2:
1236 return V_008F14_IMG_DATA_FORMAT_16_16;
1237 case 4:
1238 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1239 }
1240 break;
1241 case 32:
1242 switch (desc->nr_channels) {
1243 case 1:
1244 return V_008F14_IMG_DATA_FORMAT_32;
1245 case 2:
1246 return V_008F14_IMG_DATA_FORMAT_32_32;
1247 #if 0 /* Not supported for render targets */
1248 case 3:
1249 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1250 #endif
1251 case 4:
1252 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1253 }
1254 }
1255
1256 out_unknown:
1257 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1258 return ~0;
1259 }
1260
1261 static unsigned si_tex_wrap(unsigned wrap)
1262 {
1263 switch (wrap) {
1264 default:
1265 case PIPE_TEX_WRAP_REPEAT:
1266 return V_008F30_SQ_TEX_WRAP;
1267 case PIPE_TEX_WRAP_CLAMP:
1268 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1269 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1270 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1271 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1272 return V_008F30_SQ_TEX_CLAMP_BORDER;
1273 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1274 return V_008F30_SQ_TEX_MIRROR;
1275 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1276 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1277 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1278 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1279 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1280 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1281 }
1282 }
1283
1284 static unsigned si_tex_filter(unsigned filter)
1285 {
1286 switch (filter) {
1287 default:
1288 case PIPE_TEX_FILTER_NEAREST:
1289 return V_008F38_SQ_TEX_XY_FILTER_POINT;
1290 case PIPE_TEX_FILTER_LINEAR:
1291 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
1292 }
1293 }
1294
1295 static unsigned si_tex_mipfilter(unsigned filter)
1296 {
1297 switch (filter) {
1298 case PIPE_TEX_MIPFILTER_NEAREST:
1299 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1300 case PIPE_TEX_MIPFILTER_LINEAR:
1301 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1302 default:
1303 case PIPE_TEX_MIPFILTER_NONE:
1304 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1305 }
1306 }
1307
1308 static unsigned si_tex_compare(unsigned compare)
1309 {
1310 switch (compare) {
1311 default:
1312 case PIPE_FUNC_NEVER:
1313 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1314 case PIPE_FUNC_LESS:
1315 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1316 case PIPE_FUNC_EQUAL:
1317 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1318 case PIPE_FUNC_LEQUAL:
1319 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1320 case PIPE_FUNC_GREATER:
1321 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1322 case PIPE_FUNC_NOTEQUAL:
1323 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1324 case PIPE_FUNC_GEQUAL:
1325 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1326 case PIPE_FUNC_ALWAYS:
1327 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1328 }
1329 }
1330
1331 static unsigned si_tex_dim(unsigned dim)
1332 {
1333 switch (dim) {
1334 default:
1335 case PIPE_TEXTURE_1D:
1336 return V_008F1C_SQ_RSRC_IMG_1D;
1337 case PIPE_TEXTURE_1D_ARRAY:
1338 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1339 case PIPE_TEXTURE_2D:
1340 case PIPE_TEXTURE_RECT:
1341 return V_008F1C_SQ_RSRC_IMG_2D;
1342 case PIPE_TEXTURE_2D_ARRAY:
1343 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1344 case PIPE_TEXTURE_3D:
1345 return V_008F1C_SQ_RSRC_IMG_3D;
1346 case PIPE_TEXTURE_CUBE:
1347 return V_008F1C_SQ_RSRC_IMG_CUBE;
1348 }
1349 }
1350
1351 /*
1352 * Format support testing
1353 */
1354
1355 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1356 {
1357 return si_translate_texformat(screen, format, util_format_description(format),
1358 util_format_get_first_non_void_channel(format)) != ~0U;
1359 }
1360
1361 static uint32_t si_translate_vertexformat(struct pipe_screen *screen,
1362 enum pipe_format format,
1363 const struct util_format_description *desc,
1364 int first_non_void)
1365 {
1366 unsigned type = desc->channel[first_non_void].type;
1367 int i;
1368
1369 if (type == UTIL_FORMAT_TYPE_FIXED)
1370 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1371
1372 /* See whether the components are of the same size. */
1373 for (i = 0; i < desc->nr_channels; i++) {
1374 if (desc->channel[first_non_void].size != desc->channel[i].size)
1375 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1376 }
1377
1378 switch (desc->channel[first_non_void].size) {
1379 case 8:
1380 switch (desc->nr_channels) {
1381 case 1:
1382 return V_008F0C_BUF_DATA_FORMAT_8;
1383 case 2:
1384 return V_008F0C_BUF_DATA_FORMAT_8_8;
1385 case 3:
1386 case 4:
1387 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1388 }
1389 break;
1390 case 16:
1391 switch (desc->nr_channels) {
1392 case 1:
1393 return V_008F0C_BUF_DATA_FORMAT_16;
1394 case 2:
1395 return V_008F0C_BUF_DATA_FORMAT_16_16;
1396 case 3:
1397 case 4:
1398 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1399 }
1400 break;
1401 case 32:
1402 if (type != UTIL_FORMAT_TYPE_FLOAT)
1403 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1404
1405 switch (desc->nr_channels) {
1406 case 1:
1407 return V_008F0C_BUF_DATA_FORMAT_32;
1408 case 2:
1409 return V_008F0C_BUF_DATA_FORMAT_32_32;
1410 case 3:
1411 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1412 case 4:
1413 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1414 }
1415 break;
1416 }
1417
1418 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1419 }
1420
1421 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
1422 {
1423 const struct util_format_description *desc;
1424 int first_non_void;
1425 unsigned data_format;
1426
1427 desc = util_format_description(format);
1428 first_non_void = util_format_get_first_non_void_channel(format);
1429 data_format = si_translate_vertexformat(screen, format, desc, first_non_void);
1430 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
1431 }
1432
1433 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1434 {
1435 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1436 si_translate_colorswap(format) != ~0U;
1437 }
1438
1439 static bool si_is_zs_format_supported(enum pipe_format format)
1440 {
1441 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1442 }
1443
1444 boolean si_is_format_supported(struct pipe_screen *screen,
1445 enum pipe_format format,
1446 enum pipe_texture_target target,
1447 unsigned sample_count,
1448 unsigned usage)
1449 {
1450 unsigned retval = 0;
1451
1452 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1453 R600_ERR("r600: unsupported texture type %d\n", target);
1454 return FALSE;
1455 }
1456
1457 if (!util_format_is_supported(format, usage))
1458 return FALSE;
1459
1460 /* Multisample */
1461 if (sample_count > 1)
1462 return FALSE;
1463
1464 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
1465 si_is_sampler_format_supported(screen, format)) {
1466 retval |= PIPE_BIND_SAMPLER_VIEW;
1467 }
1468
1469 if ((usage & (PIPE_BIND_RENDER_TARGET |
1470 PIPE_BIND_DISPLAY_TARGET |
1471 PIPE_BIND_SCANOUT |
1472 PIPE_BIND_SHARED)) &&
1473 si_is_colorbuffer_format_supported(format)) {
1474 retval |= usage &
1475 (PIPE_BIND_RENDER_TARGET |
1476 PIPE_BIND_DISPLAY_TARGET |
1477 PIPE_BIND_SCANOUT |
1478 PIPE_BIND_SHARED);
1479 }
1480
1481 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1482 si_is_zs_format_supported(format)) {
1483 retval |= PIPE_BIND_DEPTH_STENCIL;
1484 }
1485
1486 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
1487 si_is_vertex_format_supported(screen, format)) {
1488 retval |= PIPE_BIND_VERTEX_BUFFER;
1489 }
1490
1491 if (usage & PIPE_BIND_TRANSFER_READ)
1492 retval |= PIPE_BIND_TRANSFER_READ;
1493 if (usage & PIPE_BIND_TRANSFER_WRITE)
1494 retval |= PIPE_BIND_TRANSFER_WRITE;
1495
1496 return retval == usage;
1497 }
1498
1499 /*
1500 * framebuffer handling
1501 */
1502
1503 static void si_cb(struct r600_context *rctx, struct si_pm4_state *pm4,
1504 const struct pipe_framebuffer_state *state, int cb)
1505 {
1506 struct r600_resource_texture *rtex;
1507 struct r600_surface *surf;
1508 unsigned level = state->cbufs[cb]->u.tex.level;
1509 unsigned pitch, slice;
1510 unsigned color_info, color_attrib;
1511 unsigned format, swap, ntype, endian;
1512 uint64_t offset;
1513 unsigned blocksize;
1514 const struct util_format_description *desc;
1515 int i;
1516 unsigned blend_clamp = 0, blend_bypass = 0;
1517 unsigned max_comp_size;
1518
1519 surf = (struct r600_surface *)state->cbufs[cb];
1520 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
1521 blocksize = util_format_get_blocksize(rtex->real_format);
1522
1523 if (rtex->depth)
1524 rctx->have_depth_fb = TRUE;
1525
1526 if (rtex->depth && !rtex->is_flushing_texture) {
1527 r600_texture_depth_flush(&rctx->context, state->cbufs[cb]->texture, TRUE);
1528 rtex = rtex->flushed_depth_texture;
1529 }
1530
1531 offset = rtex->surface.level[level].offset;
1532 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1533 offset += rtex->surface.level[level].slice_size *
1534 state->cbufs[cb]->u.tex.first_layer;
1535 }
1536 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1537 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1538 if (slice) {
1539 slice = slice - 1;
1540 }
1541
1542 color_attrib = S_028C74_TILE_MODE_INDEX(8);
1543 switch (rtex->surface.level[level].mode) {
1544 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1545 color_attrib = S_028C74_TILE_MODE_INDEX(8);
1546 break;
1547 case RADEON_SURF_MODE_1D:
1548 color_attrib = S_028C74_TILE_MODE_INDEX(9);
1549 break;
1550 case RADEON_SURF_MODE_2D:
1551 if (rtex->resource.b.b.bind & PIPE_BIND_SCANOUT) {
1552 switch (blocksize) {
1553 case 1:
1554 color_attrib = S_028C74_TILE_MODE_INDEX(10);
1555 break;
1556 case 2:
1557 color_attrib = S_028C74_TILE_MODE_INDEX(11);
1558 break;
1559 case 4:
1560 color_attrib = S_028C74_TILE_MODE_INDEX(12);
1561 break;
1562 }
1563 break;
1564 } else switch (blocksize) {
1565 case 1:
1566 color_attrib = S_028C74_TILE_MODE_INDEX(14);
1567 break;
1568 case 2:
1569 color_attrib = S_028C74_TILE_MODE_INDEX(15);
1570 break;
1571 case 4:
1572 color_attrib = S_028C74_TILE_MODE_INDEX(16);
1573 break;
1574 case 8:
1575 color_attrib = S_028C74_TILE_MODE_INDEX(17);
1576 break;
1577 default:
1578 color_attrib = S_028C74_TILE_MODE_INDEX(13);
1579 }
1580 break;
1581 }
1582
1583 desc = util_format_description(surf->base.format);
1584 for (i = 0; i < 4; i++) {
1585 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1586 break;
1587 }
1588 }
1589 if (desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1590 ntype = V_028C70_NUMBER_FLOAT;
1591 } else {
1592 ntype = V_028C70_NUMBER_UNORM;
1593 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1594 ntype = V_028C70_NUMBER_SRGB;
1595 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1596 if (desc->channel[i].normalized)
1597 ntype = V_028C70_NUMBER_SNORM;
1598 else if (desc->channel[i].pure_integer)
1599 ntype = V_028C70_NUMBER_SINT;
1600 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1601 if (desc->channel[i].normalized)
1602 ntype = V_028C70_NUMBER_UNORM;
1603 else if (desc->channel[i].pure_integer)
1604 ntype = V_028C70_NUMBER_UINT;
1605 }
1606 }
1607
1608 format = si_translate_colorformat(surf->base.format);
1609 if (format == V_028C70_COLOR_INVALID) {
1610 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
1611 }
1612 swap = si_translate_colorswap(surf->base.format);
1613 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1614 endian = V_028C70_ENDIAN_NONE;
1615 } else {
1616 endian = si_colorformat_endian_swap(format);
1617 }
1618
1619 /* blend clamp should be set for all NORM/SRGB types */
1620 if (ntype == V_028C70_NUMBER_UNORM ||
1621 ntype == V_028C70_NUMBER_SNORM ||
1622 ntype == V_028C70_NUMBER_SRGB)
1623 blend_clamp = 1;
1624
1625 /* set blend bypass according to docs if SINT/UINT or
1626 8/24 COLOR variants */
1627 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1628 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1629 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1630 blend_clamp = 0;
1631 blend_bypass = 1;
1632 }
1633
1634 color_info = S_028C70_FORMAT(format) |
1635 S_028C70_COMP_SWAP(swap) |
1636 S_028C70_BLEND_CLAMP(blend_clamp) |
1637 S_028C70_BLEND_BYPASS(blend_bypass) |
1638 S_028C70_NUMBER_TYPE(ntype) |
1639 S_028C70_ENDIAN(endian);
1640
1641 offset += r600_resource_va(rctx->context.screen, state->cbufs[cb]->texture);
1642 offset >>= 8;
1643
1644 /* FIXME handle enabling of CB beyond BASE8 which has different offset */
1645 si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE);
1646 si_pm4_set_reg(pm4, R_028C60_CB_COLOR0_BASE + cb * 0x3C, offset);
1647 si_pm4_set_reg(pm4, R_028C64_CB_COLOR0_PITCH + cb * 0x3C, S_028C64_TILE_MAX(pitch));
1648 si_pm4_set_reg(pm4, R_028C68_CB_COLOR0_SLICE + cb * 0x3C, S_028C68_TILE_MAX(slice));
1649
1650 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1651 si_pm4_set_reg(pm4, R_028C6C_CB_COLOR0_VIEW + cb * 0x3C, 0x00000000);
1652 } else {
1653 si_pm4_set_reg(pm4, R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1654 S_028C6C_SLICE_START(state->cbufs[cb]->u.tex.first_layer) |
1655 S_028C6C_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer));
1656 }
1657 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + cb * 0x3C, color_info);
1658 si_pm4_set_reg(pm4, R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C, color_attrib);
1659
1660 /* Determine pixel shader export format */
1661 max_comp_size = si_colorformat_max_comp_size(format);
1662 if (ntype == V_028C70_NUMBER_SRGB ||
1663 ((ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM) &&
1664 max_comp_size <= 10) ||
1665 (ntype == V_028C70_NUMBER_FLOAT && max_comp_size <= 16)) {
1666 rctx->export_16bpc |= 1 << cb;
1667 rctx->spi_shader_col_format |= V_028714_SPI_SHADER_FP16_ABGR << (4 * cb);
1668 } else
1669 rctx->spi_shader_col_format |= V_028714_SPI_SHADER_32_ABGR << (4 * cb);
1670 }
1671
1672 static void si_db(struct r600_context *rctx, struct si_pm4_state *pm4,
1673 const struct pipe_framebuffer_state *state)
1674 {
1675 struct r600_resource_texture *rtex;
1676 struct r600_surface *surf;
1677 unsigned level, pitch, slice, format;
1678 uint32_t z_info, s_info;
1679 uint64_t z_offs, s_offs;
1680
1681 if (state->zsbuf == NULL) {
1682 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, S_028040_FORMAT(V_028040_Z_INVALID));
1683 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, S_028044_FORMAT(V_028044_STENCIL_INVALID));
1684 return;
1685 }
1686
1687 surf = (struct r600_surface *)state->zsbuf;
1688 level = surf->base.u.tex.level;
1689 rtex = (struct r600_resource_texture*)surf->base.texture;
1690
1691 format = si_translate_dbformat(rtex->real_format);
1692
1693 if (format == V_028040_Z_INVALID) {
1694 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->real_format);
1695 }
1696
1697 z_offs = r600_resource_va(rctx->context.screen, surf->base.texture);
1698 z_offs += rtex->surface.level[level].offset;
1699
1700 s_offs = r600_resource_va(rctx->context.screen, surf->base.texture);
1701 s_offs += rtex->surface.stencil_offset;
1702 z_offs += rtex->surface.level[level].offset / 4;
1703
1704 z_offs >>= 8;
1705 s_offs >>= 8;
1706
1707 pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
1708 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1709 if (slice) {
1710 slice = slice - 1;
1711 }
1712
1713 z_info = S_028040_FORMAT(format);
1714 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
1715 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
1716 else
1717 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
1718
1719 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_1D) {
1720 z_info |= S_028040_TILE_MODE_INDEX(4);
1721 s_info |= S_028044_TILE_MODE_INDEX(4);
1722
1723 } else if (rtex->surface.level[level].mode == RADEON_SURF_MODE_2D) {
1724 switch (format) {
1725 case V_028040_Z_16:
1726 z_info |= S_028040_TILE_MODE_INDEX(5);
1727 s_info |= S_028044_TILE_MODE_INDEX(5);
1728 break;
1729 case V_028040_Z_24:
1730 case V_028040_Z_32_FLOAT:
1731 z_info |= S_028040_TILE_MODE_INDEX(6);
1732 s_info |= S_028044_TILE_MODE_INDEX(6);
1733 break;
1734 default:
1735 z_info |= S_028040_TILE_MODE_INDEX(7);
1736 s_info |= S_028044_TILE_MODE_INDEX(7);
1737 }
1738
1739 } else {
1740 R600_ERR("Invalid DB tiling mode %d!\n",
1741 rtex->surface.level[level].mode);
1742 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, S_028040_FORMAT(V_028040_Z_INVALID));
1743 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, S_028044_FORMAT(V_028044_STENCIL_INVALID));
1744 return;
1745 }
1746
1747 si_pm4_set_reg(pm4, R_028008_DB_DEPTH_VIEW,
1748 S_028008_SLICE_START(state->zsbuf->u.tex.first_layer) |
1749 S_028008_SLICE_MAX(state->zsbuf->u.tex.last_layer));
1750
1751 si_pm4_set_reg(pm4, R_02803C_DB_DEPTH_INFO, S_02803C_ADDR5_SWIZZLE_MASK(1));
1752 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, z_info);
1753 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, s_info);
1754
1755 si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE);
1756 si_pm4_set_reg(pm4, R_028048_DB_Z_READ_BASE, z_offs);
1757 si_pm4_set_reg(pm4, R_02804C_DB_STENCIL_READ_BASE, s_offs);
1758 si_pm4_set_reg(pm4, R_028050_DB_Z_WRITE_BASE, z_offs);
1759 si_pm4_set_reg(pm4, R_028054_DB_STENCIL_WRITE_BASE, s_offs);
1760
1761 si_pm4_set_reg(pm4, R_028058_DB_DEPTH_SIZE, S_028058_PITCH_TILE_MAX(pitch));
1762 si_pm4_set_reg(pm4, R_02805C_DB_DEPTH_SLICE, S_02805C_SLICE_TILE_MAX(slice));
1763 }
1764
1765 static void si_set_framebuffer_state(struct pipe_context *ctx,
1766 const struct pipe_framebuffer_state *state)
1767 {
1768 struct r600_context *rctx = (struct r600_context *)ctx;
1769 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
1770 uint32_t shader_mask, tl, br;
1771 int tl_x, tl_y, br_x, br_y;
1772
1773 if (pm4 == NULL)
1774 return;
1775
1776 si_pm4_inval_fb_cache(pm4, state->nr_cbufs);
1777
1778 if (state->zsbuf)
1779 si_pm4_inval_zsbuf_cache(pm4);
1780
1781 util_copy_framebuffer_state(&rctx->framebuffer, state);
1782
1783 /* build states */
1784 rctx->have_depth_fb = 0;
1785 rctx->export_16bpc = 0;
1786 rctx->spi_shader_col_format = 0;
1787 for (int i = 0; i < state->nr_cbufs; i++) {
1788 si_cb(rctx, pm4, state, i);
1789 }
1790 assert(!(rctx->export_16bpc & ~0xff));
1791 si_db(rctx, pm4, state);
1792
1793 shader_mask = 0;
1794 for (int i = 0; i < state->nr_cbufs; i++) {
1795 shader_mask |= 0xf << (i * 4);
1796 }
1797 tl_x = 0;
1798 tl_y = 0;
1799 br_x = state->width;
1800 br_y = state->height;
1801
1802 tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
1803 br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
1804
1805 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, tl);
1806 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR, br);
1807 si_pm4_set_reg(pm4, R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl);
1808 si_pm4_set_reg(pm4, R_028254_PA_SC_VPORT_SCISSOR_0_BR, br);
1809 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, tl);
1810 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR, br);
1811 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, tl);
1812 si_pm4_set_reg(pm4, R_028208_PA_SC_WINDOW_SCISSOR_BR, br);
1813 si_pm4_set_reg(pm4, R_028200_PA_SC_WINDOW_OFFSET, 0x00000000);
1814 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
1815 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, shader_mask);
1816 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT,
1817 rctx->spi_shader_col_format);
1818 si_pm4_set_reg(pm4, R_028BE0_PA_SC_AA_CONFIG, 0x00000000);
1819
1820 si_pm4_set_state(rctx, framebuffer, pm4);
1821 si_update_fb_rs_state(rctx);
1822 si_update_fb_blend_state(rctx);
1823 }
1824
1825 /*
1826 * shaders
1827 */
1828
1829 /* Compute the key for the hw shader variant */
1830 static INLINE struct si_shader_key si_shader_selector_key(struct pipe_context *ctx,
1831 struct si_pipe_shader_selector *sel)
1832 {
1833 struct r600_context *rctx = (struct r600_context *)ctx;
1834 struct si_shader_key key;
1835 memset(&key, 0, sizeof(key));
1836
1837 if (sel->type == PIPE_SHADER_FRAGMENT) {
1838 if (sel->fs_write_all)
1839 key.nr_cbufs = rctx->framebuffer.nr_cbufs;
1840 key.export_16bpc = rctx->export_16bpc;
1841 if (rctx->queued.named.rasterizer) {
1842 key.color_two_side = rctx->queued.named.rasterizer->two_side;
1843 /*key.flatshade = rctx->queued.named.rasterizer->flatshade;*/
1844 }
1845 if (rctx->queued.named.dsa) {
1846 key.alpha_func = rctx->queued.named.dsa->alpha_func;
1847 key.alpha_ref = rctx->queued.named.dsa->alpha_ref;
1848 } else {
1849 key.alpha_func = PIPE_FUNC_ALWAYS;
1850 }
1851 }
1852
1853 return key;
1854 }
1855
1856 /* Select the hw shader variant depending on the current state.
1857 * (*dirty) is set to 1 if current variant was changed */
1858 int si_shader_select(struct pipe_context *ctx,
1859 struct si_pipe_shader_selector *sel,
1860 unsigned *dirty)
1861 {
1862 struct si_shader_key key;
1863 struct si_pipe_shader * shader = NULL;
1864 int r;
1865
1866 key = si_shader_selector_key(ctx, sel);
1867
1868 /* Check if we don't need to change anything.
1869 * This path is also used for most shaders that don't need multiple
1870 * variants, it will cost just a computation of the key and this
1871 * test. */
1872 if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
1873 return 0;
1874 }
1875
1876 /* lookup if we have other variants in the list */
1877 if (sel->num_shaders > 1) {
1878 struct si_pipe_shader *p = sel->current, *c = p->next_variant;
1879
1880 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
1881 p = c;
1882 c = c->next_variant;
1883 }
1884
1885 if (c) {
1886 p->next_variant = c->next_variant;
1887 shader = c;
1888 }
1889 }
1890
1891 if (unlikely(!shader)) {
1892 shader = CALLOC(1, sizeof(struct si_pipe_shader));
1893 shader->selector = sel;
1894
1895 r = si_pipe_shader_create(ctx, shader, key);
1896 if (unlikely(r)) {
1897 R600_ERR("Failed to build shader variant (type=%u) %d\n",
1898 sel->type, r);
1899 sel->current = NULL;
1900 return r;
1901 }
1902
1903 /* We don't know the value of fs_write_all property until we built
1904 * at least one variant, so we may need to recompute the key (include
1905 * rctx->framebuffer.nr_cbufs) after building first variant. */
1906 if (sel->type == PIPE_SHADER_FRAGMENT &&
1907 sel->num_shaders == 0 &&
1908 shader->shader.fs_write_all) {
1909 sel->fs_write_all = 1;
1910 key = si_shader_selector_key(ctx, sel);
1911 }
1912
1913 shader->key = key;
1914 sel->num_shaders++;
1915 }
1916
1917 if (dirty)
1918 *dirty = 1;
1919
1920 shader->next_variant = sel->current;
1921 sel->current = shader;
1922
1923 return 0;
1924 }
1925
1926 static void *si_create_shader_state(struct pipe_context *ctx,
1927 const struct pipe_shader_state *state,
1928 unsigned pipe_shader_type)
1929 {
1930 struct si_pipe_shader_selector *sel = CALLOC_STRUCT(si_pipe_shader_selector);
1931 int r;
1932
1933 sel->type = pipe_shader_type;
1934 sel->tokens = tgsi_dup_tokens(state->tokens);
1935 sel->so = state->stream_output;
1936
1937 r = si_shader_select(ctx, sel, NULL);
1938 if (r) {
1939 free(sel);
1940 return NULL;
1941 }
1942
1943 return sel;
1944 }
1945
1946 static void *si_create_fs_state(struct pipe_context *ctx,
1947 const struct pipe_shader_state *state)
1948 {
1949 return si_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
1950 }
1951
1952 static void *si_create_vs_state(struct pipe_context *ctx,
1953 const struct pipe_shader_state *state)
1954 {
1955 return si_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
1956 }
1957
1958 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
1959 {
1960 struct r600_context *rctx = (struct r600_context *)ctx;
1961 struct si_pipe_shader_selector *sel = state;
1962
1963 if (rctx->vs_shader == sel)
1964 return;
1965
1966 rctx->vs_shader = sel;
1967
1968 if (sel && sel->current)
1969 si_pm4_bind_state(rctx, vs, sel->current->pm4);
1970 else
1971 si_pm4_bind_state(rctx, vs, rctx->dummy_pixel_shader->pm4);
1972 }
1973
1974 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
1975 {
1976 struct r600_context *rctx = (struct r600_context *)ctx;
1977 struct si_pipe_shader_selector *sel = state;
1978
1979 if (rctx->ps_shader == sel)
1980 return;
1981
1982 rctx->ps_shader = sel;
1983
1984 if (sel && sel->current)
1985 si_pm4_bind_state(rctx, ps, sel->current->pm4);
1986 else
1987 si_pm4_bind_state(rctx, ps, rctx->dummy_pixel_shader->pm4);
1988 }
1989
1990 static void si_delete_shader_selector(struct pipe_context *ctx,
1991 struct si_pipe_shader_selector *sel)
1992 {
1993 struct r600_context *rctx = (struct r600_context *)ctx;
1994 struct si_pipe_shader *p = sel->current, *c;
1995
1996 while (p) {
1997 c = p->next_variant;
1998 si_pm4_delete_state(rctx, vs, p->pm4);
1999 si_pipe_shader_destroy(ctx, p);
2000 free(p);
2001 p = c;
2002 }
2003
2004 free(sel->tokens);
2005 free(sel);
2006 }
2007
2008 static void si_delete_vs_shader(struct pipe_context *ctx, void *state)
2009 {
2010 struct r600_context *rctx = (struct r600_context *)ctx;
2011 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state;
2012
2013 if (rctx->vs_shader == sel) {
2014 rctx->vs_shader = NULL;
2015 }
2016
2017 si_delete_shader_selector(ctx, sel);
2018 }
2019
2020 static void si_delete_ps_shader(struct pipe_context *ctx, void *state)
2021 {
2022 struct r600_context *rctx = (struct r600_context *)ctx;
2023 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state;
2024
2025 if (rctx->ps_shader == sel) {
2026 rctx->ps_shader = NULL;
2027 }
2028
2029 si_delete_shader_selector(ctx, sel);
2030 }
2031
2032 /*
2033 * Samplers
2034 */
2035
2036 static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx,
2037 struct pipe_resource *texture,
2038 const struct pipe_sampler_view *state)
2039 {
2040 struct si_pipe_sampler_view *view = CALLOC_STRUCT(si_pipe_sampler_view);
2041 struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
2042 const struct util_format_description *desc = util_format_description(state->format);
2043 unsigned blocksize = util_format_get_blocksize(tmp->real_format);
2044 unsigned format, num_format, /*endian,*/ tiling_index;
2045 uint32_t pitch = 0;
2046 unsigned char state_swizzle[4], swizzle[4];
2047 unsigned height, depth, width;
2048 int first_non_void;
2049 uint64_t va;
2050
2051 if (view == NULL)
2052 return NULL;
2053
2054 /* initialize base object */
2055 view->base = *state;
2056 view->base.texture = NULL;
2057 pipe_reference(NULL, &texture->reference);
2058 view->base.texture = texture;
2059 view->base.reference.count = 1;
2060 view->base.context = ctx;
2061
2062 state_swizzle[0] = state->swizzle_r;
2063 state_swizzle[1] = state->swizzle_g;
2064 state_swizzle[2] = state->swizzle_b;
2065 state_swizzle[3] = state->swizzle_a;
2066 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2067
2068 first_non_void = util_format_get_first_non_void_channel(state->format);
2069 switch (desc->channel[first_non_void].type) {
2070 case UTIL_FORMAT_TYPE_FLOAT:
2071 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2072 break;
2073 case UTIL_FORMAT_TYPE_SIGNED:
2074 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2075 break;
2076 case UTIL_FORMAT_TYPE_UNSIGNED:
2077 default:
2078 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2079 }
2080
2081 format = si_translate_texformat(ctx->screen, state->format, desc, first_non_void);
2082 if (format == ~0) {
2083 format = 0;
2084 }
2085
2086 if (tmp->depth && !tmp->is_flushing_texture) {
2087 r600_texture_depth_flush(ctx, texture, TRUE);
2088 tmp = tmp->flushed_depth_texture;
2089 texture = &tmp->resource.b.b;
2090 }
2091
2092 view->resource = &tmp->resource;
2093
2094 /* not supported any more */
2095 //endian = si_colorformat_endian_swap(format);
2096
2097 width = tmp->surface.level[0].npix_x;
2098 height = tmp->surface.level[0].npix_y;
2099 depth = tmp->surface.level[0].npix_z;
2100 pitch = tmp->surface.level[0].nblk_x * util_format_get_blockwidth(state->format);
2101
2102 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
2103 height = 1;
2104 depth = texture->array_size;
2105 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
2106 depth = texture->array_size;
2107 }
2108
2109 tiling_index = 8;
2110 switch (tmp->surface.level[0].mode) {
2111 case RADEON_SURF_MODE_LINEAR_ALIGNED:
2112 tiling_index = 8;
2113 break;
2114 case RADEON_SURF_MODE_1D:
2115 tiling_index = 9;
2116 break;
2117 case RADEON_SURF_MODE_2D:
2118 if (tmp->resource.b.b.bind & PIPE_BIND_SCANOUT) {
2119 switch (blocksize) {
2120 case 1:
2121 tiling_index = 10;
2122 break;
2123 case 2:
2124 tiling_index = 11;
2125 break;
2126 case 4:
2127 tiling_index = 12;
2128 break;
2129 }
2130 break;
2131 } else switch (blocksize) {
2132 case 1:
2133 tiling_index = 14;
2134 break;
2135 case 2:
2136 tiling_index = 15;
2137 break;
2138 case 4:
2139 tiling_index = 16;
2140 break;
2141 case 8:
2142 tiling_index = 17;
2143 break;
2144 default:
2145 tiling_index = 13;
2146 }
2147 break;
2148 }
2149
2150 va = r600_resource_va(ctx->screen, texture);
2151 va += tmp->surface.level[0].offset;
2152 view->state[0] = va >> 8;
2153 view->state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) |
2154 S_008F14_DATA_FORMAT(format) |
2155 S_008F14_NUM_FORMAT(num_format));
2156 view->state[2] = (S_008F18_WIDTH(width - 1) |
2157 S_008F18_HEIGHT(height - 1));
2158 view->state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2159 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2160 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2161 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2162 S_008F1C_BASE_LEVEL(state->u.tex.first_level) |
2163 S_008F1C_LAST_LEVEL(state->u.tex.last_level) |
2164 S_008F1C_TILING_INDEX(tiling_index) |
2165 S_008F1C_POW2_PAD(texture->last_level > 0) |
2166 S_008F1C_TYPE(si_tex_dim(texture->target)));
2167 view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
2168 view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2169 S_008F24_LAST_ARRAY(state->u.tex.last_layer));
2170 view->state[6] = 0;
2171 view->state[7] = 0;
2172
2173 return &view->base;
2174 }
2175
2176 static void si_sampler_view_destroy(struct pipe_context *ctx,
2177 struct pipe_sampler_view *state)
2178 {
2179 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
2180
2181 pipe_resource_reference(&state->texture, NULL);
2182 FREE(resource);
2183 }
2184
2185 static void *si_create_sampler_state(struct pipe_context *ctx,
2186 const struct pipe_sampler_state *state)
2187 {
2188 struct si_pipe_sampler_state *rstate = CALLOC_STRUCT(si_pipe_sampler_state);
2189 union util_color uc;
2190 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
2191 unsigned border_color_type;
2192
2193 if (rstate == NULL) {
2194 return NULL;
2195 }
2196
2197 util_pack_color(state->border_color.f, PIPE_FORMAT_A8R8G8B8_UNORM, &uc);
2198 switch (uc.ui) {
2199 case 0x000000FF:
2200 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
2201 break;
2202 case 0x00000000:
2203 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
2204 break;
2205 case 0xFFFFFFFF:
2206 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
2207 break;
2208 default: /* Use border color pointer */
2209 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
2210 }
2211
2212 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
2213 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
2214 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
2215 (state->max_anisotropy & 0x7) << 9 | /* XXX */
2216 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
2217 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
2218 aniso_flag_offset << 16 | /* XXX */
2219 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map));
2220 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
2221 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
2222 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
2223 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter)) |
2224 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter)) |
2225 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)));
2226 rstate->val[3] = S_008F3C_BORDER_COLOR_TYPE(border_color_type);
2227
2228 if (border_color_type == V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2229 memcpy(rstate->border_color, state->border_color.f,
2230 sizeof(rstate->border_color));
2231 }
2232
2233 return rstate;
2234 }
2235
2236 static struct si_pm4_state *si_set_sampler_view(struct r600_context *rctx,
2237 unsigned count,
2238 struct pipe_sampler_view **views,
2239 struct r600_textures_info *samplers,
2240 unsigned user_data_reg)
2241 {
2242 struct si_pipe_sampler_view **resource = (struct si_pipe_sampler_view **)views;
2243 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
2244 int i, j;
2245 int has_depth = 0;
2246
2247 if (!count)
2248 goto out;
2249
2250 si_pm4_inval_texture_cache(pm4);
2251
2252 si_pm4_sh_data_begin(pm4);
2253 for (i = 0; i < count; i++) {
2254 pipe_sampler_view_reference(
2255 (struct pipe_sampler_view **)&samplers->views[i],
2256 views[i]);
2257
2258 if (views[i])
2259 si_pm4_add_bo(pm4, resource[i]->resource, RADEON_USAGE_READ);
2260
2261 for (j = 0; j < Elements(resource[i]->state); ++j) {
2262 si_pm4_sh_data_add(pm4, resource[i] ? resource[i]->state[j] : 0);
2263 }
2264 }
2265
2266 for (i = count; i < NUM_TEX_UNITS; i++) {
2267 if (samplers->views[i])
2268 pipe_sampler_view_reference((struct pipe_sampler_view **)&samplers->views[i], NULL);
2269 }
2270
2271 si_pm4_sh_data_end(pm4, user_data_reg, SI_SGPR_RESOURCE);
2272
2273 out:
2274 rctx->have_depth_texture = has_depth;
2275 rctx->ps_samplers.n_views = count;
2276 return pm4;
2277 }
2278
2279 static void si_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
2280 struct pipe_sampler_view **views)
2281 {
2282 struct r600_context *rctx = (struct r600_context *)ctx;
2283 struct si_pm4_state *pm4;
2284
2285 pm4 = si_set_sampler_view(rctx, count, views, &rctx->vs_samplers,
2286 R_00B130_SPI_SHADER_USER_DATA_VS_0);
2287 si_pm4_set_state(rctx, vs_sampler_views, pm4);
2288 }
2289
2290 static void si_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
2291 struct pipe_sampler_view **views)
2292 {
2293 struct r600_context *rctx = (struct r600_context *)ctx;
2294 struct si_pm4_state *pm4;
2295
2296 pm4 = si_set_sampler_view(rctx, count, views, &rctx->ps_samplers,
2297 R_00B030_SPI_SHADER_USER_DATA_PS_0);
2298 si_pm4_set_state(rctx, ps_sampler_views, pm4);
2299 }
2300
2301 static struct si_pm4_state *si_bind_sampler(struct r600_context *rctx, unsigned count,
2302 void **states,
2303 struct r600_textures_info *samplers,
2304 unsigned user_data_reg)
2305 {
2306 struct si_pipe_sampler_state **rstates = (struct si_pipe_sampler_state **)states;
2307 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
2308 uint32_t *border_color_table = NULL;
2309 int i, j;
2310
2311 if (!count)
2312 goto out;
2313
2314 si_pm4_inval_texture_cache(pm4);
2315
2316 si_pm4_sh_data_begin(pm4);
2317 for (i = 0; i < count; i++) {
2318 if (rstates[i] &&
2319 G_008F3C_BORDER_COLOR_TYPE(rstates[i]->val[3]) ==
2320 V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2321 if (!rctx->border_color_table ||
2322 ((rctx->border_color_offset + count - i) &
2323 C_008F3C_BORDER_COLOR_PTR)) {
2324 si_resource_reference(&rctx->border_color_table, NULL);
2325 rctx->border_color_offset = 0;
2326
2327 rctx->border_color_table =
2328 si_resource_create_custom(&rctx->screen->screen,
2329 PIPE_USAGE_STAGING,
2330 4096 * 4 * 4);
2331 }
2332
2333 if (!border_color_table) {
2334 border_color_table =
2335 rctx->ws->buffer_map(rctx->border_color_table->cs_buf,
2336 rctx->cs,
2337 PIPE_TRANSFER_WRITE |
2338 PIPE_TRANSFER_UNSYNCHRONIZED);
2339 }
2340
2341 for (j = 0; j < 4; j++) {
2342 union fi border_color;
2343
2344 border_color.f = rstates[i]->border_color[j];
2345 border_color_table[4 * rctx->border_color_offset + j] =
2346 util_le32_to_cpu(border_color.i);
2347 }
2348
2349 rstates[i]->val[3] &= C_008F3C_BORDER_COLOR_PTR;
2350 rstates[i]->val[3] |= S_008F3C_BORDER_COLOR_PTR(rctx->border_color_offset++);
2351 }
2352
2353 for (j = 0; j < Elements(rstates[i]->val); ++j) {
2354 si_pm4_sh_data_add(pm4, rstates[i] ? rstates[i]->val[j] : 0);
2355 }
2356 }
2357 si_pm4_sh_data_end(pm4, user_data_reg, SI_SGPR_SAMPLER);
2358
2359 if (border_color_table) {
2360 uint64_t va_offset =
2361 r600_resource_va(&rctx->screen->screen,
2362 (void*)rctx->border_color_table);
2363
2364 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, va_offset >> 8);
2365 rctx->ws->buffer_unmap(rctx->border_color_table->cs_buf);
2366 si_pm4_add_bo(pm4, rctx->border_color_table, RADEON_USAGE_READ);
2367 }
2368
2369 memcpy(samplers->samplers, states, sizeof(void*) * count);
2370
2371 out:
2372 samplers->n_samplers = count;
2373 return pm4;
2374 }
2375
2376 static void si_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
2377 {
2378 struct r600_context *rctx = (struct r600_context *)ctx;
2379 struct si_pm4_state *pm4;
2380
2381 pm4 = si_bind_sampler(rctx, count, states, &rctx->vs_samplers,
2382 R_00B130_SPI_SHADER_USER_DATA_VS_0);
2383 si_pm4_set_state(rctx, vs_sampler, pm4);
2384 }
2385
2386 static void si_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
2387 {
2388 struct r600_context *rctx = (struct r600_context *)ctx;
2389 struct si_pm4_state *pm4;
2390
2391 pm4 = si_bind_sampler(rctx, count, states, &rctx->ps_samplers,
2392 R_00B030_SPI_SHADER_USER_DATA_PS_0);
2393 si_pm4_set_state(rctx, ps_sampler, pm4);
2394 }
2395
2396 static void si_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
2397 {
2398 }
2399
2400 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
2401 {
2402 free(state);
2403 }
2404
2405 /*
2406 * Constants
2407 */
2408 static void si_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
2409 struct pipe_constant_buffer *cb)
2410 {
2411 struct r600_context *rctx = (struct r600_context *)ctx;
2412 struct si_resource *rbuffer = cb ? si_resource(cb->buffer) : NULL;
2413 struct si_pm4_state *pm4;
2414 uint64_t va_offset;
2415 uint32_t reg, offset;
2416
2417 /* Note that the state tracker can unbind constant buffers by
2418 * passing NULL here.
2419 */
2420 if (cb == NULL)
2421 return;
2422
2423 pm4 = CALLOC_STRUCT(si_pm4_state);
2424 si_pm4_inval_shader_cache(pm4);
2425
2426 if (cb->user_buffer)
2427 r600_upload_const_buffer(rctx, &rbuffer, cb->user_buffer, cb->buffer_size, &offset);
2428 else
2429 offset = 0;
2430 va_offset = r600_resource_va(ctx->screen, (void*)rbuffer);
2431 va_offset += offset;
2432
2433 si_pm4_add_bo(pm4, rbuffer, RADEON_USAGE_READ);
2434
2435 switch (shader) {
2436 case PIPE_SHADER_VERTEX:
2437 reg = R_00B130_SPI_SHADER_USER_DATA_VS_0 + SI_SGPR_CONST * 4;
2438 si_pm4_set_reg(pm4, reg, va_offset);
2439 si_pm4_set_reg(pm4, reg + 4, va_offset >> 32);
2440 si_pm4_set_state(rctx, vs_const, pm4);
2441 break;
2442
2443 case PIPE_SHADER_FRAGMENT:
2444 reg = R_00B030_SPI_SHADER_USER_DATA_PS_0 + SI_SGPR_CONST * 4;
2445 si_pm4_set_reg(pm4, reg, va_offset);
2446 si_pm4_set_reg(pm4, reg + 4, va_offset >> 32);
2447 si_pm4_set_state(rctx, ps_const, pm4);
2448 break;
2449
2450 default:
2451 R600_ERR("unsupported %d\n", shader);
2452 }
2453
2454 if (cb->buffer != &rbuffer->b.b)
2455 si_resource_reference(&rbuffer, NULL);
2456 }
2457
2458 /*
2459 * Vertex elements & buffers
2460 */
2461
2462 static void *si_create_vertex_elements(struct pipe_context *ctx,
2463 unsigned count,
2464 const struct pipe_vertex_element *elements)
2465 {
2466 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
2467 int i;
2468
2469 assert(count < PIPE_MAX_ATTRIBS);
2470 if (!v)
2471 return NULL;
2472
2473 v->count = count;
2474 for (i = 0; i < count; ++i) {
2475 const struct util_format_description *desc;
2476 unsigned data_format, num_format;
2477 int first_non_void;
2478
2479 desc = util_format_description(elements[i].src_format);
2480 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
2481 data_format = si_translate_vertexformat(ctx->screen, elements[i].src_format,
2482 desc, first_non_void);
2483
2484 switch (desc->channel[first_non_void].type) {
2485 case UTIL_FORMAT_TYPE_FIXED:
2486 num_format = V_008F0C_BUF_NUM_FORMAT_USCALED; /* XXX */
2487 break;
2488 case UTIL_FORMAT_TYPE_SIGNED:
2489 num_format = V_008F0C_BUF_NUM_FORMAT_SNORM;
2490 break;
2491 case UTIL_FORMAT_TYPE_UNSIGNED:
2492 num_format = V_008F0C_BUF_NUM_FORMAT_UNORM;
2493 break;
2494 case UTIL_FORMAT_TYPE_FLOAT:
2495 default:
2496 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2497 }
2498
2499 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2500 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2501 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2502 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2503 S_008F0C_NUM_FORMAT(num_format) |
2504 S_008F0C_DATA_FORMAT(data_format);
2505 }
2506 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
2507
2508 return v;
2509 }
2510
2511 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
2512 {
2513 struct r600_context *rctx = (struct r600_context *)ctx;
2514 struct si_vertex_element *v = (struct si_vertex_element*)state;
2515
2516 rctx->vertex_elements = v;
2517 }
2518
2519 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
2520 {
2521 struct r600_context *rctx = (struct r600_context *)ctx;
2522
2523 if (rctx->vertex_elements == state)
2524 rctx->vertex_elements = NULL;
2525 FREE(state);
2526 }
2527
2528 static void si_set_vertex_buffers(struct pipe_context *ctx, unsigned start_slot, unsigned count,
2529 const struct pipe_vertex_buffer *buffers)
2530 {
2531 struct r600_context *rctx = (struct r600_context *)ctx;
2532
2533 util_set_vertex_buffers_count(rctx->vertex_buffer, &rctx->nr_vertex_buffers, buffers, start_slot, count);
2534 }
2535
2536 static void si_set_index_buffer(struct pipe_context *ctx,
2537 const struct pipe_index_buffer *ib)
2538 {
2539 struct r600_context *rctx = (struct r600_context *)ctx;
2540
2541 if (ib) {
2542 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
2543 memcpy(&rctx->index_buffer, ib, sizeof(*ib));
2544 } else {
2545 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
2546 }
2547 }
2548
2549 /*
2550 * Misc
2551 */
2552 static void si_set_polygon_stipple(struct pipe_context *ctx,
2553 const struct pipe_poly_stipple *state)
2554 {
2555 }
2556
2557 static void si_texture_barrier(struct pipe_context *ctx)
2558 {
2559 struct r600_context *rctx = (struct r600_context *)ctx;
2560 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
2561
2562 si_pm4_inval_texture_cache(pm4);
2563 si_pm4_inval_fb_cache(pm4, rctx->framebuffer.nr_cbufs);
2564 si_pm4_set_state(rctx, texture_barrier, pm4);
2565 }
2566
2567 void si_init_state_functions(struct r600_context *rctx)
2568 {
2569 rctx->context.create_blend_state = si_create_blend_state;
2570 rctx->context.bind_blend_state = si_bind_blend_state;
2571 rctx->context.delete_blend_state = si_delete_blend_state;
2572 rctx->context.set_blend_color = si_set_blend_color;
2573
2574 rctx->context.create_rasterizer_state = si_create_rs_state;
2575 rctx->context.bind_rasterizer_state = si_bind_rs_state;
2576 rctx->context.delete_rasterizer_state = si_delete_rs_state;
2577
2578 rctx->context.create_depth_stencil_alpha_state = si_create_dsa_state;
2579 rctx->context.bind_depth_stencil_alpha_state = si_bind_dsa_state;
2580 rctx->context.delete_depth_stencil_alpha_state = si_delete_dsa_state;
2581 rctx->custom_dsa_flush = si_create_db_flush_dsa(rctx);
2582
2583 rctx->context.set_clip_state = si_set_clip_state;
2584 rctx->context.set_scissor_state = si_set_scissor_state;
2585 rctx->context.set_viewport_state = si_set_viewport_state;
2586 rctx->context.set_stencil_ref = si_set_pipe_stencil_ref;
2587
2588 rctx->context.set_framebuffer_state = si_set_framebuffer_state;
2589
2590 rctx->context.create_vs_state = si_create_vs_state;
2591 rctx->context.create_fs_state = si_create_fs_state;
2592 rctx->context.bind_vs_state = si_bind_vs_shader;
2593 rctx->context.bind_fs_state = si_bind_ps_shader;
2594 rctx->context.delete_vs_state = si_delete_vs_shader;
2595 rctx->context.delete_fs_state = si_delete_ps_shader;
2596
2597 rctx->context.create_sampler_state = si_create_sampler_state;
2598 rctx->context.bind_vertex_sampler_states = si_bind_vs_sampler;
2599 rctx->context.bind_fragment_sampler_states = si_bind_ps_sampler;
2600 rctx->context.delete_sampler_state = si_delete_sampler_state;
2601
2602 rctx->context.create_sampler_view = si_create_sampler_view;
2603 rctx->context.set_vertex_sampler_views = si_set_vs_sampler_view;
2604 rctx->context.set_fragment_sampler_views = si_set_ps_sampler_view;
2605 rctx->context.sampler_view_destroy = si_sampler_view_destroy;
2606
2607 rctx->context.set_sample_mask = si_set_sample_mask;
2608
2609 rctx->context.set_constant_buffer = si_set_constant_buffer;
2610
2611 rctx->context.create_vertex_elements_state = si_create_vertex_elements;
2612 rctx->context.bind_vertex_elements_state = si_bind_vertex_elements;
2613 rctx->context.delete_vertex_elements_state = si_delete_vertex_element;
2614 rctx->context.set_vertex_buffers = si_set_vertex_buffers;
2615 rctx->context.set_index_buffer = si_set_index_buffer;
2616
2617 rctx->context.create_stream_output_target = si_create_so_target;
2618 rctx->context.stream_output_target_destroy = si_so_target_destroy;
2619 rctx->context.set_stream_output_targets = si_set_so_targets;
2620
2621 rctx->context.texture_barrier = si_texture_barrier;
2622 rctx->context.set_polygon_stipple = si_set_polygon_stipple;
2623
2624 rctx->context.draw_vbo = si_draw_vbo;
2625 }
2626
2627 void si_init_config(struct r600_context *rctx)
2628 {
2629 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
2630
2631 si_cmd_context_control(pm4);
2632
2633 si_pm4_set_reg(pm4, R_028A4C_PA_SC_MODE_CNTL_1, 0x0);
2634
2635 si_pm4_set_reg(pm4, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0);
2636 si_pm4_set_reg(pm4, R_028A14_VGT_HOS_CNTL, 0x0);
2637 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0);
2638 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0);
2639 si_pm4_set_reg(pm4, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0);
2640 si_pm4_set_reg(pm4, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0);
2641 si_pm4_set_reg(pm4, R_028A28_VGT_GROUP_FIRST_DECR, 0x0);
2642 si_pm4_set_reg(pm4, R_028A2C_VGT_GROUP_DECR, 0x0);
2643 si_pm4_set_reg(pm4, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0);
2644 si_pm4_set_reg(pm4, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0);
2645 si_pm4_set_reg(pm4, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0);
2646 si_pm4_set_reg(pm4, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0);
2647 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, 0x0);
2648 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0x0);
2649 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
2650 si_pm4_set_reg(pm4, R_028B94_VGT_STRMOUT_CONFIG, 0x0);
2651 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
2652 si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM,
2653 S_028AA8_SWITCH_ON_EOP(1) |
2654 S_028AA8_PARTIAL_VS_WAVE_ON(1) |
2655 S_028AA8_PRIMGROUP_SIZE(63));
2656 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0x00000000);
2657 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
2658 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
2659 S_008A14_CLIP_VTX_REORDER_ENA(1));
2660
2661 si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, 0);
2662 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
2663 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
2664
2665 si_pm4_set_reg(pm4, R_028804_DB_EQAA, 0x110000);
2666
2667 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
2668
2669 switch (rctx->screen->family) {
2670 case CHIP_TAHITI:
2671 case CHIP_PITCAIRN:
2672 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x2a00126a);
2673 break;
2674 case CHIP_VERDE:
2675 default:
2676 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x0000124a);
2677 break;
2678 }
2679
2680 si_pm4_set_state(rctx, init, pm4);
2681 }