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radeonsi: move shaders to new handling
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "util/u_memory.h"
28 #include "util/u_framebuffer.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "radeonsi_pipe.h"
31 #include "si_state.h"
32 #include "sid.h"
33
34 /*
35 * inferred framebuffer and blender state
36 */
37 static void si_update_fb_blend_state(struct r600_context *rctx)
38 {
39 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
40 struct si_state_blend *blend = rctx->queued.named.blend;
41 uint32_t mask;
42
43 if (pm4 == NULL || blend == NULL)
44 return;
45
46 mask = (1ULL << ((unsigned)rctx->framebuffer.nr_cbufs * 4)) - 1;
47 mask &= blend->cb_target_mask;
48 si_pm4_set_reg(pm4, R_028238_CB_TARGET_MASK, mask);
49
50 si_pm4_set_state(rctx, fb_blend, pm4);
51 }
52
53 /*
54 * Blender functions
55 */
56
57 static uint32_t si_translate_blend_function(int blend_func)
58 {
59 switch (blend_func) {
60 case PIPE_BLEND_ADD:
61 return V_028780_COMB_DST_PLUS_SRC;
62 case PIPE_BLEND_SUBTRACT:
63 return V_028780_COMB_SRC_MINUS_DST;
64 case PIPE_BLEND_REVERSE_SUBTRACT:
65 return V_028780_COMB_DST_MINUS_SRC;
66 case PIPE_BLEND_MIN:
67 return V_028780_COMB_MIN_DST_SRC;
68 case PIPE_BLEND_MAX:
69 return V_028780_COMB_MAX_DST_SRC;
70 default:
71 R600_ERR("Unknown blend function %d\n", blend_func);
72 assert(0);
73 break;
74 }
75 return 0;
76 }
77
78 static uint32_t si_translate_blend_factor(int blend_fact)
79 {
80 switch (blend_fact) {
81 case PIPE_BLENDFACTOR_ONE:
82 return V_028780_BLEND_ONE;
83 case PIPE_BLENDFACTOR_SRC_COLOR:
84 return V_028780_BLEND_SRC_COLOR;
85 case PIPE_BLENDFACTOR_SRC_ALPHA:
86 return V_028780_BLEND_SRC_ALPHA;
87 case PIPE_BLENDFACTOR_DST_ALPHA:
88 return V_028780_BLEND_DST_ALPHA;
89 case PIPE_BLENDFACTOR_DST_COLOR:
90 return V_028780_BLEND_DST_COLOR;
91 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
92 return V_028780_BLEND_SRC_ALPHA_SATURATE;
93 case PIPE_BLENDFACTOR_CONST_COLOR:
94 return V_028780_BLEND_CONSTANT_COLOR;
95 case PIPE_BLENDFACTOR_CONST_ALPHA:
96 return V_028780_BLEND_CONSTANT_ALPHA;
97 case PIPE_BLENDFACTOR_ZERO:
98 return V_028780_BLEND_ZERO;
99 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
100 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
101 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
102 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
103 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
104 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
105 case PIPE_BLENDFACTOR_INV_DST_COLOR:
106 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
107 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
108 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
109 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
110 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
111 case PIPE_BLENDFACTOR_SRC1_COLOR:
112 return V_028780_BLEND_SRC1_COLOR;
113 case PIPE_BLENDFACTOR_SRC1_ALPHA:
114 return V_028780_BLEND_SRC1_ALPHA;
115 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
116 return V_028780_BLEND_INV_SRC1_COLOR;
117 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
118 return V_028780_BLEND_INV_SRC1_ALPHA;
119 default:
120 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
121 assert(0);
122 break;
123 }
124 return 0;
125 }
126
127 static void *si_create_blend_state(struct pipe_context *ctx,
128 const struct pipe_blend_state *state)
129 {
130 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
131 struct si_pm4_state *pm4 = &blend->pm4;
132
133 uint32_t color_control;
134
135 if (blend == NULL)
136 return NULL;
137
138 color_control = S_028808_MODE(V_028808_CB_NORMAL);
139 if (state->logicop_enable) {
140 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
141 } else {
142 color_control |= S_028808_ROP3(0xcc);
143 }
144 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
145
146 si_pm4_set_reg(pm4, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, ~0);
147 si_pm4_set_reg(pm4, R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, ~0);
148
149 blend->cb_target_mask = 0;
150 for (int i = 0; i < 8; i++) {
151 /* state->rt entries > 0 only written if independent blending */
152 const int j = state->independent_blend_enable ? i : 0;
153
154 unsigned eqRGB = state->rt[j].rgb_func;
155 unsigned srcRGB = state->rt[j].rgb_src_factor;
156 unsigned dstRGB = state->rt[j].rgb_dst_factor;
157 unsigned eqA = state->rt[j].alpha_func;
158 unsigned srcA = state->rt[j].alpha_src_factor;
159 unsigned dstA = state->rt[j].alpha_dst_factor;
160
161 unsigned blend_cntl = 0;
162
163 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
164 blend->cb_target_mask |= state->rt[j].colormask << (4 * i);
165
166 if (!state->rt[j].blend_enable) {
167 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
168 continue;
169 }
170
171 blend_cntl |= S_028780_ENABLE(1);
172 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
173 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
174 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
175
176 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
177 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
178 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
179 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
180 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
181 }
182 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
183 }
184
185 return blend;
186 }
187
188 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
189 {
190 struct r600_context *rctx = (struct r600_context *)ctx;
191 si_pm4_bind_state(rctx, blend, (struct si_state_blend *)state);
192 si_update_fb_blend_state(rctx);
193 }
194
195 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
196 {
197 struct r600_context *rctx = (struct r600_context *)ctx;
198 si_pm4_delete_state(rctx, blend, (struct si_state_blend *)state);
199 }
200
201 static void si_set_blend_color(struct pipe_context *ctx,
202 const struct pipe_blend_color *state)
203 {
204 struct r600_context *rctx = (struct r600_context *)ctx;
205 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
206
207 if (pm4 == NULL)
208 return;
209
210 si_pm4_set_reg(pm4, R_028414_CB_BLEND_RED, fui(state->color[0]));
211 si_pm4_set_reg(pm4, R_028418_CB_BLEND_GREEN, fui(state->color[1]));
212 si_pm4_set_reg(pm4, R_02841C_CB_BLEND_BLUE, fui(state->color[2]));
213 si_pm4_set_reg(pm4, R_028420_CB_BLEND_ALPHA, fui(state->color[3]));
214
215 si_pm4_set_state(rctx, blend_color, pm4);
216 }
217
218 /*
219 * Clipping, scissors and viewport
220 */
221
222 static void si_set_clip_state(struct pipe_context *ctx,
223 const struct pipe_clip_state *state)
224 {
225 struct r600_context *rctx = (struct r600_context *)ctx;
226 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
227
228 if (pm4 == NULL)
229 return;
230
231 for (int i = 0; i < 6; i++) {
232 si_pm4_set_reg(pm4, R_0285BC_PA_CL_UCP_0_X + i * 16,
233 fui(state->ucp[i][0]));
234 si_pm4_set_reg(pm4, R_0285C0_PA_CL_UCP_0_Y + i * 16,
235 fui(state->ucp[i][1]));
236 si_pm4_set_reg(pm4, R_0285C4_PA_CL_UCP_0_Z + i * 16,
237 fui(state->ucp[i][2]));
238 si_pm4_set_reg(pm4, R_0285C8_PA_CL_UCP_0_W + i * 16,
239 fui(state->ucp[i][3]));
240 }
241
242 si_pm4_set_state(rctx, clip, pm4);
243 }
244
245 static void si_set_scissor_state(struct pipe_context *ctx,
246 const struct pipe_scissor_state *state)
247 {
248 struct r600_context *rctx = (struct r600_context *)ctx;
249 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
250 uint32_t tl, br;
251
252 if (pm4 == NULL)
253 return;
254
255 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny);
256 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
257 si_pm4_set_reg(pm4, R_028210_PA_SC_CLIPRECT_0_TL, tl);
258 si_pm4_set_reg(pm4, R_028214_PA_SC_CLIPRECT_0_BR, br);
259 si_pm4_set_reg(pm4, R_028218_PA_SC_CLIPRECT_1_TL, tl);
260 si_pm4_set_reg(pm4, R_02821C_PA_SC_CLIPRECT_1_BR, br);
261 si_pm4_set_reg(pm4, R_028220_PA_SC_CLIPRECT_2_TL, tl);
262 si_pm4_set_reg(pm4, R_028224_PA_SC_CLIPRECT_2_BR, br);
263 si_pm4_set_reg(pm4, R_028228_PA_SC_CLIPRECT_3_TL, tl);
264 si_pm4_set_reg(pm4, R_02822C_PA_SC_CLIPRECT_3_BR, br);
265
266 si_pm4_set_state(rctx, scissor, pm4);
267 }
268
269 static void si_set_viewport_state(struct pipe_context *ctx,
270 const struct pipe_viewport_state *state)
271 {
272 struct r600_context *rctx = (struct r600_context *)ctx;
273 struct si_state_viewport *viewport = CALLOC_STRUCT(si_state_viewport);
274 struct si_pm4_state *pm4 = &viewport->pm4;
275
276 if (viewport == NULL)
277 return;
278
279 viewport->viewport = *state;
280 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000);
281 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000);
282 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
283 si_pm4_set_reg(pm4, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
284 si_pm4_set_reg(pm4, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
285 si_pm4_set_reg(pm4, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
286 si_pm4_set_reg(pm4, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
287 si_pm4_set_reg(pm4, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
288 si_pm4_set_reg(pm4, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
289 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
290
291 si_pm4_set_state(rctx, viewport, viewport);
292 }
293
294 /*
295 * inferred state between framebuffer and rasterizer
296 */
297 static void si_update_fb_rs_state(struct r600_context *rctx)
298 {
299 struct si_state_rasterizer *rs = rctx->queued.named.rasterizer;
300 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
301 unsigned offset_db_fmt_cntl = 0, depth;
302 float offset_units;
303
304 if (!rs || !rctx->framebuffer.zsbuf) {
305 FREE(pm4);
306 return;
307 }
308
309 offset_units = rctx->queued.named.rasterizer->offset_units;
310 switch (rctx->framebuffer.zsbuf->texture->format) {
311 case PIPE_FORMAT_Z24X8_UNORM:
312 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
313 depth = -24;
314 offset_units *= 2.0f;
315 break;
316 case PIPE_FORMAT_Z32_FLOAT:
317 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
318 depth = -23;
319 offset_units *= 1.0f;
320 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
321 break;
322 case PIPE_FORMAT_Z16_UNORM:
323 depth = -16;
324 offset_units *= 4.0f;
325 break;
326 default:
327 return;
328 }
329
330 /* FIXME some of those reg can be computed with cso */
331 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
332 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
333 fui(rctx->queued.named.rasterizer->offset_scale));
334 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units));
335 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
336 fui(rctx->queued.named.rasterizer->offset_scale));
337 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units));
338 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, offset_db_fmt_cntl);
339
340 si_pm4_set_state(rctx, fb_rs, pm4);
341 }
342
343 /*
344 * Rasterizer
345 */
346
347 static uint32_t si_translate_fill(uint32_t func)
348 {
349 switch(func) {
350 case PIPE_POLYGON_MODE_FILL:
351 return V_028814_X_DRAW_TRIANGLES;
352 case PIPE_POLYGON_MODE_LINE:
353 return V_028814_X_DRAW_LINES;
354 case PIPE_POLYGON_MODE_POINT:
355 return V_028814_X_DRAW_POINTS;
356 default:
357 assert(0);
358 return V_028814_X_DRAW_POINTS;
359 }
360 }
361
362 static void *si_create_rs_state(struct pipe_context *ctx,
363 const struct pipe_rasterizer_state *state)
364 {
365 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
366 struct si_pm4_state *pm4 = &rs->pm4;
367 unsigned tmp;
368 unsigned prov_vtx = 1, polygon_dual_mode;
369 unsigned clip_rule;
370 float psize_min, psize_max;
371
372 if (rs == NULL) {
373 return NULL;
374 }
375
376 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
377 state->fill_back != PIPE_POLYGON_MODE_FILL);
378
379 if (state->flatshade_first)
380 prov_vtx = 0;
381
382 rs->flatshade = state->flatshade;
383 rs->sprite_coord_enable = state->sprite_coord_enable;
384 rs->pa_sc_line_stipple = state->line_stipple_enable ?
385 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
386 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
387 rs->pa_su_sc_mode_cntl =
388 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
389 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
390 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
391 S_028814_FACE(!state->front_ccw) |
392 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
393 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
394 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
395 S_028814_POLY_MODE(polygon_dual_mode) |
396 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
397 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back));
398 rs->pa_cl_clip_cntl =
399 S_028810_PS_UCP_MODE(3) |
400 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
401 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
402 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
403 rs->pa_cl_vs_out_cntl =
404 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
405 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex);
406
407 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
408
409 /* offset */
410 rs->offset_units = state->offset_units;
411 rs->offset_scale = state->offset_scale * 12.0f;
412
413 /* XXX: Flat shading hangs the GPU */
414 tmp = S_0286D4_FLAT_SHADE_ENA(0);
415 if (state->sprite_coord_enable) {
416 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
417 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
418 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
419 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
420 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1);
421 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
422 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
423 }
424 }
425 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
426
427 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0x00000000);
428 /* point size 12.4 fixed point */
429 tmp = (unsigned)(state->point_size * 8.0);
430 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
431
432 if (state->point_size_per_vertex) {
433 psize_min = util_get_min_point_size(state);
434 psize_max = 8192;
435 } else {
436 /* Force the point size to be as if the vertex output was disabled. */
437 psize_min = state->point_size;
438 psize_max = state->point_size;
439 }
440 /* Divide by two, because 0.5 = 1 pixel. */
441 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
442 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
443 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
444
445 tmp = (unsigned)state->line_width * 8;
446 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
447 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
448 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable));
449
450 si_pm4_set_reg(pm4, R_028BDC_PA_SC_LINE_CNTL, 0x00000400);
451 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
452 S_028BE4_PIX_CENTER(state->gl_rasterization_rules));
453 si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000);
454 si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000);
455 si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000);
456 si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000);
457
458 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
459 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule);
460
461 return rs;
462 }
463
464 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
465 {
466 struct r600_context *rctx = (struct r600_context *)ctx;
467 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
468
469 if (state == NULL)
470 return;
471
472 // TODO
473 rctx->sprite_coord_enable = rs->sprite_coord_enable;
474 rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
475 rctx->pa_su_sc_mode_cntl = rs->pa_su_sc_mode_cntl;
476 rctx->pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
477 rctx->pa_cl_vs_out_cntl = rs->pa_cl_vs_out_cntl;
478
479 si_pm4_bind_state(rctx, rasterizer, rs);
480 si_update_fb_rs_state(rctx);
481 }
482
483 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
484 {
485 struct r600_context *rctx = (struct r600_context *)ctx;
486 si_pm4_delete_state(rctx, rasterizer, (struct si_state_rasterizer *)state);
487 }
488
489 /*
490 * infeered state between dsa and stencil ref
491 */
492 static void si_update_dsa_stencil_ref(struct r600_context *rctx)
493 {
494 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
495 struct pipe_stencil_ref *ref = &rctx->stencil_ref;
496 struct si_state_dsa *dsa = rctx->queued.named.dsa;
497
498 if (pm4 == NULL)
499 return;
500
501 si_pm4_set_reg(pm4, R_028430_DB_STENCILREFMASK,
502 S_028430_STENCILTESTVAL(ref->ref_value[0]) |
503 S_028430_STENCILMASK(dsa->valuemask[0]) |
504 S_028430_STENCILWRITEMASK(dsa->writemask[0]));
505 si_pm4_set_reg(pm4, R_028434_DB_STENCILREFMASK_BF,
506 S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
507 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
508 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]));
509
510 si_pm4_set_state(rctx, dsa_stencil_ref, pm4);
511 }
512
513 static void si_set_pipe_stencil_ref(struct pipe_context *ctx,
514 const struct pipe_stencil_ref *state)
515 {
516 struct r600_context *rctx = (struct r600_context *)ctx;
517 rctx->stencil_ref = *state;
518 si_update_dsa_stencil_ref(rctx);
519 }
520
521
522 /*
523 * DSA
524 */
525
526 /* transnates straight */
527 static uint32_t si_translate_ds_func(int func)
528 {
529 return func;
530 }
531
532 static void *si_create_dsa_state(struct pipe_context *ctx,
533 const struct pipe_depth_stencil_alpha_state *state)
534 {
535 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
536 struct si_pm4_state *pm4 = &dsa->pm4;
537 unsigned db_depth_control, /* alpha_test_control, */ alpha_ref;
538 unsigned db_render_override, db_render_control;
539
540 if (dsa == NULL) {
541 return NULL;
542 }
543
544 dsa->valuemask[0] = state->stencil[0].valuemask;
545 dsa->valuemask[1] = state->stencil[1].valuemask;
546 dsa->writemask[0] = state->stencil[0].writemask;
547 dsa->writemask[1] = state->stencil[1].writemask;
548
549 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
550 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
551 S_028800_ZFUNC(state->depth.func);
552
553 /* stencil */
554 if (state->stencil[0].enabled) {
555 db_depth_control |= S_028800_STENCIL_ENABLE(1);
556 db_depth_control |= S_028800_STENCILFUNC(si_translate_ds_func(state->stencil[0].func));
557 //db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
558 //db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
559 //db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
560
561 if (state->stencil[1].enabled) {
562 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
563 db_depth_control |= S_028800_STENCILFUNC_BF(si_translate_ds_func(state->stencil[1].func));
564 //db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
565 //db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
566 //db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
567 }
568 }
569
570 /* alpha */
571 //alpha_test_control = 0;
572 alpha_ref = 0;
573 if (state->alpha.enabled) {
574 //alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
575 //alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
576 alpha_ref = fui(state->alpha.ref_value);
577 }
578 dsa->alpha_ref = alpha_ref;
579
580 /* misc */
581 db_render_control = 0;
582 db_render_override = S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
583 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
584 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
585 /* TODO db_render_override depends on query */
586 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, 0x00000000);
587 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, 0x00000000);
588 si_pm4_set_reg(pm4, R_028028_DB_STENCIL_CLEAR, 0x00000000);
589 si_pm4_set_reg(pm4, R_02802C_DB_DEPTH_CLEAR, 0x3F800000);
590 //si_pm4_set_reg(pm4, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control);
591 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
592 si_pm4_set_reg(pm4, R_028000_DB_RENDER_CONTROL, db_render_control);
593 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
594 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
595 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
596 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
597 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00);
598 dsa->db_render_override = db_render_override;
599
600 return dsa;
601 }
602
603 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
604 {
605 struct r600_context *rctx = (struct r600_context *)ctx;
606 struct si_state_dsa *dsa = state;
607
608 if (state == NULL)
609 return;
610
611 si_pm4_bind_state(rctx, dsa, dsa);
612 si_update_dsa_stencil_ref(rctx);
613
614 // TODO
615 rctx->alpha_ref = dsa->alpha_ref;
616 rctx->alpha_ref_dirty = true;
617 }
618
619 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
620 {
621 struct r600_context *rctx = (struct r600_context *)ctx;
622 si_pm4_delete_state(rctx, dsa, (struct si_state_dsa *)state);
623 }
624
625 static void *si_create_db_flush_dsa(struct r600_context *rctx)
626 {
627 struct pipe_depth_stencil_alpha_state dsa;
628 struct si_state_dsa *state;
629
630 memset(&dsa, 0, sizeof(dsa));
631
632 state = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
633 si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL,
634 S_028000_DEPTH_COPY(1) |
635 S_028000_STENCIL_COPY(1) |
636 S_028000_COPY_CENTROID(1));
637 return state;
638 }
639
640 /*
641 * format translation
642 */
643 static uint32_t si_translate_colorformat(enum pipe_format format)
644 {
645 switch (format) {
646 /* 8-bit buffers. */
647 case PIPE_FORMAT_A8_UNORM:
648 case PIPE_FORMAT_A8_UINT:
649 case PIPE_FORMAT_A8_SINT:
650 case PIPE_FORMAT_I8_UNORM:
651 case PIPE_FORMAT_I8_UINT:
652 case PIPE_FORMAT_I8_SINT:
653 case PIPE_FORMAT_L8_UNORM:
654 case PIPE_FORMAT_L8_UINT:
655 case PIPE_FORMAT_L8_SINT:
656 case PIPE_FORMAT_L8_SRGB:
657 case PIPE_FORMAT_R8_UNORM:
658 case PIPE_FORMAT_R8_SNORM:
659 case PIPE_FORMAT_R8_UINT:
660 case PIPE_FORMAT_R8_SINT:
661 return V_028C70_COLOR_8;
662
663 /* 16-bit buffers. */
664 case PIPE_FORMAT_B5G6R5_UNORM:
665 return V_028C70_COLOR_5_6_5;
666
667 case PIPE_FORMAT_B5G5R5A1_UNORM:
668 case PIPE_FORMAT_B5G5R5X1_UNORM:
669 return V_028C70_COLOR_1_5_5_5;
670
671 case PIPE_FORMAT_B4G4R4A4_UNORM:
672 case PIPE_FORMAT_B4G4R4X4_UNORM:
673 return V_028C70_COLOR_4_4_4_4;
674
675 case PIPE_FORMAT_L8A8_UNORM:
676 case PIPE_FORMAT_L8A8_UINT:
677 case PIPE_FORMAT_L8A8_SINT:
678 case PIPE_FORMAT_L8A8_SRGB:
679 case PIPE_FORMAT_R8G8_UNORM:
680 case PIPE_FORMAT_R8G8_UINT:
681 case PIPE_FORMAT_R8G8_SINT:
682 return V_028C70_COLOR_8_8;
683
684 case PIPE_FORMAT_Z16_UNORM:
685 case PIPE_FORMAT_R16_UNORM:
686 case PIPE_FORMAT_R16_UINT:
687 case PIPE_FORMAT_R16_SINT:
688 case PIPE_FORMAT_R16_FLOAT:
689 case PIPE_FORMAT_R16G16_FLOAT:
690 return V_028C70_COLOR_16;
691
692 /* 32-bit buffers. */
693 case PIPE_FORMAT_A8B8G8R8_SRGB:
694 case PIPE_FORMAT_A8B8G8R8_UNORM:
695 case PIPE_FORMAT_A8R8G8B8_UNORM:
696 case PIPE_FORMAT_B8G8R8A8_SRGB:
697 case PIPE_FORMAT_B8G8R8A8_UNORM:
698 case PIPE_FORMAT_B8G8R8X8_UNORM:
699 case PIPE_FORMAT_R8G8B8A8_SNORM:
700 case PIPE_FORMAT_R8G8B8A8_UNORM:
701 case PIPE_FORMAT_R8G8B8X8_UNORM:
702 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
703 case PIPE_FORMAT_X8B8G8R8_UNORM:
704 case PIPE_FORMAT_X8R8G8B8_UNORM:
705 case PIPE_FORMAT_R8G8B8_UNORM:
706 case PIPE_FORMAT_R8G8B8A8_SSCALED:
707 case PIPE_FORMAT_R8G8B8A8_USCALED:
708 case PIPE_FORMAT_R8G8B8A8_SINT:
709 case PIPE_FORMAT_R8G8B8A8_UINT:
710 return V_028C70_COLOR_8_8_8_8;
711
712 case PIPE_FORMAT_R10G10B10A2_UNORM:
713 case PIPE_FORMAT_R10G10B10X2_SNORM:
714 case PIPE_FORMAT_B10G10R10A2_UNORM:
715 case PIPE_FORMAT_B10G10R10A2_UINT:
716 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
717 return V_028C70_COLOR_2_10_10_10;
718
719 case PIPE_FORMAT_Z24X8_UNORM:
720 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
721 return V_028C70_COLOR_8_24;
722
723 case PIPE_FORMAT_X8Z24_UNORM:
724 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
725 return V_028C70_COLOR_24_8;
726
727 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
728 return V_028C70_COLOR_X24_8_32_FLOAT;
729
730 case PIPE_FORMAT_R32_FLOAT:
731 case PIPE_FORMAT_Z32_FLOAT:
732 return V_028C70_COLOR_32;
733
734 case PIPE_FORMAT_R16G16_SSCALED:
735 case PIPE_FORMAT_R16G16_UNORM:
736 case PIPE_FORMAT_R16G16_UINT:
737 case PIPE_FORMAT_R16G16_SINT:
738 return V_028C70_COLOR_16_16;
739
740 case PIPE_FORMAT_R11G11B10_FLOAT:
741 return V_028C70_COLOR_10_11_11;
742
743 /* 64-bit buffers. */
744 case PIPE_FORMAT_R16G16B16_USCALED:
745 case PIPE_FORMAT_R16G16B16_SSCALED:
746 case PIPE_FORMAT_R16G16B16A16_UINT:
747 case PIPE_FORMAT_R16G16B16A16_SINT:
748 case PIPE_FORMAT_R16G16B16A16_USCALED:
749 case PIPE_FORMAT_R16G16B16A16_SSCALED:
750 case PIPE_FORMAT_R16G16B16A16_UNORM:
751 case PIPE_FORMAT_R16G16B16A16_SNORM:
752 case PIPE_FORMAT_R16G16B16_FLOAT:
753 case PIPE_FORMAT_R16G16B16A16_FLOAT:
754 return V_028C70_COLOR_16_16_16_16;
755
756 case PIPE_FORMAT_R32G32_FLOAT:
757 case PIPE_FORMAT_R32G32_USCALED:
758 case PIPE_FORMAT_R32G32_SSCALED:
759 case PIPE_FORMAT_R32G32_SINT:
760 case PIPE_FORMAT_R32G32_UINT:
761 return V_028C70_COLOR_32_32;
762
763 /* 128-bit buffers. */
764 case PIPE_FORMAT_R32G32B32A32_SNORM:
765 case PIPE_FORMAT_R32G32B32A32_UNORM:
766 case PIPE_FORMAT_R32G32B32A32_SSCALED:
767 case PIPE_FORMAT_R32G32B32A32_USCALED:
768 case PIPE_FORMAT_R32G32B32A32_SINT:
769 case PIPE_FORMAT_R32G32B32A32_UINT:
770 case PIPE_FORMAT_R32G32B32A32_FLOAT:
771 return V_028C70_COLOR_32_32_32_32;
772
773 /* YUV buffers. */
774 case PIPE_FORMAT_UYVY:
775 case PIPE_FORMAT_YUYV:
776 /* 96-bit buffers. */
777 case PIPE_FORMAT_R32G32B32_FLOAT:
778 /* 8-bit buffers. */
779 case PIPE_FORMAT_L4A4_UNORM:
780 case PIPE_FORMAT_R4A4_UNORM:
781 case PIPE_FORMAT_A4R4_UNORM:
782 default:
783 return ~0U; /* Unsupported. */
784 }
785 }
786
787 static uint32_t si_translate_colorswap(enum pipe_format format)
788 {
789 switch (format) {
790 /* 8-bit buffers. */
791 case PIPE_FORMAT_L4A4_UNORM:
792 case PIPE_FORMAT_A4R4_UNORM:
793 return V_028C70_SWAP_ALT;
794
795 case PIPE_FORMAT_A8_UNORM:
796 case PIPE_FORMAT_A8_UINT:
797 case PIPE_FORMAT_A8_SINT:
798 case PIPE_FORMAT_R4A4_UNORM:
799 return V_028C70_SWAP_ALT_REV;
800 case PIPE_FORMAT_I8_UNORM:
801 case PIPE_FORMAT_L8_UNORM:
802 case PIPE_FORMAT_I8_UINT:
803 case PIPE_FORMAT_I8_SINT:
804 case PIPE_FORMAT_L8_UINT:
805 case PIPE_FORMAT_L8_SINT:
806 case PIPE_FORMAT_L8_SRGB:
807 case PIPE_FORMAT_R8_UNORM:
808 case PIPE_FORMAT_R8_SNORM:
809 case PIPE_FORMAT_R8_UINT:
810 case PIPE_FORMAT_R8_SINT:
811 return V_028C70_SWAP_STD;
812
813 /* 16-bit buffers. */
814 case PIPE_FORMAT_B5G6R5_UNORM:
815 return V_028C70_SWAP_STD_REV;
816
817 case PIPE_FORMAT_B5G5R5A1_UNORM:
818 case PIPE_FORMAT_B5G5R5X1_UNORM:
819 return V_028C70_SWAP_ALT;
820
821 case PIPE_FORMAT_B4G4R4A4_UNORM:
822 case PIPE_FORMAT_B4G4R4X4_UNORM:
823 return V_028C70_SWAP_ALT;
824
825 case PIPE_FORMAT_Z16_UNORM:
826 return V_028C70_SWAP_STD;
827
828 case PIPE_FORMAT_L8A8_UNORM:
829 case PIPE_FORMAT_L8A8_UINT:
830 case PIPE_FORMAT_L8A8_SINT:
831 case PIPE_FORMAT_L8A8_SRGB:
832 return V_028C70_SWAP_ALT;
833 case PIPE_FORMAT_R8G8_UNORM:
834 case PIPE_FORMAT_R8G8_UINT:
835 case PIPE_FORMAT_R8G8_SINT:
836 return V_028C70_SWAP_STD;
837
838 case PIPE_FORMAT_R16_UNORM:
839 case PIPE_FORMAT_R16_UINT:
840 case PIPE_FORMAT_R16_SINT:
841 case PIPE_FORMAT_R16_FLOAT:
842 return V_028C70_SWAP_STD;
843
844 /* 32-bit buffers. */
845 case PIPE_FORMAT_A8B8G8R8_SRGB:
846 return V_028C70_SWAP_STD_REV;
847 case PIPE_FORMAT_B8G8R8A8_SRGB:
848 return V_028C70_SWAP_ALT;
849
850 case PIPE_FORMAT_B8G8R8A8_UNORM:
851 case PIPE_FORMAT_B8G8R8X8_UNORM:
852 return V_028C70_SWAP_ALT;
853
854 case PIPE_FORMAT_A8R8G8B8_UNORM:
855 case PIPE_FORMAT_X8R8G8B8_UNORM:
856 return V_028C70_SWAP_ALT_REV;
857 case PIPE_FORMAT_R8G8B8A8_SNORM:
858 case PIPE_FORMAT_R8G8B8A8_UNORM:
859 case PIPE_FORMAT_R8G8B8A8_SSCALED:
860 case PIPE_FORMAT_R8G8B8A8_USCALED:
861 case PIPE_FORMAT_R8G8B8A8_SINT:
862 case PIPE_FORMAT_R8G8B8A8_UINT:
863 case PIPE_FORMAT_R8G8B8X8_UNORM:
864 return V_028C70_SWAP_STD;
865
866 case PIPE_FORMAT_A8B8G8R8_UNORM:
867 case PIPE_FORMAT_X8B8G8R8_UNORM:
868 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
869 return V_028C70_SWAP_STD_REV;
870
871 case PIPE_FORMAT_Z24X8_UNORM:
872 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
873 return V_028C70_SWAP_STD;
874
875 case PIPE_FORMAT_X8Z24_UNORM:
876 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
877 return V_028C70_SWAP_STD;
878
879 case PIPE_FORMAT_R10G10B10A2_UNORM:
880 case PIPE_FORMAT_R10G10B10X2_SNORM:
881 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
882 return V_028C70_SWAP_STD;
883
884 case PIPE_FORMAT_B10G10R10A2_UNORM:
885 case PIPE_FORMAT_B10G10R10A2_UINT:
886 return V_028C70_SWAP_ALT;
887
888 case PIPE_FORMAT_R11G11B10_FLOAT:
889 case PIPE_FORMAT_R32_FLOAT:
890 case PIPE_FORMAT_R32_UINT:
891 case PIPE_FORMAT_R32_SINT:
892 case PIPE_FORMAT_Z32_FLOAT:
893 case PIPE_FORMAT_R16G16_FLOAT:
894 case PIPE_FORMAT_R16G16_UNORM:
895 case PIPE_FORMAT_R16G16_UINT:
896 case PIPE_FORMAT_R16G16_SINT:
897 return V_028C70_SWAP_STD;
898
899 /* 64-bit buffers. */
900 case PIPE_FORMAT_R32G32_FLOAT:
901 case PIPE_FORMAT_R32G32_UINT:
902 case PIPE_FORMAT_R32G32_SINT:
903 case PIPE_FORMAT_R16G16B16A16_UNORM:
904 case PIPE_FORMAT_R16G16B16A16_SNORM:
905 case PIPE_FORMAT_R16G16B16A16_USCALED:
906 case PIPE_FORMAT_R16G16B16A16_SSCALED:
907 case PIPE_FORMAT_R16G16B16A16_UINT:
908 case PIPE_FORMAT_R16G16B16A16_SINT:
909 case PIPE_FORMAT_R16G16B16A16_FLOAT:
910 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
911
912 /* 128-bit buffers. */
913 case PIPE_FORMAT_R32G32B32A32_FLOAT:
914 case PIPE_FORMAT_R32G32B32A32_SNORM:
915 case PIPE_FORMAT_R32G32B32A32_UNORM:
916 case PIPE_FORMAT_R32G32B32A32_SSCALED:
917 case PIPE_FORMAT_R32G32B32A32_USCALED:
918 case PIPE_FORMAT_R32G32B32A32_SINT:
919 case PIPE_FORMAT_R32G32B32A32_UINT:
920 return V_028C70_SWAP_STD;
921 default:
922 R600_ERR("unsupported colorswap format %d\n", format);
923 return ~0U;
924 }
925 return ~0U;
926 }
927
928 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
929 {
930 if (R600_BIG_ENDIAN) {
931 switch(colorformat) {
932 /* 8-bit buffers. */
933 case V_028C70_COLOR_8:
934 return V_028C70_ENDIAN_NONE;
935
936 /* 16-bit buffers. */
937 case V_028C70_COLOR_5_6_5:
938 case V_028C70_COLOR_1_5_5_5:
939 case V_028C70_COLOR_4_4_4_4:
940 case V_028C70_COLOR_16:
941 case V_028C70_COLOR_8_8:
942 return V_028C70_ENDIAN_8IN16;
943
944 /* 32-bit buffers. */
945 case V_028C70_COLOR_8_8_8_8:
946 case V_028C70_COLOR_2_10_10_10:
947 case V_028C70_COLOR_8_24:
948 case V_028C70_COLOR_24_8:
949 case V_028C70_COLOR_16_16:
950 return V_028C70_ENDIAN_8IN32;
951
952 /* 64-bit buffers. */
953 case V_028C70_COLOR_16_16_16_16:
954 return V_028C70_ENDIAN_8IN16;
955
956 case V_028C70_COLOR_32_32:
957 return V_028C70_ENDIAN_8IN32;
958
959 /* 128-bit buffers. */
960 case V_028C70_COLOR_32_32_32_32:
961 return V_028C70_ENDIAN_8IN32;
962 default:
963 return V_028C70_ENDIAN_NONE; /* Unsupported. */
964 }
965 } else {
966 return V_028C70_ENDIAN_NONE;
967 }
968 }
969
970 static uint32_t si_translate_dbformat(enum pipe_format format)
971 {
972 switch (format) {
973 case PIPE_FORMAT_Z16_UNORM:
974 return V_028040_Z_16;
975 case PIPE_FORMAT_Z24X8_UNORM:
976 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
977 return V_028040_Z_24; /* XXX no longer supported on SI */
978 case PIPE_FORMAT_Z32_FLOAT:
979 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
980 return V_028040_Z_32_FLOAT;
981 default:
982 return ~0U;
983 }
984 }
985
986 /*
987 * framebuffer handling
988 */
989
990 static void si_cb(struct r600_context *rctx, struct si_pm4_state *pm4,
991 const struct pipe_framebuffer_state *state, int cb)
992 {
993 struct r600_resource_texture *rtex;
994 struct r600_surface *surf;
995 unsigned level = state->cbufs[cb]->u.tex.level;
996 unsigned pitch, slice;
997 unsigned color_info, color_attrib;
998 unsigned format, swap, ntype, endian;
999 uint64_t offset;
1000 unsigned blocksize;
1001 const struct util_format_description *desc;
1002 int i;
1003 unsigned blend_clamp = 0, blend_bypass = 0;
1004
1005 surf = (struct r600_surface *)state->cbufs[cb];
1006 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
1007 blocksize = util_format_get_blocksize(rtex->real_format);
1008
1009 if (rtex->depth)
1010 rctx->have_depth_fb = TRUE;
1011
1012 if (rtex->depth && !rtex->is_flushing_texture) {
1013 r600_texture_depth_flush(&rctx->context, state->cbufs[cb]->texture, TRUE);
1014 rtex = rtex->flushed_depth_texture;
1015 }
1016
1017 offset = rtex->surface.level[level].offset;
1018 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1019 offset += rtex->surface.level[level].slice_size *
1020 state->cbufs[cb]->u.tex.first_layer;
1021 }
1022 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1023 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1024 if (slice) {
1025 slice = slice - 1;
1026 }
1027
1028 color_attrib = S_028C74_TILE_MODE_INDEX(8);
1029 switch (rtex->surface.level[level].mode) {
1030 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1031 color_attrib = S_028C74_TILE_MODE_INDEX(8);
1032 break;
1033 case RADEON_SURF_MODE_1D:
1034 color_attrib = S_028C74_TILE_MODE_INDEX(9);
1035 break;
1036 case RADEON_SURF_MODE_2D:
1037 if (rtex->resource.b.b.bind & PIPE_BIND_SCANOUT) {
1038 switch (blocksize) {
1039 case 1:
1040 color_attrib = S_028C74_TILE_MODE_INDEX(10);
1041 break;
1042 case 2:
1043 color_attrib = S_028C74_TILE_MODE_INDEX(11);
1044 break;
1045 case 4:
1046 color_attrib = S_028C74_TILE_MODE_INDEX(12);
1047 break;
1048 }
1049 break;
1050 } else switch (blocksize) {
1051 case 1:
1052 color_attrib = S_028C74_TILE_MODE_INDEX(14);
1053 break;
1054 case 2:
1055 color_attrib = S_028C74_TILE_MODE_INDEX(15);
1056 break;
1057 case 4:
1058 color_attrib = S_028C74_TILE_MODE_INDEX(16);
1059 break;
1060 case 8:
1061 color_attrib = S_028C74_TILE_MODE_INDEX(17);
1062 break;
1063 default:
1064 color_attrib = S_028C74_TILE_MODE_INDEX(13);
1065 }
1066 break;
1067 }
1068
1069 desc = util_format_description(surf->base.format);
1070 for (i = 0; i < 4; i++) {
1071 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1072 break;
1073 }
1074 }
1075 if (desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1076 ntype = V_028C70_NUMBER_FLOAT;
1077 } else {
1078 ntype = V_028C70_NUMBER_UNORM;
1079 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1080 ntype = V_028C70_NUMBER_SRGB;
1081 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1082 if (desc->channel[i].normalized)
1083 ntype = V_028C70_NUMBER_SNORM;
1084 else if (desc->channel[i].pure_integer)
1085 ntype = V_028C70_NUMBER_SINT;
1086 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1087 if (desc->channel[i].normalized)
1088 ntype = V_028C70_NUMBER_UNORM;
1089 else if (desc->channel[i].pure_integer)
1090 ntype = V_028C70_NUMBER_UINT;
1091 }
1092 }
1093
1094 format = si_translate_colorformat(surf->base.format);
1095 swap = si_translate_colorswap(surf->base.format);
1096 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1097 endian = V_028C70_ENDIAN_NONE;
1098 } else {
1099 endian = si_colorformat_endian_swap(format);
1100 }
1101
1102 /* blend clamp should be set for all NORM/SRGB types */
1103 if (ntype == V_028C70_NUMBER_UNORM ||
1104 ntype == V_028C70_NUMBER_SNORM ||
1105 ntype == V_028C70_NUMBER_SRGB)
1106 blend_clamp = 1;
1107
1108 /* set blend bypass according to docs if SINT/UINT or
1109 8/24 COLOR variants */
1110 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1111 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1112 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1113 blend_clamp = 0;
1114 blend_bypass = 1;
1115 }
1116
1117 color_info = S_028C70_FORMAT(format) |
1118 S_028C70_COMP_SWAP(swap) |
1119 S_028C70_BLEND_CLAMP(blend_clamp) |
1120 S_028C70_BLEND_BYPASS(blend_bypass) |
1121 S_028C70_NUMBER_TYPE(ntype) |
1122 S_028C70_ENDIAN(endian);
1123
1124 rctx->alpha_ref_dirty = true;
1125
1126 offset += r600_resource_va(rctx->context.screen, state->cbufs[cb]->texture);
1127 offset >>= 8;
1128
1129 /* FIXME handle enabling of CB beyond BASE8 which has different offset */
1130 si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE);
1131 si_pm4_set_reg(pm4, R_028C60_CB_COLOR0_BASE + cb * 0x3C, offset);
1132 si_pm4_set_reg(pm4, R_028C64_CB_COLOR0_PITCH + cb * 0x3C, S_028C64_TILE_MAX(pitch));
1133 si_pm4_set_reg(pm4, R_028C68_CB_COLOR0_SLICE + cb * 0x3C, S_028C68_TILE_MAX(slice));
1134
1135 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1136 si_pm4_set_reg(pm4, R_028C6C_CB_COLOR0_VIEW + cb * 0x3C, 0x00000000);
1137 } else {
1138 si_pm4_set_reg(pm4, R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1139 S_028C6C_SLICE_START(state->cbufs[cb]->u.tex.first_layer) |
1140 S_028C6C_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer));
1141 }
1142 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + cb * 0x3C, color_info);
1143 si_pm4_set_reg(pm4, R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C, color_attrib);
1144 }
1145
1146 static void si_db(struct r600_context *rctx, struct si_pm4_state *pm4,
1147 const struct pipe_framebuffer_state *state)
1148 {
1149 struct r600_resource_texture *rtex;
1150 struct r600_surface *surf;
1151 unsigned level, first_layer, pitch, slice, format;
1152 uint32_t db_z_info, stencil_info;
1153 uint64_t offset;
1154
1155 if (state->zsbuf == NULL) {
1156 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, 0);
1157 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, 0);
1158 return;
1159 }
1160
1161 surf = (struct r600_surface *)state->zsbuf;
1162 level = surf->base.u.tex.level;
1163 rtex = (struct r600_resource_texture*)surf->base.texture;
1164
1165 first_layer = surf->base.u.tex.first_layer;
1166 format = si_translate_dbformat(rtex->real_format);
1167
1168 offset = r600_resource_va(rctx->context.screen, surf->base.texture);
1169 offset += rtex->surface.level[level].offset;
1170 pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
1171 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1172 if (slice) {
1173 slice = slice - 1;
1174 }
1175 offset >>= 8;
1176
1177 si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE);
1178 si_pm4_set_reg(pm4, R_028048_DB_Z_READ_BASE, offset);
1179 si_pm4_set_reg(pm4, R_028050_DB_Z_WRITE_BASE, offset);
1180 si_pm4_set_reg(pm4, R_028008_DB_DEPTH_VIEW,
1181 S_028008_SLICE_START(state->zsbuf->u.tex.first_layer) |
1182 S_028008_SLICE_MAX(state->zsbuf->u.tex.last_layer));
1183
1184 db_z_info = S_028040_FORMAT(format);
1185 stencil_info = S_028044_FORMAT(rtex->stencil != 0);
1186
1187 switch (format) {
1188 case V_028040_Z_16:
1189 db_z_info |= S_028040_TILE_MODE_INDEX(5);
1190 stencil_info |= S_028044_TILE_MODE_INDEX(5);
1191 break;
1192 case V_028040_Z_24:
1193 case V_028040_Z_32_FLOAT:
1194 db_z_info |= S_028040_TILE_MODE_INDEX(6);
1195 stencil_info |= S_028044_TILE_MODE_INDEX(6);
1196 break;
1197 default:
1198 db_z_info |= S_028040_TILE_MODE_INDEX(7);
1199 stencil_info |= S_028044_TILE_MODE_INDEX(7);
1200 }
1201
1202 if (rtex->stencil) {
1203 uint64_t stencil_offset =
1204 r600_texture_get_offset(rtex->stencil, level, first_layer);
1205
1206 stencil_offset += r600_resource_va(rctx->context.screen, (void*)rtex->stencil);
1207 stencil_offset >>= 8;
1208
1209 si_pm4_add_bo(pm4, &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1210 si_pm4_set_reg(pm4, R_02804C_DB_STENCIL_READ_BASE, stencil_offset);
1211 si_pm4_set_reg(pm4, R_028054_DB_STENCIL_WRITE_BASE, stencil_offset);
1212 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, stencil_info);
1213 } else {
1214 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, 0);
1215 }
1216
1217 if (format != ~0U) {
1218 si_pm4_set_reg(pm4, R_02803C_DB_DEPTH_INFO, 0x1);
1219 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, db_z_info);
1220 si_pm4_set_reg(pm4, R_028058_DB_DEPTH_SIZE, S_028058_PITCH_TILE_MAX(pitch));
1221 si_pm4_set_reg(pm4, R_02805C_DB_DEPTH_SLICE, S_02805C_SLICE_TILE_MAX(slice));
1222
1223 } else {
1224 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, 0);
1225 }
1226 }
1227
1228 static void si_set_framebuffer_state(struct pipe_context *ctx,
1229 const struct pipe_framebuffer_state *state)
1230 {
1231 struct r600_context *rctx = (struct r600_context *)ctx;
1232 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
1233 uint32_t shader_mask, tl, br;
1234 int tl_x, tl_y, br_x, br_y;
1235
1236 if (pm4 == NULL)
1237 return;
1238
1239 si_pm4_inval_fb_cache(pm4, state->nr_cbufs);
1240
1241 if (state->zsbuf)
1242 si_pm4_inval_zsbuf_cache(pm4);
1243
1244 util_copy_framebuffer_state(&rctx->framebuffer, state);
1245
1246 /* build states */
1247 rctx->have_depth_fb = 0;
1248 for (int i = 0; i < state->nr_cbufs; i++) {
1249 si_cb(rctx, pm4, state, i);
1250 }
1251 si_db(rctx, pm4, state);
1252
1253 shader_mask = 0;
1254 for (int i = 0; i < state->nr_cbufs; i++) {
1255 shader_mask |= 0xf << (i * 4);
1256 }
1257 tl_x = 0;
1258 tl_y = 0;
1259 br_x = state->width;
1260 br_y = state->height;
1261 #if 0 /* These shouldn't be necessary on SI, see PA_SC_ENHANCE register */
1262 /* EG hw workaround */
1263 if (br_x == 0)
1264 tl_x = 1;
1265 if (br_y == 0)
1266 tl_y = 1;
1267 /* cayman hw workaround */
1268 if (rctx->chip_class == CAYMAN) {
1269 if (br_x == 1 && br_y == 1)
1270 br_x = 2;
1271 }
1272 #endif
1273 tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
1274 br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
1275
1276 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, tl);
1277 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR, br);
1278 si_pm4_set_reg(pm4, R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl);
1279 si_pm4_set_reg(pm4, R_028254_PA_SC_VPORT_SCISSOR_0_BR, br);
1280 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, tl);
1281 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR, br);
1282 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, tl);
1283 si_pm4_set_reg(pm4, R_028208_PA_SC_WINDOW_SCISSOR_BR, br);
1284 si_pm4_set_reg(pm4, R_028200_PA_SC_WINDOW_OFFSET, 0x00000000);
1285 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
1286 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, shader_mask);
1287 si_pm4_set_reg(pm4, R_028BE0_PA_SC_AA_CONFIG, 0x00000000);
1288
1289 si_pm4_set_state(rctx, framebuffer, pm4);
1290 si_update_fb_rs_state(rctx);
1291 si_update_fb_blend_state(rctx);
1292 }
1293
1294 /*
1295 * shaders
1296 */
1297
1298 static void *si_create_shader_state(struct pipe_context *ctx,
1299 const struct pipe_shader_state *state)
1300 {
1301 struct si_pipe_shader *shader = CALLOC_STRUCT(si_pipe_shader);
1302
1303 shader->tokens = tgsi_dup_tokens(state->tokens);
1304 shader->so = state->stream_output;
1305
1306 return shader;
1307 }
1308
1309 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
1310 {
1311 struct r600_context *rctx = (struct r600_context *)ctx;
1312 struct si_pipe_shader *shader = state;
1313
1314 if (rctx->vs_shader == state)
1315 return;
1316
1317 rctx->shader_dirty = true;
1318 rctx->vs_shader = shader;
1319 si_pm4_bind_state(rctx, vs, shader->pm4);
1320 }
1321
1322 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
1323 {
1324 struct r600_context *rctx = (struct r600_context *)ctx;
1325 struct si_pipe_shader *shader = state;
1326
1327 if (rctx->ps_shader == state)
1328 return;
1329
1330 rctx->shader_dirty = true;
1331 rctx->ps_shader = shader;
1332 si_pm4_bind_state(rctx, ps, shader->pm4);
1333 }
1334
1335 static void si_delete_vs_shader(struct pipe_context *ctx, void *state)
1336 {
1337 struct r600_context *rctx = (struct r600_context *)ctx;
1338 struct si_pipe_shader *shader = (struct si_pipe_shader *)state;
1339
1340 if (rctx->vs_shader == shader) {
1341 rctx->vs_shader = NULL;
1342 }
1343
1344 si_pm4_delete_state(rctx, vs, shader->pm4);
1345 free(shader->tokens);
1346 si_pipe_shader_destroy(ctx, shader);
1347 free(shader);
1348 }
1349
1350 static void si_delete_ps_shader(struct pipe_context *ctx, void *state)
1351 {
1352 struct r600_context *rctx = (struct r600_context *)ctx;
1353 struct si_pipe_shader *shader = (struct si_pipe_shader *)state;
1354
1355 if (rctx->ps_shader == shader) {
1356 rctx->ps_shader = NULL;
1357 }
1358
1359 si_pm4_delete_state(rctx, ps, shader->pm4);
1360 free(shader->tokens);
1361 si_pipe_shader_destroy(ctx, shader);
1362 free(shader);
1363 }
1364
1365 void si_pipe_shader_vs(struct pipe_context *ctx, struct si_pipe_shader *shader)
1366 {
1367 struct r600_context *rctx = (struct r600_context *)ctx;
1368 struct si_pm4_state *pm4;
1369 unsigned num_sgprs, num_user_sgprs;
1370 unsigned nparams, i;
1371 uint64_t va;
1372
1373 if (si_pipe_shader_create(ctx, shader))
1374 return;
1375
1376 si_pm4_delete_state(rctx, vs, shader->pm4);
1377 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
1378
1379 si_pm4_inval_shader_cache(pm4);
1380
1381 /* Certain attributes (position, psize, etc.) don't count as params.
1382 * VS is required to export at least one param and r600_shader_from_tgsi()
1383 * takes care of adding a dummy export.
1384 */
1385 for (nparams = 0, i = 0 ; i < shader->shader.noutput; i++) {
1386 if (shader->shader.output[i].name != TGSI_SEMANTIC_POSITION)
1387 nparams++;
1388 }
1389 if (nparams < 1)
1390 nparams = 1;
1391
1392 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
1393 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
1394
1395 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
1396 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1397 S_02870C_POS1_EXPORT_FORMAT(V_02870C_SPI_SHADER_NONE) |
1398 S_02870C_POS2_EXPORT_FORMAT(V_02870C_SPI_SHADER_NONE) |
1399 S_02870C_POS3_EXPORT_FORMAT(V_02870C_SPI_SHADER_NONE));
1400
1401 va = r600_resource_va(ctx->screen, (void *)shader->bo);
1402 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ);
1403 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
1404 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
1405
1406 num_user_sgprs = 8;
1407 num_sgprs = shader->num_sgprs;
1408 if (num_user_sgprs > num_sgprs)
1409 num_sgprs = num_user_sgprs;
1410 /* Last 2 reserved SGPRs are used for VCC */
1411 num_sgprs += 2;
1412 assert(num_sgprs <= 104);
1413
1414 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
1415 S_00B128_VGPRS((shader->num_vgprs - 1) / 4) |
1416 S_00B128_SGPRS((num_sgprs - 1) / 8));
1417 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
1418 S_00B12C_USER_SGPR(num_user_sgprs));
1419
1420 si_pm4_bind_state(rctx, vs, shader->pm4);
1421 }
1422
1423 void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *shader)
1424 {
1425 struct r600_context *rctx = (struct r600_context *)ctx;
1426 struct si_pm4_state *pm4;
1427 unsigned i, exports_ps, num_cout, spi_ps_in_control, db_shader_control;
1428 unsigned num_sgprs, num_user_sgprs;
1429 int ninterp = 0;
1430 boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
1431 unsigned spi_baryc_cntl;
1432 uint64_t va;
1433
1434 if (si_pipe_shader_create(ctx, shader))
1435 return;
1436
1437 si_pm4_delete_state(rctx, ps, shader->pm4);
1438 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
1439
1440 si_pm4_inval_shader_cache(pm4);
1441
1442 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
1443 for (i = 0; i < shader->shader.ninput; i++) {
1444 ninterp++;
1445 /* XXX: Flat shading hangs the GPU */
1446 if (shader->shader.input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
1447 (shader->shader.input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
1448 rctx->queued.named.rasterizer->flatshade))
1449 have_linear = TRUE;
1450 if (shader->shader.input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
1451 have_linear = TRUE;
1452 if (shader->shader.input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
1453 have_perspective = TRUE;
1454 if (shader->shader.input[i].centroid)
1455 have_centroid = TRUE;
1456 }
1457
1458 for (i = 0; i < shader->shader.noutput; i++) {
1459 if (shader->shader.output[i].name == TGSI_SEMANTIC_POSITION)
1460 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
1461 if (shader->shader.output[i].name == TGSI_SEMANTIC_STENCIL)
1462 db_shader_control |= 0; // XXX OP_VAL or TEST_VAL?
1463 }
1464 if (shader->shader.uses_kill)
1465 db_shader_control |= S_02880C_KILL_ENABLE(1);
1466
1467 exports_ps = 0;
1468 num_cout = 0;
1469 for (i = 0; i < shader->shader.noutput; i++) {
1470 if (shader->shader.output[i].name == TGSI_SEMANTIC_POSITION ||
1471 shader->shader.output[i].name == TGSI_SEMANTIC_STENCIL)
1472 exports_ps |= 1;
1473 else if (shader->shader.output[i].name == TGSI_SEMANTIC_COLOR) {
1474 if (shader->shader.fs_write_all)
1475 num_cout = shader->shader.nr_cbufs;
1476 else
1477 num_cout++;
1478 }
1479 }
1480 if (!exports_ps) {
1481 /* always at least export 1 component per pixel */
1482 exports_ps = 2;
1483 }
1484
1485 spi_ps_in_control = S_0286D8_NUM_INTERP(ninterp);
1486
1487 spi_baryc_cntl = 0;
1488 if (have_perspective)
1489 spi_baryc_cntl |= have_centroid ?
1490 S_0286E0_PERSP_CENTROID_CNTL(1) : S_0286E0_PERSP_CENTER_CNTL(1);
1491 if (have_linear)
1492 spi_baryc_cntl |= have_centroid ?
1493 S_0286E0_LINEAR_CENTROID_CNTL(1) : S_0286E0_LINEAR_CENTER_CNTL(1);
1494
1495 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
1496 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, shader->spi_ps_input_ena);
1497 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR, shader->spi_ps_input_ena);
1498 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
1499
1500 /* XXX: Depends on Z buffer format? */
1501 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT, 0);
1502
1503 /* XXX: Depends on color buffer format? */
1504 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT,
1505 S_028714_COL0_EXPORT_FORMAT(V_028714_SPI_SHADER_32_ABGR));
1506
1507 va = r600_resource_va(ctx->screen, (void *)shader->bo);
1508 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ);
1509 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
1510 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
1511
1512 num_user_sgprs = 6;
1513 num_sgprs = shader->num_sgprs;
1514 if (num_user_sgprs > num_sgprs)
1515 num_sgprs = num_user_sgprs;
1516 /* Last 2 reserved SGPRs are used for VCC */
1517 num_sgprs += 2;
1518 assert(num_sgprs <= 104);
1519
1520 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
1521 S_00B028_VGPRS((shader->num_vgprs - 1) / 4) |
1522 S_00B028_SGPRS((num_sgprs - 1) / 8));
1523 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
1524 S_00B02C_USER_SGPR(num_user_sgprs));
1525
1526 si_pm4_set_reg(pm4, R_02880C_DB_SHADER_CONTROL, db_shader_control);
1527
1528 shader->sprite_coord_enable = rctx->sprite_coord_enable;
1529 si_pm4_bind_state(rctx, ps, shader->pm4);
1530 }
1531
1532 void si_init_state_functions(struct r600_context *rctx)
1533 {
1534 rctx->context.create_blend_state = si_create_blend_state;
1535 rctx->context.bind_blend_state = si_bind_blend_state;
1536 rctx->context.delete_blend_state = si_delete_blend_state;
1537 rctx->context.set_blend_color = si_set_blend_color;
1538
1539 rctx->context.create_rasterizer_state = si_create_rs_state;
1540 rctx->context.bind_rasterizer_state = si_bind_rs_state;
1541 rctx->context.delete_rasterizer_state = si_delete_rs_state;
1542
1543 rctx->context.create_depth_stencil_alpha_state = si_create_dsa_state;
1544 rctx->context.bind_depth_stencil_alpha_state = si_bind_dsa_state;
1545 rctx->context.delete_depth_stencil_alpha_state = si_delete_dsa_state;
1546 rctx->custom_dsa_flush = si_create_db_flush_dsa(rctx);
1547
1548 rctx->context.set_clip_state = si_set_clip_state;
1549 rctx->context.set_scissor_state = si_set_scissor_state;
1550 rctx->context.set_viewport_state = si_set_viewport_state;
1551 rctx->context.set_stencil_ref = si_set_pipe_stencil_ref;
1552
1553 rctx->context.set_framebuffer_state = si_set_framebuffer_state;
1554
1555 rctx->context.create_vs_state = si_create_shader_state;
1556 rctx->context.create_fs_state = si_create_shader_state;
1557 rctx->context.bind_vs_state = si_bind_vs_shader;
1558 rctx->context.bind_fs_state = si_bind_ps_shader;
1559 rctx->context.delete_vs_state = si_delete_vs_shader;
1560 rctx->context.delete_fs_state = si_delete_ps_shader;
1561 }
1562
1563 void si_init_config(struct r600_context *rctx)
1564 {
1565 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
1566
1567 si_pm4_set_reg(pm4, R_028A4C_PA_SC_MODE_CNTL_1, 0x0);
1568
1569 si_pm4_set_reg(pm4, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0);
1570 si_pm4_set_reg(pm4, R_028A14_VGT_HOS_CNTL, 0x0);
1571 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0);
1572 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0);
1573 si_pm4_set_reg(pm4, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0);
1574 si_pm4_set_reg(pm4, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0);
1575 si_pm4_set_reg(pm4, R_028A28_VGT_GROUP_FIRST_DECR, 0x0);
1576 si_pm4_set_reg(pm4, R_028A2C_VGT_GROUP_DECR, 0x0);
1577 si_pm4_set_reg(pm4, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0);
1578 si_pm4_set_reg(pm4, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0);
1579 si_pm4_set_reg(pm4, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0);
1580 si_pm4_set_reg(pm4, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0);
1581 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, 0x0);
1582 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0x0);
1583 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
1584 si_pm4_set_reg(pm4, R_028B94_VGT_STRMOUT_CONFIG, 0x0);
1585 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
1586 si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM,
1587 S_028AA8_SWITCH_ON_EOP(1) |
1588 S_028AA8_PARTIAL_VS_WAVE_ON(1) |
1589 S_028AA8_PRIMGROUP_SIZE(63));
1590 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0x00000000);
1591 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
1592 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
1593
1594 si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, 0);
1595 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
1596 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
1597
1598 si_pm4_set_reg(pm4, R_028804_DB_EQAA, 0x110000);
1599
1600 si_pm4_set_state(rctx, init, pm4);
1601 }
1602
1603 static unsigned si_conv_pipe_prim(unsigned pprim)
1604 {
1605 static const unsigned prim_conv[] = {
1606 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
1607 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
1608 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
1609 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
1610 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
1611 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
1612 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
1613 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
1614 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
1615 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
1616 [PIPE_PRIM_LINES_ADJACENCY] = ~0,
1617 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = ~0,
1618 [PIPE_PRIM_TRIANGLES_ADJACENCY] = ~0,
1619 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = ~0
1620 };
1621 unsigned result = prim_conv[pprim];
1622 if (result == ~0) {
1623 R600_ERR("unsupported primitive type %d\n", pprim);
1624 }
1625 return result;
1626 }
1627
1628 bool si_update_draw_info_state(struct r600_context *rctx,
1629 const struct pipe_draw_info *info)
1630 {
1631 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
1632 unsigned prim = si_conv_pipe_prim(info->mode);
1633 unsigned ls_mask = 0;
1634
1635 if (pm4 == NULL)
1636 return false;
1637
1638 if (prim == ~0) {
1639 FREE(pm4);
1640 return false;
1641 }
1642
1643 si_pm4_set_reg(pm4, R_008958_VGT_PRIMITIVE_TYPE, prim);
1644 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
1645 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
1646 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, info->index_bias);
1647 si_pm4_set_reg(pm4, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info->restart_index);
1648 si_pm4_set_reg(pm4, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info->primitive_restart);
1649 #if 0
1650 si_pm4_set_reg(pm4, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
1651 si_pm4_set_reg(pm4, R_03CFF4_SQ_VTX_START_INST_LOC, info->start_instance);
1652 #endif
1653
1654 if (prim == V_008958_DI_PT_LINELIST)
1655 ls_mask = 1;
1656 else if (prim == V_008958_DI_PT_LINESTRIP)
1657 ls_mask = 2;
1658 si_pm4_set_reg(pm4, R_028A0C_PA_SC_LINE_STIPPLE,
1659 S_028A0C_AUTO_RESET_CNTL(ls_mask) |
1660 rctx->pa_sc_line_stipple);
1661
1662 if (info->mode == PIPE_PRIM_QUADS || info->mode == PIPE_PRIM_QUAD_STRIP || info->mode == PIPE_PRIM_POLYGON) {
1663 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
1664 S_028814_PROVOKING_VTX_LAST(1) | rctx->pa_su_sc_mode_cntl);
1665 } else {
1666 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL, rctx->pa_su_sc_mode_cntl);
1667 }
1668 si_pm4_set_reg(pm4, R_02881C_PA_CL_VS_OUT_CNTL,
1669 prim == PIPE_PRIM_POINTS ? rctx->pa_cl_vs_out_cntl : 0
1670 /*| (rctx->rasterizer->clip_plane_enable &
1671 rctx->vs_shader->shader.clip_dist_write)*/);
1672 si_pm4_set_reg(pm4, R_028810_PA_CL_CLIP_CNTL, rctx->pa_cl_clip_cntl
1673 /*| (rctx->vs_shader->shader.clip_dist_write ||
1674 rctx->vs_shader->shader.vs_prohibit_ucps ?
1675 0 : rctx->rasterizer->clip_plane_enable & 0x3F)*/);
1676
1677 si_pm4_set_state(rctx, draw_info, pm4);
1678 return true;
1679 }
1680
1681 void si_update_spi_map(struct r600_context *rctx)
1682 {
1683 struct si_shader *ps = &rctx->ps_shader->shader;
1684 struct si_shader *vs = &rctx->vs_shader->shader;
1685 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
1686 unsigned i, j, tmp;
1687
1688 for (i = 0; i < ps->ninput; i++) {
1689 tmp = 0;
1690
1691 #if 0
1692 /* XXX: Flat shading hangs the GPU */
1693 if (ps->input[i].name == TGSI_SEMANTIC_POSITION ||
1694 ps->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
1695 (ps->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
1696 rctx->rasterizer && rctx->rasterizer->flatshade)) {
1697 tmp |= S_028644_FLAT_SHADE(1);
1698 }
1699 #endif
1700
1701 if (ps->input[i].name == TGSI_SEMANTIC_GENERIC &&
1702 rctx->sprite_coord_enable & (1 << ps->input[i].sid)) {
1703 tmp |= S_028644_PT_SPRITE_TEX(1);
1704 }
1705
1706 for (j = 0; j < vs->noutput; j++) {
1707 if (ps->input[i].name == vs->output[j].name &&
1708 ps->input[i].sid == vs->output[j].sid) {
1709 tmp |= S_028644_OFFSET(vs->output[j].param_offset);
1710 break;
1711 }
1712 }
1713
1714 if (j == vs->noutput) {
1715 /* No corresponding output found, load defaults into input */
1716 tmp |= S_028644_OFFSET(0x20);
1717 }
1718
1719 si_pm4_set_reg(pm4, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4, tmp);
1720 }
1721
1722 si_pm4_set_state(rctx, spi, pm4);
1723 }