2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Christian König <christian.koenig@amd.com>
27 #include "util/u_memory.h"
28 #include "util/u_framebuffer.h"
29 #include "util/u_blitter.h"
30 #include "util/u_helpers.h"
31 #include "util/u_math.h"
32 #include "util/u_pack_color.h"
33 #include "util/u_upload_mgr.h"
34 #include "util/u_format_s3tc.h"
35 #include "tgsi/tgsi_parse.h"
36 #include "tgsi/tgsi_scan.h"
37 #include "radeonsi_pipe.h"
38 #include "radeonsi_shader.h"
40 #include "../radeon/r600_cs.h"
43 static uint32_t cik_num_banks(uint32_t nbanks
)
47 return V_02803C_ADDR_SURF_2_BANK
;
49 return V_02803C_ADDR_SURF_4_BANK
;
52 return V_02803C_ADDR_SURF_8_BANK
;
54 return V_02803C_ADDR_SURF_16_BANK
;
59 static unsigned cik_tile_split(unsigned tile_split
)
63 tile_split
= V_028040_ADDR_SURF_TILE_SPLIT_64B
;
66 tile_split
= V_028040_ADDR_SURF_TILE_SPLIT_128B
;
69 tile_split
= V_028040_ADDR_SURF_TILE_SPLIT_256B
;
72 tile_split
= V_028040_ADDR_SURF_TILE_SPLIT_512B
;
76 tile_split
= V_028040_ADDR_SURF_TILE_SPLIT_1KB
;
79 tile_split
= V_028040_ADDR_SURF_TILE_SPLIT_2KB
;
82 tile_split
= V_028040_ADDR_SURF_TILE_SPLIT_4KB
;
88 static unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect
)
90 switch (macro_tile_aspect
) {
93 macro_tile_aspect
= V_02803C_ADDR_SURF_MACRO_ASPECT_1
;
96 macro_tile_aspect
= V_02803C_ADDR_SURF_MACRO_ASPECT_2
;
99 macro_tile_aspect
= V_02803C_ADDR_SURF_MACRO_ASPECT_4
;
102 macro_tile_aspect
= V_02803C_ADDR_SURF_MACRO_ASPECT_8
;
105 return macro_tile_aspect
;
108 static unsigned cik_bank_wh(unsigned bankwh
)
113 bankwh
= V_02803C_ADDR_SURF_BANK_WIDTH_1
;
116 bankwh
= V_02803C_ADDR_SURF_BANK_WIDTH_2
;
119 bankwh
= V_02803C_ADDR_SURF_BANK_WIDTH_4
;
122 bankwh
= V_02803C_ADDR_SURF_BANK_WIDTH_8
;
128 static unsigned cik_db_pipe_config(unsigned tile_pipes
,
131 unsigned pipe_config
;
133 switch (tile_pipes
) {
135 pipe_config
= V_02803C_X_ADDR_SURF_P8_32X32_16X16
;
140 pipe_config
= V_02803C_X_ADDR_SURF_P4_16X16
;
142 pipe_config
= V_02803C_X_ADDR_SURF_P4_8X16
;
145 pipe_config
= V_02803C_ADDR_SURF_P2
;
152 * inferred framebuffer and blender state
154 static void si_update_fb_blend_state(struct r600_context
*rctx
)
156 struct si_pm4_state
*pm4
;
157 struct si_state_blend
*blend
= rctx
->queued
.named
.blend
;
163 pm4
= si_pm4_alloc_state(rctx
);
167 mask
= (1ULL << ((unsigned)rctx
->framebuffer
.nr_cbufs
* 4)) - 1;
168 mask
&= blend
->cb_target_mask
;
169 si_pm4_set_reg(pm4
, R_028238_CB_TARGET_MASK
, mask
);
171 si_pm4_set_state(rctx
, fb_blend
, pm4
);
178 static uint32_t si_translate_blend_function(int blend_func
)
180 switch (blend_func
) {
182 return V_028780_COMB_DST_PLUS_SRC
;
183 case PIPE_BLEND_SUBTRACT
:
184 return V_028780_COMB_SRC_MINUS_DST
;
185 case PIPE_BLEND_REVERSE_SUBTRACT
:
186 return V_028780_COMB_DST_MINUS_SRC
;
188 return V_028780_COMB_MIN_DST_SRC
;
190 return V_028780_COMB_MAX_DST_SRC
;
192 R600_ERR("Unknown blend function %d\n", blend_func
);
199 static uint32_t si_translate_blend_factor(int blend_fact
)
201 switch (blend_fact
) {
202 case PIPE_BLENDFACTOR_ONE
:
203 return V_028780_BLEND_ONE
;
204 case PIPE_BLENDFACTOR_SRC_COLOR
:
205 return V_028780_BLEND_SRC_COLOR
;
206 case PIPE_BLENDFACTOR_SRC_ALPHA
:
207 return V_028780_BLEND_SRC_ALPHA
;
208 case PIPE_BLENDFACTOR_DST_ALPHA
:
209 return V_028780_BLEND_DST_ALPHA
;
210 case PIPE_BLENDFACTOR_DST_COLOR
:
211 return V_028780_BLEND_DST_COLOR
;
212 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
213 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
214 case PIPE_BLENDFACTOR_CONST_COLOR
:
215 return V_028780_BLEND_CONSTANT_COLOR
;
216 case PIPE_BLENDFACTOR_CONST_ALPHA
:
217 return V_028780_BLEND_CONSTANT_ALPHA
;
218 case PIPE_BLENDFACTOR_ZERO
:
219 return V_028780_BLEND_ZERO
;
220 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
221 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
222 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
223 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
224 case PIPE_BLENDFACTOR_INV_DST_ALPHA
:
225 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
226 case PIPE_BLENDFACTOR_INV_DST_COLOR
:
227 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
228 case PIPE_BLENDFACTOR_INV_CONST_COLOR
:
229 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR
;
230 case PIPE_BLENDFACTOR_INV_CONST_ALPHA
:
231 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA
;
232 case PIPE_BLENDFACTOR_SRC1_COLOR
:
233 return V_028780_BLEND_SRC1_COLOR
;
234 case PIPE_BLENDFACTOR_SRC1_ALPHA
:
235 return V_028780_BLEND_SRC1_ALPHA
;
236 case PIPE_BLENDFACTOR_INV_SRC1_COLOR
:
237 return V_028780_BLEND_INV_SRC1_COLOR
;
238 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA
:
239 return V_028780_BLEND_INV_SRC1_ALPHA
;
241 R600_ERR("Bad blend factor %d not supported!\n", blend_fact
);
248 static void *si_create_blend_state_mode(struct pipe_context
*ctx
,
249 const struct pipe_blend_state
*state
,
252 struct si_state_blend
*blend
= CALLOC_STRUCT(si_state_blend
);
253 struct si_pm4_state
*pm4
= &blend
->pm4
;
255 uint32_t color_control
;
260 blend
->alpha_to_one
= state
->alpha_to_one
;
262 color_control
= S_028808_MODE(mode
);
263 if (state
->logicop_enable
) {
264 color_control
|= S_028808_ROP3(state
->logicop_func
| (state
->logicop_func
<< 4));
266 color_control
|= S_028808_ROP3(0xcc);
268 si_pm4_set_reg(pm4
, R_028808_CB_COLOR_CONTROL
, color_control
);
270 si_pm4_set_reg(pm4
, R_028B70_DB_ALPHA_TO_MASK
,
271 S_028B70_ALPHA_TO_MASK_ENABLE(state
->alpha_to_coverage
) |
272 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
273 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
274 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
275 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
277 blend
->cb_target_mask
= 0;
278 for (int i
= 0; i
< 8; i
++) {
279 /* state->rt entries > 0 only written if independent blending */
280 const int j
= state
->independent_blend_enable
? i
: 0;
282 unsigned eqRGB
= state
->rt
[j
].rgb_func
;
283 unsigned srcRGB
= state
->rt
[j
].rgb_src_factor
;
284 unsigned dstRGB
= state
->rt
[j
].rgb_dst_factor
;
285 unsigned eqA
= state
->rt
[j
].alpha_func
;
286 unsigned srcA
= state
->rt
[j
].alpha_src_factor
;
287 unsigned dstA
= state
->rt
[j
].alpha_dst_factor
;
289 unsigned blend_cntl
= 0;
291 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
292 blend
->cb_target_mask
|= state
->rt
[j
].colormask
<< (4 * i
);
294 if (!state
->rt
[j
].blend_enable
) {
295 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
299 blend_cntl
|= S_028780_ENABLE(1);
300 blend_cntl
|= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB
));
301 blend_cntl
|= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB
));
302 blend_cntl
|= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB
));
304 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
305 blend_cntl
|= S_028780_SEPARATE_ALPHA_BLEND(1);
306 blend_cntl
|= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA
));
307 blend_cntl
|= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA
));
308 blend_cntl
|= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA
));
310 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
316 static void *si_create_blend_state(struct pipe_context
*ctx
,
317 const struct pipe_blend_state
*state
)
319 return si_create_blend_state_mode(ctx
, state
, V_028808_CB_NORMAL
);
322 static void si_bind_blend_state(struct pipe_context
*ctx
, void *state
)
324 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
325 si_pm4_bind_state(rctx
, blend
, (struct si_state_blend
*)state
);
326 si_update_fb_blend_state(rctx
);
329 static void si_delete_blend_state(struct pipe_context
*ctx
, void *state
)
331 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
332 si_pm4_delete_state(rctx
, blend
, (struct si_state_blend
*)state
);
335 static void si_set_blend_color(struct pipe_context
*ctx
,
336 const struct pipe_blend_color
*state
)
338 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
339 struct si_pm4_state
*pm4
= si_pm4_alloc_state(rctx
);
344 si_pm4_set_reg(pm4
, R_028414_CB_BLEND_RED
, fui(state
->color
[0]));
345 si_pm4_set_reg(pm4
, R_028418_CB_BLEND_GREEN
, fui(state
->color
[1]));
346 si_pm4_set_reg(pm4
, R_02841C_CB_BLEND_BLUE
, fui(state
->color
[2]));
347 si_pm4_set_reg(pm4
, R_028420_CB_BLEND_ALPHA
, fui(state
->color
[3]));
349 si_pm4_set_state(rctx
, blend_color
, pm4
);
353 * Clipping, scissors and viewport
356 static void si_set_clip_state(struct pipe_context
*ctx
,
357 const struct pipe_clip_state
*state
)
359 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
360 struct si_pm4_state
*pm4
= si_pm4_alloc_state(rctx
);
361 struct pipe_constant_buffer cb
;
366 for (int i
= 0; i
< 6; i
++) {
367 si_pm4_set_reg(pm4
, R_0285BC_PA_CL_UCP_0_X
+ i
* 16,
368 fui(state
->ucp
[i
][0]));
369 si_pm4_set_reg(pm4
, R_0285C0_PA_CL_UCP_0_Y
+ i
* 16,
370 fui(state
->ucp
[i
][1]));
371 si_pm4_set_reg(pm4
, R_0285C4_PA_CL_UCP_0_Z
+ i
* 16,
372 fui(state
->ucp
[i
][2]));
373 si_pm4_set_reg(pm4
, R_0285C8_PA_CL_UCP_0_W
+ i
* 16,
374 fui(state
->ucp
[i
][3]));
378 cb
.user_buffer
= state
->ucp
;
379 cb
.buffer_offset
= 0;
380 cb
.buffer_size
= 4*4*8;
381 ctx
->set_constant_buffer(ctx
, PIPE_SHADER_VERTEX
, NUM_PIPE_CONST_BUFFERS
, &cb
);
382 pipe_resource_reference(&cb
.buffer
, NULL
);
384 si_pm4_set_state(rctx
, clip
, pm4
);
387 static void si_set_scissor_states(struct pipe_context
*ctx
,
389 unsigned num_scissors
,
390 const struct pipe_scissor_state
*state
)
392 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
393 struct si_pm4_state
*pm4
= si_pm4_alloc_state(rctx
);
399 tl
= S_028240_TL_X(state
->minx
) | S_028240_TL_Y(state
->miny
);
400 br
= S_028244_BR_X(state
->maxx
) | S_028244_BR_Y(state
->maxy
);
401 si_pm4_set_reg(pm4
, R_028210_PA_SC_CLIPRECT_0_TL
, tl
);
402 si_pm4_set_reg(pm4
, R_028214_PA_SC_CLIPRECT_0_BR
, br
);
403 si_pm4_set_reg(pm4
, R_028218_PA_SC_CLIPRECT_1_TL
, tl
);
404 si_pm4_set_reg(pm4
, R_02821C_PA_SC_CLIPRECT_1_BR
, br
);
405 si_pm4_set_reg(pm4
, R_028220_PA_SC_CLIPRECT_2_TL
, tl
);
406 si_pm4_set_reg(pm4
, R_028224_PA_SC_CLIPRECT_2_BR
, br
);
407 si_pm4_set_reg(pm4
, R_028228_PA_SC_CLIPRECT_3_TL
, tl
);
408 si_pm4_set_reg(pm4
, R_02822C_PA_SC_CLIPRECT_3_BR
, br
);
410 si_pm4_set_state(rctx
, scissor
, pm4
);
413 static void si_set_viewport_states(struct pipe_context
*ctx
,
415 unsigned num_viewports
,
416 const struct pipe_viewport_state
*state
)
418 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
419 struct si_state_viewport
*viewport
= CALLOC_STRUCT(si_state_viewport
);
420 struct si_pm4_state
*pm4
= &viewport
->pm4
;
422 if (viewport
== NULL
)
425 viewport
->viewport
= *state
;
426 si_pm4_set_reg(pm4
, R_0282D0_PA_SC_VPORT_ZMIN_0
, 0x00000000);
427 si_pm4_set_reg(pm4
, R_0282D4_PA_SC_VPORT_ZMAX_0
, 0x3F800000);
428 si_pm4_set_reg(pm4
, R_02843C_PA_CL_VPORT_XSCALE_0
, fui(state
->scale
[0]));
429 si_pm4_set_reg(pm4
, R_028440_PA_CL_VPORT_XOFFSET_0
, fui(state
->translate
[0]));
430 si_pm4_set_reg(pm4
, R_028444_PA_CL_VPORT_YSCALE_0
, fui(state
->scale
[1]));
431 si_pm4_set_reg(pm4
, R_028448_PA_CL_VPORT_YOFFSET_0
, fui(state
->translate
[1]));
432 si_pm4_set_reg(pm4
, R_02844C_PA_CL_VPORT_ZSCALE_0
, fui(state
->scale
[2]));
433 si_pm4_set_reg(pm4
, R_028450_PA_CL_VPORT_ZOFFSET_0
, fui(state
->translate
[2]));
434 si_pm4_set_reg(pm4
, R_028818_PA_CL_VTE_CNTL
, 0x0000043F);
436 si_pm4_set_state(rctx
, viewport
, viewport
);
440 * inferred state between framebuffer and rasterizer
442 static void si_update_fb_rs_state(struct r600_context
*rctx
)
444 struct si_state_rasterizer
*rs
= rctx
->queued
.named
.rasterizer
;
445 struct si_pm4_state
*pm4
;
446 unsigned offset_db_fmt_cntl
= 0, depth
;
449 if (!rs
|| !rctx
->framebuffer
.zsbuf
)
452 offset_units
= rctx
->queued
.named
.rasterizer
->offset_units
;
453 switch (rctx
->framebuffer
.zsbuf
->texture
->format
) {
454 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
455 case PIPE_FORMAT_X8Z24_UNORM
:
456 case PIPE_FORMAT_Z24X8_UNORM
:
457 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
459 offset_units
*= 2.0f
;
461 case PIPE_FORMAT_Z32_FLOAT
:
462 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
464 offset_units
*= 1.0f
;
465 offset_db_fmt_cntl
|= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
467 case PIPE_FORMAT_Z16_UNORM
:
469 offset_units
*= 4.0f
;
475 pm4
= si_pm4_alloc_state(rctx
);
480 /* FIXME some of those reg can be computed with cso */
481 offset_db_fmt_cntl
|= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth
);
482 si_pm4_set_reg(pm4
, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE
,
483 fui(rctx
->queued
.named
.rasterizer
->offset_scale
));
484 si_pm4_set_reg(pm4
, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET
, fui(offset_units
));
485 si_pm4_set_reg(pm4
, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE
,
486 fui(rctx
->queued
.named
.rasterizer
->offset_scale
));
487 si_pm4_set_reg(pm4
, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET
, fui(offset_units
));
488 si_pm4_set_reg(pm4
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
, offset_db_fmt_cntl
);
490 si_pm4_set_state(rctx
, fb_rs
, pm4
);
497 static uint32_t si_translate_fill(uint32_t func
)
500 case PIPE_POLYGON_MODE_FILL
:
501 return V_028814_X_DRAW_TRIANGLES
;
502 case PIPE_POLYGON_MODE_LINE
:
503 return V_028814_X_DRAW_LINES
;
504 case PIPE_POLYGON_MODE_POINT
:
505 return V_028814_X_DRAW_POINTS
;
508 return V_028814_X_DRAW_POINTS
;
512 static void *si_create_rs_state(struct pipe_context
*ctx
,
513 const struct pipe_rasterizer_state
*state
)
515 struct si_state_rasterizer
*rs
= CALLOC_STRUCT(si_state_rasterizer
);
516 struct si_pm4_state
*pm4
= &rs
->pm4
;
518 unsigned prov_vtx
= 1, polygon_dual_mode
;
520 float psize_min
, psize_max
;
526 rs
->two_side
= state
->light_twoside
;
527 rs
->multisample_enable
= state
->multisample
;
528 rs
->clip_plane_enable
= state
->clip_plane_enable
;
529 rs
->line_stipple_enable
= state
->line_stipple_enable
;
531 polygon_dual_mode
= (state
->fill_front
!= PIPE_POLYGON_MODE_FILL
||
532 state
->fill_back
!= PIPE_POLYGON_MODE_FILL
);
534 if (state
->flatshade_first
)
537 rs
->flatshade
= state
->flatshade
;
538 rs
->sprite_coord_enable
= state
->sprite_coord_enable
;
539 rs
->pa_sc_line_stipple
= state
->line_stipple_enable
?
540 S_028A0C_LINE_PATTERN(state
->line_stipple_pattern
) |
541 S_028A0C_REPEAT_COUNT(state
->line_stipple_factor
) : 0;
542 rs
->pa_su_sc_mode_cntl
=
543 S_028814_PROVOKING_VTX_LAST(prov_vtx
) |
544 S_028814_CULL_FRONT(state
->rasterizer_discard
|| (state
->cull_face
& PIPE_FACE_FRONT
) ? 1 : 0) |
545 S_028814_CULL_BACK(state
->rasterizer_discard
|| (state
->cull_face
& PIPE_FACE_BACK
) ? 1 : 0) |
546 S_028814_FACE(!state
->front_ccw
) |
547 S_028814_POLY_OFFSET_FRONT_ENABLE(state
->offset_tri
) |
548 S_028814_POLY_OFFSET_BACK_ENABLE(state
->offset_tri
) |
549 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_tri
) |
550 S_028814_POLY_MODE(polygon_dual_mode
) |
551 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state
->fill_front
)) |
552 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state
->fill_back
));
553 rs
->pa_cl_clip_cntl
=
554 S_028810_PS_UCP_MODE(3) |
555 S_028810_ZCLIP_NEAR_DISABLE(!state
->depth_clip
) |
556 S_028810_ZCLIP_FAR_DISABLE(!state
->depth_clip
) |
557 S_028810_DX_RASTERIZATION_KILL(state
->rasterizer_discard
) |
558 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
560 clip_rule
= state
->scissor
? 0xAAAA : 0xFFFF;
563 rs
->offset_units
= state
->offset_units
;
564 rs
->offset_scale
= state
->offset_scale
* 12.0f
;
566 tmp
= S_0286D4_FLAT_SHADE_ENA(1);
567 if (state
->sprite_coord_enable
) {
568 tmp
|= S_0286D4_PNT_SPRITE_ENA(1) |
569 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S
) |
570 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T
) |
571 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0
) |
572 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1
);
573 if (state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
) {
574 tmp
|= S_0286D4_PNT_SPRITE_TOP_1(1);
577 si_pm4_set_reg(pm4
, R_0286D4_SPI_INTERP_CONTROL_0
, tmp
);
579 si_pm4_set_reg(pm4
, R_028820_PA_CL_NANINF_CNTL
, 0x00000000);
580 /* point size 12.4 fixed point */
581 tmp
= (unsigned)(state
->point_size
* 8.0);
582 si_pm4_set_reg(pm4
, R_028A00_PA_SU_POINT_SIZE
, S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
));
584 if (state
->point_size_per_vertex
) {
585 psize_min
= util_get_min_point_size(state
);
588 /* Force the point size to be as if the vertex output was disabled. */
589 psize_min
= state
->point_size
;
590 psize_max
= state
->point_size
;
592 /* Divide by two, because 0.5 = 1 pixel. */
593 si_pm4_set_reg(pm4
, R_028A04_PA_SU_POINT_MINMAX
,
594 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min
/2)) |
595 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max
/2)));
597 tmp
= (unsigned)state
->line_width
* 8;
598 si_pm4_set_reg(pm4
, R_028A08_PA_SU_LINE_CNTL
, S_028A08_WIDTH(tmp
));
599 si_pm4_set_reg(pm4
, R_028A48_PA_SC_MODE_CNTL_0
,
600 S_028A48_LINE_STIPPLE_ENABLE(state
->line_stipple_enable
) |
601 S_028A48_MSAA_ENABLE(state
->multisample
));
603 si_pm4_set_reg(pm4
, R_028BE4_PA_SU_VTX_CNTL
,
604 S_028BE4_PIX_CENTER(state
->half_pixel_center
) |
605 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH
));
606 si_pm4_set_reg(pm4
, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ
, 0x3F800000);
607 si_pm4_set_reg(pm4
, R_028BEC_PA_CL_GB_VERT_DISC_ADJ
, 0x3F800000);
608 si_pm4_set_reg(pm4
, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ
, 0x3F800000);
609 si_pm4_set_reg(pm4
, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ
, 0x3F800000);
611 si_pm4_set_reg(pm4
, R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, fui(state
->offset_clamp
));
612 si_pm4_set_reg(pm4
, R_02820C_PA_SC_CLIPRECT_RULE
, clip_rule
);
617 static void si_bind_rs_state(struct pipe_context
*ctx
, void *state
)
619 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
620 struct si_state_rasterizer
*rs
= (struct si_state_rasterizer
*)state
;
626 rctx
->sprite_coord_enable
= rs
->sprite_coord_enable
;
627 rctx
->pa_sc_line_stipple
= rs
->pa_sc_line_stipple
;
628 rctx
->pa_su_sc_mode_cntl
= rs
->pa_su_sc_mode_cntl
;
630 si_pm4_bind_state(rctx
, rasterizer
, rs
);
631 si_update_fb_rs_state(rctx
);
634 static void si_delete_rs_state(struct pipe_context
*ctx
, void *state
)
636 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
637 si_pm4_delete_state(rctx
, rasterizer
, (struct si_state_rasterizer
*)state
);
641 * infeered state between dsa and stencil ref
643 static void si_update_dsa_stencil_ref(struct r600_context
*rctx
)
645 struct si_pm4_state
*pm4
= si_pm4_alloc_state(rctx
);
646 struct pipe_stencil_ref
*ref
= &rctx
->stencil_ref
;
647 struct si_state_dsa
*dsa
= rctx
->queued
.named
.dsa
;
652 si_pm4_set_reg(pm4
, R_028430_DB_STENCILREFMASK
,
653 S_028430_STENCILTESTVAL(ref
->ref_value
[0]) |
654 S_028430_STENCILMASK(dsa
->valuemask
[0]) |
655 S_028430_STENCILWRITEMASK(dsa
->writemask
[0]) |
656 S_028430_STENCILOPVAL(1));
657 si_pm4_set_reg(pm4
, R_028434_DB_STENCILREFMASK_BF
,
658 S_028434_STENCILTESTVAL_BF(ref
->ref_value
[1]) |
659 S_028434_STENCILMASK_BF(dsa
->valuemask
[1]) |
660 S_028434_STENCILWRITEMASK_BF(dsa
->writemask
[1]) |
661 S_028434_STENCILOPVAL_BF(1));
663 si_pm4_set_state(rctx
, dsa_stencil_ref
, pm4
);
666 static void si_set_pipe_stencil_ref(struct pipe_context
*ctx
,
667 const struct pipe_stencil_ref
*state
)
669 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
670 rctx
->stencil_ref
= *state
;
671 si_update_dsa_stencil_ref(rctx
);
679 static uint32_t si_translate_stencil_op(int s_op
)
682 case PIPE_STENCIL_OP_KEEP
:
683 return V_02842C_STENCIL_KEEP
;
684 case PIPE_STENCIL_OP_ZERO
:
685 return V_02842C_STENCIL_ZERO
;
686 case PIPE_STENCIL_OP_REPLACE
:
687 return V_02842C_STENCIL_REPLACE_TEST
;
688 case PIPE_STENCIL_OP_INCR
:
689 return V_02842C_STENCIL_ADD_CLAMP
;
690 case PIPE_STENCIL_OP_DECR
:
691 return V_02842C_STENCIL_SUB_CLAMP
;
692 case PIPE_STENCIL_OP_INCR_WRAP
:
693 return V_02842C_STENCIL_ADD_WRAP
;
694 case PIPE_STENCIL_OP_DECR_WRAP
:
695 return V_02842C_STENCIL_SUB_WRAP
;
696 case PIPE_STENCIL_OP_INVERT
:
697 return V_02842C_STENCIL_INVERT
;
699 R600_ERR("Unknown stencil op %d", s_op
);
706 static void *si_create_dsa_state(struct pipe_context
*ctx
,
707 const struct pipe_depth_stencil_alpha_state
*state
)
709 struct si_state_dsa
*dsa
= CALLOC_STRUCT(si_state_dsa
);
710 struct si_pm4_state
*pm4
= &dsa
->pm4
;
711 unsigned db_depth_control
;
712 unsigned db_render_control
;
713 uint32_t db_stencil_control
= 0;
719 dsa
->valuemask
[0] = state
->stencil
[0].valuemask
;
720 dsa
->valuemask
[1] = state
->stencil
[1].valuemask
;
721 dsa
->writemask
[0] = state
->stencil
[0].writemask
;
722 dsa
->writemask
[1] = state
->stencil
[1].writemask
;
724 db_depth_control
= S_028800_Z_ENABLE(state
->depth
.enabled
) |
725 S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
726 S_028800_ZFUNC(state
->depth
.func
);
729 if (state
->stencil
[0].enabled
) {
730 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
731 db_depth_control
|= S_028800_STENCILFUNC(state
->stencil
[0].func
);
732 db_stencil_control
|= S_02842C_STENCILFAIL(si_translate_stencil_op(state
->stencil
[0].fail_op
));
733 db_stencil_control
|= S_02842C_STENCILZPASS(si_translate_stencil_op(state
->stencil
[0].zpass_op
));
734 db_stencil_control
|= S_02842C_STENCILZFAIL(si_translate_stencil_op(state
->stencil
[0].zfail_op
));
736 if (state
->stencil
[1].enabled
) {
737 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
738 db_depth_control
|= S_028800_STENCILFUNC_BF(state
->stencil
[1].func
);
739 db_stencil_control
|= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state
->stencil
[1].fail_op
));
740 db_stencil_control
|= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state
->stencil
[1].zpass_op
));
741 db_stencil_control
|= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state
->stencil
[1].zfail_op
));
746 if (state
->alpha
.enabled
) {
747 dsa
->alpha_func
= state
->alpha
.func
;
748 dsa
->alpha_ref
= state
->alpha
.ref_value
;
750 si_pm4_set_reg(pm4
, R_00B030_SPI_SHADER_USER_DATA_PS_0
+
751 SI_SGPR_ALPHA_REF
* 4, fui(dsa
->alpha_ref
));
753 dsa
->alpha_func
= PIPE_FUNC_ALWAYS
;
757 db_render_control
= 0;
758 si_pm4_set_reg(pm4
, R_028020_DB_DEPTH_BOUNDS_MIN
, 0x00000000);
759 si_pm4_set_reg(pm4
, R_028024_DB_DEPTH_BOUNDS_MAX
, 0x00000000);
760 si_pm4_set_reg(pm4
, R_028028_DB_STENCIL_CLEAR
, 0x00000000);
761 si_pm4_set_reg(pm4
, R_02802C_DB_DEPTH_CLEAR
, 0x3F800000);
762 //si_pm4_set_reg(pm4, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control);
763 si_pm4_set_reg(pm4
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
764 si_pm4_set_reg(pm4
, R_028000_DB_RENDER_CONTROL
, db_render_control
);
765 si_pm4_set_reg(pm4
, R_02842C_DB_STENCIL_CONTROL
, db_stencil_control
);
766 si_pm4_set_reg(pm4
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 0x0);
767 si_pm4_set_reg(pm4
, R_028AC4_DB_SRESULTS_COMPARE_STATE1
, 0x0);
768 si_pm4_set_reg(pm4
, R_028AC8_DB_PRELOAD_CONTROL
, 0x0);
773 static void si_bind_dsa_state(struct pipe_context
*ctx
, void *state
)
775 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
776 struct si_state_dsa
*dsa
= state
;
781 si_pm4_bind_state(rctx
, dsa
, dsa
);
782 si_update_dsa_stencil_ref(rctx
);
785 static void si_delete_dsa_state(struct pipe_context
*ctx
, void *state
)
787 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
788 si_pm4_delete_state(rctx
, dsa
, (struct si_state_dsa
*)state
);
791 static void *si_create_db_flush_dsa(struct r600_context
*rctx
, bool copy_depth
,
792 bool copy_stencil
, int sample
)
794 struct pipe_depth_stencil_alpha_state dsa
;
795 struct si_state_dsa
*state
;
797 memset(&dsa
, 0, sizeof(dsa
));
799 state
= rctx
->b
.b
.create_depth_stencil_alpha_state(&rctx
->b
.b
, &dsa
);
800 if (copy_depth
|| copy_stencil
) {
801 si_pm4_set_reg(&state
->pm4
, R_028000_DB_RENDER_CONTROL
,
802 S_028000_DEPTH_COPY(copy_depth
) |
803 S_028000_STENCIL_COPY(copy_stencil
) |
804 S_028000_COPY_CENTROID(1) |
805 S_028000_COPY_SAMPLE(sample
));
807 si_pm4_set_reg(&state
->pm4
, R_028000_DB_RENDER_CONTROL
,
808 S_028000_DEPTH_COMPRESS_DISABLE(1) |
809 S_028000_STENCIL_COMPRESS_DISABLE(1));
810 si_pm4_set_reg(&state
->pm4
, R_02800C_DB_RENDER_OVERRIDE
,
811 S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE
) |
812 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE
) |
813 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE
) |
814 S_02800C_DISABLE_TILE_RATE_TILES(1));
823 static uint32_t si_translate_colorformat(enum pipe_format format
)
825 const struct util_format_description
*desc
= util_format_description(format
);
827 #define HAS_SIZE(x,y,z,w) \
828 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
829 desc->channel[2].size == (z) && desc->channel[3].size == (w))
831 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
832 return V_028C70_COLOR_10_11_11
;
834 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
835 return V_028C70_COLOR_INVALID
;
837 switch (desc
->nr_channels
) {
839 switch (desc
->channel
[0].size
) {
841 return V_028C70_COLOR_8
;
843 return V_028C70_COLOR_16
;
845 return V_028C70_COLOR_32
;
849 if (desc
->channel
[0].size
== desc
->channel
[1].size
) {
850 switch (desc
->channel
[0].size
) {
852 return V_028C70_COLOR_8_8
;
854 return V_028C70_COLOR_16_16
;
856 return V_028C70_COLOR_32_32
;
858 } else if (HAS_SIZE(8,24,0,0)) {
859 return V_028C70_COLOR_24_8
;
860 } else if (HAS_SIZE(24,8,0,0)) {
861 return V_028C70_COLOR_8_24
;
865 if (HAS_SIZE(5,6,5,0)) {
866 return V_028C70_COLOR_5_6_5
;
867 } else if (HAS_SIZE(32,8,24,0)) {
868 return V_028C70_COLOR_X24_8_32_FLOAT
;
872 if (desc
->channel
[0].size
== desc
->channel
[1].size
&&
873 desc
->channel
[0].size
== desc
->channel
[2].size
&&
874 desc
->channel
[0].size
== desc
->channel
[3].size
) {
875 switch (desc
->channel
[0].size
) {
877 return V_028C70_COLOR_4_4_4_4
;
879 return V_028C70_COLOR_8_8_8_8
;
881 return V_028C70_COLOR_16_16_16_16
;
883 return V_028C70_COLOR_32_32_32_32
;
885 } else if (HAS_SIZE(5,5,5,1)) {
886 return V_028C70_COLOR_1_5_5_5
;
887 } else if (HAS_SIZE(10,10,10,2)) {
888 return V_028C70_COLOR_2_10_10_10
;
892 return V_028C70_COLOR_INVALID
;
895 static uint32_t si_translate_colorswap(enum pipe_format format
)
897 const struct util_format_description
*desc
= util_format_description(format
);
899 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == UTIL_FORMAT_SWIZZLE_##swz)
901 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
902 return V_028C70_SWAP_STD
;
904 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
907 switch (desc
->nr_channels
) {
909 if (HAS_SWIZZLE(0,X
))
910 return V_028C70_SWAP_STD
; /* X___ */
911 else if (HAS_SWIZZLE(3,X
))
912 return V_028C70_SWAP_ALT_REV
; /* ___X */
915 if ((HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,Y
)) ||
916 (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,NONE
)) ||
917 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,Y
)))
918 return V_028C70_SWAP_STD
; /* XY__ */
919 else if ((HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,X
)) ||
920 (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,NONE
)) ||
921 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,X
)))
922 return V_028C70_SWAP_STD_REV
; /* YX__ */
923 else if (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(3,Y
))
924 return V_028C70_SWAP_ALT
; /* X__Y */
927 if (HAS_SWIZZLE(0,X
))
928 return V_028C70_SWAP_STD
; /* XYZ */
929 else if (HAS_SWIZZLE(0,Z
))
930 return V_028C70_SWAP_STD_REV
; /* ZYX */
933 /* check the middle channels, the 1st and 4th channel can be NONE */
934 if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,Z
))
935 return V_028C70_SWAP_STD
; /* XYZW */
936 else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,Y
))
937 return V_028C70_SWAP_STD_REV
; /* WZYX */
938 else if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,X
))
939 return V_028C70_SWAP_ALT
; /* ZYXW */
940 else if (HAS_SWIZZLE(1,X
) && HAS_SWIZZLE(2,Y
))
941 return V_028C70_SWAP_ALT_REV
; /* WXYZ */
947 static uint32_t si_colorformat_endian_swap(uint32_t colorformat
)
949 if (R600_BIG_ENDIAN
) {
950 switch(colorformat
) {
952 case V_028C70_COLOR_8
:
953 return V_028C70_ENDIAN_NONE
;
955 /* 16-bit buffers. */
956 case V_028C70_COLOR_5_6_5
:
957 case V_028C70_COLOR_1_5_5_5
:
958 case V_028C70_COLOR_4_4_4_4
:
959 case V_028C70_COLOR_16
:
960 case V_028C70_COLOR_8_8
:
961 return V_028C70_ENDIAN_8IN16
;
963 /* 32-bit buffers. */
964 case V_028C70_COLOR_8_8_8_8
:
965 case V_028C70_COLOR_2_10_10_10
:
966 case V_028C70_COLOR_8_24
:
967 case V_028C70_COLOR_24_8
:
968 case V_028C70_COLOR_16_16
:
969 return V_028C70_ENDIAN_8IN32
;
971 /* 64-bit buffers. */
972 case V_028C70_COLOR_16_16_16_16
:
973 return V_028C70_ENDIAN_8IN16
;
975 case V_028C70_COLOR_32_32
:
976 return V_028C70_ENDIAN_8IN32
;
978 /* 128-bit buffers. */
979 case V_028C70_COLOR_32_32_32_32
:
980 return V_028C70_ENDIAN_8IN32
;
982 return V_028C70_ENDIAN_NONE
; /* Unsupported. */
985 return V_028C70_ENDIAN_NONE
;
989 /* Returns the size in bits of the widest component of a CB format */
990 static unsigned si_colorformat_max_comp_size(uint32_t colorformat
)
992 switch(colorformat
) {
993 case V_028C70_COLOR_4_4_4_4
:
996 case V_028C70_COLOR_1_5_5_5
:
997 case V_028C70_COLOR_5_5_5_1
:
1000 case V_028C70_COLOR_5_6_5
:
1003 case V_028C70_COLOR_8
:
1004 case V_028C70_COLOR_8_8
:
1005 case V_028C70_COLOR_8_8_8_8
:
1008 case V_028C70_COLOR_10_10_10_2
:
1009 case V_028C70_COLOR_2_10_10_10
:
1012 case V_028C70_COLOR_10_11_11
:
1013 case V_028C70_COLOR_11_11_10
:
1016 case V_028C70_COLOR_16
:
1017 case V_028C70_COLOR_16_16
:
1018 case V_028C70_COLOR_16_16_16_16
:
1021 case V_028C70_COLOR_8_24
:
1022 case V_028C70_COLOR_24_8
:
1025 case V_028C70_COLOR_32
:
1026 case V_028C70_COLOR_32_32
:
1027 case V_028C70_COLOR_32_32_32_32
:
1028 case V_028C70_COLOR_X24_8_32_FLOAT
:
1032 assert(!"Unknown maximum component size");
1036 static uint32_t si_translate_dbformat(enum pipe_format format
)
1039 case PIPE_FORMAT_Z16_UNORM
:
1040 return V_028040_Z_16
;
1041 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1042 case PIPE_FORMAT_X8Z24_UNORM
:
1043 case PIPE_FORMAT_Z24X8_UNORM
:
1044 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1045 return V_028040_Z_24
; /* deprecated on SI */
1046 case PIPE_FORMAT_Z32_FLOAT
:
1047 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1048 return V_028040_Z_32_FLOAT
;
1050 return V_028040_Z_INVALID
;
1055 * Texture translation
1058 static uint32_t si_translate_texformat(struct pipe_screen
*screen
,
1059 enum pipe_format format
,
1060 const struct util_format_description
*desc
,
1063 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
1064 bool enable_s3tc
= rscreen
->b
.info
.drm_minor
>= 31;
1065 boolean uniform
= TRUE
;
1068 /* Colorspace (return non-RGB formats directly). */
1069 switch (desc
->colorspace
) {
1070 /* Depth stencil formats */
1071 case UTIL_FORMAT_COLORSPACE_ZS
:
1073 case PIPE_FORMAT_Z16_UNORM
:
1074 return V_008F14_IMG_DATA_FORMAT_16
;
1075 case PIPE_FORMAT_X24S8_UINT
:
1076 case PIPE_FORMAT_Z24X8_UNORM
:
1077 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1078 return V_008F14_IMG_DATA_FORMAT_8_24
;
1079 case PIPE_FORMAT_X8Z24_UNORM
:
1080 case PIPE_FORMAT_S8X24_UINT
:
1081 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1082 return V_008F14_IMG_DATA_FORMAT_24_8
;
1083 case PIPE_FORMAT_S8_UINT
:
1084 return V_008F14_IMG_DATA_FORMAT_8
;
1085 case PIPE_FORMAT_Z32_FLOAT
:
1086 return V_008F14_IMG_DATA_FORMAT_32
;
1087 case PIPE_FORMAT_X32_S8X24_UINT
:
1088 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1089 return V_008F14_IMG_DATA_FORMAT_X24_8_32
;
1094 case UTIL_FORMAT_COLORSPACE_YUV
:
1095 goto out_unknown
; /* TODO */
1097 case UTIL_FORMAT_COLORSPACE_SRGB
:
1098 if (desc
->nr_channels
!= 4 && desc
->nr_channels
!= 1)
1106 if (desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
) {
1111 case PIPE_FORMAT_RGTC1_SNORM
:
1112 case PIPE_FORMAT_LATC1_SNORM
:
1113 case PIPE_FORMAT_RGTC1_UNORM
:
1114 case PIPE_FORMAT_LATC1_UNORM
:
1115 return V_008F14_IMG_DATA_FORMAT_BC4
;
1116 case PIPE_FORMAT_RGTC2_SNORM
:
1117 case PIPE_FORMAT_LATC2_SNORM
:
1118 case PIPE_FORMAT_RGTC2_UNORM
:
1119 case PIPE_FORMAT_LATC2_UNORM
:
1120 return V_008F14_IMG_DATA_FORMAT_BC5
;
1126 if (desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
1131 if (!util_format_s3tc_enabled
) {
1136 case PIPE_FORMAT_DXT1_RGB
:
1137 case PIPE_FORMAT_DXT1_RGBA
:
1138 case PIPE_FORMAT_DXT1_SRGB
:
1139 case PIPE_FORMAT_DXT1_SRGBA
:
1140 return V_008F14_IMG_DATA_FORMAT_BC1
;
1141 case PIPE_FORMAT_DXT3_RGBA
:
1142 case PIPE_FORMAT_DXT3_SRGBA
:
1143 return V_008F14_IMG_DATA_FORMAT_BC2
;
1144 case PIPE_FORMAT_DXT5_RGBA
:
1145 case PIPE_FORMAT_DXT5_SRGBA
:
1146 return V_008F14_IMG_DATA_FORMAT_BC3
;
1152 if (format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
1153 return V_008F14_IMG_DATA_FORMAT_5_9_9_9
;
1154 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
1155 return V_008F14_IMG_DATA_FORMAT_10_11_11
;
1158 /* R8G8Bx_SNORM - TODO CxV8U8 */
1160 /* See whether the components are of the same size. */
1161 for (i
= 1; i
< desc
->nr_channels
; i
++) {
1162 uniform
= uniform
&& desc
->channel
[0].size
== desc
->channel
[i
].size
;
1165 /* Non-uniform formats. */
1167 switch(desc
->nr_channels
) {
1169 if (desc
->channel
[0].size
== 5 &&
1170 desc
->channel
[1].size
== 6 &&
1171 desc
->channel
[2].size
== 5) {
1172 return V_008F14_IMG_DATA_FORMAT_5_6_5
;
1176 if (desc
->channel
[0].size
== 5 &&
1177 desc
->channel
[1].size
== 5 &&
1178 desc
->channel
[2].size
== 5 &&
1179 desc
->channel
[3].size
== 1) {
1180 return V_008F14_IMG_DATA_FORMAT_1_5_5_5
;
1182 if (desc
->channel
[0].size
== 10 &&
1183 desc
->channel
[1].size
== 10 &&
1184 desc
->channel
[2].size
== 10 &&
1185 desc
->channel
[3].size
== 2) {
1186 return V_008F14_IMG_DATA_FORMAT_2_10_10_10
;
1193 if (first_non_void
< 0 || first_non_void
> 3)
1196 /* uniform formats */
1197 switch (desc
->channel
[first_non_void
].size
) {
1199 switch (desc
->nr_channels
) {
1200 #if 0 /* Not supported for render targets */
1202 return V_008F14_IMG_DATA_FORMAT_4_4
;
1205 return V_008F14_IMG_DATA_FORMAT_4_4_4_4
;
1209 switch (desc
->nr_channels
) {
1211 return V_008F14_IMG_DATA_FORMAT_8
;
1213 return V_008F14_IMG_DATA_FORMAT_8_8
;
1215 return V_008F14_IMG_DATA_FORMAT_8_8_8_8
;
1219 switch (desc
->nr_channels
) {
1221 return V_008F14_IMG_DATA_FORMAT_16
;
1223 return V_008F14_IMG_DATA_FORMAT_16_16
;
1225 return V_008F14_IMG_DATA_FORMAT_16_16_16_16
;
1229 switch (desc
->nr_channels
) {
1231 return V_008F14_IMG_DATA_FORMAT_32
;
1233 return V_008F14_IMG_DATA_FORMAT_32_32
;
1234 #if 0 /* Not supported for render targets */
1236 return V_008F14_IMG_DATA_FORMAT_32_32_32
;
1239 return V_008F14_IMG_DATA_FORMAT_32_32_32_32
;
1244 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1248 static unsigned si_tex_wrap(unsigned wrap
)
1252 case PIPE_TEX_WRAP_REPEAT
:
1253 return V_008F30_SQ_TEX_WRAP
;
1254 case PIPE_TEX_WRAP_CLAMP
:
1255 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER
;
1256 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
1257 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL
;
1258 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
1259 return V_008F30_SQ_TEX_CLAMP_BORDER
;
1260 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
1261 return V_008F30_SQ_TEX_MIRROR
;
1262 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
1263 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
1264 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
1265 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
1266 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
1267 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER
;
1271 static unsigned si_tex_filter(unsigned filter
)
1275 case PIPE_TEX_FILTER_NEAREST
:
1276 return V_008F38_SQ_TEX_XY_FILTER_POINT
;
1277 case PIPE_TEX_FILTER_LINEAR
:
1278 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR
;
1282 static unsigned si_tex_mipfilter(unsigned filter
)
1285 case PIPE_TEX_MIPFILTER_NEAREST
:
1286 return V_008F38_SQ_TEX_Z_FILTER_POINT
;
1287 case PIPE_TEX_MIPFILTER_LINEAR
:
1288 return V_008F38_SQ_TEX_Z_FILTER_LINEAR
;
1290 case PIPE_TEX_MIPFILTER_NONE
:
1291 return V_008F38_SQ_TEX_Z_FILTER_NONE
;
1295 static unsigned si_tex_compare(unsigned compare
)
1299 case PIPE_FUNC_NEVER
:
1300 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
1301 case PIPE_FUNC_LESS
:
1302 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS
;
1303 case PIPE_FUNC_EQUAL
:
1304 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL
;
1305 case PIPE_FUNC_LEQUAL
:
1306 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
1307 case PIPE_FUNC_GREATER
:
1308 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER
;
1309 case PIPE_FUNC_NOTEQUAL
:
1310 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
1311 case PIPE_FUNC_GEQUAL
:
1312 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
1313 case PIPE_FUNC_ALWAYS
:
1314 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
1318 static unsigned si_tex_dim(unsigned dim
, unsigned nr_samples
)
1322 case PIPE_TEXTURE_1D
:
1323 return V_008F1C_SQ_RSRC_IMG_1D
;
1324 case PIPE_TEXTURE_1D_ARRAY
:
1325 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY
;
1326 case PIPE_TEXTURE_2D
:
1327 case PIPE_TEXTURE_RECT
:
1328 return nr_samples
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA
:
1329 V_008F1C_SQ_RSRC_IMG_2D
;
1330 case PIPE_TEXTURE_2D_ARRAY
:
1331 return nr_samples
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
:
1332 V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
1333 case PIPE_TEXTURE_3D
:
1334 return V_008F1C_SQ_RSRC_IMG_3D
;
1335 case PIPE_TEXTURE_CUBE
:
1336 return V_008F1C_SQ_RSRC_IMG_CUBE
;
1341 * Format support testing
1344 static bool si_is_sampler_format_supported(struct pipe_screen
*screen
, enum pipe_format format
)
1346 return si_translate_texformat(screen
, format
, util_format_description(format
),
1347 util_format_get_first_non_void_channel(format
)) != ~0U;
1350 static uint32_t si_translate_buffer_dataformat(struct pipe_screen
*screen
,
1351 const struct util_format_description
*desc
,
1354 unsigned type
= desc
->channel
[first_non_void
].type
;
1357 if (type
== UTIL_FORMAT_TYPE_FIXED
)
1358 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
1360 if (desc
->nr_channels
== 4 &&
1361 desc
->channel
[0].size
== 10 &&
1362 desc
->channel
[1].size
== 10 &&
1363 desc
->channel
[2].size
== 10 &&
1364 desc
->channel
[3].size
== 2)
1365 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10
;
1367 /* See whether the components are of the same size. */
1368 for (i
= 0; i
< desc
->nr_channels
; i
++) {
1369 if (desc
->channel
[first_non_void
].size
!= desc
->channel
[i
].size
)
1370 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
1373 switch (desc
->channel
[first_non_void
].size
) {
1375 switch (desc
->nr_channels
) {
1377 return V_008F0C_BUF_DATA_FORMAT_8
;
1379 return V_008F0C_BUF_DATA_FORMAT_8_8
;
1382 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8
;
1386 switch (desc
->nr_channels
) {
1388 return V_008F0C_BUF_DATA_FORMAT_16
;
1390 return V_008F0C_BUF_DATA_FORMAT_16_16
;
1393 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16
;
1397 /* From the Southern Islands ISA documentation about MTBUF:
1398 * 'Memory reads of data in memory that is 32 or 64 bits do not
1399 * undergo any format conversion.'
1401 if (type
!= UTIL_FORMAT_TYPE_FLOAT
&&
1402 !desc
->channel
[first_non_void
].pure_integer
)
1403 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
1405 switch (desc
->nr_channels
) {
1407 return V_008F0C_BUF_DATA_FORMAT_32
;
1409 return V_008F0C_BUF_DATA_FORMAT_32_32
;
1411 return V_008F0C_BUF_DATA_FORMAT_32_32_32
;
1413 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
1418 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
1421 static uint32_t si_translate_buffer_numformat(struct pipe_screen
*screen
,
1422 const struct util_format_description
*desc
,
1425 switch (desc
->channel
[first_non_void
].type
) {
1426 case UTIL_FORMAT_TYPE_SIGNED
:
1427 if (desc
->channel
[first_non_void
].normalized
)
1428 return V_008F0C_BUF_NUM_FORMAT_SNORM
;
1429 else if (desc
->channel
[first_non_void
].pure_integer
)
1430 return V_008F0C_BUF_NUM_FORMAT_SINT
;
1432 return V_008F0C_BUF_NUM_FORMAT_SSCALED
;
1434 case UTIL_FORMAT_TYPE_UNSIGNED
:
1435 if (desc
->channel
[first_non_void
].normalized
)
1436 return V_008F0C_BUF_NUM_FORMAT_UNORM
;
1437 else if (desc
->channel
[first_non_void
].pure_integer
)
1438 return V_008F0C_BUF_NUM_FORMAT_UINT
;
1440 return V_008F0C_BUF_NUM_FORMAT_USCALED
;
1442 case UTIL_FORMAT_TYPE_FLOAT
:
1444 return V_008F0C_BUF_NUM_FORMAT_FLOAT
;
1448 static bool si_is_vertex_format_supported(struct pipe_screen
*screen
, enum pipe_format format
)
1450 const struct util_format_description
*desc
;
1452 unsigned data_format
;
1454 desc
= util_format_description(format
);
1455 first_non_void
= util_format_get_first_non_void_channel(format
);
1456 data_format
= si_translate_buffer_dataformat(screen
, desc
, first_non_void
);
1457 return data_format
!= V_008F0C_BUF_DATA_FORMAT_INVALID
;
1460 static bool si_is_colorbuffer_format_supported(enum pipe_format format
)
1462 return si_translate_colorformat(format
) != V_028C70_COLOR_INVALID
&&
1463 si_translate_colorswap(format
) != ~0U;
1466 static bool si_is_zs_format_supported(enum pipe_format format
)
1468 return si_translate_dbformat(format
) != V_028040_Z_INVALID
;
1471 boolean
si_is_format_supported(struct pipe_screen
*screen
,
1472 enum pipe_format format
,
1473 enum pipe_texture_target target
,
1474 unsigned sample_count
,
1477 struct r600_screen
*rscreen
= (struct r600_screen
*)screen
;
1478 unsigned retval
= 0;
1480 if (target
>= PIPE_MAX_TEXTURE_TYPES
) {
1481 R600_ERR("r600: unsupported texture type %d\n", target
);
1485 if (!util_format_is_supported(format
, usage
))
1488 if (sample_count
> 1) {
1489 if (HAVE_LLVM
< 0x0304)
1492 /* 2D tiling on CIK is supported since DRM 2.35.0 */
1493 if (rscreen
->b
.chip_class
>= CIK
&& rscreen
->b
.info
.drm_minor
< 35)
1496 switch (sample_count
) {
1506 if (usage
& PIPE_BIND_SAMPLER_VIEW
) {
1507 if (target
== PIPE_BUFFER
) {
1508 if (si_is_vertex_format_supported(screen
, format
))
1509 retval
|= PIPE_BIND_SAMPLER_VIEW
;
1511 if (si_is_sampler_format_supported(screen
, format
))
1512 retval
|= PIPE_BIND_SAMPLER_VIEW
;
1516 if ((usage
& (PIPE_BIND_RENDER_TARGET
|
1517 PIPE_BIND_DISPLAY_TARGET
|
1519 PIPE_BIND_SHARED
)) &&
1520 si_is_colorbuffer_format_supported(format
)) {
1522 (PIPE_BIND_RENDER_TARGET
|
1523 PIPE_BIND_DISPLAY_TARGET
|
1528 if ((usage
& PIPE_BIND_DEPTH_STENCIL
) &&
1529 si_is_zs_format_supported(format
)) {
1530 retval
|= PIPE_BIND_DEPTH_STENCIL
;
1533 if ((usage
& PIPE_BIND_VERTEX_BUFFER
) &&
1534 si_is_vertex_format_supported(screen
, format
)) {
1535 retval
|= PIPE_BIND_VERTEX_BUFFER
;
1538 if (usage
& PIPE_BIND_TRANSFER_READ
)
1539 retval
|= PIPE_BIND_TRANSFER_READ
;
1540 if (usage
& PIPE_BIND_TRANSFER_WRITE
)
1541 retval
|= PIPE_BIND_TRANSFER_WRITE
;
1543 return retval
== usage
;
1546 static unsigned si_tile_mode_index(struct r600_texture
*rtex
, unsigned level
, bool stencil
)
1548 unsigned tile_mode_index
= 0;
1551 tile_mode_index
= rtex
->surface
.stencil_tiling_index
[level
];
1553 tile_mode_index
= rtex
->surface
.tiling_index
[level
];
1555 return tile_mode_index
;
1559 * framebuffer handling
1562 static void si_cb(struct r600_context
*rctx
, struct si_pm4_state
*pm4
,
1563 const struct pipe_framebuffer_state
*state
, int cb
)
1565 struct r600_texture
*rtex
;
1566 struct r600_surface
*surf
;
1567 unsigned level
= state
->cbufs
[cb
]->u
.tex
.level
;
1568 unsigned pitch
, slice
;
1569 unsigned color_info
, color_attrib
, color_pitch
, color_view
;
1570 unsigned tile_mode_index
;
1571 unsigned format
, swap
, ntype
, endian
;
1573 const struct util_format_description
*desc
;
1575 unsigned blend_clamp
= 0, blend_bypass
= 0;
1576 unsigned max_comp_size
;
1578 surf
= (struct r600_surface
*)state
->cbufs
[cb
];
1579 rtex
= (struct r600_texture
*)state
->cbufs
[cb
]->texture
;
1581 offset
= rtex
->surface
.level
[level
].offset
;
1583 /* Layered rendering doesn't work with LINEAR_GENERAL.
1584 * (LINEAR_ALIGNED and others work) */
1585 if (rtex
->surface
.level
[level
].mode
== RADEON_SURF_MODE_LINEAR
) {
1586 assert(state
->cbufs
[cb
]->u
.tex
.first_layer
== state
->cbufs
[cb
]->u
.tex
.last_layer
);
1587 offset
+= rtex
->surface
.level
[level
].slice_size
*
1588 state
->cbufs
[cb
]->u
.tex
.first_layer
;
1591 color_view
= S_028C6C_SLICE_START(state
->cbufs
[cb
]->u
.tex
.first_layer
) |
1592 S_028C6C_SLICE_MAX(state
->cbufs
[cb
]->u
.tex
.last_layer
);
1595 pitch
= (rtex
->surface
.level
[level
].nblk_x
) / 8 - 1;
1596 slice
= (rtex
->surface
.level
[level
].nblk_x
* rtex
->surface
.level
[level
].nblk_y
) / 64;
1601 tile_mode_index
= si_tile_mode_index(rtex
, level
, false);
1603 desc
= util_format_description(surf
->base
.format
);
1604 for (i
= 0; i
< 4; i
++) {
1605 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
1609 if (i
== 4 || desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
) {
1610 ntype
= V_028C70_NUMBER_FLOAT
;
1612 ntype
= V_028C70_NUMBER_UNORM
;
1613 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
1614 ntype
= V_028C70_NUMBER_SRGB
;
1615 else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
1616 if (desc
->channel
[i
].pure_integer
) {
1617 ntype
= V_028C70_NUMBER_SINT
;
1619 assert(desc
->channel
[i
].normalized
);
1620 ntype
= V_028C70_NUMBER_SNORM
;
1622 } else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
1623 if (desc
->channel
[i
].pure_integer
) {
1624 ntype
= V_028C70_NUMBER_UINT
;
1626 assert(desc
->channel
[i
].normalized
);
1627 ntype
= V_028C70_NUMBER_UNORM
;
1632 format
= si_translate_colorformat(surf
->base
.format
);
1633 if (format
== V_028C70_COLOR_INVALID
) {
1634 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf
->base
.format
);
1636 assert(format
!= V_028C70_COLOR_INVALID
);
1637 swap
= si_translate_colorswap(surf
->base
.format
);
1638 if (rtex
->resource
.b
.b
.usage
== PIPE_USAGE_STAGING
) {
1639 endian
= V_028C70_ENDIAN_NONE
;
1641 endian
= si_colorformat_endian_swap(format
);
1644 /* blend clamp should be set for all NORM/SRGB types */
1645 if (ntype
== V_028C70_NUMBER_UNORM
||
1646 ntype
== V_028C70_NUMBER_SNORM
||
1647 ntype
== V_028C70_NUMBER_SRGB
)
1650 /* set blend bypass according to docs if SINT/UINT or
1651 8/24 COLOR variants */
1652 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
1653 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
1654 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
1659 color_info
= S_028C70_FORMAT(format
) |
1660 S_028C70_COMP_SWAP(swap
) |
1661 S_028C70_BLEND_CLAMP(blend_clamp
) |
1662 S_028C70_BLEND_BYPASS(blend_bypass
) |
1663 S_028C70_NUMBER_TYPE(ntype
) |
1664 S_028C70_ENDIAN(endian
);
1666 color_pitch
= S_028C64_TILE_MAX(pitch
);
1668 color_attrib
= S_028C74_TILE_MODE_INDEX(tile_mode_index
) |
1669 S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] == UTIL_FORMAT_SWIZZLE_1
);
1671 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
1672 unsigned log_samples
= util_logbase2(rtex
->resource
.b
.b
.nr_samples
);
1674 color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
1675 S_028C74_NUM_FRAGMENTS(log_samples
);
1677 if (rtex
->fmask
.size
) {
1678 color_info
|= S_028C70_COMPRESSION(1);
1679 unsigned fmask_bankh
= util_logbase2(rtex
->fmask
.bank_height
);
1681 color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(rtex
->fmask
.tile_mode_index
);
1683 if (rctx
->b
.chip_class
== SI
) {
1684 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
1685 color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh
);
1687 if (rctx
->b
.chip_class
>= CIK
) {
1688 color_pitch
|= S_028C64_FMASK_TILE_MAX(rtex
->fmask
.pitch
/ 8 - 1);
1693 if (rtex
->cmask
.size
) {
1694 color_info
|= S_028C70_FAST_CLEAR(1);
1697 offset
+= r600_resource_va(rctx
->b
.b
.screen
, state
->cbufs
[cb
]->texture
);
1700 si_pm4_add_bo(pm4
, &rtex
->resource
, RADEON_USAGE_READWRITE
);
1701 si_pm4_set_reg(pm4
, R_028C60_CB_COLOR0_BASE
+ cb
* 0x3C, offset
);
1702 si_pm4_set_reg(pm4
, R_028C64_CB_COLOR0_PITCH
+ cb
* 0x3C, color_pitch
);
1703 si_pm4_set_reg(pm4
, R_028C68_CB_COLOR0_SLICE
+ cb
* 0x3C, S_028C68_TILE_MAX(slice
));
1704 si_pm4_set_reg(pm4
, R_028C6C_CB_COLOR0_VIEW
+ cb
* 0x3C, color_view
);
1705 si_pm4_set_reg(pm4
, R_028C70_CB_COLOR0_INFO
+ cb
* 0x3C, color_info
);
1706 si_pm4_set_reg(pm4
, R_028C74_CB_COLOR0_ATTRIB
+ cb
* 0x3C, color_attrib
);
1708 if (rtex
->cmask
.size
) {
1709 si_pm4_set_reg(pm4
, R_028C7C_CB_COLOR0_CMASK
+ cb
* 0x3C,
1710 offset
+ (rtex
->cmask
.offset
>> 8));
1711 si_pm4_set_reg(pm4
, R_028C80_CB_COLOR0_CMASK_SLICE
+ cb
* 0x3C,
1712 S_028C80_TILE_MAX(rtex
->cmask
.slice_tile_max
));
1714 if (rtex
->fmask
.size
) {
1715 si_pm4_set_reg(pm4
, R_028C84_CB_COLOR0_FMASK
+ cb
* 0x3C,
1716 offset
+ (rtex
->fmask
.offset
>> 8));
1717 si_pm4_set_reg(pm4
, R_028C88_CB_COLOR0_FMASK_SLICE
+ cb
* 0x3C,
1718 S_028C88_TILE_MAX(rtex
->fmask
.slice_tile_max
));
1721 /* set CB_COLOR1_INFO for possible dual-src blending */
1722 if (state
->nr_cbufs
== 1) {
1724 si_pm4_set_reg(pm4
, R_028C70_CB_COLOR0_INFO
+ 1 * 0x3C, color_info
);
1727 /* Determine pixel shader export format */
1728 max_comp_size
= si_colorformat_max_comp_size(format
);
1729 if (ntype
== V_028C70_NUMBER_SRGB
||
1730 ((ntype
== V_028C70_NUMBER_UNORM
|| ntype
== V_028C70_NUMBER_SNORM
) &&
1731 max_comp_size
<= 10) ||
1732 (ntype
== V_028C70_NUMBER_FLOAT
&& max_comp_size
<= 16)) {
1733 rctx
->export_16bpc
|= 1 << cb
;
1734 /* set SPI_SHADER_COL_FORMAT for possible dual-src blending */
1735 if (state
->nr_cbufs
== 1)
1736 rctx
->export_16bpc
|= 1 << 1;
1740 /* Update register(s) containing depth buffer and draw state. */
1741 void si_update_db_draw_state(struct r600_context
*rctx
, struct r600_surface
*zsbuf
)
1743 struct si_pm4_state
*pm4
;
1744 uint32_t db_render_override
;
1745 boolean hiz_enable
= false;
1747 pm4
= si_pm4_alloc_state(rctx
);
1754 /* TODO HiS aka stencil buffer htile goes here */
1755 db_render_override
= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE
) |
1756 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE
);
1758 /* HiZ aka depth buffer htile */
1759 if (zsbuf
&& zsbuf
->base
.texture
) {
1760 struct r600_texture
*rtex
= (struct r600_texture
*)zsbuf
->base
.texture
;
1761 uint level
= zsbuf
->base
.u
.tex
.level
;
1762 /* use htile only for first level */
1763 hiz_enable
= rtex
->htile_buffer
&& !level
;
1766 db_render_override
|= S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_OFF
);
1768 db_render_override
|= S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE
);
1773 if (rctx
->num_cs_dw_nontimer_queries_suspend
) {
1774 db_render_override
|= S_02800C_NOOP_CULL_DISABLE(1);
1777 si_pm4_set_reg(pm4
, R_02800C_DB_RENDER_OVERRIDE
, db_render_override
);
1778 si_pm4_set_state(rctx
, db_draw
, pm4
);
1781 static void si_db(struct r600_context
*rctx
, struct si_pm4_state
*pm4
,
1782 const struct pipe_framebuffer_state
*state
)
1784 struct r600_screen
*rscreen
= rctx
->screen
;
1785 struct r600_texture
*rtex
;
1786 struct r600_surface
*surf
;
1787 unsigned level
, pitch
, slice
, format
, tile_mode_index
, array_mode
;
1788 unsigned macro_aspect
, tile_split
, stile_split
, bankh
, bankw
, nbanks
, pipe_config
;
1789 uint32_t z_info
, s_info
, db_depth_info
;
1790 uint64_t z_offs
, s_offs
;
1791 uint32_t db_htile_data_base
, db_htile_surface
;
1793 if (state
->zsbuf
== NULL
) {
1794 si_pm4_set_reg(pm4
, R_028040_DB_Z_INFO
, S_028040_FORMAT(V_028040_Z_INVALID
));
1795 si_pm4_set_reg(pm4
, R_028044_DB_STENCIL_INFO
, S_028044_FORMAT(V_028044_STENCIL_INVALID
));
1799 surf
= (struct r600_surface
*)state
->zsbuf
;
1800 level
= surf
->base
.u
.tex
.level
;
1801 rtex
= (struct r600_texture
*)surf
->base
.texture
;
1803 format
= si_translate_dbformat(rtex
->resource
.b
.b
.format
);
1805 if (format
== V_028040_Z_INVALID
) {
1806 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex
->resource
.b
.b
.format
);
1808 assert(format
!= V_028040_Z_INVALID
);
1810 s_offs
= z_offs
= r600_resource_va(rctx
->b
.b
.screen
, surf
->base
.texture
);
1811 z_offs
+= rtex
->surface
.level
[level
].offset
;
1812 s_offs
+= rtex
->surface
.stencil_level
[level
].offset
;
1817 pitch
= (rtex
->surface
.level
[level
].nblk_x
/ 8) - 1;
1818 slice
= (rtex
->surface
.level
[level
].nblk_x
* rtex
->surface
.level
[level
].nblk_y
) / 64;
1823 db_depth_info
= S_02803C_ADDR5_SWIZZLE_MASK(1);
1825 z_info
= S_028040_FORMAT(format
);
1826 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
1827 z_info
|= S_028040_NUM_SAMPLES(util_logbase2(rtex
->resource
.b
.b
.nr_samples
));
1830 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
)
1831 s_info
= S_028044_FORMAT(V_028044_STENCIL_8
);
1833 s_info
= S_028044_FORMAT(V_028044_STENCIL_INVALID
);
1835 if (rctx
->b
.chip_class
>= CIK
) {
1836 switch (rtex
->surface
.level
[level
].mode
) {
1837 case RADEON_SURF_MODE_2D
:
1838 array_mode
= V_02803C_ARRAY_2D_TILED_THIN1
;
1840 case RADEON_SURF_MODE_1D
:
1841 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1842 case RADEON_SURF_MODE_LINEAR
:
1844 array_mode
= V_02803C_ARRAY_1D_TILED_THIN1
;
1847 tile_split
= rtex
->surface
.tile_split
;
1848 stile_split
= rtex
->surface
.stencil_tile_split
;
1849 macro_aspect
= rtex
->surface
.mtilea
;
1850 bankw
= rtex
->surface
.bankw
;
1851 bankh
= rtex
->surface
.bankh
;
1852 tile_split
= cik_tile_split(tile_split
);
1853 stile_split
= cik_tile_split(stile_split
);
1854 macro_aspect
= cik_macro_tile_aspect(macro_aspect
);
1855 bankw
= cik_bank_wh(bankw
);
1856 bankh
= cik_bank_wh(bankh
);
1857 nbanks
= cik_num_banks(rscreen
->b
.tiling_info
.num_banks
);
1858 pipe_config
= cik_db_pipe_config(rscreen
->b
.info
.r600_num_tile_pipes
,
1859 rscreen
->b
.info
.r600_num_backends
);
1861 db_depth_info
|= S_02803C_ARRAY_MODE(array_mode
) |
1862 S_02803C_PIPE_CONFIG(pipe_config
) |
1863 S_02803C_BANK_WIDTH(bankw
) |
1864 S_02803C_BANK_HEIGHT(bankh
) |
1865 S_02803C_MACRO_TILE_ASPECT(macro_aspect
) |
1866 S_02803C_NUM_BANKS(nbanks
);
1867 z_info
|= S_028040_TILE_SPLIT(tile_split
);
1868 s_info
|= S_028044_TILE_SPLIT(stile_split
);
1870 tile_mode_index
= si_tile_mode_index(rtex
, level
, false);
1871 z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
1872 tile_mode_index
= si_tile_mode_index(rtex
, level
, true);
1873 s_info
|= S_028044_TILE_MODE_INDEX(tile_mode_index
);
1876 /* HiZ aka depth buffer htile */
1877 /* use htile only for first level */
1878 if (rtex
->htile_buffer
&& !level
) {
1879 z_info
|= S_028040_TILE_SURFACE_ENABLE(1);
1880 /* Force off means no force, DB_SHADER_CONTROL decides */
1881 uint64_t va
= r600_resource_va(&rctx
->screen
->b
.b
, &rtex
->htile_buffer
->b
.b
);
1882 db_htile_data_base
= va
>> 8;
1883 db_htile_surface
= S_028ABC_FULL_CACHE(1);
1885 db_htile_data_base
= 0;
1886 db_htile_surface
= 0;
1889 si_pm4_set_reg(pm4
, R_028008_DB_DEPTH_VIEW
,
1890 S_028008_SLICE_START(state
->zsbuf
->u
.tex
.first_layer
) |
1891 S_028008_SLICE_MAX(state
->zsbuf
->u
.tex
.last_layer
));
1892 si_pm4_set_reg(pm4
, R_028014_DB_HTILE_DATA_BASE
, db_htile_data_base
);
1894 si_pm4_set_reg(pm4
, R_02803C_DB_DEPTH_INFO
, db_depth_info
);
1895 si_pm4_set_reg(pm4
, R_028040_DB_Z_INFO
, z_info
);
1896 si_pm4_set_reg(pm4
, R_028044_DB_STENCIL_INFO
, s_info
);
1898 si_pm4_add_bo(pm4
, &rtex
->resource
, RADEON_USAGE_READWRITE
);
1899 si_pm4_set_reg(pm4
, R_028048_DB_Z_READ_BASE
, z_offs
);
1900 si_pm4_set_reg(pm4
, R_02804C_DB_STENCIL_READ_BASE
, s_offs
);
1901 si_pm4_set_reg(pm4
, R_028050_DB_Z_WRITE_BASE
, z_offs
);
1902 si_pm4_set_reg(pm4
, R_028054_DB_STENCIL_WRITE_BASE
, s_offs
);
1904 si_pm4_set_reg(pm4
, R_028058_DB_DEPTH_SIZE
, S_028058_PITCH_TILE_MAX(pitch
));
1905 si_pm4_set_reg(pm4
, R_02805C_DB_DEPTH_SLICE
, S_02805C_SLICE_TILE_MAX(slice
));
1907 si_pm4_set_reg(pm4
, R_028ABC_DB_HTILE_SURFACE
, db_htile_surface
);
1910 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1911 (((s0x) & 0xf) | (((s0y) & 0xf) << 4) | \
1912 (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) | \
1913 (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) | \
1914 (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
1917 * There are two locations (-4, 4), (4, -4). */
1918 static uint32_t sample_locs_2x
[] = {
1919 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1920 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1921 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1922 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1924 static unsigned max_dist_2x
= 4;
1926 * There are 4 locations: (-2, -2), (2, 2), (-6, 6), (6, -6). */
1927 static uint32_t sample_locs_4x
[] = {
1928 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1929 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1930 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1931 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1933 static unsigned max_dist_4x
= 6;
1934 /* Cayman/SI 8xMSAA */
1935 static uint32_t cm_sample_locs_8x
[] = {
1936 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1937 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1938 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1939 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1940 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1941 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1942 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1943 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1945 static unsigned cm_max_dist_8x
= 8;
1946 /* Cayman/SI 16xMSAA */
1947 static uint32_t cm_sample_locs_16x
[] = {
1948 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1949 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1950 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1951 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1952 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1953 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1954 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1955 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1956 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1957 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1958 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1959 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1960 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1961 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1962 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1963 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1965 static unsigned cm_max_dist_16x
= 8;
1967 static void si_get_sample_position(struct pipe_context
*ctx
,
1968 unsigned sample_count
,
1969 unsigned sample_index
,
1976 switch (sample_count
) {
1979 out_value
[0] = out_value
[1] = 0.5;
1982 offset
= 4 * (sample_index
* 2);
1983 val
.idx
= (sample_locs_2x
[0] >> offset
) & 0xf;
1984 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
1985 val
.idx
= (sample_locs_2x
[0] >> (offset
+ 4)) & 0xf;
1986 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
1989 offset
= 4 * (sample_index
* 2);
1990 val
.idx
= (sample_locs_4x
[0] >> offset
) & 0xf;
1991 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
1992 val
.idx
= (sample_locs_4x
[0] >> (offset
+ 4)) & 0xf;
1993 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
1996 offset
= 4 * (sample_index
% 4 * 2);
1997 index
= (sample_index
/ 4) * 4;
1998 val
.idx
= (cm_sample_locs_8x
[index
] >> offset
) & 0xf;
1999 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
2000 val
.idx
= (cm_sample_locs_8x
[index
] >> (offset
+ 4)) & 0xf;
2001 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
2004 offset
= 4 * (sample_index
% 4 * 2);
2005 index
= (sample_index
/ 4) * 4;
2006 val
.idx
= (cm_sample_locs_16x
[index
] >> offset
) & 0xf;
2007 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
2008 val
.idx
= (cm_sample_locs_16x
[index
] >> (offset
+ 4)) & 0xf;
2009 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
2014 static void si_set_msaa_state(struct r600_context
*rctx
, struct si_pm4_state
*pm4
, int nr_samples
)
2016 unsigned max_dist
= 0;
2018 switch (nr_samples
) {
2023 si_pm4_set_reg(pm4
, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, sample_locs_2x
[0]);
2024 si_pm4_set_reg(pm4
, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, sample_locs_2x
[1]);
2025 si_pm4_set_reg(pm4
, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, sample_locs_2x
[2]);
2026 si_pm4_set_reg(pm4
, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, sample_locs_2x
[3]);
2027 max_dist
= max_dist_2x
;
2030 si_pm4_set_reg(pm4
, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, sample_locs_4x
[0]);
2031 si_pm4_set_reg(pm4
, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, sample_locs_4x
[1]);
2032 si_pm4_set_reg(pm4
, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, sample_locs_4x
[2]);
2033 si_pm4_set_reg(pm4
, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, sample_locs_4x
[3]);
2034 max_dist
= max_dist_4x
;
2037 si_pm4_set_reg(pm4
, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, cm_sample_locs_8x
[0]);
2038 si_pm4_set_reg(pm4
, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1
, cm_sample_locs_8x
[4]);
2039 si_pm4_set_reg(pm4
, R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2
, 0);
2040 si_pm4_set_reg(pm4
, R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3
, 0);
2041 si_pm4_set_reg(pm4
, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, cm_sample_locs_8x
[1]);
2042 si_pm4_set_reg(pm4
, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1
, cm_sample_locs_8x
[5]);
2043 si_pm4_set_reg(pm4
, R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2
, 0);
2044 si_pm4_set_reg(pm4
, R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3
, 0);
2045 si_pm4_set_reg(pm4
, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, cm_sample_locs_8x
[2]);
2046 si_pm4_set_reg(pm4
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1
, cm_sample_locs_8x
[6]);
2047 si_pm4_set_reg(pm4
, R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2
, 0);
2048 si_pm4_set_reg(pm4
, R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3
, 0);
2049 si_pm4_set_reg(pm4
, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, cm_sample_locs_8x
[3]);
2050 si_pm4_set_reg(pm4
, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1
, cm_sample_locs_8x
[7]);
2051 max_dist
= cm_max_dist_8x
;
2054 si_pm4_set_reg(pm4
, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, cm_sample_locs_16x
[0]);
2055 si_pm4_set_reg(pm4
, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1
, cm_sample_locs_16x
[4]);
2056 si_pm4_set_reg(pm4
, R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2
, cm_sample_locs_16x
[8]);
2057 si_pm4_set_reg(pm4
, R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3
, cm_sample_locs_16x
[12]);
2058 si_pm4_set_reg(pm4
, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, cm_sample_locs_16x
[1]);
2059 si_pm4_set_reg(pm4
, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1
, cm_sample_locs_16x
[5]);
2060 si_pm4_set_reg(pm4
, R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2
, cm_sample_locs_16x
[9]);
2061 si_pm4_set_reg(pm4
, R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3
, cm_sample_locs_16x
[13]);
2062 si_pm4_set_reg(pm4
, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, cm_sample_locs_16x
[2]);
2063 si_pm4_set_reg(pm4
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1
, cm_sample_locs_16x
[6]);
2064 si_pm4_set_reg(pm4
, R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2
, cm_sample_locs_16x
[10]);
2065 si_pm4_set_reg(pm4
, R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3
, cm_sample_locs_16x
[14]);
2066 si_pm4_set_reg(pm4
, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, cm_sample_locs_16x
[3]);
2067 si_pm4_set_reg(pm4
, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1
, cm_sample_locs_16x
[7]);
2068 si_pm4_set_reg(pm4
, R_028C30_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2
, cm_sample_locs_16x
[11]);
2069 si_pm4_set_reg(pm4
, R_028C34_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3
, cm_sample_locs_16x
[15]);
2070 max_dist
= cm_max_dist_16x
;
2074 if (nr_samples
> 1) {
2075 unsigned log_samples
= util_logbase2(nr_samples
);
2077 si_pm4_set_reg(pm4
, R_028BDC_PA_SC_LINE_CNTL
,
2078 S_028BDC_LAST_PIXEL(1) |
2079 S_028BDC_EXPAND_LINE_WIDTH(1));
2080 si_pm4_set_reg(pm4
, R_028BE0_PA_SC_AA_CONFIG
,
2081 S_028BE0_MSAA_NUM_SAMPLES(log_samples
) |
2082 S_028BE0_MAX_SAMPLE_DIST(max_dist
) |
2083 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples
));
2085 si_pm4_set_reg(pm4
, R_028804_DB_EQAA
,
2086 S_028804_MAX_ANCHOR_SAMPLES(log_samples
) |
2087 S_028804_PS_ITER_SAMPLES(log_samples
) |
2088 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples
) |
2089 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples
) |
2090 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
2091 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
2093 si_pm4_set_reg(pm4
, R_028BDC_PA_SC_LINE_CNTL
, S_028BDC_LAST_PIXEL(1));
2094 si_pm4_set_reg(pm4
, R_028BE0_PA_SC_AA_CONFIG
, 0);
2096 si_pm4_set_reg(pm4
, R_028804_DB_EQAA
,
2097 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
2098 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
2102 static void si_set_framebuffer_state(struct pipe_context
*ctx
,
2103 const struct pipe_framebuffer_state
*state
)
2105 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2106 struct si_pm4_state
*pm4
= si_pm4_alloc_state(rctx
);
2108 int tl_x
, tl_y
, br_x
, br_y
, nr_samples
, i
;
2113 if (rctx
->framebuffer
.nr_cbufs
) {
2114 rctx
->b
.flags
|= R600_CONTEXT_FLUSH_AND_INV_CB
|
2115 R600_CONTEXT_FLUSH_AND_INV_CB_META
;
2117 if (rctx
->framebuffer
.zsbuf
) {
2118 rctx
->b
.flags
|= R600_CONTEXT_FLUSH_AND_INV_DB
;
2121 util_copy_framebuffer_state(&rctx
->framebuffer
, state
);
2124 rctx
->export_16bpc
= 0;
2125 rctx
->fb_compressed_cb_mask
= 0;
2126 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
2127 struct r600_texture
*rtex
=
2128 (struct r600_texture
*)state
->cbufs
[i
]->texture
;
2130 si_cb(rctx
, pm4
, state
, i
);
2132 if (rtex
->fmask
.size
|| rtex
->cmask
.size
) {
2133 rctx
->fb_compressed_cb_mask
|= 1 << i
;
2136 for (; i
< 8; i
++) {
2137 si_pm4_set_reg(pm4
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
2138 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
2141 assert(!(rctx
->export_16bpc
& ~0xff));
2142 si_db(rctx
, pm4
, state
);
2146 br_x
= state
->width
;
2147 br_y
= state
->height
;
2149 tl
= S_028240_TL_X(tl_x
) | S_028240_TL_Y(tl_y
);
2150 br
= S_028244_BR_X(br_x
) | S_028244_BR_Y(br_y
);
2152 si_pm4_set_reg(pm4
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, tl
);
2153 si_pm4_set_reg(pm4
, R_028244_PA_SC_GENERIC_SCISSOR_BR
, br
);
2154 si_pm4_set_reg(pm4
, R_028250_PA_SC_VPORT_SCISSOR_0_TL
, tl
);
2155 si_pm4_set_reg(pm4
, R_028254_PA_SC_VPORT_SCISSOR_0_BR
, br
);
2156 si_pm4_set_reg(pm4
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, tl
);
2157 si_pm4_set_reg(pm4
, R_028034_PA_SC_SCREEN_SCISSOR_BR
, br
);
2158 si_pm4_set_reg(pm4
, R_028204_PA_SC_WINDOW_SCISSOR_TL
, tl
);
2159 si_pm4_set_reg(pm4
, R_028208_PA_SC_WINDOW_SCISSOR_BR
, br
);
2160 si_pm4_set_reg(pm4
, R_028200_PA_SC_WINDOW_OFFSET
, 0x00000000);
2161 si_pm4_set_reg(pm4
, R_028230_PA_SC_EDGERULE
, 0xAAAAAAAA);
2163 if (state
->nr_cbufs
)
2164 nr_samples
= state
->cbufs
[0]->texture
->nr_samples
;
2165 else if (state
->zsbuf
)
2166 nr_samples
= state
->zsbuf
->texture
->nr_samples
;
2170 si_set_msaa_state(rctx
, pm4
, nr_samples
);
2171 rctx
->fb_log_samples
= util_logbase2(nr_samples
);
2172 rctx
->fb_cb0_is_integer
= state
->nr_cbufs
&&
2173 util_format_is_pure_integer(state
->cbufs
[0]->format
);
2175 si_pm4_set_state(rctx
, framebuffer
, pm4
);
2176 si_update_fb_rs_state(rctx
);
2177 si_update_fb_blend_state(rctx
);
2178 si_update_db_draw_state(rctx
, (struct r600_surface
*)state
->zsbuf
);
2185 /* Compute the key for the hw shader variant */
2186 static INLINE
void si_shader_selector_key(struct pipe_context
*ctx
,
2187 struct si_pipe_shader_selector
*sel
,
2188 union si_shader_key
*key
)
2190 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2191 memset(key
, 0, sizeof(*key
));
2193 if (sel
->type
== PIPE_SHADER_VERTEX
) {
2195 if (!rctx
->vertex_elements
)
2198 for (i
= 0; i
< rctx
->vertex_elements
->count
; ++i
)
2199 key
->vs
.instance_divisors
[i
] = rctx
->vertex_elements
->elements
[i
].instance_divisor
;
2201 if (rctx
->queued
.named
.rasterizer
->clip_plane_enable
& 0xf0)
2202 key
->vs
.ucps_enabled
|= 0x2;
2203 if (rctx
->queued
.named
.rasterizer
->clip_plane_enable
& 0xf)
2204 key
->vs
.ucps_enabled
|= 0x1;
2205 } else if (sel
->type
== PIPE_SHADER_FRAGMENT
) {
2206 if (sel
->fs_write_all
)
2207 key
->ps
.nr_cbufs
= rctx
->framebuffer
.nr_cbufs
;
2208 key
->ps
.export_16bpc
= rctx
->export_16bpc
;
2210 if (rctx
->queued
.named
.rasterizer
) {
2211 key
->ps
.color_two_side
= rctx
->queued
.named
.rasterizer
->two_side
;
2212 key
->ps
.flatshade
= rctx
->queued
.named
.rasterizer
->flatshade
;
2214 if (rctx
->queued
.named
.blend
) {
2215 key
->ps
.alpha_to_one
= rctx
->queued
.named
.blend
->alpha_to_one
&&
2216 rctx
->queued
.named
.rasterizer
->multisample_enable
&&
2217 !rctx
->fb_cb0_is_integer
;
2220 if (rctx
->queued
.named
.dsa
) {
2221 key
->ps
.alpha_func
= rctx
->queued
.named
.dsa
->alpha_func
;
2223 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
2224 if (rctx
->framebuffer
.nr_cbufs
&&
2225 rctx
->framebuffer
.cbufs
[0] &&
2226 util_format_is_pure_integer(rctx
->framebuffer
.cbufs
[0]->texture
->format
))
2227 key
->ps
.alpha_func
= PIPE_FUNC_ALWAYS
;
2229 key
->ps
.alpha_func
= PIPE_FUNC_ALWAYS
;
2234 /* Select the hw shader variant depending on the current state.
2235 * (*dirty) is set to 1 if current variant was changed */
2236 int si_shader_select(struct pipe_context
*ctx
,
2237 struct si_pipe_shader_selector
*sel
,
2240 union si_shader_key key
;
2241 struct si_pipe_shader
* shader
= NULL
;
2244 si_shader_selector_key(ctx
, sel
, &key
);
2246 /* Check if we don't need to change anything.
2247 * This path is also used for most shaders that don't need multiple
2248 * variants, it will cost just a computation of the key and this
2250 if (likely(sel
->current
&& memcmp(&sel
->current
->key
, &key
, sizeof(key
)) == 0)) {
2254 /* lookup if we have other variants in the list */
2255 if (sel
->num_shaders
> 1) {
2256 struct si_pipe_shader
*p
= sel
->current
, *c
= p
->next_variant
;
2258 while (c
&& memcmp(&c
->key
, &key
, sizeof(key
)) != 0) {
2260 c
= c
->next_variant
;
2264 p
->next_variant
= c
->next_variant
;
2269 if (unlikely(!shader
)) {
2270 shader
= CALLOC(1, sizeof(struct si_pipe_shader
));
2271 shader
->selector
= sel
;
2274 r
= si_pipe_shader_create(ctx
, shader
);
2276 R600_ERR("Failed to build shader variant (type=%u) %d\n",
2278 sel
->current
= NULL
;
2288 shader
->next_variant
= sel
->current
;
2289 sel
->current
= shader
;
2294 static void *si_create_shader_state(struct pipe_context
*ctx
,
2295 const struct pipe_shader_state
*state
,
2296 unsigned pipe_shader_type
)
2298 struct si_pipe_shader_selector
*sel
= CALLOC_STRUCT(si_pipe_shader_selector
);
2300 struct tgsi_shader_info info
;
2302 tgsi_scan_shader(state
->tokens
, &info
);
2304 sel
->type
= pipe_shader_type
;
2305 sel
->tokens
= tgsi_dup_tokens(state
->tokens
);
2306 sel
->so
= state
->stream_output
;
2307 sel
->fs_write_all
= info
.color0_writes_all_cbufs
;
2309 r
= si_shader_select(ctx
, sel
, NULL
);
2318 static void *si_create_fs_state(struct pipe_context
*ctx
,
2319 const struct pipe_shader_state
*state
)
2321 return si_create_shader_state(ctx
, state
, PIPE_SHADER_FRAGMENT
);
2324 static void *si_create_vs_state(struct pipe_context
*ctx
,
2325 const struct pipe_shader_state
*state
)
2327 return si_create_shader_state(ctx
, state
, PIPE_SHADER_VERTEX
);
2330 static void si_bind_vs_shader(struct pipe_context
*ctx
, void *state
)
2332 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2333 struct si_pipe_shader_selector
*sel
= state
;
2335 if (rctx
->vs_shader
== sel
)
2338 rctx
->vs_shader
= sel
;
2340 if (sel
&& sel
->current
) {
2341 si_pm4_bind_state(rctx
, vs
, sel
->current
->pm4
);
2342 rctx
->b
.streamout
.stride_in_dw
= sel
->so
.stride
;
2344 si_pm4_bind_state(rctx
, vs
, rctx
->dummy_pixel_shader
->pm4
);
2347 rctx
->b
.flags
|= R600_CONTEXT_INV_SHADER_CACHE
;
2350 static void si_bind_ps_shader(struct pipe_context
*ctx
, void *state
)
2352 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2353 struct si_pipe_shader_selector
*sel
= state
;
2355 if (rctx
->ps_shader
== sel
)
2358 rctx
->ps_shader
= sel
;
2360 if (sel
&& sel
->current
)
2361 si_pm4_bind_state(rctx
, ps
, sel
->current
->pm4
);
2363 si_pm4_bind_state(rctx
, ps
, rctx
->dummy_pixel_shader
->pm4
);
2365 rctx
->b
.flags
|= R600_CONTEXT_INV_SHADER_CACHE
;
2368 static void si_delete_shader_selector(struct pipe_context
*ctx
,
2369 struct si_pipe_shader_selector
*sel
)
2371 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2372 struct si_pipe_shader
*p
= sel
->current
, *c
;
2375 c
= p
->next_variant
;
2376 si_pm4_delete_state(rctx
, vs
, p
->pm4
);
2377 si_pipe_shader_destroy(ctx
, p
);
2386 static void si_delete_vs_shader(struct pipe_context
*ctx
, void *state
)
2388 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2389 struct si_pipe_shader_selector
*sel
= (struct si_pipe_shader_selector
*)state
;
2391 if (rctx
->vs_shader
== sel
) {
2392 rctx
->vs_shader
= NULL
;
2395 si_delete_shader_selector(ctx
, sel
);
2398 static void si_delete_ps_shader(struct pipe_context
*ctx
, void *state
)
2400 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2401 struct si_pipe_shader_selector
*sel
= (struct si_pipe_shader_selector
*)state
;
2403 if (rctx
->ps_shader
== sel
) {
2404 rctx
->ps_shader
= NULL
;
2407 si_delete_shader_selector(ctx
, sel
);
2414 static struct pipe_sampler_view
*si_create_sampler_view(struct pipe_context
*ctx
,
2415 struct pipe_resource
*texture
,
2416 const struct pipe_sampler_view
*state
)
2418 struct si_pipe_sampler_view
*view
= CALLOC_STRUCT(si_pipe_sampler_view
);
2419 struct r600_texture
*tmp
= (struct r600_texture
*)texture
;
2420 const struct util_format_description
*desc
;
2421 unsigned format
, num_format
;
2423 unsigned char state_swizzle
[4], swizzle
[4];
2424 unsigned height
, depth
, width
;
2425 enum pipe_format pipe_format
= state
->format
;
2426 struct radeon_surface_level
*surflevel
;
2433 /* initialize base object */
2434 view
->base
= *state
;
2435 view
->base
.texture
= NULL
;
2436 pipe_resource_reference(&view
->base
.texture
, texture
);
2437 view
->base
.reference
.count
= 1;
2438 view
->base
.context
= ctx
;
2439 view
->resource
= &tmp
->resource
;
2441 /* Buffer resource. */
2442 if (texture
->target
== PIPE_BUFFER
) {
2445 desc
= util_format_description(state
->format
);
2446 first_non_void
= util_format_get_first_non_void_channel(state
->format
);
2447 stride
= desc
->block
.bits
/ 8;
2448 va
= r600_resource_va(ctx
->screen
, texture
) + state
->u
.buf
.first_element
*stride
;
2449 format
= si_translate_buffer_dataformat(ctx
->screen
, desc
, first_non_void
);
2450 num_format
= si_translate_buffer_numformat(ctx
->screen
, desc
, first_non_void
);
2452 view
->state
[0] = va
;
2453 view
->state
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
2454 S_008F04_STRIDE(stride
);
2455 view
->state
[2] = state
->u
.buf
.last_element
+ 1 - state
->u
.buf
.first_element
;
2456 view
->state
[3] = S_008F0C_DST_SEL_X(si_map_swizzle(desc
->swizzle
[0])) |
2457 S_008F0C_DST_SEL_Y(si_map_swizzle(desc
->swizzle
[1])) |
2458 S_008F0C_DST_SEL_Z(si_map_swizzle(desc
->swizzle
[2])) |
2459 S_008F0C_DST_SEL_W(si_map_swizzle(desc
->swizzle
[3])) |
2460 S_008F0C_NUM_FORMAT(num_format
) |
2461 S_008F0C_DATA_FORMAT(format
);
2465 state_swizzle
[0] = state
->swizzle_r
;
2466 state_swizzle
[1] = state
->swizzle_g
;
2467 state_swizzle
[2] = state
->swizzle_b
;
2468 state_swizzle
[3] = state
->swizzle_a
;
2470 surflevel
= tmp
->surface
.level
;
2472 /* Texturing with separate depth and stencil. */
2473 if (tmp
->is_depth
&& !tmp
->is_flushing_texture
) {
2474 switch (pipe_format
) {
2475 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
2476 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
2478 case PIPE_FORMAT_X8Z24_UNORM
:
2479 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
2480 /* Z24 is always stored like this. */
2481 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
2483 case PIPE_FORMAT_X24S8_UINT
:
2484 case PIPE_FORMAT_S8X24_UINT
:
2485 case PIPE_FORMAT_X32_S8X24_UINT
:
2486 pipe_format
= PIPE_FORMAT_S8_UINT
;
2487 surflevel
= tmp
->surface
.stencil_level
;
2493 desc
= util_format_description(pipe_format
);
2495 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
) {
2496 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
2497 const unsigned char swizzle_yyyy
[4] = {1, 1, 1, 1};
2499 switch (pipe_format
) {
2500 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
2501 case PIPE_FORMAT_X24S8_UINT
:
2502 case PIPE_FORMAT_X32_S8X24_UINT
:
2503 case PIPE_FORMAT_X8Z24_UNORM
:
2504 util_format_compose_swizzles(swizzle_yyyy
, state_swizzle
, swizzle
);
2507 util_format_compose_swizzles(swizzle_xxxx
, state_swizzle
, swizzle
);
2510 util_format_compose_swizzles(desc
->swizzle
, state_swizzle
, swizzle
);
2513 first_non_void
= util_format_get_first_non_void_channel(pipe_format
);
2515 switch (pipe_format
) {
2516 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
2517 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
2520 if (first_non_void
< 0) {
2521 if (util_format_is_compressed(pipe_format
)) {
2522 switch (pipe_format
) {
2523 case PIPE_FORMAT_DXT1_SRGB
:
2524 case PIPE_FORMAT_DXT1_SRGBA
:
2525 case PIPE_FORMAT_DXT3_SRGBA
:
2526 case PIPE_FORMAT_DXT5_SRGBA
:
2527 num_format
= V_008F14_IMG_NUM_FORMAT_SRGB
;
2529 case PIPE_FORMAT_RGTC1_SNORM
:
2530 case PIPE_FORMAT_LATC1_SNORM
:
2531 case PIPE_FORMAT_RGTC2_SNORM
:
2532 case PIPE_FORMAT_LATC2_SNORM
:
2533 num_format
= V_008F14_IMG_NUM_FORMAT_SNORM
;
2536 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
2540 num_format
= V_008F14_IMG_NUM_FORMAT_FLOAT
;
2542 } else if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
) {
2543 num_format
= V_008F14_IMG_NUM_FORMAT_SRGB
;
2545 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
2547 switch (desc
->channel
[first_non_void
].type
) {
2548 case UTIL_FORMAT_TYPE_FLOAT
:
2549 num_format
= V_008F14_IMG_NUM_FORMAT_FLOAT
;
2551 case UTIL_FORMAT_TYPE_SIGNED
:
2552 if (desc
->channel
[first_non_void
].normalized
)
2553 num_format
= V_008F14_IMG_NUM_FORMAT_SNORM
;
2554 else if (desc
->channel
[first_non_void
].pure_integer
)
2555 num_format
= V_008F14_IMG_NUM_FORMAT_SINT
;
2557 num_format
= V_008F14_IMG_NUM_FORMAT_SSCALED
;
2559 case UTIL_FORMAT_TYPE_UNSIGNED
:
2560 if (desc
->channel
[first_non_void
].normalized
)
2561 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
2562 else if (desc
->channel
[first_non_void
].pure_integer
)
2563 num_format
= V_008F14_IMG_NUM_FORMAT_UINT
;
2565 num_format
= V_008F14_IMG_NUM_FORMAT_USCALED
;
2570 format
= si_translate_texformat(ctx
->screen
, pipe_format
, desc
, first_non_void
);
2575 /* not supported any more */
2576 //endian = si_colorformat_endian_swap(format);
2578 width
= surflevel
[0].npix_x
;
2579 height
= surflevel
[0].npix_y
;
2580 depth
= surflevel
[0].npix_z
;
2581 pitch
= surflevel
[0].nblk_x
* util_format_get_blockwidth(pipe_format
);
2583 if (texture
->target
== PIPE_TEXTURE_1D_ARRAY
) {
2585 depth
= texture
->array_size
;
2586 } else if (texture
->target
== PIPE_TEXTURE_2D_ARRAY
) {
2587 depth
= texture
->array_size
;
2590 va
= r600_resource_va(ctx
->screen
, texture
);
2591 va
+= surflevel
[0].offset
;
2592 va
+= tmp
->mipmap_shift
* surflevel
[texture
->last_level
].slice_size
;
2593 view
->state
[0] = va
>> 8;
2594 view
->state
[1] = (S_008F14_BASE_ADDRESS_HI(va
>> 40) |
2595 S_008F14_DATA_FORMAT(format
) |
2596 S_008F14_NUM_FORMAT(num_format
));
2597 view
->state
[2] = (S_008F18_WIDTH(width
- 1) |
2598 S_008F18_HEIGHT(height
- 1));
2599 view
->state
[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle
[0])) |
2600 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle
[1])) |
2601 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle
[2])) |
2602 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle
[3])) |
2603 S_008F1C_BASE_LEVEL(texture
->nr_samples
> 1 ?
2604 0 : state
->u
.tex
.first_level
- tmp
->mipmap_shift
) |
2605 S_008F1C_LAST_LEVEL(texture
->nr_samples
> 1 ?
2606 util_logbase2(texture
->nr_samples
) :
2607 state
->u
.tex
.last_level
- tmp
->mipmap_shift
) |
2608 S_008F1C_TILING_INDEX(si_tile_mode_index(tmp
, 0, false)) |
2609 S_008F1C_POW2_PAD(texture
->last_level
> 0) |
2610 S_008F1C_TYPE(si_tex_dim(texture
->target
, texture
->nr_samples
)));
2611 view
->state
[4] = (S_008F20_DEPTH(depth
- 1) | S_008F20_PITCH(pitch
- 1));
2612 view
->state
[5] = (S_008F24_BASE_ARRAY(state
->u
.tex
.first_layer
) |
2613 S_008F24_LAST_ARRAY(state
->u
.tex
.last_layer
));
2617 /* Initialize the sampler view for FMASK. */
2618 if (tmp
->fmask
.size
) {
2619 uint64_t va
= r600_resource_va(ctx
->screen
, texture
) + tmp
->fmask
.offset
;
2620 uint32_t fmask_format
;
2622 switch (texture
->nr_samples
) {
2624 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2
;
2627 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4
;
2630 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8
;
2634 fmask_format
= V_008F14_IMG_DATA_FORMAT_INVALID
;
2637 view
->fmask_state
[0] = va
>> 8;
2638 view
->fmask_state
[1] = S_008F14_BASE_ADDRESS_HI(va
>> 40) |
2639 S_008F14_DATA_FORMAT(fmask_format
) |
2640 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT
);
2641 view
->fmask_state
[2] = S_008F18_WIDTH(width
- 1) |
2642 S_008F18_HEIGHT(height
- 1);
2643 view
->fmask_state
[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X
) |
2644 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X
) |
2645 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X
) |
2646 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X
) |
2647 S_008F1C_TILING_INDEX(tmp
->fmask
.tile_mode_index
) |
2648 S_008F1C_TYPE(si_tex_dim(texture
->target
, 0));
2649 view
->fmask_state
[4] = S_008F20_DEPTH(depth
- 1) |
2650 S_008F20_PITCH(tmp
->fmask
.pitch
- 1);
2651 view
->fmask_state
[5] = S_008F24_BASE_ARRAY(state
->u
.tex
.first_layer
) |
2652 S_008F24_LAST_ARRAY(state
->u
.tex
.last_layer
);
2653 view
->fmask_state
[6] = 0;
2654 view
->fmask_state
[7] = 0;
2660 static void si_sampler_view_destroy(struct pipe_context
*ctx
,
2661 struct pipe_sampler_view
*state
)
2663 struct r600_pipe_sampler_view
*resource
= (struct r600_pipe_sampler_view
*)state
;
2665 pipe_resource_reference(&state
->texture
, NULL
);
2669 static bool wrap_mode_uses_border_color(unsigned wrap
, bool linear_filter
)
2671 return wrap
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
||
2672 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
||
2674 (wrap
== PIPE_TEX_WRAP_CLAMP
||
2675 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP
));
2678 static bool sampler_state_needs_border_color(const struct pipe_sampler_state
*state
)
2680 bool linear_filter
= state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
||
2681 state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
;
2683 return (state
->border_color
.ui
[0] || state
->border_color
.ui
[1] ||
2684 state
->border_color
.ui
[2] || state
->border_color
.ui
[3]) &&
2685 (wrap_mode_uses_border_color(state
->wrap_s
, linear_filter
) ||
2686 wrap_mode_uses_border_color(state
->wrap_t
, linear_filter
) ||
2687 wrap_mode_uses_border_color(state
->wrap_r
, linear_filter
));
2690 static void *si_create_sampler_state(struct pipe_context
*ctx
,
2691 const struct pipe_sampler_state
*state
)
2693 struct si_pipe_sampler_state
*rstate
= CALLOC_STRUCT(si_pipe_sampler_state
);
2694 unsigned aniso_flag_offset
= state
->max_anisotropy
> 1 ? 2 : 0;
2695 unsigned border_color_type
;
2697 if (rstate
== NULL
) {
2701 if (sampler_state_needs_border_color(state
))
2702 border_color_type
= V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER
;
2704 border_color_type
= V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
;
2706 rstate
->val
[0] = (S_008F30_CLAMP_X(si_tex_wrap(state
->wrap_s
)) |
2707 S_008F30_CLAMP_Y(si_tex_wrap(state
->wrap_t
)) |
2708 S_008F30_CLAMP_Z(si_tex_wrap(state
->wrap_r
)) |
2709 (state
->max_anisotropy
& 0x7) << 9 | /* XXX */
2710 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state
->compare_func
)) |
2711 S_008F30_FORCE_UNNORMALIZED(!state
->normalized_coords
) |
2712 aniso_flag_offset
<< 16 | /* XXX */
2713 S_008F30_DISABLE_CUBE_WRAP(!state
->seamless_cube_map
));
2714 rstate
->val
[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 8)) |
2715 S_008F34_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 8)));
2716 rstate
->val
[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 8)) |
2717 S_008F38_XY_MAG_FILTER(si_tex_filter(state
->mag_img_filter
)) |
2718 S_008F38_XY_MIN_FILTER(si_tex_filter(state
->min_img_filter
)) |
2719 S_008F38_MIP_FILTER(si_tex_mipfilter(state
->min_mip_filter
)));
2720 rstate
->val
[3] = S_008F3C_BORDER_COLOR_TYPE(border_color_type
);
2722 if (border_color_type
== V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER
) {
2723 memcpy(rstate
->border_color
, state
->border_color
.ui
,
2724 sizeof(rstate
->border_color
));
2730 /* XXX consider moving this function to si_descriptors.c for gcc to inline
2731 * the si_set_sampler_view calls. LTO might help too. */
2732 static void si_set_sampler_views(struct pipe_context
*ctx
,
2733 unsigned shader
, unsigned start
,
2735 struct pipe_sampler_view
**views
)
2737 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2738 struct r600_textures_info
*samplers
= &rctx
->samplers
[shader
];
2739 struct si_pipe_sampler_view
**rviews
= (struct si_pipe_sampler_view
**)views
;
2742 if (shader
!= PIPE_SHADER_VERTEX
&& shader
!= PIPE_SHADER_FRAGMENT
)
2747 for (i
= 0; i
< count
; i
++) {
2749 samplers
->depth_texture_mask
&= ~(1 << i
);
2750 samplers
->compressed_colortex_mask
&= ~(1 << i
);
2751 si_set_sampler_view(rctx
, shader
, i
, NULL
, NULL
);
2752 si_set_sampler_view(rctx
, shader
, FMASK_TEX_OFFSET
+ i
,
2757 si_set_sampler_view(rctx
, shader
, i
, views
[i
], rviews
[i
]->state
);
2759 if (views
[i
]->texture
->target
!= PIPE_BUFFER
) {
2760 struct r600_texture
*rtex
=
2761 (struct r600_texture
*)views
[i
]->texture
;
2763 if (rtex
->is_depth
&& !rtex
->is_flushing_texture
) {
2764 samplers
->depth_texture_mask
|= 1 << i
;
2766 samplers
->depth_texture_mask
&= ~(1 << i
);
2768 if (rtex
->cmask
.size
|| rtex
->fmask
.size
) {
2769 samplers
->compressed_colortex_mask
|= 1 << i
;
2771 samplers
->compressed_colortex_mask
&= ~(1 << i
);
2774 if (rtex
->fmask
.size
) {
2775 si_set_sampler_view(rctx
, shader
, FMASK_TEX_OFFSET
+ i
,
2776 views
[i
], rviews
[i
]->fmask_state
);
2778 si_set_sampler_view(rctx
, shader
, FMASK_TEX_OFFSET
+ i
,
2783 for (; i
< samplers
->n_views
; i
++) {
2784 samplers
->depth_texture_mask
&= ~(1 << i
);
2785 samplers
->compressed_colortex_mask
&= ~(1 << i
);
2786 si_set_sampler_view(rctx
, shader
, i
, NULL
, NULL
);
2787 si_set_sampler_view(rctx
, shader
, FMASK_TEX_OFFSET
+ i
,
2791 samplers
->n_views
= count
;
2792 rctx
->b
.flags
|= R600_CONTEXT_INV_TEX_CACHE
;
2795 static struct si_pm4_state
*si_set_sampler_states(struct r600_context
*rctx
, unsigned count
,
2797 struct r600_textures_info
*samplers
,
2798 unsigned user_data_reg
)
2800 struct si_pipe_sampler_state
**rstates
= (struct si_pipe_sampler_state
**)states
;
2801 struct si_pm4_state
*pm4
= si_pm4_alloc_state(rctx
);
2802 uint32_t *border_color_table
= NULL
;
2808 rctx
->b
.flags
|= R600_CONTEXT_INV_TEX_CACHE
;
2810 si_pm4_sh_data_begin(pm4
);
2811 for (i
= 0; i
< count
; i
++) {
2813 G_008F3C_BORDER_COLOR_TYPE(rstates
[i
]->val
[3]) ==
2814 V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER
) {
2815 if (!rctx
->border_color_table
||
2816 ((rctx
->border_color_offset
+ count
- i
) &
2817 C_008F3C_BORDER_COLOR_PTR
)) {
2818 r600_resource_reference(&rctx
->border_color_table
, NULL
);
2819 rctx
->border_color_offset
= 0;
2821 rctx
->border_color_table
=
2822 r600_resource_create_custom(&rctx
->screen
->b
.b
,
2827 if (!border_color_table
) {
2828 border_color_table
=
2829 rctx
->b
.ws
->buffer_map(rctx
->border_color_table
->cs_buf
,
2830 rctx
->b
.rings
.gfx
.cs
,
2831 PIPE_TRANSFER_WRITE
|
2832 PIPE_TRANSFER_UNSYNCHRONIZED
);
2835 for (j
= 0; j
< 4; j
++) {
2836 border_color_table
[4 * rctx
->border_color_offset
+ j
] =
2837 util_le32_to_cpu(rstates
[i
]->border_color
[j
]);
2840 rstates
[i
]->val
[3] &= C_008F3C_BORDER_COLOR_PTR
;
2841 rstates
[i
]->val
[3] |= S_008F3C_BORDER_COLOR_PTR(rctx
->border_color_offset
++);
2844 for (j
= 0; j
< Elements(rstates
[i
]->val
); ++j
) {
2845 si_pm4_sh_data_add(pm4
, rstates
[i
] ? rstates
[i
]->val
[j
] : 0);
2848 si_pm4_sh_data_end(pm4
, user_data_reg
, SI_SGPR_SAMPLER
);
2850 if (border_color_table
) {
2851 uint64_t va_offset
=
2852 r600_resource_va(&rctx
->screen
->b
.b
,
2853 (void*)rctx
->border_color_table
);
2855 si_pm4_set_reg(pm4
, R_028080_TA_BC_BASE_ADDR
, va_offset
>> 8);
2856 if (rctx
->b
.chip_class
>= CIK
)
2857 si_pm4_set_reg(pm4
, R_028084_TA_BC_BASE_ADDR_HI
, va_offset
>> 40);
2858 rctx
->b
.ws
->buffer_unmap(rctx
->border_color_table
->cs_buf
);
2859 si_pm4_add_bo(pm4
, rctx
->border_color_table
, RADEON_USAGE_READ
);
2862 memcpy(samplers
->samplers
, states
, sizeof(void*) * count
);
2865 samplers
->n_samplers
= count
;
2869 static void si_bind_vs_sampler_states(struct pipe_context
*ctx
, unsigned count
, void **states
)
2871 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2872 struct si_pm4_state
*pm4
;
2874 pm4
= si_set_sampler_states(rctx
, count
, states
, &rctx
->samplers
[PIPE_SHADER_VERTEX
],
2875 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2876 si_pm4_set_state(rctx
, vs_sampler
, pm4
);
2879 static void si_bind_ps_sampler_states(struct pipe_context
*ctx
, unsigned count
, void **states
)
2881 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2882 struct si_pm4_state
*pm4
;
2884 pm4
= si_set_sampler_states(rctx
, count
, states
, &rctx
->samplers
[PIPE_SHADER_FRAGMENT
],
2885 R_00B030_SPI_SHADER_USER_DATA_PS_0
);
2886 si_pm4_set_state(rctx
, ps_sampler
, pm4
);
2890 static void si_bind_sampler_states(struct pipe_context
*ctx
, unsigned shader
,
2891 unsigned start
, unsigned count
,
2897 case PIPE_SHADER_VERTEX
:
2898 si_bind_vs_sampler_states(ctx
, count
, states
);
2900 case PIPE_SHADER_FRAGMENT
:
2901 si_bind_ps_sampler_states(ctx
, count
, states
);
2910 static void si_set_sample_mask(struct pipe_context
*ctx
, unsigned sample_mask
)
2912 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2913 struct si_pm4_state
*pm4
= si_pm4_alloc_state(rctx
);
2914 uint16_t mask
= sample_mask
;
2919 si_pm4_set_reg(pm4
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, mask
| (mask
<< 16));
2920 si_pm4_set_reg(pm4
, R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1
, mask
| (mask
<< 16));
2922 si_pm4_set_state(rctx
, sample_mask
, pm4
);
2925 static void si_delete_sampler_state(struct pipe_context
*ctx
, void *state
)
2931 * Vertex elements & buffers
2934 static void *si_create_vertex_elements(struct pipe_context
*ctx
,
2936 const struct pipe_vertex_element
*elements
)
2938 struct si_vertex_element
*v
= CALLOC_STRUCT(si_vertex_element
);
2941 assert(count
< PIPE_MAX_ATTRIBS
);
2946 for (i
= 0; i
< count
; ++i
) {
2947 const struct util_format_description
*desc
;
2948 unsigned data_format
, num_format
;
2951 desc
= util_format_description(elements
[i
].src_format
);
2952 first_non_void
= util_format_get_first_non_void_channel(elements
[i
].src_format
);
2953 data_format
= si_translate_buffer_dataformat(ctx
->screen
, desc
, first_non_void
);
2954 num_format
= si_translate_buffer_numformat(ctx
->screen
, desc
, first_non_void
);
2956 v
->rsrc_word3
[i
] = S_008F0C_DST_SEL_X(si_map_swizzle(desc
->swizzle
[0])) |
2957 S_008F0C_DST_SEL_Y(si_map_swizzle(desc
->swizzle
[1])) |
2958 S_008F0C_DST_SEL_Z(si_map_swizzle(desc
->swizzle
[2])) |
2959 S_008F0C_DST_SEL_W(si_map_swizzle(desc
->swizzle
[3])) |
2960 S_008F0C_NUM_FORMAT(num_format
) |
2961 S_008F0C_DATA_FORMAT(data_format
);
2963 memcpy(v
->elements
, elements
, sizeof(struct pipe_vertex_element
) * count
);
2968 static void si_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
2970 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2971 struct si_vertex_element
*v
= (struct si_vertex_element
*)state
;
2973 rctx
->vertex_elements
= v
;
2976 static void si_delete_vertex_element(struct pipe_context
*ctx
, void *state
)
2978 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2980 if (rctx
->vertex_elements
== state
)
2981 rctx
->vertex_elements
= NULL
;
2985 static void si_set_vertex_buffers(struct pipe_context
*ctx
, unsigned start_slot
, unsigned count
,
2986 const struct pipe_vertex_buffer
*buffers
)
2988 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2990 util_set_vertex_buffers_count(rctx
->vertex_buffer
, &rctx
->nr_vertex_buffers
, buffers
, start_slot
, count
);
2993 static void si_set_index_buffer(struct pipe_context
*ctx
,
2994 const struct pipe_index_buffer
*ib
)
2996 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
2999 pipe_resource_reference(&rctx
->index_buffer
.buffer
, ib
->buffer
);
3000 memcpy(&rctx
->index_buffer
, ib
, sizeof(*ib
));
3002 pipe_resource_reference(&rctx
->index_buffer
.buffer
, NULL
);
3009 static void si_set_polygon_stipple(struct pipe_context
*ctx
,
3010 const struct pipe_poly_stipple
*state
)
3014 static void si_texture_barrier(struct pipe_context
*ctx
)
3016 struct r600_context
*rctx
= (struct r600_context
*)ctx
;
3018 rctx
->b
.flags
|= R600_CONTEXT_INV_TEX_CACHE
|
3019 R600_CONTEXT_FLUSH_AND_INV_CB
;
3022 static void *si_create_blend_custom(struct r600_context
*rctx
, unsigned mode
)
3024 struct pipe_blend_state blend
;
3026 memset(&blend
, 0, sizeof(blend
));
3027 blend
.independent_blend_enable
= true;
3028 blend
.rt
[0].colormask
= 0xf;
3029 return si_create_blend_state_mode(&rctx
->b
.b
, &blend
, mode
);
3032 static struct pipe_surface
*r600_create_surface(struct pipe_context
*pipe
,
3033 struct pipe_resource
*texture
,
3034 const struct pipe_surface
*surf_tmpl
)
3036 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
3037 struct r600_surface
*surface
= CALLOC_STRUCT(r600_surface
);
3038 unsigned level
= surf_tmpl
->u
.tex
.level
;
3040 if (surface
== NULL
)
3043 assert(surf_tmpl
->u
.tex
.first_layer
<= util_max_layer(texture
, surf_tmpl
->u
.tex
.level
));
3044 assert(surf_tmpl
->u
.tex
.last_layer
<= util_max_layer(texture
, surf_tmpl
->u
.tex
.level
));
3046 pipe_reference_init(&surface
->base
.reference
, 1);
3047 pipe_resource_reference(&surface
->base
.texture
, texture
);
3048 surface
->base
.context
= pipe
;
3049 surface
->base
.format
= surf_tmpl
->format
;
3050 surface
->base
.width
= rtex
->surface
.level
[level
].npix_x
;
3051 surface
->base
.height
= rtex
->surface
.level
[level
].npix_y
;
3052 surface
->base
.texture
= texture
;
3053 surface
->base
.u
.tex
.first_layer
= surf_tmpl
->u
.tex
.first_layer
;
3054 surface
->base
.u
.tex
.last_layer
= surf_tmpl
->u
.tex
.last_layer
;
3055 surface
->base
.u
.tex
.level
= level
;
3057 return &surface
->base
;
3060 static void r600_surface_destroy(struct pipe_context
*pipe
,
3061 struct pipe_surface
*surface
)
3063 pipe_resource_reference(&surface
->texture
, NULL
);
3067 static boolean
si_dma_copy(struct pipe_context
*ctx
,
3068 struct pipe_resource
*dst
,
3070 unsigned dst_x
, unsigned dst_y
, unsigned dst_z
,
3071 struct pipe_resource
*src
,
3073 const struct pipe_box
*src_box
)
3075 /* XXX implement this or share evergreen_dma_blit with r600g */
3079 void si_init_state_functions(struct r600_context
*rctx
)
3083 rctx
->b
.b
.create_blend_state
= si_create_blend_state
;
3084 rctx
->b
.b
.bind_blend_state
= si_bind_blend_state
;
3085 rctx
->b
.b
.delete_blend_state
= si_delete_blend_state
;
3086 rctx
->b
.b
.set_blend_color
= si_set_blend_color
;
3088 rctx
->b
.b
.create_rasterizer_state
= si_create_rs_state
;
3089 rctx
->b
.b
.bind_rasterizer_state
= si_bind_rs_state
;
3090 rctx
->b
.b
.delete_rasterizer_state
= si_delete_rs_state
;
3092 rctx
->b
.b
.create_depth_stencil_alpha_state
= si_create_dsa_state
;
3093 rctx
->b
.b
.bind_depth_stencil_alpha_state
= si_bind_dsa_state
;
3094 rctx
->b
.b
.delete_depth_stencil_alpha_state
= si_delete_dsa_state
;
3096 for (i
= 0; i
< 8; i
++) {
3097 rctx
->custom_dsa_flush_depth_stencil
[i
] = si_create_db_flush_dsa(rctx
, true, true, i
);
3098 rctx
->custom_dsa_flush_depth
[i
] = si_create_db_flush_dsa(rctx
, true, false, i
);
3099 rctx
->custom_dsa_flush_stencil
[i
] = si_create_db_flush_dsa(rctx
, false, true, i
);
3101 rctx
->custom_dsa_flush_inplace
= si_create_db_flush_dsa(rctx
, false, false, 0);
3102 rctx
->custom_blend_resolve
= si_create_blend_custom(rctx
, V_028808_CB_RESOLVE
);
3103 rctx
->custom_blend_decompress
= si_create_blend_custom(rctx
, V_028808_CB_FMASK_DECOMPRESS
);
3105 rctx
->b
.b
.set_clip_state
= si_set_clip_state
;
3106 rctx
->b
.b
.set_scissor_states
= si_set_scissor_states
;
3107 rctx
->b
.b
.set_viewport_states
= si_set_viewport_states
;
3108 rctx
->b
.b
.set_stencil_ref
= si_set_pipe_stencil_ref
;
3110 rctx
->b
.b
.set_framebuffer_state
= si_set_framebuffer_state
;
3111 rctx
->b
.b
.get_sample_position
= si_get_sample_position
;
3113 rctx
->b
.b
.create_vs_state
= si_create_vs_state
;
3114 rctx
->b
.b
.create_fs_state
= si_create_fs_state
;
3115 rctx
->b
.b
.bind_vs_state
= si_bind_vs_shader
;
3116 rctx
->b
.b
.bind_fs_state
= si_bind_ps_shader
;
3117 rctx
->b
.b
.delete_vs_state
= si_delete_vs_shader
;
3118 rctx
->b
.b
.delete_fs_state
= si_delete_ps_shader
;
3120 rctx
->b
.b
.create_sampler_state
= si_create_sampler_state
;
3121 rctx
->b
.b
.bind_sampler_states
= si_bind_sampler_states
;
3122 rctx
->b
.b
.delete_sampler_state
= si_delete_sampler_state
;
3124 rctx
->b
.b
.create_sampler_view
= si_create_sampler_view
;
3125 rctx
->b
.b
.set_sampler_views
= si_set_sampler_views
;
3126 rctx
->b
.b
.sampler_view_destroy
= si_sampler_view_destroy
;
3128 rctx
->b
.b
.set_sample_mask
= si_set_sample_mask
;
3130 rctx
->b
.b
.create_vertex_elements_state
= si_create_vertex_elements
;
3131 rctx
->b
.b
.bind_vertex_elements_state
= si_bind_vertex_elements
;
3132 rctx
->b
.b
.delete_vertex_elements_state
= si_delete_vertex_element
;
3133 rctx
->b
.b
.set_vertex_buffers
= si_set_vertex_buffers
;
3134 rctx
->b
.b
.set_index_buffer
= si_set_index_buffer
;
3136 rctx
->b
.b
.texture_barrier
= si_texture_barrier
;
3137 rctx
->b
.b
.set_polygon_stipple
= si_set_polygon_stipple
;
3138 rctx
->b
.b
.create_surface
= r600_create_surface
;
3139 rctx
->b
.b
.surface_destroy
= r600_surface_destroy
;
3140 rctx
->b
.dma_copy
= si_dma_copy
;
3142 rctx
->b
.b
.draw_vbo
= si_draw_vbo
;
3145 void si_init_config(struct r600_context
*rctx
)
3147 struct si_pm4_state
*pm4
= si_pm4_alloc_state(rctx
);
3152 si_cmd_context_control(pm4
);
3154 si_pm4_set_reg(pm4
, R_028A4C_PA_SC_MODE_CNTL_1
, 0x0);
3156 si_pm4_set_reg(pm4
, R_028A10_VGT_OUTPUT_PATH_CNTL
, 0x0);
3157 si_pm4_set_reg(pm4
, R_028A14_VGT_HOS_CNTL
, 0x0);
3158 si_pm4_set_reg(pm4
, R_028A18_VGT_HOS_MAX_TESS_LEVEL
, 0x0);
3159 si_pm4_set_reg(pm4
, R_028A1C_VGT_HOS_MIN_TESS_LEVEL
, 0x0);
3160 si_pm4_set_reg(pm4
, R_028A20_VGT_HOS_REUSE_DEPTH
, 0x0);
3161 si_pm4_set_reg(pm4
, R_028A24_VGT_GROUP_PRIM_TYPE
, 0x0);
3162 si_pm4_set_reg(pm4
, R_028A28_VGT_GROUP_FIRST_DECR
, 0x0);
3163 si_pm4_set_reg(pm4
, R_028A2C_VGT_GROUP_DECR
, 0x0);
3164 si_pm4_set_reg(pm4
, R_028A30_VGT_GROUP_VECT_0_CNTL
, 0x0);
3165 si_pm4_set_reg(pm4
, R_028A34_VGT_GROUP_VECT_1_CNTL
, 0x0);
3166 si_pm4_set_reg(pm4
, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL
, 0x0);
3167 si_pm4_set_reg(pm4
, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL
, 0x0);
3168 si_pm4_set_reg(pm4
, R_028A40_VGT_GS_MODE
, 0x0);
3169 si_pm4_set_reg(pm4
, R_028A84_VGT_PRIMITIVEID_EN
, 0x0);
3170 si_pm4_set_reg(pm4
, R_028A8C_VGT_PRIMITIVEID_RESET
, 0x0);
3171 si_pm4_set_reg(pm4
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
3172 si_pm4_set_reg(pm4
, R_028B94_VGT_STRMOUT_CONFIG
, 0x0);
3173 si_pm4_set_reg(pm4
, R_028B98_VGT_STRMOUT_BUFFER_CONFIG
, 0x0);
3174 if (rctx
->b
.chip_class
== SI
) {
3175 si_pm4_set_reg(pm4
, R_028AA8_IA_MULTI_VGT_PARAM
,
3176 S_028AA8_SWITCH_ON_EOP(1) |
3177 S_028AA8_PARTIAL_VS_WAVE_ON(1) |
3178 S_028AA8_PRIMGROUP_SIZE(63));
3180 si_pm4_set_reg(pm4
, R_028AB4_VGT_REUSE_OFF
, 0x00000000);
3181 si_pm4_set_reg(pm4
, R_028AB8_VGT_VTX_CNT_EN
, 0x0);
3182 if (rctx
->b
.chip_class
< CIK
)
3183 si_pm4_set_reg(pm4
, R_008A14_PA_CL_ENHANCE
, S_008A14_NUM_CLIP_SEQ(3) |
3184 S_008A14_CLIP_VTX_REORDER_ENA(1));
3186 si_pm4_set_reg(pm4
, R_028B54_VGT_SHADER_STAGES_EN
, 0);
3187 si_pm4_set_reg(pm4
, R_028BD4_PA_SC_CENTROID_PRIORITY_0
, 0x76543210);
3188 si_pm4_set_reg(pm4
, R_028BD8_PA_SC_CENTROID_PRIORITY_1
, 0xfedcba98);
3190 si_pm4_set_reg(pm4
, R_02882C_PA_SU_PRIM_FILTER_CNTL
, 0);
3192 if (rctx
->b
.chip_class
>= CIK
) {
3193 switch (rctx
->screen
->b
.family
) {
3195 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
, 0x16000012);
3196 si_pm4_set_reg(pm4
, R_028354_PA_SC_RASTER_CONFIG_1
, 0x00000000);
3199 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
, 0x3a00161a);
3200 si_pm4_set_reg(pm4
, R_028354_PA_SC_RASTER_CONFIG_1
, 0x0000002e);
3207 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
, 0x00000000);
3208 si_pm4_set_reg(pm4
, R_028354_PA_SC_RASTER_CONFIG_1
, 0x00000000);
3212 switch (rctx
->screen
->b
.family
) {
3215 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
, 0x2a00126a);
3218 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
, 0x0000124a);
3221 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
, 0x00000082);
3224 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
, 0x00000000);
3227 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
, 0x00000000);
3232 si_pm4_set_state(rctx
, init
, pm4
);