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radeonsi: don't set number of IB dwords for states
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "si_shader.h"
29 #include "sid.h"
30 #include "radeon/r600_cs.h"
31
32 #include "util/u_dual_blend.h"
33 #include "util/u_format.h"
34 #include "util/u_format_s3tc.h"
35 #include "util/u_memory.h"
36 #include "util/u_pstipple.h"
37
38 /* Initialize an external atom (owned by ../radeon). */
39 static void
40 si_init_external_atom(struct si_context *sctx, struct r600_atom *atom,
41 struct r600_atom **list_elem)
42 {
43 atom->id = list_elem - sctx->atoms.array + 1;
44 *list_elem = atom;
45 }
46
47 /* Initialize an atom owned by radeonsi. */
48 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
49 struct r600_atom **list_elem,
50 void (*emit_func)(struct si_context *ctx, struct r600_atom *state))
51 {
52 atom->emit = (void*)emit_func;
53 atom->dirty = false;
54 atom->id = list_elem - sctx->atoms.array + 1; /* index+1 in the atom array */
55 *list_elem = atom;
56 }
57
58 unsigned si_array_mode(unsigned mode)
59 {
60 switch (mode) {
61 case RADEON_SURF_MODE_LINEAR_ALIGNED:
62 return V_009910_ARRAY_LINEAR_ALIGNED;
63 case RADEON_SURF_MODE_1D:
64 return V_009910_ARRAY_1D_TILED_THIN1;
65 case RADEON_SURF_MODE_2D:
66 return V_009910_ARRAY_2D_TILED_THIN1;
67 default:
68 case RADEON_SURF_MODE_LINEAR:
69 return V_009910_ARRAY_LINEAR_GENERAL;
70 }
71 }
72
73 uint32_t si_num_banks(struct si_screen *sscreen, struct r600_texture *tex)
74 {
75 if (sscreen->b.chip_class >= CIK &&
76 sscreen->b.info.cik_macrotile_mode_array_valid) {
77 unsigned index, tileb;
78
79 tileb = 8 * 8 * tex->surface.bpe;
80 tileb = MIN2(tex->surface.tile_split, tileb);
81
82 for (index = 0; tileb > 64; index++) {
83 tileb >>= 1;
84 }
85 assert(index < 16);
86
87 return (sscreen->b.info.cik_macrotile_mode_array[index] >> 6) & 0x3;
88 }
89
90 if (sscreen->b.chip_class == SI &&
91 sscreen->b.info.si_tile_mode_array_valid) {
92 /* Don't use stencil_tiling_index, because num_banks is always
93 * read from the depth mode. */
94 unsigned tile_mode_index = tex->surface.tiling_index[0];
95 assert(tile_mode_index < 32);
96
97 return G_009910_NUM_BANKS(sscreen->b.info.si_tile_mode_array[tile_mode_index]);
98 }
99
100 /* The old way. */
101 switch (sscreen->b.tiling_info.num_banks) {
102 case 2:
103 return V_02803C_ADDR_SURF_2_BANK;
104 case 4:
105 return V_02803C_ADDR_SURF_4_BANK;
106 case 8:
107 default:
108 return V_02803C_ADDR_SURF_8_BANK;
109 case 16:
110 return V_02803C_ADDR_SURF_16_BANK;
111 }
112 }
113
114 unsigned cik_tile_split(unsigned tile_split)
115 {
116 switch (tile_split) {
117 case 64:
118 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_64B;
119 break;
120 case 128:
121 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_128B;
122 break;
123 case 256:
124 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_256B;
125 break;
126 case 512:
127 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_512B;
128 break;
129 default:
130 case 1024:
131 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_1KB;
132 break;
133 case 2048:
134 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_2KB;
135 break;
136 case 4096:
137 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_4KB;
138 break;
139 }
140 return tile_split;
141 }
142
143 unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect)
144 {
145 switch (macro_tile_aspect) {
146 default:
147 case 1:
148 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_1;
149 break;
150 case 2:
151 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_2;
152 break;
153 case 4:
154 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_4;
155 break;
156 case 8:
157 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_8;
158 break;
159 }
160 return macro_tile_aspect;
161 }
162
163 unsigned cik_bank_wh(unsigned bankwh)
164 {
165 switch (bankwh) {
166 default:
167 case 1:
168 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_1;
169 break;
170 case 2:
171 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_2;
172 break;
173 case 4:
174 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_4;
175 break;
176 case 8:
177 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_8;
178 break;
179 }
180 return bankwh;
181 }
182
183 unsigned cik_db_pipe_config(struct si_screen *sscreen, unsigned tile_mode)
184 {
185 if (sscreen->b.info.si_tile_mode_array_valid) {
186 uint32_t gb_tile_mode = sscreen->b.info.si_tile_mode_array[tile_mode];
187
188 return G_009910_PIPE_CONFIG(gb_tile_mode);
189 }
190
191 /* This is probably broken for a lot of chips, but it's only used
192 * if the kernel cannot return the tile mode array for CIK. */
193 switch (sscreen->b.info.r600_num_tile_pipes) {
194 case 16:
195 return V_02803C_X_ADDR_SURF_P16_32X32_16X16;
196 case 8:
197 return V_02803C_X_ADDR_SURF_P8_32X32_16X16;
198 case 4:
199 default:
200 if (sscreen->b.info.r600_num_backends == 4)
201 return V_02803C_X_ADDR_SURF_P4_16X16;
202 else
203 return V_02803C_X_ADDR_SURF_P4_8X16;
204 case 2:
205 return V_02803C_ADDR_SURF_P2;
206 }
207 }
208
209 static unsigned si_map_swizzle(unsigned swizzle)
210 {
211 switch (swizzle) {
212 case UTIL_FORMAT_SWIZZLE_Y:
213 return V_008F0C_SQ_SEL_Y;
214 case UTIL_FORMAT_SWIZZLE_Z:
215 return V_008F0C_SQ_SEL_Z;
216 case UTIL_FORMAT_SWIZZLE_W:
217 return V_008F0C_SQ_SEL_W;
218 case UTIL_FORMAT_SWIZZLE_0:
219 return V_008F0C_SQ_SEL_0;
220 case UTIL_FORMAT_SWIZZLE_1:
221 return V_008F0C_SQ_SEL_1;
222 default: /* UTIL_FORMAT_SWIZZLE_X */
223 return V_008F0C_SQ_SEL_X;
224 }
225 }
226
227 static uint32_t S_FIXED(float value, uint32_t frac_bits)
228 {
229 return value * (1 << frac_bits);
230 }
231
232 /* 12.4 fixed-point */
233 static unsigned si_pack_float_12p4(float x)
234 {
235 return x <= 0 ? 0 :
236 x >= 4096 ? 0xffff : x * 16;
237 }
238
239 /*
240 * Inferred framebuffer and blender state.
241 *
242 * One of the reasons this must be derived from the framebuffer state is that:
243 * - The blend state mask is 0xf most of the time.
244 * - The COLOR1 format isn't INVALID because of possible dual-source blending,
245 * so COLOR1 is enabled pretty much all the time.
246 * So CB_TARGET_MASK is the only register that can disable COLOR1.
247 *
248 * Another reason is to avoid a hang with dual source blending.
249 */
250 static void si_emit_cb_target_mask(struct si_context *sctx, struct r600_atom *atom)
251 {
252 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
253 struct si_state_blend *blend = sctx->queued.named.blend;
254 uint32_t mask = 0, i;
255
256 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++)
257 if (sctx->framebuffer.state.cbufs[i])
258 mask |= 0xf << (4*i);
259
260 if (blend)
261 mask &= blend->cb_target_mask;
262
263 /* Avoid a hang that happens when dual source blending is enabled
264 * but there is not enough color outputs. This is undefined behavior,
265 * so disable color writes completely.
266 *
267 * Reproducible with Unigine Heaven 4.0 and drirc missing.
268 */
269 if (blend->dual_src_blend &&
270 (sctx->ps_shader->ps_colors_written & 0x3) != 0x3)
271 mask = 0;
272
273 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, mask);
274 }
275
276 /*
277 * Blender functions
278 */
279
280 static uint32_t si_translate_blend_function(int blend_func)
281 {
282 switch (blend_func) {
283 case PIPE_BLEND_ADD:
284 return V_028780_COMB_DST_PLUS_SRC;
285 case PIPE_BLEND_SUBTRACT:
286 return V_028780_COMB_SRC_MINUS_DST;
287 case PIPE_BLEND_REVERSE_SUBTRACT:
288 return V_028780_COMB_DST_MINUS_SRC;
289 case PIPE_BLEND_MIN:
290 return V_028780_COMB_MIN_DST_SRC;
291 case PIPE_BLEND_MAX:
292 return V_028780_COMB_MAX_DST_SRC;
293 default:
294 R600_ERR("Unknown blend function %d\n", blend_func);
295 assert(0);
296 break;
297 }
298 return 0;
299 }
300
301 static uint32_t si_translate_blend_factor(int blend_fact)
302 {
303 switch (blend_fact) {
304 case PIPE_BLENDFACTOR_ONE:
305 return V_028780_BLEND_ONE;
306 case PIPE_BLENDFACTOR_SRC_COLOR:
307 return V_028780_BLEND_SRC_COLOR;
308 case PIPE_BLENDFACTOR_SRC_ALPHA:
309 return V_028780_BLEND_SRC_ALPHA;
310 case PIPE_BLENDFACTOR_DST_ALPHA:
311 return V_028780_BLEND_DST_ALPHA;
312 case PIPE_BLENDFACTOR_DST_COLOR:
313 return V_028780_BLEND_DST_COLOR;
314 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
315 return V_028780_BLEND_SRC_ALPHA_SATURATE;
316 case PIPE_BLENDFACTOR_CONST_COLOR:
317 return V_028780_BLEND_CONSTANT_COLOR;
318 case PIPE_BLENDFACTOR_CONST_ALPHA:
319 return V_028780_BLEND_CONSTANT_ALPHA;
320 case PIPE_BLENDFACTOR_ZERO:
321 return V_028780_BLEND_ZERO;
322 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
323 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
324 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
325 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
326 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
327 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
328 case PIPE_BLENDFACTOR_INV_DST_COLOR:
329 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
330 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
331 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
332 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
333 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
334 case PIPE_BLENDFACTOR_SRC1_COLOR:
335 return V_028780_BLEND_SRC1_COLOR;
336 case PIPE_BLENDFACTOR_SRC1_ALPHA:
337 return V_028780_BLEND_SRC1_ALPHA;
338 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
339 return V_028780_BLEND_INV_SRC1_COLOR;
340 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
341 return V_028780_BLEND_INV_SRC1_ALPHA;
342 default:
343 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
344 assert(0);
345 break;
346 }
347 return 0;
348 }
349
350 static void *si_create_blend_state_mode(struct pipe_context *ctx,
351 const struct pipe_blend_state *state,
352 unsigned mode)
353 {
354 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
355 struct si_pm4_state *pm4 = &blend->pm4;
356
357 uint32_t color_control = 0;
358
359 if (blend == NULL)
360 return NULL;
361
362 blend->alpha_to_one = state->alpha_to_one;
363 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
364
365 if (state->logicop_enable) {
366 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
367 } else {
368 color_control |= S_028808_ROP3(0xcc);
369 }
370
371 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
372 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
373 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
374 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
375 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
376 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
377
378 blend->cb_target_mask = 0;
379 for (int i = 0; i < 8; i++) {
380 /* state->rt entries > 0 only written if independent blending */
381 const int j = state->independent_blend_enable ? i : 0;
382
383 unsigned eqRGB = state->rt[j].rgb_func;
384 unsigned srcRGB = state->rt[j].rgb_src_factor;
385 unsigned dstRGB = state->rt[j].rgb_dst_factor;
386 unsigned eqA = state->rt[j].alpha_func;
387 unsigned srcA = state->rt[j].alpha_src_factor;
388 unsigned dstA = state->rt[j].alpha_dst_factor;
389
390 unsigned blend_cntl = 0;
391
392 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
393 blend->cb_target_mask |= state->rt[j].colormask << (4 * i);
394
395 if (!state->rt[j].blend_enable) {
396 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
397 continue;
398 }
399
400 blend_cntl |= S_028780_ENABLE(1);
401 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
402 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
403 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
404
405 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
406 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
407 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
408 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
409 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
410 }
411 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
412 }
413
414 if (blend->cb_target_mask) {
415 color_control |= S_028808_MODE(mode);
416 } else {
417 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
418 }
419 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
420
421 return blend;
422 }
423
424 static void *si_create_blend_state(struct pipe_context *ctx,
425 const struct pipe_blend_state *state)
426 {
427 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
428 }
429
430 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
431 {
432 struct si_context *sctx = (struct si_context *)ctx;
433 si_pm4_bind_state(sctx, blend, (struct si_state_blend *)state);
434 si_mark_atom_dirty(sctx, &sctx->cb_target_mask);
435 }
436
437 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
438 {
439 struct si_context *sctx = (struct si_context *)ctx;
440 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
441 }
442
443 static void si_set_blend_color(struct pipe_context *ctx,
444 const struct pipe_blend_color *state)
445 {
446 struct si_context *sctx = (struct si_context *)ctx;
447
448 if (memcmp(&sctx->blend_color.state, state, sizeof(*state)) == 0)
449 return;
450
451 sctx->blend_color.state = *state;
452 si_mark_atom_dirty(sctx, &sctx->blend_color.atom);
453 }
454
455 static void si_emit_blend_color(struct si_context *sctx, struct r600_atom *atom)
456 {
457 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
458
459 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
460 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
461 }
462
463 /*
464 * Clipping, scissors and viewport
465 */
466
467 static void si_set_clip_state(struct pipe_context *ctx,
468 const struct pipe_clip_state *state)
469 {
470 struct si_context *sctx = (struct si_context *)ctx;
471 struct pipe_constant_buffer cb;
472
473 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
474 return;
475
476 sctx->clip_state.state = *state;
477 si_mark_atom_dirty(sctx, &sctx->clip_state.atom);
478
479 cb.buffer = NULL;
480 cb.user_buffer = state->ucp;
481 cb.buffer_offset = 0;
482 cb.buffer_size = 4*4*8;
483 ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, SI_DRIVER_STATE_CONST_BUF, &cb);
484 pipe_resource_reference(&cb.buffer, NULL);
485 }
486
487 static void si_emit_clip_state(struct si_context *sctx, struct r600_atom *atom)
488 {
489 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
490
491 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
492 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
493 }
494
495 #define SIX_BITS 0x3F
496
497 static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom)
498 {
499 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
500 struct tgsi_shader_info *info = si_get_vs_info(sctx);
501 unsigned window_space =
502 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
503 unsigned clipdist_mask =
504 info->writes_clipvertex ? SIX_BITS : info->clipdist_writemask;
505
506 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
507 S_02881C_USE_VTX_POINT_SIZE(info->writes_psize) |
508 S_02881C_USE_VTX_EDGE_FLAG(info->writes_edgeflag) |
509 S_02881C_USE_VTX_RENDER_TARGET_INDX(info->writes_layer) |
510 S_02881C_USE_VTX_VIEWPORT_INDX(info->writes_viewport_index) |
511 S_02881C_VS_OUT_CCDIST0_VEC_ENA((clipdist_mask & 0x0F) != 0) |
512 S_02881C_VS_OUT_CCDIST1_VEC_ENA((clipdist_mask & 0xF0) != 0) |
513 S_02881C_VS_OUT_MISC_VEC_ENA(info->writes_psize ||
514 info->writes_edgeflag ||
515 info->writes_layer ||
516 info->writes_viewport_index) |
517 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(1) |
518 (sctx->queued.named.rasterizer->clip_plane_enable &
519 clipdist_mask));
520 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
521 sctx->queued.named.rasterizer->pa_cl_clip_cntl |
522 (clipdist_mask ? 0 :
523 sctx->queued.named.rasterizer->clip_plane_enable & SIX_BITS) |
524 S_028810_CLIP_DISABLE(window_space));
525 }
526
527 static void si_set_scissor_states(struct pipe_context *ctx,
528 unsigned start_slot,
529 unsigned num_scissors,
530 const struct pipe_scissor_state *state)
531 {
532 struct si_context *sctx = (struct si_context *)ctx;
533 int i;
534
535 for (i = 0; i < num_scissors; i++)
536 sctx->scissors.states[start_slot + i] = state[i];
537
538 sctx->scissors.dirty_mask |= ((1 << num_scissors) - 1) << start_slot;
539 si_mark_atom_dirty(sctx, &sctx->scissors.atom);
540 }
541
542 static void si_emit_scissors(struct si_context *sctx, struct r600_atom *atom)
543 {
544 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
545 struct pipe_scissor_state *states = sctx->scissors.states;
546 unsigned mask = sctx->scissors.dirty_mask;
547
548 /* The simple case: Only 1 viewport is active. */
549 if (mask & 1 &&
550 !si_get_vs_info(sctx)->writes_viewport_index) {
551 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2);
552 radeon_emit(cs, S_028250_TL_X(states[0].minx) |
553 S_028250_TL_Y(states[0].miny) |
554 S_028250_WINDOW_OFFSET_DISABLE(1));
555 radeon_emit(cs, S_028254_BR_X(states[0].maxx) |
556 S_028254_BR_Y(states[0].maxy));
557 sctx->scissors.dirty_mask &= ~1; /* clear one bit */
558 return;
559 }
560
561 while (mask) {
562 int start, count, i;
563
564 u_bit_scan_consecutive_range(&mask, &start, &count);
565
566 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL +
567 start * 4 * 2, count * 2);
568 for (i = start; i < start+count; i++) {
569 radeon_emit(cs, S_028250_TL_X(states[i].minx) |
570 S_028250_TL_Y(states[i].miny) |
571 S_028250_WINDOW_OFFSET_DISABLE(1));
572 radeon_emit(cs, S_028254_BR_X(states[i].maxx) |
573 S_028254_BR_Y(states[i].maxy));
574 }
575 }
576 sctx->scissors.dirty_mask = 0;
577 }
578
579 static void si_set_viewport_states(struct pipe_context *ctx,
580 unsigned start_slot,
581 unsigned num_viewports,
582 const struct pipe_viewport_state *state)
583 {
584 struct si_context *sctx = (struct si_context *)ctx;
585 int i;
586
587 for (i = 0; i < num_viewports; i++)
588 sctx->viewports.states[start_slot + i] = state[i];
589
590 sctx->viewports.dirty_mask |= ((1 << num_viewports) - 1) << start_slot;
591 si_mark_atom_dirty(sctx, &sctx->viewports.atom);
592 }
593
594 static void si_emit_viewports(struct si_context *sctx, struct r600_atom *atom)
595 {
596 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
597 struct pipe_viewport_state *states = sctx->viewports.states;
598 unsigned mask = sctx->viewports.dirty_mask;
599
600 /* The simple case: Only 1 viewport is active. */
601 if (mask & 1 &&
602 !si_get_vs_info(sctx)->writes_viewport_index) {
603 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE, 6);
604 radeon_emit(cs, fui(states[0].scale[0]));
605 radeon_emit(cs, fui(states[0].translate[0]));
606 radeon_emit(cs, fui(states[0].scale[1]));
607 radeon_emit(cs, fui(states[0].translate[1]));
608 radeon_emit(cs, fui(states[0].scale[2]));
609 radeon_emit(cs, fui(states[0].translate[2]));
610 sctx->viewports.dirty_mask &= ~1; /* clear one bit */
611 return;
612 }
613
614 while (mask) {
615 int start, count, i;
616
617 u_bit_scan_consecutive_range(&mask, &start, &count);
618
619 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE +
620 start * 4 * 6, count * 6);
621 for (i = start; i < start+count; i++) {
622 radeon_emit(cs, fui(states[i].scale[0]));
623 radeon_emit(cs, fui(states[i].translate[0]));
624 radeon_emit(cs, fui(states[i].scale[1]));
625 radeon_emit(cs, fui(states[i].translate[1]));
626 radeon_emit(cs, fui(states[i].scale[2]));
627 radeon_emit(cs, fui(states[i].translate[2]));
628 }
629 }
630 sctx->viewports.dirty_mask = 0;
631 }
632
633 /*
634 * inferred state between framebuffer and rasterizer
635 */
636 static void si_update_poly_offset_state(struct si_context *sctx)
637 {
638 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
639
640 if (!rs || !sctx->framebuffer.state.zsbuf)
641 return;
642
643 switch (sctx->framebuffer.state.zsbuf->texture->format) {
644 case PIPE_FORMAT_Z16_UNORM:
645 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
646 break;
647 default: /* 24-bit */
648 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
649 break;
650 case PIPE_FORMAT_Z32_FLOAT:
651 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
652 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
653 break;
654 }
655 }
656
657 /*
658 * Rasterizer
659 */
660
661 static uint32_t si_translate_fill(uint32_t func)
662 {
663 switch(func) {
664 case PIPE_POLYGON_MODE_FILL:
665 return V_028814_X_DRAW_TRIANGLES;
666 case PIPE_POLYGON_MODE_LINE:
667 return V_028814_X_DRAW_LINES;
668 case PIPE_POLYGON_MODE_POINT:
669 return V_028814_X_DRAW_POINTS;
670 default:
671 assert(0);
672 return V_028814_X_DRAW_POINTS;
673 }
674 }
675
676 static void *si_create_rs_state(struct pipe_context *ctx,
677 const struct pipe_rasterizer_state *state)
678 {
679 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
680 struct si_pm4_state *pm4 = &rs->pm4;
681 unsigned tmp, i;
682 float psize_min, psize_max;
683
684 if (rs == NULL) {
685 return NULL;
686 }
687
688 rs->two_side = state->light_twoside;
689 rs->multisample_enable = state->multisample;
690 rs->clip_plane_enable = state->clip_plane_enable;
691 rs->line_stipple_enable = state->line_stipple_enable;
692 rs->poly_stipple_enable = state->poly_stipple_enable;
693 rs->line_smooth = state->line_smooth;
694 rs->poly_smooth = state->poly_smooth;
695
696 rs->flatshade = state->flatshade;
697 rs->sprite_coord_enable = state->sprite_coord_enable;
698 rs->pa_sc_line_stipple = state->line_stipple_enable ?
699 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
700 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
701 rs->pa_cl_clip_cntl =
702 S_028810_PS_UCP_MODE(3) |
703 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
704 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
705 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
706 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
707 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
708
709 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
710 S_0286D4_FLAT_SHADE_ENA(1) |
711 S_0286D4_PNT_SPRITE_ENA(1) |
712 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
713 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
714 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
715 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
716 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
717
718 /* point size 12.4 fixed point */
719 tmp = (unsigned)(state->point_size * 8.0);
720 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
721
722 if (state->point_size_per_vertex) {
723 psize_min = util_get_min_point_size(state);
724 psize_max = 8192;
725 } else {
726 /* Force the point size to be as if the vertex output was disabled. */
727 psize_min = state->point_size;
728 psize_max = state->point_size;
729 }
730 /* Divide by two, because 0.5 = 1 pixel. */
731 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
732 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
733 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
734
735 tmp = (unsigned)state->line_width * 8;
736 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
737 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
738 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
739 S_028A48_MSAA_ENABLE(state->multisample ||
740 state->poly_smooth ||
741 state->line_smooth) |
742 S_028A48_VPORT_SCISSOR_ENABLE(state->scissor));
743
744 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
745 S_028BE4_PIX_CENTER(state->half_pixel_center) |
746 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
747
748 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
749 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
750 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
751 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
752 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
753 S_028814_FACE(!state->front_ccw) |
754 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
755 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
756 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
757 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
758 state->fill_back != PIPE_POLYGON_MODE_FILL) |
759 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
760 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
761
762 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
763 for (i = 0; i < 3; i++) {
764 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
765 float offset_units = state->offset_units;
766 float offset_scale = state->offset_scale * 16.0f;
767
768 switch (i) {
769 case 0: /* 16-bit zbuffer */
770 offset_units *= 4.0f;
771 break;
772 case 1: /* 24-bit zbuffer */
773 offset_units *= 2.0f;
774 break;
775 case 2: /* 32-bit zbuffer */
776 offset_units *= 1.0f;
777 break;
778 }
779
780 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
781 fui(offset_scale));
782 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
783 fui(offset_units));
784 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
785 fui(offset_scale));
786 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
787 fui(offset_units));
788 }
789
790 return rs;
791 }
792
793 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
794 {
795 struct si_context *sctx = (struct si_context *)ctx;
796 struct si_state_rasterizer *old_rs =
797 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
798 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
799
800 if (state == NULL)
801 return;
802
803 if (sctx->framebuffer.nr_samples > 1 &&
804 (!old_rs || old_rs->multisample_enable != rs->multisample_enable))
805 si_mark_atom_dirty(sctx, &sctx->db_render_state);
806
807 si_pm4_bind_state(sctx, rasterizer, rs);
808 si_update_poly_offset_state(sctx);
809
810 si_mark_atom_dirty(sctx, &sctx->clip_regs);
811 }
812
813 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
814 {
815 struct si_context *sctx = (struct si_context *)ctx;
816
817 if (sctx->queued.named.rasterizer == state)
818 si_pm4_bind_state(sctx, poly_offset, NULL);
819 si_pm4_delete_state(sctx, rasterizer, (struct si_state_rasterizer *)state);
820 }
821
822 /*
823 * infeered state between dsa and stencil ref
824 */
825 static void si_emit_stencil_ref(struct si_context *sctx, struct r600_atom *atom)
826 {
827 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
828 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
829 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
830
831 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
832 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
833 S_028430_STENCILMASK(dsa->valuemask[0]) |
834 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
835 S_028430_STENCILOPVAL(1));
836 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
837 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
838 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
839 S_028434_STENCILOPVAL_BF(1));
840 }
841
842 static void si_set_stencil_ref(struct pipe_context *ctx,
843 const struct pipe_stencil_ref *state)
844 {
845 struct si_context *sctx = (struct si_context *)ctx;
846
847 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
848 return;
849
850 sctx->stencil_ref.state = *state;
851 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
852 }
853
854
855 /*
856 * DSA
857 */
858
859 static uint32_t si_translate_stencil_op(int s_op)
860 {
861 switch (s_op) {
862 case PIPE_STENCIL_OP_KEEP:
863 return V_02842C_STENCIL_KEEP;
864 case PIPE_STENCIL_OP_ZERO:
865 return V_02842C_STENCIL_ZERO;
866 case PIPE_STENCIL_OP_REPLACE:
867 return V_02842C_STENCIL_REPLACE_TEST;
868 case PIPE_STENCIL_OP_INCR:
869 return V_02842C_STENCIL_ADD_CLAMP;
870 case PIPE_STENCIL_OP_DECR:
871 return V_02842C_STENCIL_SUB_CLAMP;
872 case PIPE_STENCIL_OP_INCR_WRAP:
873 return V_02842C_STENCIL_ADD_WRAP;
874 case PIPE_STENCIL_OP_DECR_WRAP:
875 return V_02842C_STENCIL_SUB_WRAP;
876 case PIPE_STENCIL_OP_INVERT:
877 return V_02842C_STENCIL_INVERT;
878 default:
879 R600_ERR("Unknown stencil op %d", s_op);
880 assert(0);
881 break;
882 }
883 return 0;
884 }
885
886 static void *si_create_dsa_state(struct pipe_context *ctx,
887 const struct pipe_depth_stencil_alpha_state *state)
888 {
889 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
890 struct si_pm4_state *pm4 = &dsa->pm4;
891 unsigned db_depth_control;
892 uint32_t db_stencil_control = 0;
893
894 if (dsa == NULL) {
895 return NULL;
896 }
897
898 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
899 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
900 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
901 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
902
903 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
904 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
905 S_028800_ZFUNC(state->depth.func) |
906 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
907
908 /* stencil */
909 if (state->stencil[0].enabled) {
910 db_depth_control |= S_028800_STENCIL_ENABLE(1);
911 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
912 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
913 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
914 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
915
916 if (state->stencil[1].enabled) {
917 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
918 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
919 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
920 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
921 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
922 }
923 }
924
925 /* alpha */
926 if (state->alpha.enabled) {
927 dsa->alpha_func = state->alpha.func;
928
929 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
930 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
931 } else {
932 dsa->alpha_func = PIPE_FUNC_ALWAYS;
933 }
934
935 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
936 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
937 if (state->depth.bounds_test) {
938 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
939 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
940 }
941
942 return dsa;
943 }
944
945 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
946 {
947 struct si_context *sctx = (struct si_context *)ctx;
948 struct si_state_dsa *dsa = state;
949
950 if (state == NULL)
951 return;
952
953 si_pm4_bind_state(sctx, dsa, dsa);
954
955 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
956 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
957 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
958 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
959 }
960 }
961
962 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
963 {
964 struct si_context *sctx = (struct si_context *)ctx;
965 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
966 }
967
968 static void *si_create_db_flush_dsa(struct si_context *sctx)
969 {
970 struct pipe_depth_stencil_alpha_state dsa = {};
971
972 return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
973 }
974
975 /* DB RENDER STATE */
976
977 static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
978 {
979 struct si_context *sctx = (struct si_context*)ctx;
980
981 si_mark_atom_dirty(sctx, &sctx->db_render_state);
982 }
983
984 static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
985 {
986 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
987 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
988 unsigned db_shader_control;
989
990 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
991
992 /* DB_RENDER_CONTROL */
993 if (sctx->dbcb_depth_copy_enabled ||
994 sctx->dbcb_stencil_copy_enabled) {
995 radeon_emit(cs,
996 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
997 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
998 S_028000_COPY_CENTROID(1) |
999 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
1000 } else if (sctx->db_inplace_flush_enabled) {
1001 radeon_emit(cs,
1002 S_028000_DEPTH_COMPRESS_DISABLE(1) |
1003 S_028000_STENCIL_COMPRESS_DISABLE(1));
1004 } else if (sctx->db_depth_clear) {
1005 radeon_emit(cs, S_028000_DEPTH_CLEAR_ENABLE(1));
1006 } else {
1007 radeon_emit(cs, 0);
1008 }
1009
1010 /* DB_COUNT_CONTROL (occlusion queries) */
1011 if (sctx->b.num_occlusion_queries > 0) {
1012 if (sctx->b.chip_class >= CIK) {
1013 radeon_emit(cs,
1014 S_028004_PERFECT_ZPASS_COUNTS(1) |
1015 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
1016 S_028004_ZPASS_ENABLE(1) |
1017 S_028004_SLICE_EVEN_ENABLE(1) |
1018 S_028004_SLICE_ODD_ENABLE(1));
1019 } else {
1020 radeon_emit(cs,
1021 S_028004_PERFECT_ZPASS_COUNTS(1) |
1022 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
1023 }
1024 } else {
1025 /* Disable occlusion queries. */
1026 if (sctx->b.chip_class >= CIK) {
1027 radeon_emit(cs, 0);
1028 } else {
1029 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
1030 }
1031 }
1032
1033 /* DB_RENDER_OVERRIDE2 */
1034 if (sctx->db_depth_disable_expclear) {
1035 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
1036 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(1));
1037 } else {
1038 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2, 0);
1039 }
1040
1041 db_shader_control = S_02880C_ALPHA_TO_MASK_DISABLE(sctx->framebuffer.cb0_is_integer) |
1042 sctx->ps_db_shader_control;
1043
1044 /* Bug workaround for smoothing (overrasterization) on SI. */
1045 if (sctx->b.chip_class == SI && sctx->smoothing_enabled)
1046 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1047 else
1048 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
1049
1050 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1051 if (sctx->framebuffer.nr_samples <= 1 || (rs && !rs->multisample_enable))
1052 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1053
1054 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
1055 db_shader_control);
1056 }
1057
1058 /*
1059 * format translation
1060 */
1061 static uint32_t si_translate_colorformat(enum pipe_format format)
1062 {
1063 const struct util_format_description *desc = util_format_description(format);
1064
1065 #define HAS_SIZE(x,y,z,w) \
1066 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1067 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1068
1069 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1070 return V_028C70_COLOR_10_11_11;
1071
1072 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1073 return V_028C70_COLOR_INVALID;
1074
1075 switch (desc->nr_channels) {
1076 case 1:
1077 switch (desc->channel[0].size) {
1078 case 8:
1079 return V_028C70_COLOR_8;
1080 case 16:
1081 return V_028C70_COLOR_16;
1082 case 32:
1083 return V_028C70_COLOR_32;
1084 }
1085 break;
1086 case 2:
1087 if (desc->channel[0].size == desc->channel[1].size) {
1088 switch (desc->channel[0].size) {
1089 case 8:
1090 return V_028C70_COLOR_8_8;
1091 case 16:
1092 return V_028C70_COLOR_16_16;
1093 case 32:
1094 return V_028C70_COLOR_32_32;
1095 }
1096 } else if (HAS_SIZE(8,24,0,0)) {
1097 return V_028C70_COLOR_24_8;
1098 } else if (HAS_SIZE(24,8,0,0)) {
1099 return V_028C70_COLOR_8_24;
1100 }
1101 break;
1102 case 3:
1103 if (HAS_SIZE(5,6,5,0)) {
1104 return V_028C70_COLOR_5_6_5;
1105 } else if (HAS_SIZE(32,8,24,0)) {
1106 return V_028C70_COLOR_X24_8_32_FLOAT;
1107 }
1108 break;
1109 case 4:
1110 if (desc->channel[0].size == desc->channel[1].size &&
1111 desc->channel[0].size == desc->channel[2].size &&
1112 desc->channel[0].size == desc->channel[3].size) {
1113 switch (desc->channel[0].size) {
1114 case 4:
1115 return V_028C70_COLOR_4_4_4_4;
1116 case 8:
1117 return V_028C70_COLOR_8_8_8_8;
1118 case 16:
1119 return V_028C70_COLOR_16_16_16_16;
1120 case 32:
1121 return V_028C70_COLOR_32_32_32_32;
1122 }
1123 } else if (HAS_SIZE(5,5,5,1)) {
1124 return V_028C70_COLOR_1_5_5_5;
1125 } else if (HAS_SIZE(10,10,10,2)) {
1126 return V_028C70_COLOR_2_10_10_10;
1127 }
1128 break;
1129 }
1130 return V_028C70_COLOR_INVALID;
1131 }
1132
1133 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1134 {
1135 if (SI_BIG_ENDIAN) {
1136 switch(colorformat) {
1137 /* 8-bit buffers. */
1138 case V_028C70_COLOR_8:
1139 return V_028C70_ENDIAN_NONE;
1140
1141 /* 16-bit buffers. */
1142 case V_028C70_COLOR_5_6_5:
1143 case V_028C70_COLOR_1_5_5_5:
1144 case V_028C70_COLOR_4_4_4_4:
1145 case V_028C70_COLOR_16:
1146 case V_028C70_COLOR_8_8:
1147 return V_028C70_ENDIAN_8IN16;
1148
1149 /* 32-bit buffers. */
1150 case V_028C70_COLOR_8_8_8_8:
1151 case V_028C70_COLOR_2_10_10_10:
1152 case V_028C70_COLOR_8_24:
1153 case V_028C70_COLOR_24_8:
1154 case V_028C70_COLOR_16_16:
1155 return V_028C70_ENDIAN_8IN32;
1156
1157 /* 64-bit buffers. */
1158 case V_028C70_COLOR_16_16_16_16:
1159 return V_028C70_ENDIAN_8IN16;
1160
1161 case V_028C70_COLOR_32_32:
1162 return V_028C70_ENDIAN_8IN32;
1163
1164 /* 128-bit buffers. */
1165 case V_028C70_COLOR_32_32_32_32:
1166 return V_028C70_ENDIAN_8IN32;
1167 default:
1168 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1169 }
1170 } else {
1171 return V_028C70_ENDIAN_NONE;
1172 }
1173 }
1174
1175 /* Returns the size in bits of the widest component of a CB format */
1176 static unsigned si_colorformat_max_comp_size(uint32_t colorformat)
1177 {
1178 switch(colorformat) {
1179 case V_028C70_COLOR_4_4_4_4:
1180 return 4;
1181
1182 case V_028C70_COLOR_1_5_5_5:
1183 case V_028C70_COLOR_5_5_5_1:
1184 return 5;
1185
1186 case V_028C70_COLOR_5_6_5:
1187 return 6;
1188
1189 case V_028C70_COLOR_8:
1190 case V_028C70_COLOR_8_8:
1191 case V_028C70_COLOR_8_8_8_8:
1192 return 8;
1193
1194 case V_028C70_COLOR_10_10_10_2:
1195 case V_028C70_COLOR_2_10_10_10:
1196 return 10;
1197
1198 case V_028C70_COLOR_10_11_11:
1199 case V_028C70_COLOR_11_11_10:
1200 return 11;
1201
1202 case V_028C70_COLOR_16:
1203 case V_028C70_COLOR_16_16:
1204 case V_028C70_COLOR_16_16_16_16:
1205 return 16;
1206
1207 case V_028C70_COLOR_8_24:
1208 case V_028C70_COLOR_24_8:
1209 return 24;
1210
1211 case V_028C70_COLOR_32:
1212 case V_028C70_COLOR_32_32:
1213 case V_028C70_COLOR_32_32_32_32:
1214 case V_028C70_COLOR_X24_8_32_FLOAT:
1215 return 32;
1216 }
1217
1218 assert(!"Unknown maximum component size");
1219 return 0;
1220 }
1221
1222 static uint32_t si_translate_dbformat(enum pipe_format format)
1223 {
1224 switch (format) {
1225 case PIPE_FORMAT_Z16_UNORM:
1226 return V_028040_Z_16;
1227 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1228 case PIPE_FORMAT_X8Z24_UNORM:
1229 case PIPE_FORMAT_Z24X8_UNORM:
1230 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1231 return V_028040_Z_24; /* deprecated on SI */
1232 case PIPE_FORMAT_Z32_FLOAT:
1233 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1234 return V_028040_Z_32_FLOAT;
1235 default:
1236 return V_028040_Z_INVALID;
1237 }
1238 }
1239
1240 /*
1241 * Texture translation
1242 */
1243
1244 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1245 enum pipe_format format,
1246 const struct util_format_description *desc,
1247 int first_non_void)
1248 {
1249 struct si_screen *sscreen = (struct si_screen*)screen;
1250 bool enable_compressed_formats = (sscreen->b.info.drm_major == 2 &&
1251 sscreen->b.info.drm_minor >= 31) ||
1252 sscreen->b.info.drm_major == 3;
1253 boolean uniform = TRUE;
1254 int i;
1255
1256 /* Colorspace (return non-RGB formats directly). */
1257 switch (desc->colorspace) {
1258 /* Depth stencil formats */
1259 case UTIL_FORMAT_COLORSPACE_ZS:
1260 switch (format) {
1261 case PIPE_FORMAT_Z16_UNORM:
1262 return V_008F14_IMG_DATA_FORMAT_16;
1263 case PIPE_FORMAT_X24S8_UINT:
1264 case PIPE_FORMAT_Z24X8_UNORM:
1265 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1266 return V_008F14_IMG_DATA_FORMAT_8_24;
1267 case PIPE_FORMAT_X8Z24_UNORM:
1268 case PIPE_FORMAT_S8X24_UINT:
1269 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1270 return V_008F14_IMG_DATA_FORMAT_24_8;
1271 case PIPE_FORMAT_S8_UINT:
1272 return V_008F14_IMG_DATA_FORMAT_8;
1273 case PIPE_FORMAT_Z32_FLOAT:
1274 return V_008F14_IMG_DATA_FORMAT_32;
1275 case PIPE_FORMAT_X32_S8X24_UINT:
1276 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1277 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1278 default:
1279 goto out_unknown;
1280 }
1281
1282 case UTIL_FORMAT_COLORSPACE_YUV:
1283 goto out_unknown; /* TODO */
1284
1285 case UTIL_FORMAT_COLORSPACE_SRGB:
1286 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1287 goto out_unknown;
1288 break;
1289
1290 default:
1291 break;
1292 }
1293
1294 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1295 if (!enable_compressed_formats)
1296 goto out_unknown;
1297
1298 switch (format) {
1299 case PIPE_FORMAT_RGTC1_SNORM:
1300 case PIPE_FORMAT_LATC1_SNORM:
1301 case PIPE_FORMAT_RGTC1_UNORM:
1302 case PIPE_FORMAT_LATC1_UNORM:
1303 return V_008F14_IMG_DATA_FORMAT_BC4;
1304 case PIPE_FORMAT_RGTC2_SNORM:
1305 case PIPE_FORMAT_LATC2_SNORM:
1306 case PIPE_FORMAT_RGTC2_UNORM:
1307 case PIPE_FORMAT_LATC2_UNORM:
1308 return V_008F14_IMG_DATA_FORMAT_BC5;
1309 default:
1310 goto out_unknown;
1311 }
1312 }
1313
1314 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1315 if (!enable_compressed_formats)
1316 goto out_unknown;
1317
1318 switch (format) {
1319 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1320 case PIPE_FORMAT_BPTC_SRGBA:
1321 return V_008F14_IMG_DATA_FORMAT_BC7;
1322 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1323 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1324 return V_008F14_IMG_DATA_FORMAT_BC6;
1325 default:
1326 goto out_unknown;
1327 }
1328 }
1329
1330 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1331 switch (format) {
1332 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1333 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1334 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1335 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1336 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1337 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1338 default:
1339 goto out_unknown;
1340 }
1341 }
1342
1343 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1344 if (!enable_compressed_formats)
1345 goto out_unknown;
1346
1347 if (!util_format_s3tc_enabled) {
1348 goto out_unknown;
1349 }
1350
1351 switch (format) {
1352 case PIPE_FORMAT_DXT1_RGB:
1353 case PIPE_FORMAT_DXT1_RGBA:
1354 case PIPE_FORMAT_DXT1_SRGB:
1355 case PIPE_FORMAT_DXT1_SRGBA:
1356 return V_008F14_IMG_DATA_FORMAT_BC1;
1357 case PIPE_FORMAT_DXT3_RGBA:
1358 case PIPE_FORMAT_DXT3_SRGBA:
1359 return V_008F14_IMG_DATA_FORMAT_BC2;
1360 case PIPE_FORMAT_DXT5_RGBA:
1361 case PIPE_FORMAT_DXT5_SRGBA:
1362 return V_008F14_IMG_DATA_FORMAT_BC3;
1363 default:
1364 goto out_unknown;
1365 }
1366 }
1367
1368 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1369 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1370 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1371 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1372 }
1373
1374 /* R8G8Bx_SNORM - TODO CxV8U8 */
1375
1376 /* See whether the components are of the same size. */
1377 for (i = 1; i < desc->nr_channels; i++) {
1378 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1379 }
1380
1381 /* Non-uniform formats. */
1382 if (!uniform) {
1383 switch(desc->nr_channels) {
1384 case 3:
1385 if (desc->channel[0].size == 5 &&
1386 desc->channel[1].size == 6 &&
1387 desc->channel[2].size == 5) {
1388 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1389 }
1390 goto out_unknown;
1391 case 4:
1392 if (desc->channel[0].size == 5 &&
1393 desc->channel[1].size == 5 &&
1394 desc->channel[2].size == 5 &&
1395 desc->channel[3].size == 1) {
1396 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1397 }
1398 if (desc->channel[0].size == 10 &&
1399 desc->channel[1].size == 10 &&
1400 desc->channel[2].size == 10 &&
1401 desc->channel[3].size == 2) {
1402 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1403 }
1404 goto out_unknown;
1405 }
1406 goto out_unknown;
1407 }
1408
1409 if (first_non_void < 0 || first_non_void > 3)
1410 goto out_unknown;
1411
1412 /* uniform formats */
1413 switch (desc->channel[first_non_void].size) {
1414 case 4:
1415 switch (desc->nr_channels) {
1416 #if 0 /* Not supported for render targets */
1417 case 2:
1418 return V_008F14_IMG_DATA_FORMAT_4_4;
1419 #endif
1420 case 4:
1421 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1422 }
1423 break;
1424 case 8:
1425 switch (desc->nr_channels) {
1426 case 1:
1427 return V_008F14_IMG_DATA_FORMAT_8;
1428 case 2:
1429 return V_008F14_IMG_DATA_FORMAT_8_8;
1430 case 4:
1431 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1432 }
1433 break;
1434 case 16:
1435 switch (desc->nr_channels) {
1436 case 1:
1437 return V_008F14_IMG_DATA_FORMAT_16;
1438 case 2:
1439 return V_008F14_IMG_DATA_FORMAT_16_16;
1440 case 4:
1441 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1442 }
1443 break;
1444 case 32:
1445 switch (desc->nr_channels) {
1446 case 1:
1447 return V_008F14_IMG_DATA_FORMAT_32;
1448 case 2:
1449 return V_008F14_IMG_DATA_FORMAT_32_32;
1450 #if 0 /* Not supported for render targets */
1451 case 3:
1452 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1453 #endif
1454 case 4:
1455 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1456 }
1457 }
1458
1459 out_unknown:
1460 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1461 return ~0;
1462 }
1463
1464 static unsigned si_tex_wrap(unsigned wrap)
1465 {
1466 switch (wrap) {
1467 default:
1468 case PIPE_TEX_WRAP_REPEAT:
1469 return V_008F30_SQ_TEX_WRAP;
1470 case PIPE_TEX_WRAP_CLAMP:
1471 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1472 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1473 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1474 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1475 return V_008F30_SQ_TEX_CLAMP_BORDER;
1476 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1477 return V_008F30_SQ_TEX_MIRROR;
1478 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1479 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1480 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1481 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1482 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1483 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1484 }
1485 }
1486
1487 static unsigned si_tex_filter(unsigned filter)
1488 {
1489 switch (filter) {
1490 default:
1491 case PIPE_TEX_FILTER_NEAREST:
1492 return V_008F38_SQ_TEX_XY_FILTER_POINT;
1493 case PIPE_TEX_FILTER_LINEAR:
1494 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
1495 }
1496 }
1497
1498 static unsigned si_tex_mipfilter(unsigned filter)
1499 {
1500 switch (filter) {
1501 case PIPE_TEX_MIPFILTER_NEAREST:
1502 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1503 case PIPE_TEX_MIPFILTER_LINEAR:
1504 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1505 default:
1506 case PIPE_TEX_MIPFILTER_NONE:
1507 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1508 }
1509 }
1510
1511 static unsigned si_tex_compare(unsigned compare)
1512 {
1513 switch (compare) {
1514 default:
1515 case PIPE_FUNC_NEVER:
1516 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1517 case PIPE_FUNC_LESS:
1518 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1519 case PIPE_FUNC_EQUAL:
1520 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1521 case PIPE_FUNC_LEQUAL:
1522 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1523 case PIPE_FUNC_GREATER:
1524 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1525 case PIPE_FUNC_NOTEQUAL:
1526 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1527 case PIPE_FUNC_GEQUAL:
1528 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1529 case PIPE_FUNC_ALWAYS:
1530 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1531 }
1532 }
1533
1534 static unsigned si_tex_dim(unsigned dim, unsigned nr_samples)
1535 {
1536 switch (dim) {
1537 default:
1538 case PIPE_TEXTURE_1D:
1539 return V_008F1C_SQ_RSRC_IMG_1D;
1540 case PIPE_TEXTURE_1D_ARRAY:
1541 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1542 case PIPE_TEXTURE_2D:
1543 case PIPE_TEXTURE_RECT:
1544 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1545 V_008F1C_SQ_RSRC_IMG_2D;
1546 case PIPE_TEXTURE_2D_ARRAY:
1547 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1548 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1549 case PIPE_TEXTURE_3D:
1550 return V_008F1C_SQ_RSRC_IMG_3D;
1551 case PIPE_TEXTURE_CUBE:
1552 case PIPE_TEXTURE_CUBE_ARRAY:
1553 return V_008F1C_SQ_RSRC_IMG_CUBE;
1554 }
1555 }
1556
1557 /*
1558 * Format support testing
1559 */
1560
1561 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1562 {
1563 return si_translate_texformat(screen, format, util_format_description(format),
1564 util_format_get_first_non_void_channel(format)) != ~0U;
1565 }
1566
1567 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1568 const struct util_format_description *desc,
1569 int first_non_void)
1570 {
1571 unsigned type = desc->channel[first_non_void].type;
1572 int i;
1573
1574 if (type == UTIL_FORMAT_TYPE_FIXED)
1575 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1576
1577 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1578 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1579
1580 if (desc->nr_channels == 4 &&
1581 desc->channel[0].size == 10 &&
1582 desc->channel[1].size == 10 &&
1583 desc->channel[2].size == 10 &&
1584 desc->channel[3].size == 2)
1585 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1586
1587 /* See whether the components are of the same size. */
1588 for (i = 0; i < desc->nr_channels; i++) {
1589 if (desc->channel[first_non_void].size != desc->channel[i].size)
1590 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1591 }
1592
1593 switch (desc->channel[first_non_void].size) {
1594 case 8:
1595 switch (desc->nr_channels) {
1596 case 1:
1597 return V_008F0C_BUF_DATA_FORMAT_8;
1598 case 2:
1599 return V_008F0C_BUF_DATA_FORMAT_8_8;
1600 case 3:
1601 case 4:
1602 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1603 }
1604 break;
1605 case 16:
1606 switch (desc->nr_channels) {
1607 case 1:
1608 return V_008F0C_BUF_DATA_FORMAT_16;
1609 case 2:
1610 return V_008F0C_BUF_DATA_FORMAT_16_16;
1611 case 3:
1612 case 4:
1613 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1614 }
1615 break;
1616 case 32:
1617 /* From the Southern Islands ISA documentation about MTBUF:
1618 * 'Memory reads of data in memory that is 32 or 64 bits do not
1619 * undergo any format conversion.'
1620 */
1621 if (type != UTIL_FORMAT_TYPE_FLOAT &&
1622 !desc->channel[first_non_void].pure_integer)
1623 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1624
1625 switch (desc->nr_channels) {
1626 case 1:
1627 return V_008F0C_BUF_DATA_FORMAT_32;
1628 case 2:
1629 return V_008F0C_BUF_DATA_FORMAT_32_32;
1630 case 3:
1631 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1632 case 4:
1633 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1634 }
1635 break;
1636 }
1637
1638 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1639 }
1640
1641 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1642 const struct util_format_description *desc,
1643 int first_non_void)
1644 {
1645 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1646 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1647
1648 switch (desc->channel[first_non_void].type) {
1649 case UTIL_FORMAT_TYPE_SIGNED:
1650 if (desc->channel[first_non_void].normalized)
1651 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1652 else if (desc->channel[first_non_void].pure_integer)
1653 return V_008F0C_BUF_NUM_FORMAT_SINT;
1654 else
1655 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1656 break;
1657 case UTIL_FORMAT_TYPE_UNSIGNED:
1658 if (desc->channel[first_non_void].normalized)
1659 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1660 else if (desc->channel[first_non_void].pure_integer)
1661 return V_008F0C_BUF_NUM_FORMAT_UINT;
1662 else
1663 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1664 break;
1665 case UTIL_FORMAT_TYPE_FLOAT:
1666 default:
1667 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1668 }
1669 }
1670
1671 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
1672 {
1673 const struct util_format_description *desc;
1674 int first_non_void;
1675 unsigned data_format;
1676
1677 desc = util_format_description(format);
1678 first_non_void = util_format_get_first_non_void_channel(format);
1679 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1680 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
1681 }
1682
1683 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1684 {
1685 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1686 r600_translate_colorswap(format) != ~0U;
1687 }
1688
1689 static bool si_is_zs_format_supported(enum pipe_format format)
1690 {
1691 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1692 }
1693
1694 boolean si_is_format_supported(struct pipe_screen *screen,
1695 enum pipe_format format,
1696 enum pipe_texture_target target,
1697 unsigned sample_count,
1698 unsigned usage)
1699 {
1700 unsigned retval = 0;
1701
1702 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1703 R600_ERR("r600: unsupported texture type %d\n", target);
1704 return FALSE;
1705 }
1706
1707 if (!util_format_is_supported(format, usage))
1708 return FALSE;
1709
1710 if (sample_count > 1) {
1711 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
1712 return FALSE;
1713
1714 switch (sample_count) {
1715 case 2:
1716 case 4:
1717 case 8:
1718 break;
1719 default:
1720 return FALSE;
1721 }
1722 }
1723
1724 if (usage & PIPE_BIND_SAMPLER_VIEW) {
1725 if (target == PIPE_BUFFER) {
1726 if (si_is_vertex_format_supported(screen, format))
1727 retval |= PIPE_BIND_SAMPLER_VIEW;
1728 } else {
1729 if (si_is_sampler_format_supported(screen, format))
1730 retval |= PIPE_BIND_SAMPLER_VIEW;
1731 }
1732 }
1733
1734 if ((usage & (PIPE_BIND_RENDER_TARGET |
1735 PIPE_BIND_DISPLAY_TARGET |
1736 PIPE_BIND_SCANOUT |
1737 PIPE_BIND_SHARED |
1738 PIPE_BIND_BLENDABLE)) &&
1739 si_is_colorbuffer_format_supported(format)) {
1740 retval |= usage &
1741 (PIPE_BIND_RENDER_TARGET |
1742 PIPE_BIND_DISPLAY_TARGET |
1743 PIPE_BIND_SCANOUT |
1744 PIPE_BIND_SHARED);
1745 if (!util_format_is_pure_integer(format) &&
1746 !util_format_is_depth_or_stencil(format))
1747 retval |= usage & PIPE_BIND_BLENDABLE;
1748 }
1749
1750 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1751 si_is_zs_format_supported(format)) {
1752 retval |= PIPE_BIND_DEPTH_STENCIL;
1753 }
1754
1755 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
1756 si_is_vertex_format_supported(screen, format)) {
1757 retval |= PIPE_BIND_VERTEX_BUFFER;
1758 }
1759
1760 if (usage & PIPE_BIND_TRANSFER_READ)
1761 retval |= PIPE_BIND_TRANSFER_READ;
1762 if (usage & PIPE_BIND_TRANSFER_WRITE)
1763 retval |= PIPE_BIND_TRANSFER_WRITE;
1764
1765 return retval == usage;
1766 }
1767
1768 unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
1769 {
1770 unsigned tile_mode_index = 0;
1771
1772 if (stencil) {
1773 tile_mode_index = rtex->surface.stencil_tiling_index[level];
1774 } else {
1775 tile_mode_index = rtex->surface.tiling_index[level];
1776 }
1777 return tile_mode_index;
1778 }
1779
1780 /*
1781 * framebuffer handling
1782 */
1783
1784 static void si_initialize_color_surface(struct si_context *sctx,
1785 struct r600_surface *surf)
1786 {
1787 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1788 unsigned level = surf->base.u.tex.level;
1789 uint64_t offset = rtex->surface.level[level].offset;
1790 unsigned pitch, slice;
1791 unsigned color_info, color_attrib, color_pitch, color_view;
1792 unsigned tile_mode_index;
1793 unsigned format, swap, ntype, endian;
1794 const struct util_format_description *desc;
1795 int i;
1796 unsigned blend_clamp = 0, blend_bypass = 0;
1797 unsigned max_comp_size;
1798
1799 /* Layered rendering doesn't work with LINEAR_GENERAL.
1800 * (LINEAR_ALIGNED and others work) */
1801 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) {
1802 assert(surf->base.u.tex.first_layer == surf->base.u.tex.last_layer);
1803 offset += rtex->surface.level[level].slice_size *
1804 surf->base.u.tex.first_layer;
1805 color_view = 0;
1806 } else {
1807 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
1808 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
1809 }
1810
1811 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1812 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1813 if (slice) {
1814 slice = slice - 1;
1815 }
1816
1817 tile_mode_index = si_tile_mode_index(rtex, level, false);
1818
1819 desc = util_format_description(surf->base.format);
1820 for (i = 0; i < 4; i++) {
1821 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1822 break;
1823 }
1824 }
1825 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1826 ntype = V_028C70_NUMBER_FLOAT;
1827 } else {
1828 ntype = V_028C70_NUMBER_UNORM;
1829 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1830 ntype = V_028C70_NUMBER_SRGB;
1831 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1832 if (desc->channel[i].pure_integer) {
1833 ntype = V_028C70_NUMBER_SINT;
1834 } else {
1835 assert(desc->channel[i].normalized);
1836 ntype = V_028C70_NUMBER_SNORM;
1837 }
1838 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1839 if (desc->channel[i].pure_integer) {
1840 ntype = V_028C70_NUMBER_UINT;
1841 } else {
1842 assert(desc->channel[i].normalized);
1843 ntype = V_028C70_NUMBER_UNORM;
1844 }
1845 }
1846 }
1847
1848 format = si_translate_colorformat(surf->base.format);
1849 if (format == V_028C70_COLOR_INVALID) {
1850 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
1851 }
1852 assert(format != V_028C70_COLOR_INVALID);
1853 swap = r600_translate_colorswap(surf->base.format);
1854 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1855 endian = V_028C70_ENDIAN_NONE;
1856 } else {
1857 endian = si_colorformat_endian_swap(format);
1858 }
1859
1860 /* blend clamp should be set for all NORM/SRGB types */
1861 if (ntype == V_028C70_NUMBER_UNORM ||
1862 ntype == V_028C70_NUMBER_SNORM ||
1863 ntype == V_028C70_NUMBER_SRGB)
1864 blend_clamp = 1;
1865
1866 /* set blend bypass according to docs if SINT/UINT or
1867 8/24 COLOR variants */
1868 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1869 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1870 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1871 blend_clamp = 0;
1872 blend_bypass = 1;
1873 }
1874
1875 color_info = S_028C70_FORMAT(format) |
1876 S_028C70_COMP_SWAP(swap) |
1877 S_028C70_BLEND_CLAMP(blend_clamp) |
1878 S_028C70_BLEND_BYPASS(blend_bypass) |
1879 S_028C70_NUMBER_TYPE(ntype) |
1880 S_028C70_ENDIAN(endian);
1881
1882 color_pitch = S_028C64_TILE_MAX(pitch);
1883
1884 color_attrib = S_028C74_TILE_MODE_INDEX(tile_mode_index) |
1885 S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == UTIL_FORMAT_SWIZZLE_1);
1886
1887 if (rtex->resource.b.b.nr_samples > 1) {
1888 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1889
1890 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1891 S_028C74_NUM_FRAGMENTS(log_samples);
1892
1893 if (rtex->fmask.size) {
1894 color_info |= S_028C70_COMPRESSION(1);
1895 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
1896
1897 color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(rtex->fmask.tile_mode_index);
1898
1899 if (sctx->b.chip_class == SI) {
1900 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
1901 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1902 }
1903 if (sctx->b.chip_class >= CIK) {
1904 color_pitch |= S_028C64_FMASK_TILE_MAX(rtex->fmask.pitch / 8 - 1);
1905 }
1906 }
1907 }
1908
1909 offset += rtex->resource.gpu_address;
1910
1911 surf->cb_color_base = offset >> 8;
1912 surf->cb_color_pitch = color_pitch;
1913 surf->cb_color_slice = S_028C68_TILE_MAX(slice);
1914 surf->cb_color_view = color_view;
1915 surf->cb_color_info = color_info;
1916 surf->cb_color_attrib = color_attrib;
1917
1918 if (sctx->b.chip_class >= VI)
1919 surf->cb_dcc_control = S_028C78_OVERWRITE_COMBINER_DISABLE(1);
1920
1921 if (rtex->fmask.size) {
1922 surf->cb_color_fmask = (offset + rtex->fmask.offset) >> 8;
1923 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max);
1924 } else {
1925 /* This must be set for fast clear to work without FMASK. */
1926 surf->cb_color_fmask = surf->cb_color_base;
1927 surf->cb_color_fmask_slice = surf->cb_color_slice;
1928 surf->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
1929
1930 if (sctx->b.chip_class == SI) {
1931 unsigned bankh = util_logbase2(rtex->surface.bankh);
1932 surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
1933 }
1934
1935 if (sctx->b.chip_class >= CIK) {
1936 surf->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch);
1937 }
1938 }
1939
1940 /* Determine pixel shader export format */
1941 max_comp_size = si_colorformat_max_comp_size(format);
1942 if (ntype == V_028C70_NUMBER_SRGB ||
1943 ((ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM) &&
1944 max_comp_size <= 10) ||
1945 (ntype == V_028C70_NUMBER_FLOAT && max_comp_size <= 16)) {
1946 surf->export_16bpc = true;
1947 }
1948
1949 surf->color_initialized = true;
1950 }
1951
1952 static void si_init_depth_surface(struct si_context *sctx,
1953 struct r600_surface *surf)
1954 {
1955 struct si_screen *sscreen = sctx->screen;
1956 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1957 unsigned level = surf->base.u.tex.level;
1958 struct radeon_surf_level *levelinfo = &rtex->surface.level[level];
1959 unsigned format, tile_mode_index, array_mode;
1960 unsigned macro_aspect, tile_split, stile_split, bankh, bankw, nbanks, pipe_config;
1961 uint32_t z_info, s_info, db_depth_info;
1962 uint64_t z_offs, s_offs;
1963 uint32_t db_htile_data_base, db_htile_surface, pa_su_poly_offset_db_fmt_cntl = 0;
1964
1965 switch (sctx->framebuffer.state.zsbuf->texture->format) {
1966 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1967 case PIPE_FORMAT_X8Z24_UNORM:
1968 case PIPE_FORMAT_Z24X8_UNORM:
1969 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1970 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
1971 break;
1972 case PIPE_FORMAT_Z32_FLOAT:
1973 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1974 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
1975 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1976 break;
1977 case PIPE_FORMAT_Z16_UNORM:
1978 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
1979 break;
1980 default:
1981 assert(0);
1982 }
1983
1984 format = si_translate_dbformat(rtex->resource.b.b.format);
1985
1986 if (format == V_028040_Z_INVALID) {
1987 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
1988 }
1989 assert(format != V_028040_Z_INVALID);
1990
1991 s_offs = z_offs = rtex->resource.gpu_address;
1992 z_offs += rtex->surface.level[level].offset;
1993 s_offs += rtex->surface.stencil_level[level].offset;
1994
1995 db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
1996
1997 z_info = S_028040_FORMAT(format);
1998 if (rtex->resource.b.b.nr_samples > 1) {
1999 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
2000 }
2001
2002 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
2003 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
2004 else
2005 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
2006
2007 if (sctx->b.chip_class >= CIK) {
2008 switch (rtex->surface.level[level].mode) {
2009 case RADEON_SURF_MODE_2D:
2010 array_mode = V_02803C_ARRAY_2D_TILED_THIN1;
2011 break;
2012 case RADEON_SURF_MODE_1D:
2013 case RADEON_SURF_MODE_LINEAR_ALIGNED:
2014 case RADEON_SURF_MODE_LINEAR:
2015 default:
2016 array_mode = V_02803C_ARRAY_1D_TILED_THIN1;
2017 break;
2018 }
2019 tile_split = rtex->surface.tile_split;
2020 stile_split = rtex->surface.stencil_tile_split;
2021 macro_aspect = rtex->surface.mtilea;
2022 bankw = rtex->surface.bankw;
2023 bankh = rtex->surface.bankh;
2024 tile_split = cik_tile_split(tile_split);
2025 stile_split = cik_tile_split(stile_split);
2026 macro_aspect = cik_macro_tile_aspect(macro_aspect);
2027 bankw = cik_bank_wh(bankw);
2028 bankh = cik_bank_wh(bankh);
2029 nbanks = si_num_banks(sscreen, rtex);
2030 tile_mode_index = si_tile_mode_index(rtex, level, false);
2031 pipe_config = cik_db_pipe_config(sscreen, tile_mode_index);
2032
2033 db_depth_info |= S_02803C_ARRAY_MODE(array_mode) |
2034 S_02803C_PIPE_CONFIG(pipe_config) |
2035 S_02803C_BANK_WIDTH(bankw) |
2036 S_02803C_BANK_HEIGHT(bankh) |
2037 S_02803C_MACRO_TILE_ASPECT(macro_aspect) |
2038 S_02803C_NUM_BANKS(nbanks);
2039 z_info |= S_028040_TILE_SPLIT(tile_split);
2040 s_info |= S_028044_TILE_SPLIT(stile_split);
2041 } else {
2042 tile_mode_index = si_tile_mode_index(rtex, level, false);
2043 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2044 tile_mode_index = si_tile_mode_index(rtex, level, true);
2045 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2046 }
2047
2048 /* HiZ aka depth buffer htile */
2049 /* use htile only for first level */
2050 if (rtex->htile_buffer && !level) {
2051 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2052 S_028040_ALLOW_EXPCLEAR(1);
2053
2054 /* Use all of the htile_buffer for depth, because we don't
2055 * use HTILE for stencil because of FAST_STENCIL_DISABLE. */
2056 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2057
2058 uint64_t va = rtex->htile_buffer->gpu_address;
2059 db_htile_data_base = va >> 8;
2060 db_htile_surface = S_028ABC_FULL_CACHE(1);
2061 } else {
2062 db_htile_data_base = 0;
2063 db_htile_surface = 0;
2064 }
2065
2066 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2067
2068 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2069 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2070 surf->db_htile_data_base = db_htile_data_base;
2071 surf->db_depth_info = db_depth_info;
2072 surf->db_z_info = z_info;
2073 surf->db_stencil_info = s_info;
2074 surf->db_depth_base = z_offs >> 8;
2075 surf->db_stencil_base = s_offs >> 8;
2076 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2077 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2078 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2079 levelinfo->nblk_y) / 64 - 1);
2080 surf->db_htile_surface = db_htile_surface;
2081 surf->pa_su_poly_offset_db_fmt_cntl = pa_su_poly_offset_db_fmt_cntl;
2082
2083 surf->depth_initialized = true;
2084 }
2085
2086 static void si_set_framebuffer_state(struct pipe_context *ctx,
2087 const struct pipe_framebuffer_state *state)
2088 {
2089 struct si_context *sctx = (struct si_context *)ctx;
2090 struct pipe_constant_buffer constbuf = {0};
2091 struct r600_surface *surf = NULL;
2092 struct r600_texture *rtex;
2093 bool old_cb0_is_integer = sctx->framebuffer.cb0_is_integer;
2094 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2095 int i;
2096
2097 /* Only flush TC when changing the framebuffer state, because
2098 * the only client not using TC that can change textures is
2099 * the framebuffer.
2100 *
2101 * Flush all CB and DB caches here because all buffers can be used
2102 * for write by both TC (with shader image stores) and CB/DB.
2103 */
2104 sctx->b.flags |= SI_CONTEXT_INV_TC_L1 |
2105 SI_CONTEXT_INV_TC_L2 |
2106 SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER;
2107
2108 /* Take the maximum of the old and new count. If the new count is lower,
2109 * dirtying is needed to disable the unbound colorbuffers.
2110 */
2111 sctx->framebuffer.dirty_cbufs |=
2112 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2113 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2114
2115 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2116
2117 sctx->framebuffer.export_16bpc = 0;
2118 sctx->framebuffer.compressed_cb_mask = 0;
2119 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2120 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2121 sctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
2122 util_format_is_pure_integer(state->cbufs[0]->format);
2123
2124 if (sctx->framebuffer.cb0_is_integer != old_cb0_is_integer)
2125 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2126
2127 for (i = 0; i < state->nr_cbufs; i++) {
2128 if (!state->cbufs[i])
2129 continue;
2130
2131 surf = (struct r600_surface*)state->cbufs[i];
2132 rtex = (struct r600_texture*)surf->base.texture;
2133
2134 if (!surf->color_initialized) {
2135 si_initialize_color_surface(sctx, surf);
2136 }
2137
2138 if (surf->export_16bpc) {
2139 sctx->framebuffer.export_16bpc |= 1 << i;
2140 }
2141
2142 if (rtex->fmask.size && rtex->cmask.size) {
2143 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2144 }
2145 r600_context_add_resource_size(ctx, surf->base.texture);
2146 }
2147 /* Set the 16BPC export for possible dual-src blending. */
2148 if (i == 1 && surf && surf->export_16bpc) {
2149 sctx->framebuffer.export_16bpc |= 1 << 1;
2150 }
2151
2152 assert(!(sctx->framebuffer.export_16bpc & ~0xff));
2153
2154 if (state->zsbuf) {
2155 surf = (struct r600_surface*)state->zsbuf;
2156
2157 if (!surf->depth_initialized) {
2158 si_init_depth_surface(sctx, surf);
2159 }
2160 r600_context_add_resource_size(ctx, surf->base.texture);
2161 }
2162
2163 si_update_poly_offset_state(sctx);
2164 si_mark_atom_dirty(sctx, &sctx->cb_target_mask);
2165 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
2166
2167 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2168 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2169 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2170
2171 /* Set sample locations as fragment shader constants. */
2172 switch (sctx->framebuffer.nr_samples) {
2173 case 1:
2174 constbuf.user_buffer = sctx->b.sample_locations_1x;
2175 break;
2176 case 2:
2177 constbuf.user_buffer = sctx->b.sample_locations_2x;
2178 break;
2179 case 4:
2180 constbuf.user_buffer = sctx->b.sample_locations_4x;
2181 break;
2182 case 8:
2183 constbuf.user_buffer = sctx->b.sample_locations_8x;
2184 break;
2185 case 16:
2186 constbuf.user_buffer = sctx->b.sample_locations_16x;
2187 break;
2188 default:
2189 assert(0);
2190 }
2191 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2192 ctx->set_constant_buffer(ctx, PIPE_SHADER_FRAGMENT,
2193 SI_DRIVER_STATE_CONST_BUF, &constbuf);
2194
2195 /* Smoothing (only possible with nr_samples == 1) uses the same
2196 * sample locations as the MSAA it simulates.
2197 *
2198 * Therefore, don't update the sample locations when
2199 * transitioning from no AA to smoothing-equivalent AA, and
2200 * vice versa.
2201 */
2202 if ((sctx->framebuffer.nr_samples != 1 ||
2203 old_nr_samples != SI_NUM_SMOOTH_AA_SAMPLES) &&
2204 (sctx->framebuffer.nr_samples != SI_NUM_SMOOTH_AA_SAMPLES ||
2205 old_nr_samples != 1))
2206 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs);
2207 }
2208 }
2209
2210 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
2211 {
2212 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
2213 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2214 unsigned i, nr_cbufs = state->nr_cbufs;
2215 struct r600_texture *tex = NULL;
2216 struct r600_surface *cb = NULL;
2217
2218 /* Colorbuffers. */
2219 for (i = 0; i < nr_cbufs; i++) {
2220 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2221 continue;
2222
2223 cb = (struct r600_surface*)state->cbufs[i];
2224 if (!cb) {
2225 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2226 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2227 continue;
2228 }
2229
2230 tex = (struct r600_texture *)cb->base.texture;
2231 radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx,
2232 &tex->resource, RADEON_USAGE_READWRITE,
2233 tex->surface.nsamples > 1 ?
2234 RADEON_PRIO_COLOR_BUFFER_MSAA :
2235 RADEON_PRIO_COLOR_BUFFER);
2236
2237 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2238 radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx,
2239 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2240 RADEON_PRIO_COLOR_META);
2241 }
2242
2243 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
2244 sctx->b.chip_class >= VI ? 14 : 13);
2245 radeon_emit(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
2246 radeon_emit(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
2247 radeon_emit(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
2248 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
2249 radeon_emit(cs, cb->cb_color_info | tex->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
2250 radeon_emit(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
2251 radeon_emit(cs, cb->cb_dcc_control); /* R_028C78_CB_COLOR0_DCC_CONTROL */
2252 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
2253 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
2254 radeon_emit(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
2255 radeon_emit(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
2256 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
2257 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
2258
2259 if (sctx->b.chip_class >= VI)
2260 radeon_emit(cs, 0); /* R_028C94_CB_COLOR0_DCC_BASE */
2261 }
2262 /* set CB_COLOR1_INFO for possible dual-src blending */
2263 if (i == 1 && state->cbufs[0] &&
2264 sctx->framebuffer.dirty_cbufs & (1 << 0)) {
2265 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
2266 cb->cb_color_info | tex->cb_color_info);
2267 i++;
2268 }
2269 for (; i < 8 ; i++)
2270 if (sctx->framebuffer.dirty_cbufs & (1 << i))
2271 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
2272
2273 /* ZS buffer. */
2274 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
2275 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
2276 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
2277
2278 radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx,
2279 &rtex->resource, RADEON_USAGE_READWRITE,
2280 zb->base.texture->nr_samples > 1 ?
2281 RADEON_PRIO_DEPTH_BUFFER_MSAA :
2282 RADEON_PRIO_DEPTH_BUFFER);
2283
2284 if (zb->db_htile_data_base) {
2285 radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx,
2286 rtex->htile_buffer, RADEON_USAGE_READWRITE,
2287 RADEON_PRIO_DEPTH_META);
2288 }
2289
2290 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
2291 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
2292
2293 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
2294 radeon_emit(cs, zb->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
2295 radeon_emit(cs, zb->db_z_info | /* R_028040_DB_Z_INFO */
2296 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
2297 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
2298 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
2299 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
2300 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
2301 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
2302 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
2303 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
2304
2305 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
2306 radeon_set_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
2307 radeon_set_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2308 zb->pa_su_poly_offset_db_fmt_cntl);
2309 } else if (sctx->framebuffer.dirty_zsbuf) {
2310 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
2311 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
2312 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
2313 }
2314
2315 /* Framebuffer dimensions. */
2316 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2317 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2318 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
2319
2320 sctx->framebuffer.dirty_cbufs = 0;
2321 sctx->framebuffer.dirty_zsbuf = false;
2322 }
2323
2324 static void si_emit_msaa_sample_locs(struct si_context *sctx,
2325 struct r600_atom *atom)
2326 {
2327 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
2328 unsigned nr_samples = sctx->framebuffer.nr_samples;
2329
2330 cayman_emit_msaa_sample_locs(cs, nr_samples > 1 ? nr_samples :
2331 SI_NUM_SMOOTH_AA_SAMPLES);
2332 }
2333
2334 static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom)
2335 {
2336 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
2337
2338 cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples,
2339 sctx->ps_iter_samples,
2340 sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0);
2341 }
2342
2343
2344 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
2345 {
2346 struct si_context *sctx = (struct si_context *)ctx;
2347
2348 if (sctx->ps_iter_samples == min_samples)
2349 return;
2350
2351 sctx->ps_iter_samples = min_samples;
2352
2353 if (sctx->framebuffer.nr_samples > 1)
2354 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2355 }
2356
2357 /*
2358 * Samplers
2359 */
2360
2361 /**
2362 * Create a sampler view.
2363 *
2364 * @param ctx context
2365 * @param texture texture
2366 * @param state sampler view template
2367 * @param width0 width0 override (for compressed textures as int)
2368 * @param height0 height0 override (for compressed textures as int)
2369 * @param force_level set the base address to the level (for compressed textures)
2370 */
2371 struct pipe_sampler_view *
2372 si_create_sampler_view_custom(struct pipe_context *ctx,
2373 struct pipe_resource *texture,
2374 const struct pipe_sampler_view *state,
2375 unsigned width0, unsigned height0,
2376 unsigned force_level)
2377 {
2378 struct si_context *sctx = (struct si_context*)ctx;
2379 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
2380 struct r600_texture *tmp = (struct r600_texture*)texture;
2381 const struct util_format_description *desc;
2382 unsigned format, num_format, base_level, first_level, last_level;
2383 uint32_t pitch = 0;
2384 unsigned char state_swizzle[4], swizzle[4];
2385 unsigned height, depth, width;
2386 enum pipe_format pipe_format = state->format;
2387 struct radeon_surf_level *surflevel;
2388 int first_non_void;
2389 uint64_t va;
2390
2391 if (view == NULL)
2392 return NULL;
2393
2394 /* initialize base object */
2395 view->base = *state;
2396 view->base.texture = NULL;
2397 view->base.reference.count = 1;
2398 view->base.context = ctx;
2399
2400 /* NULL resource, obey swizzle (only ZERO and ONE make sense). */
2401 if (!texture) {
2402 view->state[3] = S_008F1C_DST_SEL_X(si_map_swizzle(state->swizzle_r)) |
2403 S_008F1C_DST_SEL_Y(si_map_swizzle(state->swizzle_g)) |
2404 S_008F1C_DST_SEL_Z(si_map_swizzle(state->swizzle_b)) |
2405 S_008F1C_DST_SEL_W(si_map_swizzle(state->swizzle_a)) |
2406 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D);
2407 return &view->base;
2408 }
2409
2410 pipe_resource_reference(&view->base.texture, texture);
2411 view->resource = &tmp->resource;
2412
2413 /* Buffer resource. */
2414 if (texture->target == PIPE_BUFFER) {
2415 unsigned stride, num_records;
2416
2417 desc = util_format_description(state->format);
2418 first_non_void = util_format_get_first_non_void_channel(state->format);
2419 stride = desc->block.bits / 8;
2420 va = tmp->resource.gpu_address + state->u.buf.first_element*stride;
2421 format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
2422 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
2423
2424 num_records = state->u.buf.last_element + 1 - state->u.buf.first_element;
2425 num_records = MIN2(num_records, texture->width0 / stride);
2426
2427 if (sctx->b.chip_class >= VI)
2428 num_records *= stride;
2429
2430 view->state[4] = va;
2431 view->state[5] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
2432 S_008F04_STRIDE(stride);
2433 view->state[6] = num_records;
2434 view->state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2435 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2436 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2437 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2438 S_008F0C_NUM_FORMAT(num_format) |
2439 S_008F0C_DATA_FORMAT(format);
2440
2441 LIST_ADDTAIL(&view->list, &sctx->b.texture_buffers);
2442 return &view->base;
2443 }
2444
2445 state_swizzle[0] = state->swizzle_r;
2446 state_swizzle[1] = state->swizzle_g;
2447 state_swizzle[2] = state->swizzle_b;
2448 state_swizzle[3] = state->swizzle_a;
2449
2450 surflevel = tmp->surface.level;
2451
2452 /* Texturing with separate depth and stencil. */
2453 if (tmp->is_depth && !tmp->is_flushing_texture) {
2454 switch (pipe_format) {
2455 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2456 pipe_format = PIPE_FORMAT_Z32_FLOAT;
2457 break;
2458 case PIPE_FORMAT_X8Z24_UNORM:
2459 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2460 /* Z24 is always stored like this. */
2461 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
2462 break;
2463 case PIPE_FORMAT_X24S8_UINT:
2464 case PIPE_FORMAT_S8X24_UINT:
2465 case PIPE_FORMAT_X32_S8X24_UINT:
2466 pipe_format = PIPE_FORMAT_S8_UINT;
2467 surflevel = tmp->surface.stencil_level;
2468 break;
2469 default:;
2470 }
2471 }
2472
2473 desc = util_format_description(pipe_format);
2474
2475 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2476 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2477 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2478
2479 switch (pipe_format) {
2480 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2481 case PIPE_FORMAT_X24S8_UINT:
2482 case PIPE_FORMAT_X32_S8X24_UINT:
2483 case PIPE_FORMAT_X8Z24_UNORM:
2484 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
2485 break;
2486 default:
2487 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
2488 }
2489 } else {
2490 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2491 }
2492
2493 first_non_void = util_format_get_first_non_void_channel(pipe_format);
2494
2495 switch (pipe_format) {
2496 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2497 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2498 break;
2499 default:
2500 if (first_non_void < 0) {
2501 if (util_format_is_compressed(pipe_format)) {
2502 switch (pipe_format) {
2503 case PIPE_FORMAT_DXT1_SRGB:
2504 case PIPE_FORMAT_DXT1_SRGBA:
2505 case PIPE_FORMAT_DXT3_SRGBA:
2506 case PIPE_FORMAT_DXT5_SRGBA:
2507 case PIPE_FORMAT_BPTC_SRGBA:
2508 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2509 break;
2510 case PIPE_FORMAT_RGTC1_SNORM:
2511 case PIPE_FORMAT_LATC1_SNORM:
2512 case PIPE_FORMAT_RGTC2_SNORM:
2513 case PIPE_FORMAT_LATC2_SNORM:
2514 /* implies float, so use SNORM/UNORM to determine
2515 whether data is signed or not */
2516 case PIPE_FORMAT_BPTC_RGB_FLOAT:
2517 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2518 break;
2519 default:
2520 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2521 break;
2522 }
2523 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
2524 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2525 } else {
2526 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2527 }
2528 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
2529 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2530 } else {
2531 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2532
2533 switch (desc->channel[first_non_void].type) {
2534 case UTIL_FORMAT_TYPE_FLOAT:
2535 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2536 break;
2537 case UTIL_FORMAT_TYPE_SIGNED:
2538 if (desc->channel[first_non_void].normalized)
2539 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2540 else if (desc->channel[first_non_void].pure_integer)
2541 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
2542 else
2543 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
2544 break;
2545 case UTIL_FORMAT_TYPE_UNSIGNED:
2546 if (desc->channel[first_non_void].normalized)
2547 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2548 else if (desc->channel[first_non_void].pure_integer)
2549 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
2550 else
2551 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
2552 }
2553 }
2554 }
2555
2556 format = si_translate_texformat(ctx->screen, pipe_format, desc, first_non_void);
2557 if (format == ~0) {
2558 format = 0;
2559 }
2560
2561 base_level = 0;
2562 first_level = state->u.tex.first_level;
2563 last_level = state->u.tex.last_level;
2564 width = width0;
2565 height = height0;
2566 depth = texture->depth0;
2567
2568 if (force_level) {
2569 assert(force_level == first_level &&
2570 force_level == last_level);
2571 base_level = force_level;
2572 first_level = 0;
2573 last_level = 0;
2574 width = u_minify(width, force_level);
2575 height = u_minify(height, force_level);
2576 depth = u_minify(depth, force_level);
2577 }
2578
2579 pitch = surflevel[base_level].nblk_x * util_format_get_blockwidth(pipe_format);
2580
2581 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
2582 height = 1;
2583 depth = texture->array_size;
2584 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
2585 depth = texture->array_size;
2586 } else if (texture->target == PIPE_TEXTURE_CUBE_ARRAY)
2587 depth = texture->array_size / 6;
2588
2589 va = tmp->resource.gpu_address + surflevel[base_level].offset;
2590
2591 view->state[0] = va >> 8;
2592 view->state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) |
2593 S_008F14_DATA_FORMAT(format) |
2594 S_008F14_NUM_FORMAT(num_format));
2595 view->state[2] = (S_008F18_WIDTH(width - 1) |
2596 S_008F18_HEIGHT(height - 1));
2597 view->state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2598 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2599 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2600 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2601 S_008F1C_BASE_LEVEL(texture->nr_samples > 1 ?
2602 0 : first_level) |
2603 S_008F1C_LAST_LEVEL(texture->nr_samples > 1 ?
2604 util_logbase2(texture->nr_samples) :
2605 last_level) |
2606 S_008F1C_TILING_INDEX(si_tile_mode_index(tmp, base_level, false)) |
2607 S_008F1C_POW2_PAD(texture->last_level > 0) |
2608 S_008F1C_TYPE(si_tex_dim(texture->target, texture->nr_samples)));
2609 view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
2610 view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2611 S_008F24_LAST_ARRAY(state->u.tex.last_layer));
2612 view->state[6] = 0;
2613 view->state[7] = 0;
2614
2615 /* Initialize the sampler view for FMASK. */
2616 if (tmp->fmask.size) {
2617 uint64_t va = tmp->resource.gpu_address + tmp->fmask.offset;
2618 uint32_t fmask_format;
2619
2620 switch (texture->nr_samples) {
2621 case 2:
2622 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
2623 break;
2624 case 4:
2625 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
2626 break;
2627 case 8:
2628 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
2629 break;
2630 default:
2631 assert(0);
2632 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
2633 }
2634
2635 view->fmask_state[0] = va >> 8;
2636 view->fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
2637 S_008F14_DATA_FORMAT(fmask_format) |
2638 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT);
2639 view->fmask_state[2] = S_008F18_WIDTH(width - 1) |
2640 S_008F18_HEIGHT(height - 1);
2641 view->fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
2642 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
2643 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
2644 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
2645 S_008F1C_TILING_INDEX(tmp->fmask.tile_mode_index) |
2646 S_008F1C_TYPE(si_tex_dim(texture->target, 0));
2647 view->fmask_state[4] = S_008F20_DEPTH(depth - 1) |
2648 S_008F20_PITCH(tmp->fmask.pitch - 1);
2649 view->fmask_state[5] = S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2650 S_008F24_LAST_ARRAY(state->u.tex.last_layer);
2651 view->fmask_state[6] = 0;
2652 view->fmask_state[7] = 0;
2653 }
2654
2655 return &view->base;
2656 }
2657
2658 static struct pipe_sampler_view *
2659 si_create_sampler_view(struct pipe_context *ctx,
2660 struct pipe_resource *texture,
2661 const struct pipe_sampler_view *state)
2662 {
2663 return si_create_sampler_view_custom(ctx, texture, state,
2664 texture ? texture->width0 : 0,
2665 texture ? texture->height0 : 0, 0);
2666 }
2667
2668 static void si_sampler_view_destroy(struct pipe_context *ctx,
2669 struct pipe_sampler_view *state)
2670 {
2671 struct si_sampler_view *view = (struct si_sampler_view *)state;
2672
2673 if (view->resource && view->resource->b.b.target == PIPE_BUFFER)
2674 LIST_DELINIT(&view->list);
2675
2676 pipe_resource_reference(&state->texture, NULL);
2677 FREE(view);
2678 }
2679
2680 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
2681 {
2682 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
2683 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
2684 (linear_filter &&
2685 (wrap == PIPE_TEX_WRAP_CLAMP ||
2686 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
2687 }
2688
2689 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
2690 {
2691 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
2692 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
2693
2694 return (state->border_color.ui[0] || state->border_color.ui[1] ||
2695 state->border_color.ui[2] || state->border_color.ui[3]) &&
2696 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
2697 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
2698 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
2699 }
2700
2701 static void *si_create_sampler_state(struct pipe_context *ctx,
2702 const struct pipe_sampler_state *state)
2703 {
2704 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
2705 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
2706 unsigned border_color_type;
2707
2708 if (rstate == NULL) {
2709 return NULL;
2710 }
2711
2712 if (sampler_state_needs_border_color(state))
2713 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
2714 else
2715 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
2716
2717 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
2718 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
2719 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
2720 r600_tex_aniso_filter(state->max_anisotropy) << 9 |
2721 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
2722 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
2723 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map));
2724 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
2725 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
2726 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
2727 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
2728 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter) | aniso_flag_offset) |
2729 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)));
2730 rstate->val[3] = S_008F3C_BORDER_COLOR_TYPE(border_color_type);
2731
2732 if (border_color_type == V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2733 memcpy(rstate->border_color, state->border_color.ui,
2734 sizeof(rstate->border_color));
2735 }
2736
2737 return rstate;
2738 }
2739
2740 /* Upload border colors and update the pointers in resource descriptors.
2741 * There can only be 4096 border colors per context.
2742 *
2743 * XXX: This is broken if the buffer gets reallocated.
2744 */
2745 static void si_set_border_colors(struct si_context *sctx, unsigned count,
2746 void **states)
2747 {
2748 struct si_sampler_state **rstates = (struct si_sampler_state **)states;
2749 uint32_t *border_color_table = NULL;
2750 int i, j;
2751
2752 for (i = 0; i < count; i++) {
2753 if (rstates[i] &&
2754 G_008F3C_BORDER_COLOR_TYPE(rstates[i]->val[3]) ==
2755 V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2756 if (!sctx->border_color_table ||
2757 ((sctx->border_color_offset + count - i) &
2758 C_008F3C_BORDER_COLOR_PTR)) {
2759 r600_resource_reference(&sctx->border_color_table, NULL);
2760 sctx->border_color_offset = 0;
2761
2762 sctx->border_color_table =
2763 si_resource_create_custom(&sctx->screen->b.b,
2764 PIPE_USAGE_DYNAMIC,
2765 4096 * 4 * 4);
2766 }
2767
2768 if (!border_color_table) {
2769 border_color_table =
2770 sctx->b.ws->buffer_map(sctx->border_color_table->cs_buf,
2771 sctx->b.rings.gfx.cs,
2772 PIPE_TRANSFER_WRITE |
2773 PIPE_TRANSFER_UNSYNCHRONIZED);
2774 }
2775
2776 for (j = 0; j < 4; j++) {
2777 border_color_table[4 * sctx->border_color_offset + j] =
2778 util_le32_to_cpu(rstates[i]->border_color[j]);
2779 }
2780
2781 rstates[i]->val[3] &= C_008F3C_BORDER_COLOR_PTR;
2782 rstates[i]->val[3] |= S_008F3C_BORDER_COLOR_PTR(sctx->border_color_offset++);
2783 }
2784 }
2785
2786 if (border_color_table) {
2787 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
2788
2789 uint64_t va_offset = sctx->border_color_table->gpu_address;
2790
2791 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, va_offset >> 8);
2792 if (sctx->b.chip_class >= CIK)
2793 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, va_offset >> 40);
2794 si_pm4_add_bo(pm4, sctx->border_color_table, RADEON_USAGE_READ,
2795 RADEON_PRIO_SHADER_DATA);
2796 si_pm4_set_state(sctx, ta_bordercolor_base, pm4);
2797 }
2798 }
2799
2800 static void si_bind_sampler_states(struct pipe_context *ctx, unsigned shader,
2801 unsigned start, unsigned count,
2802 void **states)
2803 {
2804 struct si_context *sctx = (struct si_context *)ctx;
2805
2806 if (!count || shader >= SI_NUM_SHADERS)
2807 return;
2808
2809 si_set_border_colors(sctx, count, states);
2810 si_set_sampler_descriptors(sctx, shader, start, count, states);
2811 }
2812
2813 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
2814 {
2815 struct si_context *sctx = (struct si_context *)ctx;
2816
2817 if (sctx->sample_mask.sample_mask == (uint16_t)sample_mask)
2818 return;
2819
2820 sctx->sample_mask.sample_mask = sample_mask;
2821 si_mark_atom_dirty(sctx, &sctx->sample_mask.atom);
2822 }
2823
2824 static void si_emit_sample_mask(struct si_context *sctx, struct r600_atom *atom)
2825 {
2826 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
2827 unsigned mask = sctx->sample_mask.sample_mask;
2828
2829 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
2830 radeon_emit(cs, mask | (mask << 16));
2831 radeon_emit(cs, mask | (mask << 16));
2832 }
2833
2834 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
2835 {
2836 free(state);
2837 }
2838
2839 /*
2840 * Vertex elements & buffers
2841 */
2842
2843 static void *si_create_vertex_elements(struct pipe_context *ctx,
2844 unsigned count,
2845 const struct pipe_vertex_element *elements)
2846 {
2847 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
2848 int i;
2849
2850 assert(count < SI_MAX_ATTRIBS);
2851 if (!v)
2852 return NULL;
2853
2854 v->count = count;
2855 for (i = 0; i < count; ++i) {
2856 const struct util_format_description *desc;
2857 unsigned data_format, num_format;
2858 int first_non_void;
2859
2860 desc = util_format_description(elements[i].src_format);
2861 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
2862 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
2863 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
2864
2865 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2866 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2867 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2868 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2869 S_008F0C_NUM_FORMAT(num_format) |
2870 S_008F0C_DATA_FORMAT(data_format);
2871 v->format_size[i] = desc->block.bits / 8;
2872 }
2873 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
2874
2875 return v;
2876 }
2877
2878 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
2879 {
2880 struct si_context *sctx = (struct si_context *)ctx;
2881 struct si_vertex_element *v = (struct si_vertex_element*)state;
2882
2883 sctx->vertex_elements = v;
2884 sctx->vertex_buffers_dirty = true;
2885 }
2886
2887 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
2888 {
2889 struct si_context *sctx = (struct si_context *)ctx;
2890
2891 if (sctx->vertex_elements == state)
2892 sctx->vertex_elements = NULL;
2893 FREE(state);
2894 }
2895
2896 static void si_set_vertex_buffers(struct pipe_context *ctx,
2897 unsigned start_slot, unsigned count,
2898 const struct pipe_vertex_buffer *buffers)
2899 {
2900 struct si_context *sctx = (struct si_context *)ctx;
2901 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
2902 int i;
2903
2904 assert(start_slot + count <= Elements(sctx->vertex_buffer));
2905
2906 if (buffers) {
2907 for (i = 0; i < count; i++) {
2908 const struct pipe_vertex_buffer *src = buffers + i;
2909 struct pipe_vertex_buffer *dsti = dst + i;
2910
2911 pipe_resource_reference(&dsti->buffer, src->buffer);
2912 dsti->buffer_offset = src->buffer_offset;
2913 dsti->stride = src->stride;
2914 r600_context_add_resource_size(ctx, src->buffer);
2915 }
2916 } else {
2917 for (i = 0; i < count; i++) {
2918 pipe_resource_reference(&dst[i].buffer, NULL);
2919 }
2920 }
2921 sctx->vertex_buffers_dirty = true;
2922 }
2923
2924 static void si_set_index_buffer(struct pipe_context *ctx,
2925 const struct pipe_index_buffer *ib)
2926 {
2927 struct si_context *sctx = (struct si_context *)ctx;
2928
2929 if (ib) {
2930 pipe_resource_reference(&sctx->index_buffer.buffer, ib->buffer);
2931 memcpy(&sctx->index_buffer, ib, sizeof(*ib));
2932 r600_context_add_resource_size(ctx, ib->buffer);
2933 } else {
2934 pipe_resource_reference(&sctx->index_buffer.buffer, NULL);
2935 }
2936 }
2937
2938 /*
2939 * Misc
2940 */
2941 static void si_set_polygon_stipple(struct pipe_context *ctx,
2942 const struct pipe_poly_stipple *state)
2943 {
2944 struct si_context *sctx = (struct si_context *)ctx;
2945 struct pipe_resource *tex;
2946 struct pipe_sampler_view *view;
2947 bool is_zero = true;
2948 bool is_one = true;
2949 int i;
2950
2951 /* The hardware obeys 0 and 1 swizzles in the descriptor even if
2952 * the resource is NULL/invalid. Take advantage of this fact and skip
2953 * texture allocation if the stipple pattern is constant.
2954 *
2955 * This is an optimization for the common case when stippling isn't
2956 * used but set_polygon_stipple is still called by st/mesa.
2957 */
2958 for (i = 0; i < Elements(state->stipple); i++) {
2959 is_zero = is_zero && state->stipple[i] == 0;
2960 is_one = is_one && state->stipple[i] == 0xffffffff;
2961 }
2962
2963 if (is_zero || is_one) {
2964 struct pipe_sampler_view templ = {{0}};
2965
2966 templ.swizzle_r = PIPE_SWIZZLE_ZERO;
2967 templ.swizzle_g = PIPE_SWIZZLE_ZERO;
2968 templ.swizzle_b = PIPE_SWIZZLE_ZERO;
2969 /* The pattern should be inverted in the texture. */
2970 templ.swizzle_a = is_zero ? PIPE_SWIZZLE_ONE : PIPE_SWIZZLE_ZERO;
2971
2972 view = ctx->create_sampler_view(ctx, NULL, &templ);
2973 } else {
2974 /* Create a new texture. */
2975 tex = util_pstipple_create_stipple_texture(ctx, state->stipple);
2976 if (!tex)
2977 return;
2978
2979 view = util_pstipple_create_sampler_view(ctx, tex);
2980 pipe_resource_reference(&tex, NULL);
2981 }
2982
2983 ctx->set_sampler_views(ctx, PIPE_SHADER_FRAGMENT,
2984 SI_POLY_STIPPLE_SAMPLER, 1, &view);
2985 pipe_sampler_view_reference(&view, NULL);
2986
2987 /* Bind the sampler state if needed. */
2988 if (!sctx->pstipple_sampler_state) {
2989 sctx->pstipple_sampler_state = util_pstipple_create_sampler(ctx);
2990 ctx->bind_sampler_states(ctx, PIPE_SHADER_FRAGMENT,
2991 SI_POLY_STIPPLE_SAMPLER, 1,
2992 &sctx->pstipple_sampler_state);
2993 }
2994 }
2995
2996 static void si_set_tess_state(struct pipe_context *ctx,
2997 const float default_outer_level[4],
2998 const float default_inner_level[2])
2999 {
3000 struct si_context *sctx = (struct si_context *)ctx;
3001 struct pipe_constant_buffer cb;
3002 float array[8];
3003
3004 memcpy(array, default_outer_level, sizeof(float) * 4);
3005 memcpy(array+4, default_inner_level, sizeof(float) * 2);
3006
3007 cb.buffer = NULL;
3008 cb.user_buffer = NULL;
3009 cb.buffer_size = sizeof(array);
3010
3011 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
3012 (void*)array, sizeof(array),
3013 &cb.buffer_offset);
3014
3015 ctx->set_constant_buffer(ctx, PIPE_SHADER_TESS_CTRL,
3016 SI_DRIVER_STATE_CONST_BUF, &cb);
3017 pipe_resource_reference(&cb.buffer, NULL);
3018 }
3019
3020 static void si_texture_barrier(struct pipe_context *ctx)
3021 {
3022 struct si_context *sctx = (struct si_context *)ctx;
3023
3024 sctx->b.flags |= SI_CONTEXT_INV_TC_L1 |
3025 SI_CONTEXT_INV_TC_L2 |
3026 SI_CONTEXT_FLUSH_AND_INV_CB;
3027 }
3028
3029 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
3030 {
3031 struct pipe_blend_state blend;
3032
3033 memset(&blend, 0, sizeof(blend));
3034 blend.independent_blend_enable = true;
3035 blend.rt[0].colormask = 0xf;
3036 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
3037 }
3038
3039 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
3040 bool include_draw_vbo)
3041 {
3042 si_need_cs_space((struct si_context*)ctx, num_dw, include_draw_vbo);
3043 }
3044
3045 static void si_init_config(struct si_context *sctx);
3046
3047 void si_init_state_functions(struct si_context *sctx)
3048 {
3049 si_init_external_atom(sctx, &sctx->b.streamout.begin_atom, &sctx->atoms.s.streamout_begin);
3050 si_init_external_atom(sctx, &sctx->b.streamout.enable_atom, &sctx->atoms.s.streamout_enable);
3051
3052 si_init_atom(sctx, &sctx->cache_flush, &sctx->atoms.s.cache_flush, si_emit_cache_flush);
3053 si_init_atom(sctx, &sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state);
3054 si_init_atom(sctx, &sctx->msaa_sample_locs, &sctx->atoms.s.msaa_sample_locs, si_emit_msaa_sample_locs);
3055 si_init_atom(sctx, &sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state);
3056 si_init_atom(sctx, &sctx->msaa_config, &sctx->atoms.s.msaa_config, si_emit_msaa_config);
3057 si_init_atom(sctx, &sctx->sample_mask.atom, &sctx->atoms.s.sample_mask, si_emit_sample_mask);
3058 si_init_atom(sctx, &sctx->cb_target_mask, &sctx->atoms.s.cb_target_mask, si_emit_cb_target_mask);
3059 si_init_atom(sctx, &sctx->blend_color.atom, &sctx->atoms.s.blend_color, si_emit_blend_color);
3060 si_init_atom(sctx, &sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs);
3061 si_init_atom(sctx, &sctx->clip_state.atom, &sctx->atoms.s.clip_state, si_emit_clip_state);
3062 si_init_atom(sctx, &sctx->scissors.atom, &sctx->atoms.s.scissors, si_emit_scissors);
3063 si_init_atom(sctx, &sctx->viewports.atom, &sctx->atoms.s.viewports, si_emit_viewports);
3064 si_init_atom(sctx, &sctx->stencil_ref.atom, &sctx->atoms.s.stencil_ref, si_emit_stencil_ref);
3065
3066 sctx->b.b.create_blend_state = si_create_blend_state;
3067 sctx->b.b.bind_blend_state = si_bind_blend_state;
3068 sctx->b.b.delete_blend_state = si_delete_blend_state;
3069 sctx->b.b.set_blend_color = si_set_blend_color;
3070
3071 sctx->b.b.create_rasterizer_state = si_create_rs_state;
3072 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
3073 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
3074
3075 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
3076 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
3077 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
3078
3079 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
3080 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
3081 sctx->custom_blend_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
3082 sctx->custom_blend_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
3083
3084 sctx->b.b.set_clip_state = si_set_clip_state;
3085 sctx->b.b.set_scissor_states = si_set_scissor_states;
3086 sctx->b.b.set_viewport_states = si_set_viewport_states;
3087 sctx->b.b.set_stencil_ref = si_set_stencil_ref;
3088
3089 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
3090 sctx->b.b.get_sample_position = cayman_get_sample_position;
3091
3092 sctx->b.b.create_sampler_state = si_create_sampler_state;
3093 sctx->b.b.bind_sampler_states = si_bind_sampler_states;
3094 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
3095
3096 sctx->b.b.create_sampler_view = si_create_sampler_view;
3097 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
3098
3099 sctx->b.b.set_sample_mask = si_set_sample_mask;
3100
3101 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
3102 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
3103 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
3104 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
3105 sctx->b.b.set_index_buffer = si_set_index_buffer;
3106
3107 sctx->b.b.texture_barrier = si_texture_barrier;
3108 sctx->b.b.set_polygon_stipple = si_set_polygon_stipple;
3109 sctx->b.b.set_min_samples = si_set_min_samples;
3110 sctx->b.b.set_tess_state = si_set_tess_state;
3111
3112 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
3113 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
3114
3115 sctx->b.b.draw_vbo = si_draw_vbo;
3116
3117 if (sctx->b.chip_class >= CIK) {
3118 sctx->b.dma_copy = cik_sdma_copy;
3119 } else {
3120 sctx->b.dma_copy = si_dma_copy;
3121 }
3122
3123 si_init_config(sctx);
3124 }
3125
3126 static void
3127 si_write_harvested_raster_configs(struct si_context *sctx,
3128 struct si_pm4_state *pm4,
3129 unsigned raster_config,
3130 unsigned raster_config_1)
3131 {
3132 unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1);
3133 unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1);
3134 unsigned rb_mask = sctx->screen->b.info.si_backend_enabled_mask;
3135 unsigned num_rb = MIN2(sctx->screen->b.info.r600_num_backends, 16);
3136 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
3137 unsigned rb_per_se = num_rb / num_se;
3138 unsigned se_mask[4];
3139 unsigned se;
3140
3141 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
3142 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
3143 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
3144 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
3145
3146 assert(num_se == 1 || num_se == 2 || num_se == 4);
3147 assert(sh_per_se == 1 || sh_per_se == 2);
3148 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
3149
3150 /* XXX: I can't figure out what the *_XSEL and *_YSEL
3151 * fields are for, so I'm leaving them as their default
3152 * values. */
3153
3154 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
3155 (!se_mask[2] && !se_mask[3]))) {
3156 raster_config_1 &= C_028354_SE_PAIR_MAP;
3157
3158 if (!se_mask[0] && !se_mask[1]) {
3159 raster_config_1 |=
3160 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
3161 } else {
3162 raster_config_1 |=
3163 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
3164 }
3165 }
3166
3167 for (se = 0; se < num_se; se++) {
3168 unsigned raster_config_se = raster_config;
3169 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
3170 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
3171 int idx = (se / 2) * 2;
3172
3173 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
3174 raster_config_se &= C_028350_SE_MAP;
3175
3176 if (!se_mask[idx]) {
3177 raster_config_se |=
3178 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
3179 } else {
3180 raster_config_se |=
3181 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
3182 }
3183 }
3184
3185 pkr0_mask &= rb_mask;
3186 pkr1_mask &= rb_mask;
3187 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
3188 raster_config_se &= C_028350_PKR_MAP;
3189
3190 if (!pkr0_mask) {
3191 raster_config_se |=
3192 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
3193 } else {
3194 raster_config_se |=
3195 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
3196 }
3197 }
3198
3199 if (rb_per_se >= 2) {
3200 unsigned rb0_mask = 1 << (se * rb_per_se);
3201 unsigned rb1_mask = rb0_mask << 1;
3202
3203 rb0_mask &= rb_mask;
3204 rb1_mask &= rb_mask;
3205 if (!rb0_mask || !rb1_mask) {
3206 raster_config_se &= C_028350_RB_MAP_PKR0;
3207
3208 if (!rb0_mask) {
3209 raster_config_se |=
3210 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
3211 } else {
3212 raster_config_se |=
3213 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
3214 }
3215 }
3216
3217 if (rb_per_se > 2) {
3218 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
3219 rb1_mask = rb0_mask << 1;
3220 rb0_mask &= rb_mask;
3221 rb1_mask &= rb_mask;
3222 if (!rb0_mask || !rb1_mask) {
3223 raster_config_se &= C_028350_RB_MAP_PKR1;
3224
3225 if (!rb0_mask) {
3226 raster_config_se |=
3227 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
3228 } else {
3229 raster_config_se |=
3230 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
3231 }
3232 }
3233 }
3234 }
3235
3236 /* GRBM_GFX_INDEX is privileged on VI */
3237 if (sctx->b.chip_class <= CIK)
3238 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3239 SE_INDEX(se) | SH_BROADCAST_WRITES |
3240 INSTANCE_BROADCAST_WRITES);
3241 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
3242 if (sctx->b.chip_class >= CIK)
3243 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
3244 }
3245
3246 /* GRBM_GFX_INDEX is privileged on VI */
3247 if (sctx->b.chip_class <= CIK)
3248 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3249 SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
3250 INSTANCE_BROADCAST_WRITES);
3251 }
3252
3253 static void si_init_config(struct si_context *sctx)
3254 {
3255 unsigned num_rb = MIN2(sctx->screen->b.info.r600_num_backends, 16);
3256 unsigned rb_mask = sctx->screen->b.info.si_backend_enabled_mask;
3257 unsigned raster_config, raster_config_1;
3258 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3259 int i;
3260
3261 if (pm4 == NULL)
3262 return;
3263
3264 si_cmd_context_control(pm4);
3265
3266 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
3267 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
3268
3269 /* FIXME calculate these values somehow ??? */
3270 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, 0x80);
3271 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
3272 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
3273
3274 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
3275 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3276
3277 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
3278 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0);
3279 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
3280 if (sctx->b.chip_class < CIK)
3281 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
3282 S_008A14_CLIP_VTX_REORDER_ENA(1));
3283
3284 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
3285 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
3286
3287 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
3288
3289 for (i = 0; i < 16; i++) {
3290 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0);
3291 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0));
3292 }
3293
3294 switch (sctx->screen->b.family) {
3295 case CHIP_TAHITI:
3296 case CHIP_PITCAIRN:
3297 raster_config = 0x2a00126a;
3298 raster_config_1 = 0x00000000;
3299 break;
3300 case CHIP_VERDE:
3301 raster_config = 0x0000124a;
3302 raster_config_1 = 0x00000000;
3303 break;
3304 case CHIP_OLAND:
3305 raster_config = 0x00000082;
3306 raster_config_1 = 0x00000000;
3307 break;
3308 case CHIP_HAINAN:
3309 raster_config = 0x00000000;
3310 raster_config_1 = 0x00000000;
3311 break;
3312 case CHIP_BONAIRE:
3313 raster_config = 0x16000012;
3314 raster_config_1 = 0x00000000;
3315 break;
3316 case CHIP_HAWAII:
3317 raster_config = 0x3a00161a;
3318 raster_config_1 = 0x0000002e;
3319 break;
3320 case CHIP_FIJI:
3321 /* Fiji should be same as Hawaii, but that causes corruption in some cases */
3322 raster_config = 0x16000012; /* 0x3a00161a */
3323 raster_config_1 = 0x0000002a; /* 0x0000002e */
3324 break;
3325 case CHIP_TONGA:
3326 raster_config = 0x16000012;
3327 raster_config_1 = 0x0000002a;
3328 break;
3329 case CHIP_ICELAND:
3330 raster_config = 0x00000002;
3331 raster_config_1 = 0x00000000;
3332 break;
3333 case CHIP_CARRIZO:
3334 raster_config = 0x00000002;
3335 raster_config_1 = 0x00000000;
3336 break;
3337 case CHIP_KAVERI:
3338 /* KV should be 0x00000002, but that causes problems with radeon */
3339 raster_config = 0x00000000; /* 0x00000002 */
3340 raster_config_1 = 0x00000000;
3341 break;
3342 case CHIP_KABINI:
3343 case CHIP_MULLINS:
3344 raster_config = 0x00000000;
3345 raster_config_1 = 0x00000000;
3346 break;
3347 default:
3348 fprintf(stderr,
3349 "radeonsi: Unknown GPU, using 0 for raster_config\n");
3350 raster_config = 0x00000000;
3351 raster_config_1 = 0x00000000;
3352 break;
3353 }
3354
3355 /* Always use the default config when all backends are enabled
3356 * (or when we failed to determine the enabled backends).
3357 */
3358 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
3359 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
3360 raster_config);
3361 if (sctx->b.chip_class >= CIK)
3362 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
3363 raster_config_1);
3364 } else {
3365 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
3366 }
3367
3368 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
3369 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
3370 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
3371 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
3372 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
3373 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
3374 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
3375
3376 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
3377 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
3378 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
3379 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
3380 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
3381 si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, fui(1.0));
3382 si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, fui(1.0));
3383 si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, fui(1.0));
3384 si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, fui(1.0));
3385 si_pm4_set_reg(pm4, R_028028_DB_STENCIL_CLEAR, 0);
3386 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
3387 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
3388 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
3389
3390 /* There is a hang if stencil is used and fast stencil is enabled
3391 * regardless of whether HTILE is depth-only or not.
3392 */
3393 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE,
3394 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3395 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE) |
3396 S_02800C_FAST_STENCIL_DISABLE(1));
3397
3398 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
3399 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
3400 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
3401
3402 if (sctx->b.chip_class >= CIK) {
3403 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xfffc));
3404 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
3405 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xfffe));
3406 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
3407 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
3408 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(0));
3409 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
3410 }
3411
3412 if (sctx->b.chip_class >= VI) {
3413 si_pm4_set_reg(pm4, R_028424_CB_DCC_CONTROL,
3414 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1));
3415 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
3416 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
3417 }
3418
3419 sctx->init_config = pm4;
3420 }