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vc4: Try to schedule QIR instructions between writing to and reading math.
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "sid.h"
29 #include "radeon/r600_cs.h"
30 #include "radeon/r600_query.h"
31
32 #include "util/u_dual_blend.h"
33 #include "util/u_format.h"
34 #include "util/u_format_s3tc.h"
35 #include "util/u_memory.h"
36 #include "util/u_resource.h"
37
38 /* Initialize an external atom (owned by ../radeon). */
39 static void
40 si_init_external_atom(struct si_context *sctx, struct r600_atom *atom,
41 struct r600_atom **list_elem)
42 {
43 atom->id = list_elem - sctx->atoms.array + 1;
44 *list_elem = atom;
45 }
46
47 /* Initialize an atom owned by radeonsi. */
48 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
49 struct r600_atom **list_elem,
50 void (*emit_func)(struct si_context *ctx, struct r600_atom *state))
51 {
52 atom->emit = (void*)emit_func;
53 atom->id = list_elem - sctx->atoms.array + 1; /* index+1 in the atom array */
54 *list_elem = atom;
55 }
56
57 static unsigned si_map_swizzle(unsigned swizzle)
58 {
59 switch (swizzle) {
60 case PIPE_SWIZZLE_Y:
61 return V_008F0C_SQ_SEL_Y;
62 case PIPE_SWIZZLE_Z:
63 return V_008F0C_SQ_SEL_Z;
64 case PIPE_SWIZZLE_W:
65 return V_008F0C_SQ_SEL_W;
66 case PIPE_SWIZZLE_0:
67 return V_008F0C_SQ_SEL_0;
68 case PIPE_SWIZZLE_1:
69 return V_008F0C_SQ_SEL_1;
70 default: /* PIPE_SWIZZLE_X */
71 return V_008F0C_SQ_SEL_X;
72 }
73 }
74
75 static uint32_t S_FIXED(float value, uint32_t frac_bits)
76 {
77 return value * (1 << frac_bits);
78 }
79
80 /* 12.4 fixed-point */
81 static unsigned si_pack_float_12p4(float x)
82 {
83 return x <= 0 ? 0 :
84 x >= 4096 ? 0xffff : x * 16;
85 }
86
87 /*
88 * Inferred framebuffer and blender state.
89 *
90 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
91 * if there is not enough PS outputs.
92 */
93 static void si_emit_cb_render_state(struct si_context *sctx, struct r600_atom *atom)
94 {
95 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
96 struct si_state_blend *blend = sctx->queued.named.blend;
97 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
98 * but you never know. */
99 uint32_t cb_target_mask = sctx->framebuffer.colorbuf_enabled_4bit;
100 unsigned i;
101
102 if (blend)
103 cb_target_mask &= blend->cb_target_mask;
104
105 /* Avoid a hang that happens when dual source blending is enabled
106 * but there is not enough color outputs. This is undefined behavior,
107 * so disable color writes completely.
108 *
109 * Reproducible with Unigine Heaven 4.0 and drirc missing.
110 */
111 if (blend && blend->dual_src_blend &&
112 sctx->ps_shader.cso &&
113 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
114 cb_target_mask = 0;
115
116 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, cb_target_mask);
117
118 /* STONEY-specific register settings. */
119 if (sctx->b.family == CHIP_STONEY) {
120 unsigned spi_shader_col_format =
121 sctx->ps_shader.cso ?
122 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format : 0;
123 unsigned sx_ps_downconvert = 0;
124 unsigned sx_blend_opt_epsilon = 0;
125 unsigned sx_blend_opt_control = 0;
126
127 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
128 struct r600_surface *surf =
129 (struct r600_surface*)sctx->framebuffer.state.cbufs[i];
130 unsigned format, swap, spi_format, colormask;
131 bool has_alpha, has_rgb;
132
133 if (!surf)
134 continue;
135
136 format = G_028C70_FORMAT(surf->cb_color_info);
137 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
138 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
139 colormask = (cb_target_mask >> (i * 4)) & 0xf;
140
141 /* Set if RGB and A are present. */
142 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
143
144 if (format == V_028C70_COLOR_8 ||
145 format == V_028C70_COLOR_16 ||
146 format == V_028C70_COLOR_32)
147 has_rgb = !has_alpha;
148 else
149 has_rgb = true;
150
151 /* Check the colormask and export format. */
152 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
153 has_rgb = false;
154 if (!(colormask & PIPE_MASK_A))
155 has_alpha = false;
156
157 if (spi_format == V_028714_SPI_SHADER_ZERO) {
158 has_rgb = false;
159 has_alpha = false;
160 }
161
162 /* Disable value checking for disabled channels. */
163 if (!has_rgb)
164 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
165 if (!has_alpha)
166 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
167
168 /* Enable down-conversion for 32bpp and smaller formats. */
169 switch (format) {
170 case V_028C70_COLOR_8:
171 case V_028C70_COLOR_8_8:
172 case V_028C70_COLOR_8_8_8_8:
173 /* For 1 and 2-channel formats, use the superset thereof. */
174 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
175 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
176 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
177 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
178 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
179 }
180 break;
181
182 case V_028C70_COLOR_5_6_5:
183 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
184 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
185 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
186 }
187 break;
188
189 case V_028C70_COLOR_1_5_5_5:
190 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
191 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
192 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
193 }
194 break;
195
196 case V_028C70_COLOR_4_4_4_4:
197 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
198 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
199 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
200 }
201 break;
202
203 case V_028C70_COLOR_32:
204 if (swap == V_0280A0_SWAP_STD &&
205 spi_format == V_028714_SPI_SHADER_32_R)
206 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
207 else if (swap == V_0280A0_SWAP_ALT_REV &&
208 spi_format == V_028714_SPI_SHADER_32_AR)
209 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
210 break;
211
212 case V_028C70_COLOR_16:
213 case V_028C70_COLOR_16_16:
214 /* For 1-channel formats, use the superset thereof. */
215 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
216 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
217 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
218 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
219 if (swap == V_0280A0_SWAP_STD ||
220 swap == V_0280A0_SWAP_STD_REV)
221 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
222 else
223 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
224 }
225 break;
226
227 case V_028C70_COLOR_10_11_11:
228 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
229 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
230 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
231 }
232 break;
233
234 case V_028C70_COLOR_2_10_10_10:
235 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
236 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
237 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
238 }
239 break;
240 }
241 }
242
243 if (sctx->screen->b.debug_flags & DBG_NO_RB_PLUS) {
244 sx_ps_downconvert = 0;
245 sx_blend_opt_epsilon = 0;
246 sx_blend_opt_control = 0;
247 }
248
249 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
250 radeon_emit(cs, sx_ps_downconvert); /* R_028754_SX_PS_DOWNCONVERT */
251 radeon_emit(cs, sx_blend_opt_epsilon); /* R_028758_SX_BLEND_OPT_EPSILON */
252 radeon_emit(cs, sx_blend_opt_control); /* R_02875C_SX_BLEND_OPT_CONTROL */
253 }
254 }
255
256 /*
257 * Blender functions
258 */
259
260 static uint32_t si_translate_blend_function(int blend_func)
261 {
262 switch (blend_func) {
263 case PIPE_BLEND_ADD:
264 return V_028780_COMB_DST_PLUS_SRC;
265 case PIPE_BLEND_SUBTRACT:
266 return V_028780_COMB_SRC_MINUS_DST;
267 case PIPE_BLEND_REVERSE_SUBTRACT:
268 return V_028780_COMB_DST_MINUS_SRC;
269 case PIPE_BLEND_MIN:
270 return V_028780_COMB_MIN_DST_SRC;
271 case PIPE_BLEND_MAX:
272 return V_028780_COMB_MAX_DST_SRC;
273 default:
274 R600_ERR("Unknown blend function %d\n", blend_func);
275 assert(0);
276 break;
277 }
278 return 0;
279 }
280
281 static uint32_t si_translate_blend_factor(int blend_fact)
282 {
283 switch (blend_fact) {
284 case PIPE_BLENDFACTOR_ONE:
285 return V_028780_BLEND_ONE;
286 case PIPE_BLENDFACTOR_SRC_COLOR:
287 return V_028780_BLEND_SRC_COLOR;
288 case PIPE_BLENDFACTOR_SRC_ALPHA:
289 return V_028780_BLEND_SRC_ALPHA;
290 case PIPE_BLENDFACTOR_DST_ALPHA:
291 return V_028780_BLEND_DST_ALPHA;
292 case PIPE_BLENDFACTOR_DST_COLOR:
293 return V_028780_BLEND_DST_COLOR;
294 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
295 return V_028780_BLEND_SRC_ALPHA_SATURATE;
296 case PIPE_BLENDFACTOR_CONST_COLOR:
297 return V_028780_BLEND_CONSTANT_COLOR;
298 case PIPE_BLENDFACTOR_CONST_ALPHA:
299 return V_028780_BLEND_CONSTANT_ALPHA;
300 case PIPE_BLENDFACTOR_ZERO:
301 return V_028780_BLEND_ZERO;
302 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
303 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
304 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
305 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
306 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
307 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
308 case PIPE_BLENDFACTOR_INV_DST_COLOR:
309 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
310 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
311 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
312 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
313 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
314 case PIPE_BLENDFACTOR_SRC1_COLOR:
315 return V_028780_BLEND_SRC1_COLOR;
316 case PIPE_BLENDFACTOR_SRC1_ALPHA:
317 return V_028780_BLEND_SRC1_ALPHA;
318 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
319 return V_028780_BLEND_INV_SRC1_COLOR;
320 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
321 return V_028780_BLEND_INV_SRC1_ALPHA;
322 default:
323 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
324 assert(0);
325 break;
326 }
327 return 0;
328 }
329
330 static uint32_t si_translate_blend_opt_function(int blend_func)
331 {
332 switch (blend_func) {
333 case PIPE_BLEND_ADD:
334 return V_028760_OPT_COMB_ADD;
335 case PIPE_BLEND_SUBTRACT:
336 return V_028760_OPT_COMB_SUBTRACT;
337 case PIPE_BLEND_REVERSE_SUBTRACT:
338 return V_028760_OPT_COMB_REVSUBTRACT;
339 case PIPE_BLEND_MIN:
340 return V_028760_OPT_COMB_MIN;
341 case PIPE_BLEND_MAX:
342 return V_028760_OPT_COMB_MAX;
343 default:
344 return V_028760_OPT_COMB_BLEND_DISABLED;
345 }
346 }
347
348 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
349 {
350 switch (blend_fact) {
351 case PIPE_BLENDFACTOR_ZERO:
352 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
353 case PIPE_BLENDFACTOR_ONE:
354 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
355 case PIPE_BLENDFACTOR_SRC_COLOR:
356 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
357 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
358 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
359 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
360 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
361 case PIPE_BLENDFACTOR_SRC_ALPHA:
362 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
363 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
364 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
365 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
366 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
367 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
368 default:
369 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
370 }
371 }
372
373 /**
374 * Get rid of DST in the blend factors by commuting the operands:
375 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
376 */
377 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
378 unsigned *dst_factor, unsigned expected_dst,
379 unsigned replacement_src)
380 {
381 if (*src_factor == expected_dst &&
382 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
383 *src_factor = PIPE_BLENDFACTOR_ZERO;
384 *dst_factor = replacement_src;
385
386 /* Commuting the operands requires reversing subtractions. */
387 if (*func == PIPE_BLEND_SUBTRACT)
388 *func = PIPE_BLEND_REVERSE_SUBTRACT;
389 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
390 *func = PIPE_BLEND_SUBTRACT;
391 }
392 }
393
394 static bool si_blend_factor_uses_dst(unsigned factor)
395 {
396 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
397 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
398 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
399 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
400 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
401 }
402
403 static void *si_create_blend_state_mode(struct pipe_context *ctx,
404 const struct pipe_blend_state *state,
405 unsigned mode)
406 {
407 struct si_context *sctx = (struct si_context*)ctx;
408 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
409 struct si_pm4_state *pm4 = &blend->pm4;
410 uint32_t sx_mrt_blend_opt[8] = {0};
411 uint32_t color_control = 0;
412
413 if (!blend)
414 return NULL;
415
416 blend->alpha_to_coverage = state->alpha_to_coverage;
417 blend->alpha_to_one = state->alpha_to_one;
418 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
419
420 if (state->logicop_enable) {
421 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
422 } else {
423 color_control |= S_028808_ROP3(0xcc);
424 }
425
426 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
427 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
428 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
429 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
430 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
431 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
432
433 if (state->alpha_to_coverage)
434 blend->need_src_alpha_4bit |= 0xf;
435
436 blend->cb_target_mask = 0;
437 for (int i = 0; i < 8; i++) {
438 /* state->rt entries > 0 only written if independent blending */
439 const int j = state->independent_blend_enable ? i : 0;
440
441 unsigned eqRGB = state->rt[j].rgb_func;
442 unsigned srcRGB = state->rt[j].rgb_src_factor;
443 unsigned dstRGB = state->rt[j].rgb_dst_factor;
444 unsigned eqA = state->rt[j].alpha_func;
445 unsigned srcA = state->rt[j].alpha_src_factor;
446 unsigned dstA = state->rt[j].alpha_dst_factor;
447
448 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
449 unsigned blend_cntl = 0;
450
451 sx_mrt_blend_opt[i] =
452 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
453 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
454
455 /* Only set dual source blending for MRT0 to avoid a hang. */
456 if (i >= 1 && blend->dual_src_blend) {
457 /* Vulkan does this for dual source blending. */
458 if (i == 1)
459 blend_cntl |= S_028780_ENABLE(1);
460
461 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
462 continue;
463 }
464
465 /* Only addition and subtraction equations are supported with
466 * dual source blending.
467 */
468 if (blend->dual_src_blend &&
469 (eqRGB == PIPE_BLEND_MIN || eqRGB == PIPE_BLEND_MAX ||
470 eqA == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MAX)) {
471 assert(!"Unsupported equation for dual source blending");
472 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
473 continue;
474 }
475
476 /* cb_render_state will disable unused ones */
477 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
478
479 if (!state->rt[j].colormask || !state->rt[j].blend_enable) {
480 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
481 continue;
482 }
483
484 /* Blending optimizations for Stoney.
485 * These transformations don't change the behavior.
486 *
487 * First, get rid of DST in the blend factors:
488 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
489 */
490 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
491 PIPE_BLENDFACTOR_DST_COLOR,
492 PIPE_BLENDFACTOR_SRC_COLOR);
493 si_blend_remove_dst(&eqA, &srcA, &dstA,
494 PIPE_BLENDFACTOR_DST_COLOR,
495 PIPE_BLENDFACTOR_SRC_COLOR);
496 si_blend_remove_dst(&eqA, &srcA, &dstA,
497 PIPE_BLENDFACTOR_DST_ALPHA,
498 PIPE_BLENDFACTOR_SRC_ALPHA);
499
500 /* Look up the ideal settings from tables. */
501 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
502 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
503 srcA_opt = si_translate_blend_opt_factor(srcA, true);
504 dstA_opt = si_translate_blend_opt_factor(dstA, true);
505
506 /* Handle interdependencies. */
507 if (si_blend_factor_uses_dst(srcRGB))
508 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
509 if (si_blend_factor_uses_dst(srcA))
510 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
511
512 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
513 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
514 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
515 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
516 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
517
518 /* Set the final value. */
519 sx_mrt_blend_opt[i] =
520 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
521 S_028760_COLOR_DST_OPT(dstRGB_opt) |
522 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
523 S_028760_ALPHA_SRC_OPT(srcA_opt) |
524 S_028760_ALPHA_DST_OPT(dstA_opt) |
525 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
526
527 /* Set blend state. */
528 blend_cntl |= S_028780_ENABLE(1);
529 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
530 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
531 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
532
533 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
534 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
535 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
536 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
537 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
538 }
539 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
540
541 blend->blend_enable_4bit |= 0xfu << (i * 4);
542
543 /* This is only important for formats without alpha. */
544 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
545 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
546 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
547 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
548 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
549 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
550 blend->need_src_alpha_4bit |= 0xfu << (i * 4);
551 }
552
553 if (blend->cb_target_mask) {
554 color_control |= S_028808_MODE(mode);
555 } else {
556 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
557 }
558
559 if (sctx->b.family == CHIP_STONEY) {
560 /* Disable RB+ blend optimizations for dual source blending.
561 * Vulkan does this.
562 */
563 if (blend->dual_src_blend) {
564 for (int i = 0; i < 8; i++) {
565 sx_mrt_blend_opt[i] =
566 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
567 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
568 }
569 }
570
571 for (int i = 0; i < 8; i++)
572 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
573 sx_mrt_blend_opt[i]);
574
575 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
576 if (blend->dual_src_blend || state->logicop_enable ||
577 mode == V_028808_CB_RESOLVE)
578 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
579 }
580
581 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
582 return blend;
583 }
584
585 static void *si_create_blend_state(struct pipe_context *ctx,
586 const struct pipe_blend_state *state)
587 {
588 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
589 }
590
591 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
592 {
593 struct si_context *sctx = (struct si_context *)ctx;
594 si_pm4_bind_state(sctx, blend, (struct si_state_blend *)state);
595 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
596 sctx->do_update_shaders = true;
597 }
598
599 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
600 {
601 struct si_context *sctx = (struct si_context *)ctx;
602 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
603 }
604
605 static void si_set_blend_color(struct pipe_context *ctx,
606 const struct pipe_blend_color *state)
607 {
608 struct si_context *sctx = (struct si_context *)ctx;
609
610 if (memcmp(&sctx->blend_color.state, state, sizeof(*state)) == 0)
611 return;
612
613 sctx->blend_color.state = *state;
614 si_mark_atom_dirty(sctx, &sctx->blend_color.atom);
615 }
616
617 static void si_emit_blend_color(struct si_context *sctx, struct r600_atom *atom)
618 {
619 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
620
621 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
622 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
623 }
624
625 /*
626 * Clipping
627 */
628
629 static void si_set_clip_state(struct pipe_context *ctx,
630 const struct pipe_clip_state *state)
631 {
632 struct si_context *sctx = (struct si_context *)ctx;
633 struct pipe_constant_buffer cb;
634
635 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
636 return;
637
638 sctx->clip_state.state = *state;
639 si_mark_atom_dirty(sctx, &sctx->clip_state.atom);
640
641 cb.buffer = NULL;
642 cb.user_buffer = state->ucp;
643 cb.buffer_offset = 0;
644 cb.buffer_size = 4*4*8;
645 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
646 pipe_resource_reference(&cb.buffer, NULL);
647 }
648
649 static void si_emit_clip_state(struct si_context *sctx, struct r600_atom *atom)
650 {
651 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
652
653 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
654 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
655 }
656
657 #define SIX_BITS 0x3F
658
659 static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom)
660 {
661 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
662 struct si_shader *vs = si_get_vs_state(sctx);
663 struct tgsi_shader_info *info = si_get_vs_info(sctx);
664 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
665 unsigned window_space =
666 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
667 unsigned clipdist_mask =
668 info->writes_clipvertex ? SIX_BITS : info->clipdist_writemask;
669 unsigned ucp_mask = clipdist_mask ? 0 : rs->clip_plane_enable & SIX_BITS;
670 unsigned culldist_mask = info->culldist_writemask << info->num_written_clipdistance;
671 unsigned total_mask;
672
673 if (vs->key.opt.hw_vs.clip_disable) {
674 assert(!info->culldist_writemask);
675 clipdist_mask = 0;
676 culldist_mask = 0;
677 }
678 total_mask = clipdist_mask | culldist_mask;
679
680 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
681 S_02881C_USE_VTX_POINT_SIZE(info->writes_psize) |
682 S_02881C_USE_VTX_EDGE_FLAG(info->writes_edgeflag) |
683 S_02881C_USE_VTX_RENDER_TARGET_INDX(info->writes_layer) |
684 S_02881C_USE_VTX_VIEWPORT_INDX(info->writes_viewport_index) |
685 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0F) != 0) |
686 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xF0) != 0) |
687 S_02881C_VS_OUT_MISC_VEC_ENA(info->writes_psize ||
688 info->writes_edgeflag ||
689 info->writes_layer ||
690 info->writes_viewport_index) |
691 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(1) |
692 (rs->clip_plane_enable &
693 clipdist_mask) | (culldist_mask << 8));
694 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
695 rs->pa_cl_clip_cntl |
696 ucp_mask |
697 S_028810_CLIP_DISABLE(window_space));
698
699 /* reuse needs to be set off if we write oViewport */
700 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF,
701 S_028AB4_REUSE_OFF(info->writes_viewport_index));
702 }
703
704 /*
705 * inferred state between framebuffer and rasterizer
706 */
707 static void si_update_poly_offset_state(struct si_context *sctx)
708 {
709 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
710
711 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf)
712 return;
713
714 /* Use the user format, not db_render_format, so that the polygon
715 * offset behaves as expected by applications.
716 */
717 switch (sctx->framebuffer.state.zsbuf->texture->format) {
718 case PIPE_FORMAT_Z16_UNORM:
719 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
720 break;
721 default: /* 24-bit */
722 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
723 break;
724 case PIPE_FORMAT_Z32_FLOAT:
725 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
726 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
727 break;
728 }
729 }
730
731 /*
732 * Rasterizer
733 */
734
735 static uint32_t si_translate_fill(uint32_t func)
736 {
737 switch(func) {
738 case PIPE_POLYGON_MODE_FILL:
739 return V_028814_X_DRAW_TRIANGLES;
740 case PIPE_POLYGON_MODE_LINE:
741 return V_028814_X_DRAW_LINES;
742 case PIPE_POLYGON_MODE_POINT:
743 return V_028814_X_DRAW_POINTS;
744 default:
745 assert(0);
746 return V_028814_X_DRAW_POINTS;
747 }
748 }
749
750 static void *si_create_rs_state(struct pipe_context *ctx,
751 const struct pipe_rasterizer_state *state)
752 {
753 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
754 struct si_pm4_state *pm4 = &rs->pm4;
755 unsigned tmp, i;
756 float psize_min, psize_max;
757
758 if (!rs) {
759 return NULL;
760 }
761
762 rs->scissor_enable = state->scissor;
763 rs->clip_halfz = state->clip_halfz;
764 rs->two_side = state->light_twoside;
765 rs->multisample_enable = state->multisample;
766 rs->force_persample_interp = state->force_persample_interp;
767 rs->clip_plane_enable = state->clip_plane_enable;
768 rs->line_stipple_enable = state->line_stipple_enable;
769 rs->poly_stipple_enable = state->poly_stipple_enable;
770 rs->line_smooth = state->line_smooth;
771 rs->poly_smooth = state->poly_smooth;
772 rs->uses_poly_offset = state->offset_point || state->offset_line ||
773 state->offset_tri;
774 rs->clamp_fragment_color = state->clamp_fragment_color;
775 rs->flatshade = state->flatshade;
776 rs->sprite_coord_enable = state->sprite_coord_enable;
777 rs->rasterizer_discard = state->rasterizer_discard;
778 rs->pa_sc_line_stipple = state->line_stipple_enable ?
779 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
780 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
781 rs->pa_cl_clip_cntl =
782 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
783 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
784 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
785 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
786 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
787
788 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
789 S_0286D4_FLAT_SHADE_ENA(1) |
790 S_0286D4_PNT_SPRITE_ENA(1) |
791 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
792 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
793 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
794 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
795 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
796
797 /* point size 12.4 fixed point */
798 tmp = (unsigned)(state->point_size * 8.0);
799 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
800
801 if (state->point_size_per_vertex) {
802 psize_min = util_get_min_point_size(state);
803 psize_max = 8192;
804 } else {
805 /* Force the point size to be as if the vertex output was disabled. */
806 psize_min = state->point_size;
807 psize_max = state->point_size;
808 }
809 /* Divide by two, because 0.5 = 1 pixel. */
810 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
811 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
812 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
813
814 tmp = (unsigned)state->line_width * 8;
815 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
816 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
817 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
818 S_028A48_MSAA_ENABLE(state->multisample ||
819 state->poly_smooth ||
820 state->line_smooth) |
821 S_028A48_VPORT_SCISSOR_ENABLE(1));
822
823 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
824 S_028BE4_PIX_CENTER(state->half_pixel_center) |
825 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
826
827 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
828 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
829 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
830 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
831 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
832 S_028814_FACE(!state->front_ccw) |
833 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
834 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
835 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
836 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
837 state->fill_back != PIPE_POLYGON_MODE_FILL) |
838 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
839 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
840 si_pm4_set_reg(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0 +
841 SI_SGPR_VS_STATE_BITS * 4, state->clamp_vertex_color);
842
843 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
844 for (i = 0; i < 3; i++) {
845 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
846 float offset_units = state->offset_units;
847 float offset_scale = state->offset_scale * 16.0f;
848 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
849
850 if (!state->offset_units_unscaled) {
851 switch (i) {
852 case 0: /* 16-bit zbuffer */
853 offset_units *= 4.0f;
854 pa_su_poly_offset_db_fmt_cntl =
855 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
856 break;
857 case 1: /* 24-bit zbuffer */
858 offset_units *= 2.0f;
859 pa_su_poly_offset_db_fmt_cntl =
860 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
861 break;
862 case 2: /* 32-bit zbuffer */
863 offset_units *= 1.0f;
864 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
865 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
866 break;
867 }
868 }
869
870 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
871 fui(offset_scale));
872 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
873 fui(offset_units));
874 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
875 fui(offset_scale));
876 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
877 fui(offset_units));
878 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
879 pa_su_poly_offset_db_fmt_cntl);
880 }
881
882 return rs;
883 }
884
885 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
886 {
887 struct si_context *sctx = (struct si_context *)ctx;
888 struct si_state_rasterizer *old_rs =
889 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
890 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
891
892 if (!state)
893 return;
894
895 if (!old_rs || old_rs->multisample_enable != rs->multisample_enable) {
896 si_mark_atom_dirty(sctx, &sctx->db_render_state);
897
898 /* Update the small primitive filter workaround if necessary. */
899 if (sctx->b.family >= CHIP_POLARIS10 &&
900 sctx->framebuffer.nr_samples > 1)
901 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
902 }
903
904 r600_viewport_set_rast_deps(&sctx->b, rs->scissor_enable, rs->clip_halfz);
905
906 si_pm4_bind_state(sctx, rasterizer, rs);
907 si_update_poly_offset_state(sctx);
908
909 si_mark_atom_dirty(sctx, &sctx->clip_regs);
910 sctx->do_update_shaders = true;
911 }
912
913 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
914 {
915 struct si_context *sctx = (struct si_context *)ctx;
916
917 if (sctx->queued.named.rasterizer == state)
918 si_pm4_bind_state(sctx, poly_offset, NULL);
919 si_pm4_delete_state(sctx, rasterizer, (struct si_state_rasterizer *)state);
920 }
921
922 /*
923 * infeered state between dsa and stencil ref
924 */
925 static void si_emit_stencil_ref(struct si_context *sctx, struct r600_atom *atom)
926 {
927 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
928 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
929 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
930
931 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
932 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
933 S_028430_STENCILMASK(dsa->valuemask[0]) |
934 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
935 S_028430_STENCILOPVAL(1));
936 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
937 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
938 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
939 S_028434_STENCILOPVAL_BF(1));
940 }
941
942 static void si_set_stencil_ref(struct pipe_context *ctx,
943 const struct pipe_stencil_ref *state)
944 {
945 struct si_context *sctx = (struct si_context *)ctx;
946
947 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
948 return;
949
950 sctx->stencil_ref.state = *state;
951 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
952 }
953
954
955 /*
956 * DSA
957 */
958
959 static uint32_t si_translate_stencil_op(int s_op)
960 {
961 switch (s_op) {
962 case PIPE_STENCIL_OP_KEEP:
963 return V_02842C_STENCIL_KEEP;
964 case PIPE_STENCIL_OP_ZERO:
965 return V_02842C_STENCIL_ZERO;
966 case PIPE_STENCIL_OP_REPLACE:
967 return V_02842C_STENCIL_REPLACE_TEST;
968 case PIPE_STENCIL_OP_INCR:
969 return V_02842C_STENCIL_ADD_CLAMP;
970 case PIPE_STENCIL_OP_DECR:
971 return V_02842C_STENCIL_SUB_CLAMP;
972 case PIPE_STENCIL_OP_INCR_WRAP:
973 return V_02842C_STENCIL_ADD_WRAP;
974 case PIPE_STENCIL_OP_DECR_WRAP:
975 return V_02842C_STENCIL_SUB_WRAP;
976 case PIPE_STENCIL_OP_INVERT:
977 return V_02842C_STENCIL_INVERT;
978 default:
979 R600_ERR("Unknown stencil op %d", s_op);
980 assert(0);
981 break;
982 }
983 return 0;
984 }
985
986 static void *si_create_dsa_state(struct pipe_context *ctx,
987 const struct pipe_depth_stencil_alpha_state *state)
988 {
989 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
990 struct si_pm4_state *pm4 = &dsa->pm4;
991 unsigned db_depth_control;
992 uint32_t db_stencil_control = 0;
993
994 if (!dsa) {
995 return NULL;
996 }
997
998 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
999 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
1000 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
1001 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
1002
1003 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
1004 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
1005 S_028800_ZFUNC(state->depth.func) |
1006 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
1007
1008 /* stencil */
1009 if (state->stencil[0].enabled) {
1010 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1011 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
1012 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
1013 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
1014 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
1015
1016 if (state->stencil[1].enabled) {
1017 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1018 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1019 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
1020 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
1021 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
1022 }
1023 }
1024
1025 /* alpha */
1026 if (state->alpha.enabled) {
1027 dsa->alpha_func = state->alpha.func;
1028
1029 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1030 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
1031 } else {
1032 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1033 }
1034
1035 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1036 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1037 if (state->depth.bounds_test) {
1038 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1039 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1040 }
1041
1042 return dsa;
1043 }
1044
1045 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1046 {
1047 struct si_context *sctx = (struct si_context *)ctx;
1048 struct si_state_dsa *dsa = state;
1049
1050 if (!state)
1051 return;
1052
1053 si_pm4_bind_state(sctx, dsa, dsa);
1054
1055 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1056 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1057 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1058 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1059 }
1060 sctx->do_update_shaders = true;
1061 }
1062
1063 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1064 {
1065 struct si_context *sctx = (struct si_context *)ctx;
1066 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1067 }
1068
1069 static void *si_create_db_flush_dsa(struct si_context *sctx)
1070 {
1071 struct pipe_depth_stencil_alpha_state dsa = {};
1072
1073 return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
1074 }
1075
1076 /* DB RENDER STATE */
1077
1078 static void si_set_active_query_state(struct pipe_context *ctx, boolean enable)
1079 {
1080 struct si_context *sctx = (struct si_context*)ctx;
1081
1082 /* Pipeline stat & streamout queries. */
1083 if (enable) {
1084 sctx->b.flags &= ~R600_CONTEXT_STOP_PIPELINE_STATS;
1085 sctx->b.flags |= R600_CONTEXT_START_PIPELINE_STATS;
1086 } else {
1087 sctx->b.flags &= ~R600_CONTEXT_START_PIPELINE_STATS;
1088 sctx->b.flags |= R600_CONTEXT_STOP_PIPELINE_STATS;
1089 }
1090
1091 /* Occlusion queries. */
1092 if (sctx->occlusion_queries_disabled != !enable) {
1093 sctx->occlusion_queries_disabled = !enable;
1094 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1095 }
1096 }
1097
1098 static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
1099 {
1100 struct si_context *sctx = (struct si_context*)ctx;
1101
1102 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1103 }
1104
1105 static void si_save_qbo_state(struct pipe_context *ctx, struct r600_qbo_state *st)
1106 {
1107 struct si_context *sctx = (struct si_context*)ctx;
1108
1109 st->saved_compute = sctx->cs_shader_state.program;
1110
1111 si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1112 si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
1113 }
1114
1115 static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
1116 {
1117 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1118 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1119 unsigned db_shader_control;
1120
1121 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1122
1123 /* DB_RENDER_CONTROL */
1124 if (sctx->dbcb_depth_copy_enabled ||
1125 sctx->dbcb_stencil_copy_enabled) {
1126 radeon_emit(cs,
1127 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1128 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1129 S_028000_COPY_CENTROID(1) |
1130 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
1131 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1132 radeon_emit(cs,
1133 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1134 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace));
1135 } else {
1136 radeon_emit(cs,
1137 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1138 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear));
1139 }
1140
1141 /* DB_COUNT_CONTROL (occlusion queries) */
1142 if (sctx->b.num_occlusion_queries > 0 &&
1143 !sctx->occlusion_queries_disabled) {
1144 bool perfect = sctx->b.num_perfect_occlusion_queries > 0;
1145
1146 if (sctx->b.chip_class >= CIK) {
1147 radeon_emit(cs,
1148 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1149 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
1150 S_028004_ZPASS_ENABLE(1) |
1151 S_028004_SLICE_EVEN_ENABLE(1) |
1152 S_028004_SLICE_ODD_ENABLE(1));
1153 } else {
1154 radeon_emit(cs,
1155 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1156 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
1157 }
1158 } else {
1159 /* Disable occlusion queries. */
1160 if (sctx->b.chip_class >= CIK) {
1161 radeon_emit(cs, 0);
1162 } else {
1163 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
1164 }
1165 }
1166
1167 /* DB_RENDER_OVERRIDE2 */
1168 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
1169 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1170 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1171 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4));
1172
1173 db_shader_control = sctx->ps_db_shader_control;
1174
1175 /* Bug workaround for smoothing (overrasterization) on SI. */
1176 if (sctx->b.chip_class == SI && sctx->smoothing_enabled) {
1177 db_shader_control &= C_02880C_Z_ORDER;
1178 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1179 }
1180
1181 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1182 if (!rs || !rs->multisample_enable)
1183 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1184
1185 if (sctx->b.family == CHIP_STONEY &&
1186 sctx->screen->b.debug_flags & DBG_NO_RB_PLUS)
1187 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1188
1189 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
1190 db_shader_control);
1191 }
1192
1193 /*
1194 * format translation
1195 */
1196 static uint32_t si_translate_colorformat(enum pipe_format format)
1197 {
1198 const struct util_format_description *desc = util_format_description(format);
1199
1200 #define HAS_SIZE(x,y,z,w) \
1201 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1202 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1203
1204 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1205 return V_028C70_COLOR_10_11_11;
1206
1207 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1208 return V_028C70_COLOR_INVALID;
1209
1210 /* hw cannot support mixed formats (except depth/stencil, since
1211 * stencil is not written to). */
1212 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1213 return V_028C70_COLOR_INVALID;
1214
1215 switch (desc->nr_channels) {
1216 case 1:
1217 switch (desc->channel[0].size) {
1218 case 8:
1219 return V_028C70_COLOR_8;
1220 case 16:
1221 return V_028C70_COLOR_16;
1222 case 32:
1223 return V_028C70_COLOR_32;
1224 }
1225 break;
1226 case 2:
1227 if (desc->channel[0].size == desc->channel[1].size) {
1228 switch (desc->channel[0].size) {
1229 case 8:
1230 return V_028C70_COLOR_8_8;
1231 case 16:
1232 return V_028C70_COLOR_16_16;
1233 case 32:
1234 return V_028C70_COLOR_32_32;
1235 }
1236 } else if (HAS_SIZE(8,24,0,0)) {
1237 return V_028C70_COLOR_24_8;
1238 } else if (HAS_SIZE(24,8,0,0)) {
1239 return V_028C70_COLOR_8_24;
1240 }
1241 break;
1242 case 3:
1243 if (HAS_SIZE(5,6,5,0)) {
1244 return V_028C70_COLOR_5_6_5;
1245 } else if (HAS_SIZE(32,8,24,0)) {
1246 return V_028C70_COLOR_X24_8_32_FLOAT;
1247 }
1248 break;
1249 case 4:
1250 if (desc->channel[0].size == desc->channel[1].size &&
1251 desc->channel[0].size == desc->channel[2].size &&
1252 desc->channel[0].size == desc->channel[3].size) {
1253 switch (desc->channel[0].size) {
1254 case 4:
1255 return V_028C70_COLOR_4_4_4_4;
1256 case 8:
1257 return V_028C70_COLOR_8_8_8_8;
1258 case 16:
1259 return V_028C70_COLOR_16_16_16_16;
1260 case 32:
1261 return V_028C70_COLOR_32_32_32_32;
1262 }
1263 } else if (HAS_SIZE(5,5,5,1)) {
1264 return V_028C70_COLOR_1_5_5_5;
1265 } else if (HAS_SIZE(10,10,10,2)) {
1266 return V_028C70_COLOR_2_10_10_10;
1267 }
1268 break;
1269 }
1270 return V_028C70_COLOR_INVALID;
1271 }
1272
1273 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1274 {
1275 if (SI_BIG_ENDIAN) {
1276 switch(colorformat) {
1277 /* 8-bit buffers. */
1278 case V_028C70_COLOR_8:
1279 return V_028C70_ENDIAN_NONE;
1280
1281 /* 16-bit buffers. */
1282 case V_028C70_COLOR_5_6_5:
1283 case V_028C70_COLOR_1_5_5_5:
1284 case V_028C70_COLOR_4_4_4_4:
1285 case V_028C70_COLOR_16:
1286 case V_028C70_COLOR_8_8:
1287 return V_028C70_ENDIAN_8IN16;
1288
1289 /* 32-bit buffers. */
1290 case V_028C70_COLOR_8_8_8_8:
1291 case V_028C70_COLOR_2_10_10_10:
1292 case V_028C70_COLOR_8_24:
1293 case V_028C70_COLOR_24_8:
1294 case V_028C70_COLOR_16_16:
1295 return V_028C70_ENDIAN_8IN32;
1296
1297 /* 64-bit buffers. */
1298 case V_028C70_COLOR_16_16_16_16:
1299 return V_028C70_ENDIAN_8IN16;
1300
1301 case V_028C70_COLOR_32_32:
1302 return V_028C70_ENDIAN_8IN32;
1303
1304 /* 128-bit buffers. */
1305 case V_028C70_COLOR_32_32_32_32:
1306 return V_028C70_ENDIAN_8IN32;
1307 default:
1308 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1309 }
1310 } else {
1311 return V_028C70_ENDIAN_NONE;
1312 }
1313 }
1314
1315 static uint32_t si_translate_dbformat(enum pipe_format format)
1316 {
1317 switch (format) {
1318 case PIPE_FORMAT_Z16_UNORM:
1319 return V_028040_Z_16;
1320 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1321 case PIPE_FORMAT_X8Z24_UNORM:
1322 case PIPE_FORMAT_Z24X8_UNORM:
1323 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1324 return V_028040_Z_24; /* deprecated on SI */
1325 case PIPE_FORMAT_Z32_FLOAT:
1326 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1327 return V_028040_Z_32_FLOAT;
1328 default:
1329 return V_028040_Z_INVALID;
1330 }
1331 }
1332
1333 /*
1334 * Texture translation
1335 */
1336
1337 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1338 enum pipe_format format,
1339 const struct util_format_description *desc,
1340 int first_non_void)
1341 {
1342 struct si_screen *sscreen = (struct si_screen*)screen;
1343 bool enable_compressed_formats = (sscreen->b.info.drm_major == 2 &&
1344 sscreen->b.info.drm_minor >= 31) ||
1345 sscreen->b.info.drm_major == 3;
1346 bool uniform = true;
1347 int i;
1348
1349 /* Colorspace (return non-RGB formats directly). */
1350 switch (desc->colorspace) {
1351 /* Depth stencil formats */
1352 case UTIL_FORMAT_COLORSPACE_ZS:
1353 switch (format) {
1354 case PIPE_FORMAT_Z16_UNORM:
1355 return V_008F14_IMG_DATA_FORMAT_16;
1356 case PIPE_FORMAT_X24S8_UINT:
1357 case PIPE_FORMAT_Z24X8_UNORM:
1358 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1359 return V_008F14_IMG_DATA_FORMAT_8_24;
1360 case PIPE_FORMAT_X8Z24_UNORM:
1361 case PIPE_FORMAT_S8X24_UINT:
1362 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1363 return V_008F14_IMG_DATA_FORMAT_24_8;
1364 case PIPE_FORMAT_S8_UINT:
1365 return V_008F14_IMG_DATA_FORMAT_8;
1366 case PIPE_FORMAT_Z32_FLOAT:
1367 return V_008F14_IMG_DATA_FORMAT_32;
1368 case PIPE_FORMAT_X32_S8X24_UINT:
1369 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1370 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1371 default:
1372 goto out_unknown;
1373 }
1374
1375 case UTIL_FORMAT_COLORSPACE_YUV:
1376 goto out_unknown; /* TODO */
1377
1378 case UTIL_FORMAT_COLORSPACE_SRGB:
1379 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1380 goto out_unknown;
1381 break;
1382
1383 default:
1384 break;
1385 }
1386
1387 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1388 if (!enable_compressed_formats)
1389 goto out_unknown;
1390
1391 switch (format) {
1392 case PIPE_FORMAT_RGTC1_SNORM:
1393 case PIPE_FORMAT_LATC1_SNORM:
1394 case PIPE_FORMAT_RGTC1_UNORM:
1395 case PIPE_FORMAT_LATC1_UNORM:
1396 return V_008F14_IMG_DATA_FORMAT_BC4;
1397 case PIPE_FORMAT_RGTC2_SNORM:
1398 case PIPE_FORMAT_LATC2_SNORM:
1399 case PIPE_FORMAT_RGTC2_UNORM:
1400 case PIPE_FORMAT_LATC2_UNORM:
1401 return V_008F14_IMG_DATA_FORMAT_BC5;
1402 default:
1403 goto out_unknown;
1404 }
1405 }
1406
1407 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1408 sscreen->b.family == CHIP_STONEY) {
1409 switch (format) {
1410 case PIPE_FORMAT_ETC1_RGB8:
1411 case PIPE_FORMAT_ETC2_RGB8:
1412 case PIPE_FORMAT_ETC2_SRGB8:
1413 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1414 case PIPE_FORMAT_ETC2_RGB8A1:
1415 case PIPE_FORMAT_ETC2_SRGB8A1:
1416 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1417 case PIPE_FORMAT_ETC2_RGBA8:
1418 case PIPE_FORMAT_ETC2_SRGBA8:
1419 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1420 case PIPE_FORMAT_ETC2_R11_UNORM:
1421 case PIPE_FORMAT_ETC2_R11_SNORM:
1422 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1423 case PIPE_FORMAT_ETC2_RG11_UNORM:
1424 case PIPE_FORMAT_ETC2_RG11_SNORM:
1425 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1426 default:
1427 goto out_unknown;
1428 }
1429 }
1430
1431 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1432 if (!enable_compressed_formats)
1433 goto out_unknown;
1434
1435 switch (format) {
1436 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1437 case PIPE_FORMAT_BPTC_SRGBA:
1438 return V_008F14_IMG_DATA_FORMAT_BC7;
1439 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1440 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1441 return V_008F14_IMG_DATA_FORMAT_BC6;
1442 default:
1443 goto out_unknown;
1444 }
1445 }
1446
1447 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1448 switch (format) {
1449 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1450 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1451 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1452 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1453 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1454 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1455 default:
1456 goto out_unknown;
1457 }
1458 }
1459
1460 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1461 if (!enable_compressed_formats)
1462 goto out_unknown;
1463
1464 if (!util_format_s3tc_enabled) {
1465 goto out_unknown;
1466 }
1467
1468 switch (format) {
1469 case PIPE_FORMAT_DXT1_RGB:
1470 case PIPE_FORMAT_DXT1_RGBA:
1471 case PIPE_FORMAT_DXT1_SRGB:
1472 case PIPE_FORMAT_DXT1_SRGBA:
1473 return V_008F14_IMG_DATA_FORMAT_BC1;
1474 case PIPE_FORMAT_DXT3_RGBA:
1475 case PIPE_FORMAT_DXT3_SRGBA:
1476 return V_008F14_IMG_DATA_FORMAT_BC2;
1477 case PIPE_FORMAT_DXT5_RGBA:
1478 case PIPE_FORMAT_DXT5_SRGBA:
1479 return V_008F14_IMG_DATA_FORMAT_BC3;
1480 default:
1481 goto out_unknown;
1482 }
1483 }
1484
1485 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1486 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1487 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1488 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1489 }
1490
1491 /* R8G8Bx_SNORM - TODO CxV8U8 */
1492
1493 /* hw cannot support mixed formats (except depth/stencil, since only
1494 * depth is read).*/
1495 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1496 goto out_unknown;
1497
1498 /* See whether the components are of the same size. */
1499 for (i = 1; i < desc->nr_channels; i++) {
1500 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1501 }
1502
1503 /* Non-uniform formats. */
1504 if (!uniform) {
1505 switch(desc->nr_channels) {
1506 case 3:
1507 if (desc->channel[0].size == 5 &&
1508 desc->channel[1].size == 6 &&
1509 desc->channel[2].size == 5) {
1510 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1511 }
1512 goto out_unknown;
1513 case 4:
1514 if (desc->channel[0].size == 5 &&
1515 desc->channel[1].size == 5 &&
1516 desc->channel[2].size == 5 &&
1517 desc->channel[3].size == 1) {
1518 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1519 }
1520 if (desc->channel[0].size == 10 &&
1521 desc->channel[1].size == 10 &&
1522 desc->channel[2].size == 10 &&
1523 desc->channel[3].size == 2) {
1524 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1525 }
1526 goto out_unknown;
1527 }
1528 goto out_unknown;
1529 }
1530
1531 if (first_non_void < 0 || first_non_void > 3)
1532 goto out_unknown;
1533
1534 /* uniform formats */
1535 switch (desc->channel[first_non_void].size) {
1536 case 4:
1537 switch (desc->nr_channels) {
1538 #if 0 /* Not supported for render targets */
1539 case 2:
1540 return V_008F14_IMG_DATA_FORMAT_4_4;
1541 #endif
1542 case 4:
1543 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1544 }
1545 break;
1546 case 8:
1547 switch (desc->nr_channels) {
1548 case 1:
1549 return V_008F14_IMG_DATA_FORMAT_8;
1550 case 2:
1551 return V_008F14_IMG_DATA_FORMAT_8_8;
1552 case 4:
1553 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1554 }
1555 break;
1556 case 16:
1557 switch (desc->nr_channels) {
1558 case 1:
1559 return V_008F14_IMG_DATA_FORMAT_16;
1560 case 2:
1561 return V_008F14_IMG_DATA_FORMAT_16_16;
1562 case 4:
1563 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1564 }
1565 break;
1566 case 32:
1567 switch (desc->nr_channels) {
1568 case 1:
1569 return V_008F14_IMG_DATA_FORMAT_32;
1570 case 2:
1571 return V_008F14_IMG_DATA_FORMAT_32_32;
1572 #if 0 /* Not supported for render targets */
1573 case 3:
1574 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1575 #endif
1576 case 4:
1577 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1578 }
1579 }
1580
1581 out_unknown:
1582 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1583 return ~0;
1584 }
1585
1586 static unsigned si_tex_wrap(unsigned wrap)
1587 {
1588 switch (wrap) {
1589 default:
1590 case PIPE_TEX_WRAP_REPEAT:
1591 return V_008F30_SQ_TEX_WRAP;
1592 case PIPE_TEX_WRAP_CLAMP:
1593 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1594 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1595 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1596 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1597 return V_008F30_SQ_TEX_CLAMP_BORDER;
1598 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1599 return V_008F30_SQ_TEX_MIRROR;
1600 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1601 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1602 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1603 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1604 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1605 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1606 }
1607 }
1608
1609 static unsigned si_tex_mipfilter(unsigned filter)
1610 {
1611 switch (filter) {
1612 case PIPE_TEX_MIPFILTER_NEAREST:
1613 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1614 case PIPE_TEX_MIPFILTER_LINEAR:
1615 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1616 default:
1617 case PIPE_TEX_MIPFILTER_NONE:
1618 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1619 }
1620 }
1621
1622 static unsigned si_tex_compare(unsigned compare)
1623 {
1624 switch (compare) {
1625 default:
1626 case PIPE_FUNC_NEVER:
1627 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1628 case PIPE_FUNC_LESS:
1629 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1630 case PIPE_FUNC_EQUAL:
1631 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1632 case PIPE_FUNC_LEQUAL:
1633 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1634 case PIPE_FUNC_GREATER:
1635 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1636 case PIPE_FUNC_NOTEQUAL:
1637 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1638 case PIPE_FUNC_GEQUAL:
1639 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1640 case PIPE_FUNC_ALWAYS:
1641 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1642 }
1643 }
1644
1645 static unsigned si_tex_dim(unsigned res_target, unsigned view_target,
1646 unsigned nr_samples)
1647 {
1648 if (view_target == PIPE_TEXTURE_CUBE ||
1649 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1650 res_target = view_target;
1651 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1652 else if (res_target == PIPE_TEXTURE_CUBE ||
1653 res_target == PIPE_TEXTURE_CUBE_ARRAY)
1654 res_target = PIPE_TEXTURE_2D_ARRAY;
1655
1656 switch (res_target) {
1657 default:
1658 case PIPE_TEXTURE_1D:
1659 return V_008F1C_SQ_RSRC_IMG_1D;
1660 case PIPE_TEXTURE_1D_ARRAY:
1661 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1662 case PIPE_TEXTURE_2D:
1663 case PIPE_TEXTURE_RECT:
1664 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1665 V_008F1C_SQ_RSRC_IMG_2D;
1666 case PIPE_TEXTURE_2D_ARRAY:
1667 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1668 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1669 case PIPE_TEXTURE_3D:
1670 return V_008F1C_SQ_RSRC_IMG_3D;
1671 case PIPE_TEXTURE_CUBE:
1672 case PIPE_TEXTURE_CUBE_ARRAY:
1673 return V_008F1C_SQ_RSRC_IMG_CUBE;
1674 }
1675 }
1676
1677 /*
1678 * Format support testing
1679 */
1680
1681 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1682 {
1683 return si_translate_texformat(screen, format, util_format_description(format),
1684 util_format_get_first_non_void_channel(format)) != ~0U;
1685 }
1686
1687 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1688 const struct util_format_description *desc,
1689 int first_non_void)
1690 {
1691 unsigned type;
1692 int i;
1693
1694 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1695 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1696
1697 assert(first_non_void >= 0);
1698 type = desc->channel[first_non_void].type;
1699
1700 if (type == UTIL_FORMAT_TYPE_FIXED)
1701 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1702
1703 if (desc->nr_channels == 4 &&
1704 desc->channel[0].size == 10 &&
1705 desc->channel[1].size == 10 &&
1706 desc->channel[2].size == 10 &&
1707 desc->channel[3].size == 2)
1708 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1709
1710 /* See whether the components are of the same size. */
1711 for (i = 0; i < desc->nr_channels; i++) {
1712 if (desc->channel[first_non_void].size != desc->channel[i].size)
1713 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1714 }
1715
1716 switch (desc->channel[first_non_void].size) {
1717 case 8:
1718 switch (desc->nr_channels) {
1719 case 1:
1720 return V_008F0C_BUF_DATA_FORMAT_8;
1721 case 2:
1722 return V_008F0C_BUF_DATA_FORMAT_8_8;
1723 case 3:
1724 case 4:
1725 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1726 }
1727 break;
1728 case 16:
1729 switch (desc->nr_channels) {
1730 case 1:
1731 return V_008F0C_BUF_DATA_FORMAT_16;
1732 case 2:
1733 return V_008F0C_BUF_DATA_FORMAT_16_16;
1734 case 3:
1735 case 4:
1736 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1737 }
1738 break;
1739 case 32:
1740 /* From the Southern Islands ISA documentation about MTBUF:
1741 * 'Memory reads of data in memory that is 32 or 64 bits do not
1742 * undergo any format conversion.'
1743 */
1744 if (type != UTIL_FORMAT_TYPE_FLOAT &&
1745 !desc->channel[first_non_void].pure_integer)
1746 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1747
1748 switch (desc->nr_channels) {
1749 case 1:
1750 return V_008F0C_BUF_DATA_FORMAT_32;
1751 case 2:
1752 return V_008F0C_BUF_DATA_FORMAT_32_32;
1753 case 3:
1754 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1755 case 4:
1756 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1757 }
1758 break;
1759 }
1760
1761 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1762 }
1763
1764 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1765 const struct util_format_description *desc,
1766 int first_non_void)
1767 {
1768 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1769 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1770
1771 assert(first_non_void >= 0);
1772
1773 switch (desc->channel[first_non_void].type) {
1774 case UTIL_FORMAT_TYPE_SIGNED:
1775 if (desc->channel[first_non_void].normalized)
1776 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1777 else if (desc->channel[first_non_void].pure_integer)
1778 return V_008F0C_BUF_NUM_FORMAT_SINT;
1779 else
1780 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1781 break;
1782 case UTIL_FORMAT_TYPE_UNSIGNED:
1783 if (desc->channel[first_non_void].normalized)
1784 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1785 else if (desc->channel[first_non_void].pure_integer)
1786 return V_008F0C_BUF_NUM_FORMAT_UINT;
1787 else
1788 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1789 break;
1790 case UTIL_FORMAT_TYPE_FLOAT:
1791 default:
1792 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1793 }
1794 }
1795
1796 static unsigned si_is_vertex_format_supported(struct pipe_screen *screen,
1797 enum pipe_format format,
1798 unsigned usage)
1799 {
1800 const struct util_format_description *desc;
1801 int first_non_void;
1802 unsigned data_format;
1803
1804 assert((usage & ~(PIPE_BIND_SHADER_IMAGE |
1805 PIPE_BIND_SAMPLER_VIEW |
1806 PIPE_BIND_VERTEX_BUFFER)) == 0);
1807
1808 desc = util_format_description(format);
1809
1810 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
1811 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
1812 * for read-only access (with caveats surrounding bounds checks), but
1813 * obviously fails for write access which we have to implement for
1814 * shader images. Luckily, OpenGL doesn't expect this to be supported
1815 * anyway, and so the only impact is on PBO uploads / downloads, which
1816 * shouldn't be expected to be fast for GL_RGB anyway.
1817 */
1818 if (desc->block.bits == 3 * 8 ||
1819 desc->block.bits == 3 * 16) {
1820 if (usage & (PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW)) {
1821 usage &= ~(PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW);
1822 if (!usage)
1823 return 0;
1824 }
1825 }
1826
1827 first_non_void = util_format_get_first_non_void_channel(format);
1828 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1829 if (data_format == V_008F0C_BUF_DATA_FORMAT_INVALID)
1830 return 0;
1831
1832 return usage;
1833 }
1834
1835 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1836 {
1837 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1838 r600_translate_colorswap(format, false) != ~0U;
1839 }
1840
1841 static bool si_is_zs_format_supported(enum pipe_format format)
1842 {
1843 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1844 }
1845
1846 static boolean si_is_format_supported(struct pipe_screen *screen,
1847 enum pipe_format format,
1848 enum pipe_texture_target target,
1849 unsigned sample_count,
1850 unsigned usage)
1851 {
1852 unsigned retval = 0;
1853
1854 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1855 R600_ERR("r600: unsupported texture type %d\n", target);
1856 return false;
1857 }
1858
1859 if (!util_format_is_supported(format, usage))
1860 return false;
1861
1862 if (sample_count > 1) {
1863 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
1864 return false;
1865
1866 if (usage & PIPE_BIND_SHADER_IMAGE)
1867 return false;
1868
1869 switch (sample_count) {
1870 case 2:
1871 case 4:
1872 case 8:
1873 break;
1874 case 16:
1875 if (format == PIPE_FORMAT_NONE)
1876 return true;
1877 else
1878 return false;
1879 default:
1880 return false;
1881 }
1882 }
1883
1884 if (usage & (PIPE_BIND_SAMPLER_VIEW |
1885 PIPE_BIND_SHADER_IMAGE)) {
1886 if (target == PIPE_BUFFER) {
1887 retval |= si_is_vertex_format_supported(
1888 screen, format, usage & (PIPE_BIND_SAMPLER_VIEW |
1889 PIPE_BIND_SHADER_IMAGE));
1890 } else {
1891 if (si_is_sampler_format_supported(screen, format))
1892 retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
1893 PIPE_BIND_SHADER_IMAGE);
1894 }
1895 }
1896
1897 if ((usage & (PIPE_BIND_RENDER_TARGET |
1898 PIPE_BIND_DISPLAY_TARGET |
1899 PIPE_BIND_SCANOUT |
1900 PIPE_BIND_SHARED |
1901 PIPE_BIND_BLENDABLE)) &&
1902 si_is_colorbuffer_format_supported(format)) {
1903 retval |= usage &
1904 (PIPE_BIND_RENDER_TARGET |
1905 PIPE_BIND_DISPLAY_TARGET |
1906 PIPE_BIND_SCANOUT |
1907 PIPE_BIND_SHARED);
1908 if (!util_format_is_pure_integer(format) &&
1909 !util_format_is_depth_or_stencil(format))
1910 retval |= usage & PIPE_BIND_BLENDABLE;
1911 }
1912
1913 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1914 si_is_zs_format_supported(format)) {
1915 retval |= PIPE_BIND_DEPTH_STENCIL;
1916 }
1917
1918 if (usage & PIPE_BIND_VERTEX_BUFFER) {
1919 retval |= si_is_vertex_format_supported(screen, format,
1920 PIPE_BIND_VERTEX_BUFFER);
1921 }
1922
1923 if ((usage & PIPE_BIND_LINEAR) &&
1924 !util_format_is_compressed(format) &&
1925 !(usage & PIPE_BIND_DEPTH_STENCIL))
1926 retval |= PIPE_BIND_LINEAR;
1927
1928 return retval == usage;
1929 }
1930
1931 /*
1932 * framebuffer handling
1933 */
1934
1935 static void si_choose_spi_color_formats(struct r600_surface *surf,
1936 unsigned format, unsigned swap,
1937 unsigned ntype, bool is_depth)
1938 {
1939 /* Alpha is needed for alpha-to-coverage.
1940 * Blending may be with or without alpha.
1941 */
1942 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
1943 unsigned alpha = 0; /* exports alpha, but may not support blending */
1944 unsigned blend = 0; /* supports blending, but may not export alpha */
1945 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
1946
1947 /* Choose the SPI color formats. These are required values for Stoney/RB+.
1948 * Other chips have multiple choices, though they are not necessarily better.
1949 */
1950 switch (format) {
1951 case V_028C70_COLOR_5_6_5:
1952 case V_028C70_COLOR_1_5_5_5:
1953 case V_028C70_COLOR_5_5_5_1:
1954 case V_028C70_COLOR_4_4_4_4:
1955 case V_028C70_COLOR_10_11_11:
1956 case V_028C70_COLOR_11_11_10:
1957 case V_028C70_COLOR_8:
1958 case V_028C70_COLOR_8_8:
1959 case V_028C70_COLOR_8_8_8_8:
1960 case V_028C70_COLOR_10_10_10_2:
1961 case V_028C70_COLOR_2_10_10_10:
1962 if (ntype == V_028C70_NUMBER_UINT)
1963 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
1964 else if (ntype == V_028C70_NUMBER_SINT)
1965 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
1966 else
1967 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
1968 break;
1969
1970 case V_028C70_COLOR_16:
1971 case V_028C70_COLOR_16_16:
1972 case V_028C70_COLOR_16_16_16_16:
1973 if (ntype == V_028C70_NUMBER_UNORM ||
1974 ntype == V_028C70_NUMBER_SNORM) {
1975 /* UNORM16 and SNORM16 don't support blending */
1976 if (ntype == V_028C70_NUMBER_UNORM)
1977 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
1978 else
1979 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
1980
1981 /* Use 32 bits per channel for blending. */
1982 if (format == V_028C70_COLOR_16) {
1983 if (swap == V_028C70_SWAP_STD) { /* R */
1984 blend = V_028714_SPI_SHADER_32_R;
1985 blend_alpha = V_028714_SPI_SHADER_32_AR;
1986 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
1987 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
1988 else
1989 assert(0);
1990 } else if (format == V_028C70_COLOR_16_16) {
1991 if (swap == V_028C70_SWAP_STD) { /* RG */
1992 blend = V_028714_SPI_SHADER_32_GR;
1993 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
1994 } else if (swap == V_028C70_SWAP_ALT) /* RA */
1995 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
1996 else
1997 assert(0);
1998 } else /* 16_16_16_16 */
1999 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2000 } else if (ntype == V_028C70_NUMBER_UINT)
2001 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2002 else if (ntype == V_028C70_NUMBER_SINT)
2003 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2004 else if (ntype == V_028C70_NUMBER_FLOAT)
2005 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2006 else
2007 assert(0);
2008 break;
2009
2010 case V_028C70_COLOR_32:
2011 if (swap == V_028C70_SWAP_STD) { /* R */
2012 blend = normal = V_028714_SPI_SHADER_32_R;
2013 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
2014 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2015 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2016 else
2017 assert(0);
2018 break;
2019
2020 case V_028C70_COLOR_32_32:
2021 if (swap == V_028C70_SWAP_STD) { /* RG */
2022 blend = normal = V_028714_SPI_SHADER_32_GR;
2023 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2024 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2025 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2026 else
2027 assert(0);
2028 break;
2029
2030 case V_028C70_COLOR_32_32_32_32:
2031 case V_028C70_COLOR_8_24:
2032 case V_028C70_COLOR_24_8:
2033 case V_028C70_COLOR_X24_8_32_FLOAT:
2034 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2035 break;
2036
2037 default:
2038 assert(0);
2039 return;
2040 }
2041
2042 /* The DB->CB copy needs 32_ABGR. */
2043 if (is_depth)
2044 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2045
2046 surf->spi_shader_col_format = normal;
2047 surf->spi_shader_col_format_alpha = alpha;
2048 surf->spi_shader_col_format_blend = blend;
2049 surf->spi_shader_col_format_blend_alpha = blend_alpha;
2050 }
2051
2052 static void si_initialize_color_surface(struct si_context *sctx,
2053 struct r600_surface *surf)
2054 {
2055 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2056 unsigned color_info, color_attrib, color_view;
2057 unsigned format, swap, ntype, endian;
2058 const struct util_format_description *desc;
2059 int i;
2060 unsigned blend_clamp = 0, blend_bypass = 0;
2061
2062 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2063 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
2064
2065 desc = util_format_description(surf->base.format);
2066 for (i = 0; i < 4; i++) {
2067 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2068 break;
2069 }
2070 }
2071 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
2072 ntype = V_028C70_NUMBER_FLOAT;
2073 } else {
2074 ntype = V_028C70_NUMBER_UNORM;
2075 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2076 ntype = V_028C70_NUMBER_SRGB;
2077 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2078 if (desc->channel[i].pure_integer) {
2079 ntype = V_028C70_NUMBER_SINT;
2080 } else {
2081 assert(desc->channel[i].normalized);
2082 ntype = V_028C70_NUMBER_SNORM;
2083 }
2084 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2085 if (desc->channel[i].pure_integer) {
2086 ntype = V_028C70_NUMBER_UINT;
2087 } else {
2088 assert(desc->channel[i].normalized);
2089 ntype = V_028C70_NUMBER_UNORM;
2090 }
2091 }
2092 }
2093
2094 format = si_translate_colorformat(surf->base.format);
2095 if (format == V_028C70_COLOR_INVALID) {
2096 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2097 }
2098 assert(format != V_028C70_COLOR_INVALID);
2099 swap = r600_translate_colorswap(surf->base.format, false);
2100 endian = si_colorformat_endian_swap(format);
2101
2102 /* blend clamp should be set for all NORM/SRGB types */
2103 if (ntype == V_028C70_NUMBER_UNORM ||
2104 ntype == V_028C70_NUMBER_SNORM ||
2105 ntype == V_028C70_NUMBER_SRGB)
2106 blend_clamp = 1;
2107
2108 /* set blend bypass according to docs if SINT/UINT or
2109 8/24 COLOR variants */
2110 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2111 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2112 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2113 blend_clamp = 0;
2114 blend_bypass = 1;
2115 }
2116
2117 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
2118 (format == V_028C70_COLOR_8 ||
2119 format == V_028C70_COLOR_8_8 ||
2120 format == V_028C70_COLOR_8_8_8_8))
2121 surf->color_is_int8 = true;
2122
2123 color_info = S_028C70_FORMAT(format) |
2124 S_028C70_COMP_SWAP(swap) |
2125 S_028C70_BLEND_CLAMP(blend_clamp) |
2126 S_028C70_BLEND_BYPASS(blend_bypass) |
2127 S_028C70_SIMPLE_FLOAT(1) |
2128 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2129 ntype != V_028C70_NUMBER_SNORM &&
2130 ntype != V_028C70_NUMBER_SRGB &&
2131 format != V_028C70_COLOR_8_24 &&
2132 format != V_028C70_COLOR_24_8) |
2133 S_028C70_NUMBER_TYPE(ntype) |
2134 S_028C70_ENDIAN(endian);
2135
2136 /* Intensity is implemented as Red, so treat it that way. */
2137 color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2138 util_format_is_intensity(surf->base.format));
2139
2140 if (rtex->resource.b.b.nr_samples > 1) {
2141 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
2142
2143 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2144 S_028C74_NUM_FRAGMENTS(log_samples);
2145
2146 if (rtex->fmask.size) {
2147 color_info |= S_028C70_COMPRESSION(1);
2148 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
2149
2150 if (sctx->b.chip_class == SI) {
2151 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2152 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2153 }
2154 }
2155 }
2156
2157 surf->cb_color_view = color_view;
2158 surf->cb_color_info = color_info;
2159 surf->cb_color_attrib = color_attrib;
2160
2161 if (sctx->b.chip_class >= VI) {
2162 unsigned max_uncompressed_block_size = 2;
2163
2164 if (rtex->resource.b.b.nr_samples > 1) {
2165 if (rtex->surface.bpe == 1)
2166 max_uncompressed_block_size = 0;
2167 else if (rtex->surface.bpe == 2)
2168 max_uncompressed_block_size = 1;
2169 }
2170
2171 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2172 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2173 }
2174
2175 /* This must be set for fast clear to work without FMASK. */
2176 if (!rtex->fmask.size && sctx->b.chip_class == SI) {
2177 unsigned bankh = util_logbase2(rtex->surface.bankh);
2178 surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2179 }
2180
2181 /* Determine pixel shader export format */
2182 si_choose_spi_color_formats(surf, format, swap, ntype, rtex->is_depth);
2183
2184 surf->color_initialized = true;
2185 }
2186
2187 static void si_init_depth_surface(struct si_context *sctx,
2188 struct r600_surface *surf)
2189 {
2190 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2191 unsigned level = surf->base.u.tex.level;
2192 struct radeon_surf_level *levelinfo = &rtex->surface.level[level];
2193 unsigned format;
2194 uint32_t z_info, s_info, db_depth_info;
2195 uint64_t z_offs, s_offs;
2196 uint32_t db_htile_data_base, db_htile_surface;
2197
2198 format = si_translate_dbformat(rtex->db_render_format);
2199
2200 if (format == V_028040_Z_INVALID) {
2201 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
2202 }
2203 assert(format != V_028040_Z_INVALID);
2204
2205 s_offs = z_offs = rtex->resource.gpu_address;
2206 z_offs += rtex->surface.level[level].offset;
2207 s_offs += rtex->surface.stencil_level[level].offset;
2208
2209 db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!rtex->tc_compatible_htile);
2210
2211 z_info = S_028040_FORMAT(format);
2212 if (rtex->resource.b.b.nr_samples > 1) {
2213 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
2214 }
2215
2216 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
2217 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
2218 else
2219 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
2220
2221 if (sctx->b.chip_class >= CIK) {
2222 struct radeon_info *info = &sctx->screen->b.info;
2223 unsigned index = rtex->surface.tiling_index[level];
2224 unsigned stencil_index = rtex->surface.stencil_tiling_index[level];
2225 unsigned macro_index = rtex->surface.macro_tile_index;
2226 unsigned tile_mode = info->si_tile_mode_array[index];
2227 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2228 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2229
2230 db_depth_info |=
2231 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2232 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2233 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2234 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2235 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2236 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2237 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2238 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2239 } else {
2240 unsigned tile_mode_index = si_tile_mode_index(rtex, level, false);
2241 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2242 tile_mode_index = si_tile_mode_index(rtex, level, true);
2243 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2244 }
2245
2246 /* HiZ aka depth buffer htile */
2247 /* use htile only for first level */
2248 if (rtex->htile_buffer && !level) {
2249 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2250 S_028040_ALLOW_EXPCLEAR(1);
2251
2252 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
2253 /* Workaround: For a not yet understood reason, the
2254 * combination of MSAA, fast stencil clear and stencil
2255 * decompress messes with subsequent stencil buffer
2256 * uses. Problem was reproduced on Verde, Bonaire,
2257 * Tonga, and Carrizo.
2258 *
2259 * Disabling EXPCLEAR works around the problem.
2260 *
2261 * Check piglit's arb_texture_multisample-stencil-clear
2262 * test if you want to try changing this.
2263 */
2264 if (rtex->resource.b.b.nr_samples <= 1)
2265 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2266 } else if (!rtex->tc_compatible_htile) {
2267 /* Use all of the htile_buffer for depth if there's no stencil.
2268 * This must not be set when TC-compatible HTILE is enabled
2269 * due to a hw bug.
2270 */
2271 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2272 }
2273
2274 uint64_t va = rtex->htile_buffer->gpu_address;
2275 db_htile_data_base = va >> 8;
2276 db_htile_surface = S_028ABC_FULL_CACHE(1);
2277
2278 if (rtex->tc_compatible_htile) {
2279 db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
2280
2281 switch (rtex->resource.b.b.nr_samples) {
2282 case 0:
2283 case 1:
2284 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2285 break;
2286 case 2:
2287 case 4:
2288 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2289 break;
2290 case 8:
2291 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2292 break;
2293 default:
2294 assert(0);
2295 }
2296 }
2297 } else {
2298 db_htile_data_base = 0;
2299 db_htile_surface = 0;
2300 }
2301
2302 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2303
2304 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2305 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2306 surf->db_htile_data_base = db_htile_data_base;
2307 surf->db_depth_info = db_depth_info;
2308 surf->db_z_info = z_info;
2309 surf->db_stencil_info = s_info;
2310 surf->db_depth_base = z_offs >> 8;
2311 surf->db_stencil_base = s_offs >> 8;
2312 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2313 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2314 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2315 levelinfo->nblk_y) / 64 - 1);
2316 surf->db_htile_surface = db_htile_surface;
2317
2318 surf->depth_initialized = true;
2319 }
2320
2321 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
2322 {
2323 for (int i = 0; i < state->nr_cbufs; ++i) {
2324 struct r600_surface *surf = NULL;
2325 struct r600_texture *rtex;
2326
2327 if (!state->cbufs[i])
2328 continue;
2329 surf = (struct r600_surface*)state->cbufs[i];
2330 rtex = (struct r600_texture*)surf->base.texture;
2331
2332 p_atomic_dec(&rtex->framebuffers_bound);
2333 }
2334 }
2335
2336 static void si_set_framebuffer_state(struct pipe_context *ctx,
2337 const struct pipe_framebuffer_state *state)
2338 {
2339 struct si_context *sctx = (struct si_context *)ctx;
2340 struct pipe_constant_buffer constbuf = {0};
2341 struct r600_surface *surf = NULL;
2342 struct r600_texture *rtex;
2343 bool old_any_dst_linear = sctx->framebuffer.any_dst_linear;
2344 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2345 int i;
2346
2347 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
2348 if (!sctx->framebuffer.state.cbufs[i])
2349 continue;
2350
2351 rtex = (struct r600_texture*)sctx->framebuffer.state.cbufs[i]->texture;
2352 if (rtex->dcc_gather_statistics)
2353 vi_separate_dcc_stop_query(ctx, rtex);
2354 }
2355
2356 /* Only flush TC when changing the framebuffer state, because
2357 * the only client not using TC that can change textures is
2358 * the framebuffer.
2359 *
2360 * Flush all CB and DB caches here because all buffers can be used
2361 * for write by both TC (with shader image stores) and CB/DB.
2362 */
2363 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
2364 SI_CONTEXT_INV_GLOBAL_L2 |
2365 SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER |
2366 SI_CONTEXT_CS_PARTIAL_FLUSH;
2367
2368 /* Take the maximum of the old and new count. If the new count is lower,
2369 * dirtying is needed to disable the unbound colorbuffers.
2370 */
2371 sctx->framebuffer.dirty_cbufs |=
2372 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2373 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2374
2375 si_dec_framebuffer_counters(&sctx->framebuffer.state);
2376 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2377
2378 sctx->framebuffer.colorbuf_enabled_4bit = 0;
2379 sctx->framebuffer.spi_shader_col_format = 0;
2380 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2381 sctx->framebuffer.spi_shader_col_format_blend = 0;
2382 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2383 sctx->framebuffer.color_is_int8 = 0;
2384
2385 sctx->framebuffer.compressed_cb_mask = 0;
2386 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2387 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2388 sctx->framebuffer.any_dst_linear = false;
2389
2390 for (i = 0; i < state->nr_cbufs; i++) {
2391 if (!state->cbufs[i])
2392 continue;
2393
2394 surf = (struct r600_surface*)state->cbufs[i];
2395 rtex = (struct r600_texture*)surf->base.texture;
2396
2397 if (!surf->color_initialized) {
2398 si_initialize_color_surface(sctx, surf);
2399 }
2400
2401 sctx->framebuffer.colorbuf_enabled_4bit |= 0xf << (i * 4);
2402 sctx->framebuffer.spi_shader_col_format |=
2403 surf->spi_shader_col_format << (i * 4);
2404 sctx->framebuffer.spi_shader_col_format_alpha |=
2405 surf->spi_shader_col_format_alpha << (i * 4);
2406 sctx->framebuffer.spi_shader_col_format_blend |=
2407 surf->spi_shader_col_format_blend << (i * 4);
2408 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2409 surf->spi_shader_col_format_blend_alpha << (i * 4);
2410
2411 if (surf->color_is_int8)
2412 sctx->framebuffer.color_is_int8 |= 1 << i;
2413
2414 if (rtex->fmask.size) {
2415 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2416 }
2417
2418 if (rtex->surface.is_linear)
2419 sctx->framebuffer.any_dst_linear = true;
2420
2421 r600_context_add_resource_size(ctx, surf->base.texture);
2422
2423 p_atomic_inc(&rtex->framebuffers_bound);
2424
2425 if (rtex->dcc_gather_statistics) {
2426 /* Dirty tracking must be enabled for DCC usage analysis. */
2427 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2428 vi_separate_dcc_start_query(ctx, rtex);
2429 }
2430 }
2431
2432 if (state->zsbuf) {
2433 surf = (struct r600_surface*)state->zsbuf;
2434 rtex = (struct r600_texture*)surf->base.texture;
2435
2436 if (!surf->depth_initialized) {
2437 si_init_depth_surface(sctx, surf);
2438 }
2439 r600_context_add_resource_size(ctx, surf->base.texture);
2440 }
2441
2442 si_update_poly_offset_state(sctx);
2443 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2444 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
2445
2446 if (sctx->framebuffer.any_dst_linear != old_any_dst_linear)
2447 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2448
2449 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2450 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2451 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2452
2453 /* Set sample locations as fragment shader constants. */
2454 switch (sctx->framebuffer.nr_samples) {
2455 case 1:
2456 constbuf.user_buffer = sctx->b.sample_locations_1x;
2457 break;
2458 case 2:
2459 constbuf.user_buffer = sctx->b.sample_locations_2x;
2460 break;
2461 case 4:
2462 constbuf.user_buffer = sctx->b.sample_locations_4x;
2463 break;
2464 case 8:
2465 constbuf.user_buffer = sctx->b.sample_locations_8x;
2466 break;
2467 case 16:
2468 constbuf.user_buffer = sctx->b.sample_locations_16x;
2469 break;
2470 default:
2471 R600_ERR("Requested an invalid number of samples %i.\n",
2472 sctx->framebuffer.nr_samples);
2473 assert(0);
2474 }
2475 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2476 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
2477
2478 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
2479 }
2480
2481 sctx->need_check_render_feedback = true;
2482 sctx->do_update_shaders = true;
2483 }
2484
2485 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
2486 {
2487 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2488 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2489 unsigned i, nr_cbufs = state->nr_cbufs;
2490 struct r600_texture *tex = NULL;
2491 struct r600_surface *cb = NULL;
2492 unsigned cb_color_info = 0;
2493
2494 /* Colorbuffers. */
2495 for (i = 0; i < nr_cbufs; i++) {
2496 const struct radeon_surf_level *level_info;
2497 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
2498 unsigned cb_color_base, cb_color_fmask, cb_color_attrib;
2499 unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
2500
2501 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2502 continue;
2503
2504 cb = (struct r600_surface*)state->cbufs[i];
2505 if (!cb) {
2506 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2507 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2508 continue;
2509 }
2510
2511 tex = (struct r600_texture *)cb->base.texture;
2512 level_info = &tex->surface.level[cb->base.u.tex.level];
2513 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2514 &tex->resource, RADEON_USAGE_READWRITE,
2515 tex->resource.b.b.nr_samples > 1 ?
2516 RADEON_PRIO_COLOR_BUFFER_MSAA :
2517 RADEON_PRIO_COLOR_BUFFER);
2518
2519 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2520 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2521 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2522 RADEON_PRIO_CMASK);
2523 }
2524
2525 if (tex->dcc_separate_buffer)
2526 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2527 tex->dcc_separate_buffer,
2528 RADEON_USAGE_READWRITE,
2529 RADEON_PRIO_DCC);
2530
2531 /* Compute mutable surface parameters. */
2532 pitch_tile_max = level_info->nblk_x / 8 - 1;
2533 slice_tile_max = level_info->nblk_x *
2534 level_info->nblk_y / 64 - 1;
2535 tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false);
2536
2537 cb_color_base = (tex->resource.gpu_address + level_info->offset) >> 8;
2538 cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
2539 cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
2540 cb_color_attrib = cb->cb_color_attrib |
2541 S_028C74_TILE_MODE_INDEX(tile_mode_index);
2542
2543 if (tex->fmask.size) {
2544 if (sctx->b.chip_class >= CIK)
2545 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->fmask.pitch_in_pixels / 8 - 1);
2546 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->fmask.tile_mode_index);
2547 cb_color_fmask = (tex->resource.gpu_address + tex->fmask.offset) >> 8;
2548 cb_color_fmask_slice = S_028C88_TILE_MAX(tex->fmask.slice_tile_max);
2549 } else {
2550 /* This must be set for fast clear to work without FMASK. */
2551 if (sctx->b.chip_class >= CIK)
2552 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
2553 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
2554 cb_color_fmask = cb_color_base;
2555 cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
2556 }
2557
2558 cb_color_info = cb->cb_color_info | tex->cb_color_info;
2559
2560 if (tex->dcc_offset && cb->base.u.tex.level < tex->surface.num_dcc_levels) {
2561 bool is_msaa_resolve_dst = state->cbufs[0] &&
2562 state->cbufs[0]->texture->nr_samples > 1 &&
2563 state->cbufs[1] == &cb->base &&
2564 state->cbufs[1]->texture->nr_samples <= 1;
2565
2566 if (!is_msaa_resolve_dst)
2567 cb_color_info |= S_028C70_DCC_ENABLE(1);
2568 }
2569
2570 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
2571 sctx->b.chip_class >= VI ? 14 : 13);
2572 radeon_emit(cs, cb_color_base); /* R_028C60_CB_COLOR0_BASE */
2573 radeon_emit(cs, cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
2574 radeon_emit(cs, cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
2575 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
2576 radeon_emit(cs, cb_color_info); /* R_028C70_CB_COLOR0_INFO */
2577 radeon_emit(cs, cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
2578 radeon_emit(cs, cb->cb_dcc_control); /* R_028C78_CB_COLOR0_DCC_CONTROL */
2579 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
2580 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
2581 radeon_emit(cs, cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
2582 radeon_emit(cs, cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
2583 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
2584 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
2585
2586 if (sctx->b.chip_class >= VI) /* R_028C94_CB_COLOR0_DCC_BASE */
2587 radeon_emit(cs, ((!tex->dcc_separate_buffer ? tex->resource.gpu_address : 0) +
2588 tex->dcc_offset +
2589 tex->surface.level[cb->base.u.tex.level].dcc_offset) >> 8);
2590 }
2591 for (; i < 8 ; i++)
2592 if (sctx->framebuffer.dirty_cbufs & (1 << i))
2593 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
2594
2595 /* ZS buffer. */
2596 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
2597 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
2598 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
2599
2600 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2601 &rtex->resource, RADEON_USAGE_READWRITE,
2602 zb->base.texture->nr_samples > 1 ?
2603 RADEON_PRIO_DEPTH_BUFFER_MSAA :
2604 RADEON_PRIO_DEPTH_BUFFER);
2605
2606 if (zb->db_htile_data_base) {
2607 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2608 rtex->htile_buffer, RADEON_USAGE_READWRITE,
2609 RADEON_PRIO_HTILE);
2610 }
2611
2612 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
2613 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
2614
2615 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
2616 radeon_emit(cs, zb->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
2617 radeon_emit(cs, zb->db_z_info | /* R_028040_DB_Z_INFO */
2618 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
2619 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
2620 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
2621 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
2622 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
2623 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
2624 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
2625 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
2626
2627 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
2628 radeon_emit(cs, rtex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
2629 radeon_emit(cs, fui(rtex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
2630
2631 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
2632 } else if (sctx->framebuffer.dirty_zsbuf) {
2633 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
2634 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
2635 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
2636 }
2637
2638 /* Framebuffer dimensions. */
2639 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2640 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2641 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
2642
2643 sctx->framebuffer.dirty_cbufs = 0;
2644 sctx->framebuffer.dirty_zsbuf = false;
2645 }
2646
2647 static void si_emit_msaa_sample_locs(struct si_context *sctx,
2648 struct r600_atom *atom)
2649 {
2650 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2651 unsigned nr_samples = sctx->framebuffer.nr_samples;
2652
2653 /* Smoothing (only possible with nr_samples == 1) uses the same
2654 * sample locations as the MSAA it simulates.
2655 */
2656 if (nr_samples <= 1 && sctx->smoothing_enabled)
2657 nr_samples = SI_NUM_SMOOTH_AA_SAMPLES;
2658
2659 /* On Polaris, the small primitive filter uses the sample locations
2660 * even when MSAA is off, so we need to make sure they're set to 0.
2661 */
2662 if (sctx->b.family >= CHIP_POLARIS10)
2663 nr_samples = MAX2(nr_samples, 1);
2664
2665 if (nr_samples >= 1 &&
2666 (nr_samples != sctx->msaa_sample_locs.nr_samples)) {
2667 sctx->msaa_sample_locs.nr_samples = nr_samples;
2668 cayman_emit_msaa_sample_locs(cs, nr_samples);
2669 }
2670
2671 if (sctx->b.family >= CHIP_POLARIS10) {
2672 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
2673 unsigned small_prim_filter_cntl =
2674 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
2675 S_028830_LINE_FILTER_DISABLE(1); /* line bug */
2676
2677 /* The alternative of setting sample locations to 0 would
2678 * require a DB flush to avoid Z errors, see
2679 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
2680 */
2681 if (sctx->framebuffer.nr_samples > 1 && rs && !rs->multisample_enable)
2682 small_prim_filter_cntl &= C_028830_SMALL_PRIM_FILTER_ENABLE;
2683
2684 radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
2685 small_prim_filter_cntl);
2686 }
2687 }
2688
2689 static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom)
2690 {
2691 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2692 unsigned num_tile_pipes = sctx->screen->b.info.num_tile_pipes;
2693 /* 33% faster rendering to linear color buffers */
2694 bool dst_is_linear = sctx->framebuffer.any_dst_linear;
2695 unsigned sc_mode_cntl_1 =
2696 S_028A4C_WALK_SIZE(dst_is_linear) |
2697 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear) |
2698 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
2699 /* always 1: */
2700 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
2701 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
2702 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
2703 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
2704 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
2705 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
2706
2707 cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples,
2708 sctx->ps_iter_samples,
2709 sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0,
2710 sc_mode_cntl_1);
2711 }
2712
2713 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
2714 {
2715 struct si_context *sctx = (struct si_context *)ctx;
2716
2717 if (sctx->ps_iter_samples == min_samples)
2718 return;
2719
2720 sctx->ps_iter_samples = min_samples;
2721 sctx->do_update_shaders = true;
2722
2723 if (sctx->framebuffer.nr_samples > 1)
2724 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2725 }
2726
2727 /*
2728 * Samplers
2729 */
2730
2731 /**
2732 * Build the sampler view descriptor for a buffer texture.
2733 * @param state 256-bit descriptor; only the high 128 bits are filled in
2734 */
2735 void
2736 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
2737 enum pipe_format format,
2738 unsigned offset, unsigned size,
2739 uint32_t *state)
2740 {
2741 const struct util_format_description *desc;
2742 int first_non_void;
2743 unsigned stride;
2744 unsigned num_records;
2745 unsigned num_format, data_format;
2746
2747 desc = util_format_description(format);
2748 first_non_void = util_format_get_first_non_void_channel(format);
2749 stride = desc->block.bits / 8;
2750 num_format = si_translate_buffer_numformat(&screen->b.b, desc, first_non_void);
2751 data_format = si_translate_buffer_dataformat(&screen->b.b, desc, first_non_void);
2752
2753 num_records = size / stride;
2754 num_records = MIN2(num_records, (buf->b.b.width0 - offset) / stride);
2755
2756 if (screen->b.chip_class >= VI)
2757 num_records *= stride;
2758
2759 state[4] = 0;
2760 state[5] = S_008F04_STRIDE(stride);
2761 state[6] = num_records;
2762 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2763 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2764 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2765 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2766 S_008F0C_NUM_FORMAT(num_format) |
2767 S_008F0C_DATA_FORMAT(data_format);
2768 }
2769
2770 /**
2771 * Build the sampler view descriptor for a texture.
2772 */
2773 void
2774 si_make_texture_descriptor(struct si_screen *screen,
2775 struct r600_texture *tex,
2776 bool sampler,
2777 enum pipe_texture_target target,
2778 enum pipe_format pipe_format,
2779 const unsigned char state_swizzle[4],
2780 unsigned first_level, unsigned last_level,
2781 unsigned first_layer, unsigned last_layer,
2782 unsigned width, unsigned height, unsigned depth,
2783 uint32_t *state,
2784 uint32_t *fmask_state)
2785 {
2786 struct pipe_resource *res = &tex->resource.b.b;
2787 const struct util_format_description *desc;
2788 unsigned char swizzle[4];
2789 int first_non_void;
2790 unsigned num_format, data_format, type;
2791 uint64_t va;
2792
2793 desc = util_format_description(pipe_format);
2794
2795 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2796 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2797 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2798
2799 switch (pipe_format) {
2800 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2801 case PIPE_FORMAT_X24S8_UINT:
2802 case PIPE_FORMAT_X32_S8X24_UINT:
2803 case PIPE_FORMAT_X8Z24_UNORM:
2804 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
2805 break;
2806 default:
2807 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
2808 }
2809 } else {
2810 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2811 }
2812
2813 first_non_void = util_format_get_first_non_void_channel(pipe_format);
2814
2815 switch (pipe_format) {
2816 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2817 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2818 break;
2819 default:
2820 if (first_non_void < 0) {
2821 if (util_format_is_compressed(pipe_format)) {
2822 switch (pipe_format) {
2823 case PIPE_FORMAT_DXT1_SRGB:
2824 case PIPE_FORMAT_DXT1_SRGBA:
2825 case PIPE_FORMAT_DXT3_SRGBA:
2826 case PIPE_FORMAT_DXT5_SRGBA:
2827 case PIPE_FORMAT_BPTC_SRGBA:
2828 case PIPE_FORMAT_ETC2_SRGB8:
2829 case PIPE_FORMAT_ETC2_SRGB8A1:
2830 case PIPE_FORMAT_ETC2_SRGBA8:
2831 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2832 break;
2833 case PIPE_FORMAT_RGTC1_SNORM:
2834 case PIPE_FORMAT_LATC1_SNORM:
2835 case PIPE_FORMAT_RGTC2_SNORM:
2836 case PIPE_FORMAT_LATC2_SNORM:
2837 case PIPE_FORMAT_ETC2_R11_SNORM:
2838 case PIPE_FORMAT_ETC2_RG11_SNORM:
2839 /* implies float, so use SNORM/UNORM to determine
2840 whether data is signed or not */
2841 case PIPE_FORMAT_BPTC_RGB_FLOAT:
2842 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2843 break;
2844 default:
2845 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2846 break;
2847 }
2848 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
2849 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2850 } else {
2851 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2852 }
2853 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
2854 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2855 } else {
2856 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2857
2858 switch (desc->channel[first_non_void].type) {
2859 case UTIL_FORMAT_TYPE_FLOAT:
2860 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2861 break;
2862 case UTIL_FORMAT_TYPE_SIGNED:
2863 if (desc->channel[first_non_void].normalized)
2864 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2865 else if (desc->channel[first_non_void].pure_integer)
2866 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
2867 else
2868 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
2869 break;
2870 case UTIL_FORMAT_TYPE_UNSIGNED:
2871 if (desc->channel[first_non_void].normalized)
2872 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2873 else if (desc->channel[first_non_void].pure_integer)
2874 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
2875 else
2876 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
2877 }
2878 }
2879 }
2880
2881 data_format = si_translate_texformat(&screen->b.b, pipe_format, desc, first_non_void);
2882 if (data_format == ~0) {
2883 data_format = 0;
2884 }
2885
2886 if (!sampler &&
2887 (res->target == PIPE_TEXTURE_CUBE ||
2888 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
2889 res->target == PIPE_TEXTURE_3D)) {
2890 /* For the purpose of shader images, treat cube maps and 3D
2891 * textures as 2D arrays. For 3D textures, the address
2892 * calculations for mipmaps are different, so we rely on the
2893 * caller to effectively disable mipmaps.
2894 */
2895 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
2896
2897 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
2898 } else {
2899 type = si_tex_dim(res->target, target, res->nr_samples);
2900 }
2901
2902 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
2903 height = 1;
2904 depth = res->array_size;
2905 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
2906 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
2907 if (sampler || res->target != PIPE_TEXTURE_3D)
2908 depth = res->array_size;
2909 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
2910 depth = res->array_size / 6;
2911
2912 state[0] = 0;
2913 state[1] = (S_008F14_DATA_FORMAT(data_format) |
2914 S_008F14_NUM_FORMAT(num_format));
2915 state[2] = (S_008F18_WIDTH(width - 1) |
2916 S_008F18_HEIGHT(height - 1) |
2917 S_008F18_PERF_MOD(4));
2918 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2919 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2920 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2921 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2922 S_008F1C_BASE_LEVEL(res->nr_samples > 1 ?
2923 0 : first_level) |
2924 S_008F1C_LAST_LEVEL(res->nr_samples > 1 ?
2925 util_logbase2(res->nr_samples) :
2926 last_level) |
2927 S_008F1C_POW2_PAD(res->last_level > 0) |
2928 S_008F1C_TYPE(type));
2929 state[4] = S_008F20_DEPTH(depth - 1);
2930 state[5] = (S_008F24_BASE_ARRAY(first_layer) |
2931 S_008F24_LAST_ARRAY(last_layer));
2932 state[6] = 0;
2933 state[7] = 0;
2934
2935 if (tex->dcc_offset) {
2936 unsigned swap = r600_translate_colorswap(pipe_format, false);
2937
2938 state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
2939 } else {
2940 /* The last dword is unused by hw. The shader uses it to clear
2941 * bits in the first dword of sampler state.
2942 */
2943 if (screen->b.chip_class <= CIK && res->nr_samples <= 1) {
2944 if (first_level == last_level)
2945 state[7] = C_008F30_MAX_ANISO_RATIO;
2946 else
2947 state[7] = 0xffffffff;
2948 }
2949 }
2950
2951 /* Initialize the sampler view for FMASK. */
2952 if (tex->fmask.size) {
2953 uint32_t fmask_format;
2954
2955 va = tex->resource.gpu_address + tex->fmask.offset;
2956
2957 switch (res->nr_samples) {
2958 case 2:
2959 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
2960 break;
2961 case 4:
2962 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
2963 break;
2964 case 8:
2965 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
2966 break;
2967 default:
2968 assert(0);
2969 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
2970 }
2971
2972 fmask_state[0] = va >> 8;
2973 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
2974 S_008F14_DATA_FORMAT(fmask_format) |
2975 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT);
2976 fmask_state[2] = S_008F18_WIDTH(width - 1) |
2977 S_008F18_HEIGHT(height - 1);
2978 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
2979 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
2980 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
2981 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
2982 S_008F1C_TILING_INDEX(tex->fmask.tile_mode_index) |
2983 S_008F1C_TYPE(si_tex_dim(res->target, target, 0));
2984 fmask_state[4] = S_008F20_DEPTH(depth - 1) |
2985 S_008F20_PITCH(tex->fmask.pitch_in_pixels - 1);
2986 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer) |
2987 S_008F24_LAST_ARRAY(last_layer);
2988 fmask_state[6] = 0;
2989 fmask_state[7] = 0;
2990 }
2991 }
2992
2993 /**
2994 * Create a sampler view.
2995 *
2996 * @param ctx context
2997 * @param texture texture
2998 * @param state sampler view template
2999 * @param width0 width0 override (for compressed textures as int)
3000 * @param height0 height0 override (for compressed textures as int)
3001 * @param force_level set the base address to the level (for compressed textures)
3002 */
3003 struct pipe_sampler_view *
3004 si_create_sampler_view_custom(struct pipe_context *ctx,
3005 struct pipe_resource *texture,
3006 const struct pipe_sampler_view *state,
3007 unsigned width0, unsigned height0,
3008 unsigned force_level)
3009 {
3010 struct si_context *sctx = (struct si_context*)ctx;
3011 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
3012 struct r600_texture *tmp = (struct r600_texture*)texture;
3013 unsigned base_level, first_level, last_level;
3014 unsigned char state_swizzle[4];
3015 unsigned height, depth, width;
3016 unsigned last_layer = state->u.tex.last_layer;
3017 enum pipe_format pipe_format;
3018 const struct radeon_surf_level *surflevel;
3019
3020 if (!view)
3021 return NULL;
3022
3023 /* initialize base object */
3024 view->base = *state;
3025 view->base.texture = NULL;
3026 view->base.reference.count = 1;
3027 view->base.context = ctx;
3028
3029 assert(texture);
3030 pipe_resource_reference(&view->base.texture, texture);
3031
3032 if (state->format == PIPE_FORMAT_X24S8_UINT ||
3033 state->format == PIPE_FORMAT_S8X24_UINT ||
3034 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
3035 state->format == PIPE_FORMAT_S8_UINT)
3036 view->is_stencil_sampler = true;
3037
3038 /* Buffer resource. */
3039 if (texture->target == PIPE_BUFFER) {
3040 si_make_buffer_descriptor(sctx->screen,
3041 (struct r600_resource *)texture,
3042 state->format,
3043 state->u.buf.offset,
3044 state->u.buf.size,
3045 view->state);
3046 return &view->base;
3047 }
3048
3049 state_swizzle[0] = state->swizzle_r;
3050 state_swizzle[1] = state->swizzle_g;
3051 state_swizzle[2] = state->swizzle_b;
3052 state_swizzle[3] = state->swizzle_a;
3053
3054 base_level = 0;
3055 first_level = state->u.tex.first_level;
3056 last_level = state->u.tex.last_level;
3057 width = width0;
3058 height = height0;
3059 depth = texture->depth0;
3060
3061 if (force_level) {
3062 assert(force_level == first_level &&
3063 force_level == last_level);
3064 base_level = force_level;
3065 first_level = 0;
3066 last_level = 0;
3067 width = u_minify(width, force_level);
3068 height = u_minify(height, force_level);
3069 depth = u_minify(depth, force_level);
3070 }
3071
3072 /* This is not needed if state trackers set last_layer correctly. */
3073 if (state->target == PIPE_TEXTURE_1D ||
3074 state->target == PIPE_TEXTURE_2D ||
3075 state->target == PIPE_TEXTURE_RECT ||
3076 state->target == PIPE_TEXTURE_CUBE)
3077 last_layer = state->u.tex.first_layer;
3078
3079 /* Texturing with separate depth and stencil. */
3080 pipe_format = state->format;
3081
3082 /* Depth/stencil texturing sometimes needs separate texture. */
3083 if (tmp->is_depth && !r600_can_sample_zs(tmp, view->is_stencil_sampler)) {
3084 if (!tmp->flushed_depth_texture &&
3085 !r600_init_flushed_depth_texture(ctx, texture, NULL)) {
3086 pipe_resource_reference(&view->base.texture, NULL);
3087 FREE(view);
3088 return NULL;
3089 }
3090
3091 assert(tmp->flushed_depth_texture);
3092
3093 /* Override format for the case where the flushed texture
3094 * contains only Z or only S.
3095 */
3096 if (tmp->flushed_depth_texture->resource.b.b.format != tmp->resource.b.b.format)
3097 pipe_format = tmp->flushed_depth_texture->resource.b.b.format;
3098
3099 tmp = tmp->flushed_depth_texture;
3100 }
3101
3102 surflevel = tmp->surface.level;
3103
3104 if (tmp->db_compatible) {
3105 if (!view->is_stencil_sampler)
3106 pipe_format = tmp->db_render_format;
3107
3108 switch (pipe_format) {
3109 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
3110 pipe_format = PIPE_FORMAT_Z32_FLOAT;
3111 break;
3112 case PIPE_FORMAT_X8Z24_UNORM:
3113 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3114 /* Z24 is always stored like this for DB
3115 * compatibility.
3116 */
3117 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
3118 break;
3119 case PIPE_FORMAT_X24S8_UINT:
3120 case PIPE_FORMAT_S8X24_UINT:
3121 case PIPE_FORMAT_X32_S8X24_UINT:
3122 pipe_format = PIPE_FORMAT_S8_UINT;
3123 surflevel = tmp->surface.stencil_level;
3124 break;
3125 default:;
3126 }
3127 }
3128
3129 vi_dcc_disable_if_incompatible_format(&sctx->b, texture,
3130 state->u.tex.first_level,
3131 state->format);
3132
3133 si_make_texture_descriptor(sctx->screen, tmp, true,
3134 state->target, pipe_format, state_swizzle,
3135 first_level, last_level,
3136 state->u.tex.first_layer, last_layer,
3137 width, height, depth,
3138 view->state, view->fmask_state);
3139
3140 view->base_level_info = &surflevel[base_level];
3141 view->base_level = base_level;
3142 view->block_width = util_format_get_blockwidth(pipe_format);
3143 return &view->base;
3144 }
3145
3146 static struct pipe_sampler_view *
3147 si_create_sampler_view(struct pipe_context *ctx,
3148 struct pipe_resource *texture,
3149 const struct pipe_sampler_view *state)
3150 {
3151 return si_create_sampler_view_custom(ctx, texture, state,
3152 texture ? texture->width0 : 0,
3153 texture ? texture->height0 : 0, 0);
3154 }
3155
3156 static void si_sampler_view_destroy(struct pipe_context *ctx,
3157 struct pipe_sampler_view *state)
3158 {
3159 struct si_sampler_view *view = (struct si_sampler_view *)state;
3160
3161 pipe_resource_reference(&state->texture, NULL);
3162 FREE(view);
3163 }
3164
3165 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
3166 {
3167 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
3168 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
3169 (linear_filter &&
3170 (wrap == PIPE_TEX_WRAP_CLAMP ||
3171 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
3172 }
3173
3174 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
3175 {
3176 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
3177 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
3178
3179 return (state->border_color.ui[0] || state->border_color.ui[1] ||
3180 state->border_color.ui[2] || state->border_color.ui[3]) &&
3181 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
3182 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
3183 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
3184 }
3185
3186 static void *si_create_sampler_state(struct pipe_context *ctx,
3187 const struct pipe_sampler_state *state)
3188 {
3189 struct si_context *sctx = (struct si_context *)ctx;
3190 struct r600_common_screen *rscreen = sctx->b.screen;
3191 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
3192 unsigned border_color_type, border_color_index = 0;
3193 unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
3194 : state->max_anisotropy;
3195 unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso);
3196
3197 if (!rstate) {
3198 return NULL;
3199 }
3200
3201 if (!sampler_state_needs_border_color(state))
3202 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3203 else if (state->border_color.f[0] == 0 &&
3204 state->border_color.f[1] == 0 &&
3205 state->border_color.f[2] == 0 &&
3206 state->border_color.f[3] == 0)
3207 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3208 else if (state->border_color.f[0] == 0 &&
3209 state->border_color.f[1] == 0 &&
3210 state->border_color.f[2] == 0 &&
3211 state->border_color.f[3] == 1)
3212 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3213 else if (state->border_color.f[0] == 1 &&
3214 state->border_color.f[1] == 1 &&
3215 state->border_color.f[2] == 1 &&
3216 state->border_color.f[3] == 1)
3217 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3218 else {
3219 int i;
3220
3221 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
3222
3223 /* Check if the border has been uploaded already. */
3224 for (i = 0; i < sctx->border_color_count; i++)
3225 if (memcmp(&sctx->border_color_table[i], &state->border_color,
3226 sizeof(state->border_color)) == 0)
3227 break;
3228
3229 if (i >= SI_MAX_BORDER_COLORS) {
3230 /* Getting 4096 unique border colors is very unlikely. */
3231 fprintf(stderr, "radeonsi: The border color table is full. "
3232 "Any new border colors will be just black. "
3233 "Please file a bug.\n");
3234 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3235 } else {
3236 if (i == sctx->border_color_count) {
3237 /* Upload a new border color. */
3238 memcpy(&sctx->border_color_table[i], &state->border_color,
3239 sizeof(state->border_color));
3240 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
3241 &state->border_color,
3242 sizeof(state->border_color));
3243 sctx->border_color_count++;
3244 }
3245
3246 border_color_index = i;
3247 }
3248 }
3249
3250 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
3251 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
3252 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
3253 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3254 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
3255 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
3256 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
3257 S_008F30_ANISO_BIAS(max_aniso_ratio) |
3258 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
3259 S_008F30_COMPAT_MODE(sctx->b.chip_class >= VI));
3260 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
3261 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)) |
3262 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
3263 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
3264 S_008F38_XY_MAG_FILTER(eg_tex_filter(state->mag_img_filter, max_aniso)) |
3265 S_008F38_XY_MIN_FILTER(eg_tex_filter(state->min_img_filter, max_aniso)) |
3266 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
3267 S_008F38_MIP_POINT_PRECLAMP(1) |
3268 S_008F38_DISABLE_LSB_CEIL(1) |
3269 S_008F38_FILTER_PREC_FIX(1) |
3270 S_008F38_ANISO_OVERRIDE(sctx->b.chip_class >= VI));
3271 rstate->val[3] = S_008F3C_BORDER_COLOR_PTR(border_color_index) |
3272 S_008F3C_BORDER_COLOR_TYPE(border_color_type);
3273 return rstate;
3274 }
3275
3276 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
3277 {
3278 struct si_context *sctx = (struct si_context *)ctx;
3279
3280 if (sctx->sample_mask.sample_mask == (uint16_t)sample_mask)
3281 return;
3282
3283 sctx->sample_mask.sample_mask = sample_mask;
3284 si_mark_atom_dirty(sctx, &sctx->sample_mask.atom);
3285 }
3286
3287 static void si_emit_sample_mask(struct si_context *sctx, struct r600_atom *atom)
3288 {
3289 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
3290 unsigned mask = sctx->sample_mask.sample_mask;
3291
3292 /* Needed for line and polygon smoothing as well as for the Polaris
3293 * small primitive filter. We expect the state tracker to take care of
3294 * this for us.
3295 */
3296 assert(mask == 0xffff || sctx->framebuffer.nr_samples > 1 ||
3297 (mask & 1 && sctx->blitter->running));
3298
3299 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3300 radeon_emit(cs, mask | (mask << 16));
3301 radeon_emit(cs, mask | (mask << 16));
3302 }
3303
3304 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
3305 {
3306 free(state);
3307 }
3308
3309 /*
3310 * Vertex elements & buffers
3311 */
3312
3313 static void *si_create_vertex_elements(struct pipe_context *ctx,
3314 unsigned count,
3315 const struct pipe_vertex_element *elements)
3316 {
3317 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
3318 int i;
3319
3320 assert(count <= SI_MAX_ATTRIBS);
3321 if (!v)
3322 return NULL;
3323
3324 v->count = count;
3325 for (i = 0; i < count; ++i) {
3326 const struct util_format_description *desc;
3327 unsigned data_format, num_format;
3328 int first_non_void;
3329
3330 desc = util_format_description(elements[i].src_format);
3331 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
3332 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
3333 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
3334
3335 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3336 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3337 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3338 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
3339 S_008F0C_NUM_FORMAT(num_format) |
3340 S_008F0C_DATA_FORMAT(data_format);
3341 v->format_size[i] = desc->block.bits / 8;
3342
3343 /* The hardware always treats the 2-bit alpha channel as
3344 * unsigned, so a shader workaround is needed.
3345 */
3346 if (data_format == V_008F0C_BUF_DATA_FORMAT_2_10_10_10) {
3347 if (num_format == V_008F0C_BUF_NUM_FORMAT_SNORM) {
3348 v->fix_fetch |= SI_FIX_FETCH_A2_SNORM << (2 * i);
3349 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SSCALED) {
3350 v->fix_fetch |= SI_FIX_FETCH_A2_SSCALED << (2 * i);
3351 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SINT) {
3352 /* This isn't actually used in OpenGL. */
3353 v->fix_fetch |= SI_FIX_FETCH_A2_SINT << (2 * i);
3354 }
3355 }
3356
3357 /* We work around the fact that 8_8_8 and 16_16_16 data formats
3358 * do not exist by using the corresponding 4-component formats.
3359 * This requires a fixup of the descriptor for bounds checks.
3360 */
3361 if (desc->block.bits == 3 * 8 ||
3362 desc->block.bits == 3 * 16) {
3363 v->fix_size3 |= (desc->block.bits / 24) << (2 * i);
3364 }
3365 }
3366 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
3367
3368 return v;
3369 }
3370
3371 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
3372 {
3373 struct si_context *sctx = (struct si_context *)ctx;
3374 struct si_vertex_element *v = (struct si_vertex_element*)state;
3375
3376 sctx->vertex_elements = v;
3377 sctx->vertex_buffers_dirty = true;
3378 sctx->do_update_shaders = true;
3379 }
3380
3381 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
3382 {
3383 struct si_context *sctx = (struct si_context *)ctx;
3384
3385 if (sctx->vertex_elements == state)
3386 sctx->vertex_elements = NULL;
3387 FREE(state);
3388 }
3389
3390 static void si_set_vertex_buffers(struct pipe_context *ctx,
3391 unsigned start_slot, unsigned count,
3392 const struct pipe_vertex_buffer *buffers)
3393 {
3394 struct si_context *sctx = (struct si_context *)ctx;
3395 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
3396 int i;
3397
3398 assert(start_slot + count <= ARRAY_SIZE(sctx->vertex_buffer));
3399
3400 if (buffers) {
3401 for (i = 0; i < count; i++) {
3402 const struct pipe_vertex_buffer *src = buffers + i;
3403 struct pipe_vertex_buffer *dsti = dst + i;
3404 struct pipe_resource *buf = src->buffer;
3405
3406 pipe_resource_reference(&dsti->buffer, buf);
3407 dsti->buffer_offset = src->buffer_offset;
3408 dsti->stride = src->stride;
3409 r600_context_add_resource_size(ctx, buf);
3410 if (buf)
3411 r600_resource(buf)->bind_history |= PIPE_BIND_VERTEX_BUFFER;
3412 }
3413 } else {
3414 for (i = 0; i < count; i++) {
3415 pipe_resource_reference(&dst[i].buffer, NULL);
3416 }
3417 }
3418 sctx->vertex_buffers_dirty = true;
3419 }
3420
3421 static void si_set_index_buffer(struct pipe_context *ctx,
3422 const struct pipe_index_buffer *ib)
3423 {
3424 struct si_context *sctx = (struct si_context *)ctx;
3425
3426 if (ib) {
3427 struct pipe_resource *buf = ib->buffer;
3428
3429 pipe_resource_reference(&sctx->index_buffer.buffer, buf);
3430 memcpy(&sctx->index_buffer, ib, sizeof(*ib));
3431 r600_context_add_resource_size(ctx, buf);
3432 if (buf)
3433 r600_resource(buf)->bind_history |= PIPE_BIND_INDEX_BUFFER;
3434 } else {
3435 pipe_resource_reference(&sctx->index_buffer.buffer, NULL);
3436 }
3437 }
3438
3439 /*
3440 * Misc
3441 */
3442
3443 static void si_set_tess_state(struct pipe_context *ctx,
3444 const float default_outer_level[4],
3445 const float default_inner_level[2])
3446 {
3447 struct si_context *sctx = (struct si_context *)ctx;
3448 struct pipe_constant_buffer cb;
3449 float array[8];
3450
3451 memcpy(array, default_outer_level, sizeof(float) * 4);
3452 memcpy(array+4, default_inner_level, sizeof(float) * 2);
3453
3454 cb.buffer = NULL;
3455 cb.user_buffer = NULL;
3456 cb.buffer_size = sizeof(array);
3457
3458 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
3459 (void*)array, sizeof(array),
3460 &cb.buffer_offset);
3461
3462 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
3463 pipe_resource_reference(&cb.buffer, NULL);
3464 }
3465
3466 static void si_texture_barrier(struct pipe_context *ctx)
3467 {
3468 struct si_context *sctx = (struct si_context *)ctx;
3469
3470 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
3471 SI_CONTEXT_INV_GLOBAL_L2 |
3472 SI_CONTEXT_FLUSH_AND_INV_CB |
3473 SI_CONTEXT_CS_PARTIAL_FLUSH;
3474 }
3475
3476 /* This only ensures coherency for shader image/buffer stores. */
3477 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
3478 {
3479 struct si_context *sctx = (struct si_context *)ctx;
3480
3481 /* Subsequent commands must wait for all shader invocations to
3482 * complete. */
3483 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
3484 SI_CONTEXT_CS_PARTIAL_FLUSH;
3485
3486 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
3487 sctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 |
3488 SI_CONTEXT_INV_VMEM_L1;
3489
3490 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
3491 PIPE_BARRIER_SHADER_BUFFER |
3492 PIPE_BARRIER_TEXTURE |
3493 PIPE_BARRIER_IMAGE |
3494 PIPE_BARRIER_STREAMOUT_BUFFER |
3495 PIPE_BARRIER_GLOBAL_BUFFER)) {
3496 /* As far as I can tell, L1 contents are written back to L2
3497 * automatically at end of shader, but the contents of other
3498 * L1 caches might still be stale. */
3499 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
3500 }
3501
3502 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
3503 /* Indices are read through TC L2 since VI.
3504 * L1 isn't used.
3505 */
3506 if (sctx->screen->b.chip_class <= CIK)
3507 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
3508 }
3509
3510 if (flags & PIPE_BARRIER_FRAMEBUFFER)
3511 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER;
3512
3513 if (flags & (PIPE_BARRIER_FRAMEBUFFER |
3514 PIPE_BARRIER_INDIRECT_BUFFER))
3515 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
3516 }
3517
3518 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
3519 {
3520 struct pipe_blend_state blend;
3521
3522 memset(&blend, 0, sizeof(blend));
3523 blend.independent_blend_enable = true;
3524 blend.rt[0].colormask = 0xf;
3525 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
3526 }
3527
3528 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
3529 bool include_draw_vbo)
3530 {
3531 si_need_cs_space((struct si_context*)ctx);
3532 }
3533
3534 static void si_init_config(struct si_context *sctx);
3535
3536 void si_init_state_functions(struct si_context *sctx)
3537 {
3538 si_init_external_atom(sctx, &sctx->b.render_cond_atom, &sctx->atoms.s.render_cond);
3539 si_init_external_atom(sctx, &sctx->b.streamout.begin_atom, &sctx->atoms.s.streamout_begin);
3540 si_init_external_atom(sctx, &sctx->b.streamout.enable_atom, &sctx->atoms.s.streamout_enable);
3541 si_init_external_atom(sctx, &sctx->b.scissors.atom, &sctx->atoms.s.scissors);
3542 si_init_external_atom(sctx, &sctx->b.viewports.atom, &sctx->atoms.s.viewports);
3543
3544 si_init_atom(sctx, &sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state);
3545 si_init_atom(sctx, &sctx->msaa_sample_locs.atom, &sctx->atoms.s.msaa_sample_locs, si_emit_msaa_sample_locs);
3546 si_init_atom(sctx, &sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state);
3547 si_init_atom(sctx, &sctx->msaa_config, &sctx->atoms.s.msaa_config, si_emit_msaa_config);
3548 si_init_atom(sctx, &sctx->sample_mask.atom, &sctx->atoms.s.sample_mask, si_emit_sample_mask);
3549 si_init_atom(sctx, &sctx->cb_render_state, &sctx->atoms.s.cb_render_state, si_emit_cb_render_state);
3550 si_init_atom(sctx, &sctx->blend_color.atom, &sctx->atoms.s.blend_color, si_emit_blend_color);
3551 si_init_atom(sctx, &sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs);
3552 si_init_atom(sctx, &sctx->clip_state.atom, &sctx->atoms.s.clip_state, si_emit_clip_state);
3553 si_init_atom(sctx, &sctx->stencil_ref.atom, &sctx->atoms.s.stencil_ref, si_emit_stencil_ref);
3554
3555 sctx->b.b.create_blend_state = si_create_blend_state;
3556 sctx->b.b.bind_blend_state = si_bind_blend_state;
3557 sctx->b.b.delete_blend_state = si_delete_blend_state;
3558 sctx->b.b.set_blend_color = si_set_blend_color;
3559
3560 sctx->b.b.create_rasterizer_state = si_create_rs_state;
3561 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
3562 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
3563
3564 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
3565 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
3566 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
3567
3568 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
3569 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
3570 sctx->custom_blend_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
3571 sctx->custom_blend_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
3572 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
3573
3574 sctx->b.b.set_clip_state = si_set_clip_state;
3575 sctx->b.b.set_stencil_ref = si_set_stencil_ref;
3576
3577 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
3578 sctx->b.b.get_sample_position = cayman_get_sample_position;
3579
3580 sctx->b.b.create_sampler_state = si_create_sampler_state;
3581 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
3582
3583 sctx->b.b.create_sampler_view = si_create_sampler_view;
3584 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
3585
3586 sctx->b.b.set_sample_mask = si_set_sample_mask;
3587
3588 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
3589 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
3590 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
3591 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
3592 sctx->b.b.set_index_buffer = si_set_index_buffer;
3593
3594 sctx->b.b.texture_barrier = si_texture_barrier;
3595 sctx->b.b.memory_barrier = si_memory_barrier;
3596 sctx->b.b.set_min_samples = si_set_min_samples;
3597 sctx->b.b.set_tess_state = si_set_tess_state;
3598
3599 sctx->b.b.set_active_query_state = si_set_active_query_state;
3600 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
3601 sctx->b.save_qbo_state = si_save_qbo_state;
3602 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
3603
3604 sctx->b.b.draw_vbo = si_draw_vbo;
3605
3606 si_init_config(sctx);
3607 }
3608
3609 static uint32_t si_get_bo_metadata_word1(struct r600_common_screen *rscreen)
3610 {
3611 return (ATI_VENDOR_ID << 16) | rscreen->info.pci_id;
3612 }
3613
3614 static void si_query_opaque_metadata(struct r600_common_screen *rscreen,
3615 struct r600_texture *rtex,
3616 struct radeon_bo_metadata *md)
3617 {
3618 struct si_screen *sscreen = (struct si_screen*)rscreen;
3619 struct pipe_resource *res = &rtex->resource.b.b;
3620 static const unsigned char swizzle[] = {
3621 PIPE_SWIZZLE_X,
3622 PIPE_SWIZZLE_Y,
3623 PIPE_SWIZZLE_Z,
3624 PIPE_SWIZZLE_W
3625 };
3626 uint32_t desc[8], i;
3627 bool is_array = util_resource_is_array_texture(res);
3628
3629 /* DRM 2.x.x doesn't support this. */
3630 if (rscreen->info.drm_major != 3)
3631 return;
3632
3633 assert(rtex->dcc_separate_buffer == NULL);
3634 assert(rtex->fmask.size == 0);
3635
3636 /* Metadata image format format version 1:
3637 * [0] = 1 (metadata format identifier)
3638 * [1] = (VENDOR_ID << 16) | PCI_ID
3639 * [2:9] = image descriptor for the whole resource
3640 * [2] is always 0, because the base address is cleared
3641 * [9] is the DCC offset bits [39:8] from the beginning of
3642 * the buffer
3643 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
3644 */
3645
3646 md->metadata[0] = 1; /* metadata image format version 1 */
3647
3648 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
3649 md->metadata[1] = si_get_bo_metadata_word1(rscreen);
3650
3651 si_make_texture_descriptor(sscreen, rtex, true,
3652 res->target, res->format,
3653 swizzle, 0, res->last_level, 0,
3654 is_array ? res->array_size - 1 : 0,
3655 res->width0, res->height0, res->depth0,
3656 desc, NULL);
3657
3658 si_set_mutable_tex_desc_fields(rtex, &rtex->surface.level[0], 0, 0,
3659 rtex->surface.blk_w, false, desc);
3660
3661 /* Clear the base address and set the relative DCC offset. */
3662 desc[0] = 0;
3663 desc[1] &= C_008F14_BASE_ADDRESS_HI;
3664 desc[7] = rtex->dcc_offset >> 8;
3665
3666 /* Dwords [2:9] contain the image descriptor. */
3667 memcpy(&md->metadata[2], desc, sizeof(desc));
3668
3669 /* Dwords [10:..] contain the mipmap level offsets. */
3670 for (i = 0; i <= res->last_level; i++)
3671 md->metadata[10+i] = rtex->surface.level[i].offset >> 8;
3672
3673 md->size_metadata = (11 + res->last_level) * 4;
3674 }
3675
3676 static void si_apply_opaque_metadata(struct r600_common_screen *rscreen,
3677 struct r600_texture *rtex,
3678 struct radeon_bo_metadata *md)
3679 {
3680 uint32_t *desc = &md->metadata[2];
3681
3682 if (rscreen->chip_class < VI)
3683 return;
3684
3685 /* Return if DCC is enabled. The texture should be set up with it
3686 * already.
3687 */
3688 if (md->size_metadata >= 11 * 4 &&
3689 md->metadata[0] != 0 &&
3690 md->metadata[1] == si_get_bo_metadata_word1(rscreen) &&
3691 G_008F28_COMPRESSION_EN(desc[6])) {
3692 assert(rtex->dcc_offset == ((uint64_t)desc[7] << 8));
3693 return;
3694 }
3695
3696 /* Disable DCC. These are always set by texture_from_handle and must
3697 * be cleared here.
3698 */
3699 rtex->dcc_offset = 0;
3700 }
3701
3702 void si_init_screen_state_functions(struct si_screen *sscreen)
3703 {
3704 sscreen->b.b.is_format_supported = si_is_format_supported;
3705 sscreen->b.query_opaque_metadata = si_query_opaque_metadata;
3706 sscreen->b.apply_opaque_metadata = si_apply_opaque_metadata;
3707 }
3708
3709 static void
3710 si_write_harvested_raster_configs(struct si_context *sctx,
3711 struct si_pm4_state *pm4,
3712 unsigned raster_config,
3713 unsigned raster_config_1)
3714 {
3715 unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1);
3716 unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1);
3717 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
3718 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
3719 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
3720 unsigned rb_per_se = num_rb / num_se;
3721 unsigned se_mask[4];
3722 unsigned se;
3723
3724 se_mask[0] = ((1 << rb_per_se) - 1);
3725 se_mask[1] = (se_mask[0] << rb_per_se);
3726 se_mask[2] = (se_mask[1] << rb_per_se);
3727 se_mask[3] = (se_mask[2] << rb_per_se);
3728
3729 se_mask[0] &= rb_mask;
3730 se_mask[1] &= rb_mask;
3731 se_mask[2] &= rb_mask;
3732 se_mask[3] &= rb_mask;
3733
3734 assert(num_se == 1 || num_se == 2 || num_se == 4);
3735 assert(sh_per_se == 1 || sh_per_se == 2);
3736 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
3737
3738 /* XXX: I can't figure out what the *_XSEL and *_YSEL
3739 * fields are for, so I'm leaving them as their default
3740 * values. */
3741
3742 for (se = 0; se < num_se; se++) {
3743 unsigned raster_config_se = raster_config;
3744 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
3745 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
3746 int idx = (se / 2) * 2;
3747
3748 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
3749 raster_config_se &= C_028350_SE_MAP;
3750
3751 if (!se_mask[idx]) {
3752 raster_config_se |=
3753 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
3754 } else {
3755 raster_config_se |=
3756 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
3757 }
3758 }
3759
3760 pkr0_mask &= rb_mask;
3761 pkr1_mask &= rb_mask;
3762 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
3763 raster_config_se &= C_028350_PKR_MAP;
3764
3765 if (!pkr0_mask) {
3766 raster_config_se |=
3767 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
3768 } else {
3769 raster_config_se |=
3770 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
3771 }
3772 }
3773
3774 if (rb_per_se >= 2) {
3775 unsigned rb0_mask = 1 << (se * rb_per_se);
3776 unsigned rb1_mask = rb0_mask << 1;
3777
3778 rb0_mask &= rb_mask;
3779 rb1_mask &= rb_mask;
3780 if (!rb0_mask || !rb1_mask) {
3781 raster_config_se &= C_028350_RB_MAP_PKR0;
3782
3783 if (!rb0_mask) {
3784 raster_config_se |=
3785 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
3786 } else {
3787 raster_config_se |=
3788 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
3789 }
3790 }
3791
3792 if (rb_per_se > 2) {
3793 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
3794 rb1_mask = rb0_mask << 1;
3795 rb0_mask &= rb_mask;
3796 rb1_mask &= rb_mask;
3797 if (!rb0_mask || !rb1_mask) {
3798 raster_config_se &= C_028350_RB_MAP_PKR1;
3799
3800 if (!rb0_mask) {
3801 raster_config_se |=
3802 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
3803 } else {
3804 raster_config_se |=
3805 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
3806 }
3807 }
3808 }
3809 }
3810
3811 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
3812 if (sctx->b.chip_class < CIK)
3813 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3814 SE_INDEX(se) | SH_BROADCAST_WRITES |
3815 INSTANCE_BROADCAST_WRITES);
3816 else
3817 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
3818 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
3819 S_030800_INSTANCE_BROADCAST_WRITES(1));
3820 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
3821 }
3822
3823 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
3824 if (sctx->b.chip_class < CIK)
3825 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3826 SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
3827 INSTANCE_BROADCAST_WRITES);
3828 else {
3829 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
3830 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
3831 S_030800_INSTANCE_BROADCAST_WRITES(1));
3832
3833 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
3834 (!se_mask[2] && !se_mask[3]))) {
3835 raster_config_1 &= C_028354_SE_PAIR_MAP;
3836
3837 if (!se_mask[0] && !se_mask[1]) {
3838 raster_config_1 |=
3839 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
3840 } else {
3841 raster_config_1 |=
3842 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
3843 }
3844 }
3845
3846 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
3847 }
3848 }
3849
3850 static void si_init_config(struct si_context *sctx)
3851 {
3852 struct si_screen *sscreen = sctx->screen;
3853 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
3854 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
3855 unsigned raster_config, raster_config_1;
3856 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
3857 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3858
3859 if (!pm4)
3860 return;
3861
3862 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
3863 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
3864 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
3865 si_pm4_cmd_end(pm4, false);
3866
3867 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
3868 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
3869
3870 /* FIXME calculate these values somehow ??? */
3871 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
3872 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
3873 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
3874
3875 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
3876 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3877
3878 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
3879 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
3880 if (sctx->b.chip_class < CIK)
3881 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
3882 S_008A14_CLIP_VTX_REORDER_ENA(1));
3883
3884 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
3885 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
3886
3887 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
3888
3889 switch (sctx->screen->b.family) {
3890 case CHIP_TAHITI:
3891 case CHIP_PITCAIRN:
3892 raster_config = 0x2a00126a;
3893 raster_config_1 = 0x00000000;
3894 break;
3895 case CHIP_VERDE:
3896 raster_config = 0x0000124a;
3897 raster_config_1 = 0x00000000;
3898 break;
3899 case CHIP_OLAND:
3900 raster_config = 0x00000082;
3901 raster_config_1 = 0x00000000;
3902 break;
3903 case CHIP_HAINAN:
3904 raster_config = 0x00000000;
3905 raster_config_1 = 0x00000000;
3906 break;
3907 case CHIP_BONAIRE:
3908 raster_config = 0x16000012;
3909 raster_config_1 = 0x00000000;
3910 break;
3911 case CHIP_HAWAII:
3912 raster_config = 0x3a00161a;
3913 raster_config_1 = 0x0000002e;
3914 break;
3915 case CHIP_FIJI:
3916 if (sscreen->b.info.cik_macrotile_mode_array[0] == 0x000000e8) {
3917 /* old kernels with old tiling config */
3918 raster_config = 0x16000012;
3919 raster_config_1 = 0x0000002a;
3920 } else {
3921 raster_config = 0x3a00161a;
3922 raster_config_1 = 0x0000002e;
3923 }
3924 break;
3925 case CHIP_POLARIS10:
3926 raster_config = 0x16000012;
3927 raster_config_1 = 0x0000002a;
3928 break;
3929 case CHIP_POLARIS11:
3930 raster_config = 0x16000012;
3931 raster_config_1 = 0x00000000;
3932 break;
3933 case CHIP_TONGA:
3934 raster_config = 0x16000012;
3935 raster_config_1 = 0x0000002a;
3936 break;
3937 case CHIP_ICELAND:
3938 if (num_rb == 1)
3939 raster_config = 0x00000000;
3940 else
3941 raster_config = 0x00000002;
3942 raster_config_1 = 0x00000000;
3943 break;
3944 case CHIP_CARRIZO:
3945 raster_config = 0x00000002;
3946 raster_config_1 = 0x00000000;
3947 break;
3948 case CHIP_KAVERI:
3949 /* KV should be 0x00000002, but that causes problems with radeon */
3950 raster_config = 0x00000000; /* 0x00000002 */
3951 raster_config_1 = 0x00000000;
3952 break;
3953 case CHIP_KABINI:
3954 case CHIP_MULLINS:
3955 case CHIP_STONEY:
3956 raster_config = 0x00000000;
3957 raster_config_1 = 0x00000000;
3958 break;
3959 default:
3960 fprintf(stderr,
3961 "radeonsi: Unknown GPU, using 0 for raster_config\n");
3962 raster_config = 0x00000000;
3963 raster_config_1 = 0x00000000;
3964 break;
3965 }
3966
3967 /* Always use the default config when all backends are enabled
3968 * (or when we failed to determine the enabled backends).
3969 */
3970 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
3971 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
3972 raster_config);
3973 if (sctx->b.chip_class >= CIK)
3974 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
3975 raster_config_1);
3976 } else {
3977 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
3978 }
3979
3980 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
3981 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
3982 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
3983 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
3984 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
3985 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
3986 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
3987
3988 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
3989 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
3990 S_028230_ER_TRI(0xA) |
3991 S_028230_ER_POINT(0xA) |
3992 S_028230_ER_RECT(0xA) |
3993 /* Required by DX10_DIAMOND_TEST_ENA: */
3994 S_028230_ER_LINE_LR(0x1A) |
3995 S_028230_ER_LINE_RL(0x26) |
3996 S_028230_ER_LINE_TB(0xA) |
3997 S_028230_ER_LINE_BT(0xA));
3998 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
3999 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
4000 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
4001 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
4002 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
4003 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
4004 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 0);
4005
4006 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
4007 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
4008 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
4009
4010 if (sctx->b.chip_class >= CIK) {
4011 /* If this is 0, Bonaire can hang even if GS isn't being used.
4012 * Other chips are unaffected. These are suboptimal values,
4013 * but we don't use on-chip GS.
4014 */
4015 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
4016 S_028A44_ES_VERTS_PER_SUBGRP(64) |
4017 S_028A44_GS_PRIMS_PER_SUBGRP(4));
4018
4019 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff));
4020 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
4021 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xffff));
4022 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
4023
4024 if (sscreen->b.info.num_good_compute_units /
4025 (sscreen->b.info.max_se * sscreen->b.info.max_sh_per_se) <= 4) {
4026 /* Too few available compute units per SH. Disallowing
4027 * VS to run on CU0 could hurt us more than late VS
4028 * allocation would help.
4029 *
4030 * LATE_ALLOC_VS = 2 is the highest safe number.
4031 */
4032 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
4033 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
4034 } else {
4035 /* Set LATE_ALLOC_VS == 31. It should be less than
4036 * the number of scratch waves. Limitations:
4037 * - VS can't execute on CU0.
4038 * - If HS writes outputs to LDS, LS can't execute on CU0.
4039 */
4040 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xfffe));
4041 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
4042 }
4043
4044 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
4045 }
4046
4047 if (sctx->b.chip_class >= VI) {
4048 unsigned vgt_tess_distribution;
4049
4050 si_pm4_set_reg(pm4, R_028424_CB_DCC_CONTROL,
4051 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
4052 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
4053 if (sctx->b.family < CHIP_POLARIS10)
4054 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
4055 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
4056
4057 vgt_tess_distribution =
4058 S_028B50_ACCUM_ISOLINE(32) |
4059 S_028B50_ACCUM_TRI(11) |
4060 S_028B50_ACCUM_QUAD(11) |
4061 S_028B50_DONUT_SPLIT(16);
4062
4063 /* Testing with Unigine Heaven extreme tesselation yielded best results
4064 * with TRAP_SPLIT = 3.
4065 */
4066 if (sctx->b.family == CHIP_FIJI ||
4067 sctx->b.family >= CHIP_POLARIS10)
4068 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
4069
4070 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution);
4071 } else {
4072 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
4073 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
4074 }
4075
4076 if (sctx->b.family == CHIP_STONEY)
4077 si_pm4_set_reg(pm4, R_028C40_PA_SC_SHADER_CONTROL, 0);
4078
4079 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
4080 if (sctx->b.chip_class >= CIK)
4081 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, border_color_va >> 40);
4082 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
4083 RADEON_PRIO_BORDER_COLORS);
4084
4085 si_pm4_upload_indirect_buffer(sctx, pm4);
4086 sctx->init_config = pm4;
4087 }