projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radeonsi: support thread-safe shaders shared by multiple contexts
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "si_shader.h"
29 #include "sid.h"
30 #include "radeon/r600_cs.h"
31
32 #include "util/u_dual_blend.h"
33 #include "util/u_format.h"
34 #include "util/u_format_s3tc.h"
35 #include "util/u_memory.h"
36 #include "util/u_pstipple.h"
37
38 /* Initialize an external atom (owned by ../radeon). */
39 static void
40 si_init_external_atom(struct si_context *sctx, struct r600_atom *atom,
41 struct r600_atom **list_elem)
42 {
43 atom->id = list_elem - sctx->atoms.array + 1;
44 *list_elem = atom;
45 }
46
47 /* Initialize an atom owned by radeonsi. */
48 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
49 struct r600_atom **list_elem,
50 void (*emit_func)(struct si_context *ctx, struct r600_atom *state))
51 {
52 atom->emit = (void*)emit_func;
53 atom->id = list_elem - sctx->atoms.array + 1; /* index+1 in the atom array */
54 *list_elem = atom;
55 }
56
57 unsigned si_array_mode(unsigned mode)
58 {
59 switch (mode) {
60 case RADEON_SURF_MODE_LINEAR_ALIGNED:
61 return V_009910_ARRAY_LINEAR_ALIGNED;
62 case RADEON_SURF_MODE_1D:
63 return V_009910_ARRAY_1D_TILED_THIN1;
64 case RADEON_SURF_MODE_2D:
65 return V_009910_ARRAY_2D_TILED_THIN1;
66 default:
67 case RADEON_SURF_MODE_LINEAR:
68 return V_009910_ARRAY_LINEAR_GENERAL;
69 }
70 }
71
72 uint32_t si_num_banks(struct si_screen *sscreen, struct r600_texture *tex)
73 {
74 if (sscreen->b.chip_class >= CIK &&
75 sscreen->b.info.cik_macrotile_mode_array_valid) {
76 unsigned index, tileb;
77
78 tileb = 8 * 8 * tex->surface.bpe;
79 tileb = MIN2(tex->surface.tile_split, tileb);
80
81 for (index = 0; tileb > 64; index++) {
82 tileb >>= 1;
83 }
84 assert(index < 16);
85
86 return (sscreen->b.info.cik_macrotile_mode_array[index] >> 6) & 0x3;
87 }
88
89 if (sscreen->b.chip_class == SI &&
90 sscreen->b.info.si_tile_mode_array_valid) {
91 /* Don't use stencil_tiling_index, because num_banks is always
92 * read from the depth mode. */
93 unsigned tile_mode_index = tex->surface.tiling_index[0];
94 assert(tile_mode_index < 32);
95
96 return G_009910_NUM_BANKS(sscreen->b.info.si_tile_mode_array[tile_mode_index]);
97 }
98
99 /* The old way. */
100 switch (sscreen->b.tiling_info.num_banks) {
101 case 2:
102 return V_02803C_ADDR_SURF_2_BANK;
103 case 4:
104 return V_02803C_ADDR_SURF_4_BANK;
105 case 8:
106 default:
107 return V_02803C_ADDR_SURF_8_BANK;
108 case 16:
109 return V_02803C_ADDR_SURF_16_BANK;
110 }
111 }
112
113 unsigned cik_tile_split(unsigned tile_split)
114 {
115 switch (tile_split) {
116 case 64:
117 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_64B;
118 break;
119 case 128:
120 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_128B;
121 break;
122 case 256:
123 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_256B;
124 break;
125 case 512:
126 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_512B;
127 break;
128 default:
129 case 1024:
130 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_1KB;
131 break;
132 case 2048:
133 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_2KB;
134 break;
135 case 4096:
136 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_4KB;
137 break;
138 }
139 return tile_split;
140 }
141
142 unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect)
143 {
144 switch (macro_tile_aspect) {
145 default:
146 case 1:
147 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_1;
148 break;
149 case 2:
150 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_2;
151 break;
152 case 4:
153 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_4;
154 break;
155 case 8:
156 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_8;
157 break;
158 }
159 return macro_tile_aspect;
160 }
161
162 unsigned cik_bank_wh(unsigned bankwh)
163 {
164 switch (bankwh) {
165 default:
166 case 1:
167 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_1;
168 break;
169 case 2:
170 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_2;
171 break;
172 case 4:
173 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_4;
174 break;
175 case 8:
176 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_8;
177 break;
178 }
179 return bankwh;
180 }
181
182 unsigned cik_db_pipe_config(struct si_screen *sscreen, unsigned tile_mode)
183 {
184 if (sscreen->b.info.si_tile_mode_array_valid) {
185 uint32_t gb_tile_mode = sscreen->b.info.si_tile_mode_array[tile_mode];
186
187 return G_009910_PIPE_CONFIG(gb_tile_mode);
188 }
189
190 /* This is probably broken for a lot of chips, but it's only used
191 * if the kernel cannot return the tile mode array for CIK. */
192 switch (sscreen->b.info.r600_num_tile_pipes) {
193 case 16:
194 return V_02803C_X_ADDR_SURF_P16_32X32_16X16;
195 case 8:
196 return V_02803C_X_ADDR_SURF_P8_32X32_16X16;
197 case 4:
198 default:
199 if (sscreen->b.info.r600_num_backends == 4)
200 return V_02803C_X_ADDR_SURF_P4_16X16;
201 else
202 return V_02803C_X_ADDR_SURF_P4_8X16;
203 case 2:
204 return V_02803C_ADDR_SURF_P2;
205 }
206 }
207
208 static unsigned si_map_swizzle(unsigned swizzle)
209 {
210 switch (swizzle) {
211 case UTIL_FORMAT_SWIZZLE_Y:
212 return V_008F0C_SQ_SEL_Y;
213 case UTIL_FORMAT_SWIZZLE_Z:
214 return V_008F0C_SQ_SEL_Z;
215 case UTIL_FORMAT_SWIZZLE_W:
216 return V_008F0C_SQ_SEL_W;
217 case UTIL_FORMAT_SWIZZLE_0:
218 return V_008F0C_SQ_SEL_0;
219 case UTIL_FORMAT_SWIZZLE_1:
220 return V_008F0C_SQ_SEL_1;
221 default: /* UTIL_FORMAT_SWIZZLE_X */
222 return V_008F0C_SQ_SEL_X;
223 }
224 }
225
226 static uint32_t S_FIXED(float value, uint32_t frac_bits)
227 {
228 return value * (1 << frac_bits);
229 }
230
231 /* 12.4 fixed-point */
232 static unsigned si_pack_float_12p4(float x)
233 {
234 return x <= 0 ? 0 :
235 x >= 4096 ? 0xffff : x * 16;
236 }
237
238 /*
239 * Inferred framebuffer and blender state.
240 *
241 * One of the reasons this must be derived from the framebuffer state is that:
242 * - The blend state mask is 0xf most of the time.
243 * - The COLOR1 format isn't INVALID because of possible dual-source blending,
244 * so COLOR1 is enabled pretty much all the time.
245 * So CB_TARGET_MASK is the only register that can disable COLOR1.
246 *
247 * Another reason is to avoid a hang with dual source blending.
248 */
249 static void si_emit_cb_target_mask(struct si_context *sctx, struct r600_atom *atom)
250 {
251 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
252 struct si_state_blend *blend = sctx->queued.named.blend;
253 uint32_t mask = 0, i;
254
255 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++)
256 if (sctx->framebuffer.state.cbufs[i])
257 mask |= 0xf << (4*i);
258
259 if (blend)
260 mask &= blend->cb_target_mask;
261
262 /* Avoid a hang that happens when dual source blending is enabled
263 * but there is not enough color outputs. This is undefined behavior,
264 * so disable color writes completely.
265 *
266 * Reproducible with Unigine Heaven 4.0 and drirc missing.
267 */
268 if (blend->dual_src_blend &&
269 (sctx->ps_shader.cso->ps_colors_written & 0x3) != 0x3)
270 mask = 0;
271
272 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, mask);
273 }
274
275 /*
276 * Blender functions
277 */
278
279 static uint32_t si_translate_blend_function(int blend_func)
280 {
281 switch (blend_func) {
282 case PIPE_BLEND_ADD:
283 return V_028780_COMB_DST_PLUS_SRC;
284 case PIPE_BLEND_SUBTRACT:
285 return V_028780_COMB_SRC_MINUS_DST;
286 case PIPE_BLEND_REVERSE_SUBTRACT:
287 return V_028780_COMB_DST_MINUS_SRC;
288 case PIPE_BLEND_MIN:
289 return V_028780_COMB_MIN_DST_SRC;
290 case PIPE_BLEND_MAX:
291 return V_028780_COMB_MAX_DST_SRC;
292 default:
293 R600_ERR("Unknown blend function %d\n", blend_func);
294 assert(0);
295 break;
296 }
297 return 0;
298 }
299
300 static uint32_t si_translate_blend_factor(int blend_fact)
301 {
302 switch (blend_fact) {
303 case PIPE_BLENDFACTOR_ONE:
304 return V_028780_BLEND_ONE;
305 case PIPE_BLENDFACTOR_SRC_COLOR:
306 return V_028780_BLEND_SRC_COLOR;
307 case PIPE_BLENDFACTOR_SRC_ALPHA:
308 return V_028780_BLEND_SRC_ALPHA;
309 case PIPE_BLENDFACTOR_DST_ALPHA:
310 return V_028780_BLEND_DST_ALPHA;
311 case PIPE_BLENDFACTOR_DST_COLOR:
312 return V_028780_BLEND_DST_COLOR;
313 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
314 return V_028780_BLEND_SRC_ALPHA_SATURATE;
315 case PIPE_BLENDFACTOR_CONST_COLOR:
316 return V_028780_BLEND_CONSTANT_COLOR;
317 case PIPE_BLENDFACTOR_CONST_ALPHA:
318 return V_028780_BLEND_CONSTANT_ALPHA;
319 case PIPE_BLENDFACTOR_ZERO:
320 return V_028780_BLEND_ZERO;
321 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
322 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
323 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
324 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
325 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
326 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
327 case PIPE_BLENDFACTOR_INV_DST_COLOR:
328 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
329 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
330 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
331 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
332 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
333 case PIPE_BLENDFACTOR_SRC1_COLOR:
334 return V_028780_BLEND_SRC1_COLOR;
335 case PIPE_BLENDFACTOR_SRC1_ALPHA:
336 return V_028780_BLEND_SRC1_ALPHA;
337 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
338 return V_028780_BLEND_INV_SRC1_COLOR;
339 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
340 return V_028780_BLEND_INV_SRC1_ALPHA;
341 default:
342 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
343 assert(0);
344 break;
345 }
346 return 0;
347 }
348
349 static void *si_create_blend_state_mode(struct pipe_context *ctx,
350 const struct pipe_blend_state *state,
351 unsigned mode)
352 {
353 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
354 struct si_pm4_state *pm4 = &blend->pm4;
355
356 uint32_t color_control = 0;
357
358 if (blend == NULL)
359 return NULL;
360
361 blend->alpha_to_one = state->alpha_to_one;
362 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
363
364 if (state->logicop_enable) {
365 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
366 } else {
367 color_control |= S_028808_ROP3(0xcc);
368 }
369
370 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
371 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
372 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
373 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
374 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
375 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
376
377 blend->cb_target_mask = 0;
378 for (int i = 0; i < 8; i++) {
379 /* state->rt entries > 0 only written if independent blending */
380 const int j = state->independent_blend_enable ? i : 0;
381
382 unsigned eqRGB = state->rt[j].rgb_func;
383 unsigned srcRGB = state->rt[j].rgb_src_factor;
384 unsigned dstRGB = state->rt[j].rgb_dst_factor;
385 unsigned eqA = state->rt[j].alpha_func;
386 unsigned srcA = state->rt[j].alpha_src_factor;
387 unsigned dstA = state->rt[j].alpha_dst_factor;
388
389 unsigned blend_cntl = 0;
390
391 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
392 blend->cb_target_mask |= state->rt[j].colormask << (4 * i);
393
394 if (!state->rt[j].blend_enable) {
395 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
396 continue;
397 }
398
399 blend_cntl |= S_028780_ENABLE(1);
400 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
401 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
402 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
403
404 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
405 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
406 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
407 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
408 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
409 }
410 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
411 }
412
413 if (blend->cb_target_mask) {
414 color_control |= S_028808_MODE(mode);
415 } else {
416 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
417 }
418 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
419
420 return blend;
421 }
422
423 static void *si_create_blend_state(struct pipe_context *ctx,
424 const struct pipe_blend_state *state)
425 {
426 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
427 }
428
429 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
430 {
431 struct si_context *sctx = (struct si_context *)ctx;
432 si_pm4_bind_state(sctx, blend, (struct si_state_blend *)state);
433 si_mark_atom_dirty(sctx, &sctx->cb_target_mask);
434 }
435
436 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
437 {
438 struct si_context *sctx = (struct si_context *)ctx;
439 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
440 }
441
442 static void si_set_blend_color(struct pipe_context *ctx,
443 const struct pipe_blend_color *state)
444 {
445 struct si_context *sctx = (struct si_context *)ctx;
446
447 if (memcmp(&sctx->blend_color.state, state, sizeof(*state)) == 0)
448 return;
449
450 sctx->blend_color.state = *state;
451 si_mark_atom_dirty(sctx, &sctx->blend_color.atom);
452 }
453
454 static void si_emit_blend_color(struct si_context *sctx, struct r600_atom *atom)
455 {
456 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
457
458 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
459 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
460 }
461
462 /*
463 * Clipping, scissors and viewport
464 */
465
466 static void si_set_clip_state(struct pipe_context *ctx,
467 const struct pipe_clip_state *state)
468 {
469 struct si_context *sctx = (struct si_context *)ctx;
470 struct pipe_constant_buffer cb;
471
472 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
473 return;
474
475 sctx->clip_state.state = *state;
476 si_mark_atom_dirty(sctx, &sctx->clip_state.atom);
477
478 cb.buffer = NULL;
479 cb.user_buffer = state->ucp;
480 cb.buffer_offset = 0;
481 cb.buffer_size = 4*4*8;
482 ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, SI_DRIVER_STATE_CONST_BUF, &cb);
483 pipe_resource_reference(&cb.buffer, NULL);
484 }
485
486 static void si_emit_clip_state(struct si_context *sctx, struct r600_atom *atom)
487 {
488 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
489
490 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
491 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
492 }
493
494 #define SIX_BITS 0x3F
495
496 static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom)
497 {
498 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
499 struct tgsi_shader_info *info = si_get_vs_info(sctx);
500 unsigned window_space =
501 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
502 unsigned clipdist_mask =
503 info->writes_clipvertex ? SIX_BITS : info->clipdist_writemask;
504
505 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
506 S_02881C_USE_VTX_POINT_SIZE(info->writes_psize) |
507 S_02881C_USE_VTX_EDGE_FLAG(info->writes_edgeflag) |
508 S_02881C_USE_VTX_RENDER_TARGET_INDX(info->writes_layer) |
509 S_02881C_USE_VTX_VIEWPORT_INDX(info->writes_viewport_index) |
510 S_02881C_VS_OUT_CCDIST0_VEC_ENA((clipdist_mask & 0x0F) != 0) |
511 S_02881C_VS_OUT_CCDIST1_VEC_ENA((clipdist_mask & 0xF0) != 0) |
512 S_02881C_VS_OUT_MISC_VEC_ENA(info->writes_psize ||
513 info->writes_edgeflag ||
514 info->writes_layer ||
515 info->writes_viewport_index) |
516 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(1) |
517 (sctx->queued.named.rasterizer->clip_plane_enable &
518 clipdist_mask));
519 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
520 sctx->queued.named.rasterizer->pa_cl_clip_cntl |
521 (clipdist_mask ? 0 :
522 sctx->queued.named.rasterizer->clip_plane_enable & SIX_BITS) |
523 S_028810_CLIP_DISABLE(window_space));
524 }
525
526 static void si_set_scissor_states(struct pipe_context *ctx,
527 unsigned start_slot,
528 unsigned num_scissors,
529 const struct pipe_scissor_state *state)
530 {
531 struct si_context *sctx = (struct si_context *)ctx;
532 int i;
533
534 for (i = 0; i < num_scissors; i++)
535 sctx->scissors.states[start_slot + i] = state[i];
536
537 sctx->scissors.dirty_mask |= ((1 << num_scissors) - 1) << start_slot;
538 si_mark_atom_dirty(sctx, &sctx->scissors.atom);
539 }
540
541 static void si_emit_scissors(struct si_context *sctx, struct r600_atom *atom)
542 {
543 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
544 struct pipe_scissor_state *states = sctx->scissors.states;
545 unsigned mask = sctx->scissors.dirty_mask;
546
547 /* The simple case: Only 1 viewport is active. */
548 if (mask & 1 &&
549 !si_get_vs_info(sctx)->writes_viewport_index) {
550 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2);
551 radeon_emit(cs, S_028250_TL_X(states[0].minx) |
552 S_028250_TL_Y(states[0].miny) |
553 S_028250_WINDOW_OFFSET_DISABLE(1));
554 radeon_emit(cs, S_028254_BR_X(states[0].maxx) |
555 S_028254_BR_Y(states[0].maxy));
556 sctx->scissors.dirty_mask &= ~1; /* clear one bit */
557 return;
558 }
559
560 while (mask) {
561 int start, count, i;
562
563 u_bit_scan_consecutive_range(&mask, &start, &count);
564
565 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL +
566 start * 4 * 2, count * 2);
567 for (i = start; i < start+count; i++) {
568 radeon_emit(cs, S_028250_TL_X(states[i].minx) |
569 S_028250_TL_Y(states[i].miny) |
570 S_028250_WINDOW_OFFSET_DISABLE(1));
571 radeon_emit(cs, S_028254_BR_X(states[i].maxx) |
572 S_028254_BR_Y(states[i].maxy));
573 }
574 }
575 sctx->scissors.dirty_mask = 0;
576 }
577
578 static void si_set_viewport_states(struct pipe_context *ctx,
579 unsigned start_slot,
580 unsigned num_viewports,
581 const struct pipe_viewport_state *state)
582 {
583 struct si_context *sctx = (struct si_context *)ctx;
584 int i;
585
586 for (i = 0; i < num_viewports; i++)
587 sctx->viewports.states[start_slot + i] = state[i];
588
589 sctx->viewports.dirty_mask |= ((1 << num_viewports) - 1) << start_slot;
590 si_mark_atom_dirty(sctx, &sctx->viewports.atom);
591 }
592
593 static void si_emit_viewports(struct si_context *sctx, struct r600_atom *atom)
594 {
595 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
596 struct pipe_viewport_state *states = sctx->viewports.states;
597 unsigned mask = sctx->viewports.dirty_mask;
598
599 /* The simple case: Only 1 viewport is active. */
600 if (mask & 1 &&
601 !si_get_vs_info(sctx)->writes_viewport_index) {
602 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE, 6);
603 radeon_emit(cs, fui(states[0].scale[0]));
604 radeon_emit(cs, fui(states[0].translate[0]));
605 radeon_emit(cs, fui(states[0].scale[1]));
606 radeon_emit(cs, fui(states[0].translate[1]));
607 radeon_emit(cs, fui(states[0].scale[2]));
608 radeon_emit(cs, fui(states[0].translate[2]));
609 sctx->viewports.dirty_mask &= ~1; /* clear one bit */
610 return;
611 }
612
613 while (mask) {
614 int start, count, i;
615
616 u_bit_scan_consecutive_range(&mask, &start, &count);
617
618 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE +
619 start * 4 * 6, count * 6);
620 for (i = start; i < start+count; i++) {
621 radeon_emit(cs, fui(states[i].scale[0]));
622 radeon_emit(cs, fui(states[i].translate[0]));
623 radeon_emit(cs, fui(states[i].scale[1]));
624 radeon_emit(cs, fui(states[i].translate[1]));
625 radeon_emit(cs, fui(states[i].scale[2]));
626 radeon_emit(cs, fui(states[i].translate[2]));
627 }
628 }
629 sctx->viewports.dirty_mask = 0;
630 }
631
632 /*
633 * inferred state between framebuffer and rasterizer
634 */
635 static void si_update_poly_offset_state(struct si_context *sctx)
636 {
637 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
638
639 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf)
640 return;
641
642 switch (sctx->framebuffer.state.zsbuf->texture->format) {
643 case PIPE_FORMAT_Z16_UNORM:
644 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
645 break;
646 default: /* 24-bit */
647 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
648 break;
649 case PIPE_FORMAT_Z32_FLOAT:
650 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
651 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
652 break;
653 }
654 }
655
656 /*
657 * Rasterizer
658 */
659
660 static uint32_t si_translate_fill(uint32_t func)
661 {
662 switch(func) {
663 case PIPE_POLYGON_MODE_FILL:
664 return V_028814_X_DRAW_TRIANGLES;
665 case PIPE_POLYGON_MODE_LINE:
666 return V_028814_X_DRAW_LINES;
667 case PIPE_POLYGON_MODE_POINT:
668 return V_028814_X_DRAW_POINTS;
669 default:
670 assert(0);
671 return V_028814_X_DRAW_POINTS;
672 }
673 }
674
675 static void *si_create_rs_state(struct pipe_context *ctx,
676 const struct pipe_rasterizer_state *state)
677 {
678 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
679 struct si_pm4_state *pm4 = &rs->pm4;
680 unsigned tmp, i;
681 float psize_min, psize_max;
682
683 if (rs == NULL) {
684 return NULL;
685 }
686
687 rs->two_side = state->light_twoside;
688 rs->multisample_enable = state->multisample;
689 rs->force_persample_interp = state->force_persample_interp;
690 rs->clip_plane_enable = state->clip_plane_enable;
691 rs->line_stipple_enable = state->line_stipple_enable;
692 rs->poly_stipple_enable = state->poly_stipple_enable;
693 rs->line_smooth = state->line_smooth;
694 rs->poly_smooth = state->poly_smooth;
695 rs->uses_poly_offset = state->offset_point || state->offset_line ||
696 state->offset_tri;
697 rs->clamp_fragment_color = state->clamp_fragment_color;
698 rs->flatshade = state->flatshade;
699 rs->sprite_coord_enable = state->sprite_coord_enable;
700 rs->pa_sc_line_stipple = state->line_stipple_enable ?
701 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
702 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
703 rs->pa_cl_clip_cntl =
704 S_028810_PS_UCP_MODE(3) |
705 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
706 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
707 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
708 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
709 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
710
711 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
712 S_0286D4_FLAT_SHADE_ENA(1) |
713 S_0286D4_PNT_SPRITE_ENA(1) |
714 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
715 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
716 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
717 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
718 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
719
720 /* point size 12.4 fixed point */
721 tmp = (unsigned)(state->point_size * 8.0);
722 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
723
724 if (state->point_size_per_vertex) {
725 psize_min = util_get_min_point_size(state);
726 psize_max = 8192;
727 } else {
728 /* Force the point size to be as if the vertex output was disabled. */
729 psize_min = state->point_size;
730 psize_max = state->point_size;
731 }
732 /* Divide by two, because 0.5 = 1 pixel. */
733 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
734 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
735 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
736
737 tmp = (unsigned)state->line_width * 8;
738 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
739 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
740 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
741 S_028A48_MSAA_ENABLE(state->multisample ||
742 state->poly_smooth ||
743 state->line_smooth) |
744 S_028A48_VPORT_SCISSOR_ENABLE(state->scissor));
745
746 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
747 S_028BE4_PIX_CENTER(state->half_pixel_center) |
748 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
749
750 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
751 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
752 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
753 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
754 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
755 S_028814_FACE(!state->front_ccw) |
756 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
757 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
758 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
759 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
760 state->fill_back != PIPE_POLYGON_MODE_FILL) |
761 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
762 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
763 si_pm4_set_reg(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0 +
764 SI_SGPR_VS_STATE_BITS * 4, state->clamp_vertex_color);
765
766 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
767 for (i = 0; i < 3; i++) {
768 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
769 float offset_units = state->offset_units;
770 float offset_scale = state->offset_scale * 16.0f;
771
772 switch (i) {
773 case 0: /* 16-bit zbuffer */
774 offset_units *= 4.0f;
775 break;
776 case 1: /* 24-bit zbuffer */
777 offset_units *= 2.0f;
778 break;
779 case 2: /* 32-bit zbuffer */
780 offset_units *= 1.0f;
781 break;
782 }
783
784 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
785 fui(offset_scale));
786 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
787 fui(offset_units));
788 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
789 fui(offset_scale));
790 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
791 fui(offset_units));
792 }
793
794 return rs;
795 }
796
797 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
798 {
799 struct si_context *sctx = (struct si_context *)ctx;
800 struct si_state_rasterizer *old_rs =
801 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
802 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
803
804 if (state == NULL)
805 return;
806
807 if (sctx->framebuffer.nr_samples > 1 &&
808 (!old_rs || old_rs->multisample_enable != rs->multisample_enable))
809 si_mark_atom_dirty(sctx, &sctx->db_render_state);
810
811 si_pm4_bind_state(sctx, rasterizer, rs);
812 si_update_poly_offset_state(sctx);
813
814 si_mark_atom_dirty(sctx, &sctx->clip_regs);
815 }
816
817 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
818 {
819 struct si_context *sctx = (struct si_context *)ctx;
820
821 if (sctx->queued.named.rasterizer == state)
822 si_pm4_bind_state(sctx, poly_offset, NULL);
823 si_pm4_delete_state(sctx, rasterizer, (struct si_state_rasterizer *)state);
824 }
825
826 /*
827 * infeered state between dsa and stencil ref
828 */
829 static void si_emit_stencil_ref(struct si_context *sctx, struct r600_atom *atom)
830 {
831 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
832 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
833 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
834
835 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
836 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
837 S_028430_STENCILMASK(dsa->valuemask[0]) |
838 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
839 S_028430_STENCILOPVAL(1));
840 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
841 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
842 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
843 S_028434_STENCILOPVAL_BF(1));
844 }
845
846 static void si_set_stencil_ref(struct pipe_context *ctx,
847 const struct pipe_stencil_ref *state)
848 {
849 struct si_context *sctx = (struct si_context *)ctx;
850
851 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
852 return;
853
854 sctx->stencil_ref.state = *state;
855 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
856 }
857
858
859 /*
860 * DSA
861 */
862
863 static uint32_t si_translate_stencil_op(int s_op)
864 {
865 switch (s_op) {
866 case PIPE_STENCIL_OP_KEEP:
867 return V_02842C_STENCIL_KEEP;
868 case PIPE_STENCIL_OP_ZERO:
869 return V_02842C_STENCIL_ZERO;
870 case PIPE_STENCIL_OP_REPLACE:
871 return V_02842C_STENCIL_REPLACE_TEST;
872 case PIPE_STENCIL_OP_INCR:
873 return V_02842C_STENCIL_ADD_CLAMP;
874 case PIPE_STENCIL_OP_DECR:
875 return V_02842C_STENCIL_SUB_CLAMP;
876 case PIPE_STENCIL_OP_INCR_WRAP:
877 return V_02842C_STENCIL_ADD_WRAP;
878 case PIPE_STENCIL_OP_DECR_WRAP:
879 return V_02842C_STENCIL_SUB_WRAP;
880 case PIPE_STENCIL_OP_INVERT:
881 return V_02842C_STENCIL_INVERT;
882 default:
883 R600_ERR("Unknown stencil op %d", s_op);
884 assert(0);
885 break;
886 }
887 return 0;
888 }
889
890 static void *si_create_dsa_state(struct pipe_context *ctx,
891 const struct pipe_depth_stencil_alpha_state *state)
892 {
893 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
894 struct si_pm4_state *pm4 = &dsa->pm4;
895 unsigned db_depth_control;
896 uint32_t db_stencil_control = 0;
897
898 if (dsa == NULL) {
899 return NULL;
900 }
901
902 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
903 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
904 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
905 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
906
907 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
908 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
909 S_028800_ZFUNC(state->depth.func) |
910 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
911
912 /* stencil */
913 if (state->stencil[0].enabled) {
914 db_depth_control |= S_028800_STENCIL_ENABLE(1);
915 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
916 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
917 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
918 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
919
920 if (state->stencil[1].enabled) {
921 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
922 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
923 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
924 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
925 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
926 }
927 }
928
929 /* alpha */
930 if (state->alpha.enabled) {
931 dsa->alpha_func = state->alpha.func;
932
933 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
934 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
935 } else {
936 dsa->alpha_func = PIPE_FUNC_ALWAYS;
937 }
938
939 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
940 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
941 if (state->depth.bounds_test) {
942 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
943 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
944 }
945
946 return dsa;
947 }
948
949 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
950 {
951 struct si_context *sctx = (struct si_context *)ctx;
952 struct si_state_dsa *dsa = state;
953
954 if (state == NULL)
955 return;
956
957 si_pm4_bind_state(sctx, dsa, dsa);
958
959 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
960 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
961 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
962 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
963 }
964 }
965
966 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
967 {
968 struct si_context *sctx = (struct si_context *)ctx;
969 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
970 }
971
972 static void *si_create_db_flush_dsa(struct si_context *sctx)
973 {
974 struct pipe_depth_stencil_alpha_state dsa = {};
975
976 return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
977 }
978
979 /* DB RENDER STATE */
980
981 static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
982 {
983 struct si_context *sctx = (struct si_context*)ctx;
984
985 si_mark_atom_dirty(sctx, &sctx->db_render_state);
986 }
987
988 static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
989 {
990 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
991 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
992 unsigned db_shader_control;
993
994 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
995
996 /* DB_RENDER_CONTROL */
997 if (sctx->dbcb_depth_copy_enabled ||
998 sctx->dbcb_stencil_copy_enabled) {
999 radeon_emit(cs,
1000 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1001 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1002 S_028000_COPY_CENTROID(1) |
1003 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
1004 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1005 radeon_emit(cs,
1006 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1007 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace));
1008 } else if (sctx->db_depth_clear) {
1009 radeon_emit(cs, S_028000_DEPTH_CLEAR_ENABLE(1));
1010 } else {
1011 radeon_emit(cs, 0);
1012 }
1013
1014 /* DB_COUNT_CONTROL (occlusion queries) */
1015 if (sctx->b.num_occlusion_queries > 0) {
1016 if (sctx->b.chip_class >= CIK) {
1017 radeon_emit(cs,
1018 S_028004_PERFECT_ZPASS_COUNTS(1) |
1019 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
1020 S_028004_ZPASS_ENABLE(1) |
1021 S_028004_SLICE_EVEN_ENABLE(1) |
1022 S_028004_SLICE_ODD_ENABLE(1));
1023 } else {
1024 radeon_emit(cs,
1025 S_028004_PERFECT_ZPASS_COUNTS(1) |
1026 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
1027 }
1028 } else {
1029 /* Disable occlusion queries. */
1030 if (sctx->b.chip_class >= CIK) {
1031 radeon_emit(cs, 0);
1032 } else {
1033 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
1034 }
1035 }
1036
1037 /* DB_RENDER_OVERRIDE2 */
1038 if (sctx->db_depth_disable_expclear) {
1039 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
1040 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(1));
1041 } else {
1042 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2, 0);
1043 }
1044
1045 db_shader_control = S_02880C_ALPHA_TO_MASK_DISABLE(sctx->framebuffer.cb0_is_integer) |
1046 sctx->ps_db_shader_control;
1047
1048 /* Bug workaround for smoothing (overrasterization) on SI. */
1049 if (sctx->b.chip_class == SI && sctx->smoothing_enabled)
1050 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1051 else
1052 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
1053
1054 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1055 if (sctx->framebuffer.nr_samples <= 1 || (rs && !rs->multisample_enable))
1056 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1057
1058 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
1059 db_shader_control);
1060 }
1061
1062 /*
1063 * format translation
1064 */
1065 static uint32_t si_translate_colorformat(enum pipe_format format)
1066 {
1067 const struct util_format_description *desc = util_format_description(format);
1068
1069 #define HAS_SIZE(x,y,z,w) \
1070 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1071 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1072
1073 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1074 return V_028C70_COLOR_10_11_11;
1075
1076 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1077 return V_028C70_COLOR_INVALID;
1078
1079 switch (desc->nr_channels) {
1080 case 1:
1081 switch (desc->channel[0].size) {
1082 case 8:
1083 return V_028C70_COLOR_8;
1084 case 16:
1085 return V_028C70_COLOR_16;
1086 case 32:
1087 return V_028C70_COLOR_32;
1088 }
1089 break;
1090 case 2:
1091 if (desc->channel[0].size == desc->channel[1].size) {
1092 switch (desc->channel[0].size) {
1093 case 8:
1094 return V_028C70_COLOR_8_8;
1095 case 16:
1096 return V_028C70_COLOR_16_16;
1097 case 32:
1098 return V_028C70_COLOR_32_32;
1099 }
1100 } else if (HAS_SIZE(8,24,0,0)) {
1101 return V_028C70_COLOR_24_8;
1102 } else if (HAS_SIZE(24,8,0,0)) {
1103 return V_028C70_COLOR_8_24;
1104 }
1105 break;
1106 case 3:
1107 if (HAS_SIZE(5,6,5,0)) {
1108 return V_028C70_COLOR_5_6_5;
1109 } else if (HAS_SIZE(32,8,24,0)) {
1110 return V_028C70_COLOR_X24_8_32_FLOAT;
1111 }
1112 break;
1113 case 4:
1114 if (desc->channel[0].size == desc->channel[1].size &&
1115 desc->channel[0].size == desc->channel[2].size &&
1116 desc->channel[0].size == desc->channel[3].size) {
1117 switch (desc->channel[0].size) {
1118 case 4:
1119 return V_028C70_COLOR_4_4_4_4;
1120 case 8:
1121 return V_028C70_COLOR_8_8_8_8;
1122 case 16:
1123 return V_028C70_COLOR_16_16_16_16;
1124 case 32:
1125 return V_028C70_COLOR_32_32_32_32;
1126 }
1127 } else if (HAS_SIZE(5,5,5,1)) {
1128 return V_028C70_COLOR_1_5_5_5;
1129 } else if (HAS_SIZE(10,10,10,2)) {
1130 return V_028C70_COLOR_2_10_10_10;
1131 }
1132 break;
1133 }
1134 return V_028C70_COLOR_INVALID;
1135 }
1136
1137 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1138 {
1139 if (SI_BIG_ENDIAN) {
1140 switch(colorformat) {
1141 /* 8-bit buffers. */
1142 case V_028C70_COLOR_8:
1143 return V_028C70_ENDIAN_NONE;
1144
1145 /* 16-bit buffers. */
1146 case V_028C70_COLOR_5_6_5:
1147 case V_028C70_COLOR_1_5_5_5:
1148 case V_028C70_COLOR_4_4_4_4:
1149 case V_028C70_COLOR_16:
1150 case V_028C70_COLOR_8_8:
1151 return V_028C70_ENDIAN_8IN16;
1152
1153 /* 32-bit buffers. */
1154 case V_028C70_COLOR_8_8_8_8:
1155 case V_028C70_COLOR_2_10_10_10:
1156 case V_028C70_COLOR_8_24:
1157 case V_028C70_COLOR_24_8:
1158 case V_028C70_COLOR_16_16:
1159 return V_028C70_ENDIAN_8IN32;
1160
1161 /* 64-bit buffers. */
1162 case V_028C70_COLOR_16_16_16_16:
1163 return V_028C70_ENDIAN_8IN16;
1164
1165 case V_028C70_COLOR_32_32:
1166 return V_028C70_ENDIAN_8IN32;
1167
1168 /* 128-bit buffers. */
1169 case V_028C70_COLOR_32_32_32_32:
1170 return V_028C70_ENDIAN_8IN32;
1171 default:
1172 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1173 }
1174 } else {
1175 return V_028C70_ENDIAN_NONE;
1176 }
1177 }
1178
1179 /* Returns the size in bits of the widest component of a CB format */
1180 static unsigned si_colorformat_max_comp_size(uint32_t colorformat)
1181 {
1182 switch(colorformat) {
1183 case V_028C70_COLOR_4_4_4_4:
1184 return 4;
1185
1186 case V_028C70_COLOR_1_5_5_5:
1187 case V_028C70_COLOR_5_5_5_1:
1188 return 5;
1189
1190 case V_028C70_COLOR_5_6_5:
1191 return 6;
1192
1193 case V_028C70_COLOR_8:
1194 case V_028C70_COLOR_8_8:
1195 case V_028C70_COLOR_8_8_8_8:
1196 return 8;
1197
1198 case V_028C70_COLOR_10_10_10_2:
1199 case V_028C70_COLOR_2_10_10_10:
1200 return 10;
1201
1202 case V_028C70_COLOR_10_11_11:
1203 case V_028C70_COLOR_11_11_10:
1204 return 11;
1205
1206 case V_028C70_COLOR_16:
1207 case V_028C70_COLOR_16_16:
1208 case V_028C70_COLOR_16_16_16_16:
1209 return 16;
1210
1211 case V_028C70_COLOR_8_24:
1212 case V_028C70_COLOR_24_8:
1213 return 24;
1214
1215 case V_028C70_COLOR_32:
1216 case V_028C70_COLOR_32_32:
1217 case V_028C70_COLOR_32_32_32_32:
1218 case V_028C70_COLOR_X24_8_32_FLOAT:
1219 return 32;
1220 }
1221
1222 assert(!"Unknown maximum component size");
1223 return 0;
1224 }
1225
1226 static uint32_t si_translate_dbformat(enum pipe_format format)
1227 {
1228 switch (format) {
1229 case PIPE_FORMAT_Z16_UNORM:
1230 return V_028040_Z_16;
1231 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1232 case PIPE_FORMAT_X8Z24_UNORM:
1233 case PIPE_FORMAT_Z24X8_UNORM:
1234 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1235 return V_028040_Z_24; /* deprecated on SI */
1236 case PIPE_FORMAT_Z32_FLOAT:
1237 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1238 return V_028040_Z_32_FLOAT;
1239 default:
1240 return V_028040_Z_INVALID;
1241 }
1242 }
1243
1244 /*
1245 * Texture translation
1246 */
1247
1248 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1249 enum pipe_format format,
1250 const struct util_format_description *desc,
1251 int first_non_void)
1252 {
1253 struct si_screen *sscreen = (struct si_screen*)screen;
1254 bool enable_compressed_formats = (sscreen->b.info.drm_major == 2 &&
1255 sscreen->b.info.drm_minor >= 31) ||
1256 sscreen->b.info.drm_major == 3;
1257 boolean uniform = TRUE;
1258 int i;
1259
1260 /* Colorspace (return non-RGB formats directly). */
1261 switch (desc->colorspace) {
1262 /* Depth stencil formats */
1263 case UTIL_FORMAT_COLORSPACE_ZS:
1264 switch (format) {
1265 case PIPE_FORMAT_Z16_UNORM:
1266 return V_008F14_IMG_DATA_FORMAT_16;
1267 case PIPE_FORMAT_X24S8_UINT:
1268 case PIPE_FORMAT_Z24X8_UNORM:
1269 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1270 return V_008F14_IMG_DATA_FORMAT_8_24;
1271 case PIPE_FORMAT_X8Z24_UNORM:
1272 case PIPE_FORMAT_S8X24_UINT:
1273 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1274 return V_008F14_IMG_DATA_FORMAT_24_8;
1275 case PIPE_FORMAT_S8_UINT:
1276 return V_008F14_IMG_DATA_FORMAT_8;
1277 case PIPE_FORMAT_Z32_FLOAT:
1278 return V_008F14_IMG_DATA_FORMAT_32;
1279 case PIPE_FORMAT_X32_S8X24_UINT:
1280 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1281 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1282 default:
1283 goto out_unknown;
1284 }
1285
1286 case UTIL_FORMAT_COLORSPACE_YUV:
1287 goto out_unknown; /* TODO */
1288
1289 case UTIL_FORMAT_COLORSPACE_SRGB:
1290 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1291 goto out_unknown;
1292 break;
1293
1294 default:
1295 break;
1296 }
1297
1298 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1299 if (!enable_compressed_formats)
1300 goto out_unknown;
1301
1302 switch (format) {
1303 case PIPE_FORMAT_RGTC1_SNORM:
1304 case PIPE_FORMAT_LATC1_SNORM:
1305 case PIPE_FORMAT_RGTC1_UNORM:
1306 case PIPE_FORMAT_LATC1_UNORM:
1307 return V_008F14_IMG_DATA_FORMAT_BC4;
1308 case PIPE_FORMAT_RGTC2_SNORM:
1309 case PIPE_FORMAT_LATC2_SNORM:
1310 case PIPE_FORMAT_RGTC2_UNORM:
1311 case PIPE_FORMAT_LATC2_UNORM:
1312 return V_008F14_IMG_DATA_FORMAT_BC5;
1313 default:
1314 goto out_unknown;
1315 }
1316 }
1317
1318 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1319 if (!enable_compressed_formats)
1320 goto out_unknown;
1321
1322 switch (format) {
1323 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1324 case PIPE_FORMAT_BPTC_SRGBA:
1325 return V_008F14_IMG_DATA_FORMAT_BC7;
1326 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1327 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1328 return V_008F14_IMG_DATA_FORMAT_BC6;
1329 default:
1330 goto out_unknown;
1331 }
1332 }
1333
1334 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1335 switch (format) {
1336 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1337 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1338 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1339 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1340 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1341 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1342 default:
1343 goto out_unknown;
1344 }
1345 }
1346
1347 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1348 if (!enable_compressed_formats)
1349 goto out_unknown;
1350
1351 if (!util_format_s3tc_enabled) {
1352 goto out_unknown;
1353 }
1354
1355 switch (format) {
1356 case PIPE_FORMAT_DXT1_RGB:
1357 case PIPE_FORMAT_DXT1_RGBA:
1358 case PIPE_FORMAT_DXT1_SRGB:
1359 case PIPE_FORMAT_DXT1_SRGBA:
1360 return V_008F14_IMG_DATA_FORMAT_BC1;
1361 case PIPE_FORMAT_DXT3_RGBA:
1362 case PIPE_FORMAT_DXT3_SRGBA:
1363 return V_008F14_IMG_DATA_FORMAT_BC2;
1364 case PIPE_FORMAT_DXT5_RGBA:
1365 case PIPE_FORMAT_DXT5_SRGBA:
1366 return V_008F14_IMG_DATA_FORMAT_BC3;
1367 default:
1368 goto out_unknown;
1369 }
1370 }
1371
1372 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1373 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1374 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1375 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1376 }
1377
1378 /* R8G8Bx_SNORM - TODO CxV8U8 */
1379
1380 /* See whether the components are of the same size. */
1381 for (i = 1; i < desc->nr_channels; i++) {
1382 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1383 }
1384
1385 /* Non-uniform formats. */
1386 if (!uniform) {
1387 switch(desc->nr_channels) {
1388 case 3:
1389 if (desc->channel[0].size == 5 &&
1390 desc->channel[1].size == 6 &&
1391 desc->channel[2].size == 5) {
1392 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1393 }
1394 goto out_unknown;
1395 case 4:
1396 if (desc->channel[0].size == 5 &&
1397 desc->channel[1].size == 5 &&
1398 desc->channel[2].size == 5 &&
1399 desc->channel[3].size == 1) {
1400 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1401 }
1402 if (desc->channel[0].size == 10 &&
1403 desc->channel[1].size == 10 &&
1404 desc->channel[2].size == 10 &&
1405 desc->channel[3].size == 2) {
1406 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1407 }
1408 goto out_unknown;
1409 }
1410 goto out_unknown;
1411 }
1412
1413 if (first_non_void < 0 || first_non_void > 3)
1414 goto out_unknown;
1415
1416 /* uniform formats */
1417 switch (desc->channel[first_non_void].size) {
1418 case 4:
1419 switch (desc->nr_channels) {
1420 #if 0 /* Not supported for render targets */
1421 case 2:
1422 return V_008F14_IMG_DATA_FORMAT_4_4;
1423 #endif
1424 case 4:
1425 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1426 }
1427 break;
1428 case 8:
1429 switch (desc->nr_channels) {
1430 case 1:
1431 return V_008F14_IMG_DATA_FORMAT_8;
1432 case 2:
1433 return V_008F14_IMG_DATA_FORMAT_8_8;
1434 case 4:
1435 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1436 }
1437 break;
1438 case 16:
1439 switch (desc->nr_channels) {
1440 case 1:
1441 return V_008F14_IMG_DATA_FORMAT_16;
1442 case 2:
1443 return V_008F14_IMG_DATA_FORMAT_16_16;
1444 case 4:
1445 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1446 }
1447 break;
1448 case 32:
1449 switch (desc->nr_channels) {
1450 case 1:
1451 return V_008F14_IMG_DATA_FORMAT_32;
1452 case 2:
1453 return V_008F14_IMG_DATA_FORMAT_32_32;
1454 #if 0 /* Not supported for render targets */
1455 case 3:
1456 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1457 #endif
1458 case 4:
1459 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1460 }
1461 }
1462
1463 out_unknown:
1464 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1465 return ~0;
1466 }
1467
1468 static unsigned si_tex_wrap(unsigned wrap)
1469 {
1470 switch (wrap) {
1471 default:
1472 case PIPE_TEX_WRAP_REPEAT:
1473 return V_008F30_SQ_TEX_WRAP;
1474 case PIPE_TEX_WRAP_CLAMP:
1475 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1476 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1477 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1478 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1479 return V_008F30_SQ_TEX_CLAMP_BORDER;
1480 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1481 return V_008F30_SQ_TEX_MIRROR;
1482 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1483 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1484 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1485 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1486 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1487 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1488 }
1489 }
1490
1491 static unsigned si_tex_filter(unsigned filter)
1492 {
1493 switch (filter) {
1494 default:
1495 case PIPE_TEX_FILTER_NEAREST:
1496 return V_008F38_SQ_TEX_XY_FILTER_POINT;
1497 case PIPE_TEX_FILTER_LINEAR:
1498 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
1499 }
1500 }
1501
1502 static unsigned si_tex_mipfilter(unsigned filter)
1503 {
1504 switch (filter) {
1505 case PIPE_TEX_MIPFILTER_NEAREST:
1506 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1507 case PIPE_TEX_MIPFILTER_LINEAR:
1508 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1509 default:
1510 case PIPE_TEX_MIPFILTER_NONE:
1511 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1512 }
1513 }
1514
1515 static unsigned si_tex_compare(unsigned compare)
1516 {
1517 switch (compare) {
1518 default:
1519 case PIPE_FUNC_NEVER:
1520 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1521 case PIPE_FUNC_LESS:
1522 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1523 case PIPE_FUNC_EQUAL:
1524 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1525 case PIPE_FUNC_LEQUAL:
1526 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1527 case PIPE_FUNC_GREATER:
1528 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1529 case PIPE_FUNC_NOTEQUAL:
1530 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1531 case PIPE_FUNC_GEQUAL:
1532 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1533 case PIPE_FUNC_ALWAYS:
1534 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1535 }
1536 }
1537
1538 static unsigned si_tex_dim(unsigned res_target, unsigned view_target,
1539 unsigned nr_samples)
1540 {
1541 if (view_target == PIPE_TEXTURE_CUBE ||
1542 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1543 res_target = view_target;
1544
1545 switch (res_target) {
1546 default:
1547 case PIPE_TEXTURE_1D:
1548 return V_008F1C_SQ_RSRC_IMG_1D;
1549 case PIPE_TEXTURE_1D_ARRAY:
1550 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1551 case PIPE_TEXTURE_2D:
1552 case PIPE_TEXTURE_RECT:
1553 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1554 V_008F1C_SQ_RSRC_IMG_2D;
1555 case PIPE_TEXTURE_2D_ARRAY:
1556 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1557 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1558 case PIPE_TEXTURE_3D:
1559 return V_008F1C_SQ_RSRC_IMG_3D;
1560 case PIPE_TEXTURE_CUBE:
1561 case PIPE_TEXTURE_CUBE_ARRAY:
1562 return V_008F1C_SQ_RSRC_IMG_CUBE;
1563 }
1564 }
1565
1566 /*
1567 * Format support testing
1568 */
1569
1570 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1571 {
1572 return si_translate_texformat(screen, format, util_format_description(format),
1573 util_format_get_first_non_void_channel(format)) != ~0U;
1574 }
1575
1576 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1577 const struct util_format_description *desc,
1578 int first_non_void)
1579 {
1580 unsigned type = desc->channel[first_non_void].type;
1581 int i;
1582
1583 if (type == UTIL_FORMAT_TYPE_FIXED)
1584 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1585
1586 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1587 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1588
1589 if (desc->nr_channels == 4 &&
1590 desc->channel[0].size == 10 &&
1591 desc->channel[1].size == 10 &&
1592 desc->channel[2].size == 10 &&
1593 desc->channel[3].size == 2)
1594 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1595
1596 /* See whether the components are of the same size. */
1597 for (i = 0; i < desc->nr_channels; i++) {
1598 if (desc->channel[first_non_void].size != desc->channel[i].size)
1599 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1600 }
1601
1602 switch (desc->channel[first_non_void].size) {
1603 case 8:
1604 switch (desc->nr_channels) {
1605 case 1:
1606 return V_008F0C_BUF_DATA_FORMAT_8;
1607 case 2:
1608 return V_008F0C_BUF_DATA_FORMAT_8_8;
1609 case 3:
1610 case 4:
1611 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1612 }
1613 break;
1614 case 16:
1615 switch (desc->nr_channels) {
1616 case 1:
1617 return V_008F0C_BUF_DATA_FORMAT_16;
1618 case 2:
1619 return V_008F0C_BUF_DATA_FORMAT_16_16;
1620 case 3:
1621 case 4:
1622 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1623 }
1624 break;
1625 case 32:
1626 /* From the Southern Islands ISA documentation about MTBUF:
1627 * 'Memory reads of data in memory that is 32 or 64 bits do not
1628 * undergo any format conversion.'
1629 */
1630 if (type != UTIL_FORMAT_TYPE_FLOAT &&
1631 !desc->channel[first_non_void].pure_integer)
1632 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1633
1634 switch (desc->nr_channels) {
1635 case 1:
1636 return V_008F0C_BUF_DATA_FORMAT_32;
1637 case 2:
1638 return V_008F0C_BUF_DATA_FORMAT_32_32;
1639 case 3:
1640 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1641 case 4:
1642 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1643 }
1644 break;
1645 }
1646
1647 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1648 }
1649
1650 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1651 const struct util_format_description *desc,
1652 int first_non_void)
1653 {
1654 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1655 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1656
1657 switch (desc->channel[first_non_void].type) {
1658 case UTIL_FORMAT_TYPE_SIGNED:
1659 if (desc->channel[first_non_void].normalized)
1660 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1661 else if (desc->channel[first_non_void].pure_integer)
1662 return V_008F0C_BUF_NUM_FORMAT_SINT;
1663 else
1664 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1665 break;
1666 case UTIL_FORMAT_TYPE_UNSIGNED:
1667 if (desc->channel[first_non_void].normalized)
1668 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1669 else if (desc->channel[first_non_void].pure_integer)
1670 return V_008F0C_BUF_NUM_FORMAT_UINT;
1671 else
1672 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1673 break;
1674 case UTIL_FORMAT_TYPE_FLOAT:
1675 default:
1676 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1677 }
1678 }
1679
1680 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
1681 {
1682 const struct util_format_description *desc;
1683 int first_non_void;
1684 unsigned data_format;
1685
1686 desc = util_format_description(format);
1687 first_non_void = util_format_get_first_non_void_channel(format);
1688 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1689 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
1690 }
1691
1692 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1693 {
1694 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1695 r600_translate_colorswap(format) != ~0U;
1696 }
1697
1698 static bool si_is_zs_format_supported(enum pipe_format format)
1699 {
1700 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1701 }
1702
1703 boolean si_is_format_supported(struct pipe_screen *screen,
1704 enum pipe_format format,
1705 enum pipe_texture_target target,
1706 unsigned sample_count,
1707 unsigned usage)
1708 {
1709 unsigned retval = 0;
1710
1711 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1712 R600_ERR("r600: unsupported texture type %d\n", target);
1713 return FALSE;
1714 }
1715
1716 if (!util_format_is_supported(format, usage))
1717 return FALSE;
1718
1719 if (sample_count > 1) {
1720 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
1721 return FALSE;
1722
1723 switch (sample_count) {
1724 case 2:
1725 case 4:
1726 case 8:
1727 break;
1728 default:
1729 return FALSE;
1730 }
1731 }
1732
1733 if (usage & PIPE_BIND_SAMPLER_VIEW) {
1734 if (target == PIPE_BUFFER) {
1735 if (si_is_vertex_format_supported(screen, format))
1736 retval |= PIPE_BIND_SAMPLER_VIEW;
1737 } else {
1738 if (si_is_sampler_format_supported(screen, format))
1739 retval |= PIPE_BIND_SAMPLER_VIEW;
1740 }
1741 }
1742
1743 if ((usage & (PIPE_BIND_RENDER_TARGET |
1744 PIPE_BIND_DISPLAY_TARGET |
1745 PIPE_BIND_SCANOUT |
1746 PIPE_BIND_SHARED |
1747 PIPE_BIND_BLENDABLE)) &&
1748 si_is_colorbuffer_format_supported(format)) {
1749 retval |= usage &
1750 (PIPE_BIND_RENDER_TARGET |
1751 PIPE_BIND_DISPLAY_TARGET |
1752 PIPE_BIND_SCANOUT |
1753 PIPE_BIND_SHARED);
1754 if (!util_format_is_pure_integer(format) &&
1755 !util_format_is_depth_or_stencil(format))
1756 retval |= usage & PIPE_BIND_BLENDABLE;
1757 }
1758
1759 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1760 si_is_zs_format_supported(format)) {
1761 retval |= PIPE_BIND_DEPTH_STENCIL;
1762 }
1763
1764 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
1765 si_is_vertex_format_supported(screen, format)) {
1766 retval |= PIPE_BIND_VERTEX_BUFFER;
1767 }
1768
1769 if (usage & PIPE_BIND_TRANSFER_READ)
1770 retval |= PIPE_BIND_TRANSFER_READ;
1771 if (usage & PIPE_BIND_TRANSFER_WRITE)
1772 retval |= PIPE_BIND_TRANSFER_WRITE;
1773
1774 return retval == usage;
1775 }
1776
1777 unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
1778 {
1779 unsigned tile_mode_index = 0;
1780
1781 if (stencil) {
1782 tile_mode_index = rtex->surface.stencil_tiling_index[level];
1783 } else {
1784 tile_mode_index = rtex->surface.tiling_index[level];
1785 }
1786 return tile_mode_index;
1787 }
1788
1789 /*
1790 * framebuffer handling
1791 */
1792
1793 static void si_initialize_color_surface(struct si_context *sctx,
1794 struct r600_surface *surf)
1795 {
1796 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1797 unsigned level = surf->base.u.tex.level;
1798 uint64_t offset = rtex->surface.level[level].offset;
1799 unsigned pitch, slice;
1800 unsigned color_info, color_attrib, color_pitch, color_view;
1801 unsigned tile_mode_index;
1802 unsigned format, swap, ntype, endian;
1803 const struct util_format_description *desc;
1804 int i;
1805 unsigned blend_clamp = 0, blend_bypass = 0;
1806 unsigned max_comp_size;
1807
1808 /* Layered rendering doesn't work with LINEAR_GENERAL.
1809 * (LINEAR_ALIGNED and others work) */
1810 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) {
1811 assert(surf->base.u.tex.first_layer == surf->base.u.tex.last_layer);
1812 offset += rtex->surface.level[level].slice_size *
1813 surf->base.u.tex.first_layer;
1814 color_view = 0;
1815 } else {
1816 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
1817 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
1818 }
1819
1820 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1821 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1822 if (slice) {
1823 slice = slice - 1;
1824 }
1825
1826 tile_mode_index = si_tile_mode_index(rtex, level, false);
1827
1828 desc = util_format_description(surf->base.format);
1829 for (i = 0; i < 4; i++) {
1830 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1831 break;
1832 }
1833 }
1834 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1835 ntype = V_028C70_NUMBER_FLOAT;
1836 } else {
1837 ntype = V_028C70_NUMBER_UNORM;
1838 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1839 ntype = V_028C70_NUMBER_SRGB;
1840 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1841 if (desc->channel[i].pure_integer) {
1842 ntype = V_028C70_NUMBER_SINT;
1843 } else {
1844 assert(desc->channel[i].normalized);
1845 ntype = V_028C70_NUMBER_SNORM;
1846 }
1847 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1848 if (desc->channel[i].pure_integer) {
1849 ntype = V_028C70_NUMBER_UINT;
1850 } else {
1851 assert(desc->channel[i].normalized);
1852 ntype = V_028C70_NUMBER_UNORM;
1853 }
1854 }
1855 }
1856
1857 format = si_translate_colorformat(surf->base.format);
1858 if (format == V_028C70_COLOR_INVALID) {
1859 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
1860 }
1861 assert(format != V_028C70_COLOR_INVALID);
1862 swap = r600_translate_colorswap(surf->base.format);
1863 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1864 endian = V_028C70_ENDIAN_NONE;
1865 } else {
1866 endian = si_colorformat_endian_swap(format);
1867 }
1868
1869 /* blend clamp should be set for all NORM/SRGB types */
1870 if (ntype == V_028C70_NUMBER_UNORM ||
1871 ntype == V_028C70_NUMBER_SNORM ||
1872 ntype == V_028C70_NUMBER_SRGB)
1873 blend_clamp = 1;
1874
1875 /* set blend bypass according to docs if SINT/UINT or
1876 8/24 COLOR variants */
1877 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1878 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1879 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1880 blend_clamp = 0;
1881 blend_bypass = 1;
1882 }
1883
1884 color_info = S_028C70_FORMAT(format) |
1885 S_028C70_COMP_SWAP(swap) |
1886 S_028C70_BLEND_CLAMP(blend_clamp) |
1887 S_028C70_BLEND_BYPASS(blend_bypass) |
1888 S_028C70_NUMBER_TYPE(ntype) |
1889 S_028C70_ENDIAN(endian);
1890
1891 color_pitch = S_028C64_TILE_MAX(pitch);
1892
1893 color_attrib = S_028C74_TILE_MODE_INDEX(tile_mode_index) |
1894 S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == UTIL_FORMAT_SWIZZLE_1);
1895
1896 if (rtex->resource.b.b.nr_samples > 1) {
1897 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1898
1899 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1900 S_028C74_NUM_FRAGMENTS(log_samples);
1901
1902 if (rtex->fmask.size) {
1903 color_info |= S_028C70_COMPRESSION(1);
1904 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
1905
1906 color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(rtex->fmask.tile_mode_index);
1907
1908 if (sctx->b.chip_class == SI) {
1909 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
1910 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1911 }
1912 if (sctx->b.chip_class >= CIK) {
1913 color_pitch |= S_028C64_FMASK_TILE_MAX(rtex->fmask.pitch / 8 - 1);
1914 }
1915 }
1916 }
1917
1918 offset += rtex->resource.gpu_address;
1919
1920 surf->cb_color_base = offset >> 8;
1921 surf->cb_color_pitch = color_pitch;
1922 surf->cb_color_slice = S_028C68_TILE_MAX(slice);
1923 surf->cb_color_view = color_view;
1924 surf->cb_color_info = color_info;
1925 surf->cb_color_attrib = color_attrib;
1926
1927 if (sctx->b.chip_class >= VI)
1928 surf->cb_dcc_control = S_028C78_OVERWRITE_COMBINER_DISABLE(1);
1929
1930 if (rtex->fmask.size) {
1931 surf->cb_color_fmask = (offset + rtex->fmask.offset) >> 8;
1932 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max);
1933 } else {
1934 /* This must be set for fast clear to work without FMASK. */
1935 surf->cb_color_fmask = surf->cb_color_base;
1936 surf->cb_color_fmask_slice = surf->cb_color_slice;
1937 surf->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
1938
1939 if (sctx->b.chip_class == SI) {
1940 unsigned bankh = util_logbase2(rtex->surface.bankh);
1941 surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
1942 }
1943
1944 if (sctx->b.chip_class >= CIK) {
1945 surf->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch);
1946 }
1947 }
1948
1949 /* Determine pixel shader export format */
1950 max_comp_size = si_colorformat_max_comp_size(format);
1951 if (ntype == V_028C70_NUMBER_SRGB ||
1952 ((ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM) &&
1953 max_comp_size <= 10) ||
1954 (ntype == V_028C70_NUMBER_FLOAT && max_comp_size <= 16)) {
1955 surf->export_16bpc = true;
1956 }
1957
1958 surf->color_initialized = true;
1959 }
1960
1961 static void si_init_depth_surface(struct si_context *sctx,
1962 struct r600_surface *surf)
1963 {
1964 struct si_screen *sscreen = sctx->screen;
1965 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1966 unsigned level = surf->base.u.tex.level;
1967 struct radeon_surf_level *levelinfo = &rtex->surface.level[level];
1968 unsigned format, tile_mode_index, array_mode;
1969 unsigned macro_aspect, tile_split, stile_split, bankh, bankw, nbanks, pipe_config;
1970 uint32_t z_info, s_info, db_depth_info;
1971 uint64_t z_offs, s_offs;
1972 uint32_t db_htile_data_base, db_htile_surface, pa_su_poly_offset_db_fmt_cntl = 0;
1973
1974 switch (sctx->framebuffer.state.zsbuf->texture->format) {
1975 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1976 case PIPE_FORMAT_X8Z24_UNORM:
1977 case PIPE_FORMAT_Z24X8_UNORM:
1978 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1979 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
1980 break;
1981 case PIPE_FORMAT_Z32_FLOAT:
1982 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1983 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
1984 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1985 break;
1986 case PIPE_FORMAT_Z16_UNORM:
1987 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
1988 break;
1989 default:
1990 assert(0);
1991 }
1992
1993 format = si_translate_dbformat(rtex->resource.b.b.format);
1994
1995 if (format == V_028040_Z_INVALID) {
1996 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
1997 }
1998 assert(format != V_028040_Z_INVALID);
1999
2000 s_offs = z_offs = rtex->resource.gpu_address;
2001 z_offs += rtex->surface.level[level].offset;
2002 s_offs += rtex->surface.stencil_level[level].offset;
2003
2004 db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
2005
2006 z_info = S_028040_FORMAT(format);
2007 if (rtex->resource.b.b.nr_samples > 1) {
2008 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
2009 }
2010
2011 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
2012 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
2013 else
2014 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
2015
2016 if (sctx->b.chip_class >= CIK) {
2017 switch (rtex->surface.level[level].mode) {
2018 case RADEON_SURF_MODE_2D:
2019 array_mode = V_02803C_ARRAY_2D_TILED_THIN1;
2020 break;
2021 case RADEON_SURF_MODE_1D:
2022 case RADEON_SURF_MODE_LINEAR_ALIGNED:
2023 case RADEON_SURF_MODE_LINEAR:
2024 default:
2025 array_mode = V_02803C_ARRAY_1D_TILED_THIN1;
2026 break;
2027 }
2028 tile_split = rtex->surface.tile_split;
2029 stile_split = rtex->surface.stencil_tile_split;
2030 macro_aspect = rtex->surface.mtilea;
2031 bankw = rtex->surface.bankw;
2032 bankh = rtex->surface.bankh;
2033 tile_split = cik_tile_split(tile_split);
2034 stile_split = cik_tile_split(stile_split);
2035 macro_aspect = cik_macro_tile_aspect(macro_aspect);
2036 bankw = cik_bank_wh(bankw);
2037 bankh = cik_bank_wh(bankh);
2038 nbanks = si_num_banks(sscreen, rtex);
2039 tile_mode_index = si_tile_mode_index(rtex, level, false);
2040 pipe_config = cik_db_pipe_config(sscreen, tile_mode_index);
2041
2042 db_depth_info |= S_02803C_ARRAY_MODE(array_mode) |
2043 S_02803C_PIPE_CONFIG(pipe_config) |
2044 S_02803C_BANK_WIDTH(bankw) |
2045 S_02803C_BANK_HEIGHT(bankh) |
2046 S_02803C_MACRO_TILE_ASPECT(macro_aspect) |
2047 S_02803C_NUM_BANKS(nbanks);
2048 z_info |= S_028040_TILE_SPLIT(tile_split);
2049 s_info |= S_028044_TILE_SPLIT(stile_split);
2050 } else {
2051 tile_mode_index = si_tile_mode_index(rtex, level, false);
2052 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2053 tile_mode_index = si_tile_mode_index(rtex, level, true);
2054 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2055 }
2056
2057 /* HiZ aka depth buffer htile */
2058 /* use htile only for first level */
2059 if (rtex->htile_buffer && !level) {
2060 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2061 S_028040_ALLOW_EXPCLEAR(1);
2062
2063 /* Use all of the htile_buffer for depth, because we don't
2064 * use HTILE for stencil because of FAST_STENCIL_DISABLE. */
2065 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2066
2067 uint64_t va = rtex->htile_buffer->gpu_address;
2068 db_htile_data_base = va >> 8;
2069 db_htile_surface = S_028ABC_FULL_CACHE(1);
2070 } else {
2071 db_htile_data_base = 0;
2072 db_htile_surface = 0;
2073 }
2074
2075 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2076
2077 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2078 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2079 surf->db_htile_data_base = db_htile_data_base;
2080 surf->db_depth_info = db_depth_info;
2081 surf->db_z_info = z_info;
2082 surf->db_stencil_info = s_info;
2083 surf->db_depth_base = z_offs >> 8;
2084 surf->db_stencil_base = s_offs >> 8;
2085 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2086 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2087 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2088 levelinfo->nblk_y) / 64 - 1);
2089 surf->db_htile_surface = db_htile_surface;
2090 surf->pa_su_poly_offset_db_fmt_cntl = pa_su_poly_offset_db_fmt_cntl;
2091
2092 surf->depth_initialized = true;
2093 }
2094
2095 static void si_set_framebuffer_state(struct pipe_context *ctx,
2096 const struct pipe_framebuffer_state *state)
2097 {
2098 struct si_context *sctx = (struct si_context *)ctx;
2099 struct pipe_constant_buffer constbuf = {0};
2100 struct r600_surface *surf = NULL;
2101 struct r600_texture *rtex;
2102 bool old_cb0_is_integer = sctx->framebuffer.cb0_is_integer;
2103 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2104 int i;
2105
2106 /* Only flush TC when changing the framebuffer state, because
2107 * the only client not using TC that can change textures is
2108 * the framebuffer.
2109 *
2110 * Flush all CB and DB caches here because all buffers can be used
2111 * for write by both TC (with shader image stores) and CB/DB.
2112 */
2113 sctx->b.flags |= SI_CONTEXT_INV_TC_L1 |
2114 SI_CONTEXT_INV_TC_L2 |
2115 SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER;
2116
2117 /* Take the maximum of the old and new count. If the new count is lower,
2118 * dirtying is needed to disable the unbound colorbuffers.
2119 */
2120 sctx->framebuffer.dirty_cbufs |=
2121 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2122 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2123
2124 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2125
2126 sctx->framebuffer.export_16bpc = 0;
2127 sctx->framebuffer.compressed_cb_mask = 0;
2128 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2129 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2130 sctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
2131 util_format_is_pure_integer(state->cbufs[0]->format);
2132
2133 if (sctx->framebuffer.cb0_is_integer != old_cb0_is_integer)
2134 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2135
2136 for (i = 0; i < state->nr_cbufs; i++) {
2137 if (!state->cbufs[i])
2138 continue;
2139
2140 surf = (struct r600_surface*)state->cbufs[i];
2141 rtex = (struct r600_texture*)surf->base.texture;
2142
2143 if (!surf->color_initialized) {
2144 si_initialize_color_surface(sctx, surf);
2145 }
2146
2147 if (surf->export_16bpc) {
2148 sctx->framebuffer.export_16bpc |= 1 << i;
2149 }
2150
2151 if (rtex->fmask.size && rtex->cmask.size) {
2152 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2153 }
2154 r600_context_add_resource_size(ctx, surf->base.texture);
2155 }
2156 /* Set the 16BPC export for possible dual-src blending. */
2157 if (i == 1 && surf && surf->export_16bpc) {
2158 sctx->framebuffer.export_16bpc |= 1 << 1;
2159 }
2160
2161 assert(!(sctx->framebuffer.export_16bpc & ~0xff));
2162
2163 if (state->zsbuf) {
2164 surf = (struct r600_surface*)state->zsbuf;
2165
2166 if (!surf->depth_initialized) {
2167 si_init_depth_surface(sctx, surf);
2168 }
2169 r600_context_add_resource_size(ctx, surf->base.texture);
2170 }
2171
2172 si_update_poly_offset_state(sctx);
2173 si_mark_atom_dirty(sctx, &sctx->cb_target_mask);
2174 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
2175
2176 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2177 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2178 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2179
2180 /* Set sample locations as fragment shader constants. */
2181 switch (sctx->framebuffer.nr_samples) {
2182 case 1:
2183 constbuf.user_buffer = sctx->b.sample_locations_1x;
2184 break;
2185 case 2:
2186 constbuf.user_buffer = sctx->b.sample_locations_2x;
2187 break;
2188 case 4:
2189 constbuf.user_buffer = sctx->b.sample_locations_4x;
2190 break;
2191 case 8:
2192 constbuf.user_buffer = sctx->b.sample_locations_8x;
2193 break;
2194 case 16:
2195 constbuf.user_buffer = sctx->b.sample_locations_16x;
2196 break;
2197 default:
2198 assert(0);
2199 }
2200 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2201 ctx->set_constant_buffer(ctx, PIPE_SHADER_FRAGMENT,
2202 SI_DRIVER_STATE_CONST_BUF, &constbuf);
2203
2204 /* Smoothing (only possible with nr_samples == 1) uses the same
2205 * sample locations as the MSAA it simulates.
2206 *
2207 * Therefore, don't update the sample locations when
2208 * transitioning from no AA to smoothing-equivalent AA, and
2209 * vice versa.
2210 */
2211 if ((sctx->framebuffer.nr_samples != 1 ||
2212 old_nr_samples != SI_NUM_SMOOTH_AA_SAMPLES) &&
2213 (sctx->framebuffer.nr_samples != SI_NUM_SMOOTH_AA_SAMPLES ||
2214 old_nr_samples != 1))
2215 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs);
2216 }
2217 }
2218
2219 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
2220 {
2221 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
2222 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2223 unsigned i, nr_cbufs = state->nr_cbufs;
2224 struct r600_texture *tex = NULL;
2225 struct r600_surface *cb = NULL;
2226
2227 /* Colorbuffers. */
2228 for (i = 0; i < nr_cbufs; i++) {
2229 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2230 continue;
2231
2232 cb = (struct r600_surface*)state->cbufs[i];
2233 if (!cb) {
2234 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2235 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2236 continue;
2237 }
2238
2239 tex = (struct r600_texture *)cb->base.texture;
2240 radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx,
2241 &tex->resource, RADEON_USAGE_READWRITE,
2242 tex->surface.nsamples > 1 ?
2243 RADEON_PRIO_COLOR_BUFFER_MSAA :
2244 RADEON_PRIO_COLOR_BUFFER);
2245
2246 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2247 radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx,
2248 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2249 RADEON_PRIO_CMASK);
2250 }
2251
2252 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
2253 sctx->b.chip_class >= VI ? 14 : 13);
2254 radeon_emit(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
2255 radeon_emit(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
2256 radeon_emit(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
2257 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
2258 radeon_emit(cs, cb->cb_color_info | tex->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
2259 radeon_emit(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
2260 radeon_emit(cs, cb->cb_dcc_control); /* R_028C78_CB_COLOR0_DCC_CONTROL */
2261 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
2262 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
2263 radeon_emit(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
2264 radeon_emit(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
2265 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
2266 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
2267
2268 if (sctx->b.chip_class >= VI)
2269 radeon_emit(cs, 0); /* R_028C94_CB_COLOR0_DCC_BASE */
2270 }
2271 /* set CB_COLOR1_INFO for possible dual-src blending */
2272 if (i == 1 && state->cbufs[0] &&
2273 sctx->framebuffer.dirty_cbufs & (1 << 0)) {
2274 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
2275 cb->cb_color_info | tex->cb_color_info);
2276 i++;
2277 }
2278 for (; i < 8 ; i++)
2279 if (sctx->framebuffer.dirty_cbufs & (1 << i))
2280 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
2281
2282 /* ZS buffer. */
2283 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
2284 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
2285 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
2286
2287 radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx,
2288 &rtex->resource, RADEON_USAGE_READWRITE,
2289 zb->base.texture->nr_samples > 1 ?
2290 RADEON_PRIO_DEPTH_BUFFER_MSAA :
2291 RADEON_PRIO_DEPTH_BUFFER);
2292
2293 if (zb->db_htile_data_base) {
2294 radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx,
2295 rtex->htile_buffer, RADEON_USAGE_READWRITE,
2296 RADEON_PRIO_HTILE);
2297 }
2298
2299 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
2300 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
2301
2302 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
2303 radeon_emit(cs, zb->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
2304 radeon_emit(cs, zb->db_z_info | /* R_028040_DB_Z_INFO */
2305 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
2306 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
2307 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
2308 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
2309 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
2310 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
2311 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
2312 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
2313
2314 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
2315 radeon_set_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
2316 radeon_set_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2317 zb->pa_su_poly_offset_db_fmt_cntl);
2318 } else if (sctx->framebuffer.dirty_zsbuf) {
2319 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
2320 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
2321 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
2322 }
2323
2324 /* Framebuffer dimensions. */
2325 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2326 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2327 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
2328
2329 sctx->framebuffer.dirty_cbufs = 0;
2330 sctx->framebuffer.dirty_zsbuf = false;
2331 }
2332
2333 static void si_emit_msaa_sample_locs(struct si_context *sctx,
2334 struct r600_atom *atom)
2335 {
2336 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
2337 unsigned nr_samples = sctx->framebuffer.nr_samples;
2338
2339 cayman_emit_msaa_sample_locs(cs, nr_samples > 1 ? nr_samples :
2340 SI_NUM_SMOOTH_AA_SAMPLES);
2341 }
2342
2343 static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom)
2344 {
2345 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
2346
2347 cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples,
2348 sctx->ps_iter_samples,
2349 sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0);
2350 }
2351
2352
2353 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
2354 {
2355 struct si_context *sctx = (struct si_context *)ctx;
2356
2357 if (sctx->ps_iter_samples == min_samples)
2358 return;
2359
2360 sctx->ps_iter_samples = min_samples;
2361
2362 if (sctx->framebuffer.nr_samples > 1)
2363 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2364 }
2365
2366 /*
2367 * Samplers
2368 */
2369
2370 /**
2371 * Create a sampler view.
2372 *
2373 * @param ctx context
2374 * @param texture texture
2375 * @param state sampler view template
2376 * @param width0 width0 override (for compressed textures as int)
2377 * @param height0 height0 override (for compressed textures as int)
2378 * @param force_level set the base address to the level (for compressed textures)
2379 */
2380 struct pipe_sampler_view *
2381 si_create_sampler_view_custom(struct pipe_context *ctx,
2382 struct pipe_resource *texture,
2383 const struct pipe_sampler_view *state,
2384 unsigned width0, unsigned height0,
2385 unsigned force_level)
2386 {
2387 struct si_context *sctx = (struct si_context*)ctx;
2388 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
2389 struct r600_texture *tmp = (struct r600_texture*)texture;
2390 const struct util_format_description *desc;
2391 unsigned format, num_format, base_level, first_level, last_level;
2392 uint32_t pitch = 0;
2393 unsigned char state_swizzle[4], swizzle[4];
2394 unsigned height, depth, width;
2395 enum pipe_format pipe_format = state->format;
2396 struct radeon_surf_level *surflevel;
2397 int first_non_void;
2398 uint64_t va;
2399 unsigned last_layer = state->u.tex.last_layer;
2400
2401 if (view == NULL)
2402 return NULL;
2403
2404 /* initialize base object */
2405 view->base = *state;
2406 view->base.texture = NULL;
2407 view->base.reference.count = 1;
2408 view->base.context = ctx;
2409
2410 /* NULL resource, obey swizzle (only ZERO and ONE make sense). */
2411 if (!texture) {
2412 view->state[3] = S_008F1C_DST_SEL_X(si_map_swizzle(state->swizzle_r)) |
2413 S_008F1C_DST_SEL_Y(si_map_swizzle(state->swizzle_g)) |
2414 S_008F1C_DST_SEL_Z(si_map_swizzle(state->swizzle_b)) |
2415 S_008F1C_DST_SEL_W(si_map_swizzle(state->swizzle_a)) |
2416 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D);
2417 return &view->base;
2418 }
2419
2420 pipe_resource_reference(&view->base.texture, texture);
2421 view->resource = &tmp->resource;
2422
2423 if (state->format == PIPE_FORMAT_X24S8_UINT ||
2424 state->format == PIPE_FORMAT_S8X24_UINT ||
2425 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
2426 state->format == PIPE_FORMAT_S8_UINT)
2427 view->is_stencil_sampler = true;
2428
2429 /* Buffer resource. */
2430 if (texture->target == PIPE_BUFFER) {
2431 unsigned stride, num_records;
2432
2433 desc = util_format_description(state->format);
2434 first_non_void = util_format_get_first_non_void_channel(state->format);
2435 stride = desc->block.bits / 8;
2436 va = tmp->resource.gpu_address + state->u.buf.first_element*stride;
2437 format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
2438 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
2439
2440 num_records = state->u.buf.last_element + 1 - state->u.buf.first_element;
2441 num_records = MIN2(num_records, texture->width0 / stride);
2442
2443 if (sctx->b.chip_class >= VI)
2444 num_records *= stride;
2445
2446 view->state[4] = va;
2447 view->state[5] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
2448 S_008F04_STRIDE(stride);
2449 view->state[6] = num_records;
2450 view->state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2451 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2452 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2453 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2454 S_008F0C_NUM_FORMAT(num_format) |
2455 S_008F0C_DATA_FORMAT(format);
2456
2457 LIST_ADDTAIL(&view->list, &sctx->b.texture_buffers);
2458 return &view->base;
2459 }
2460
2461 state_swizzle[0] = state->swizzle_r;
2462 state_swizzle[1] = state->swizzle_g;
2463 state_swizzle[2] = state->swizzle_b;
2464 state_swizzle[3] = state->swizzle_a;
2465
2466 surflevel = tmp->surface.level;
2467
2468 /* Texturing with separate depth and stencil. */
2469 if (tmp->is_depth && !tmp->is_flushing_texture) {
2470 switch (pipe_format) {
2471 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2472 pipe_format = PIPE_FORMAT_Z32_FLOAT;
2473 break;
2474 case PIPE_FORMAT_X8Z24_UNORM:
2475 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2476 /* Z24 is always stored like this. */
2477 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
2478 break;
2479 case PIPE_FORMAT_X24S8_UINT:
2480 case PIPE_FORMAT_S8X24_UINT:
2481 case PIPE_FORMAT_X32_S8X24_UINT:
2482 pipe_format = PIPE_FORMAT_S8_UINT;
2483 surflevel = tmp->surface.stencil_level;
2484 break;
2485 default:;
2486 }
2487 }
2488
2489 desc = util_format_description(pipe_format);
2490
2491 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2492 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2493 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2494
2495 switch (pipe_format) {
2496 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2497 case PIPE_FORMAT_X24S8_UINT:
2498 case PIPE_FORMAT_X32_S8X24_UINT:
2499 case PIPE_FORMAT_X8Z24_UNORM:
2500 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
2501 break;
2502 default:
2503 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
2504 }
2505 } else {
2506 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2507 }
2508
2509 first_non_void = util_format_get_first_non_void_channel(pipe_format);
2510
2511 switch (pipe_format) {
2512 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2513 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2514 break;
2515 default:
2516 if (first_non_void < 0) {
2517 if (util_format_is_compressed(pipe_format)) {
2518 switch (pipe_format) {
2519 case PIPE_FORMAT_DXT1_SRGB:
2520 case PIPE_FORMAT_DXT1_SRGBA:
2521 case PIPE_FORMAT_DXT3_SRGBA:
2522 case PIPE_FORMAT_DXT5_SRGBA:
2523 case PIPE_FORMAT_BPTC_SRGBA:
2524 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2525 break;
2526 case PIPE_FORMAT_RGTC1_SNORM:
2527 case PIPE_FORMAT_LATC1_SNORM:
2528 case PIPE_FORMAT_RGTC2_SNORM:
2529 case PIPE_FORMAT_LATC2_SNORM:
2530 /* implies float, so use SNORM/UNORM to determine
2531 whether data is signed or not */
2532 case PIPE_FORMAT_BPTC_RGB_FLOAT:
2533 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2534 break;
2535 default:
2536 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2537 break;
2538 }
2539 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
2540 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2541 } else {
2542 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2543 }
2544 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
2545 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2546 } else {
2547 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2548
2549 switch (desc->channel[first_non_void].type) {
2550 case UTIL_FORMAT_TYPE_FLOAT:
2551 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2552 break;
2553 case UTIL_FORMAT_TYPE_SIGNED:
2554 if (desc->channel[first_non_void].normalized)
2555 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2556 else if (desc->channel[first_non_void].pure_integer)
2557 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
2558 else
2559 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
2560 break;
2561 case UTIL_FORMAT_TYPE_UNSIGNED:
2562 if (desc->channel[first_non_void].normalized)
2563 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2564 else if (desc->channel[first_non_void].pure_integer)
2565 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
2566 else
2567 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
2568 }
2569 }
2570 }
2571
2572 format = si_translate_texformat(ctx->screen, pipe_format, desc, first_non_void);
2573 if (format == ~0) {
2574 format = 0;
2575 }
2576
2577 base_level = 0;
2578 first_level = state->u.tex.first_level;
2579 last_level = state->u.tex.last_level;
2580 width = width0;
2581 height = height0;
2582 depth = texture->depth0;
2583
2584 if (force_level) {
2585 assert(force_level == first_level &&
2586 force_level == last_level);
2587 base_level = force_level;
2588 first_level = 0;
2589 last_level = 0;
2590 width = u_minify(width, force_level);
2591 height = u_minify(height, force_level);
2592 depth = u_minify(depth, force_level);
2593 }
2594
2595 pitch = surflevel[base_level].nblk_x * util_format_get_blockwidth(pipe_format);
2596
2597 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
2598 height = 1;
2599 depth = texture->array_size;
2600 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
2601 depth = texture->array_size;
2602 } else if (texture->target == PIPE_TEXTURE_CUBE_ARRAY)
2603 depth = texture->array_size / 6;
2604
2605 /* This is not needed if state trackers set last_layer correctly. */
2606 if (state->target == PIPE_TEXTURE_1D ||
2607 state->target == PIPE_TEXTURE_2D ||
2608 state->target == PIPE_TEXTURE_RECT ||
2609 state->target == PIPE_TEXTURE_CUBE)
2610 last_layer = state->u.tex.first_layer;
2611
2612 va = tmp->resource.gpu_address + surflevel[base_level].offset;
2613
2614 view->state[0] = va >> 8;
2615 view->state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) |
2616 S_008F14_DATA_FORMAT(format) |
2617 S_008F14_NUM_FORMAT(num_format));
2618 view->state[2] = (S_008F18_WIDTH(width - 1) |
2619 S_008F18_HEIGHT(height - 1));
2620 view->state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2621 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2622 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2623 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2624 S_008F1C_BASE_LEVEL(texture->nr_samples > 1 ?
2625 0 : first_level) |
2626 S_008F1C_LAST_LEVEL(texture->nr_samples > 1 ?
2627 util_logbase2(texture->nr_samples) :
2628 last_level) |
2629 S_008F1C_TILING_INDEX(si_tile_mode_index(tmp, base_level, false)) |
2630 S_008F1C_POW2_PAD(texture->last_level > 0) |
2631 S_008F1C_TYPE(si_tex_dim(texture->target, state->target,
2632 texture->nr_samples)));
2633 view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
2634 view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2635 S_008F24_LAST_ARRAY(last_layer));
2636 view->state[6] = 0;
2637 view->state[7] = 0;
2638
2639 /* Initialize the sampler view for FMASK. */
2640 if (tmp->fmask.size) {
2641 uint64_t va = tmp->resource.gpu_address + tmp->fmask.offset;
2642 uint32_t fmask_format;
2643
2644 switch (texture->nr_samples) {
2645 case 2:
2646 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
2647 break;
2648 case 4:
2649 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
2650 break;
2651 case 8:
2652 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
2653 break;
2654 default:
2655 assert(0);
2656 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
2657 }
2658
2659 view->fmask_state[0] = va >> 8;
2660 view->fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
2661 S_008F14_DATA_FORMAT(fmask_format) |
2662 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT);
2663 view->fmask_state[2] = S_008F18_WIDTH(width - 1) |
2664 S_008F18_HEIGHT(height - 1);
2665 view->fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
2666 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
2667 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
2668 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
2669 S_008F1C_TILING_INDEX(tmp->fmask.tile_mode_index) |
2670 S_008F1C_TYPE(si_tex_dim(texture->target,
2671 state->target, 0));
2672 view->fmask_state[4] = S_008F20_DEPTH(depth - 1) |
2673 S_008F20_PITCH(tmp->fmask.pitch - 1);
2674 view->fmask_state[5] = S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2675 S_008F24_LAST_ARRAY(last_layer);
2676 view->fmask_state[6] = 0;
2677 view->fmask_state[7] = 0;
2678 }
2679
2680 return &view->base;
2681 }
2682
2683 static struct pipe_sampler_view *
2684 si_create_sampler_view(struct pipe_context *ctx,
2685 struct pipe_resource *texture,
2686 const struct pipe_sampler_view *state)
2687 {
2688 return si_create_sampler_view_custom(ctx, texture, state,
2689 texture ? texture->width0 : 0,
2690 texture ? texture->height0 : 0, 0);
2691 }
2692
2693 static void si_sampler_view_destroy(struct pipe_context *ctx,
2694 struct pipe_sampler_view *state)
2695 {
2696 struct si_sampler_view *view = (struct si_sampler_view *)state;
2697
2698 if (view->resource && view->resource->b.b.target == PIPE_BUFFER)
2699 LIST_DELINIT(&view->list);
2700
2701 pipe_resource_reference(&state->texture, NULL);
2702 FREE(view);
2703 }
2704
2705 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
2706 {
2707 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
2708 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
2709 (linear_filter &&
2710 (wrap == PIPE_TEX_WRAP_CLAMP ||
2711 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
2712 }
2713
2714 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
2715 {
2716 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
2717 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
2718
2719 return (state->border_color.ui[0] || state->border_color.ui[1] ||
2720 state->border_color.ui[2] || state->border_color.ui[3]) &&
2721 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
2722 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
2723 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
2724 }
2725
2726 static void *si_create_sampler_state(struct pipe_context *ctx,
2727 const struct pipe_sampler_state *state)
2728 {
2729 struct si_context *sctx = (struct si_context *)ctx;
2730 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
2731 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
2732 unsigned border_color_type, border_color_index = 0;
2733
2734 if (rstate == NULL) {
2735 return NULL;
2736 }
2737
2738 if (!sampler_state_needs_border_color(state))
2739 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
2740 else if (state->border_color.f[0] == 0 &&
2741 state->border_color.f[1] == 0 &&
2742 state->border_color.f[2] == 0 &&
2743 state->border_color.f[3] == 0)
2744 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
2745 else if (state->border_color.f[0] == 0 &&
2746 state->border_color.f[1] == 0 &&
2747 state->border_color.f[2] == 0 &&
2748 state->border_color.f[3] == 1)
2749 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
2750 else if (state->border_color.f[0] == 1 &&
2751 state->border_color.f[1] == 1 &&
2752 state->border_color.f[2] == 1 &&
2753 state->border_color.f[3] == 1)
2754 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
2755 else {
2756 int i;
2757
2758 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
2759
2760 /* Check if the border has been uploaded already. */
2761 for (i = 0; i < sctx->border_color_count; i++)
2762 if (memcmp(&sctx->border_color_table[i], &state->border_color,
2763 sizeof(state->border_color)) == 0)
2764 break;
2765
2766 if (i >= SI_MAX_BORDER_COLORS) {
2767 /* Getting 4096 unique border colors is very unlikely. */
2768 fprintf(stderr, "radeonsi: The border color table is full. "
2769 "Any new border colors will be just black. "
2770 "Please file a bug.\n");
2771 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
2772 } else {
2773 if (i == sctx->border_color_count) {
2774 /* Upload a new border color. */
2775 memcpy(&sctx->border_color_table[i], &state->border_color,
2776 sizeof(state->border_color));
2777 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
2778 &state->border_color,
2779 sizeof(state->border_color));
2780 sctx->border_color_count++;
2781 }
2782
2783 border_color_index = i;
2784 }
2785 }
2786
2787 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
2788 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
2789 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
2790 r600_tex_aniso_filter(state->max_anisotropy) << 9 |
2791 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
2792 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
2793 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map));
2794 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
2795 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
2796 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
2797 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
2798 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter) | aniso_flag_offset) |
2799 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)));
2800 rstate->val[3] = S_008F3C_BORDER_COLOR_PTR(border_color_index) |
2801 S_008F3C_BORDER_COLOR_TYPE(border_color_type);
2802 return rstate;
2803 }
2804
2805 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
2806 {
2807 struct si_context *sctx = (struct si_context *)ctx;
2808
2809 if (sctx->sample_mask.sample_mask == (uint16_t)sample_mask)
2810 return;
2811
2812 sctx->sample_mask.sample_mask = sample_mask;
2813 si_mark_atom_dirty(sctx, &sctx->sample_mask.atom);
2814 }
2815
2816 static void si_emit_sample_mask(struct si_context *sctx, struct r600_atom *atom)
2817 {
2818 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
2819 unsigned mask = sctx->sample_mask.sample_mask;
2820
2821 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
2822 radeon_emit(cs, mask | (mask << 16));
2823 radeon_emit(cs, mask | (mask << 16));
2824 }
2825
2826 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
2827 {
2828 free(state);
2829 }
2830
2831 /*
2832 * Vertex elements & buffers
2833 */
2834
2835 static void *si_create_vertex_elements(struct pipe_context *ctx,
2836 unsigned count,
2837 const struct pipe_vertex_element *elements)
2838 {
2839 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
2840 int i;
2841
2842 assert(count < SI_MAX_ATTRIBS);
2843 if (!v)
2844 return NULL;
2845
2846 v->count = count;
2847 for (i = 0; i < count; ++i) {
2848 const struct util_format_description *desc;
2849 unsigned data_format, num_format;
2850 int first_non_void;
2851
2852 desc = util_format_description(elements[i].src_format);
2853 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
2854 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
2855 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
2856
2857 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2858 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2859 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2860 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2861 S_008F0C_NUM_FORMAT(num_format) |
2862 S_008F0C_DATA_FORMAT(data_format);
2863 v->format_size[i] = desc->block.bits / 8;
2864 }
2865 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
2866
2867 return v;
2868 }
2869
2870 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
2871 {
2872 struct si_context *sctx = (struct si_context *)ctx;
2873 struct si_vertex_element *v = (struct si_vertex_element*)state;
2874
2875 sctx->vertex_elements = v;
2876 sctx->vertex_buffers_dirty = true;
2877 }
2878
2879 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
2880 {
2881 struct si_context *sctx = (struct si_context *)ctx;
2882
2883 if (sctx->vertex_elements == state)
2884 sctx->vertex_elements = NULL;
2885 FREE(state);
2886 }
2887
2888 static void si_set_vertex_buffers(struct pipe_context *ctx,
2889 unsigned start_slot, unsigned count,
2890 const struct pipe_vertex_buffer *buffers)
2891 {
2892 struct si_context *sctx = (struct si_context *)ctx;
2893 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
2894 int i;
2895
2896 assert(start_slot + count <= Elements(sctx->vertex_buffer));
2897
2898 if (buffers) {
2899 for (i = 0; i < count; i++) {
2900 const struct pipe_vertex_buffer *src = buffers + i;
2901 struct pipe_vertex_buffer *dsti = dst + i;
2902
2903 pipe_resource_reference(&dsti->buffer, src->buffer);
2904 dsti->buffer_offset = src->buffer_offset;
2905 dsti->stride = src->stride;
2906 r600_context_add_resource_size(ctx, src->buffer);
2907 }
2908 } else {
2909 for (i = 0; i < count; i++) {
2910 pipe_resource_reference(&dst[i].buffer, NULL);
2911 }
2912 }
2913 sctx->vertex_buffers_dirty = true;
2914 }
2915
2916 static void si_set_index_buffer(struct pipe_context *ctx,
2917 const struct pipe_index_buffer *ib)
2918 {
2919 struct si_context *sctx = (struct si_context *)ctx;
2920
2921 if (ib) {
2922 pipe_resource_reference(&sctx->index_buffer.buffer, ib->buffer);
2923 memcpy(&sctx->index_buffer, ib, sizeof(*ib));
2924 r600_context_add_resource_size(ctx, ib->buffer);
2925 } else {
2926 pipe_resource_reference(&sctx->index_buffer.buffer, NULL);
2927 }
2928 }
2929
2930 /*
2931 * Misc
2932 */
2933 static void si_set_polygon_stipple(struct pipe_context *ctx,
2934 const struct pipe_poly_stipple *state)
2935 {
2936 struct si_context *sctx = (struct si_context *)ctx;
2937 struct pipe_resource *tex;
2938 struct pipe_sampler_view *view;
2939 bool is_zero = true;
2940 bool is_one = true;
2941 int i;
2942
2943 /* The hardware obeys 0 and 1 swizzles in the descriptor even if
2944 * the resource is NULL/invalid. Take advantage of this fact and skip
2945 * texture allocation if the stipple pattern is constant.
2946 *
2947 * This is an optimization for the common case when stippling isn't
2948 * used but set_polygon_stipple is still called by st/mesa.
2949 */
2950 for (i = 0; i < Elements(state->stipple); i++) {
2951 is_zero = is_zero && state->stipple[i] == 0;
2952 is_one = is_one && state->stipple[i] == 0xffffffff;
2953 }
2954
2955 if (is_zero || is_one) {
2956 struct pipe_sampler_view templ = {{0}};
2957
2958 templ.swizzle_r = PIPE_SWIZZLE_ZERO;
2959 templ.swizzle_g = PIPE_SWIZZLE_ZERO;
2960 templ.swizzle_b = PIPE_SWIZZLE_ZERO;
2961 /* The pattern should be inverted in the texture. */
2962 templ.swizzle_a = is_zero ? PIPE_SWIZZLE_ONE : PIPE_SWIZZLE_ZERO;
2963
2964 view = ctx->create_sampler_view(ctx, NULL, &templ);
2965 } else {
2966 /* Create a new texture. */
2967 tex = util_pstipple_create_stipple_texture(ctx, state->stipple);
2968 if (!tex)
2969 return;
2970
2971 view = util_pstipple_create_sampler_view(ctx, tex);
2972 pipe_resource_reference(&tex, NULL);
2973 }
2974
2975 ctx->set_sampler_views(ctx, PIPE_SHADER_FRAGMENT,
2976 SI_POLY_STIPPLE_SAMPLER, 1, &view);
2977 pipe_sampler_view_reference(&view, NULL);
2978
2979 /* Bind the sampler state if needed. */
2980 if (!sctx->pstipple_sampler_state) {
2981 sctx->pstipple_sampler_state = util_pstipple_create_sampler(ctx);
2982 ctx->bind_sampler_states(ctx, PIPE_SHADER_FRAGMENT,
2983 SI_POLY_STIPPLE_SAMPLER, 1,
2984 &sctx->pstipple_sampler_state);
2985 }
2986 }
2987
2988 static void si_set_tess_state(struct pipe_context *ctx,
2989 const float default_outer_level[4],
2990 const float default_inner_level[2])
2991 {
2992 struct si_context *sctx = (struct si_context *)ctx;
2993 struct pipe_constant_buffer cb;
2994 float array[8];
2995
2996 memcpy(array, default_outer_level, sizeof(float) * 4);
2997 memcpy(array+4, default_inner_level, sizeof(float) * 2);
2998
2999 cb.buffer = NULL;
3000 cb.user_buffer = NULL;
3001 cb.buffer_size = sizeof(array);
3002
3003 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
3004 (void*)array, sizeof(array),
3005 &cb.buffer_offset);
3006
3007 ctx->set_constant_buffer(ctx, PIPE_SHADER_TESS_CTRL,
3008 SI_DRIVER_STATE_CONST_BUF, &cb);
3009 pipe_resource_reference(&cb.buffer, NULL);
3010 }
3011
3012 static void si_texture_barrier(struct pipe_context *ctx)
3013 {
3014 struct si_context *sctx = (struct si_context *)ctx;
3015
3016 sctx->b.flags |= SI_CONTEXT_INV_TC_L1 |
3017 SI_CONTEXT_INV_TC_L2 |
3018 SI_CONTEXT_FLUSH_AND_INV_CB;
3019 }
3020
3021 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
3022 {
3023 struct pipe_blend_state blend;
3024
3025 memset(&blend, 0, sizeof(blend));
3026 blend.independent_blend_enable = true;
3027 blend.rt[0].colormask = 0xf;
3028 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
3029 }
3030
3031 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
3032 bool include_draw_vbo)
3033 {
3034 si_need_cs_space((struct si_context*)ctx);
3035 }
3036
3037 static void si_init_config(struct si_context *sctx);
3038
3039 void si_init_state_functions(struct si_context *sctx)
3040 {
3041 si_init_external_atom(sctx, &sctx->b.streamout.begin_atom, &sctx->atoms.s.streamout_begin);
3042 si_init_external_atom(sctx, &sctx->b.streamout.enable_atom, &sctx->atoms.s.streamout_enable);
3043
3044 si_init_atom(sctx, &sctx->cache_flush, &sctx->atoms.s.cache_flush, si_emit_cache_flush);
3045 si_init_atom(sctx, &sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state);
3046 si_init_atom(sctx, &sctx->msaa_sample_locs, &sctx->atoms.s.msaa_sample_locs, si_emit_msaa_sample_locs);
3047 si_init_atom(sctx, &sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state);
3048 si_init_atom(sctx, &sctx->msaa_config, &sctx->atoms.s.msaa_config, si_emit_msaa_config);
3049 si_init_atom(sctx, &sctx->sample_mask.atom, &sctx->atoms.s.sample_mask, si_emit_sample_mask);
3050 si_init_atom(sctx, &sctx->cb_target_mask, &sctx->atoms.s.cb_target_mask, si_emit_cb_target_mask);
3051 si_init_atom(sctx, &sctx->blend_color.atom, &sctx->atoms.s.blend_color, si_emit_blend_color);
3052 si_init_atom(sctx, &sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs);
3053 si_init_atom(sctx, &sctx->clip_state.atom, &sctx->atoms.s.clip_state, si_emit_clip_state);
3054 si_init_atom(sctx, &sctx->scissors.atom, &sctx->atoms.s.scissors, si_emit_scissors);
3055 si_init_atom(sctx, &sctx->viewports.atom, &sctx->atoms.s.viewports, si_emit_viewports);
3056 si_init_atom(sctx, &sctx->stencil_ref.atom, &sctx->atoms.s.stencil_ref, si_emit_stencil_ref);
3057
3058 sctx->b.b.create_blend_state = si_create_blend_state;
3059 sctx->b.b.bind_blend_state = si_bind_blend_state;
3060 sctx->b.b.delete_blend_state = si_delete_blend_state;
3061 sctx->b.b.set_blend_color = si_set_blend_color;
3062
3063 sctx->b.b.create_rasterizer_state = si_create_rs_state;
3064 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
3065 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
3066
3067 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
3068 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
3069 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
3070
3071 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
3072 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
3073 sctx->custom_blend_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
3074 sctx->custom_blend_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
3075
3076 sctx->b.b.set_clip_state = si_set_clip_state;
3077 sctx->b.b.set_scissor_states = si_set_scissor_states;
3078 sctx->b.b.set_viewport_states = si_set_viewport_states;
3079 sctx->b.b.set_stencil_ref = si_set_stencil_ref;
3080
3081 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
3082 sctx->b.b.get_sample_position = cayman_get_sample_position;
3083
3084 sctx->b.b.create_sampler_state = si_create_sampler_state;
3085 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
3086
3087 sctx->b.b.create_sampler_view = si_create_sampler_view;
3088 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
3089
3090 sctx->b.b.set_sample_mask = si_set_sample_mask;
3091
3092 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
3093 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
3094 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
3095 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
3096 sctx->b.b.set_index_buffer = si_set_index_buffer;
3097
3098 sctx->b.b.texture_barrier = si_texture_barrier;
3099 sctx->b.b.set_polygon_stipple = si_set_polygon_stipple;
3100 sctx->b.b.set_min_samples = si_set_min_samples;
3101 sctx->b.b.set_tess_state = si_set_tess_state;
3102
3103 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
3104 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
3105
3106 sctx->b.b.draw_vbo = si_draw_vbo;
3107
3108 if (sctx->b.chip_class >= CIK) {
3109 sctx->b.dma_copy = cik_sdma_copy;
3110 } else {
3111 sctx->b.dma_copy = si_dma_copy;
3112 }
3113
3114 si_init_config(sctx);
3115 }
3116
3117 static void
3118 si_write_harvested_raster_configs(struct si_context *sctx,
3119 struct si_pm4_state *pm4,
3120 unsigned raster_config,
3121 unsigned raster_config_1)
3122 {
3123 unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1);
3124 unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1);
3125 unsigned rb_mask = sctx->screen->b.info.si_backend_enabled_mask;
3126 unsigned num_rb = MIN2(sctx->screen->b.info.r600_num_backends, 16);
3127 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
3128 unsigned rb_per_se = num_rb / num_se;
3129 unsigned se_mask[4];
3130 unsigned se;
3131
3132 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
3133 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
3134 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
3135 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
3136
3137 assert(num_se == 1 || num_se == 2 || num_se == 4);
3138 assert(sh_per_se == 1 || sh_per_se == 2);
3139 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
3140
3141 /* XXX: I can't figure out what the *_XSEL and *_YSEL
3142 * fields are for, so I'm leaving them as their default
3143 * values. */
3144
3145 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
3146 (!se_mask[2] && !se_mask[3]))) {
3147 raster_config_1 &= C_028354_SE_PAIR_MAP;
3148
3149 if (!se_mask[0] && !se_mask[1]) {
3150 raster_config_1 |=
3151 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
3152 } else {
3153 raster_config_1 |=
3154 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
3155 }
3156 }
3157
3158 for (se = 0; se < num_se; se++) {
3159 unsigned raster_config_se = raster_config;
3160 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
3161 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
3162 int idx = (se / 2) * 2;
3163
3164 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
3165 raster_config_se &= C_028350_SE_MAP;
3166
3167 if (!se_mask[idx]) {
3168 raster_config_se |=
3169 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
3170 } else {
3171 raster_config_se |=
3172 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
3173 }
3174 }
3175
3176 pkr0_mask &= rb_mask;
3177 pkr1_mask &= rb_mask;
3178 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
3179 raster_config_se &= C_028350_PKR_MAP;
3180
3181 if (!pkr0_mask) {
3182 raster_config_se |=
3183 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
3184 } else {
3185 raster_config_se |=
3186 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
3187 }
3188 }
3189
3190 if (rb_per_se >= 2) {
3191 unsigned rb0_mask = 1 << (se * rb_per_se);
3192 unsigned rb1_mask = rb0_mask << 1;
3193
3194 rb0_mask &= rb_mask;
3195 rb1_mask &= rb_mask;
3196 if (!rb0_mask || !rb1_mask) {
3197 raster_config_se &= C_028350_RB_MAP_PKR0;
3198
3199 if (!rb0_mask) {
3200 raster_config_se |=
3201 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
3202 } else {
3203 raster_config_se |=
3204 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
3205 }
3206 }
3207
3208 if (rb_per_se > 2) {
3209 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
3210 rb1_mask = rb0_mask << 1;
3211 rb0_mask &= rb_mask;
3212 rb1_mask &= rb_mask;
3213 if (!rb0_mask || !rb1_mask) {
3214 raster_config_se &= C_028350_RB_MAP_PKR1;
3215
3216 if (!rb0_mask) {
3217 raster_config_se |=
3218 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
3219 } else {
3220 raster_config_se |=
3221 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
3222 }
3223 }
3224 }
3225 }
3226
3227 /* GRBM_GFX_INDEX is privileged on VI */
3228 if (sctx->b.chip_class <= CIK)
3229 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3230 SE_INDEX(se) | SH_BROADCAST_WRITES |
3231 INSTANCE_BROADCAST_WRITES);
3232 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
3233 if (sctx->b.chip_class >= CIK)
3234 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
3235 }
3236
3237 /* GRBM_GFX_INDEX is privileged on VI */
3238 if (sctx->b.chip_class <= CIK)
3239 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3240 SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
3241 INSTANCE_BROADCAST_WRITES);
3242 }
3243
3244 static void si_init_config(struct si_context *sctx)
3245 {
3246 unsigned num_rb = MIN2(sctx->screen->b.info.r600_num_backends, 16);
3247 unsigned rb_mask = sctx->screen->b.info.si_backend_enabled_mask;
3248 unsigned raster_config, raster_config_1;
3249 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
3250 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3251 int i;
3252
3253 if (pm4 == NULL)
3254 return;
3255
3256 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
3257 si_pm4_cmd_add(pm4, 0x80000000);
3258 si_pm4_cmd_add(pm4, 0x80000000);
3259 si_pm4_cmd_end(pm4, false);
3260
3261 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
3262 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
3263
3264 /* FIXME calculate these values somehow ??? */
3265 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, 0x80);
3266 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
3267 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
3268
3269 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
3270 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3271
3272 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
3273 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0);
3274 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
3275 if (sctx->b.chip_class < CIK)
3276 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
3277 S_008A14_CLIP_VTX_REORDER_ENA(1));
3278
3279 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
3280 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
3281
3282 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
3283
3284 for (i = 0; i < 16; i++) {
3285 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0);
3286 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0));
3287 }
3288
3289 switch (sctx->screen->b.family) {
3290 case CHIP_TAHITI:
3291 case CHIP_PITCAIRN:
3292 raster_config = 0x2a00126a;
3293 raster_config_1 = 0x00000000;
3294 break;
3295 case CHIP_VERDE:
3296 raster_config = 0x0000124a;
3297 raster_config_1 = 0x00000000;
3298 break;
3299 case CHIP_OLAND:
3300 raster_config = 0x00000082;
3301 raster_config_1 = 0x00000000;
3302 break;
3303 case CHIP_HAINAN:
3304 raster_config = 0x00000000;
3305 raster_config_1 = 0x00000000;
3306 break;
3307 case CHIP_BONAIRE:
3308 raster_config = 0x16000012;
3309 raster_config_1 = 0x00000000;
3310 break;
3311 case CHIP_HAWAII:
3312 raster_config = 0x3a00161a;
3313 raster_config_1 = 0x0000002e;
3314 break;
3315 case CHIP_FIJI:
3316 /* Fiji should be same as Hawaii, but that causes corruption in some cases */
3317 raster_config = 0x16000012; /* 0x3a00161a */
3318 raster_config_1 = 0x0000002a; /* 0x0000002e */
3319 break;
3320 case CHIP_TONGA:
3321 raster_config = 0x16000012;
3322 raster_config_1 = 0x0000002a;
3323 break;
3324 case CHIP_ICELAND:
3325 raster_config = 0x00000002;
3326 raster_config_1 = 0x00000000;
3327 break;
3328 case CHIP_CARRIZO:
3329 raster_config = 0x00000002;
3330 raster_config_1 = 0x00000000;
3331 break;
3332 case CHIP_KAVERI:
3333 /* KV should be 0x00000002, but that causes problems with radeon */
3334 raster_config = 0x00000000; /* 0x00000002 */
3335 raster_config_1 = 0x00000000;
3336 break;
3337 case CHIP_KABINI:
3338 case CHIP_MULLINS:
3339 raster_config = 0x00000000;
3340 raster_config_1 = 0x00000000;
3341 break;
3342 default:
3343 fprintf(stderr,
3344 "radeonsi: Unknown GPU, using 0 for raster_config\n");
3345 raster_config = 0x00000000;
3346 raster_config_1 = 0x00000000;
3347 break;
3348 }
3349
3350 /* Always use the default config when all backends are enabled
3351 * (or when we failed to determine the enabled backends).
3352 */
3353 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
3354 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
3355 raster_config);
3356 if (sctx->b.chip_class >= CIK)
3357 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
3358 raster_config_1);
3359 } else {
3360 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
3361 }
3362
3363 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
3364 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
3365 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
3366 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
3367 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
3368 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
3369 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
3370
3371 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
3372 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
3373 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
3374 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
3375 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
3376 si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, fui(1.0));
3377 si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, fui(1.0));
3378 si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, fui(1.0));
3379 si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, fui(1.0));
3380 si_pm4_set_reg(pm4, R_028028_DB_STENCIL_CLEAR, 0);
3381 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
3382 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
3383 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
3384
3385 /* There is a hang if stencil is used and fast stencil is enabled
3386 * regardless of whether HTILE is depth-only or not.
3387 */
3388 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE,
3389 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3390 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE) |
3391 S_02800C_FAST_STENCIL_DISABLE(1));
3392
3393 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
3394 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
3395 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
3396
3397 if (sctx->b.chip_class >= CIK) {
3398 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xfffc));
3399 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
3400 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xfffe));
3401 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
3402 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
3403 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(0));
3404 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
3405 }
3406
3407 if (sctx->b.chip_class >= VI) {
3408 si_pm4_set_reg(pm4, R_028424_CB_DCC_CONTROL,
3409 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1));
3410 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
3411 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
3412 }
3413
3414 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
3415 if (sctx->b.chip_class >= CIK)
3416 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, border_color_va >> 40);
3417 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
3418 RADEON_PRIO_BORDER_COLORS);
3419
3420 si_pm4_upload_indirect_buffer(sctx, pm4);
3421 sctx->init_config = pm4;
3422 }