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radeonsi: clean up decompress blend state names
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "sid.h"
29 #include "gfx9d.h"
30 #include "radeon/r600_cs.h"
31 #include "radeon/r600_query.h"
32
33 #include "util/u_dual_blend.h"
34 #include "util/u_format.h"
35 #include "util/u_format_s3tc.h"
36 #include "util/u_memory.h"
37 #include "util/u_resource.h"
38 #include "util/u_upload_mgr.h"
39
40 /* Initialize an external atom (owned by ../radeon). */
41 static void
42 si_init_external_atom(struct si_context *sctx, struct r600_atom *atom,
43 struct r600_atom **list_elem)
44 {
45 atom->id = list_elem - sctx->atoms.array;
46 *list_elem = atom;
47 }
48
49 /* Initialize an atom owned by radeonsi. */
50 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
51 struct r600_atom **list_elem,
52 void (*emit_func)(struct si_context *ctx, struct r600_atom *state))
53 {
54 atom->emit = (void*)emit_func;
55 atom->id = list_elem - sctx->atoms.array;
56 *list_elem = atom;
57 }
58
59 static unsigned si_map_swizzle(unsigned swizzle)
60 {
61 switch (swizzle) {
62 case PIPE_SWIZZLE_Y:
63 return V_008F0C_SQ_SEL_Y;
64 case PIPE_SWIZZLE_Z:
65 return V_008F0C_SQ_SEL_Z;
66 case PIPE_SWIZZLE_W:
67 return V_008F0C_SQ_SEL_W;
68 case PIPE_SWIZZLE_0:
69 return V_008F0C_SQ_SEL_0;
70 case PIPE_SWIZZLE_1:
71 return V_008F0C_SQ_SEL_1;
72 default: /* PIPE_SWIZZLE_X */
73 return V_008F0C_SQ_SEL_X;
74 }
75 }
76
77 static uint32_t S_FIXED(float value, uint32_t frac_bits)
78 {
79 return value * (1 << frac_bits);
80 }
81
82 /* 12.4 fixed-point */
83 static unsigned si_pack_float_12p4(float x)
84 {
85 return x <= 0 ? 0 :
86 x >= 4096 ? 0xffff : x * 16;
87 }
88
89 /*
90 * Inferred framebuffer and blender state.
91 *
92 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
93 * if there is not enough PS outputs.
94 */
95 static void si_emit_cb_render_state(struct si_context *sctx, struct r600_atom *atom)
96 {
97 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
98 struct si_state_blend *blend = sctx->queued.named.blend;
99 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
100 * but you never know. */
101 uint32_t cb_target_mask = sctx->framebuffer.colorbuf_enabled_4bit;
102 unsigned i;
103
104 if (blend)
105 cb_target_mask &= blend->cb_target_mask;
106
107 /* Avoid a hang that happens when dual source blending is enabled
108 * but there is not enough color outputs. This is undefined behavior,
109 * so disable color writes completely.
110 *
111 * Reproducible with Unigine Heaven 4.0 and drirc missing.
112 */
113 if (blend && blend->dual_src_blend &&
114 sctx->ps_shader.cso &&
115 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
116 cb_target_mask = 0;
117
118 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, cb_target_mask);
119
120 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
121 * I think we don't have to do anything between IBs.
122 */
123 if (sctx->b.chip_class >= GFX9 &&
124 sctx->last_cb_target_mask != cb_target_mask) {
125 sctx->last_cb_target_mask = cb_target_mask;
126
127 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
128 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
129 }
130
131 /* RB+ register settings. */
132 if (sctx->screen->b.rbplus_allowed) {
133 unsigned spi_shader_col_format =
134 sctx->ps_shader.cso ?
135 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format : 0;
136 unsigned sx_ps_downconvert = 0;
137 unsigned sx_blend_opt_epsilon = 0;
138 unsigned sx_blend_opt_control = 0;
139
140 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
141 struct r600_surface *surf =
142 (struct r600_surface*)sctx->framebuffer.state.cbufs[i];
143 unsigned format, swap, spi_format, colormask;
144 bool has_alpha, has_rgb;
145
146 if (!surf)
147 continue;
148
149 format = G_028C70_FORMAT(surf->cb_color_info);
150 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
151 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
152 colormask = (cb_target_mask >> (i * 4)) & 0xf;
153
154 /* Set if RGB and A are present. */
155 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
156
157 if (format == V_028C70_COLOR_8 ||
158 format == V_028C70_COLOR_16 ||
159 format == V_028C70_COLOR_32)
160 has_rgb = !has_alpha;
161 else
162 has_rgb = true;
163
164 /* Check the colormask and export format. */
165 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
166 has_rgb = false;
167 if (!(colormask & PIPE_MASK_A))
168 has_alpha = false;
169
170 if (spi_format == V_028714_SPI_SHADER_ZERO) {
171 has_rgb = false;
172 has_alpha = false;
173 }
174
175 /* Disable value checking for disabled channels. */
176 if (!has_rgb)
177 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
178 if (!has_alpha)
179 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
180
181 /* Enable down-conversion for 32bpp and smaller formats. */
182 switch (format) {
183 case V_028C70_COLOR_8:
184 case V_028C70_COLOR_8_8:
185 case V_028C70_COLOR_8_8_8_8:
186 /* For 1 and 2-channel formats, use the superset thereof. */
187 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
188 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
189 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
190 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
191 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
192 }
193 break;
194
195 case V_028C70_COLOR_5_6_5:
196 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
197 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
198 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
199 }
200 break;
201
202 case V_028C70_COLOR_1_5_5_5:
203 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
204 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
205 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
206 }
207 break;
208
209 case V_028C70_COLOR_4_4_4_4:
210 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
211 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
212 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
213 }
214 break;
215
216 case V_028C70_COLOR_32:
217 if (swap == V_0280A0_SWAP_STD &&
218 spi_format == V_028714_SPI_SHADER_32_R)
219 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
220 else if (swap == V_0280A0_SWAP_ALT_REV &&
221 spi_format == V_028714_SPI_SHADER_32_AR)
222 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
223 break;
224
225 case V_028C70_COLOR_16:
226 case V_028C70_COLOR_16_16:
227 /* For 1-channel formats, use the superset thereof. */
228 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
229 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
230 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
231 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
232 if (swap == V_0280A0_SWAP_STD ||
233 swap == V_0280A0_SWAP_STD_REV)
234 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
235 else
236 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
237 }
238 break;
239
240 case V_028C70_COLOR_10_11_11:
241 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
242 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
243 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
244 }
245 break;
246
247 case V_028C70_COLOR_2_10_10_10:
248 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
249 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
250 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
251 }
252 break;
253 }
254 }
255
256 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
257 radeon_emit(cs, sx_ps_downconvert); /* R_028754_SX_PS_DOWNCONVERT */
258 radeon_emit(cs, sx_blend_opt_epsilon); /* R_028758_SX_BLEND_OPT_EPSILON */
259 radeon_emit(cs, sx_blend_opt_control); /* R_02875C_SX_BLEND_OPT_CONTROL */
260 } else if (sctx->screen->b.has_rbplus) {
261 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
262 radeon_emit(cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
263 radeon_emit(cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
264 radeon_emit(cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
265 }
266 }
267
268 /*
269 * Blender functions
270 */
271
272 static uint32_t si_translate_blend_function(int blend_func)
273 {
274 switch (blend_func) {
275 case PIPE_BLEND_ADD:
276 return V_028780_COMB_DST_PLUS_SRC;
277 case PIPE_BLEND_SUBTRACT:
278 return V_028780_COMB_SRC_MINUS_DST;
279 case PIPE_BLEND_REVERSE_SUBTRACT:
280 return V_028780_COMB_DST_MINUS_SRC;
281 case PIPE_BLEND_MIN:
282 return V_028780_COMB_MIN_DST_SRC;
283 case PIPE_BLEND_MAX:
284 return V_028780_COMB_MAX_DST_SRC;
285 default:
286 R600_ERR("Unknown blend function %d\n", blend_func);
287 assert(0);
288 break;
289 }
290 return 0;
291 }
292
293 static uint32_t si_translate_blend_factor(int blend_fact)
294 {
295 switch (blend_fact) {
296 case PIPE_BLENDFACTOR_ONE:
297 return V_028780_BLEND_ONE;
298 case PIPE_BLENDFACTOR_SRC_COLOR:
299 return V_028780_BLEND_SRC_COLOR;
300 case PIPE_BLENDFACTOR_SRC_ALPHA:
301 return V_028780_BLEND_SRC_ALPHA;
302 case PIPE_BLENDFACTOR_DST_ALPHA:
303 return V_028780_BLEND_DST_ALPHA;
304 case PIPE_BLENDFACTOR_DST_COLOR:
305 return V_028780_BLEND_DST_COLOR;
306 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
307 return V_028780_BLEND_SRC_ALPHA_SATURATE;
308 case PIPE_BLENDFACTOR_CONST_COLOR:
309 return V_028780_BLEND_CONSTANT_COLOR;
310 case PIPE_BLENDFACTOR_CONST_ALPHA:
311 return V_028780_BLEND_CONSTANT_ALPHA;
312 case PIPE_BLENDFACTOR_ZERO:
313 return V_028780_BLEND_ZERO;
314 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
315 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
316 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
317 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
318 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
319 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
320 case PIPE_BLENDFACTOR_INV_DST_COLOR:
321 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
322 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
323 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
324 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
325 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
326 case PIPE_BLENDFACTOR_SRC1_COLOR:
327 return V_028780_BLEND_SRC1_COLOR;
328 case PIPE_BLENDFACTOR_SRC1_ALPHA:
329 return V_028780_BLEND_SRC1_ALPHA;
330 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
331 return V_028780_BLEND_INV_SRC1_COLOR;
332 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
333 return V_028780_BLEND_INV_SRC1_ALPHA;
334 default:
335 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
336 assert(0);
337 break;
338 }
339 return 0;
340 }
341
342 static uint32_t si_translate_blend_opt_function(int blend_func)
343 {
344 switch (blend_func) {
345 case PIPE_BLEND_ADD:
346 return V_028760_OPT_COMB_ADD;
347 case PIPE_BLEND_SUBTRACT:
348 return V_028760_OPT_COMB_SUBTRACT;
349 case PIPE_BLEND_REVERSE_SUBTRACT:
350 return V_028760_OPT_COMB_REVSUBTRACT;
351 case PIPE_BLEND_MIN:
352 return V_028760_OPT_COMB_MIN;
353 case PIPE_BLEND_MAX:
354 return V_028760_OPT_COMB_MAX;
355 default:
356 return V_028760_OPT_COMB_BLEND_DISABLED;
357 }
358 }
359
360 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
361 {
362 switch (blend_fact) {
363 case PIPE_BLENDFACTOR_ZERO:
364 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
365 case PIPE_BLENDFACTOR_ONE:
366 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
367 case PIPE_BLENDFACTOR_SRC_COLOR:
368 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
369 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
370 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
371 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
372 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
373 case PIPE_BLENDFACTOR_SRC_ALPHA:
374 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
375 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
376 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
377 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
378 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
379 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
380 default:
381 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
382 }
383 }
384
385 /**
386 * Get rid of DST in the blend factors by commuting the operands:
387 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
388 */
389 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
390 unsigned *dst_factor, unsigned expected_dst,
391 unsigned replacement_src)
392 {
393 if (*src_factor == expected_dst &&
394 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
395 *src_factor = PIPE_BLENDFACTOR_ZERO;
396 *dst_factor = replacement_src;
397
398 /* Commuting the operands requires reversing subtractions. */
399 if (*func == PIPE_BLEND_SUBTRACT)
400 *func = PIPE_BLEND_REVERSE_SUBTRACT;
401 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
402 *func = PIPE_BLEND_SUBTRACT;
403 }
404 }
405
406 static bool si_blend_factor_uses_dst(unsigned factor)
407 {
408 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
409 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
410 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
411 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
412 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
413 }
414
415 static void *si_create_blend_state_mode(struct pipe_context *ctx,
416 const struct pipe_blend_state *state,
417 unsigned mode)
418 {
419 struct si_context *sctx = (struct si_context*)ctx;
420 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
421 struct si_pm4_state *pm4 = &blend->pm4;
422 uint32_t sx_mrt_blend_opt[8] = {0};
423 uint32_t color_control = 0;
424
425 if (!blend)
426 return NULL;
427
428 blend->alpha_to_coverage = state->alpha_to_coverage;
429 blend->alpha_to_one = state->alpha_to_one;
430 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
431
432 if (state->logicop_enable) {
433 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
434 } else {
435 color_control |= S_028808_ROP3(0xcc);
436 }
437
438 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
439 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
440 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
441 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
442 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
443 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
444
445 if (state->alpha_to_coverage)
446 blend->need_src_alpha_4bit |= 0xf;
447
448 blend->cb_target_mask = 0;
449 for (int i = 0; i < 8; i++) {
450 /* state->rt entries > 0 only written if independent blending */
451 const int j = state->independent_blend_enable ? i : 0;
452
453 unsigned eqRGB = state->rt[j].rgb_func;
454 unsigned srcRGB = state->rt[j].rgb_src_factor;
455 unsigned dstRGB = state->rt[j].rgb_dst_factor;
456 unsigned eqA = state->rt[j].alpha_func;
457 unsigned srcA = state->rt[j].alpha_src_factor;
458 unsigned dstA = state->rt[j].alpha_dst_factor;
459
460 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
461 unsigned blend_cntl = 0;
462
463 sx_mrt_blend_opt[i] =
464 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
465 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
466
467 /* Only set dual source blending for MRT0 to avoid a hang. */
468 if (i >= 1 && blend->dual_src_blend) {
469 /* Vulkan does this for dual source blending. */
470 if (i == 1)
471 blend_cntl |= S_028780_ENABLE(1);
472
473 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
474 continue;
475 }
476
477 /* Only addition and subtraction equations are supported with
478 * dual source blending.
479 */
480 if (blend->dual_src_blend &&
481 (eqRGB == PIPE_BLEND_MIN || eqRGB == PIPE_BLEND_MAX ||
482 eqA == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MAX)) {
483 assert(!"Unsupported equation for dual source blending");
484 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
485 continue;
486 }
487
488 /* cb_render_state will disable unused ones */
489 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
490
491 if (!state->rt[j].colormask || !state->rt[j].blend_enable) {
492 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
493 continue;
494 }
495
496 /* Blending optimizations for RB+.
497 * These transformations don't change the behavior.
498 *
499 * First, get rid of DST in the blend factors:
500 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
501 */
502 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
503 PIPE_BLENDFACTOR_DST_COLOR,
504 PIPE_BLENDFACTOR_SRC_COLOR);
505 si_blend_remove_dst(&eqA, &srcA, &dstA,
506 PIPE_BLENDFACTOR_DST_COLOR,
507 PIPE_BLENDFACTOR_SRC_COLOR);
508 si_blend_remove_dst(&eqA, &srcA, &dstA,
509 PIPE_BLENDFACTOR_DST_ALPHA,
510 PIPE_BLENDFACTOR_SRC_ALPHA);
511
512 /* Look up the ideal settings from tables. */
513 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
514 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
515 srcA_opt = si_translate_blend_opt_factor(srcA, true);
516 dstA_opt = si_translate_blend_opt_factor(dstA, true);
517
518 /* Handle interdependencies. */
519 if (si_blend_factor_uses_dst(srcRGB))
520 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
521 if (si_blend_factor_uses_dst(srcA))
522 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
523
524 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
525 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
526 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
527 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
528 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
529
530 /* Set the final value. */
531 sx_mrt_blend_opt[i] =
532 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
533 S_028760_COLOR_DST_OPT(dstRGB_opt) |
534 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
535 S_028760_ALPHA_SRC_OPT(srcA_opt) |
536 S_028760_ALPHA_DST_OPT(dstA_opt) |
537 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
538
539 /* Set blend state. */
540 blend_cntl |= S_028780_ENABLE(1);
541 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
542 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
543 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
544
545 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
546 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
547 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
548 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
549 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
550 }
551 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
552
553 blend->blend_enable_4bit |= 0xfu << (i * 4);
554
555 /* This is only important for formats without alpha. */
556 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
557 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
558 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
559 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
560 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
561 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
562 blend->need_src_alpha_4bit |= 0xfu << (i * 4);
563 }
564
565 if (blend->cb_target_mask) {
566 color_control |= S_028808_MODE(mode);
567 } else {
568 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
569 }
570
571 if (sctx->screen->b.has_rbplus) {
572 /* Disable RB+ blend optimizations for dual source blending.
573 * Vulkan does this.
574 */
575 if (blend->dual_src_blend) {
576 for (int i = 0; i < 8; i++) {
577 sx_mrt_blend_opt[i] =
578 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
579 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
580 }
581 }
582
583 for (int i = 0; i < 8; i++)
584 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
585 sx_mrt_blend_opt[i]);
586
587 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
588 if (blend->dual_src_blend || state->logicop_enable ||
589 mode == V_028808_CB_RESOLVE)
590 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
591 }
592
593 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
594 return blend;
595 }
596
597 static void *si_create_blend_state(struct pipe_context *ctx,
598 const struct pipe_blend_state *state)
599 {
600 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
601 }
602
603 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
604 {
605 struct si_context *sctx = (struct si_context *)ctx;
606 si_pm4_bind_state(sctx, blend, (struct si_state_blend *)state);
607 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
608 sctx->do_update_shaders = true;
609 }
610
611 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
612 {
613 struct si_context *sctx = (struct si_context *)ctx;
614 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
615 }
616
617 static void si_set_blend_color(struct pipe_context *ctx,
618 const struct pipe_blend_color *state)
619 {
620 struct si_context *sctx = (struct si_context *)ctx;
621
622 sctx->blend_color.state = *state;
623 si_mark_atom_dirty(sctx, &sctx->blend_color.atom);
624 }
625
626 static void si_emit_blend_color(struct si_context *sctx, struct r600_atom *atom)
627 {
628 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
629
630 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
631 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
632 }
633
634 /*
635 * Clipping
636 */
637
638 static void si_set_clip_state(struct pipe_context *ctx,
639 const struct pipe_clip_state *state)
640 {
641 struct si_context *sctx = (struct si_context *)ctx;
642 struct pipe_constant_buffer cb;
643
644 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
645 return;
646
647 sctx->clip_state.state = *state;
648 si_mark_atom_dirty(sctx, &sctx->clip_state.atom);
649
650 cb.buffer = NULL;
651 cb.user_buffer = state->ucp;
652 cb.buffer_offset = 0;
653 cb.buffer_size = 4*4*8;
654 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
655 pipe_resource_reference(&cb.buffer, NULL);
656 }
657
658 static void si_emit_clip_state(struct si_context *sctx, struct r600_atom *atom)
659 {
660 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
661
662 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
663 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
664 }
665
666 #define SIX_BITS 0x3F
667
668 static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom)
669 {
670 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
671 struct si_shader *vs = si_get_vs_state(sctx);
672 struct tgsi_shader_info *info = si_get_vs_info(sctx);
673 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
674 unsigned window_space =
675 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
676 unsigned clipdist_mask =
677 info->writes_clipvertex ? SIX_BITS : info->clipdist_writemask;
678 unsigned ucp_mask = clipdist_mask ? 0 : rs->clip_plane_enable & SIX_BITS;
679 unsigned culldist_mask = info->culldist_writemask << info->num_written_clipdistance;
680 unsigned total_mask;
681 bool misc_vec_ena;
682
683 if (vs->key.opt.hw_vs.clip_disable) {
684 assert(!info->culldist_writemask);
685 clipdist_mask = 0;
686 culldist_mask = 0;
687 }
688 total_mask = clipdist_mask | culldist_mask;
689
690 /* Clip distances on points have no effect, so need to be implemented
691 * as cull distances. This applies for the clipvertex case as well.
692 *
693 * Setting this for primitives other than points should have no adverse
694 * effects.
695 */
696 clipdist_mask &= rs->clip_plane_enable;
697 culldist_mask |= clipdist_mask;
698
699 misc_vec_ena = info->writes_psize || info->writes_edgeflag ||
700 info->writes_layer || info->writes_viewport_index;
701
702 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
703 S_02881C_USE_VTX_POINT_SIZE(info->writes_psize) |
704 S_02881C_USE_VTX_EDGE_FLAG(info->writes_edgeflag) |
705 S_02881C_USE_VTX_RENDER_TARGET_INDX(info->writes_layer) |
706 S_02881C_USE_VTX_VIEWPORT_INDX(info->writes_viewport_index) |
707 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0F) != 0) |
708 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xF0) != 0) |
709 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
710 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
711 clipdist_mask | (culldist_mask << 8));
712 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
713 rs->pa_cl_clip_cntl |
714 ucp_mask |
715 S_028810_CLIP_DISABLE(window_space));
716
717 if (sctx->b.chip_class <= VI) {
718 /* reuse needs to be set off if we write oViewport */
719 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF,
720 S_028AB4_REUSE_OFF(info->writes_viewport_index));
721 }
722 }
723
724 /*
725 * inferred state between framebuffer and rasterizer
726 */
727 static void si_update_poly_offset_state(struct si_context *sctx)
728 {
729 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
730
731 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf) {
732 si_pm4_bind_state(sctx, poly_offset, NULL);
733 return;
734 }
735
736 /* Use the user format, not db_render_format, so that the polygon
737 * offset behaves as expected by applications.
738 */
739 switch (sctx->framebuffer.state.zsbuf->texture->format) {
740 case PIPE_FORMAT_Z16_UNORM:
741 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
742 break;
743 default: /* 24-bit */
744 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
745 break;
746 case PIPE_FORMAT_Z32_FLOAT:
747 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
748 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
749 break;
750 }
751 }
752
753 /*
754 * Rasterizer
755 */
756
757 static uint32_t si_translate_fill(uint32_t func)
758 {
759 switch(func) {
760 case PIPE_POLYGON_MODE_FILL:
761 return V_028814_X_DRAW_TRIANGLES;
762 case PIPE_POLYGON_MODE_LINE:
763 return V_028814_X_DRAW_LINES;
764 case PIPE_POLYGON_MODE_POINT:
765 return V_028814_X_DRAW_POINTS;
766 default:
767 assert(0);
768 return V_028814_X_DRAW_POINTS;
769 }
770 }
771
772 static void *si_create_rs_state(struct pipe_context *ctx,
773 const struct pipe_rasterizer_state *state)
774 {
775 struct si_screen *sscreen = ((struct si_context *)ctx)->screen;
776 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
777 struct si_pm4_state *pm4 = &rs->pm4;
778 unsigned tmp, i;
779 float psize_min, psize_max;
780
781 if (!rs) {
782 return NULL;
783 }
784
785 rs->scissor_enable = state->scissor;
786 rs->clip_halfz = state->clip_halfz;
787 rs->two_side = state->light_twoside;
788 rs->multisample_enable = state->multisample;
789 rs->force_persample_interp = state->force_persample_interp;
790 rs->clip_plane_enable = state->clip_plane_enable;
791 rs->line_stipple_enable = state->line_stipple_enable;
792 rs->poly_stipple_enable = state->poly_stipple_enable;
793 rs->line_smooth = state->line_smooth;
794 rs->poly_smooth = state->poly_smooth;
795 rs->uses_poly_offset = state->offset_point || state->offset_line ||
796 state->offset_tri;
797 rs->clamp_fragment_color = state->clamp_fragment_color;
798 rs->clamp_vertex_color = state->clamp_vertex_color;
799 rs->flatshade = state->flatshade;
800 rs->sprite_coord_enable = state->sprite_coord_enable;
801 rs->rasterizer_discard = state->rasterizer_discard;
802 rs->pa_sc_line_stipple = state->line_stipple_enable ?
803 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
804 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
805 rs->pa_cl_clip_cntl =
806 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
807 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
808 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
809 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
810 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
811
812 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
813 S_0286D4_FLAT_SHADE_ENA(1) |
814 S_0286D4_PNT_SPRITE_ENA(1) |
815 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
816 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
817 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
818 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
819 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
820
821 /* point size 12.4 fixed point */
822 tmp = (unsigned)(state->point_size * 8.0);
823 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
824
825 if (state->point_size_per_vertex) {
826 psize_min = util_get_min_point_size(state);
827 psize_max = 8192;
828 } else {
829 /* Force the point size to be as if the vertex output was disabled. */
830 psize_min = state->point_size;
831 psize_max = state->point_size;
832 }
833 /* Divide by two, because 0.5 = 1 pixel. */
834 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
835 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
836 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
837
838 tmp = (unsigned)state->line_width * 8;
839 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
840 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
841 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
842 S_028A48_MSAA_ENABLE(state->multisample ||
843 state->poly_smooth ||
844 state->line_smooth) |
845 S_028A48_VPORT_SCISSOR_ENABLE(1) |
846 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen->b.chip_class >= GFX9));
847
848 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
849 S_028BE4_PIX_CENTER(state->half_pixel_center) |
850 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
851
852 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
853 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
854 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
855 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
856 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
857 S_028814_FACE(!state->front_ccw) |
858 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
859 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
860 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
861 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
862 state->fill_back != PIPE_POLYGON_MODE_FILL) |
863 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
864 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
865
866 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
867 for (i = 0; i < 3; i++) {
868 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
869 float offset_units = state->offset_units;
870 float offset_scale = state->offset_scale * 16.0f;
871 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
872
873 if (!state->offset_units_unscaled) {
874 switch (i) {
875 case 0: /* 16-bit zbuffer */
876 offset_units *= 4.0f;
877 pa_su_poly_offset_db_fmt_cntl =
878 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
879 break;
880 case 1: /* 24-bit zbuffer */
881 offset_units *= 2.0f;
882 pa_su_poly_offset_db_fmt_cntl =
883 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
884 break;
885 case 2: /* 32-bit zbuffer */
886 offset_units *= 1.0f;
887 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
888 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
889 break;
890 }
891 }
892
893 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
894 fui(offset_scale));
895 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
896 fui(offset_units));
897 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
898 fui(offset_scale));
899 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
900 fui(offset_units));
901 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
902 pa_su_poly_offset_db_fmt_cntl);
903 }
904
905 return rs;
906 }
907
908 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
909 {
910 struct si_context *sctx = (struct si_context *)ctx;
911 struct si_state_rasterizer *old_rs =
912 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
913 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
914
915 if (!state)
916 return;
917
918 if (!old_rs || old_rs->multisample_enable != rs->multisample_enable) {
919 si_mark_atom_dirty(sctx, &sctx->db_render_state);
920
921 /* Update the small primitive filter workaround if necessary. */
922 if (sctx->screen->has_msaa_sample_loc_bug &&
923 sctx->framebuffer.nr_samples > 1)
924 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
925 }
926
927 sctx->current_vs_state &= C_VS_STATE_CLAMP_VERTEX_COLOR;
928 sctx->current_vs_state |= S_VS_STATE_CLAMP_VERTEX_COLOR(rs->clamp_vertex_color);
929
930 r600_viewport_set_rast_deps(&sctx->b, rs->scissor_enable, rs->clip_halfz);
931
932 si_pm4_bind_state(sctx, rasterizer, rs);
933 si_update_poly_offset_state(sctx);
934
935 si_mark_atom_dirty(sctx, &sctx->clip_regs);
936 sctx->ia_multi_vgt_param_key.u.line_stipple_enabled =
937 rs->line_stipple_enable;
938 sctx->do_update_shaders = true;
939 }
940
941 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
942 {
943 struct si_context *sctx = (struct si_context *)ctx;
944
945 if (sctx->queued.named.rasterizer == state)
946 si_pm4_bind_state(sctx, poly_offset, NULL);
947 si_pm4_delete_state(sctx, rasterizer, (struct si_state_rasterizer *)state);
948 }
949
950 /*
951 * infeered state between dsa and stencil ref
952 */
953 static void si_emit_stencil_ref(struct si_context *sctx, struct r600_atom *atom)
954 {
955 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
956 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
957 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
958
959 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
960 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
961 S_028430_STENCILMASK(dsa->valuemask[0]) |
962 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
963 S_028430_STENCILOPVAL(1));
964 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
965 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
966 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
967 S_028434_STENCILOPVAL_BF(1));
968 }
969
970 static void si_set_stencil_ref(struct pipe_context *ctx,
971 const struct pipe_stencil_ref *state)
972 {
973 struct si_context *sctx = (struct si_context *)ctx;
974
975 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
976 return;
977
978 sctx->stencil_ref.state = *state;
979 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
980 }
981
982
983 /*
984 * DSA
985 */
986
987 static uint32_t si_translate_stencil_op(int s_op)
988 {
989 switch (s_op) {
990 case PIPE_STENCIL_OP_KEEP:
991 return V_02842C_STENCIL_KEEP;
992 case PIPE_STENCIL_OP_ZERO:
993 return V_02842C_STENCIL_ZERO;
994 case PIPE_STENCIL_OP_REPLACE:
995 return V_02842C_STENCIL_REPLACE_TEST;
996 case PIPE_STENCIL_OP_INCR:
997 return V_02842C_STENCIL_ADD_CLAMP;
998 case PIPE_STENCIL_OP_DECR:
999 return V_02842C_STENCIL_SUB_CLAMP;
1000 case PIPE_STENCIL_OP_INCR_WRAP:
1001 return V_02842C_STENCIL_ADD_WRAP;
1002 case PIPE_STENCIL_OP_DECR_WRAP:
1003 return V_02842C_STENCIL_SUB_WRAP;
1004 case PIPE_STENCIL_OP_INVERT:
1005 return V_02842C_STENCIL_INVERT;
1006 default:
1007 R600_ERR("Unknown stencil op %d", s_op);
1008 assert(0);
1009 break;
1010 }
1011 return 0;
1012 }
1013
1014 static void *si_create_dsa_state(struct pipe_context *ctx,
1015 const struct pipe_depth_stencil_alpha_state *state)
1016 {
1017 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
1018 struct si_pm4_state *pm4 = &dsa->pm4;
1019 unsigned db_depth_control;
1020 uint32_t db_stencil_control = 0;
1021
1022 if (!dsa) {
1023 return NULL;
1024 }
1025
1026 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
1027 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
1028 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
1029 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
1030
1031 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
1032 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
1033 S_028800_ZFUNC(state->depth.func) |
1034 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
1035
1036 /* stencil */
1037 if (state->stencil[0].enabled) {
1038 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1039 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
1040 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
1041 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
1042 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
1043
1044 if (state->stencil[1].enabled) {
1045 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1046 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1047 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
1048 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
1049 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
1050 }
1051 }
1052
1053 /* alpha */
1054 if (state->alpha.enabled) {
1055 dsa->alpha_func = state->alpha.func;
1056
1057 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1058 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
1059 } else {
1060 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1061 }
1062
1063 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1064 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1065 if (state->depth.bounds_test) {
1066 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1067 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1068 }
1069
1070 return dsa;
1071 }
1072
1073 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1074 {
1075 struct si_context *sctx = (struct si_context *)ctx;
1076 struct si_state_dsa *dsa = state;
1077
1078 if (!state)
1079 return;
1080
1081 si_pm4_bind_state(sctx, dsa, dsa);
1082
1083 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1084 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1085 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1086 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1087 }
1088 sctx->do_update_shaders = true;
1089 }
1090
1091 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1092 {
1093 struct si_context *sctx = (struct si_context *)ctx;
1094 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1095 }
1096
1097 static void *si_create_db_flush_dsa(struct si_context *sctx)
1098 {
1099 struct pipe_depth_stencil_alpha_state dsa = {};
1100
1101 return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
1102 }
1103
1104 /* DB RENDER STATE */
1105
1106 static void si_set_active_query_state(struct pipe_context *ctx, boolean enable)
1107 {
1108 struct si_context *sctx = (struct si_context*)ctx;
1109
1110 /* Pipeline stat & streamout queries. */
1111 if (enable) {
1112 sctx->b.flags &= ~R600_CONTEXT_STOP_PIPELINE_STATS;
1113 sctx->b.flags |= R600_CONTEXT_START_PIPELINE_STATS;
1114 } else {
1115 sctx->b.flags &= ~R600_CONTEXT_START_PIPELINE_STATS;
1116 sctx->b.flags |= R600_CONTEXT_STOP_PIPELINE_STATS;
1117 }
1118
1119 /* Occlusion queries. */
1120 if (sctx->occlusion_queries_disabled != !enable) {
1121 sctx->occlusion_queries_disabled = !enable;
1122 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1123 }
1124 }
1125
1126 static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
1127 {
1128 struct si_context *sctx = (struct si_context*)ctx;
1129
1130 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1131 }
1132
1133 static void si_save_qbo_state(struct pipe_context *ctx, struct r600_qbo_state *st)
1134 {
1135 struct si_context *sctx = (struct si_context*)ctx;
1136
1137 st->saved_compute = sctx->cs_shader_state.program;
1138
1139 si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1140 si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
1141 }
1142
1143 static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
1144 {
1145 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1146 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1147 unsigned db_shader_control;
1148
1149 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1150
1151 /* DB_RENDER_CONTROL */
1152 if (sctx->dbcb_depth_copy_enabled ||
1153 sctx->dbcb_stencil_copy_enabled) {
1154 radeon_emit(cs,
1155 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1156 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1157 S_028000_COPY_CENTROID(1) |
1158 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
1159 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1160 radeon_emit(cs,
1161 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1162 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace));
1163 } else {
1164 radeon_emit(cs,
1165 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1166 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear));
1167 }
1168
1169 /* DB_COUNT_CONTROL (occlusion queries) */
1170 if (sctx->b.num_occlusion_queries > 0 &&
1171 !sctx->occlusion_queries_disabled) {
1172 bool perfect = sctx->b.num_perfect_occlusion_queries > 0;
1173
1174 if (sctx->b.chip_class >= CIK) {
1175 radeon_emit(cs,
1176 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1177 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
1178 S_028004_ZPASS_ENABLE(1) |
1179 S_028004_SLICE_EVEN_ENABLE(1) |
1180 S_028004_SLICE_ODD_ENABLE(1));
1181 } else {
1182 radeon_emit(cs,
1183 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1184 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
1185 }
1186 } else {
1187 /* Disable occlusion queries. */
1188 if (sctx->b.chip_class >= CIK) {
1189 radeon_emit(cs, 0);
1190 } else {
1191 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
1192 }
1193 }
1194
1195 /* DB_RENDER_OVERRIDE2 */
1196 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
1197 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1198 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1199 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4));
1200
1201 db_shader_control = sctx->ps_db_shader_control;
1202
1203 /* Bug workaround for smoothing (overrasterization) on SI. */
1204 if (sctx->b.chip_class == SI && sctx->smoothing_enabled) {
1205 db_shader_control &= C_02880C_Z_ORDER;
1206 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1207 }
1208
1209 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1210 if (!rs || !rs->multisample_enable)
1211 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1212
1213 if (sctx->screen->b.has_rbplus &&
1214 !sctx->screen->b.rbplus_allowed)
1215 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1216
1217 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
1218 db_shader_control);
1219 }
1220
1221 /*
1222 * format translation
1223 */
1224 static uint32_t si_translate_colorformat(enum pipe_format format)
1225 {
1226 const struct util_format_description *desc = util_format_description(format);
1227
1228 #define HAS_SIZE(x,y,z,w) \
1229 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1230 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1231
1232 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1233 return V_028C70_COLOR_10_11_11;
1234
1235 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1236 return V_028C70_COLOR_INVALID;
1237
1238 /* hw cannot support mixed formats (except depth/stencil, since
1239 * stencil is not written to). */
1240 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1241 return V_028C70_COLOR_INVALID;
1242
1243 switch (desc->nr_channels) {
1244 case 1:
1245 switch (desc->channel[0].size) {
1246 case 8:
1247 return V_028C70_COLOR_8;
1248 case 16:
1249 return V_028C70_COLOR_16;
1250 case 32:
1251 return V_028C70_COLOR_32;
1252 }
1253 break;
1254 case 2:
1255 if (desc->channel[0].size == desc->channel[1].size) {
1256 switch (desc->channel[0].size) {
1257 case 8:
1258 return V_028C70_COLOR_8_8;
1259 case 16:
1260 return V_028C70_COLOR_16_16;
1261 case 32:
1262 return V_028C70_COLOR_32_32;
1263 }
1264 } else if (HAS_SIZE(8,24,0,0)) {
1265 return V_028C70_COLOR_24_8;
1266 } else if (HAS_SIZE(24,8,0,0)) {
1267 return V_028C70_COLOR_8_24;
1268 }
1269 break;
1270 case 3:
1271 if (HAS_SIZE(5,6,5,0)) {
1272 return V_028C70_COLOR_5_6_5;
1273 } else if (HAS_SIZE(32,8,24,0)) {
1274 return V_028C70_COLOR_X24_8_32_FLOAT;
1275 }
1276 break;
1277 case 4:
1278 if (desc->channel[0].size == desc->channel[1].size &&
1279 desc->channel[0].size == desc->channel[2].size &&
1280 desc->channel[0].size == desc->channel[3].size) {
1281 switch (desc->channel[0].size) {
1282 case 4:
1283 return V_028C70_COLOR_4_4_4_4;
1284 case 8:
1285 return V_028C70_COLOR_8_8_8_8;
1286 case 16:
1287 return V_028C70_COLOR_16_16_16_16;
1288 case 32:
1289 return V_028C70_COLOR_32_32_32_32;
1290 }
1291 } else if (HAS_SIZE(5,5,5,1)) {
1292 return V_028C70_COLOR_1_5_5_5;
1293 } else if (HAS_SIZE(10,10,10,2)) {
1294 return V_028C70_COLOR_2_10_10_10;
1295 }
1296 break;
1297 }
1298 return V_028C70_COLOR_INVALID;
1299 }
1300
1301 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1302 {
1303 if (SI_BIG_ENDIAN) {
1304 switch(colorformat) {
1305 /* 8-bit buffers. */
1306 case V_028C70_COLOR_8:
1307 return V_028C70_ENDIAN_NONE;
1308
1309 /* 16-bit buffers. */
1310 case V_028C70_COLOR_5_6_5:
1311 case V_028C70_COLOR_1_5_5_5:
1312 case V_028C70_COLOR_4_4_4_4:
1313 case V_028C70_COLOR_16:
1314 case V_028C70_COLOR_8_8:
1315 return V_028C70_ENDIAN_8IN16;
1316
1317 /* 32-bit buffers. */
1318 case V_028C70_COLOR_8_8_8_8:
1319 case V_028C70_COLOR_2_10_10_10:
1320 case V_028C70_COLOR_8_24:
1321 case V_028C70_COLOR_24_8:
1322 case V_028C70_COLOR_16_16:
1323 return V_028C70_ENDIAN_8IN32;
1324
1325 /* 64-bit buffers. */
1326 case V_028C70_COLOR_16_16_16_16:
1327 return V_028C70_ENDIAN_8IN16;
1328
1329 case V_028C70_COLOR_32_32:
1330 return V_028C70_ENDIAN_8IN32;
1331
1332 /* 128-bit buffers. */
1333 case V_028C70_COLOR_32_32_32_32:
1334 return V_028C70_ENDIAN_8IN32;
1335 default:
1336 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1337 }
1338 } else {
1339 return V_028C70_ENDIAN_NONE;
1340 }
1341 }
1342
1343 static uint32_t si_translate_dbformat(enum pipe_format format)
1344 {
1345 switch (format) {
1346 case PIPE_FORMAT_Z16_UNORM:
1347 return V_028040_Z_16;
1348 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1349 case PIPE_FORMAT_X8Z24_UNORM:
1350 case PIPE_FORMAT_Z24X8_UNORM:
1351 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1352 return V_028040_Z_24; /* deprecated on SI */
1353 case PIPE_FORMAT_Z32_FLOAT:
1354 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1355 return V_028040_Z_32_FLOAT;
1356 default:
1357 return V_028040_Z_INVALID;
1358 }
1359 }
1360
1361 /*
1362 * Texture translation
1363 */
1364
1365 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1366 enum pipe_format format,
1367 const struct util_format_description *desc,
1368 int first_non_void)
1369 {
1370 struct si_screen *sscreen = (struct si_screen*)screen;
1371 bool enable_compressed_formats = (sscreen->b.info.drm_major == 2 &&
1372 sscreen->b.info.drm_minor >= 31) ||
1373 sscreen->b.info.drm_major == 3;
1374 bool uniform = true;
1375 int i;
1376
1377 /* Colorspace (return non-RGB formats directly). */
1378 switch (desc->colorspace) {
1379 /* Depth stencil formats */
1380 case UTIL_FORMAT_COLORSPACE_ZS:
1381 switch (format) {
1382 case PIPE_FORMAT_Z16_UNORM:
1383 return V_008F14_IMG_DATA_FORMAT_16;
1384 case PIPE_FORMAT_X24S8_UINT:
1385 case PIPE_FORMAT_S8X24_UINT:
1386 /*
1387 * Implemented as an 8_8_8_8 data format to fix texture
1388 * gathers in stencil sampling. This affects at least
1389 * GL45-CTS.texture_cube_map_array.sampling on VI.
1390 */
1391 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1392 case PIPE_FORMAT_Z24X8_UNORM:
1393 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1394 return V_008F14_IMG_DATA_FORMAT_8_24;
1395 case PIPE_FORMAT_X8Z24_UNORM:
1396 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1397 return V_008F14_IMG_DATA_FORMAT_24_8;
1398 case PIPE_FORMAT_S8_UINT:
1399 return V_008F14_IMG_DATA_FORMAT_8;
1400 case PIPE_FORMAT_Z32_FLOAT:
1401 return V_008F14_IMG_DATA_FORMAT_32;
1402 case PIPE_FORMAT_X32_S8X24_UINT:
1403 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1404 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1405 default:
1406 goto out_unknown;
1407 }
1408
1409 case UTIL_FORMAT_COLORSPACE_YUV:
1410 goto out_unknown; /* TODO */
1411
1412 case UTIL_FORMAT_COLORSPACE_SRGB:
1413 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1414 goto out_unknown;
1415 break;
1416
1417 default:
1418 break;
1419 }
1420
1421 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1422 if (!enable_compressed_formats)
1423 goto out_unknown;
1424
1425 switch (format) {
1426 case PIPE_FORMAT_RGTC1_SNORM:
1427 case PIPE_FORMAT_LATC1_SNORM:
1428 case PIPE_FORMAT_RGTC1_UNORM:
1429 case PIPE_FORMAT_LATC1_UNORM:
1430 return V_008F14_IMG_DATA_FORMAT_BC4;
1431 case PIPE_FORMAT_RGTC2_SNORM:
1432 case PIPE_FORMAT_LATC2_SNORM:
1433 case PIPE_FORMAT_RGTC2_UNORM:
1434 case PIPE_FORMAT_LATC2_UNORM:
1435 return V_008F14_IMG_DATA_FORMAT_BC5;
1436 default:
1437 goto out_unknown;
1438 }
1439 }
1440
1441 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1442 (sscreen->b.family == CHIP_STONEY ||
1443 sscreen->b.chip_class >= GFX9)) {
1444 switch (format) {
1445 case PIPE_FORMAT_ETC1_RGB8:
1446 case PIPE_FORMAT_ETC2_RGB8:
1447 case PIPE_FORMAT_ETC2_SRGB8:
1448 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1449 case PIPE_FORMAT_ETC2_RGB8A1:
1450 case PIPE_FORMAT_ETC2_SRGB8A1:
1451 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1452 case PIPE_FORMAT_ETC2_RGBA8:
1453 case PIPE_FORMAT_ETC2_SRGBA8:
1454 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1455 case PIPE_FORMAT_ETC2_R11_UNORM:
1456 case PIPE_FORMAT_ETC2_R11_SNORM:
1457 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1458 case PIPE_FORMAT_ETC2_RG11_UNORM:
1459 case PIPE_FORMAT_ETC2_RG11_SNORM:
1460 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1461 default:
1462 goto out_unknown;
1463 }
1464 }
1465
1466 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1467 if (!enable_compressed_formats)
1468 goto out_unknown;
1469
1470 switch (format) {
1471 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1472 case PIPE_FORMAT_BPTC_SRGBA:
1473 return V_008F14_IMG_DATA_FORMAT_BC7;
1474 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1475 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1476 return V_008F14_IMG_DATA_FORMAT_BC6;
1477 default:
1478 goto out_unknown;
1479 }
1480 }
1481
1482 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1483 switch (format) {
1484 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1485 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1486 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1487 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1488 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1489 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1490 default:
1491 goto out_unknown;
1492 }
1493 }
1494
1495 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1496 if (!enable_compressed_formats)
1497 goto out_unknown;
1498
1499 if (!util_format_s3tc_enabled) {
1500 goto out_unknown;
1501 }
1502
1503 switch (format) {
1504 case PIPE_FORMAT_DXT1_RGB:
1505 case PIPE_FORMAT_DXT1_RGBA:
1506 case PIPE_FORMAT_DXT1_SRGB:
1507 case PIPE_FORMAT_DXT1_SRGBA:
1508 return V_008F14_IMG_DATA_FORMAT_BC1;
1509 case PIPE_FORMAT_DXT3_RGBA:
1510 case PIPE_FORMAT_DXT3_SRGBA:
1511 return V_008F14_IMG_DATA_FORMAT_BC2;
1512 case PIPE_FORMAT_DXT5_RGBA:
1513 case PIPE_FORMAT_DXT5_SRGBA:
1514 return V_008F14_IMG_DATA_FORMAT_BC3;
1515 default:
1516 goto out_unknown;
1517 }
1518 }
1519
1520 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1521 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1522 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1523 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1524 }
1525
1526 /* R8G8Bx_SNORM - TODO CxV8U8 */
1527
1528 /* hw cannot support mixed formats (except depth/stencil, since only
1529 * depth is read).*/
1530 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1531 goto out_unknown;
1532
1533 /* See whether the components are of the same size. */
1534 for (i = 1; i < desc->nr_channels; i++) {
1535 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1536 }
1537
1538 /* Non-uniform formats. */
1539 if (!uniform) {
1540 switch(desc->nr_channels) {
1541 case 3:
1542 if (desc->channel[0].size == 5 &&
1543 desc->channel[1].size == 6 &&
1544 desc->channel[2].size == 5) {
1545 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1546 }
1547 goto out_unknown;
1548 case 4:
1549 if (desc->channel[0].size == 5 &&
1550 desc->channel[1].size == 5 &&
1551 desc->channel[2].size == 5 &&
1552 desc->channel[3].size == 1) {
1553 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1554 }
1555 if (desc->channel[0].size == 10 &&
1556 desc->channel[1].size == 10 &&
1557 desc->channel[2].size == 10 &&
1558 desc->channel[3].size == 2) {
1559 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1560 }
1561 goto out_unknown;
1562 }
1563 goto out_unknown;
1564 }
1565
1566 if (first_non_void < 0 || first_non_void > 3)
1567 goto out_unknown;
1568
1569 /* uniform formats */
1570 switch (desc->channel[first_non_void].size) {
1571 case 4:
1572 switch (desc->nr_channels) {
1573 #if 0 /* Not supported for render targets */
1574 case 2:
1575 return V_008F14_IMG_DATA_FORMAT_4_4;
1576 #endif
1577 case 4:
1578 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1579 }
1580 break;
1581 case 8:
1582 switch (desc->nr_channels) {
1583 case 1:
1584 return V_008F14_IMG_DATA_FORMAT_8;
1585 case 2:
1586 return V_008F14_IMG_DATA_FORMAT_8_8;
1587 case 4:
1588 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1589 }
1590 break;
1591 case 16:
1592 switch (desc->nr_channels) {
1593 case 1:
1594 return V_008F14_IMG_DATA_FORMAT_16;
1595 case 2:
1596 return V_008F14_IMG_DATA_FORMAT_16_16;
1597 case 4:
1598 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1599 }
1600 break;
1601 case 32:
1602 switch (desc->nr_channels) {
1603 case 1:
1604 return V_008F14_IMG_DATA_FORMAT_32;
1605 case 2:
1606 return V_008F14_IMG_DATA_FORMAT_32_32;
1607 #if 0 /* Not supported for render targets */
1608 case 3:
1609 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1610 #endif
1611 case 4:
1612 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1613 }
1614 }
1615
1616 out_unknown:
1617 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1618 return ~0;
1619 }
1620
1621 static unsigned si_tex_wrap(unsigned wrap)
1622 {
1623 switch (wrap) {
1624 default:
1625 case PIPE_TEX_WRAP_REPEAT:
1626 return V_008F30_SQ_TEX_WRAP;
1627 case PIPE_TEX_WRAP_CLAMP:
1628 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1629 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1630 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1631 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1632 return V_008F30_SQ_TEX_CLAMP_BORDER;
1633 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1634 return V_008F30_SQ_TEX_MIRROR;
1635 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1636 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1637 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1638 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1639 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1640 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1641 }
1642 }
1643
1644 static unsigned si_tex_mipfilter(unsigned filter)
1645 {
1646 switch (filter) {
1647 case PIPE_TEX_MIPFILTER_NEAREST:
1648 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1649 case PIPE_TEX_MIPFILTER_LINEAR:
1650 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1651 default:
1652 case PIPE_TEX_MIPFILTER_NONE:
1653 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1654 }
1655 }
1656
1657 static unsigned si_tex_compare(unsigned compare)
1658 {
1659 switch (compare) {
1660 default:
1661 case PIPE_FUNC_NEVER:
1662 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1663 case PIPE_FUNC_LESS:
1664 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1665 case PIPE_FUNC_EQUAL:
1666 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1667 case PIPE_FUNC_LEQUAL:
1668 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1669 case PIPE_FUNC_GREATER:
1670 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1671 case PIPE_FUNC_NOTEQUAL:
1672 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1673 case PIPE_FUNC_GEQUAL:
1674 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1675 case PIPE_FUNC_ALWAYS:
1676 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1677 }
1678 }
1679
1680 static unsigned si_tex_dim(struct si_screen *sscreen, struct r600_texture *rtex,
1681 unsigned view_target, unsigned nr_samples)
1682 {
1683 unsigned res_target = rtex->resource.b.b.target;
1684
1685 if (view_target == PIPE_TEXTURE_CUBE ||
1686 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1687 res_target = view_target;
1688 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1689 else if (res_target == PIPE_TEXTURE_CUBE ||
1690 res_target == PIPE_TEXTURE_CUBE_ARRAY)
1691 res_target = PIPE_TEXTURE_2D_ARRAY;
1692
1693 /* GFX9 allocates 1D textures as 2D. */
1694 if ((res_target == PIPE_TEXTURE_1D ||
1695 res_target == PIPE_TEXTURE_1D_ARRAY) &&
1696 sscreen->b.chip_class >= GFX9 &&
1697 rtex->surface.u.gfx9.resource_type == RADEON_RESOURCE_2D) {
1698 if (res_target == PIPE_TEXTURE_1D)
1699 res_target = PIPE_TEXTURE_2D;
1700 else
1701 res_target = PIPE_TEXTURE_2D_ARRAY;
1702 }
1703
1704 switch (res_target) {
1705 default:
1706 case PIPE_TEXTURE_1D:
1707 return V_008F1C_SQ_RSRC_IMG_1D;
1708 case PIPE_TEXTURE_1D_ARRAY:
1709 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1710 case PIPE_TEXTURE_2D:
1711 case PIPE_TEXTURE_RECT:
1712 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1713 V_008F1C_SQ_RSRC_IMG_2D;
1714 case PIPE_TEXTURE_2D_ARRAY:
1715 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1716 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1717 case PIPE_TEXTURE_3D:
1718 return V_008F1C_SQ_RSRC_IMG_3D;
1719 case PIPE_TEXTURE_CUBE:
1720 case PIPE_TEXTURE_CUBE_ARRAY:
1721 return V_008F1C_SQ_RSRC_IMG_CUBE;
1722 }
1723 }
1724
1725 /*
1726 * Format support testing
1727 */
1728
1729 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1730 {
1731 return si_translate_texformat(screen, format, util_format_description(format),
1732 util_format_get_first_non_void_channel(format)) != ~0U;
1733 }
1734
1735 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1736 const struct util_format_description *desc,
1737 int first_non_void)
1738 {
1739 int i;
1740
1741 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1742 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1743
1744 assert(first_non_void >= 0);
1745
1746 if (desc->nr_channels == 4 &&
1747 desc->channel[0].size == 10 &&
1748 desc->channel[1].size == 10 &&
1749 desc->channel[2].size == 10 &&
1750 desc->channel[3].size == 2)
1751 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1752
1753 /* See whether the components are of the same size. */
1754 for (i = 0; i < desc->nr_channels; i++) {
1755 if (desc->channel[first_non_void].size != desc->channel[i].size)
1756 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1757 }
1758
1759 switch (desc->channel[first_non_void].size) {
1760 case 8:
1761 switch (desc->nr_channels) {
1762 case 1:
1763 case 3: /* 3 loads */
1764 return V_008F0C_BUF_DATA_FORMAT_8;
1765 case 2:
1766 return V_008F0C_BUF_DATA_FORMAT_8_8;
1767 case 4:
1768 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1769 }
1770 break;
1771 case 16:
1772 switch (desc->nr_channels) {
1773 case 1:
1774 case 3: /* 3 loads */
1775 return V_008F0C_BUF_DATA_FORMAT_16;
1776 case 2:
1777 return V_008F0C_BUF_DATA_FORMAT_16_16;
1778 case 4:
1779 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1780 }
1781 break;
1782 case 32:
1783 switch (desc->nr_channels) {
1784 case 1:
1785 return V_008F0C_BUF_DATA_FORMAT_32;
1786 case 2:
1787 return V_008F0C_BUF_DATA_FORMAT_32_32;
1788 case 3:
1789 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1790 case 4:
1791 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1792 }
1793 break;
1794 case 64:
1795 /* Legacy double formats. */
1796 switch (desc->nr_channels) {
1797 case 1: /* 1 load */
1798 return V_008F0C_BUF_DATA_FORMAT_32_32;
1799 case 2: /* 1 load */
1800 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1801 case 3: /* 3 loads */
1802 return V_008F0C_BUF_DATA_FORMAT_32_32;
1803 case 4: /* 2 loads */
1804 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1805 }
1806 break;
1807 }
1808
1809 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1810 }
1811
1812 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1813 const struct util_format_description *desc,
1814 int first_non_void)
1815 {
1816 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1817 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1818
1819 assert(first_non_void >= 0);
1820
1821 switch (desc->channel[first_non_void].type) {
1822 case UTIL_FORMAT_TYPE_SIGNED:
1823 case UTIL_FORMAT_TYPE_FIXED:
1824 if (desc->channel[first_non_void].size >= 32 ||
1825 desc->channel[first_non_void].pure_integer)
1826 return V_008F0C_BUF_NUM_FORMAT_SINT;
1827 else if (desc->channel[first_non_void].normalized)
1828 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1829 else
1830 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1831 break;
1832 case UTIL_FORMAT_TYPE_UNSIGNED:
1833 if (desc->channel[first_non_void].size >= 32 ||
1834 desc->channel[first_non_void].pure_integer)
1835 return V_008F0C_BUF_NUM_FORMAT_UINT;
1836 else if (desc->channel[first_non_void].normalized)
1837 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1838 else
1839 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1840 break;
1841 case UTIL_FORMAT_TYPE_FLOAT:
1842 default:
1843 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1844 }
1845 }
1846
1847 static unsigned si_is_vertex_format_supported(struct pipe_screen *screen,
1848 enum pipe_format format,
1849 unsigned usage)
1850 {
1851 const struct util_format_description *desc;
1852 int first_non_void;
1853 unsigned data_format;
1854
1855 assert((usage & ~(PIPE_BIND_SHADER_IMAGE |
1856 PIPE_BIND_SAMPLER_VIEW |
1857 PIPE_BIND_VERTEX_BUFFER)) == 0);
1858
1859 desc = util_format_description(format);
1860
1861 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
1862 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
1863 * for read-only access (with caveats surrounding bounds checks), but
1864 * obviously fails for write access which we have to implement for
1865 * shader images. Luckily, OpenGL doesn't expect this to be supported
1866 * anyway, and so the only impact is on PBO uploads / downloads, which
1867 * shouldn't be expected to be fast for GL_RGB anyway.
1868 */
1869 if (desc->block.bits == 3 * 8 ||
1870 desc->block.bits == 3 * 16) {
1871 if (usage & (PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW)) {
1872 usage &= ~(PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW);
1873 if (!usage)
1874 return 0;
1875 }
1876 }
1877
1878 first_non_void = util_format_get_first_non_void_channel(format);
1879 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1880 if (data_format == V_008F0C_BUF_DATA_FORMAT_INVALID)
1881 return 0;
1882
1883 return usage;
1884 }
1885
1886 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1887 {
1888 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1889 r600_translate_colorswap(format, false) != ~0U;
1890 }
1891
1892 static bool si_is_zs_format_supported(enum pipe_format format)
1893 {
1894 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1895 }
1896
1897 static boolean si_is_format_supported(struct pipe_screen *screen,
1898 enum pipe_format format,
1899 enum pipe_texture_target target,
1900 unsigned sample_count,
1901 unsigned usage)
1902 {
1903 unsigned retval = 0;
1904
1905 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1906 R600_ERR("r600: unsupported texture type %d\n", target);
1907 return false;
1908 }
1909
1910 if (!util_format_is_supported(format, usage))
1911 return false;
1912
1913 if (sample_count > 1) {
1914 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
1915 return false;
1916
1917 if (usage & PIPE_BIND_SHADER_IMAGE)
1918 return false;
1919
1920 switch (sample_count) {
1921 case 2:
1922 case 4:
1923 case 8:
1924 break;
1925 case 16:
1926 if (format == PIPE_FORMAT_NONE)
1927 return true;
1928 else
1929 return false;
1930 default:
1931 return false;
1932 }
1933 }
1934
1935 if (usage & (PIPE_BIND_SAMPLER_VIEW |
1936 PIPE_BIND_SHADER_IMAGE)) {
1937 if (target == PIPE_BUFFER) {
1938 retval |= si_is_vertex_format_supported(
1939 screen, format, usage & (PIPE_BIND_SAMPLER_VIEW |
1940 PIPE_BIND_SHADER_IMAGE));
1941 } else {
1942 if (si_is_sampler_format_supported(screen, format))
1943 retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
1944 PIPE_BIND_SHADER_IMAGE);
1945 }
1946 }
1947
1948 if ((usage & (PIPE_BIND_RENDER_TARGET |
1949 PIPE_BIND_DISPLAY_TARGET |
1950 PIPE_BIND_SCANOUT |
1951 PIPE_BIND_SHARED |
1952 PIPE_BIND_BLENDABLE)) &&
1953 si_is_colorbuffer_format_supported(format)) {
1954 retval |= usage &
1955 (PIPE_BIND_RENDER_TARGET |
1956 PIPE_BIND_DISPLAY_TARGET |
1957 PIPE_BIND_SCANOUT |
1958 PIPE_BIND_SHARED);
1959 if (!util_format_is_pure_integer(format) &&
1960 !util_format_is_depth_or_stencil(format))
1961 retval |= usage & PIPE_BIND_BLENDABLE;
1962 }
1963
1964 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1965 si_is_zs_format_supported(format)) {
1966 retval |= PIPE_BIND_DEPTH_STENCIL;
1967 }
1968
1969 if (usage & PIPE_BIND_VERTEX_BUFFER) {
1970 retval |= si_is_vertex_format_supported(screen, format,
1971 PIPE_BIND_VERTEX_BUFFER);
1972 }
1973
1974 if ((usage & PIPE_BIND_LINEAR) &&
1975 !util_format_is_compressed(format) &&
1976 !(usage & PIPE_BIND_DEPTH_STENCIL))
1977 retval |= PIPE_BIND_LINEAR;
1978
1979 return retval == usage;
1980 }
1981
1982 /*
1983 * framebuffer handling
1984 */
1985
1986 static void si_choose_spi_color_formats(struct r600_surface *surf,
1987 unsigned format, unsigned swap,
1988 unsigned ntype, bool is_depth)
1989 {
1990 /* Alpha is needed for alpha-to-coverage.
1991 * Blending may be with or without alpha.
1992 */
1993 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
1994 unsigned alpha = 0; /* exports alpha, but may not support blending */
1995 unsigned blend = 0; /* supports blending, but may not export alpha */
1996 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
1997
1998 /* Choose the SPI color formats. These are required values for RB+.
1999 * Other chips have multiple choices, though they are not necessarily better.
2000 */
2001 switch (format) {
2002 case V_028C70_COLOR_5_6_5:
2003 case V_028C70_COLOR_1_5_5_5:
2004 case V_028C70_COLOR_5_5_5_1:
2005 case V_028C70_COLOR_4_4_4_4:
2006 case V_028C70_COLOR_10_11_11:
2007 case V_028C70_COLOR_11_11_10:
2008 case V_028C70_COLOR_8:
2009 case V_028C70_COLOR_8_8:
2010 case V_028C70_COLOR_8_8_8_8:
2011 case V_028C70_COLOR_10_10_10_2:
2012 case V_028C70_COLOR_2_10_10_10:
2013 if (ntype == V_028C70_NUMBER_UINT)
2014 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2015 else if (ntype == V_028C70_NUMBER_SINT)
2016 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2017 else
2018 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2019 break;
2020
2021 case V_028C70_COLOR_16:
2022 case V_028C70_COLOR_16_16:
2023 case V_028C70_COLOR_16_16_16_16:
2024 if (ntype == V_028C70_NUMBER_UNORM ||
2025 ntype == V_028C70_NUMBER_SNORM) {
2026 /* UNORM16 and SNORM16 don't support blending */
2027 if (ntype == V_028C70_NUMBER_UNORM)
2028 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
2029 else
2030 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
2031
2032 /* Use 32 bits per channel for blending. */
2033 if (format == V_028C70_COLOR_16) {
2034 if (swap == V_028C70_SWAP_STD) { /* R */
2035 blend = V_028714_SPI_SHADER_32_R;
2036 blend_alpha = V_028714_SPI_SHADER_32_AR;
2037 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2038 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2039 else
2040 assert(0);
2041 } else if (format == V_028C70_COLOR_16_16) {
2042 if (swap == V_028C70_SWAP_STD) { /* RG */
2043 blend = V_028714_SPI_SHADER_32_GR;
2044 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2045 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2046 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2047 else
2048 assert(0);
2049 } else /* 16_16_16_16 */
2050 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2051 } else if (ntype == V_028C70_NUMBER_UINT)
2052 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2053 else if (ntype == V_028C70_NUMBER_SINT)
2054 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2055 else if (ntype == V_028C70_NUMBER_FLOAT)
2056 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2057 else
2058 assert(0);
2059 break;
2060
2061 case V_028C70_COLOR_32:
2062 if (swap == V_028C70_SWAP_STD) { /* R */
2063 blend = normal = V_028714_SPI_SHADER_32_R;
2064 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
2065 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2066 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2067 else
2068 assert(0);
2069 break;
2070
2071 case V_028C70_COLOR_32_32:
2072 if (swap == V_028C70_SWAP_STD) { /* RG */
2073 blend = normal = V_028714_SPI_SHADER_32_GR;
2074 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2075 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2076 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2077 else
2078 assert(0);
2079 break;
2080
2081 case V_028C70_COLOR_32_32_32_32:
2082 case V_028C70_COLOR_8_24:
2083 case V_028C70_COLOR_24_8:
2084 case V_028C70_COLOR_X24_8_32_FLOAT:
2085 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2086 break;
2087
2088 default:
2089 assert(0);
2090 return;
2091 }
2092
2093 /* The DB->CB copy needs 32_ABGR. */
2094 if (is_depth)
2095 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2096
2097 surf->spi_shader_col_format = normal;
2098 surf->spi_shader_col_format_alpha = alpha;
2099 surf->spi_shader_col_format_blend = blend;
2100 surf->spi_shader_col_format_blend_alpha = blend_alpha;
2101 }
2102
2103 static void si_initialize_color_surface(struct si_context *sctx,
2104 struct r600_surface *surf)
2105 {
2106 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2107 unsigned color_info, color_attrib, color_view;
2108 unsigned format, swap, ntype, endian;
2109 const struct util_format_description *desc;
2110 int i;
2111 unsigned blend_clamp = 0, blend_bypass = 0;
2112
2113 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2114 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
2115
2116 desc = util_format_description(surf->base.format);
2117 for (i = 0; i < 4; i++) {
2118 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2119 break;
2120 }
2121 }
2122 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
2123 ntype = V_028C70_NUMBER_FLOAT;
2124 } else {
2125 ntype = V_028C70_NUMBER_UNORM;
2126 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2127 ntype = V_028C70_NUMBER_SRGB;
2128 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2129 if (desc->channel[i].pure_integer) {
2130 ntype = V_028C70_NUMBER_SINT;
2131 } else {
2132 assert(desc->channel[i].normalized);
2133 ntype = V_028C70_NUMBER_SNORM;
2134 }
2135 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2136 if (desc->channel[i].pure_integer) {
2137 ntype = V_028C70_NUMBER_UINT;
2138 } else {
2139 assert(desc->channel[i].normalized);
2140 ntype = V_028C70_NUMBER_UNORM;
2141 }
2142 }
2143 }
2144
2145 format = si_translate_colorformat(surf->base.format);
2146 if (format == V_028C70_COLOR_INVALID) {
2147 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2148 }
2149 assert(format != V_028C70_COLOR_INVALID);
2150 swap = r600_translate_colorswap(surf->base.format, false);
2151 endian = si_colorformat_endian_swap(format);
2152
2153 /* blend clamp should be set for all NORM/SRGB types */
2154 if (ntype == V_028C70_NUMBER_UNORM ||
2155 ntype == V_028C70_NUMBER_SNORM ||
2156 ntype == V_028C70_NUMBER_SRGB)
2157 blend_clamp = 1;
2158
2159 /* set blend bypass according to docs if SINT/UINT or
2160 8/24 COLOR variants */
2161 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2162 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2163 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2164 blend_clamp = 0;
2165 blend_bypass = 1;
2166 }
2167
2168 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) {
2169 if (format == V_028C70_COLOR_8 ||
2170 format == V_028C70_COLOR_8_8 ||
2171 format == V_028C70_COLOR_8_8_8_8)
2172 surf->color_is_int8 = true;
2173 else if (format == V_028C70_COLOR_10_10_10_2 ||
2174 format == V_028C70_COLOR_2_10_10_10)
2175 surf->color_is_int10 = true;
2176 }
2177
2178 color_info = S_028C70_FORMAT(format) |
2179 S_028C70_COMP_SWAP(swap) |
2180 S_028C70_BLEND_CLAMP(blend_clamp) |
2181 S_028C70_BLEND_BYPASS(blend_bypass) |
2182 S_028C70_SIMPLE_FLOAT(1) |
2183 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2184 ntype != V_028C70_NUMBER_SNORM &&
2185 ntype != V_028C70_NUMBER_SRGB &&
2186 format != V_028C70_COLOR_8_24 &&
2187 format != V_028C70_COLOR_24_8) |
2188 S_028C70_NUMBER_TYPE(ntype) |
2189 S_028C70_ENDIAN(endian);
2190
2191 /* Intensity is implemented as Red, so treat it that way. */
2192 color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2193 util_format_is_intensity(surf->base.format));
2194
2195 if (rtex->resource.b.b.nr_samples > 1) {
2196 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
2197
2198 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2199 S_028C74_NUM_FRAGMENTS(log_samples);
2200
2201 if (rtex->fmask.size) {
2202 color_info |= S_028C70_COMPRESSION(1);
2203 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
2204
2205 if (sctx->b.chip_class == SI) {
2206 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2207 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2208 }
2209 }
2210 }
2211
2212 surf->cb_color_view = color_view;
2213 surf->cb_color_info = color_info;
2214 surf->cb_color_attrib = color_attrib;
2215
2216 if (sctx->b.chip_class >= VI) {
2217 unsigned max_uncompressed_block_size = 2;
2218
2219 if (rtex->resource.b.b.nr_samples > 1) {
2220 if (rtex->surface.bpe == 1)
2221 max_uncompressed_block_size = 0;
2222 else if (rtex->surface.bpe == 2)
2223 max_uncompressed_block_size = 1;
2224 }
2225
2226 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2227 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2228 }
2229
2230 /* This must be set for fast clear to work without FMASK. */
2231 if (!rtex->fmask.size && sctx->b.chip_class == SI) {
2232 unsigned bankh = util_logbase2(rtex->surface.u.legacy.bankh);
2233 surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2234 }
2235
2236 if (sctx->b.chip_class >= GFX9) {
2237 unsigned mip0_depth = util_max_layer(&rtex->resource.b.b, 0);
2238
2239 surf->cb_color_view |= S_028C6C_MIP_LEVEL(surf->base.u.tex.level);
2240 surf->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
2241 S_028C74_RESOURCE_TYPE(rtex->surface.u.gfx9.resource_type);
2242 surf->cb_color_attrib2 = S_028C68_MIP0_WIDTH(surf->width0 - 1) |
2243 S_028C68_MIP0_HEIGHT(surf->height0 - 1) |
2244 S_028C68_MAX_MIP(rtex->resource.b.b.last_level);
2245 }
2246
2247 /* Determine pixel shader export format */
2248 si_choose_spi_color_formats(surf, format, swap, ntype, rtex->is_depth);
2249
2250 surf->color_initialized = true;
2251 }
2252
2253 static void si_init_depth_surface(struct si_context *sctx,
2254 struct r600_surface *surf)
2255 {
2256 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2257 unsigned level = surf->base.u.tex.level;
2258 unsigned format, stencil_format;
2259 uint32_t z_info, s_info;
2260
2261 format = si_translate_dbformat(rtex->db_render_format);
2262 stencil_format = rtex->surface.flags & RADEON_SURF_SBUFFER ?
2263 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
2264
2265 assert(format != V_028040_Z_INVALID);
2266 if (format == V_028040_Z_INVALID)
2267 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
2268
2269 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2270 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2271 surf->db_htile_data_base = 0;
2272 surf->db_htile_surface = 0;
2273
2274 if (sctx->b.chip_class >= GFX9) {
2275 assert(rtex->surface.u.gfx9.surf_offset == 0);
2276 surf->db_depth_base = rtex->resource.gpu_address >> 8;
2277 surf->db_stencil_base = (rtex->resource.gpu_address +
2278 rtex->surface.u.gfx9.stencil_offset) >> 8;
2279 z_info = S_028038_FORMAT(format) |
2280 S_028038_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples)) |
2281 S_028038_SW_MODE(rtex->surface.u.gfx9.surf.swizzle_mode) |
2282 S_028038_MAXMIP(rtex->resource.b.b.last_level);
2283 s_info = S_02803C_FORMAT(stencil_format) |
2284 S_02803C_SW_MODE(rtex->surface.u.gfx9.stencil.swizzle_mode);
2285 surf->db_z_info2 = S_028068_EPITCH(rtex->surface.u.gfx9.surf.epitch);
2286 surf->db_stencil_info2 = S_02806C_EPITCH(rtex->surface.u.gfx9.stencil.epitch);
2287 surf->db_depth_view |= S_028008_MIPID(level);
2288 surf->db_depth_size = S_02801C_X_MAX(rtex->resource.b.b.width0 - 1) |
2289 S_02801C_Y_MAX(rtex->resource.b.b.height0 - 1);
2290
2291 /* Only use HTILE for the first level. */
2292 if (rtex->htile_buffer && !level) {
2293 z_info |= S_028038_TILE_SURFACE_ENABLE(1) |
2294 S_028038_ALLOW_EXPCLEAR(1);
2295
2296 if (rtex->tc_compatible_htile) {
2297 unsigned max_zplanes = 4;
2298
2299 if (rtex->db_render_format == PIPE_FORMAT_Z16_UNORM &&
2300 rtex->resource.b.b.nr_samples > 1)
2301 max_zplanes = 2;
2302
2303 z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1) |
2304 S_028038_ITERATE_FLUSH(1);
2305 s_info |= S_02803C_ITERATE_FLUSH(1);
2306 }
2307
2308 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
2309 /* Stencil buffer workaround ported from the SI-CI-VI code.
2310 * See that for explanation.
2311 */
2312 s_info |= S_02803C_ALLOW_EXPCLEAR(rtex->resource.b.b.nr_samples <= 1);
2313 } else {
2314 /* Use all HTILE for depth if there's no stencil. */
2315 s_info |= S_02803C_TILE_STENCIL_DISABLE(1);
2316 }
2317
2318 surf->db_htile_data_base = rtex->htile_buffer->gpu_address >> 8;
2319 surf->db_htile_surface = S_028ABC_FULL_CACHE(1) |
2320 S_028ABC_PIPE_ALIGNED(rtex->surface.u.gfx9.htile.pipe_aligned) |
2321 S_028ABC_RB_ALIGNED(rtex->surface.u.gfx9.htile.rb_aligned);
2322 }
2323 } else {
2324 /* SI-CI-VI */
2325 struct legacy_surf_level *levelinfo = &rtex->surface.u.legacy.level[level];
2326
2327 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2328
2329 surf->db_depth_base = (rtex->resource.gpu_address +
2330 rtex->surface.u.legacy.level[level].offset) >> 8;
2331 surf->db_stencil_base = (rtex->resource.gpu_address +
2332 rtex->surface.u.legacy.stencil_level[level].offset) >> 8;
2333
2334 z_info = S_028040_FORMAT(format) |
2335 S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
2336 s_info = S_028044_FORMAT(stencil_format);
2337 surf->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!rtex->tc_compatible_htile);
2338
2339 if (sctx->b.chip_class >= CIK) {
2340 struct radeon_info *info = &sctx->screen->b.info;
2341 unsigned index = rtex->surface.u.legacy.tiling_index[level];
2342 unsigned stencil_index = rtex->surface.u.legacy.stencil_tiling_index[level];
2343 unsigned macro_index = rtex->surface.u.legacy.macro_tile_index;
2344 unsigned tile_mode = info->si_tile_mode_array[index];
2345 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2346 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2347
2348 surf->db_depth_info |=
2349 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2350 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2351 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2352 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2353 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2354 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2355 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2356 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2357 } else {
2358 unsigned tile_mode_index = si_tile_mode_index(rtex, level, false);
2359 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2360 tile_mode_index = si_tile_mode_index(rtex, level, true);
2361 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2362 }
2363
2364 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2365 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2366 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2367 levelinfo->nblk_y) / 64 - 1);
2368
2369 /* Only use HTILE for the first level. */
2370 if (rtex->htile_buffer && !level) {
2371 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2372 S_028040_ALLOW_EXPCLEAR(1);
2373
2374 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
2375 /* Workaround: For a not yet understood reason, the
2376 * combination of MSAA, fast stencil clear and stencil
2377 * decompress messes with subsequent stencil buffer
2378 * uses. Problem was reproduced on Verde, Bonaire,
2379 * Tonga, and Carrizo.
2380 *
2381 * Disabling EXPCLEAR works around the problem.
2382 *
2383 * Check piglit's arb_texture_multisample-stencil-clear
2384 * test if you want to try changing this.
2385 */
2386 if (rtex->resource.b.b.nr_samples <= 1)
2387 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2388 } else if (!rtex->tc_compatible_htile) {
2389 /* Use all of the htile_buffer for depth if there's no stencil.
2390 * This must not be set when TC-compatible HTILE is enabled
2391 * due to a hw bug.
2392 */
2393 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2394 }
2395
2396 surf->db_htile_data_base = rtex->htile_buffer->gpu_address >> 8;
2397 surf->db_htile_surface = S_028ABC_FULL_CACHE(1);
2398
2399 if (rtex->tc_compatible_htile) {
2400 surf->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
2401
2402 if (rtex->resource.b.b.nr_samples <= 1)
2403 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2404 else if (rtex->resource.b.b.nr_samples <= 4)
2405 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2406 else
2407 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2408 }
2409 }
2410 }
2411
2412 surf->db_z_info = z_info;
2413 surf->db_stencil_info = s_info;
2414
2415 surf->depth_initialized = true;
2416 }
2417
2418 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
2419 {
2420 for (int i = 0; i < state->nr_cbufs; ++i) {
2421 struct r600_surface *surf = NULL;
2422 struct r600_texture *rtex;
2423
2424 if (!state->cbufs[i])
2425 continue;
2426 surf = (struct r600_surface*)state->cbufs[i];
2427 rtex = (struct r600_texture*)surf->base.texture;
2428
2429 p_atomic_dec(&rtex->framebuffers_bound);
2430 }
2431 }
2432
2433 static void si_set_framebuffer_state(struct pipe_context *ctx,
2434 const struct pipe_framebuffer_state *state)
2435 {
2436 struct si_context *sctx = (struct si_context *)ctx;
2437 struct pipe_constant_buffer constbuf = {0};
2438 struct r600_surface *surf = NULL;
2439 struct r600_texture *rtex;
2440 bool old_any_dst_linear = sctx->framebuffer.any_dst_linear;
2441 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2442 bool unbound = false;
2443 int i;
2444
2445 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
2446 if (!sctx->framebuffer.state.cbufs[i])
2447 continue;
2448
2449 rtex = (struct r600_texture*)sctx->framebuffer.state.cbufs[i]->texture;
2450 if (rtex->dcc_gather_statistics)
2451 vi_separate_dcc_stop_query(ctx, rtex);
2452 }
2453
2454 /* Disable DCC if the formats are incompatible. */
2455 for (i = 0; i < state->nr_cbufs; i++) {
2456 if (!state->cbufs[i])
2457 continue;
2458
2459 surf = (struct r600_surface*)state->cbufs[i];
2460 rtex = (struct r600_texture*)surf->base.texture;
2461
2462 if (!surf->dcc_incompatible)
2463 continue;
2464
2465 /* Since the DCC decompression calls back into set_framebuffer-
2466 * _state, we need to unbind the framebuffer, so that
2467 * vi_separate_dcc_stop_query isn't called twice with the same
2468 * color buffer.
2469 */
2470 if (!unbound) {
2471 util_copy_framebuffer_state(&sctx->framebuffer.state, NULL);
2472 unbound = true;
2473 }
2474
2475 if (vi_dcc_enabled(rtex, surf->base.u.tex.level))
2476 if (!r600_texture_disable_dcc(&sctx->b, rtex))
2477 sctx->b.decompress_dcc(ctx, rtex);
2478
2479 surf->dcc_incompatible = false;
2480 }
2481
2482 /* Only flush TC when changing the framebuffer state, because
2483 * the only client not using TC that can change textures is
2484 * the framebuffer.
2485 *
2486 * Flush all CB and DB caches here because all buffers can be used
2487 * for write by both TC (with shader image stores) and CB/DB.
2488 */
2489 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
2490 SI_CONTEXT_INV_GLOBAL_L2 |
2491 SI_CONTEXT_FLUSH_AND_INV_CB |
2492 SI_CONTEXT_FLUSH_AND_INV_DB |
2493 SI_CONTEXT_CS_PARTIAL_FLUSH;
2494
2495 /* Take the maximum of the old and new count. If the new count is lower,
2496 * dirtying is needed to disable the unbound colorbuffers.
2497 */
2498 sctx->framebuffer.dirty_cbufs |=
2499 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2500 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2501
2502 si_dec_framebuffer_counters(&sctx->framebuffer.state);
2503 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2504
2505 sctx->framebuffer.colorbuf_enabled_4bit = 0;
2506 sctx->framebuffer.spi_shader_col_format = 0;
2507 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2508 sctx->framebuffer.spi_shader_col_format_blend = 0;
2509 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2510 sctx->framebuffer.color_is_int8 = 0;
2511 sctx->framebuffer.color_is_int10 = 0;
2512
2513 sctx->framebuffer.compressed_cb_mask = 0;
2514 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2515 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2516 sctx->framebuffer.any_dst_linear = false;
2517
2518 for (i = 0; i < state->nr_cbufs; i++) {
2519 if (!state->cbufs[i])
2520 continue;
2521
2522 surf = (struct r600_surface*)state->cbufs[i];
2523 rtex = (struct r600_texture*)surf->base.texture;
2524
2525 if (!surf->color_initialized) {
2526 si_initialize_color_surface(sctx, surf);
2527 }
2528
2529 sctx->framebuffer.colorbuf_enabled_4bit |= 0xf << (i * 4);
2530 sctx->framebuffer.spi_shader_col_format |=
2531 surf->spi_shader_col_format << (i * 4);
2532 sctx->framebuffer.spi_shader_col_format_alpha |=
2533 surf->spi_shader_col_format_alpha << (i * 4);
2534 sctx->framebuffer.spi_shader_col_format_blend |=
2535 surf->spi_shader_col_format_blend << (i * 4);
2536 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2537 surf->spi_shader_col_format_blend_alpha << (i * 4);
2538
2539 if (surf->color_is_int8)
2540 sctx->framebuffer.color_is_int8 |= 1 << i;
2541 if (surf->color_is_int10)
2542 sctx->framebuffer.color_is_int10 |= 1 << i;
2543
2544 if (rtex->fmask.size) {
2545 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2546 }
2547
2548 if (rtex->surface.is_linear)
2549 sctx->framebuffer.any_dst_linear = true;
2550
2551 r600_context_add_resource_size(ctx, surf->base.texture);
2552
2553 p_atomic_inc(&rtex->framebuffers_bound);
2554
2555 if (rtex->dcc_gather_statistics) {
2556 /* Dirty tracking must be enabled for DCC usage analysis. */
2557 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2558 vi_separate_dcc_start_query(ctx, rtex);
2559 }
2560 }
2561
2562 if (state->zsbuf) {
2563 surf = (struct r600_surface*)state->zsbuf;
2564 rtex = (struct r600_texture*)surf->base.texture;
2565
2566 if (!surf->depth_initialized) {
2567 si_init_depth_surface(sctx, surf);
2568 }
2569 r600_context_add_resource_size(ctx, surf->base.texture);
2570 }
2571
2572 si_update_poly_offset_state(sctx);
2573 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2574 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
2575
2576 if (sctx->framebuffer.any_dst_linear != old_any_dst_linear)
2577 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2578
2579 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2580 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2581 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2582
2583 /* Set sample locations as fragment shader constants. */
2584 switch (sctx->framebuffer.nr_samples) {
2585 case 1:
2586 constbuf.user_buffer = sctx->b.sample_locations_1x;
2587 break;
2588 case 2:
2589 constbuf.user_buffer = sctx->b.sample_locations_2x;
2590 break;
2591 case 4:
2592 constbuf.user_buffer = sctx->b.sample_locations_4x;
2593 break;
2594 case 8:
2595 constbuf.user_buffer = sctx->b.sample_locations_8x;
2596 break;
2597 case 16:
2598 constbuf.user_buffer = sctx->b.sample_locations_16x;
2599 break;
2600 default:
2601 R600_ERR("Requested an invalid number of samples %i.\n",
2602 sctx->framebuffer.nr_samples);
2603 assert(0);
2604 }
2605 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2606 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
2607
2608 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
2609 }
2610
2611 sctx->need_check_render_feedback = true;
2612 sctx->do_update_shaders = true;
2613 sctx->framebuffer.do_update_surf_dirtiness = true;
2614 }
2615
2616 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
2617 {
2618 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2619 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2620 unsigned i, nr_cbufs = state->nr_cbufs;
2621 struct r600_texture *tex = NULL;
2622 struct r600_surface *cb = NULL;
2623 unsigned cb_color_info = 0;
2624
2625 /* Colorbuffers. */
2626 for (i = 0; i < nr_cbufs; i++) {
2627 uint64_t cb_color_base, cb_color_fmask, cb_dcc_base;
2628 unsigned cb_color_attrib;
2629
2630 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2631 continue;
2632
2633 cb = (struct r600_surface*)state->cbufs[i];
2634 if (!cb) {
2635 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2636 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2637 continue;
2638 }
2639
2640 tex = (struct r600_texture *)cb->base.texture;
2641 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2642 &tex->resource, RADEON_USAGE_READWRITE,
2643 tex->resource.b.b.nr_samples > 1 ?
2644 RADEON_PRIO_COLOR_BUFFER_MSAA :
2645 RADEON_PRIO_COLOR_BUFFER);
2646
2647 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2648 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2649 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2650 RADEON_PRIO_CMASK);
2651 }
2652
2653 if (tex->dcc_separate_buffer)
2654 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2655 tex->dcc_separate_buffer,
2656 RADEON_USAGE_READWRITE,
2657 RADEON_PRIO_DCC);
2658
2659 /* Compute mutable surface parameters. */
2660 cb_color_base = tex->resource.gpu_address >> 8;
2661 cb_color_fmask = cb_color_base;
2662 cb_dcc_base = 0;
2663 cb_color_info = cb->cb_color_info | tex->cb_color_info;
2664 cb_color_attrib = cb->cb_color_attrib;
2665
2666 if (tex->fmask.size)
2667 cb_color_fmask = (tex->resource.gpu_address + tex->fmask.offset) >> 8;
2668
2669 /* Set up DCC. */
2670 if (vi_dcc_enabled(tex, cb->base.u.tex.level)) {
2671 bool is_msaa_resolve_dst = state->cbufs[0] &&
2672 state->cbufs[0]->texture->nr_samples > 1 &&
2673 state->cbufs[1] == &cb->base &&
2674 state->cbufs[1]->texture->nr_samples <= 1;
2675
2676 if (!is_msaa_resolve_dst)
2677 cb_color_info |= S_028C70_DCC_ENABLE(1);
2678
2679 cb_dcc_base = ((!tex->dcc_separate_buffer ? tex->resource.gpu_address : 0) +
2680 tex->dcc_offset) >> 8;
2681 }
2682
2683 if (sctx->b.chip_class >= GFX9) {
2684 struct gfx9_surf_meta_flags meta;
2685
2686 if (tex->dcc_offset)
2687 meta = tex->surface.u.gfx9.dcc;
2688 else
2689 meta = tex->surface.u.gfx9.cmask;
2690
2691 /* Set mutable surface parameters. */
2692 cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
2693 cb_color_attrib |= S_028C74_COLOR_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
2694 S_028C74_FMASK_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
2695 S_028C74_RB_ALIGNED(meta.rb_aligned) |
2696 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
2697
2698 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 15);
2699 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
2700 radeon_emit(cs, cb_color_base >> 32); /* CB_COLOR0_BASE_EXT */
2701 radeon_emit(cs, cb->cb_color_attrib2); /* CB_COLOR0_ATTRIB2 */
2702 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
2703 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
2704 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
2705 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
2706 radeon_emit(cs, tex->cmask.base_address_reg); /* CB_COLOR0_CMASK */
2707 radeon_emit(cs, tex->cmask.base_address_reg >> 32); /* CB_COLOR0_CMASK_BASE_EXT */
2708 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
2709 radeon_emit(cs, cb_color_fmask >> 32); /* CB_COLOR0_FMASK_BASE_EXT */
2710 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
2711 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
2712 radeon_emit(cs, cb_dcc_base); /* CB_COLOR0_DCC_BASE */
2713 radeon_emit(cs, cb_dcc_base >> 32); /* CB_COLOR0_DCC_BASE_EXT */
2714
2715 radeon_set_context_reg(cs, R_0287A0_CB_MRT0_EPITCH + i * 4,
2716 S_0287A0_EPITCH(tex->surface.u.gfx9.surf.epitch));
2717 } else {
2718 /* Compute mutable surface parameters (SI-CI-VI). */
2719 const struct legacy_surf_level *level_info =
2720 &tex->surface.u.legacy.level[cb->base.u.tex.level];
2721 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
2722 unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
2723
2724 cb_color_base += level_info->offset >> 8;
2725 if (cb_dcc_base)
2726 cb_dcc_base += level_info->dcc_offset >> 8;
2727
2728 pitch_tile_max = level_info->nblk_x / 8 - 1;
2729 slice_tile_max = level_info->nblk_x *
2730 level_info->nblk_y / 64 - 1;
2731 tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false);
2732
2733 cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
2734 cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
2735 cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
2736
2737 if (tex->fmask.size) {
2738 if (sctx->b.chip_class >= CIK)
2739 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->fmask.pitch_in_pixels / 8 - 1);
2740 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->fmask.tile_mode_index);
2741 cb_color_fmask_slice = S_028C88_TILE_MAX(tex->fmask.slice_tile_max);
2742 } else {
2743 /* This must be set for fast clear to work without FMASK. */
2744 if (sctx->b.chip_class >= CIK)
2745 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
2746 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
2747 cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
2748 }
2749
2750 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
2751 sctx->b.chip_class >= VI ? 14 : 13);
2752 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
2753 radeon_emit(cs, cb_color_pitch); /* CB_COLOR0_PITCH */
2754 radeon_emit(cs, cb_color_slice); /* CB_COLOR0_SLICE */
2755 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
2756 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
2757 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
2758 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
2759 radeon_emit(cs, tex->cmask.base_address_reg); /* CB_COLOR0_CMASK */
2760 radeon_emit(cs, tex->cmask.slice_tile_max); /* CB_COLOR0_CMASK_SLICE */
2761 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
2762 radeon_emit(cs, cb_color_fmask_slice); /* CB_COLOR0_FMASK_SLICE */
2763 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
2764 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
2765
2766 if (sctx->b.chip_class >= VI) /* R_028C94_CB_COLOR0_DCC_BASE */
2767 radeon_emit(cs, cb_dcc_base);
2768 }
2769 }
2770 for (; i < 8 ; i++)
2771 if (sctx->framebuffer.dirty_cbufs & (1 << i))
2772 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
2773
2774 /* ZS buffer. */
2775 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
2776 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
2777 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
2778
2779 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2780 &rtex->resource, RADEON_USAGE_READWRITE,
2781 zb->base.texture->nr_samples > 1 ?
2782 RADEON_PRIO_DEPTH_BUFFER_MSAA :
2783 RADEON_PRIO_DEPTH_BUFFER);
2784
2785 if (zb->db_htile_data_base) {
2786 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2787 rtex->htile_buffer, RADEON_USAGE_READWRITE,
2788 RADEON_PRIO_HTILE);
2789 }
2790
2791 if (sctx->b.chip_class >= GFX9) {
2792 radeon_set_context_reg_seq(cs, R_028014_DB_HTILE_DATA_BASE, 3);
2793 radeon_emit(cs, zb->db_htile_data_base); /* DB_HTILE_DATA_BASE */
2794 radeon_emit(cs, zb->db_htile_data_base >> 32); /* DB_HTILE_DATA_BASE_HI */
2795 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
2796
2797 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 10);
2798 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
2799 S_028038_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
2800 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
2801 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
2802 radeon_emit(cs, zb->db_depth_base >> 32); /* DB_Z_READ_BASE_HI */
2803 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
2804 radeon_emit(cs, zb->db_stencil_base >> 32); /* DB_STENCIL_READ_BASE_HI */
2805 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
2806 radeon_emit(cs, zb->db_depth_base >> 32); /* DB_Z_WRITE_BASE_HI */
2807 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
2808 radeon_emit(cs, zb->db_stencil_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
2809
2810 radeon_set_context_reg_seq(cs, R_028068_DB_Z_INFO2, 2);
2811 radeon_emit(cs, zb->db_z_info2); /* DB_Z_INFO2 */
2812 radeon_emit(cs, zb->db_stencil_info2); /* DB_STENCIL_INFO2 */
2813 } else {
2814 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
2815
2816 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
2817 radeon_emit(cs, zb->db_depth_info); /* DB_DEPTH_INFO */
2818 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
2819 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
2820 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
2821 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
2822 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
2823 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
2824 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
2825 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
2826 radeon_emit(cs, zb->db_depth_slice); /* DB_DEPTH_SLICE */
2827 }
2828
2829 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
2830 radeon_emit(cs, rtex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
2831 radeon_emit(cs, fui(rtex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
2832
2833 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
2834 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
2835 } else if (sctx->framebuffer.dirty_zsbuf) {
2836 if (sctx->b.chip_class >= GFX9)
2837 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 2);
2838 else
2839 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
2840
2841 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
2842 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
2843 }
2844
2845 /* Framebuffer dimensions. */
2846 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2847 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2848 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
2849
2850 if (sctx->b.chip_class >= GFX9) {
2851 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2852 radeon_emit(cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
2853 }
2854
2855 sctx->framebuffer.dirty_cbufs = 0;
2856 sctx->framebuffer.dirty_zsbuf = false;
2857 }
2858
2859 static void si_emit_msaa_sample_locs(struct si_context *sctx,
2860 struct r600_atom *atom)
2861 {
2862 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2863 unsigned nr_samples = sctx->framebuffer.nr_samples;
2864 bool has_msaa_sample_loc_bug = sctx->screen->has_msaa_sample_loc_bug;
2865
2866 /* Smoothing (only possible with nr_samples == 1) uses the same
2867 * sample locations as the MSAA it simulates.
2868 */
2869 if (nr_samples <= 1 && sctx->smoothing_enabled)
2870 nr_samples = SI_NUM_SMOOTH_AA_SAMPLES;
2871
2872 /* On Polaris, the small primitive filter uses the sample locations
2873 * even when MSAA is off, so we need to make sure they're set to 0.
2874 */
2875 if (has_msaa_sample_loc_bug)
2876 nr_samples = MAX2(nr_samples, 1);
2877
2878 if (nr_samples >= 1 &&
2879 (nr_samples != sctx->msaa_sample_locs.nr_samples)) {
2880 sctx->msaa_sample_locs.nr_samples = nr_samples;
2881 cayman_emit_msaa_sample_locs(cs, nr_samples);
2882 }
2883
2884 if (sctx->b.family >= CHIP_POLARIS10) {
2885 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
2886 unsigned small_prim_filter_cntl =
2887 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
2888 /* line bug */
2889 S_028830_LINE_FILTER_DISABLE(sctx->b.family <= CHIP_POLARIS12);
2890
2891 /* The alternative of setting sample locations to 0 would
2892 * require a DB flush to avoid Z errors, see
2893 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
2894 */
2895 if (has_msaa_sample_loc_bug &&
2896 sctx->framebuffer.nr_samples > 1 &&
2897 rs && !rs->multisample_enable)
2898 small_prim_filter_cntl &= C_028830_SMALL_PRIM_FILTER_ENABLE;
2899
2900 radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
2901 small_prim_filter_cntl);
2902 }
2903 }
2904
2905 static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom)
2906 {
2907 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2908 unsigned num_tile_pipes = sctx->screen->b.info.num_tile_pipes;
2909 /* 33% faster rendering to linear color buffers */
2910 bool dst_is_linear = sctx->framebuffer.any_dst_linear;
2911 unsigned sc_mode_cntl_1 =
2912 S_028A4C_WALK_SIZE(dst_is_linear) |
2913 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear) |
2914 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
2915 /* always 1: */
2916 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
2917 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
2918 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
2919 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
2920 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
2921 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
2922
2923 cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples,
2924 sctx->ps_iter_samples,
2925 sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0,
2926 sc_mode_cntl_1);
2927
2928 /* GFX9: Flush DFSM when the AA mode changes. */
2929 if (sctx->b.chip_class >= GFX9) {
2930 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2931 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
2932 }
2933 }
2934
2935 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
2936 {
2937 struct si_context *sctx = (struct si_context *)ctx;
2938
2939 if (sctx->ps_iter_samples == min_samples)
2940 return;
2941
2942 sctx->ps_iter_samples = min_samples;
2943 sctx->do_update_shaders = true;
2944
2945 if (sctx->framebuffer.nr_samples > 1)
2946 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2947 }
2948
2949 /*
2950 * Samplers
2951 */
2952
2953 /**
2954 * Build the sampler view descriptor for a buffer texture.
2955 * @param state 256-bit descriptor; only the high 128 bits are filled in
2956 */
2957 void
2958 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
2959 enum pipe_format format,
2960 unsigned offset, unsigned size,
2961 uint32_t *state)
2962 {
2963 const struct util_format_description *desc;
2964 int first_non_void;
2965 unsigned stride;
2966 unsigned num_records;
2967 unsigned num_format, data_format;
2968
2969 desc = util_format_description(format);
2970 first_non_void = util_format_get_first_non_void_channel(format);
2971 stride = desc->block.bits / 8;
2972 num_format = si_translate_buffer_numformat(&screen->b.b, desc, first_non_void);
2973 data_format = si_translate_buffer_dataformat(&screen->b.b, desc, first_non_void);
2974
2975 num_records = size / stride;
2976 num_records = MIN2(num_records, (buf->b.b.width0 - offset) / stride);
2977
2978 /* The NUM_RECORDS field has a different meaning depending on the chip,
2979 * instruction type, STRIDE, and SWIZZLE_ENABLE.
2980 *
2981 * SI-CIK:
2982 * - If STRIDE == 0, it's in byte units.
2983 * - If STRIDE != 0, it's in units of STRIDE, used with inst.IDXEN.
2984 *
2985 * VI:
2986 * - For SMEM and STRIDE == 0, it's in byte units.
2987 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
2988 * - For VMEM and STRIDE == 0 or SWIZZLE_ENABLE == 0, it's in byte units.
2989 * - For VMEM and STRIDE != 0 and SWIZZLE_ENABLE == 1, it's in units of STRIDE.
2990 * NOTE: There is incompatibility between VMEM and SMEM opcodes due to SWIZZLE_-
2991 * ENABLE. The workaround is to set STRIDE = 0 if SWIZZLE_ENABLE == 0 when
2992 * using SMEM. This can be done in the shader by clearing STRIDE with s_and.
2993 * That way the same descriptor can be used by both SMEM and VMEM.
2994 *
2995 * GFX9:
2996 * - For SMEM and STRIDE == 0, it's in byte units.
2997 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
2998 * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
2999 * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
3000 */
3001 if (screen->b.chip_class >= GFX9)
3002 /* When vindex == 0, LLVM sets IDXEN = 0, thus changing units
3003 * from STRIDE to bytes. This works around it by setting
3004 * NUM_RECORDS to at least the size of one element, so that
3005 * the first element is readable when IDXEN == 0.
3006 *
3007 * TODO: Fix this in LLVM, but do we need a new intrinsic where
3008 * IDXEN is enforced?
3009 */
3010 num_records = num_records ? MAX2(num_records, stride) : 0;
3011 else if (screen->b.chip_class == VI)
3012 num_records *= stride;
3013
3014 state[4] = 0;
3015 state[5] = S_008F04_STRIDE(stride);
3016 state[6] = num_records;
3017 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3018 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3019 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3020 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
3021 S_008F0C_NUM_FORMAT(num_format) |
3022 S_008F0C_DATA_FORMAT(data_format);
3023 }
3024
3025 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle[4])
3026 {
3027 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3028
3029 if (swizzle[3] == PIPE_SWIZZLE_X) {
3030 /* For the pre-defined border color values (white, opaque
3031 * black, transparent black), the only thing that matters is
3032 * that the alpha channel winds up in the correct place
3033 * (because the RGB channels are all the same) so either of
3034 * these enumerations will work.
3035 */
3036 if (swizzle[2] == PIPE_SWIZZLE_Y)
3037 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
3038 else
3039 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
3040 } else if (swizzle[0] == PIPE_SWIZZLE_X) {
3041 if (swizzle[1] == PIPE_SWIZZLE_Y)
3042 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3043 else
3044 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
3045 } else if (swizzle[1] == PIPE_SWIZZLE_X) {
3046 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
3047 } else if (swizzle[2] == PIPE_SWIZZLE_X) {
3048 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
3049 }
3050
3051 return bc_swizzle;
3052 }
3053
3054 /**
3055 * Build the sampler view descriptor for a texture.
3056 */
3057 void
3058 si_make_texture_descriptor(struct si_screen *screen,
3059 struct r600_texture *tex,
3060 bool sampler,
3061 enum pipe_texture_target target,
3062 enum pipe_format pipe_format,
3063 const unsigned char state_swizzle[4],
3064 unsigned first_level, unsigned last_level,
3065 unsigned first_layer, unsigned last_layer,
3066 unsigned width, unsigned height, unsigned depth,
3067 uint32_t *state,
3068 uint32_t *fmask_state)
3069 {
3070 struct pipe_resource *res = &tex->resource.b.b;
3071 const struct util_format_description *base_desc, *desc;
3072 unsigned char swizzle[4];
3073 int first_non_void;
3074 unsigned num_format, data_format, type;
3075 uint64_t va;
3076
3077 desc = util_format_description(pipe_format);
3078 base_desc = util_format_description(res->format);
3079
3080 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
3081 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
3082 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
3083 const unsigned char swizzle_wwww[4] = {3, 3, 3, 3};
3084
3085 switch (pipe_format) {
3086 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3087 case PIPE_FORMAT_X32_S8X24_UINT:
3088 case PIPE_FORMAT_X8Z24_UNORM:
3089 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3090 break;
3091 case PIPE_FORMAT_X24S8_UINT:
3092 /*
3093 * X24S8 is implemented as an 8_8_8_8 data format, to
3094 * fix texture gathers. This affects at least
3095 * GL45-CTS.texture_cube_map_array.sampling on VI.
3096 */
3097 util_format_compose_swizzles(swizzle_wwww, state_swizzle, swizzle);
3098 break;
3099 default:
3100 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
3101 }
3102 } else {
3103 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
3104 }
3105
3106 first_non_void = util_format_get_first_non_void_channel(pipe_format);
3107
3108 switch (pipe_format) {
3109 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3110 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3111 break;
3112 default:
3113 if (first_non_void < 0) {
3114 if (util_format_is_compressed(pipe_format)) {
3115 switch (pipe_format) {
3116 case PIPE_FORMAT_DXT1_SRGB:
3117 case PIPE_FORMAT_DXT1_SRGBA:
3118 case PIPE_FORMAT_DXT3_SRGBA:
3119 case PIPE_FORMAT_DXT5_SRGBA:
3120 case PIPE_FORMAT_BPTC_SRGBA:
3121 case PIPE_FORMAT_ETC2_SRGB8:
3122 case PIPE_FORMAT_ETC2_SRGB8A1:
3123 case PIPE_FORMAT_ETC2_SRGBA8:
3124 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3125 break;
3126 case PIPE_FORMAT_RGTC1_SNORM:
3127 case PIPE_FORMAT_LATC1_SNORM:
3128 case PIPE_FORMAT_RGTC2_SNORM:
3129 case PIPE_FORMAT_LATC2_SNORM:
3130 case PIPE_FORMAT_ETC2_R11_SNORM:
3131 case PIPE_FORMAT_ETC2_RG11_SNORM:
3132 /* implies float, so use SNORM/UNORM to determine
3133 whether data is signed or not */
3134 case PIPE_FORMAT_BPTC_RGB_FLOAT:
3135 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3136 break;
3137 default:
3138 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3139 break;
3140 }
3141 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
3142 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3143 } else {
3144 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3145 }
3146 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
3147 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3148 } else {
3149 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3150
3151 switch (desc->channel[first_non_void].type) {
3152 case UTIL_FORMAT_TYPE_FLOAT:
3153 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3154 break;
3155 case UTIL_FORMAT_TYPE_SIGNED:
3156 if (desc->channel[first_non_void].normalized)
3157 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3158 else if (desc->channel[first_non_void].pure_integer)
3159 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
3160 else
3161 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
3162 break;
3163 case UTIL_FORMAT_TYPE_UNSIGNED:
3164 if (desc->channel[first_non_void].normalized)
3165 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3166 else if (desc->channel[first_non_void].pure_integer)
3167 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3168 else
3169 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
3170 }
3171 }
3172 }
3173
3174 data_format = si_translate_texformat(&screen->b.b, pipe_format, desc, first_non_void);
3175 if (data_format == ~0) {
3176 data_format = 0;
3177 }
3178
3179 /* Enable clamping for UNORM depth formats promoted to Z32F. */
3180 if (screen->b.chip_class >= GFX9 &&
3181 util_format_has_depth(desc) &&
3182 num_format == V_008F14_IMG_NUM_FORMAT_FLOAT &&
3183 util_get_depth_format_type(base_desc) != UTIL_FORMAT_TYPE_FLOAT) {
3184 /* NUM_FORMAT=FLOAT and DATA_FORMAT=24_8 means "clamp to [0,1]". */
3185 data_format = V_008F14_IMG_DATA_FORMAT_24_8;
3186 }
3187
3188 if (!sampler &&
3189 (res->target == PIPE_TEXTURE_CUBE ||
3190 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
3191 (screen->b.chip_class <= VI &&
3192 res->target == PIPE_TEXTURE_3D))) {
3193 /* For the purpose of shader images, treat cube maps and 3D
3194 * textures as 2D arrays. For 3D textures, the address
3195 * calculations for mipmaps are different, so we rely on the
3196 * caller to effectively disable mipmaps.
3197 */
3198 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
3199
3200 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
3201 } else {
3202 type = si_tex_dim(screen, tex, target, res->nr_samples);
3203 }
3204
3205 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
3206 height = 1;
3207 depth = res->array_size;
3208 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
3209 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
3210 if (sampler || res->target != PIPE_TEXTURE_3D)
3211 depth = res->array_size;
3212 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
3213 depth = res->array_size / 6;
3214
3215 state[0] = 0;
3216 state[1] = (S_008F14_DATA_FORMAT_GFX6(data_format) |
3217 S_008F14_NUM_FORMAT_GFX6(num_format));
3218 state[2] = (S_008F18_WIDTH(width - 1) |
3219 S_008F18_HEIGHT(height - 1) |
3220 S_008F18_PERF_MOD(4));
3221 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
3222 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
3223 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
3224 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
3225 S_008F1C_BASE_LEVEL(res->nr_samples > 1 ?
3226 0 : first_level) |
3227 S_008F1C_LAST_LEVEL(res->nr_samples > 1 ?
3228 util_logbase2(res->nr_samples) :
3229 last_level) |
3230 S_008F1C_TYPE(type));
3231 state[4] = 0;
3232 state[5] = S_008F24_BASE_ARRAY(first_layer);
3233 state[6] = 0;
3234 state[7] = 0;
3235
3236 if (screen->b.chip_class >= GFX9) {
3237 unsigned bc_swizzle = gfx9_border_color_swizzle(desc->swizzle);
3238
3239 /* Depth is the the last accessible layer on Gfx9.
3240 * The hw doesn't need to know the total number of layers.
3241 */
3242 if (type == V_008F1C_SQ_RSRC_IMG_3D)
3243 state[4] |= S_008F20_DEPTH(depth - 1);
3244 else
3245 state[4] |= S_008F20_DEPTH(last_layer);
3246
3247 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
3248 state[5] |= S_008F24_MAX_MIP(res->nr_samples > 1 ?
3249 util_logbase2(res->nr_samples) :
3250 tex->resource.b.b.last_level);
3251 } else {
3252 state[3] |= S_008F1C_POW2_PAD(res->last_level > 0);
3253 state[4] |= S_008F20_DEPTH(depth - 1);
3254 state[5] |= S_008F24_LAST_ARRAY(last_layer);
3255 }
3256
3257 if (tex->dcc_offset) {
3258 unsigned swap = r600_translate_colorswap(pipe_format, false);
3259
3260 state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
3261 } else {
3262 /* The last dword is unused by hw. The shader uses it to clear
3263 * bits in the first dword of sampler state.
3264 */
3265 if (screen->b.chip_class <= CIK && res->nr_samples <= 1) {
3266 if (first_level == last_level)
3267 state[7] = C_008F30_MAX_ANISO_RATIO;
3268 else
3269 state[7] = 0xffffffff;
3270 }
3271 }
3272
3273 /* Initialize the sampler view for FMASK. */
3274 if (tex->fmask.size) {
3275 uint32_t data_format, num_format;
3276
3277 va = tex->resource.gpu_address + tex->fmask.offset;
3278
3279 if (screen->b.chip_class >= GFX9) {
3280 data_format = V_008F14_IMG_DATA_FORMAT_FMASK;
3281 switch (res->nr_samples) {
3282 case 2:
3283 num_format = V_008F14_IMG_FMASK_8_2_2;
3284 break;
3285 case 4:
3286 num_format = V_008F14_IMG_FMASK_8_4_4;
3287 break;
3288 case 8:
3289 num_format = V_008F14_IMG_FMASK_32_8_8;
3290 break;
3291 default:
3292 unreachable("invalid nr_samples");
3293 }
3294 } else {
3295 switch (res->nr_samples) {
3296 case 2:
3297 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
3298 break;
3299 case 4:
3300 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
3301 break;
3302 case 8:
3303 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
3304 break;
3305 default:
3306 unreachable("invalid nr_samples");
3307 }
3308 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3309 }
3310
3311 fmask_state[0] = va >> 8;
3312 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
3313 S_008F14_DATA_FORMAT_GFX6(data_format) |
3314 S_008F14_NUM_FORMAT_GFX6(num_format);
3315 fmask_state[2] = S_008F18_WIDTH(width - 1) |
3316 S_008F18_HEIGHT(height - 1);
3317 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
3318 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
3319 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
3320 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
3321 S_008F1C_TYPE(si_tex_dim(screen, tex, target, 0));
3322 fmask_state[4] = 0;
3323 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
3324 fmask_state[6] = 0;
3325 fmask_state[7] = 0;
3326
3327 if (screen->b.chip_class >= GFX9) {
3328 fmask_state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode);
3329 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
3330 S_008F20_PITCH_GFX9(tex->surface.u.gfx9.fmask.epitch);
3331 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned) |
3332 S_008F24_META_RB_ALIGNED(tex->surface.u.gfx9.cmask.rb_aligned);
3333 } else {
3334 fmask_state[3] |= S_008F1C_TILING_INDEX(tex->fmask.tile_mode_index);
3335 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
3336 S_008F20_PITCH_GFX6(tex->fmask.pitch_in_pixels - 1);
3337 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
3338 }
3339 }
3340 }
3341
3342 /**
3343 * Create a sampler view.
3344 *
3345 * @param ctx context
3346 * @param texture texture
3347 * @param state sampler view template
3348 * @param width0 width0 override (for compressed textures as int)
3349 * @param height0 height0 override (for compressed textures as int)
3350 * @param force_level set the base address to the level (for compressed textures)
3351 */
3352 struct pipe_sampler_view *
3353 si_create_sampler_view_custom(struct pipe_context *ctx,
3354 struct pipe_resource *texture,
3355 const struct pipe_sampler_view *state,
3356 unsigned width0, unsigned height0,
3357 unsigned force_level)
3358 {
3359 struct si_context *sctx = (struct si_context*)ctx;
3360 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
3361 struct r600_texture *tmp = (struct r600_texture*)texture;
3362 unsigned base_level, first_level, last_level;
3363 unsigned char state_swizzle[4];
3364 unsigned height, depth, width;
3365 unsigned last_layer = state->u.tex.last_layer;
3366 enum pipe_format pipe_format;
3367 const struct legacy_surf_level *surflevel;
3368
3369 if (!view)
3370 return NULL;
3371
3372 /* initialize base object */
3373 view->base = *state;
3374 view->base.texture = NULL;
3375 view->base.reference.count = 1;
3376 view->base.context = ctx;
3377
3378 assert(texture);
3379 pipe_resource_reference(&view->base.texture, texture);
3380
3381 if (state->format == PIPE_FORMAT_X24S8_UINT ||
3382 state->format == PIPE_FORMAT_S8X24_UINT ||
3383 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
3384 state->format == PIPE_FORMAT_S8_UINT)
3385 view->is_stencil_sampler = true;
3386
3387 /* Buffer resource. */
3388 if (texture->target == PIPE_BUFFER) {
3389 si_make_buffer_descriptor(sctx->screen,
3390 (struct r600_resource *)texture,
3391 state->format,
3392 state->u.buf.offset,
3393 state->u.buf.size,
3394 view->state);
3395 return &view->base;
3396 }
3397
3398 state_swizzle[0] = state->swizzle_r;
3399 state_swizzle[1] = state->swizzle_g;
3400 state_swizzle[2] = state->swizzle_b;
3401 state_swizzle[3] = state->swizzle_a;
3402
3403 base_level = 0;
3404 first_level = state->u.tex.first_level;
3405 last_level = state->u.tex.last_level;
3406 width = width0;
3407 height = height0;
3408 depth = texture->depth0;
3409
3410 if (sctx->b.chip_class <= VI && force_level) {
3411 assert(force_level == first_level &&
3412 force_level == last_level);
3413 base_level = force_level;
3414 first_level = 0;
3415 last_level = 0;
3416 width = u_minify(width, force_level);
3417 height = u_minify(height, force_level);
3418 depth = u_minify(depth, force_level);
3419 }
3420
3421 /* This is not needed if state trackers set last_layer correctly. */
3422 if (state->target == PIPE_TEXTURE_1D ||
3423 state->target == PIPE_TEXTURE_2D ||
3424 state->target == PIPE_TEXTURE_RECT ||
3425 state->target == PIPE_TEXTURE_CUBE)
3426 last_layer = state->u.tex.first_layer;
3427
3428 /* Texturing with separate depth and stencil. */
3429 pipe_format = state->format;
3430
3431 /* Depth/stencil texturing sometimes needs separate texture. */
3432 if (tmp->is_depth && !r600_can_sample_zs(tmp, view->is_stencil_sampler)) {
3433 if (!tmp->flushed_depth_texture &&
3434 !r600_init_flushed_depth_texture(ctx, texture, NULL)) {
3435 pipe_resource_reference(&view->base.texture, NULL);
3436 FREE(view);
3437 return NULL;
3438 }
3439
3440 assert(tmp->flushed_depth_texture);
3441
3442 /* Override format for the case where the flushed texture
3443 * contains only Z or only S.
3444 */
3445 if (tmp->flushed_depth_texture->resource.b.b.format != tmp->resource.b.b.format)
3446 pipe_format = tmp->flushed_depth_texture->resource.b.b.format;
3447
3448 tmp = tmp->flushed_depth_texture;
3449 }
3450
3451 surflevel = tmp->surface.u.legacy.level;
3452
3453 if (tmp->db_compatible) {
3454 if (!view->is_stencil_sampler)
3455 pipe_format = tmp->db_render_format;
3456
3457 switch (pipe_format) {
3458 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
3459 pipe_format = PIPE_FORMAT_Z32_FLOAT;
3460 break;
3461 case PIPE_FORMAT_X8Z24_UNORM:
3462 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3463 /* Z24 is always stored like this for DB
3464 * compatibility.
3465 */
3466 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
3467 break;
3468 case PIPE_FORMAT_X24S8_UINT:
3469 case PIPE_FORMAT_S8X24_UINT:
3470 case PIPE_FORMAT_X32_S8X24_UINT:
3471 pipe_format = PIPE_FORMAT_S8_UINT;
3472 surflevel = tmp->surface.u.legacy.stencil_level;
3473 break;
3474 default:;
3475 }
3476 }
3477
3478 view->dcc_incompatible =
3479 vi_dcc_formats_are_incompatible(texture,
3480 state->u.tex.first_level,
3481 state->format);
3482
3483 si_make_texture_descriptor(sctx->screen, tmp, true,
3484 state->target, pipe_format, state_swizzle,
3485 first_level, last_level,
3486 state->u.tex.first_layer, last_layer,
3487 width, height, depth,
3488 view->state, view->fmask_state);
3489
3490 view->base_level_info = &surflevel[base_level];
3491 view->base_level = base_level;
3492 view->block_width = util_format_get_blockwidth(pipe_format);
3493 return &view->base;
3494 }
3495
3496 static struct pipe_sampler_view *
3497 si_create_sampler_view(struct pipe_context *ctx,
3498 struct pipe_resource *texture,
3499 const struct pipe_sampler_view *state)
3500 {
3501 return si_create_sampler_view_custom(ctx, texture, state,
3502 texture ? texture->width0 : 0,
3503 texture ? texture->height0 : 0, 0);
3504 }
3505
3506 static void si_sampler_view_destroy(struct pipe_context *ctx,
3507 struct pipe_sampler_view *state)
3508 {
3509 struct si_sampler_view *view = (struct si_sampler_view *)state;
3510
3511 pipe_resource_reference(&state->texture, NULL);
3512 FREE(view);
3513 }
3514
3515 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
3516 {
3517 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
3518 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
3519 (linear_filter &&
3520 (wrap == PIPE_TEX_WRAP_CLAMP ||
3521 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
3522 }
3523
3524 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
3525 {
3526 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
3527 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
3528
3529 return (state->border_color.ui[0] || state->border_color.ui[1] ||
3530 state->border_color.ui[2] || state->border_color.ui[3]) &&
3531 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
3532 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
3533 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
3534 }
3535
3536 static void *si_create_sampler_state(struct pipe_context *ctx,
3537 const struct pipe_sampler_state *state)
3538 {
3539 struct si_context *sctx = (struct si_context *)ctx;
3540 struct r600_common_screen *rscreen = sctx->b.screen;
3541 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
3542 unsigned border_color_type, border_color_index = 0;
3543 unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
3544 : state->max_anisotropy;
3545 unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso);
3546
3547 if (!rstate) {
3548 return NULL;
3549 }
3550
3551 if (!sampler_state_needs_border_color(state))
3552 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3553 else if (state->border_color.f[0] == 0 &&
3554 state->border_color.f[1] == 0 &&
3555 state->border_color.f[2] == 0 &&
3556 state->border_color.f[3] == 0)
3557 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3558 else if (state->border_color.f[0] == 0 &&
3559 state->border_color.f[1] == 0 &&
3560 state->border_color.f[2] == 0 &&
3561 state->border_color.f[3] == 1)
3562 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3563 else if (state->border_color.f[0] == 1 &&
3564 state->border_color.f[1] == 1 &&
3565 state->border_color.f[2] == 1 &&
3566 state->border_color.f[3] == 1)
3567 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3568 else {
3569 int i;
3570
3571 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
3572
3573 /* Check if the border has been uploaded already. */
3574 for (i = 0; i < sctx->border_color_count; i++)
3575 if (memcmp(&sctx->border_color_table[i], &state->border_color,
3576 sizeof(state->border_color)) == 0)
3577 break;
3578
3579 if (i >= SI_MAX_BORDER_COLORS) {
3580 /* Getting 4096 unique border colors is very unlikely. */
3581 fprintf(stderr, "radeonsi: The border color table is full. "
3582 "Any new border colors will be just black. "
3583 "Please file a bug.\n");
3584 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3585 } else {
3586 if (i == sctx->border_color_count) {
3587 /* Upload a new border color. */
3588 memcpy(&sctx->border_color_table[i], &state->border_color,
3589 sizeof(state->border_color));
3590 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
3591 &state->border_color,
3592 sizeof(state->border_color));
3593 sctx->border_color_count++;
3594 }
3595
3596 border_color_index = i;
3597 }
3598 }
3599
3600 #ifdef DEBUG
3601 rstate->magic = SI_SAMPLER_STATE_MAGIC;
3602 #endif
3603 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
3604 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
3605 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
3606 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3607 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
3608 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
3609 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
3610 S_008F30_ANISO_BIAS(max_aniso_ratio) |
3611 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
3612 S_008F30_COMPAT_MODE(sctx->b.chip_class >= VI));
3613 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
3614 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)) |
3615 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
3616 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
3617 S_008F38_XY_MAG_FILTER(eg_tex_filter(state->mag_img_filter, max_aniso)) |
3618 S_008F38_XY_MIN_FILTER(eg_tex_filter(state->min_img_filter, max_aniso)) |
3619 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
3620 S_008F38_MIP_POINT_PRECLAMP(1) |
3621 S_008F38_DISABLE_LSB_CEIL(sctx->b.chip_class <= VI) |
3622 S_008F38_FILTER_PREC_FIX(1) |
3623 S_008F38_ANISO_OVERRIDE(sctx->b.chip_class >= VI));
3624 rstate->val[3] = S_008F3C_BORDER_COLOR_PTR(border_color_index) |
3625 S_008F3C_BORDER_COLOR_TYPE(border_color_type);
3626 return rstate;
3627 }
3628
3629 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
3630 {
3631 struct si_context *sctx = (struct si_context *)ctx;
3632
3633 if (sctx->sample_mask.sample_mask == (uint16_t)sample_mask)
3634 return;
3635
3636 sctx->sample_mask.sample_mask = sample_mask;
3637 si_mark_atom_dirty(sctx, &sctx->sample_mask.atom);
3638 }
3639
3640 static void si_emit_sample_mask(struct si_context *sctx, struct r600_atom *atom)
3641 {
3642 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
3643 unsigned mask = sctx->sample_mask.sample_mask;
3644
3645 /* Needed for line and polygon smoothing as well as for the Polaris
3646 * small primitive filter. We expect the state tracker to take care of
3647 * this for us.
3648 */
3649 assert(mask == 0xffff || sctx->framebuffer.nr_samples > 1 ||
3650 (mask & 1 && sctx->blitter->running));
3651
3652 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3653 radeon_emit(cs, mask | (mask << 16));
3654 radeon_emit(cs, mask | (mask << 16));
3655 }
3656
3657 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
3658 {
3659 #ifdef DEBUG
3660 struct si_sampler_state *s = state;
3661
3662 assert(s->magic == SI_SAMPLER_STATE_MAGIC);
3663 s->magic = 0;
3664 #endif
3665 free(state);
3666 }
3667
3668 /*
3669 * Vertex elements & buffers
3670 */
3671
3672 static void *si_create_vertex_elements(struct pipe_context *ctx,
3673 unsigned count,
3674 const struct pipe_vertex_element *elements)
3675 {
3676 struct si_screen *sscreen = (struct si_screen*)ctx->screen;
3677 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
3678 bool used[SI_NUM_VERTEX_BUFFERS] = {};
3679 int i;
3680
3681 assert(count <= SI_MAX_ATTRIBS);
3682 if (!v)
3683 return NULL;
3684
3685 v->count = count;
3686 v->desc_list_byte_size = align(count * 16, SI_CPDMA_ALIGNMENT);
3687
3688 for (i = 0; i < count; ++i) {
3689 const struct util_format_description *desc;
3690 const struct util_format_channel_description *channel;
3691 unsigned data_format, num_format;
3692 int first_non_void;
3693 unsigned vbo_index = elements[i].vertex_buffer_index;
3694 unsigned char swizzle[4];
3695
3696 if (vbo_index >= SI_NUM_VERTEX_BUFFERS) {
3697 FREE(v);
3698 return NULL;
3699 }
3700
3701 if (!used[vbo_index]) {
3702 v->first_vb_use_mask |= 1 << i;
3703 used[vbo_index] = true;
3704 }
3705
3706 desc = util_format_description(elements[i].src_format);
3707 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
3708 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
3709 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
3710 channel = first_non_void >= 0 ? &desc->channel[first_non_void] : NULL;
3711 memcpy(swizzle, desc->swizzle, sizeof(swizzle));
3712
3713 v->format_size[i] = desc->block.bits / 8;
3714
3715 /* The hardware always treats the 2-bit alpha channel as
3716 * unsigned, so a shader workaround is needed. The affected
3717 * chips are VI and older except Stoney (GFX8.1).
3718 */
3719 if (data_format == V_008F0C_BUF_DATA_FORMAT_2_10_10_10 &&
3720 sscreen->b.chip_class <= VI &&
3721 sscreen->b.family != CHIP_STONEY) {
3722 if (num_format == V_008F0C_BUF_NUM_FORMAT_SNORM) {
3723 v->fix_fetch[i] = SI_FIX_FETCH_A2_SNORM;
3724 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SSCALED) {
3725 v->fix_fetch[i] = SI_FIX_FETCH_A2_SSCALED;
3726 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SINT) {
3727 /* This isn't actually used in OpenGL. */
3728 v->fix_fetch[i] = SI_FIX_FETCH_A2_SINT;
3729 }
3730 } else if (channel && channel->type == UTIL_FORMAT_TYPE_FIXED) {
3731 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
3732 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_FIXED;
3733 else
3734 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_FIXED;
3735 } else if (channel && channel->size == 32 && !channel->pure_integer) {
3736 if (channel->type == UTIL_FORMAT_TYPE_SIGNED) {
3737 if (channel->normalized) {
3738 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
3739 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_SNORM;
3740 else
3741 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SNORM;
3742 } else {
3743 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SSCALED;
3744 }
3745 } else if (channel->type == UTIL_FORMAT_TYPE_UNSIGNED) {
3746 if (channel->normalized) {
3747 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
3748 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_UNORM;
3749 else
3750 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_UNORM;
3751 } else {
3752 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_USCALED;
3753 }
3754 }
3755 } else if (channel && channel->size == 64 &&
3756 channel->type == UTIL_FORMAT_TYPE_FLOAT) {
3757 switch (desc->nr_channels) {
3758 case 1:
3759 case 2:
3760 v->fix_fetch[i] = SI_FIX_FETCH_RG_64_FLOAT;
3761 swizzle[0] = PIPE_SWIZZLE_X;
3762 swizzle[1] = PIPE_SWIZZLE_Y;
3763 swizzle[2] = desc->nr_channels == 2 ? PIPE_SWIZZLE_Z : PIPE_SWIZZLE_0;
3764 swizzle[3] = desc->nr_channels == 2 ? PIPE_SWIZZLE_W : PIPE_SWIZZLE_0;
3765 break;
3766 case 3:
3767 v->fix_fetch[i] = SI_FIX_FETCH_RGB_64_FLOAT;
3768 swizzle[0] = PIPE_SWIZZLE_X; /* 3 loads */
3769 swizzle[1] = PIPE_SWIZZLE_Y;
3770 swizzle[2] = PIPE_SWIZZLE_0;
3771 swizzle[3] = PIPE_SWIZZLE_0;
3772 break;
3773 case 4:
3774 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_64_FLOAT;
3775 swizzle[0] = PIPE_SWIZZLE_X; /* 2 loads */
3776 swizzle[1] = PIPE_SWIZZLE_Y;
3777 swizzle[2] = PIPE_SWIZZLE_Z;
3778 swizzle[3] = PIPE_SWIZZLE_W;
3779 break;
3780 default:
3781 assert(0);
3782 }
3783 } else if (channel && desc->nr_channels == 3) {
3784 assert(desc->swizzle[0] == PIPE_SWIZZLE_X);
3785
3786 if (channel->size == 8) {
3787 if (channel->pure_integer)
3788 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8_INT;
3789 else
3790 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8;
3791 } else if (channel->size == 16) {
3792 if (channel->pure_integer)
3793 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16_INT;
3794 else
3795 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16;
3796 }
3797 }
3798
3799 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
3800 S_008F0C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
3801 S_008F0C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
3802 S_008F0C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
3803 S_008F0C_NUM_FORMAT(num_format) |
3804 S_008F0C_DATA_FORMAT(data_format);
3805 }
3806 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
3807
3808 return v;
3809 }
3810
3811 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
3812 {
3813 struct si_context *sctx = (struct si_context *)ctx;
3814 struct si_vertex_element *v = (struct si_vertex_element*)state;
3815
3816 sctx->vertex_elements = v;
3817 sctx->vertex_buffers_dirty = true;
3818 sctx->do_update_shaders = true;
3819 }
3820
3821 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
3822 {
3823 struct si_context *sctx = (struct si_context *)ctx;
3824
3825 if (sctx->vertex_elements == state)
3826 sctx->vertex_elements = NULL;
3827 FREE(state);
3828 }
3829
3830 static void si_set_vertex_buffers(struct pipe_context *ctx,
3831 unsigned start_slot, unsigned count,
3832 const struct pipe_vertex_buffer *buffers)
3833 {
3834 struct si_context *sctx = (struct si_context *)ctx;
3835 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
3836 int i;
3837
3838 assert(start_slot + count <= ARRAY_SIZE(sctx->vertex_buffer));
3839
3840 if (buffers) {
3841 for (i = 0; i < count; i++) {
3842 const struct pipe_vertex_buffer *src = buffers + i;
3843 struct pipe_vertex_buffer *dsti = dst + i;
3844 struct pipe_resource *buf = src->buffer.resource;
3845
3846 pipe_resource_reference(&dsti->buffer.resource, buf);
3847 dsti->buffer_offset = src->buffer_offset;
3848 dsti->stride = src->stride;
3849 r600_context_add_resource_size(ctx, buf);
3850 if (buf)
3851 r600_resource(buf)->bind_history |= PIPE_BIND_VERTEX_BUFFER;
3852 }
3853 } else {
3854 for (i = 0; i < count; i++) {
3855 pipe_resource_reference(&dst[i].buffer.resource, NULL);
3856 }
3857 }
3858 sctx->vertex_buffers_dirty = true;
3859 }
3860
3861 /*
3862 * Misc
3863 */
3864
3865 static void si_set_tess_state(struct pipe_context *ctx,
3866 const float default_outer_level[4],
3867 const float default_inner_level[2])
3868 {
3869 struct si_context *sctx = (struct si_context *)ctx;
3870 struct pipe_constant_buffer cb;
3871 float array[8];
3872
3873 memcpy(array, default_outer_level, sizeof(float) * 4);
3874 memcpy(array+4, default_inner_level, sizeof(float) * 2);
3875
3876 cb.buffer = NULL;
3877 cb.user_buffer = NULL;
3878 cb.buffer_size = sizeof(array);
3879
3880 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
3881 (void*)array, sizeof(array),
3882 &cb.buffer_offset);
3883
3884 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
3885 pipe_resource_reference(&cb.buffer, NULL);
3886 }
3887
3888 static void si_texture_barrier(struct pipe_context *ctx, unsigned flags)
3889 {
3890 struct si_context *sctx = (struct si_context *)ctx;
3891
3892 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
3893 SI_CONTEXT_INV_GLOBAL_L2 |
3894 SI_CONTEXT_FLUSH_AND_INV_CB;
3895 sctx->framebuffer.do_update_surf_dirtiness = true;
3896 }
3897
3898 /* This only ensures coherency for shader image/buffer stores. */
3899 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
3900 {
3901 struct si_context *sctx = (struct si_context *)ctx;
3902
3903 /* Subsequent commands must wait for all shader invocations to
3904 * complete. */
3905 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
3906 SI_CONTEXT_CS_PARTIAL_FLUSH;
3907
3908 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
3909 sctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 |
3910 SI_CONTEXT_INV_VMEM_L1;
3911
3912 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
3913 PIPE_BARRIER_SHADER_BUFFER |
3914 PIPE_BARRIER_TEXTURE |
3915 PIPE_BARRIER_IMAGE |
3916 PIPE_BARRIER_STREAMOUT_BUFFER |
3917 PIPE_BARRIER_GLOBAL_BUFFER)) {
3918 /* As far as I can tell, L1 contents are written back to L2
3919 * automatically at end of shader, but the contents of other
3920 * L1 caches might still be stale. */
3921 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
3922 }
3923
3924 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
3925 /* Indices are read through TC L2 since VI.
3926 * L1 isn't used.
3927 */
3928 if (sctx->screen->b.chip_class <= CIK)
3929 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
3930 }
3931
3932 if (flags & PIPE_BARRIER_FRAMEBUFFER)
3933 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_CB |
3934 SI_CONTEXT_FLUSH_AND_INV_DB;
3935
3936 if (flags & (PIPE_BARRIER_FRAMEBUFFER |
3937 PIPE_BARRIER_INDIRECT_BUFFER))
3938 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
3939 }
3940
3941 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
3942 {
3943 struct pipe_blend_state blend;
3944
3945 memset(&blend, 0, sizeof(blend));
3946 blend.independent_blend_enable = true;
3947 blend.rt[0].colormask = 0xf;
3948 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
3949 }
3950
3951 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
3952 bool include_draw_vbo)
3953 {
3954 si_need_cs_space((struct si_context*)ctx);
3955 }
3956
3957 static void si_init_config(struct si_context *sctx);
3958
3959 void si_init_state_functions(struct si_context *sctx)
3960 {
3961 si_init_external_atom(sctx, &sctx->b.render_cond_atom, &sctx->atoms.s.render_cond);
3962 si_init_external_atom(sctx, &sctx->b.streamout.begin_atom, &sctx->atoms.s.streamout_begin);
3963 si_init_external_atom(sctx, &sctx->b.streamout.enable_atom, &sctx->atoms.s.streamout_enable);
3964 si_init_external_atom(sctx, &sctx->b.scissors.atom, &sctx->atoms.s.scissors);
3965 si_init_external_atom(sctx, &sctx->b.viewports.atom, &sctx->atoms.s.viewports);
3966
3967 si_init_atom(sctx, &sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state);
3968 si_init_atom(sctx, &sctx->msaa_sample_locs.atom, &sctx->atoms.s.msaa_sample_locs, si_emit_msaa_sample_locs);
3969 si_init_atom(sctx, &sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state);
3970 si_init_atom(sctx, &sctx->msaa_config, &sctx->atoms.s.msaa_config, si_emit_msaa_config);
3971 si_init_atom(sctx, &sctx->sample_mask.atom, &sctx->atoms.s.sample_mask, si_emit_sample_mask);
3972 si_init_atom(sctx, &sctx->cb_render_state, &sctx->atoms.s.cb_render_state, si_emit_cb_render_state);
3973 si_init_atom(sctx, &sctx->blend_color.atom, &sctx->atoms.s.blend_color, si_emit_blend_color);
3974 si_init_atom(sctx, &sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs);
3975 si_init_atom(sctx, &sctx->clip_state.atom, &sctx->atoms.s.clip_state, si_emit_clip_state);
3976 si_init_atom(sctx, &sctx->stencil_ref.atom, &sctx->atoms.s.stencil_ref, si_emit_stencil_ref);
3977
3978 sctx->b.b.create_blend_state = si_create_blend_state;
3979 sctx->b.b.bind_blend_state = si_bind_blend_state;
3980 sctx->b.b.delete_blend_state = si_delete_blend_state;
3981 sctx->b.b.set_blend_color = si_set_blend_color;
3982
3983 sctx->b.b.create_rasterizer_state = si_create_rs_state;
3984 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
3985 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
3986
3987 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
3988 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
3989 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
3990
3991 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
3992 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
3993 sctx->custom_blend_fmask_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
3994 sctx->custom_blend_eliminate_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
3995 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
3996
3997 sctx->b.b.set_clip_state = si_set_clip_state;
3998 sctx->b.b.set_stencil_ref = si_set_stencil_ref;
3999
4000 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
4001 sctx->b.b.get_sample_position = cayman_get_sample_position;
4002
4003 sctx->b.b.create_sampler_state = si_create_sampler_state;
4004 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
4005
4006 sctx->b.b.create_sampler_view = si_create_sampler_view;
4007 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
4008
4009 sctx->b.b.set_sample_mask = si_set_sample_mask;
4010
4011 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
4012 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
4013 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
4014 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
4015
4016 sctx->b.b.texture_barrier = si_texture_barrier;
4017 sctx->b.b.memory_barrier = si_memory_barrier;
4018 sctx->b.b.set_min_samples = si_set_min_samples;
4019 sctx->b.b.set_tess_state = si_set_tess_state;
4020
4021 sctx->b.b.set_active_query_state = si_set_active_query_state;
4022 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
4023 sctx->b.save_qbo_state = si_save_qbo_state;
4024 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
4025
4026 sctx->b.b.draw_vbo = si_draw_vbo;
4027
4028 si_init_config(sctx);
4029 }
4030
4031 static uint32_t si_get_bo_metadata_word1(struct r600_common_screen *rscreen)
4032 {
4033 return (ATI_VENDOR_ID << 16) | rscreen->info.pci_id;
4034 }
4035
4036 static void si_query_opaque_metadata(struct r600_common_screen *rscreen,
4037 struct r600_texture *rtex,
4038 struct radeon_bo_metadata *md)
4039 {
4040 struct si_screen *sscreen = (struct si_screen*)rscreen;
4041 struct pipe_resource *res = &rtex->resource.b.b;
4042 static const unsigned char swizzle[] = {
4043 PIPE_SWIZZLE_X,
4044 PIPE_SWIZZLE_Y,
4045 PIPE_SWIZZLE_Z,
4046 PIPE_SWIZZLE_W
4047 };
4048 uint32_t desc[8], i;
4049 bool is_array = util_resource_is_array_texture(res);
4050
4051 /* DRM 2.x.x doesn't support this. */
4052 if (rscreen->info.drm_major != 3)
4053 return;
4054
4055 assert(rtex->dcc_separate_buffer == NULL);
4056 assert(rtex->fmask.size == 0);
4057
4058 /* Metadata image format format version 1:
4059 * [0] = 1 (metadata format identifier)
4060 * [1] = (VENDOR_ID << 16) | PCI_ID
4061 * [2:9] = image descriptor for the whole resource
4062 * [2] is always 0, because the base address is cleared
4063 * [9] is the DCC offset bits [39:8] from the beginning of
4064 * the buffer
4065 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
4066 */
4067
4068 md->metadata[0] = 1; /* metadata image format version 1 */
4069
4070 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
4071 md->metadata[1] = si_get_bo_metadata_word1(rscreen);
4072
4073 si_make_texture_descriptor(sscreen, rtex, true,
4074 res->target, res->format,
4075 swizzle, 0, res->last_level, 0,
4076 is_array ? res->array_size - 1 : 0,
4077 res->width0, res->height0, res->depth0,
4078 desc, NULL);
4079
4080 si_set_mutable_tex_desc_fields(sscreen, rtex, &rtex->surface.u.legacy.level[0],
4081 0, 0, rtex->surface.blk_w, false, desc);
4082
4083 /* Clear the base address and set the relative DCC offset. */
4084 desc[0] = 0;
4085 desc[1] &= C_008F14_BASE_ADDRESS_HI;
4086 desc[7] = rtex->dcc_offset >> 8;
4087
4088 /* Dwords [2:9] contain the image descriptor. */
4089 memcpy(&md->metadata[2], desc, sizeof(desc));
4090 md->size_metadata = 10 * 4;
4091
4092 /* Dwords [10:..] contain the mipmap level offsets. */
4093 if (rscreen->chip_class <= VI) {
4094 for (i = 0; i <= res->last_level; i++)
4095 md->metadata[10+i] = rtex->surface.u.legacy.level[i].offset >> 8;
4096
4097 md->size_metadata += (1 + res->last_level) * 4;
4098 }
4099 }
4100
4101 static void si_apply_opaque_metadata(struct r600_common_screen *rscreen,
4102 struct r600_texture *rtex,
4103 struct radeon_bo_metadata *md)
4104 {
4105 uint32_t *desc = &md->metadata[2];
4106
4107 if (rscreen->chip_class < VI)
4108 return;
4109
4110 /* Return if DCC is enabled. The texture should be set up with it
4111 * already.
4112 */
4113 if (md->size_metadata >= 11 * 4 &&
4114 md->metadata[0] != 0 &&
4115 md->metadata[1] == si_get_bo_metadata_word1(rscreen) &&
4116 G_008F28_COMPRESSION_EN(desc[6])) {
4117 assert(rtex->dcc_offset == ((uint64_t)desc[7] << 8));
4118 return;
4119 }
4120
4121 /* Disable DCC. These are always set by texture_from_handle and must
4122 * be cleared here.
4123 */
4124 rtex->dcc_offset = 0;
4125 }
4126
4127 void si_init_screen_state_functions(struct si_screen *sscreen)
4128 {
4129 sscreen->b.b.is_format_supported = si_is_format_supported;
4130 sscreen->b.query_opaque_metadata = si_query_opaque_metadata;
4131 sscreen->b.apply_opaque_metadata = si_apply_opaque_metadata;
4132 }
4133
4134 static void
4135 si_write_harvested_raster_configs(struct si_context *sctx,
4136 struct si_pm4_state *pm4,
4137 unsigned raster_config,
4138 unsigned raster_config_1)
4139 {
4140 unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1);
4141 unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1);
4142 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
4143 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
4144 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
4145 unsigned rb_per_se = num_rb / num_se;
4146 unsigned se_mask[4];
4147 unsigned se;
4148
4149 se_mask[0] = ((1 << rb_per_se) - 1);
4150 se_mask[1] = (se_mask[0] << rb_per_se);
4151 se_mask[2] = (se_mask[1] << rb_per_se);
4152 se_mask[3] = (se_mask[2] << rb_per_se);
4153
4154 se_mask[0] &= rb_mask;
4155 se_mask[1] &= rb_mask;
4156 se_mask[2] &= rb_mask;
4157 se_mask[3] &= rb_mask;
4158
4159 assert(num_se == 1 || num_se == 2 || num_se == 4);
4160 assert(sh_per_se == 1 || sh_per_se == 2);
4161 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
4162
4163 /* XXX: I can't figure out what the *_XSEL and *_YSEL
4164 * fields are for, so I'm leaving them as their default
4165 * values. */
4166
4167 for (se = 0; se < num_se; se++) {
4168 unsigned raster_config_se = raster_config;
4169 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
4170 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
4171 int idx = (se / 2) * 2;
4172
4173 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
4174 raster_config_se &= C_028350_SE_MAP;
4175
4176 if (!se_mask[idx]) {
4177 raster_config_se |=
4178 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
4179 } else {
4180 raster_config_se |=
4181 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
4182 }
4183 }
4184
4185 pkr0_mask &= rb_mask;
4186 pkr1_mask &= rb_mask;
4187 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
4188 raster_config_se &= C_028350_PKR_MAP;
4189
4190 if (!pkr0_mask) {
4191 raster_config_se |=
4192 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
4193 } else {
4194 raster_config_se |=
4195 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
4196 }
4197 }
4198
4199 if (rb_per_se >= 2) {
4200 unsigned rb0_mask = 1 << (se * rb_per_se);
4201 unsigned rb1_mask = rb0_mask << 1;
4202
4203 rb0_mask &= rb_mask;
4204 rb1_mask &= rb_mask;
4205 if (!rb0_mask || !rb1_mask) {
4206 raster_config_se &= C_028350_RB_MAP_PKR0;
4207
4208 if (!rb0_mask) {
4209 raster_config_se |=
4210 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
4211 } else {
4212 raster_config_se |=
4213 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
4214 }
4215 }
4216
4217 if (rb_per_se > 2) {
4218 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
4219 rb1_mask = rb0_mask << 1;
4220 rb0_mask &= rb_mask;
4221 rb1_mask &= rb_mask;
4222 if (!rb0_mask || !rb1_mask) {
4223 raster_config_se &= C_028350_RB_MAP_PKR1;
4224
4225 if (!rb0_mask) {
4226 raster_config_se |=
4227 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
4228 } else {
4229 raster_config_se |=
4230 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
4231 }
4232 }
4233 }
4234 }
4235
4236 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
4237 if (sctx->b.chip_class < CIK)
4238 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
4239 SE_INDEX(se) | SH_BROADCAST_WRITES |
4240 INSTANCE_BROADCAST_WRITES);
4241 else
4242 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
4243 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
4244 S_030800_INSTANCE_BROADCAST_WRITES(1));
4245 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
4246 }
4247
4248 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
4249 if (sctx->b.chip_class < CIK)
4250 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
4251 SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
4252 INSTANCE_BROADCAST_WRITES);
4253 else {
4254 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
4255 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
4256 S_030800_INSTANCE_BROADCAST_WRITES(1));
4257
4258 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
4259 (!se_mask[2] && !se_mask[3]))) {
4260 raster_config_1 &= C_028354_SE_PAIR_MAP;
4261
4262 if (!se_mask[0] && !se_mask[1]) {
4263 raster_config_1 |=
4264 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
4265 } else {
4266 raster_config_1 |=
4267 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
4268 }
4269 }
4270
4271 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
4272 }
4273 }
4274
4275 static void si_init_config(struct si_context *sctx)
4276 {
4277 struct si_screen *sscreen = sctx->screen;
4278 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
4279 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
4280 unsigned raster_config, raster_config_1;
4281 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
4282 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
4283
4284 if (!pm4)
4285 return;
4286
4287 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
4288 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
4289 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
4290 si_pm4_cmd_end(pm4, false);
4291
4292 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
4293 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
4294
4295 /* FIXME calculate these values somehow ??? */
4296 if (sctx->b.chip_class <= VI) {
4297 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
4298 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
4299 }
4300 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
4301
4302 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
4303 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
4304
4305 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
4306 si_pm4_set_reg(pm4, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
4307 if (sctx->b.chip_class >= GFX9)
4308 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0);
4309 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
4310 if (sctx->b.chip_class < CIK)
4311 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
4312 S_008A14_CLIP_VTX_REORDER_ENA(1));
4313
4314 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
4315 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
4316
4317 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
4318
4319 switch (sctx->screen->b.family) {
4320 case CHIP_TAHITI:
4321 case CHIP_PITCAIRN:
4322 raster_config = 0x2a00126a;
4323 raster_config_1 = 0x00000000;
4324 break;
4325 case CHIP_VERDE:
4326 raster_config = 0x0000124a;
4327 raster_config_1 = 0x00000000;
4328 break;
4329 case CHIP_OLAND:
4330 raster_config = 0x00000082;
4331 raster_config_1 = 0x00000000;
4332 break;
4333 case CHIP_HAINAN:
4334 raster_config = 0x00000000;
4335 raster_config_1 = 0x00000000;
4336 break;
4337 case CHIP_BONAIRE:
4338 raster_config = 0x16000012;
4339 raster_config_1 = 0x00000000;
4340 break;
4341 case CHIP_HAWAII:
4342 raster_config = 0x3a00161a;
4343 raster_config_1 = 0x0000002e;
4344 break;
4345 case CHIP_FIJI:
4346 if (sscreen->b.info.cik_macrotile_mode_array[0] == 0x000000e8) {
4347 /* old kernels with old tiling config */
4348 raster_config = 0x16000012;
4349 raster_config_1 = 0x0000002a;
4350 } else {
4351 raster_config = 0x3a00161a;
4352 raster_config_1 = 0x0000002e;
4353 }
4354 break;
4355 case CHIP_POLARIS10:
4356 raster_config = 0x16000012;
4357 raster_config_1 = 0x0000002a;
4358 break;
4359 case CHIP_POLARIS11:
4360 case CHIP_POLARIS12:
4361 raster_config = 0x16000012;
4362 raster_config_1 = 0x00000000;
4363 break;
4364 case CHIP_TONGA:
4365 raster_config = 0x16000012;
4366 raster_config_1 = 0x0000002a;
4367 break;
4368 case CHIP_ICELAND:
4369 if (num_rb == 1)
4370 raster_config = 0x00000000;
4371 else
4372 raster_config = 0x00000002;
4373 raster_config_1 = 0x00000000;
4374 break;
4375 case CHIP_CARRIZO:
4376 raster_config = 0x00000002;
4377 raster_config_1 = 0x00000000;
4378 break;
4379 case CHIP_KAVERI:
4380 /* KV should be 0x00000002, but that causes problems with radeon */
4381 raster_config = 0x00000000; /* 0x00000002 */
4382 raster_config_1 = 0x00000000;
4383 break;
4384 case CHIP_KABINI:
4385 case CHIP_MULLINS:
4386 case CHIP_STONEY:
4387 raster_config = 0x00000000;
4388 raster_config_1 = 0x00000000;
4389 break;
4390 default:
4391 if (sctx->b.chip_class <= VI) {
4392 fprintf(stderr,
4393 "radeonsi: Unknown GPU, using 0 for raster_config\n");
4394 raster_config = 0x00000000;
4395 raster_config_1 = 0x00000000;
4396 }
4397 break;
4398 }
4399
4400 if (sctx->b.chip_class <= VI) {
4401 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
4402 /* Always use the default config when all backends are enabled
4403 * (or when we failed to determine the enabled backends).
4404 */
4405 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
4406 raster_config);
4407 if (sctx->b.chip_class >= CIK)
4408 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
4409 raster_config_1);
4410 } else {
4411 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
4412 }
4413 }
4414
4415 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
4416 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
4417 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
4418 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
4419 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
4420 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
4421 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
4422
4423 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
4424 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
4425 S_028230_ER_TRI(0xA) |
4426 S_028230_ER_POINT(0xA) |
4427 S_028230_ER_RECT(0xA) |
4428 /* Required by DX10_DIAMOND_TEST_ENA: */
4429 S_028230_ER_LINE_LR(0x1A) |
4430 S_028230_ER_LINE_RL(0x26) |
4431 S_028230_ER_LINE_TB(0xA) |
4432 S_028230_ER_LINE_BT(0xA));
4433 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
4434 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
4435 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
4436 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
4437 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
4438 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
4439 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 0);
4440
4441 if (sctx->b.chip_class >= GFX9) {
4442 si_pm4_set_reg(pm4, R_030920_VGT_MAX_VTX_INDX, ~0);
4443 si_pm4_set_reg(pm4, R_030924_VGT_MIN_VTX_INDX, 0);
4444 si_pm4_set_reg(pm4, R_030928_VGT_INDX_OFFSET, 0);
4445 } else {
4446 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
4447 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
4448 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
4449 }
4450
4451 if (sctx->b.chip_class >= CIK) {
4452 if (sctx->b.chip_class >= GFX9) {
4453 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, S_00B41C_CU_EN(0xffff));
4454 } else {
4455 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff));
4456 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
4457 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xffff));
4458
4459 /* If this is 0, Bonaire can hang even if GS isn't being used.
4460 * Other chips are unaffected. These are suboptimal values,
4461 * but we don't use on-chip GS.
4462 */
4463 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
4464 S_028A44_ES_VERTS_PER_SUBGRP(64) |
4465 S_028A44_GS_PRIMS_PER_SUBGRP(4));
4466 }
4467 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
4468
4469 if (sscreen->b.info.num_good_compute_units /
4470 (sscreen->b.info.max_se * sscreen->b.info.max_sh_per_se) <= 4) {
4471 /* Too few available compute units per SH. Disallowing
4472 * VS to run on CU0 could hurt us more than late VS
4473 * allocation would help.
4474 *
4475 * LATE_ALLOC_VS = 2 is the highest safe number.
4476 */
4477 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
4478 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
4479 } else {
4480 /* Set LATE_ALLOC_VS == 31. It should be less than
4481 * the number of scratch waves. Limitations:
4482 * - VS can't execute on CU0.
4483 * - If HS writes outputs to LDS, LS can't execute on CU0.
4484 */
4485 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xfffe));
4486 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
4487 }
4488
4489 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
4490 }
4491
4492 if (sctx->b.chip_class >= VI) {
4493 unsigned vgt_tess_distribution;
4494
4495 si_pm4_set_reg(pm4, R_028424_CB_DCC_CONTROL,
4496 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
4497 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
4498 if (sctx->b.family < CHIP_POLARIS10)
4499 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
4500 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
4501
4502 vgt_tess_distribution =
4503 S_028B50_ACCUM_ISOLINE(32) |
4504 S_028B50_ACCUM_TRI(11) |
4505 S_028B50_ACCUM_QUAD(11) |
4506 S_028B50_DONUT_SPLIT(16);
4507
4508 /* Testing with Unigine Heaven extreme tesselation yielded best results
4509 * with TRAP_SPLIT = 3.
4510 */
4511 if (sctx->b.family == CHIP_FIJI ||
4512 sctx->b.family >= CHIP_POLARIS10)
4513 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
4514
4515 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution);
4516 } else {
4517 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
4518 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
4519 }
4520
4521 if (sctx->screen->b.has_rbplus)
4522 si_pm4_set_reg(pm4, R_028C40_PA_SC_SHADER_CONTROL, 0);
4523
4524 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
4525 if (sctx->b.chip_class >= CIK)
4526 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, border_color_va >> 40);
4527 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
4528 RADEON_PRIO_BORDER_COLORS);
4529
4530 if (sctx->b.chip_class >= GFX9) {
4531 unsigned num_se = sscreen->b.info.max_se;
4532 unsigned pc_lines = 0;
4533
4534 switch (sctx->b.family) {
4535 case CHIP_VEGA10:
4536 pc_lines = 4096;
4537 break;
4538 case CHIP_RAVEN:
4539 pc_lines = 1024;
4540 break;
4541 default:
4542 assert(0);
4543 }
4544
4545 si_pm4_set_reg(pm4, R_028060_DB_DFSM_CONTROL,
4546 S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF));
4547 si_pm4_set_reg(pm4, R_028064_DB_RENDER_FILTER, 0);
4548 /* TODO: We can use this to disable RBs for rendering to GART: */
4549 si_pm4_set_reg(pm4, R_02835C_PA_SC_TILE_STEERING_OVERRIDE, 0);
4550 si_pm4_set_reg(pm4, R_02883C_PA_SU_OVER_RASTERIZATION_CNTL, 0);
4551 /* TODO: Enable the binner: */
4552 si_pm4_set_reg(pm4, R_028C44_PA_SC_BINNER_CNTL_0,
4553 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
4554 S_028C44_DISABLE_START_OF_PRIM(1));
4555 si_pm4_set_reg(pm4, R_028C48_PA_SC_BINNER_CNTL_1,
4556 S_028C48_MAX_ALLOC_COUNT(MIN2(128, pc_lines / (4 * num_se))) |
4557 S_028C48_MAX_PRIM_PER_BATCH(1023));
4558 si_pm4_set_reg(pm4, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
4559 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
4560 si_pm4_set_reg(pm4, R_030968_VGT_INSTANCE_BASE_ID, 0);
4561 }
4562
4563 si_pm4_upload_indirect_buffer(sctx, pm4);
4564 sctx->init_config = pm4;
4565 }