2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Christian König <christian.koenig@amd.com>
30 #include "radeon/r600_cs.h"
31 #include "radeon/r600_query.h"
33 #include "util/u_dual_blend.h"
34 #include "util/u_format.h"
35 #include "util/u_format_s3tc.h"
36 #include "util/u_memory.h"
37 #include "util/u_resource.h"
38 #include "util/u_upload_mgr.h"
40 /* Initialize an external atom (owned by ../radeon). */
42 si_init_external_atom(struct si_context
*sctx
, struct r600_atom
*atom
,
43 struct r600_atom
**list_elem
)
45 atom
->id
= list_elem
- sctx
->atoms
.array
;
49 /* Initialize an atom owned by radeonsi. */
50 void si_init_atom(struct si_context
*sctx
, struct r600_atom
*atom
,
51 struct r600_atom
**list_elem
,
52 void (*emit_func
)(struct si_context
*ctx
, struct r600_atom
*state
))
54 atom
->emit
= (void*)emit_func
;
55 atom
->id
= list_elem
- sctx
->atoms
.array
;
59 static unsigned si_map_swizzle(unsigned swizzle
)
63 return V_008F0C_SQ_SEL_Y
;
65 return V_008F0C_SQ_SEL_Z
;
67 return V_008F0C_SQ_SEL_W
;
69 return V_008F0C_SQ_SEL_0
;
71 return V_008F0C_SQ_SEL_1
;
72 default: /* PIPE_SWIZZLE_X */
73 return V_008F0C_SQ_SEL_X
;
77 /* 12.4 fixed-point */
78 static unsigned si_pack_float_12p4(float x
)
81 x
>= 4096 ? 0xffff : x
* 16;
85 * Inferred framebuffer and blender state.
87 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
88 * if there is not enough PS outputs.
90 static void si_emit_cb_render_state(struct si_context
*sctx
, struct r600_atom
*atom
)
92 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
93 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
94 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
95 * but you never know. */
96 uint32_t cb_target_mask
= sctx
->framebuffer
.colorbuf_enabled_4bit
;
100 cb_target_mask
&= blend
->cb_target_mask
;
102 /* Avoid a hang that happens when dual source blending is enabled
103 * but there is not enough color outputs. This is undefined behavior,
104 * so disable color writes completely.
106 * Reproducible with Unigine Heaven 4.0 and drirc missing.
108 if (blend
&& blend
->dual_src_blend
&&
109 sctx
->ps_shader
.cso
&&
110 (sctx
->ps_shader
.cso
->info
.colors_written
& 0x3) != 0x3)
113 radeon_set_context_reg(cs
, R_028238_CB_TARGET_MASK
, cb_target_mask
);
115 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
116 * I think we don't have to do anything between IBs.
118 if (sctx
->screen
->dfsm_allowed
&&
119 sctx
->last_cb_target_mask
!= cb_target_mask
) {
120 sctx
->last_cb_target_mask
= cb_target_mask
;
122 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
123 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
126 /* RB+ register settings. */
127 if (sctx
->screen
->b
.rbplus_allowed
) {
128 unsigned spi_shader_col_format
=
129 sctx
->ps_shader
.cso
?
130 sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.spi_shader_col_format
: 0;
131 unsigned sx_ps_downconvert
= 0;
132 unsigned sx_blend_opt_epsilon
= 0;
133 unsigned sx_blend_opt_control
= 0;
135 for (i
= 0; i
< sctx
->framebuffer
.state
.nr_cbufs
; i
++) {
136 struct r600_surface
*surf
=
137 (struct r600_surface
*)sctx
->framebuffer
.state
.cbufs
[i
];
138 unsigned format
, swap
, spi_format
, colormask
;
139 bool has_alpha
, has_rgb
;
144 format
= G_028C70_FORMAT(surf
->cb_color_info
);
145 swap
= G_028C70_COMP_SWAP(surf
->cb_color_info
);
146 spi_format
= (spi_shader_col_format
>> (i
* 4)) & 0xf;
147 colormask
= (cb_target_mask
>> (i
* 4)) & 0xf;
149 /* Set if RGB and A are present. */
150 has_alpha
= !G_028C74_FORCE_DST_ALPHA_1(surf
->cb_color_attrib
);
152 if (format
== V_028C70_COLOR_8
||
153 format
== V_028C70_COLOR_16
||
154 format
== V_028C70_COLOR_32
)
155 has_rgb
= !has_alpha
;
159 /* Check the colormask and export format. */
160 if (!(colormask
& (PIPE_MASK_RGBA
& ~PIPE_MASK_A
)))
162 if (!(colormask
& PIPE_MASK_A
))
165 if (spi_format
== V_028714_SPI_SHADER_ZERO
) {
170 /* Disable value checking for disabled channels. */
172 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
174 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
176 /* Enable down-conversion for 32bpp and smaller formats. */
178 case V_028C70_COLOR_8
:
179 case V_028C70_COLOR_8_8
:
180 case V_028C70_COLOR_8_8_8_8
:
181 /* For 1 and 2-channel formats, use the superset thereof. */
182 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
||
183 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
184 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
185 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_8_8_8_8
<< (i
* 4);
186 sx_blend_opt_epsilon
|= V_028758_8BIT_FORMAT
<< (i
* 4);
190 case V_028C70_COLOR_5_6_5
:
191 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
192 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_5_6_5
<< (i
* 4);
193 sx_blend_opt_epsilon
|= V_028758_6BIT_FORMAT
<< (i
* 4);
197 case V_028C70_COLOR_1_5_5_5
:
198 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
199 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_1_5_5_5
<< (i
* 4);
200 sx_blend_opt_epsilon
|= V_028758_5BIT_FORMAT
<< (i
* 4);
204 case V_028C70_COLOR_4_4_4_4
:
205 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
206 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_4_4_4_4
<< (i
* 4);
207 sx_blend_opt_epsilon
|= V_028758_4BIT_FORMAT
<< (i
* 4);
211 case V_028C70_COLOR_32
:
212 if (swap
== V_0280A0_SWAP_STD
&&
213 spi_format
== V_028714_SPI_SHADER_32_R
)
214 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_R
<< (i
* 4);
215 else if (swap
== V_0280A0_SWAP_ALT_REV
&&
216 spi_format
== V_028714_SPI_SHADER_32_AR
)
217 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_A
<< (i
* 4);
220 case V_028C70_COLOR_16
:
221 case V_028C70_COLOR_16_16
:
222 /* For 1-channel formats, use the superset thereof. */
223 if (spi_format
== V_028714_SPI_SHADER_UNORM16_ABGR
||
224 spi_format
== V_028714_SPI_SHADER_SNORM16_ABGR
||
225 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
226 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
227 if (swap
== V_0280A0_SWAP_STD
||
228 swap
== V_0280A0_SWAP_STD_REV
)
229 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_GR
<< (i
* 4);
231 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_AR
<< (i
* 4);
235 case V_028C70_COLOR_10_11_11
:
236 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
237 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_10_11_11
<< (i
* 4);
238 sx_blend_opt_epsilon
|= V_028758_11BIT_FORMAT
<< (i
* 4);
242 case V_028C70_COLOR_2_10_10_10
:
243 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
244 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_2_10_10_10
<< (i
* 4);
245 sx_blend_opt_epsilon
|= V_028758_10BIT_FORMAT
<< (i
* 4);
251 radeon_set_context_reg_seq(cs
, R_028754_SX_PS_DOWNCONVERT
, 3);
252 radeon_emit(cs
, sx_ps_downconvert
); /* R_028754_SX_PS_DOWNCONVERT */
253 radeon_emit(cs
, sx_blend_opt_epsilon
); /* R_028758_SX_BLEND_OPT_EPSILON */
254 radeon_emit(cs
, sx_blend_opt_control
); /* R_02875C_SX_BLEND_OPT_CONTROL */
255 } else if (sctx
->screen
->b
.has_rbplus
) {
256 radeon_set_context_reg_seq(cs
, R_028754_SX_PS_DOWNCONVERT
, 3);
257 radeon_emit(cs
, 0); /* R_028754_SX_PS_DOWNCONVERT */
258 radeon_emit(cs
, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
259 radeon_emit(cs
, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
267 static uint32_t si_translate_blend_function(int blend_func
)
269 switch (blend_func
) {
271 return V_028780_COMB_DST_PLUS_SRC
;
272 case PIPE_BLEND_SUBTRACT
:
273 return V_028780_COMB_SRC_MINUS_DST
;
274 case PIPE_BLEND_REVERSE_SUBTRACT
:
275 return V_028780_COMB_DST_MINUS_SRC
;
277 return V_028780_COMB_MIN_DST_SRC
;
279 return V_028780_COMB_MAX_DST_SRC
;
281 R600_ERR("Unknown blend function %d\n", blend_func
);
288 static uint32_t si_translate_blend_factor(int blend_fact
)
290 switch (blend_fact
) {
291 case PIPE_BLENDFACTOR_ONE
:
292 return V_028780_BLEND_ONE
;
293 case PIPE_BLENDFACTOR_SRC_COLOR
:
294 return V_028780_BLEND_SRC_COLOR
;
295 case PIPE_BLENDFACTOR_SRC_ALPHA
:
296 return V_028780_BLEND_SRC_ALPHA
;
297 case PIPE_BLENDFACTOR_DST_ALPHA
:
298 return V_028780_BLEND_DST_ALPHA
;
299 case PIPE_BLENDFACTOR_DST_COLOR
:
300 return V_028780_BLEND_DST_COLOR
;
301 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
302 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
303 case PIPE_BLENDFACTOR_CONST_COLOR
:
304 return V_028780_BLEND_CONSTANT_COLOR
;
305 case PIPE_BLENDFACTOR_CONST_ALPHA
:
306 return V_028780_BLEND_CONSTANT_ALPHA
;
307 case PIPE_BLENDFACTOR_ZERO
:
308 return V_028780_BLEND_ZERO
;
309 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
310 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
311 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
312 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
313 case PIPE_BLENDFACTOR_INV_DST_ALPHA
:
314 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
315 case PIPE_BLENDFACTOR_INV_DST_COLOR
:
316 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
317 case PIPE_BLENDFACTOR_INV_CONST_COLOR
:
318 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR
;
319 case PIPE_BLENDFACTOR_INV_CONST_ALPHA
:
320 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA
;
321 case PIPE_BLENDFACTOR_SRC1_COLOR
:
322 return V_028780_BLEND_SRC1_COLOR
;
323 case PIPE_BLENDFACTOR_SRC1_ALPHA
:
324 return V_028780_BLEND_SRC1_ALPHA
;
325 case PIPE_BLENDFACTOR_INV_SRC1_COLOR
:
326 return V_028780_BLEND_INV_SRC1_COLOR
;
327 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA
:
328 return V_028780_BLEND_INV_SRC1_ALPHA
;
330 R600_ERR("Bad blend factor %d not supported!\n", blend_fact
);
337 static uint32_t si_translate_blend_opt_function(int blend_func
)
339 switch (blend_func
) {
341 return V_028760_OPT_COMB_ADD
;
342 case PIPE_BLEND_SUBTRACT
:
343 return V_028760_OPT_COMB_SUBTRACT
;
344 case PIPE_BLEND_REVERSE_SUBTRACT
:
345 return V_028760_OPT_COMB_REVSUBTRACT
;
347 return V_028760_OPT_COMB_MIN
;
349 return V_028760_OPT_COMB_MAX
;
351 return V_028760_OPT_COMB_BLEND_DISABLED
;
355 static uint32_t si_translate_blend_opt_factor(int blend_fact
, bool is_alpha
)
357 switch (blend_fact
) {
358 case PIPE_BLENDFACTOR_ZERO
:
359 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL
;
360 case PIPE_BLENDFACTOR_ONE
:
361 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
;
362 case PIPE_BLENDFACTOR_SRC_COLOR
:
363 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
364 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0
;
365 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
366 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
367 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1
;
368 case PIPE_BLENDFACTOR_SRC_ALPHA
:
369 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
;
370 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
371 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
;
372 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
373 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
374 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
376 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
380 static void si_blend_check_commutativity(struct si_screen
*sscreen
,
381 struct si_state_blend
*blend
,
382 enum pipe_blend_func func
,
383 enum pipe_blendfactor src
,
384 enum pipe_blendfactor dst
,
387 /* Src factor is allowed when it does not depend on Dst */
388 static const uint32_t src_allowed
=
389 (1u << PIPE_BLENDFACTOR_ONE
) |
390 (1u << PIPE_BLENDFACTOR_SRC_COLOR
) |
391 (1u << PIPE_BLENDFACTOR_SRC_ALPHA
) |
392 (1u << PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
) |
393 (1u << PIPE_BLENDFACTOR_CONST_COLOR
) |
394 (1u << PIPE_BLENDFACTOR_CONST_ALPHA
) |
395 (1u << PIPE_BLENDFACTOR_SRC1_COLOR
) |
396 (1u << PIPE_BLENDFACTOR_SRC1_ALPHA
) |
397 (1u << PIPE_BLENDFACTOR_ZERO
) |
398 (1u << PIPE_BLENDFACTOR_INV_SRC_COLOR
) |
399 (1u << PIPE_BLENDFACTOR_INV_SRC_ALPHA
) |
400 (1u << PIPE_BLENDFACTOR_INV_CONST_COLOR
) |
401 (1u << PIPE_BLENDFACTOR_INV_CONST_ALPHA
) |
402 (1u << PIPE_BLENDFACTOR_INV_SRC1_COLOR
) |
403 (1u << PIPE_BLENDFACTOR_INV_SRC1_ALPHA
);
405 if (dst
== PIPE_BLENDFACTOR_ONE
&&
406 (src_allowed
& (1u << src
))) {
407 /* Addition is commutative, but floating point addition isn't
408 * associative: subtle changes can be introduced via different
411 * Out-of-order is also non-deterministic, which means that
412 * this breaks OpenGL invariance requirements. So only enable
413 * out-of-order additive blending if explicitly allowed by a
416 if (func
== PIPE_BLEND_MAX
|| func
== PIPE_BLEND_MIN
||
417 (func
== PIPE_BLEND_ADD
&& sscreen
->commutative_blend_add
))
418 blend
->commutative_4bit
|= chanmask
;
423 * Get rid of DST in the blend factors by commuting the operands:
424 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
426 static void si_blend_remove_dst(unsigned *func
, unsigned *src_factor
,
427 unsigned *dst_factor
, unsigned expected_dst
,
428 unsigned replacement_src
)
430 if (*src_factor
== expected_dst
&&
431 *dst_factor
== PIPE_BLENDFACTOR_ZERO
) {
432 *src_factor
= PIPE_BLENDFACTOR_ZERO
;
433 *dst_factor
= replacement_src
;
435 /* Commuting the operands requires reversing subtractions. */
436 if (*func
== PIPE_BLEND_SUBTRACT
)
437 *func
= PIPE_BLEND_REVERSE_SUBTRACT
;
438 else if (*func
== PIPE_BLEND_REVERSE_SUBTRACT
)
439 *func
= PIPE_BLEND_SUBTRACT
;
443 static bool si_blend_factor_uses_dst(unsigned factor
)
445 return factor
== PIPE_BLENDFACTOR_DST_COLOR
||
446 factor
== PIPE_BLENDFACTOR_DST_ALPHA
||
447 factor
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
448 factor
== PIPE_BLENDFACTOR_INV_DST_ALPHA
||
449 factor
== PIPE_BLENDFACTOR_INV_DST_COLOR
;
452 static void *si_create_blend_state_mode(struct pipe_context
*ctx
,
453 const struct pipe_blend_state
*state
,
456 struct si_context
*sctx
= (struct si_context
*)ctx
;
457 struct si_state_blend
*blend
= CALLOC_STRUCT(si_state_blend
);
458 struct si_pm4_state
*pm4
= &blend
->pm4
;
459 uint32_t sx_mrt_blend_opt
[8] = {0};
460 uint32_t color_control
= 0;
465 blend
->alpha_to_coverage
= state
->alpha_to_coverage
;
466 blend
->alpha_to_one
= state
->alpha_to_one
;
467 blend
->dual_src_blend
= util_blend_state_is_dual(state
, 0);
468 blend
->logicop_enable
= state
->logicop_enable
;
470 if (state
->logicop_enable
) {
471 color_control
|= S_028808_ROP3(state
->logicop_func
| (state
->logicop_func
<< 4));
473 color_control
|= S_028808_ROP3(0xcc);
476 si_pm4_set_reg(pm4
, R_028B70_DB_ALPHA_TO_MASK
,
477 S_028B70_ALPHA_TO_MASK_ENABLE(state
->alpha_to_coverage
) |
478 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
479 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
480 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
481 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
483 if (state
->alpha_to_coverage
)
484 blend
->need_src_alpha_4bit
|= 0xf;
486 blend
->cb_target_mask
= 0;
487 blend
->cb_target_enabled_4bit
= 0;
489 for (int i
= 0; i
< 8; i
++) {
490 /* state->rt entries > 0 only written if independent blending */
491 const int j
= state
->independent_blend_enable
? i
: 0;
493 unsigned eqRGB
= state
->rt
[j
].rgb_func
;
494 unsigned srcRGB
= state
->rt
[j
].rgb_src_factor
;
495 unsigned dstRGB
= state
->rt
[j
].rgb_dst_factor
;
496 unsigned eqA
= state
->rt
[j
].alpha_func
;
497 unsigned srcA
= state
->rt
[j
].alpha_src_factor
;
498 unsigned dstA
= state
->rt
[j
].alpha_dst_factor
;
500 unsigned srcRGB_opt
, dstRGB_opt
, srcA_opt
, dstA_opt
;
501 unsigned blend_cntl
= 0;
503 sx_mrt_blend_opt
[i
] =
504 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) |
505 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
507 /* Only set dual source blending for MRT0 to avoid a hang. */
508 if (i
>= 1 && blend
->dual_src_blend
) {
509 /* Vulkan does this for dual source blending. */
511 blend_cntl
|= S_028780_ENABLE(1);
513 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
517 /* Only addition and subtraction equations are supported with
518 * dual source blending.
520 if (blend
->dual_src_blend
&&
521 (eqRGB
== PIPE_BLEND_MIN
|| eqRGB
== PIPE_BLEND_MAX
||
522 eqA
== PIPE_BLEND_MIN
|| eqA
== PIPE_BLEND_MAX
)) {
523 assert(!"Unsupported equation for dual source blending");
524 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
528 /* cb_render_state will disable unused ones */
529 blend
->cb_target_mask
|= (unsigned)state
->rt
[j
].colormask
<< (4 * i
);
530 if (state
->rt
[j
].colormask
)
531 blend
->cb_target_enabled_4bit
|= 0xf << (4 * i
);
533 if (!state
->rt
[j
].colormask
|| !state
->rt
[j
].blend_enable
) {
534 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
538 si_blend_check_commutativity(sctx
->screen
, blend
,
539 eqRGB
, srcRGB
, dstRGB
, 0x7 << (4 * i
));
540 si_blend_check_commutativity(sctx
->screen
, blend
,
541 eqA
, srcA
, dstA
, 0x8 << (4 * i
));
543 /* Blending optimizations for RB+.
544 * These transformations don't change the behavior.
546 * First, get rid of DST in the blend factors:
547 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
549 si_blend_remove_dst(&eqRGB
, &srcRGB
, &dstRGB
,
550 PIPE_BLENDFACTOR_DST_COLOR
,
551 PIPE_BLENDFACTOR_SRC_COLOR
);
552 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
553 PIPE_BLENDFACTOR_DST_COLOR
,
554 PIPE_BLENDFACTOR_SRC_COLOR
);
555 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
556 PIPE_BLENDFACTOR_DST_ALPHA
,
557 PIPE_BLENDFACTOR_SRC_ALPHA
);
559 /* Look up the ideal settings from tables. */
560 srcRGB_opt
= si_translate_blend_opt_factor(srcRGB
, false);
561 dstRGB_opt
= si_translate_blend_opt_factor(dstRGB
, false);
562 srcA_opt
= si_translate_blend_opt_factor(srcA
, true);
563 dstA_opt
= si_translate_blend_opt_factor(dstA
, true);
565 /* Handle interdependencies. */
566 if (si_blend_factor_uses_dst(srcRGB
))
567 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
568 if (si_blend_factor_uses_dst(srcA
))
569 dstA_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
571 if (srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
&&
572 (dstRGB
== PIPE_BLENDFACTOR_ZERO
||
573 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
574 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
))
575 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
577 /* Set the final value. */
578 sx_mrt_blend_opt
[i
] =
579 S_028760_COLOR_SRC_OPT(srcRGB_opt
) |
580 S_028760_COLOR_DST_OPT(dstRGB_opt
) |
581 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB
)) |
582 S_028760_ALPHA_SRC_OPT(srcA_opt
) |
583 S_028760_ALPHA_DST_OPT(dstA_opt
) |
584 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA
));
586 /* Set blend state. */
587 blend_cntl
|= S_028780_ENABLE(1);
588 blend_cntl
|= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB
));
589 blend_cntl
|= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB
));
590 blend_cntl
|= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB
));
592 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
593 blend_cntl
|= S_028780_SEPARATE_ALPHA_BLEND(1);
594 blend_cntl
|= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA
));
595 blend_cntl
|= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA
));
596 blend_cntl
|= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA
));
598 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
600 blend
->blend_enable_4bit
|= 0xfu
<< (i
* 4);
602 /* This is only important for formats without alpha. */
603 if (srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
604 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
605 srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
606 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
607 srcRGB
== PIPE_BLENDFACTOR_INV_SRC_ALPHA
||
608 dstRGB
== PIPE_BLENDFACTOR_INV_SRC_ALPHA
)
609 blend
->need_src_alpha_4bit
|= 0xfu
<< (i
* 4);
612 if (blend
->cb_target_mask
) {
613 color_control
|= S_028808_MODE(mode
);
615 color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
618 if (sctx
->screen
->b
.has_rbplus
) {
619 /* Disable RB+ blend optimizations for dual source blending.
622 if (blend
->dual_src_blend
) {
623 for (int i
= 0; i
< 8; i
++) {
624 sx_mrt_blend_opt
[i
] =
625 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE
) |
626 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE
);
630 for (int i
= 0; i
< 8; i
++)
631 si_pm4_set_reg(pm4
, R_028760_SX_MRT0_BLEND_OPT
+ i
* 4,
632 sx_mrt_blend_opt
[i
]);
634 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
635 if (blend
->dual_src_blend
|| state
->logicop_enable
||
636 mode
== V_028808_CB_RESOLVE
)
637 color_control
|= S_028808_DISABLE_DUAL_QUAD(1);
640 si_pm4_set_reg(pm4
, R_028808_CB_COLOR_CONTROL
, color_control
);
644 static void *si_create_blend_state(struct pipe_context
*ctx
,
645 const struct pipe_blend_state
*state
)
647 return si_create_blend_state_mode(ctx
, state
, V_028808_CB_NORMAL
);
650 static void si_bind_blend_state(struct pipe_context
*ctx
, void *state
)
652 struct si_context
*sctx
= (struct si_context
*)ctx
;
653 struct si_state_blend
*old_blend
= sctx
->queued
.named
.blend
;
654 struct si_state_blend
*blend
= (struct si_state_blend
*)state
;
660 old_blend
->cb_target_mask
!= blend
->cb_target_mask
||
661 old_blend
->dual_src_blend
!= blend
->dual_src_blend
)
662 si_mark_atom_dirty(sctx
, &sctx
->cb_render_state
);
664 si_pm4_bind_state(sctx
, blend
, state
);
667 old_blend
->cb_target_mask
!= blend
->cb_target_mask
||
668 old_blend
->alpha_to_coverage
!= blend
->alpha_to_coverage
||
669 old_blend
->alpha_to_one
!= blend
->alpha_to_one
||
670 old_blend
->dual_src_blend
!= blend
->dual_src_blend
||
671 old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
||
672 old_blend
->need_src_alpha_4bit
!= blend
->need_src_alpha_4bit
)
673 sctx
->do_update_shaders
= true;
675 if (sctx
->screen
->dpbb_allowed
&&
677 old_blend
->alpha_to_coverage
!= blend
->alpha_to_coverage
||
678 old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
||
679 old_blend
->cb_target_enabled_4bit
!= blend
->cb_target_enabled_4bit
))
680 si_mark_atom_dirty(sctx
, &sctx
->dpbb_state
);
682 if (sctx
->screen
->has_out_of_order_rast
&&
684 (old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
||
685 old_blend
->cb_target_enabled_4bit
!= blend
->cb_target_enabled_4bit
||
686 old_blend
->commutative_4bit
!= blend
->commutative_4bit
||
687 old_blend
->logicop_enable
!= blend
->logicop_enable
)))
688 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
691 static void si_delete_blend_state(struct pipe_context
*ctx
, void *state
)
693 struct si_context
*sctx
= (struct si_context
*)ctx
;
694 si_pm4_delete_state(sctx
, blend
, (struct si_state_blend
*)state
);
697 static void si_set_blend_color(struct pipe_context
*ctx
,
698 const struct pipe_blend_color
*state
)
700 struct si_context
*sctx
= (struct si_context
*)ctx
;
701 static const struct pipe_blend_color zeros
;
703 sctx
->blend_color
.state
= *state
;
704 sctx
->blend_color
.any_nonzeros
= memcmp(state
, &zeros
, sizeof(*state
)) != 0;
705 si_mark_atom_dirty(sctx
, &sctx
->blend_color
.atom
);
708 static void si_emit_blend_color(struct si_context
*sctx
, struct r600_atom
*atom
)
710 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
712 radeon_set_context_reg_seq(cs
, R_028414_CB_BLEND_RED
, 4);
713 radeon_emit_array(cs
, (uint32_t*)sctx
->blend_color
.state
.color
, 4);
720 static void si_set_clip_state(struct pipe_context
*ctx
,
721 const struct pipe_clip_state
*state
)
723 struct si_context
*sctx
= (struct si_context
*)ctx
;
724 struct pipe_constant_buffer cb
;
725 static const struct pipe_clip_state zeros
;
727 if (memcmp(&sctx
->clip_state
.state
, state
, sizeof(*state
)) == 0)
730 sctx
->clip_state
.state
= *state
;
731 sctx
->clip_state
.any_nonzeros
= memcmp(state
, &zeros
, sizeof(*state
)) != 0;
732 si_mark_atom_dirty(sctx
, &sctx
->clip_state
.atom
);
735 cb
.user_buffer
= state
->ucp
;
736 cb
.buffer_offset
= 0;
737 cb
.buffer_size
= 4*4*8;
738 si_set_rw_buffer(sctx
, SI_VS_CONST_CLIP_PLANES
, &cb
);
739 pipe_resource_reference(&cb
.buffer
, NULL
);
742 static void si_emit_clip_state(struct si_context
*sctx
, struct r600_atom
*atom
)
744 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
746 radeon_set_context_reg_seq(cs
, R_0285BC_PA_CL_UCP_0_X
, 6*4);
747 radeon_emit_array(cs
, (uint32_t*)sctx
->clip_state
.state
.ucp
, 6*4);
750 static void si_emit_clip_regs(struct si_context
*sctx
, struct r600_atom
*atom
)
752 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
753 struct si_shader
*vs
= si_get_vs_state(sctx
);
754 struct si_shader_selector
*vs_sel
= vs
->selector
;
755 struct tgsi_shader_info
*info
= &vs_sel
->info
;
756 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
757 unsigned window_space
=
758 info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
759 unsigned clipdist_mask
= vs_sel
->clipdist_mask
;
760 unsigned ucp_mask
= clipdist_mask
? 0 : rs
->clip_plane_enable
& SIX_BITS
;
761 unsigned culldist_mask
= vs_sel
->culldist_mask
;
764 if (vs
->key
.opt
.clip_disable
) {
765 assert(!info
->culldist_writemask
);
769 total_mask
= clipdist_mask
| culldist_mask
;
771 /* Clip distances on points have no effect, so need to be implemented
772 * as cull distances. This applies for the clipvertex case as well.
774 * Setting this for primitives other than points should have no adverse
777 clipdist_mask
&= rs
->clip_plane_enable
;
778 culldist_mask
|= clipdist_mask
;
780 radeon_set_context_reg(cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
781 vs_sel
->pa_cl_vs_out_cntl
|
782 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0F) != 0) |
783 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xF0) != 0) |
784 clipdist_mask
| (culldist_mask
<< 8));
785 radeon_set_context_reg(cs
, R_028810_PA_CL_CLIP_CNTL
,
786 rs
->pa_cl_clip_cntl
|
788 S_028810_CLIP_DISABLE(window_space
));
792 * inferred state between framebuffer and rasterizer
794 static void si_update_poly_offset_state(struct si_context
*sctx
)
796 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
798 if (!rs
|| !rs
->uses_poly_offset
|| !sctx
->framebuffer
.state
.zsbuf
) {
799 si_pm4_bind_state(sctx
, poly_offset
, NULL
);
803 /* Use the user format, not db_render_format, so that the polygon
804 * offset behaves as expected by applications.
806 switch (sctx
->framebuffer
.state
.zsbuf
->texture
->format
) {
807 case PIPE_FORMAT_Z16_UNORM
:
808 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[0]);
810 default: /* 24-bit */
811 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[1]);
813 case PIPE_FORMAT_Z32_FLOAT
:
814 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
815 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[2]);
824 static uint32_t si_translate_fill(uint32_t func
)
827 case PIPE_POLYGON_MODE_FILL
:
828 return V_028814_X_DRAW_TRIANGLES
;
829 case PIPE_POLYGON_MODE_LINE
:
830 return V_028814_X_DRAW_LINES
;
831 case PIPE_POLYGON_MODE_POINT
:
832 return V_028814_X_DRAW_POINTS
;
835 return V_028814_X_DRAW_POINTS
;
839 static void *si_create_rs_state(struct pipe_context
*ctx
,
840 const struct pipe_rasterizer_state
*state
)
842 struct si_screen
*sscreen
= ((struct si_context
*)ctx
)->screen
;
843 struct si_state_rasterizer
*rs
= CALLOC_STRUCT(si_state_rasterizer
);
844 struct si_pm4_state
*pm4
= &rs
->pm4
;
846 float psize_min
, psize_max
;
852 rs
->scissor_enable
= state
->scissor
;
853 rs
->clip_halfz
= state
->clip_halfz
;
854 rs
->two_side
= state
->light_twoside
;
855 rs
->multisample_enable
= state
->multisample
;
856 rs
->force_persample_interp
= state
->force_persample_interp
;
857 rs
->clip_plane_enable
= state
->clip_plane_enable
;
858 rs
->line_stipple_enable
= state
->line_stipple_enable
;
859 rs
->poly_stipple_enable
= state
->poly_stipple_enable
;
860 rs
->line_smooth
= state
->line_smooth
;
861 rs
->poly_smooth
= state
->poly_smooth
;
862 rs
->uses_poly_offset
= state
->offset_point
|| state
->offset_line
||
864 rs
->clamp_fragment_color
= state
->clamp_fragment_color
;
865 rs
->clamp_vertex_color
= state
->clamp_vertex_color
;
866 rs
->flatshade
= state
->flatshade
;
867 rs
->sprite_coord_enable
= state
->sprite_coord_enable
;
868 rs
->rasterizer_discard
= state
->rasterizer_discard
;
869 rs
->pa_sc_line_stipple
= state
->line_stipple_enable
?
870 S_028A0C_LINE_PATTERN(state
->line_stipple_pattern
) |
871 S_028A0C_REPEAT_COUNT(state
->line_stipple_factor
) : 0;
872 rs
->pa_cl_clip_cntl
=
873 S_028810_DX_CLIP_SPACE_DEF(state
->clip_halfz
) |
874 S_028810_ZCLIP_NEAR_DISABLE(!state
->depth_clip
) |
875 S_028810_ZCLIP_FAR_DISABLE(!state
->depth_clip
) |
876 S_028810_DX_RASTERIZATION_KILL(state
->rasterizer_discard
) |
877 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
879 si_pm4_set_reg(pm4
, R_0286D4_SPI_INTERP_CONTROL_0
,
880 S_0286D4_FLAT_SHADE_ENA(1) |
881 S_0286D4_PNT_SPRITE_ENA(1) |
882 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S
) |
883 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T
) |
884 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0
) |
885 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1
) |
886 S_0286D4_PNT_SPRITE_TOP_1(state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
));
888 /* point size 12.4 fixed point */
889 tmp
= (unsigned)(state
->point_size
* 8.0);
890 si_pm4_set_reg(pm4
, R_028A00_PA_SU_POINT_SIZE
, S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
));
892 if (state
->point_size_per_vertex
) {
893 psize_min
= util_get_min_point_size(state
);
896 /* Force the point size to be as if the vertex output was disabled. */
897 psize_min
= state
->point_size
;
898 psize_max
= state
->point_size
;
900 /* Divide by two, because 0.5 = 1 pixel. */
901 si_pm4_set_reg(pm4
, R_028A04_PA_SU_POINT_MINMAX
,
902 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min
/2)) |
903 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max
/2)));
905 tmp
= (unsigned)state
->line_width
* 8;
906 si_pm4_set_reg(pm4
, R_028A08_PA_SU_LINE_CNTL
, S_028A08_WIDTH(tmp
));
907 si_pm4_set_reg(pm4
, R_028A48_PA_SC_MODE_CNTL_0
,
908 S_028A48_LINE_STIPPLE_ENABLE(state
->line_stipple_enable
) |
909 S_028A48_MSAA_ENABLE(state
->multisample
||
910 state
->poly_smooth
||
911 state
->line_smooth
) |
912 S_028A48_VPORT_SCISSOR_ENABLE(1) |
913 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen
->b
.chip_class
>= GFX9
));
915 si_pm4_set_reg(pm4
, R_028BE4_PA_SU_VTX_CNTL
,
916 S_028BE4_PIX_CENTER(state
->half_pixel_center
) |
917 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH
));
919 si_pm4_set_reg(pm4
, R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, fui(state
->offset_clamp
));
920 si_pm4_set_reg(pm4
, R_028814_PA_SU_SC_MODE_CNTL
,
921 S_028814_PROVOKING_VTX_LAST(!state
->flatshade_first
) |
922 S_028814_CULL_FRONT((state
->cull_face
& PIPE_FACE_FRONT
) ? 1 : 0) |
923 S_028814_CULL_BACK((state
->cull_face
& PIPE_FACE_BACK
) ? 1 : 0) |
924 S_028814_FACE(!state
->front_ccw
) |
925 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state
, state
->fill_front
)) |
926 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state
, state
->fill_back
)) |
927 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_point
|| state
->offset_line
) |
928 S_028814_POLY_MODE(state
->fill_front
!= PIPE_POLYGON_MODE_FILL
||
929 state
->fill_back
!= PIPE_POLYGON_MODE_FILL
) |
930 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state
->fill_front
)) |
931 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state
->fill_back
)));
933 if (!rs
->uses_poly_offset
)
936 rs
->pm4_poly_offset
= CALLOC(3, sizeof(struct si_pm4_state
));
937 if (!rs
->pm4_poly_offset
) {
942 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
943 for (i
= 0; i
< 3; i
++) {
944 struct si_pm4_state
*pm4
= &rs
->pm4_poly_offset
[i
];
945 float offset_units
= state
->offset_units
;
946 float offset_scale
= state
->offset_scale
* 16.0f
;
947 uint32_t pa_su_poly_offset_db_fmt_cntl
= 0;
949 if (!state
->offset_units_unscaled
) {
951 case 0: /* 16-bit zbuffer */
952 offset_units
*= 4.0f
;
953 pa_su_poly_offset_db_fmt_cntl
=
954 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
956 case 1: /* 24-bit zbuffer */
957 offset_units
*= 2.0f
;
958 pa_su_poly_offset_db_fmt_cntl
=
959 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
961 case 2: /* 32-bit zbuffer */
962 offset_units
*= 1.0f
;
963 pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
964 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
969 si_pm4_set_reg(pm4
, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE
,
971 si_pm4_set_reg(pm4
, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET
,
973 si_pm4_set_reg(pm4
, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE
,
975 si_pm4_set_reg(pm4
, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET
,
977 si_pm4_set_reg(pm4
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
978 pa_su_poly_offset_db_fmt_cntl
);
984 static void si_bind_rs_state(struct pipe_context
*ctx
, void *state
)
986 struct si_context
*sctx
= (struct si_context
*)ctx
;
987 struct si_state_rasterizer
*old_rs
=
988 (struct si_state_rasterizer
*)sctx
->queued
.named
.rasterizer
;
989 struct si_state_rasterizer
*rs
= (struct si_state_rasterizer
*)state
;
994 if (!old_rs
|| old_rs
->multisample_enable
!= rs
->multisample_enable
) {
995 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
997 /* Update the small primitive filter workaround if necessary. */
998 if (sctx
->screen
->has_msaa_sample_loc_bug
&&
999 sctx
->framebuffer
.nr_samples
> 1)
1000 si_mark_atom_dirty(sctx
, &sctx
->msaa_sample_locs
.atom
);
1003 sctx
->current_vs_state
&= C_VS_STATE_CLAMP_VERTEX_COLOR
;
1004 sctx
->current_vs_state
|= S_VS_STATE_CLAMP_VERTEX_COLOR(rs
->clamp_vertex_color
);
1006 r600_viewport_set_rast_deps(&sctx
->b
, rs
->scissor_enable
, rs
->clip_halfz
);
1008 si_pm4_bind_state(sctx
, rasterizer
, rs
);
1009 si_update_poly_offset_state(sctx
);
1012 old_rs
->clip_plane_enable
!= rs
->clip_plane_enable
||
1013 old_rs
->pa_cl_clip_cntl
!= rs
->pa_cl_clip_cntl
)
1014 si_mark_atom_dirty(sctx
, &sctx
->clip_regs
);
1016 sctx
->ia_multi_vgt_param_key
.u
.line_stipple_enabled
=
1017 rs
->line_stipple_enable
;
1020 old_rs
->clip_plane_enable
!= rs
->clip_plane_enable
||
1021 old_rs
->rasterizer_discard
!= rs
->rasterizer_discard
||
1022 old_rs
->sprite_coord_enable
!= rs
->sprite_coord_enable
||
1023 old_rs
->flatshade
!= rs
->flatshade
||
1024 old_rs
->two_side
!= rs
->two_side
||
1025 old_rs
->multisample_enable
!= rs
->multisample_enable
||
1026 old_rs
->poly_stipple_enable
!= rs
->poly_stipple_enable
||
1027 old_rs
->poly_smooth
!= rs
->poly_smooth
||
1028 old_rs
->line_smooth
!= rs
->line_smooth
||
1029 old_rs
->clamp_fragment_color
!= rs
->clamp_fragment_color
||
1030 old_rs
->force_persample_interp
!= rs
->force_persample_interp
)
1031 sctx
->do_update_shaders
= true;
1034 static void si_delete_rs_state(struct pipe_context
*ctx
, void *state
)
1036 struct si_context
*sctx
= (struct si_context
*)ctx
;
1037 struct si_state_rasterizer
*rs
= (struct si_state_rasterizer
*)state
;
1039 if (sctx
->queued
.named
.rasterizer
== state
)
1040 si_pm4_bind_state(sctx
, poly_offset
, NULL
);
1042 FREE(rs
->pm4_poly_offset
);
1043 si_pm4_delete_state(sctx
, rasterizer
, rs
);
1047 * infeered state between dsa and stencil ref
1049 static void si_emit_stencil_ref(struct si_context
*sctx
, struct r600_atom
*atom
)
1051 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
1052 struct pipe_stencil_ref
*ref
= &sctx
->stencil_ref
.state
;
1053 struct si_dsa_stencil_ref_part
*dsa
= &sctx
->stencil_ref
.dsa_part
;
1055 radeon_set_context_reg_seq(cs
, R_028430_DB_STENCILREFMASK
, 2);
1056 radeon_emit(cs
, S_028430_STENCILTESTVAL(ref
->ref_value
[0]) |
1057 S_028430_STENCILMASK(dsa
->valuemask
[0]) |
1058 S_028430_STENCILWRITEMASK(dsa
->writemask
[0]) |
1059 S_028430_STENCILOPVAL(1));
1060 radeon_emit(cs
, S_028434_STENCILTESTVAL_BF(ref
->ref_value
[1]) |
1061 S_028434_STENCILMASK_BF(dsa
->valuemask
[1]) |
1062 S_028434_STENCILWRITEMASK_BF(dsa
->writemask
[1]) |
1063 S_028434_STENCILOPVAL_BF(1));
1066 static void si_set_stencil_ref(struct pipe_context
*ctx
,
1067 const struct pipe_stencil_ref
*state
)
1069 struct si_context
*sctx
= (struct si_context
*)ctx
;
1071 if (memcmp(&sctx
->stencil_ref
.state
, state
, sizeof(*state
)) == 0)
1074 sctx
->stencil_ref
.state
= *state
;
1075 si_mark_atom_dirty(sctx
, &sctx
->stencil_ref
.atom
);
1083 static uint32_t si_translate_stencil_op(int s_op
)
1086 case PIPE_STENCIL_OP_KEEP
:
1087 return V_02842C_STENCIL_KEEP
;
1088 case PIPE_STENCIL_OP_ZERO
:
1089 return V_02842C_STENCIL_ZERO
;
1090 case PIPE_STENCIL_OP_REPLACE
:
1091 return V_02842C_STENCIL_REPLACE_TEST
;
1092 case PIPE_STENCIL_OP_INCR
:
1093 return V_02842C_STENCIL_ADD_CLAMP
;
1094 case PIPE_STENCIL_OP_DECR
:
1095 return V_02842C_STENCIL_SUB_CLAMP
;
1096 case PIPE_STENCIL_OP_INCR_WRAP
:
1097 return V_02842C_STENCIL_ADD_WRAP
;
1098 case PIPE_STENCIL_OP_DECR_WRAP
:
1099 return V_02842C_STENCIL_SUB_WRAP
;
1100 case PIPE_STENCIL_OP_INVERT
:
1101 return V_02842C_STENCIL_INVERT
;
1103 R600_ERR("Unknown stencil op %d", s_op
);
1110 static bool si_dsa_writes_stencil(const struct pipe_stencil_state
*s
)
1112 return s
->enabled
&& s
->writemask
&&
1113 (s
->fail_op
!= PIPE_STENCIL_OP_KEEP
||
1114 s
->zfail_op
!= PIPE_STENCIL_OP_KEEP
||
1115 s
->zpass_op
!= PIPE_STENCIL_OP_KEEP
);
1118 static bool si_order_invariant_stencil_op(enum pipe_stencil_op op
)
1120 /* REPLACE is normally order invariant, except when the stencil
1121 * reference value is written by the fragment shader. Tracking this
1122 * interaction does not seem worth the effort, so be conservative. */
1123 return op
!= PIPE_STENCIL_OP_INCR
&&
1124 op
!= PIPE_STENCIL_OP_DECR
&&
1125 op
!= PIPE_STENCIL_OP_REPLACE
;
1128 /* Compute whether, assuming Z writes are disabled, this stencil state is order
1129 * invariant in the sense that the set of passing fragments as well as the
1130 * final stencil buffer result does not depend on the order of fragments. */
1131 static bool si_order_invariant_stencil_state(const struct pipe_stencil_state
*state
)
1133 return !state
->enabled
|| !state
->writemask
||
1134 /* The following assumes that Z writes are disabled. */
1135 (state
->func
== PIPE_FUNC_ALWAYS
&&
1136 si_order_invariant_stencil_op(state
->zpass_op
) &&
1137 si_order_invariant_stencil_op(state
->zfail_op
)) ||
1138 (state
->func
== PIPE_FUNC_NEVER
&&
1139 si_order_invariant_stencil_op(state
->fail_op
));
1142 static void *si_create_dsa_state(struct pipe_context
*ctx
,
1143 const struct pipe_depth_stencil_alpha_state
*state
)
1145 struct si_context
*sctx
= (struct si_context
*)ctx
;
1146 struct si_state_dsa
*dsa
= CALLOC_STRUCT(si_state_dsa
);
1147 struct si_pm4_state
*pm4
= &dsa
->pm4
;
1148 unsigned db_depth_control
;
1149 uint32_t db_stencil_control
= 0;
1155 dsa
->stencil_ref
.valuemask
[0] = state
->stencil
[0].valuemask
;
1156 dsa
->stencil_ref
.valuemask
[1] = state
->stencil
[1].valuemask
;
1157 dsa
->stencil_ref
.writemask
[0] = state
->stencil
[0].writemask
;
1158 dsa
->stencil_ref
.writemask
[1] = state
->stencil
[1].writemask
;
1160 db_depth_control
= S_028800_Z_ENABLE(state
->depth
.enabled
) |
1161 S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
1162 S_028800_ZFUNC(state
->depth
.func
) |
1163 S_028800_DEPTH_BOUNDS_ENABLE(state
->depth
.bounds_test
);
1166 if (state
->stencil
[0].enabled
) {
1167 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
1168 db_depth_control
|= S_028800_STENCILFUNC(state
->stencil
[0].func
);
1169 db_stencil_control
|= S_02842C_STENCILFAIL(si_translate_stencil_op(state
->stencil
[0].fail_op
));
1170 db_stencil_control
|= S_02842C_STENCILZPASS(si_translate_stencil_op(state
->stencil
[0].zpass_op
));
1171 db_stencil_control
|= S_02842C_STENCILZFAIL(si_translate_stencil_op(state
->stencil
[0].zfail_op
));
1173 if (state
->stencil
[1].enabled
) {
1174 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
1175 db_depth_control
|= S_028800_STENCILFUNC_BF(state
->stencil
[1].func
);
1176 db_stencil_control
|= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state
->stencil
[1].fail_op
));
1177 db_stencil_control
|= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state
->stencil
[1].zpass_op
));
1178 db_stencil_control
|= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state
->stencil
[1].zfail_op
));
1183 if (state
->alpha
.enabled
) {
1184 dsa
->alpha_func
= state
->alpha
.func
;
1186 si_pm4_set_reg(pm4
, R_00B030_SPI_SHADER_USER_DATA_PS_0
+
1187 SI_SGPR_ALPHA_REF
* 4, fui(state
->alpha
.ref_value
));
1189 dsa
->alpha_func
= PIPE_FUNC_ALWAYS
;
1192 si_pm4_set_reg(pm4
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
1193 if (state
->stencil
[0].enabled
)
1194 si_pm4_set_reg(pm4
, R_02842C_DB_STENCIL_CONTROL
, db_stencil_control
);
1195 if (state
->depth
.bounds_test
) {
1196 si_pm4_set_reg(pm4
, R_028020_DB_DEPTH_BOUNDS_MIN
, fui(state
->depth
.bounds_min
));
1197 si_pm4_set_reg(pm4
, R_028024_DB_DEPTH_BOUNDS_MAX
, fui(state
->depth
.bounds_max
));
1200 dsa
->depth_enabled
= state
->depth
.enabled
;
1201 dsa
->depth_write_enabled
= state
->depth
.enabled
&&
1202 state
->depth
.writemask
;
1203 dsa
->stencil_enabled
= state
->stencil
[0].enabled
;
1204 dsa
->stencil_write_enabled
= state
->stencil
[0].enabled
&&
1205 (si_dsa_writes_stencil(&state
->stencil
[0]) ||
1206 si_dsa_writes_stencil(&state
->stencil
[1]));
1207 dsa
->db_can_write
= dsa
->depth_write_enabled
||
1208 dsa
->stencil_write_enabled
;
1210 bool zfunc_is_ordered
=
1211 state
->depth
.func
== PIPE_FUNC_NEVER
||
1212 state
->depth
.func
== PIPE_FUNC_LESS
||
1213 state
->depth
.func
== PIPE_FUNC_LEQUAL
||
1214 state
->depth
.func
== PIPE_FUNC_GREATER
||
1215 state
->depth
.func
== PIPE_FUNC_GEQUAL
;
1217 bool nozwrite_and_order_invariant_stencil
=
1218 !dsa
->db_can_write
||
1219 (!dsa
->depth_write_enabled
&&
1220 si_order_invariant_stencil_state(&state
->stencil
[0]) &&
1221 si_order_invariant_stencil_state(&state
->stencil
[1]));
1223 dsa
->order_invariance
[1].zs
=
1224 nozwrite_and_order_invariant_stencil
||
1225 (!dsa
->stencil_write_enabled
&& zfunc_is_ordered
);
1226 dsa
->order_invariance
[0].zs
= !dsa
->depth_write_enabled
|| zfunc_is_ordered
;
1228 dsa
->order_invariance
[1].pass_set
=
1229 nozwrite_and_order_invariant_stencil
||
1230 (!dsa
->stencil_write_enabled
&&
1231 (state
->depth
.func
== PIPE_FUNC_ALWAYS
||
1232 state
->depth
.func
== PIPE_FUNC_NEVER
));
1233 dsa
->order_invariance
[0].pass_set
=
1234 !dsa
->depth_write_enabled
||
1235 (state
->depth
.func
== PIPE_FUNC_ALWAYS
||
1236 state
->depth
.func
== PIPE_FUNC_NEVER
);
1238 dsa
->order_invariance
[1].pass_last
=
1239 sctx
->screen
->assume_no_z_fights
&&
1240 !dsa
->stencil_write_enabled
&&
1241 dsa
->depth_write_enabled
&& zfunc_is_ordered
;
1242 dsa
->order_invariance
[0].pass_last
=
1243 sctx
->screen
->assume_no_z_fights
&&
1244 dsa
->depth_write_enabled
&& zfunc_is_ordered
;
1249 static void si_bind_dsa_state(struct pipe_context
*ctx
, void *state
)
1251 struct si_context
*sctx
= (struct si_context
*)ctx
;
1252 struct si_state_dsa
*old_dsa
= sctx
->queued
.named
.dsa
;
1253 struct si_state_dsa
*dsa
= state
;
1258 si_pm4_bind_state(sctx
, dsa
, dsa
);
1260 if (memcmp(&dsa
->stencil_ref
, &sctx
->stencil_ref
.dsa_part
,
1261 sizeof(struct si_dsa_stencil_ref_part
)) != 0) {
1262 sctx
->stencil_ref
.dsa_part
= dsa
->stencil_ref
;
1263 si_mark_atom_dirty(sctx
, &sctx
->stencil_ref
.atom
);
1266 if (!old_dsa
|| old_dsa
->alpha_func
!= dsa
->alpha_func
)
1267 sctx
->do_update_shaders
= true;
1269 if (sctx
->screen
->dpbb_allowed
&&
1271 (old_dsa
->depth_enabled
!= dsa
->depth_enabled
||
1272 old_dsa
->stencil_enabled
!= dsa
->stencil_enabled
||
1273 old_dsa
->db_can_write
!= dsa
->db_can_write
)))
1274 si_mark_atom_dirty(sctx
, &sctx
->dpbb_state
);
1276 if (sctx
->screen
->has_out_of_order_rast
&&
1278 memcmp(old_dsa
->order_invariance
, dsa
->order_invariance
,
1279 sizeof(old_dsa
->order_invariance
))))
1280 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
1283 static void si_delete_dsa_state(struct pipe_context
*ctx
, void *state
)
1285 struct si_context
*sctx
= (struct si_context
*)ctx
;
1286 si_pm4_delete_state(sctx
, dsa
, (struct si_state_dsa
*)state
);
1289 static void *si_create_db_flush_dsa(struct si_context
*sctx
)
1291 struct pipe_depth_stencil_alpha_state dsa
= {};
1293 return sctx
->b
.b
.create_depth_stencil_alpha_state(&sctx
->b
.b
, &dsa
);
1296 /* DB RENDER STATE */
1298 static void si_set_active_query_state(struct pipe_context
*ctx
, boolean enable
)
1300 struct si_context
*sctx
= (struct si_context
*)ctx
;
1302 /* Pipeline stat & streamout queries. */
1304 sctx
->b
.flags
&= ~R600_CONTEXT_STOP_PIPELINE_STATS
;
1305 sctx
->b
.flags
|= R600_CONTEXT_START_PIPELINE_STATS
;
1307 sctx
->b
.flags
&= ~R600_CONTEXT_START_PIPELINE_STATS
;
1308 sctx
->b
.flags
|= R600_CONTEXT_STOP_PIPELINE_STATS
;
1311 /* Occlusion queries. */
1312 if (sctx
->occlusion_queries_disabled
!= !enable
) {
1313 sctx
->occlusion_queries_disabled
= !enable
;
1314 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
1318 static void si_set_occlusion_query_state(struct pipe_context
*ctx
,
1320 bool old_perfect_enable
)
1322 struct si_context
*sctx
= (struct si_context
*)ctx
;
1324 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
1326 bool perfect_enable
= sctx
->b
.num_perfect_occlusion_queries
!= 0;
1328 if (perfect_enable
!= old_perfect_enable
)
1329 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
1332 static void si_save_qbo_state(struct pipe_context
*ctx
, struct r600_qbo_state
*st
)
1334 struct si_context
*sctx
= (struct si_context
*)ctx
;
1336 st
->saved_compute
= sctx
->cs_shader_state
.program
;
1338 si_get_pipe_constant_buffer(sctx
, PIPE_SHADER_COMPUTE
, 0, &st
->saved_const0
);
1339 si_get_shader_buffers(sctx
, PIPE_SHADER_COMPUTE
, 0, 3, st
->saved_ssbo
);
1342 static void si_emit_db_render_state(struct si_context
*sctx
, struct r600_atom
*state
)
1344 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
1345 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
1346 unsigned db_shader_control
;
1348 radeon_set_context_reg_seq(cs
, R_028000_DB_RENDER_CONTROL
, 2);
1350 /* DB_RENDER_CONTROL */
1351 if (sctx
->dbcb_depth_copy_enabled
||
1352 sctx
->dbcb_stencil_copy_enabled
) {
1354 S_028000_DEPTH_COPY(sctx
->dbcb_depth_copy_enabled
) |
1355 S_028000_STENCIL_COPY(sctx
->dbcb_stencil_copy_enabled
) |
1356 S_028000_COPY_CENTROID(1) |
1357 S_028000_COPY_SAMPLE(sctx
->dbcb_copy_sample
));
1358 } else if (sctx
->db_flush_depth_inplace
|| sctx
->db_flush_stencil_inplace
) {
1360 S_028000_DEPTH_COMPRESS_DISABLE(sctx
->db_flush_depth_inplace
) |
1361 S_028000_STENCIL_COMPRESS_DISABLE(sctx
->db_flush_stencil_inplace
));
1364 S_028000_DEPTH_CLEAR_ENABLE(sctx
->db_depth_clear
) |
1365 S_028000_STENCIL_CLEAR_ENABLE(sctx
->db_stencil_clear
));
1368 /* DB_COUNT_CONTROL (occlusion queries) */
1369 if (sctx
->b
.num_occlusion_queries
> 0 &&
1370 !sctx
->occlusion_queries_disabled
) {
1371 bool perfect
= sctx
->b
.num_perfect_occlusion_queries
> 0;
1373 if (sctx
->b
.chip_class
>= CIK
) {
1375 S_028004_PERFECT_ZPASS_COUNTS(perfect
) |
1376 S_028004_SAMPLE_RATE(sctx
->framebuffer
.log_samples
) |
1377 S_028004_ZPASS_ENABLE(1) |
1378 S_028004_SLICE_EVEN_ENABLE(1) |
1379 S_028004_SLICE_ODD_ENABLE(1));
1382 S_028004_PERFECT_ZPASS_COUNTS(perfect
) |
1383 S_028004_SAMPLE_RATE(sctx
->framebuffer
.log_samples
));
1386 /* Disable occlusion queries. */
1387 if (sctx
->b
.chip_class
>= CIK
) {
1390 radeon_emit(cs
, S_028004_ZPASS_INCREMENT_DISABLE(1));
1394 /* DB_RENDER_OVERRIDE2 */
1395 radeon_set_context_reg(cs
, R_028010_DB_RENDER_OVERRIDE2
,
1396 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx
->db_depth_disable_expclear
) |
1397 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx
->db_stencil_disable_expclear
) |
1398 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx
->framebuffer
.nr_samples
>= 4));
1400 db_shader_control
= sctx
->ps_db_shader_control
;
1402 /* Bug workaround for smoothing (overrasterization) on SI. */
1403 if (sctx
->b
.chip_class
== SI
&& sctx
->smoothing_enabled
) {
1404 db_shader_control
&= C_02880C_Z_ORDER
;
1405 db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
);
1408 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1409 if (!rs
|| !rs
->multisample_enable
)
1410 db_shader_control
&= C_02880C_MASK_EXPORT_ENABLE
;
1412 if (sctx
->screen
->b
.has_rbplus
&&
1413 !sctx
->screen
->b
.rbplus_allowed
)
1414 db_shader_control
|= S_02880C_DUAL_QUAD_DISABLE(1);
1416 radeon_set_context_reg(cs
, R_02880C_DB_SHADER_CONTROL
,
1421 * format translation
1423 static uint32_t si_translate_colorformat(enum pipe_format format
)
1425 const struct util_format_description
*desc
= util_format_description(format
);
1427 return V_028C70_COLOR_INVALID
;
1429 #define HAS_SIZE(x,y,z,w) \
1430 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1431 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1433 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
1434 return V_028C70_COLOR_10_11_11
;
1436 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
1437 return V_028C70_COLOR_INVALID
;
1439 /* hw cannot support mixed formats (except depth/stencil, since
1440 * stencil is not written to). */
1441 if (desc
->is_mixed
&& desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
)
1442 return V_028C70_COLOR_INVALID
;
1444 switch (desc
->nr_channels
) {
1446 switch (desc
->channel
[0].size
) {
1448 return V_028C70_COLOR_8
;
1450 return V_028C70_COLOR_16
;
1452 return V_028C70_COLOR_32
;
1456 if (desc
->channel
[0].size
== desc
->channel
[1].size
) {
1457 switch (desc
->channel
[0].size
) {
1459 return V_028C70_COLOR_8_8
;
1461 return V_028C70_COLOR_16_16
;
1463 return V_028C70_COLOR_32_32
;
1465 } else if (HAS_SIZE(8,24,0,0)) {
1466 return V_028C70_COLOR_24_8
;
1467 } else if (HAS_SIZE(24,8,0,0)) {
1468 return V_028C70_COLOR_8_24
;
1472 if (HAS_SIZE(5,6,5,0)) {
1473 return V_028C70_COLOR_5_6_5
;
1474 } else if (HAS_SIZE(32,8,24,0)) {
1475 return V_028C70_COLOR_X24_8_32_FLOAT
;
1479 if (desc
->channel
[0].size
== desc
->channel
[1].size
&&
1480 desc
->channel
[0].size
== desc
->channel
[2].size
&&
1481 desc
->channel
[0].size
== desc
->channel
[3].size
) {
1482 switch (desc
->channel
[0].size
) {
1484 return V_028C70_COLOR_4_4_4_4
;
1486 return V_028C70_COLOR_8_8_8_8
;
1488 return V_028C70_COLOR_16_16_16_16
;
1490 return V_028C70_COLOR_32_32_32_32
;
1492 } else if (HAS_SIZE(5,5,5,1)) {
1493 return V_028C70_COLOR_1_5_5_5
;
1494 } else if (HAS_SIZE(10,10,10,2)) {
1495 return V_028C70_COLOR_2_10_10_10
;
1499 return V_028C70_COLOR_INVALID
;
1502 static uint32_t si_colorformat_endian_swap(uint32_t colorformat
)
1504 if (SI_BIG_ENDIAN
) {
1505 switch(colorformat
) {
1506 /* 8-bit buffers. */
1507 case V_028C70_COLOR_8
:
1508 return V_028C70_ENDIAN_NONE
;
1510 /* 16-bit buffers. */
1511 case V_028C70_COLOR_5_6_5
:
1512 case V_028C70_COLOR_1_5_5_5
:
1513 case V_028C70_COLOR_4_4_4_4
:
1514 case V_028C70_COLOR_16
:
1515 case V_028C70_COLOR_8_8
:
1516 return V_028C70_ENDIAN_8IN16
;
1518 /* 32-bit buffers. */
1519 case V_028C70_COLOR_8_8_8_8
:
1520 case V_028C70_COLOR_2_10_10_10
:
1521 case V_028C70_COLOR_8_24
:
1522 case V_028C70_COLOR_24_8
:
1523 case V_028C70_COLOR_16_16
:
1524 return V_028C70_ENDIAN_8IN32
;
1526 /* 64-bit buffers. */
1527 case V_028C70_COLOR_16_16_16_16
:
1528 return V_028C70_ENDIAN_8IN16
;
1530 case V_028C70_COLOR_32_32
:
1531 return V_028C70_ENDIAN_8IN32
;
1533 /* 128-bit buffers. */
1534 case V_028C70_COLOR_32_32_32_32
:
1535 return V_028C70_ENDIAN_8IN32
;
1537 return V_028C70_ENDIAN_NONE
; /* Unsupported. */
1540 return V_028C70_ENDIAN_NONE
;
1544 static uint32_t si_translate_dbformat(enum pipe_format format
)
1547 case PIPE_FORMAT_Z16_UNORM
:
1548 return V_028040_Z_16
;
1549 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1550 case PIPE_FORMAT_X8Z24_UNORM
:
1551 case PIPE_FORMAT_Z24X8_UNORM
:
1552 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1553 return V_028040_Z_24
; /* deprecated on SI */
1554 case PIPE_FORMAT_Z32_FLOAT
:
1555 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1556 return V_028040_Z_32_FLOAT
;
1558 return V_028040_Z_INVALID
;
1563 * Texture translation
1566 static uint32_t si_translate_texformat(struct pipe_screen
*screen
,
1567 enum pipe_format format
,
1568 const struct util_format_description
*desc
,
1571 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1572 bool enable_compressed_formats
= (sscreen
->b
.info
.drm_major
== 2 &&
1573 sscreen
->b
.info
.drm_minor
>= 31) ||
1574 sscreen
->b
.info
.drm_major
== 3;
1575 bool uniform
= true;
1578 /* Colorspace (return non-RGB formats directly). */
1579 switch (desc
->colorspace
) {
1580 /* Depth stencil formats */
1581 case UTIL_FORMAT_COLORSPACE_ZS
:
1583 case PIPE_FORMAT_Z16_UNORM
:
1584 return V_008F14_IMG_DATA_FORMAT_16
;
1585 case PIPE_FORMAT_X24S8_UINT
:
1586 case PIPE_FORMAT_S8X24_UINT
:
1588 * Implemented as an 8_8_8_8 data format to fix texture
1589 * gathers in stencil sampling. This affects at least
1590 * GL45-CTS.texture_cube_map_array.sampling on VI.
1592 return V_008F14_IMG_DATA_FORMAT_8_8_8_8
;
1593 case PIPE_FORMAT_Z24X8_UNORM
:
1594 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1595 return V_008F14_IMG_DATA_FORMAT_8_24
;
1596 case PIPE_FORMAT_X8Z24_UNORM
:
1597 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1598 return V_008F14_IMG_DATA_FORMAT_24_8
;
1599 case PIPE_FORMAT_S8_UINT
:
1600 return V_008F14_IMG_DATA_FORMAT_8
;
1601 case PIPE_FORMAT_Z32_FLOAT
:
1602 return V_008F14_IMG_DATA_FORMAT_32
;
1603 case PIPE_FORMAT_X32_S8X24_UINT
:
1604 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1605 return V_008F14_IMG_DATA_FORMAT_X24_8_32
;
1610 case UTIL_FORMAT_COLORSPACE_YUV
:
1611 goto out_unknown
; /* TODO */
1613 case UTIL_FORMAT_COLORSPACE_SRGB
:
1614 if (desc
->nr_channels
!= 4 && desc
->nr_channels
!= 1)
1622 if (desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
) {
1623 if (!enable_compressed_formats
)
1627 case PIPE_FORMAT_RGTC1_SNORM
:
1628 case PIPE_FORMAT_LATC1_SNORM
:
1629 case PIPE_FORMAT_RGTC1_UNORM
:
1630 case PIPE_FORMAT_LATC1_UNORM
:
1631 return V_008F14_IMG_DATA_FORMAT_BC4
;
1632 case PIPE_FORMAT_RGTC2_SNORM
:
1633 case PIPE_FORMAT_LATC2_SNORM
:
1634 case PIPE_FORMAT_RGTC2_UNORM
:
1635 case PIPE_FORMAT_LATC2_UNORM
:
1636 return V_008F14_IMG_DATA_FORMAT_BC5
;
1642 if (desc
->layout
== UTIL_FORMAT_LAYOUT_ETC
&&
1643 (sscreen
->b
.family
== CHIP_STONEY
||
1644 sscreen
->b
.chip_class
>= GFX9
)) {
1646 case PIPE_FORMAT_ETC1_RGB8
:
1647 case PIPE_FORMAT_ETC2_RGB8
:
1648 case PIPE_FORMAT_ETC2_SRGB8
:
1649 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB
;
1650 case PIPE_FORMAT_ETC2_RGB8A1
:
1651 case PIPE_FORMAT_ETC2_SRGB8A1
:
1652 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1
;
1653 case PIPE_FORMAT_ETC2_RGBA8
:
1654 case PIPE_FORMAT_ETC2_SRGBA8
:
1655 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA
;
1656 case PIPE_FORMAT_ETC2_R11_UNORM
:
1657 case PIPE_FORMAT_ETC2_R11_SNORM
:
1658 return V_008F14_IMG_DATA_FORMAT_ETC2_R
;
1659 case PIPE_FORMAT_ETC2_RG11_UNORM
:
1660 case PIPE_FORMAT_ETC2_RG11_SNORM
:
1661 return V_008F14_IMG_DATA_FORMAT_ETC2_RG
;
1667 if (desc
->layout
== UTIL_FORMAT_LAYOUT_BPTC
) {
1668 if (!enable_compressed_formats
)
1672 case PIPE_FORMAT_BPTC_RGBA_UNORM
:
1673 case PIPE_FORMAT_BPTC_SRGBA
:
1674 return V_008F14_IMG_DATA_FORMAT_BC7
;
1675 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
1676 case PIPE_FORMAT_BPTC_RGB_UFLOAT
:
1677 return V_008F14_IMG_DATA_FORMAT_BC6
;
1683 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
1685 case PIPE_FORMAT_R8G8_B8G8_UNORM
:
1686 case PIPE_FORMAT_G8R8_B8R8_UNORM
:
1687 return V_008F14_IMG_DATA_FORMAT_GB_GR
;
1688 case PIPE_FORMAT_G8R8_G8B8_UNORM
:
1689 case PIPE_FORMAT_R8G8_R8B8_UNORM
:
1690 return V_008F14_IMG_DATA_FORMAT_BG_RG
;
1696 if (desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
1697 if (!enable_compressed_formats
)
1700 if (!util_format_s3tc_enabled
) {
1705 case PIPE_FORMAT_DXT1_RGB
:
1706 case PIPE_FORMAT_DXT1_RGBA
:
1707 case PIPE_FORMAT_DXT1_SRGB
:
1708 case PIPE_FORMAT_DXT1_SRGBA
:
1709 return V_008F14_IMG_DATA_FORMAT_BC1
;
1710 case PIPE_FORMAT_DXT3_RGBA
:
1711 case PIPE_FORMAT_DXT3_SRGBA
:
1712 return V_008F14_IMG_DATA_FORMAT_BC2
;
1713 case PIPE_FORMAT_DXT5_RGBA
:
1714 case PIPE_FORMAT_DXT5_SRGBA
:
1715 return V_008F14_IMG_DATA_FORMAT_BC3
;
1721 if (format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
1722 return V_008F14_IMG_DATA_FORMAT_5_9_9_9
;
1723 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
1724 return V_008F14_IMG_DATA_FORMAT_10_11_11
;
1727 /* R8G8Bx_SNORM - TODO CxV8U8 */
1729 /* hw cannot support mixed formats (except depth/stencil, since only
1731 if (desc
->is_mixed
&& desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
)
1734 /* See whether the components are of the same size. */
1735 for (i
= 1; i
< desc
->nr_channels
; i
++) {
1736 uniform
= uniform
&& desc
->channel
[0].size
== desc
->channel
[i
].size
;
1739 /* Non-uniform formats. */
1741 switch(desc
->nr_channels
) {
1743 if (desc
->channel
[0].size
== 5 &&
1744 desc
->channel
[1].size
== 6 &&
1745 desc
->channel
[2].size
== 5) {
1746 return V_008F14_IMG_DATA_FORMAT_5_6_5
;
1750 if (desc
->channel
[0].size
== 5 &&
1751 desc
->channel
[1].size
== 5 &&
1752 desc
->channel
[2].size
== 5 &&
1753 desc
->channel
[3].size
== 1) {
1754 return V_008F14_IMG_DATA_FORMAT_1_5_5_5
;
1756 if (desc
->channel
[0].size
== 10 &&
1757 desc
->channel
[1].size
== 10 &&
1758 desc
->channel
[2].size
== 10 &&
1759 desc
->channel
[3].size
== 2) {
1760 return V_008F14_IMG_DATA_FORMAT_2_10_10_10
;
1767 if (first_non_void
< 0 || first_non_void
> 3)
1770 /* uniform formats */
1771 switch (desc
->channel
[first_non_void
].size
) {
1773 switch (desc
->nr_channels
) {
1774 #if 0 /* Not supported for render targets */
1776 return V_008F14_IMG_DATA_FORMAT_4_4
;
1779 return V_008F14_IMG_DATA_FORMAT_4_4_4_4
;
1783 switch (desc
->nr_channels
) {
1785 return V_008F14_IMG_DATA_FORMAT_8
;
1787 return V_008F14_IMG_DATA_FORMAT_8_8
;
1789 return V_008F14_IMG_DATA_FORMAT_8_8_8_8
;
1793 switch (desc
->nr_channels
) {
1795 return V_008F14_IMG_DATA_FORMAT_16
;
1797 return V_008F14_IMG_DATA_FORMAT_16_16
;
1799 return V_008F14_IMG_DATA_FORMAT_16_16_16_16
;
1803 switch (desc
->nr_channels
) {
1805 return V_008F14_IMG_DATA_FORMAT_32
;
1807 return V_008F14_IMG_DATA_FORMAT_32_32
;
1808 #if 0 /* Not supported for render targets */
1810 return V_008F14_IMG_DATA_FORMAT_32_32_32
;
1813 return V_008F14_IMG_DATA_FORMAT_32_32_32_32
;
1818 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1822 static unsigned si_tex_wrap(unsigned wrap
)
1826 case PIPE_TEX_WRAP_REPEAT
:
1827 return V_008F30_SQ_TEX_WRAP
;
1828 case PIPE_TEX_WRAP_CLAMP
:
1829 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER
;
1830 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
1831 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL
;
1832 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
1833 return V_008F30_SQ_TEX_CLAMP_BORDER
;
1834 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
1835 return V_008F30_SQ_TEX_MIRROR
;
1836 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
1837 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
1838 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
1839 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
1840 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
1841 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER
;
1845 static unsigned si_tex_mipfilter(unsigned filter
)
1848 case PIPE_TEX_MIPFILTER_NEAREST
:
1849 return V_008F38_SQ_TEX_Z_FILTER_POINT
;
1850 case PIPE_TEX_MIPFILTER_LINEAR
:
1851 return V_008F38_SQ_TEX_Z_FILTER_LINEAR
;
1853 case PIPE_TEX_MIPFILTER_NONE
:
1854 return V_008F38_SQ_TEX_Z_FILTER_NONE
;
1858 static unsigned si_tex_compare(unsigned compare
)
1862 case PIPE_FUNC_NEVER
:
1863 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
1864 case PIPE_FUNC_LESS
:
1865 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS
;
1866 case PIPE_FUNC_EQUAL
:
1867 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL
;
1868 case PIPE_FUNC_LEQUAL
:
1869 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
1870 case PIPE_FUNC_GREATER
:
1871 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER
;
1872 case PIPE_FUNC_NOTEQUAL
:
1873 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
1874 case PIPE_FUNC_GEQUAL
:
1875 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
1876 case PIPE_FUNC_ALWAYS
:
1877 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
1881 static unsigned si_tex_dim(struct si_screen
*sscreen
, struct r600_texture
*rtex
,
1882 unsigned view_target
, unsigned nr_samples
)
1884 unsigned res_target
= rtex
->resource
.b
.b
.target
;
1886 if (view_target
== PIPE_TEXTURE_CUBE
||
1887 view_target
== PIPE_TEXTURE_CUBE_ARRAY
)
1888 res_target
= view_target
;
1889 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1890 else if (res_target
== PIPE_TEXTURE_CUBE
||
1891 res_target
== PIPE_TEXTURE_CUBE_ARRAY
)
1892 res_target
= PIPE_TEXTURE_2D_ARRAY
;
1894 /* GFX9 allocates 1D textures as 2D. */
1895 if ((res_target
== PIPE_TEXTURE_1D
||
1896 res_target
== PIPE_TEXTURE_1D_ARRAY
) &&
1897 sscreen
->b
.chip_class
>= GFX9
&&
1898 rtex
->surface
.u
.gfx9
.resource_type
== RADEON_RESOURCE_2D
) {
1899 if (res_target
== PIPE_TEXTURE_1D
)
1900 res_target
= PIPE_TEXTURE_2D
;
1902 res_target
= PIPE_TEXTURE_2D_ARRAY
;
1905 switch (res_target
) {
1907 case PIPE_TEXTURE_1D
:
1908 return V_008F1C_SQ_RSRC_IMG_1D
;
1909 case PIPE_TEXTURE_1D_ARRAY
:
1910 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY
;
1911 case PIPE_TEXTURE_2D
:
1912 case PIPE_TEXTURE_RECT
:
1913 return nr_samples
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA
:
1914 V_008F1C_SQ_RSRC_IMG_2D
;
1915 case PIPE_TEXTURE_2D_ARRAY
:
1916 return nr_samples
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
:
1917 V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
1918 case PIPE_TEXTURE_3D
:
1919 return V_008F1C_SQ_RSRC_IMG_3D
;
1920 case PIPE_TEXTURE_CUBE
:
1921 case PIPE_TEXTURE_CUBE_ARRAY
:
1922 return V_008F1C_SQ_RSRC_IMG_CUBE
;
1927 * Format support testing
1930 static bool si_is_sampler_format_supported(struct pipe_screen
*screen
, enum pipe_format format
)
1932 const struct util_format_description
*desc
= util_format_description(format
);
1936 return si_translate_texformat(screen
, format
, desc
,
1937 util_format_get_first_non_void_channel(format
)) != ~0U;
1940 static uint32_t si_translate_buffer_dataformat(struct pipe_screen
*screen
,
1941 const struct util_format_description
*desc
,
1946 if (desc
->format
== PIPE_FORMAT_R11G11B10_FLOAT
)
1947 return V_008F0C_BUF_DATA_FORMAT_10_11_11
;
1949 assert(first_non_void
>= 0);
1951 if (desc
->nr_channels
== 4 &&
1952 desc
->channel
[0].size
== 10 &&
1953 desc
->channel
[1].size
== 10 &&
1954 desc
->channel
[2].size
== 10 &&
1955 desc
->channel
[3].size
== 2)
1956 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10
;
1958 /* See whether the components are of the same size. */
1959 for (i
= 0; i
< desc
->nr_channels
; i
++) {
1960 if (desc
->channel
[first_non_void
].size
!= desc
->channel
[i
].size
)
1961 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
1964 switch (desc
->channel
[first_non_void
].size
) {
1966 switch (desc
->nr_channels
) {
1968 case 3: /* 3 loads */
1969 return V_008F0C_BUF_DATA_FORMAT_8
;
1971 return V_008F0C_BUF_DATA_FORMAT_8_8
;
1973 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8
;
1977 switch (desc
->nr_channels
) {
1979 case 3: /* 3 loads */
1980 return V_008F0C_BUF_DATA_FORMAT_16
;
1982 return V_008F0C_BUF_DATA_FORMAT_16_16
;
1984 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16
;
1988 switch (desc
->nr_channels
) {
1990 return V_008F0C_BUF_DATA_FORMAT_32
;
1992 return V_008F0C_BUF_DATA_FORMAT_32_32
;
1994 return V_008F0C_BUF_DATA_FORMAT_32_32_32
;
1996 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
2000 /* Legacy double formats. */
2001 switch (desc
->nr_channels
) {
2002 case 1: /* 1 load */
2003 return V_008F0C_BUF_DATA_FORMAT_32_32
;
2004 case 2: /* 1 load */
2005 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
2006 case 3: /* 3 loads */
2007 return V_008F0C_BUF_DATA_FORMAT_32_32
;
2008 case 4: /* 2 loads */
2009 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
2014 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
2017 static uint32_t si_translate_buffer_numformat(struct pipe_screen
*screen
,
2018 const struct util_format_description
*desc
,
2021 if (desc
->format
== PIPE_FORMAT_R11G11B10_FLOAT
)
2022 return V_008F0C_BUF_NUM_FORMAT_FLOAT
;
2024 assert(first_non_void
>= 0);
2026 switch (desc
->channel
[first_non_void
].type
) {
2027 case UTIL_FORMAT_TYPE_SIGNED
:
2028 case UTIL_FORMAT_TYPE_FIXED
:
2029 if (desc
->channel
[first_non_void
].size
>= 32 ||
2030 desc
->channel
[first_non_void
].pure_integer
)
2031 return V_008F0C_BUF_NUM_FORMAT_SINT
;
2032 else if (desc
->channel
[first_non_void
].normalized
)
2033 return V_008F0C_BUF_NUM_FORMAT_SNORM
;
2035 return V_008F0C_BUF_NUM_FORMAT_SSCALED
;
2037 case UTIL_FORMAT_TYPE_UNSIGNED
:
2038 if (desc
->channel
[first_non_void
].size
>= 32 ||
2039 desc
->channel
[first_non_void
].pure_integer
)
2040 return V_008F0C_BUF_NUM_FORMAT_UINT
;
2041 else if (desc
->channel
[first_non_void
].normalized
)
2042 return V_008F0C_BUF_NUM_FORMAT_UNORM
;
2044 return V_008F0C_BUF_NUM_FORMAT_USCALED
;
2046 case UTIL_FORMAT_TYPE_FLOAT
:
2048 return V_008F0C_BUF_NUM_FORMAT_FLOAT
;
2052 static unsigned si_is_vertex_format_supported(struct pipe_screen
*screen
,
2053 enum pipe_format format
,
2056 const struct util_format_description
*desc
;
2058 unsigned data_format
;
2060 assert((usage
& ~(PIPE_BIND_SHADER_IMAGE
|
2061 PIPE_BIND_SAMPLER_VIEW
|
2062 PIPE_BIND_VERTEX_BUFFER
)) == 0);
2064 desc
= util_format_description(format
);
2068 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
2069 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
2070 * for read-only access (with caveats surrounding bounds checks), but
2071 * obviously fails for write access which we have to implement for
2072 * shader images. Luckily, OpenGL doesn't expect this to be supported
2073 * anyway, and so the only impact is on PBO uploads / downloads, which
2074 * shouldn't be expected to be fast for GL_RGB anyway.
2076 if (desc
->block
.bits
== 3 * 8 ||
2077 desc
->block
.bits
== 3 * 16) {
2078 if (usage
& (PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SAMPLER_VIEW
)) {
2079 usage
&= ~(PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SAMPLER_VIEW
);
2085 first_non_void
= util_format_get_first_non_void_channel(format
);
2086 data_format
= si_translate_buffer_dataformat(screen
, desc
, first_non_void
);
2087 if (data_format
== V_008F0C_BUF_DATA_FORMAT_INVALID
)
2093 static bool si_is_colorbuffer_format_supported(enum pipe_format format
)
2095 return si_translate_colorformat(format
) != V_028C70_COLOR_INVALID
&&
2096 r600_translate_colorswap(format
, false) != ~0U;
2099 static bool si_is_zs_format_supported(enum pipe_format format
)
2101 return si_translate_dbformat(format
) != V_028040_Z_INVALID
;
2104 static boolean
si_is_format_supported(struct pipe_screen
*screen
,
2105 enum pipe_format format
,
2106 enum pipe_texture_target target
,
2107 unsigned sample_count
,
2110 unsigned retval
= 0;
2112 if (target
>= PIPE_MAX_TEXTURE_TYPES
) {
2113 R600_ERR("r600: unsupported texture type %d\n", target
);
2117 if (!util_format_is_supported(format
, usage
))
2120 if (sample_count
> 1) {
2121 if (!screen
->get_param(screen
, PIPE_CAP_TEXTURE_MULTISAMPLE
))
2124 if (usage
& PIPE_BIND_SHADER_IMAGE
)
2127 switch (sample_count
) {
2133 if (format
== PIPE_FORMAT_NONE
)
2142 if (usage
& (PIPE_BIND_SAMPLER_VIEW
|
2143 PIPE_BIND_SHADER_IMAGE
)) {
2144 if (target
== PIPE_BUFFER
) {
2145 retval
|= si_is_vertex_format_supported(
2146 screen
, format
, usage
& (PIPE_BIND_SAMPLER_VIEW
|
2147 PIPE_BIND_SHADER_IMAGE
));
2149 if (si_is_sampler_format_supported(screen
, format
))
2150 retval
|= usage
& (PIPE_BIND_SAMPLER_VIEW
|
2151 PIPE_BIND_SHADER_IMAGE
);
2155 if ((usage
& (PIPE_BIND_RENDER_TARGET
|
2156 PIPE_BIND_DISPLAY_TARGET
|
2159 PIPE_BIND_BLENDABLE
)) &&
2160 si_is_colorbuffer_format_supported(format
)) {
2162 (PIPE_BIND_RENDER_TARGET
|
2163 PIPE_BIND_DISPLAY_TARGET
|
2166 if (!util_format_is_pure_integer(format
) &&
2167 !util_format_is_depth_or_stencil(format
))
2168 retval
|= usage
& PIPE_BIND_BLENDABLE
;
2171 if ((usage
& PIPE_BIND_DEPTH_STENCIL
) &&
2172 si_is_zs_format_supported(format
)) {
2173 retval
|= PIPE_BIND_DEPTH_STENCIL
;
2176 if (usage
& PIPE_BIND_VERTEX_BUFFER
) {
2177 retval
|= si_is_vertex_format_supported(screen
, format
,
2178 PIPE_BIND_VERTEX_BUFFER
);
2181 if ((usage
& PIPE_BIND_LINEAR
) &&
2182 !util_format_is_compressed(format
) &&
2183 !(usage
& PIPE_BIND_DEPTH_STENCIL
))
2184 retval
|= PIPE_BIND_LINEAR
;
2186 return retval
== usage
;
2190 * framebuffer handling
2193 static void si_choose_spi_color_formats(struct r600_surface
*surf
,
2194 unsigned format
, unsigned swap
,
2195 unsigned ntype
, bool is_depth
)
2197 /* Alpha is needed for alpha-to-coverage.
2198 * Blending may be with or without alpha.
2200 unsigned normal
= 0; /* most optimal, may not support blending or export alpha */
2201 unsigned alpha
= 0; /* exports alpha, but may not support blending */
2202 unsigned blend
= 0; /* supports blending, but may not export alpha */
2203 unsigned blend_alpha
= 0; /* least optimal, supports blending and exports alpha */
2205 /* Choose the SPI color formats. These are required values for RB+.
2206 * Other chips have multiple choices, though they are not necessarily better.
2209 case V_028C70_COLOR_5_6_5
:
2210 case V_028C70_COLOR_1_5_5_5
:
2211 case V_028C70_COLOR_5_5_5_1
:
2212 case V_028C70_COLOR_4_4_4_4
:
2213 case V_028C70_COLOR_10_11_11
:
2214 case V_028C70_COLOR_11_11_10
:
2215 case V_028C70_COLOR_8
:
2216 case V_028C70_COLOR_8_8
:
2217 case V_028C70_COLOR_8_8_8_8
:
2218 case V_028C70_COLOR_10_10_10_2
:
2219 case V_028C70_COLOR_2_10_10_10
:
2220 if (ntype
== V_028C70_NUMBER_UINT
)
2221 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
2222 else if (ntype
== V_028C70_NUMBER_SINT
)
2223 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
2225 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
2228 case V_028C70_COLOR_16
:
2229 case V_028C70_COLOR_16_16
:
2230 case V_028C70_COLOR_16_16_16_16
:
2231 if (ntype
== V_028C70_NUMBER_UNORM
||
2232 ntype
== V_028C70_NUMBER_SNORM
) {
2233 /* UNORM16 and SNORM16 don't support blending */
2234 if (ntype
== V_028C70_NUMBER_UNORM
)
2235 normal
= alpha
= V_028714_SPI_SHADER_UNORM16_ABGR
;
2237 normal
= alpha
= V_028714_SPI_SHADER_SNORM16_ABGR
;
2239 /* Use 32 bits per channel for blending. */
2240 if (format
== V_028C70_COLOR_16
) {
2241 if (swap
== V_028C70_SWAP_STD
) { /* R */
2242 blend
= V_028714_SPI_SHADER_32_R
;
2243 blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2244 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
2245 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2248 } else if (format
== V_028C70_COLOR_16_16
) {
2249 if (swap
== V_028C70_SWAP_STD
) { /* RG */
2250 blend
= V_028714_SPI_SHADER_32_GR
;
2251 blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2252 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
2253 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2256 } else /* 16_16_16_16 */
2257 blend
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2258 } else if (ntype
== V_028C70_NUMBER_UINT
)
2259 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
2260 else if (ntype
== V_028C70_NUMBER_SINT
)
2261 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
2262 else if (ntype
== V_028C70_NUMBER_FLOAT
)
2263 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
2268 case V_028C70_COLOR_32
:
2269 if (swap
== V_028C70_SWAP_STD
) { /* R */
2270 blend
= normal
= V_028714_SPI_SHADER_32_R
;
2271 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2272 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
2273 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
2278 case V_028C70_COLOR_32_32
:
2279 if (swap
== V_028C70_SWAP_STD
) { /* RG */
2280 blend
= normal
= V_028714_SPI_SHADER_32_GR
;
2281 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2282 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
2283 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
2288 case V_028C70_COLOR_32_32_32_32
:
2289 case V_028C70_COLOR_8_24
:
2290 case V_028C70_COLOR_24_8
:
2291 case V_028C70_COLOR_X24_8_32_FLOAT
:
2292 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
2300 /* The DB->CB copy needs 32_ABGR. */
2302 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
2304 surf
->spi_shader_col_format
= normal
;
2305 surf
->spi_shader_col_format_alpha
= alpha
;
2306 surf
->spi_shader_col_format_blend
= blend
;
2307 surf
->spi_shader_col_format_blend_alpha
= blend_alpha
;
2310 static void si_initialize_color_surface(struct si_context
*sctx
,
2311 struct r600_surface
*surf
)
2313 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->base
.texture
;
2314 unsigned color_info
, color_attrib
, color_view
;
2315 unsigned format
, swap
, ntype
, endian
;
2316 const struct util_format_description
*desc
;
2318 unsigned blend_clamp
= 0, blend_bypass
= 0;
2320 color_view
= S_028C6C_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
2321 S_028C6C_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
2323 desc
= util_format_description(surf
->base
.format
);
2324 for (firstchan
= 0; firstchan
< 4; firstchan
++) {
2325 if (desc
->channel
[firstchan
].type
!= UTIL_FORMAT_TYPE_VOID
) {
2329 if (firstchan
== 4 || desc
->channel
[firstchan
].type
== UTIL_FORMAT_TYPE_FLOAT
) {
2330 ntype
= V_028C70_NUMBER_FLOAT
;
2332 ntype
= V_028C70_NUMBER_UNORM
;
2333 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
2334 ntype
= V_028C70_NUMBER_SRGB
;
2335 else if (desc
->channel
[firstchan
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2336 if (desc
->channel
[firstchan
].pure_integer
) {
2337 ntype
= V_028C70_NUMBER_SINT
;
2339 assert(desc
->channel
[firstchan
].normalized
);
2340 ntype
= V_028C70_NUMBER_SNORM
;
2342 } else if (desc
->channel
[firstchan
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
2343 if (desc
->channel
[firstchan
].pure_integer
) {
2344 ntype
= V_028C70_NUMBER_UINT
;
2346 assert(desc
->channel
[firstchan
].normalized
);
2347 ntype
= V_028C70_NUMBER_UNORM
;
2352 format
= si_translate_colorformat(surf
->base
.format
);
2353 if (format
== V_028C70_COLOR_INVALID
) {
2354 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf
->base
.format
);
2356 assert(format
!= V_028C70_COLOR_INVALID
);
2357 swap
= r600_translate_colorswap(surf
->base
.format
, false);
2358 endian
= si_colorformat_endian_swap(format
);
2360 /* blend clamp should be set for all NORM/SRGB types */
2361 if (ntype
== V_028C70_NUMBER_UNORM
||
2362 ntype
== V_028C70_NUMBER_SNORM
||
2363 ntype
== V_028C70_NUMBER_SRGB
)
2366 /* set blend bypass according to docs if SINT/UINT or
2367 8/24 COLOR variants */
2368 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
2369 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
2370 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
2375 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
) {
2376 if (format
== V_028C70_COLOR_8
||
2377 format
== V_028C70_COLOR_8_8
||
2378 format
== V_028C70_COLOR_8_8_8_8
)
2379 surf
->color_is_int8
= true;
2380 else if (format
== V_028C70_COLOR_10_10_10_2
||
2381 format
== V_028C70_COLOR_2_10_10_10
)
2382 surf
->color_is_int10
= true;
2385 color_info
= S_028C70_FORMAT(format
) |
2386 S_028C70_COMP_SWAP(swap
) |
2387 S_028C70_BLEND_CLAMP(blend_clamp
) |
2388 S_028C70_BLEND_BYPASS(blend_bypass
) |
2389 S_028C70_SIMPLE_FLOAT(1) |
2390 S_028C70_ROUND_MODE(ntype
!= V_028C70_NUMBER_UNORM
&&
2391 ntype
!= V_028C70_NUMBER_SNORM
&&
2392 ntype
!= V_028C70_NUMBER_SRGB
&&
2393 format
!= V_028C70_COLOR_8_24
&&
2394 format
!= V_028C70_COLOR_24_8
) |
2395 S_028C70_NUMBER_TYPE(ntype
) |
2396 S_028C70_ENDIAN(endian
);
2398 /* Intensity is implemented as Red, so treat it that way. */
2399 color_attrib
= S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] == PIPE_SWIZZLE_1
||
2400 util_format_is_intensity(surf
->base
.format
));
2402 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
2403 unsigned log_samples
= util_logbase2(rtex
->resource
.b
.b
.nr_samples
);
2405 color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
2406 S_028C74_NUM_FRAGMENTS(log_samples
);
2408 if (rtex
->fmask
.size
) {
2409 color_info
|= S_028C70_COMPRESSION(1);
2410 unsigned fmask_bankh
= util_logbase2(rtex
->fmask
.bank_height
);
2412 if (sctx
->b
.chip_class
== SI
) {
2413 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2414 color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh
);
2419 surf
->cb_color_view
= color_view
;
2420 surf
->cb_color_info
= color_info
;
2421 surf
->cb_color_attrib
= color_attrib
;
2423 if (sctx
->b
.chip_class
>= VI
) {
2424 unsigned max_uncompressed_block_size
= 2;
2426 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
2427 if (rtex
->surface
.bpe
== 1)
2428 max_uncompressed_block_size
= 0;
2429 else if (rtex
->surface
.bpe
== 2)
2430 max_uncompressed_block_size
= 1;
2433 surf
->cb_dcc_control
= S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size
) |
2434 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2437 /* This must be set for fast clear to work without FMASK. */
2438 if (!rtex
->fmask
.size
&& sctx
->b
.chip_class
== SI
) {
2439 unsigned bankh
= util_logbase2(rtex
->surface
.u
.legacy
.bankh
);
2440 surf
->cb_color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(bankh
);
2443 if (sctx
->b
.chip_class
>= GFX9
) {
2444 unsigned mip0_depth
= util_max_layer(&rtex
->resource
.b
.b
, 0);
2446 surf
->cb_color_view
|= S_028C6C_MIP_LEVEL(surf
->base
.u
.tex
.level
);
2447 surf
->cb_color_attrib
|= S_028C74_MIP0_DEPTH(mip0_depth
) |
2448 S_028C74_RESOURCE_TYPE(rtex
->surface
.u
.gfx9
.resource_type
);
2449 surf
->cb_color_attrib2
= S_028C68_MIP0_WIDTH(surf
->width0
- 1) |
2450 S_028C68_MIP0_HEIGHT(surf
->height0
- 1) |
2451 S_028C68_MAX_MIP(rtex
->resource
.b
.b
.last_level
);
2454 /* Determine pixel shader export format */
2455 si_choose_spi_color_formats(surf
, format
, swap
, ntype
, rtex
->is_depth
);
2457 surf
->color_initialized
= true;
2460 static void si_init_depth_surface(struct si_context
*sctx
,
2461 struct r600_surface
*surf
)
2463 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->base
.texture
;
2464 unsigned level
= surf
->base
.u
.tex
.level
;
2465 unsigned format
, stencil_format
;
2466 uint32_t z_info
, s_info
;
2468 format
= si_translate_dbformat(rtex
->db_render_format
);
2469 stencil_format
= rtex
->surface
.has_stencil
?
2470 V_028044_STENCIL_8
: V_028044_STENCIL_INVALID
;
2472 assert(format
!= V_028040_Z_INVALID
);
2473 if (format
== V_028040_Z_INVALID
)
2474 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex
->resource
.b
.b
.format
);
2476 surf
->db_depth_view
= S_028008_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
2477 S_028008_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
2478 surf
->db_htile_data_base
= 0;
2479 surf
->db_htile_surface
= 0;
2481 if (sctx
->b
.chip_class
>= GFX9
) {
2482 assert(rtex
->surface
.u
.gfx9
.surf_offset
== 0);
2483 surf
->db_depth_base
= rtex
->resource
.gpu_address
>> 8;
2484 surf
->db_stencil_base
= (rtex
->resource
.gpu_address
+
2485 rtex
->surface
.u
.gfx9
.stencil_offset
) >> 8;
2486 z_info
= S_028038_FORMAT(format
) |
2487 S_028038_NUM_SAMPLES(util_logbase2(rtex
->resource
.b
.b
.nr_samples
)) |
2488 S_028038_SW_MODE(rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
2489 S_028038_MAXMIP(rtex
->resource
.b
.b
.last_level
);
2490 s_info
= S_02803C_FORMAT(stencil_format
) |
2491 S_02803C_SW_MODE(rtex
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
2492 surf
->db_z_info2
= S_028068_EPITCH(rtex
->surface
.u
.gfx9
.surf
.epitch
);
2493 surf
->db_stencil_info2
= S_02806C_EPITCH(rtex
->surface
.u
.gfx9
.stencil
.epitch
);
2494 surf
->db_depth_view
|= S_028008_MIPID(level
);
2495 surf
->db_depth_size
= S_02801C_X_MAX(rtex
->resource
.b
.b
.width0
- 1) |
2496 S_02801C_Y_MAX(rtex
->resource
.b
.b
.height0
- 1);
2498 if (r600_htile_enabled(rtex
, level
)) {
2499 z_info
|= S_028038_TILE_SURFACE_ENABLE(1) |
2500 S_028038_ALLOW_EXPCLEAR(1);
2502 if (rtex
->tc_compatible_htile
) {
2503 unsigned max_zplanes
= 4;
2505 if (rtex
->db_render_format
== PIPE_FORMAT_Z16_UNORM
&&
2506 rtex
->resource
.b
.b
.nr_samples
> 1)
2509 z_info
|= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes
+ 1) |
2510 S_028038_ITERATE_FLUSH(1);
2511 s_info
|= S_02803C_ITERATE_FLUSH(1);
2514 if (rtex
->surface
.has_stencil
) {
2515 /* Stencil buffer workaround ported from the SI-CI-VI code.
2516 * See that for explanation.
2518 s_info
|= S_02803C_ALLOW_EXPCLEAR(rtex
->resource
.b
.b
.nr_samples
<= 1);
2520 /* Use all HTILE for depth if there's no stencil. */
2521 s_info
|= S_02803C_TILE_STENCIL_DISABLE(1);
2524 surf
->db_htile_data_base
= (rtex
->resource
.gpu_address
+
2525 rtex
->htile_offset
) >> 8;
2526 surf
->db_htile_surface
= S_028ABC_FULL_CACHE(1) |
2527 S_028ABC_PIPE_ALIGNED(rtex
->surface
.u
.gfx9
.htile
.pipe_aligned
) |
2528 S_028ABC_RB_ALIGNED(rtex
->surface
.u
.gfx9
.htile
.rb_aligned
);
2532 struct legacy_surf_level
*levelinfo
= &rtex
->surface
.u
.legacy
.level
[level
];
2534 assert(levelinfo
->nblk_x
% 8 == 0 && levelinfo
->nblk_y
% 8 == 0);
2536 surf
->db_depth_base
= (rtex
->resource
.gpu_address
+
2537 rtex
->surface
.u
.legacy
.level
[level
].offset
) >> 8;
2538 surf
->db_stencil_base
= (rtex
->resource
.gpu_address
+
2539 rtex
->surface
.u
.legacy
.stencil_level
[level
].offset
) >> 8;
2541 z_info
= S_028040_FORMAT(format
) |
2542 S_028040_NUM_SAMPLES(util_logbase2(rtex
->resource
.b
.b
.nr_samples
));
2543 s_info
= S_028044_FORMAT(stencil_format
);
2544 surf
->db_depth_info
= S_02803C_ADDR5_SWIZZLE_MASK(!rtex
->tc_compatible_htile
);
2546 if (sctx
->b
.chip_class
>= CIK
) {
2547 struct radeon_info
*info
= &sctx
->screen
->b
.info
;
2548 unsigned index
= rtex
->surface
.u
.legacy
.tiling_index
[level
];
2549 unsigned stencil_index
= rtex
->surface
.u
.legacy
.stencil_tiling_index
[level
];
2550 unsigned macro_index
= rtex
->surface
.u
.legacy
.macro_tile_index
;
2551 unsigned tile_mode
= info
->si_tile_mode_array
[index
];
2552 unsigned stencil_tile_mode
= info
->si_tile_mode_array
[stencil_index
];
2553 unsigned macro_mode
= info
->cik_macrotile_mode_array
[macro_index
];
2555 surf
->db_depth_info
|=
2556 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode
)) |
2557 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode
)) |
2558 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode
)) |
2559 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode
)) |
2560 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode
)) |
2561 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode
));
2562 z_info
|= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode
));
2563 s_info
|= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode
));
2565 unsigned tile_mode_index
= si_tile_mode_index(rtex
, level
, false);
2566 z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
2567 tile_mode_index
= si_tile_mode_index(rtex
, level
, true);
2568 s_info
|= S_028044_TILE_MODE_INDEX(tile_mode_index
);
2571 surf
->db_depth_size
= S_028058_PITCH_TILE_MAX((levelinfo
->nblk_x
/ 8) - 1) |
2572 S_028058_HEIGHT_TILE_MAX((levelinfo
->nblk_y
/ 8) - 1);
2573 surf
->db_depth_slice
= S_02805C_SLICE_TILE_MAX((levelinfo
->nblk_x
*
2574 levelinfo
->nblk_y
) / 64 - 1);
2576 if (r600_htile_enabled(rtex
, level
)) {
2577 z_info
|= S_028040_TILE_SURFACE_ENABLE(1) |
2578 S_028040_ALLOW_EXPCLEAR(1);
2580 if (rtex
->surface
.has_stencil
) {
2581 /* Workaround: For a not yet understood reason, the
2582 * combination of MSAA, fast stencil clear and stencil
2583 * decompress messes with subsequent stencil buffer
2584 * uses. Problem was reproduced on Verde, Bonaire,
2585 * Tonga, and Carrizo.
2587 * Disabling EXPCLEAR works around the problem.
2589 * Check piglit's arb_texture_multisample-stencil-clear
2590 * test if you want to try changing this.
2592 if (rtex
->resource
.b
.b
.nr_samples
<= 1)
2593 s_info
|= S_028044_ALLOW_EXPCLEAR(1);
2594 } else if (!rtex
->tc_compatible_htile
) {
2595 /* Use all of the htile_buffer for depth if there's no stencil.
2596 * This must not be set when TC-compatible HTILE is enabled
2599 s_info
|= S_028044_TILE_STENCIL_DISABLE(1);
2602 surf
->db_htile_data_base
= (rtex
->resource
.gpu_address
+
2603 rtex
->htile_offset
) >> 8;
2604 surf
->db_htile_surface
= S_028ABC_FULL_CACHE(1);
2606 if (rtex
->tc_compatible_htile
) {
2607 surf
->db_htile_surface
|= S_028ABC_TC_COMPATIBLE(1);
2609 if (rtex
->resource
.b
.b
.nr_samples
<= 1)
2610 z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2611 else if (rtex
->resource
.b
.b
.nr_samples
<= 4)
2612 z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2614 z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2619 surf
->db_z_info
= z_info
;
2620 surf
->db_stencil_info
= s_info
;
2622 surf
->depth_initialized
= true;
2625 void si_update_fb_dirtiness_after_rendering(struct si_context
*sctx
)
2627 if (sctx
->decompression_enabled
)
2630 if (sctx
->framebuffer
.state
.zsbuf
) {
2631 struct pipe_surface
*surf
= sctx
->framebuffer
.state
.zsbuf
;
2632 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->texture
;
2634 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2636 if (rtex
->surface
.has_stencil
)
2637 rtex
->stencil_dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2639 if (sctx
->framebuffer
.compressed_cb_mask
) {
2640 struct pipe_surface
*surf
;
2641 struct r600_texture
*rtex
;
2642 unsigned mask
= sctx
->framebuffer
.compressed_cb_mask
;
2645 unsigned i
= u_bit_scan(&mask
);
2646 surf
= sctx
->framebuffer
.state
.cbufs
[i
];
2647 rtex
= (struct r600_texture
*)surf
->texture
;
2649 if (rtex
->fmask
.size
)
2650 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2651 if (rtex
->dcc_gather_statistics
)
2652 rtex
->separate_dcc_dirty
= true;
2657 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state
*state
)
2659 for (int i
= 0; i
< state
->nr_cbufs
; ++i
) {
2660 struct r600_surface
*surf
= NULL
;
2661 struct r600_texture
*rtex
;
2663 if (!state
->cbufs
[i
])
2665 surf
= (struct r600_surface
*)state
->cbufs
[i
];
2666 rtex
= (struct r600_texture
*)surf
->base
.texture
;
2668 p_atomic_dec(&rtex
->framebuffers_bound
);
2672 static void si_set_framebuffer_state(struct pipe_context
*ctx
,
2673 const struct pipe_framebuffer_state
*state
)
2675 struct si_context
*sctx
= (struct si_context
*)ctx
;
2676 struct pipe_constant_buffer constbuf
= {0};
2677 struct r600_surface
*surf
= NULL
;
2678 struct r600_texture
*rtex
;
2679 bool old_any_dst_linear
= sctx
->framebuffer
.any_dst_linear
;
2680 unsigned old_nr_samples
= sctx
->framebuffer
.nr_samples
;
2681 unsigned old_colorbuf_enabled_4bit
= sctx
->framebuffer
.colorbuf_enabled_4bit
;
2682 bool old_has_zsbuf
= !!sctx
->framebuffer
.state
.zsbuf
;
2683 bool old_has_stencil
=
2685 ((struct r600_texture
*)sctx
->framebuffer
.state
.zsbuf
->texture
)->surface
.has_stencil
;
2686 bool unbound
= false;
2689 si_update_fb_dirtiness_after_rendering(sctx
);
2691 for (i
= 0; i
< sctx
->framebuffer
.state
.nr_cbufs
; i
++) {
2692 if (!sctx
->framebuffer
.state
.cbufs
[i
])
2695 rtex
= (struct r600_texture
*)sctx
->framebuffer
.state
.cbufs
[i
]->texture
;
2696 if (rtex
->dcc_gather_statistics
)
2697 vi_separate_dcc_stop_query(ctx
, rtex
);
2700 /* Disable DCC if the formats are incompatible. */
2701 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
2702 if (!state
->cbufs
[i
])
2705 surf
= (struct r600_surface
*)state
->cbufs
[i
];
2706 rtex
= (struct r600_texture
*)surf
->base
.texture
;
2708 if (!surf
->dcc_incompatible
)
2711 /* Since the DCC decompression calls back into set_framebuffer-
2712 * _state, we need to unbind the framebuffer, so that
2713 * vi_separate_dcc_stop_query isn't called twice with the same
2717 util_copy_framebuffer_state(&sctx
->framebuffer
.state
, NULL
);
2721 if (vi_dcc_enabled(rtex
, surf
->base
.u
.tex
.level
))
2722 if (!r600_texture_disable_dcc(&sctx
->b
, rtex
))
2723 sctx
->b
.decompress_dcc(ctx
, rtex
);
2725 surf
->dcc_incompatible
= false;
2728 /* Only flush TC when changing the framebuffer state, because
2729 * the only client not using TC that can change textures is
2732 * Wait for compute shaders because of possible transitions:
2733 * - FB write -> shader read
2734 * - shader write -> FB read
2736 * DB caches are flushed on demand (using si_decompress_textures).
2738 * When MSAA is enabled, CB and TC caches are flushed on demand
2739 * (after FMASK decompression). Shader write -> FB read transitions
2740 * cannot happen for MSAA textures, because MSAA shader images are
2743 * Only flush and wait for CB if there is actually a bound color buffer.
2745 if (sctx
->framebuffer
.nr_samples
<= 1 &&
2746 sctx
->framebuffer
.state
.nr_cbufs
)
2747 si_make_CB_shader_coherent(sctx
, sctx
->framebuffer
.nr_samples
,
2748 sctx
->framebuffer
.CB_has_shader_readable_metadata
);
2750 sctx
->b
.flags
|= SI_CONTEXT_CS_PARTIAL_FLUSH
;
2752 /* u_blitter doesn't invoke depth decompression when it does multiple
2753 * blits in a row, but the only case when it matters for DB is when
2754 * doing generate_mipmap. So here we flush DB manually between
2755 * individual generate_mipmap blits.
2756 * Note that lower mipmap levels aren't compressed.
2758 if (sctx
->generate_mipmap_for_depth
) {
2759 si_make_DB_shader_coherent(sctx
, 1, false,
2760 sctx
->framebuffer
.DB_has_shader_readable_metadata
);
2761 } else if (sctx
->b
.chip_class
== GFX9
) {
2762 /* It appears that DB metadata "leaks" in a sequence of:
2764 * - DCC decompress for shader image writes (with DB disabled)
2765 * - render with DEPTH_BEFORE_SHADER=1
2766 * Flushing DB metadata works around the problem.
2768 sctx
->b
.flags
|= SI_CONTEXT_FLUSH_AND_INV_DB_META
;
2771 /* Take the maximum of the old and new count. If the new count is lower,
2772 * dirtying is needed to disable the unbound colorbuffers.
2774 sctx
->framebuffer
.dirty_cbufs
|=
2775 (1 << MAX2(sctx
->framebuffer
.state
.nr_cbufs
, state
->nr_cbufs
)) - 1;
2776 sctx
->framebuffer
.dirty_zsbuf
|= sctx
->framebuffer
.state
.zsbuf
!= state
->zsbuf
;
2778 si_dec_framebuffer_counters(&sctx
->framebuffer
.state
);
2779 util_copy_framebuffer_state(&sctx
->framebuffer
.state
, state
);
2781 sctx
->framebuffer
.colorbuf_enabled_4bit
= 0;
2782 sctx
->framebuffer
.spi_shader_col_format
= 0;
2783 sctx
->framebuffer
.spi_shader_col_format_alpha
= 0;
2784 sctx
->framebuffer
.spi_shader_col_format_blend
= 0;
2785 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
= 0;
2786 sctx
->framebuffer
.color_is_int8
= 0;
2787 sctx
->framebuffer
.color_is_int10
= 0;
2789 sctx
->framebuffer
.compressed_cb_mask
= 0;
2790 sctx
->framebuffer
.nr_samples
= util_framebuffer_get_num_samples(state
);
2791 sctx
->framebuffer
.log_samples
= util_logbase2(sctx
->framebuffer
.nr_samples
);
2792 sctx
->framebuffer
.any_dst_linear
= false;
2793 sctx
->framebuffer
.CB_has_shader_readable_metadata
= false;
2794 sctx
->framebuffer
.DB_has_shader_readable_metadata
= false;
2796 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
2797 if (!state
->cbufs
[i
])
2800 surf
= (struct r600_surface
*)state
->cbufs
[i
];
2801 rtex
= (struct r600_texture
*)surf
->base
.texture
;
2803 if (!surf
->color_initialized
) {
2804 si_initialize_color_surface(sctx
, surf
);
2807 sctx
->framebuffer
.colorbuf_enabled_4bit
|= 0xf << (i
* 4);
2808 sctx
->framebuffer
.spi_shader_col_format
|=
2809 surf
->spi_shader_col_format
<< (i
* 4);
2810 sctx
->framebuffer
.spi_shader_col_format_alpha
|=
2811 surf
->spi_shader_col_format_alpha
<< (i
* 4);
2812 sctx
->framebuffer
.spi_shader_col_format_blend
|=
2813 surf
->spi_shader_col_format_blend
<< (i
* 4);
2814 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
|=
2815 surf
->spi_shader_col_format_blend_alpha
<< (i
* 4);
2817 if (surf
->color_is_int8
)
2818 sctx
->framebuffer
.color_is_int8
|= 1 << i
;
2819 if (surf
->color_is_int10
)
2820 sctx
->framebuffer
.color_is_int10
|= 1 << i
;
2822 if (rtex
->fmask
.size
) {
2823 sctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
2826 if (rtex
->surface
.is_linear
)
2827 sctx
->framebuffer
.any_dst_linear
= true;
2829 if (vi_dcc_enabled(rtex
, surf
->base
.u
.tex
.level
))
2830 sctx
->framebuffer
.CB_has_shader_readable_metadata
= true;
2832 r600_context_add_resource_size(ctx
, surf
->base
.texture
);
2834 p_atomic_inc(&rtex
->framebuffers_bound
);
2836 if (rtex
->dcc_gather_statistics
) {
2837 /* Dirty tracking must be enabled for DCC usage analysis. */
2838 sctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
2839 vi_separate_dcc_start_query(ctx
, rtex
);
2843 struct r600_texture
*zstex
= NULL
;
2846 surf
= (struct r600_surface
*)state
->zsbuf
;
2847 zstex
= (struct r600_texture
*)surf
->base
.texture
;
2849 if (!surf
->depth_initialized
) {
2850 si_init_depth_surface(sctx
, surf
);
2853 if (vi_tc_compat_htile_enabled(zstex
, surf
->base
.u
.tex
.level
))
2854 sctx
->framebuffer
.DB_has_shader_readable_metadata
= true;
2856 r600_context_add_resource_size(ctx
, surf
->base
.texture
);
2859 si_update_poly_offset_state(sctx
);
2860 si_mark_atom_dirty(sctx
, &sctx
->cb_render_state
);
2861 si_mark_atom_dirty(sctx
, &sctx
->framebuffer
.atom
);
2863 if (sctx
->screen
->dpbb_allowed
)
2864 si_mark_atom_dirty(sctx
, &sctx
->dpbb_state
);
2866 if (sctx
->framebuffer
.any_dst_linear
!= old_any_dst_linear
)
2867 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
2869 if (sctx
->screen
->has_out_of_order_rast
&&
2870 (sctx
->framebuffer
.colorbuf_enabled_4bit
!= old_colorbuf_enabled_4bit
||
2871 !!sctx
->framebuffer
.state
.zsbuf
!= old_has_zsbuf
||
2872 (zstex
&& zstex
->surface
.has_stencil
!= old_has_stencil
)))
2873 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
2875 if (sctx
->framebuffer
.nr_samples
!= old_nr_samples
) {
2876 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
2877 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
2879 /* Set sample locations as fragment shader constants. */
2880 switch (sctx
->framebuffer
.nr_samples
) {
2882 constbuf
.user_buffer
= sctx
->b
.sample_locations_1x
;
2885 constbuf
.user_buffer
= sctx
->b
.sample_locations_2x
;
2888 constbuf
.user_buffer
= sctx
->b
.sample_locations_4x
;
2891 constbuf
.user_buffer
= sctx
->b
.sample_locations_8x
;
2894 constbuf
.user_buffer
= sctx
->b
.sample_locations_16x
;
2897 R600_ERR("Requested an invalid number of samples %i.\n",
2898 sctx
->framebuffer
.nr_samples
);
2901 constbuf
.buffer_size
= sctx
->framebuffer
.nr_samples
* 2 * 4;
2902 si_set_rw_buffer(sctx
, SI_PS_CONST_SAMPLE_POSITIONS
, &constbuf
);
2904 si_mark_atom_dirty(sctx
, &sctx
->msaa_sample_locs
.atom
);
2907 sctx
->do_update_shaders
= true;
2909 if (!sctx
->decompression_enabled
) {
2910 /* Prevent textures decompression when the framebuffer state
2911 * changes come from the decompression passes themselves.
2913 sctx
->need_check_render_feedback
= true;
2917 static void si_emit_framebuffer_state(struct si_context
*sctx
, struct r600_atom
*atom
)
2919 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
2920 struct pipe_framebuffer_state
*state
= &sctx
->framebuffer
.state
;
2921 unsigned i
, nr_cbufs
= state
->nr_cbufs
;
2922 struct r600_texture
*tex
= NULL
;
2923 struct r600_surface
*cb
= NULL
;
2924 unsigned cb_color_info
= 0;
2927 for (i
= 0; i
< nr_cbufs
; i
++) {
2928 uint64_t cb_color_base
, cb_color_fmask
, cb_dcc_base
;
2929 unsigned cb_color_attrib
;
2931 if (!(sctx
->framebuffer
.dirty_cbufs
& (1 << i
)))
2934 cb
= (struct r600_surface
*)state
->cbufs
[i
];
2936 radeon_set_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
2937 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
2941 tex
= (struct r600_texture
*)cb
->base
.texture
;
2942 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
2943 &tex
->resource
, RADEON_USAGE_READWRITE
,
2944 tex
->resource
.b
.b
.nr_samples
> 1 ?
2945 RADEON_PRIO_COLOR_BUFFER_MSAA
:
2946 RADEON_PRIO_COLOR_BUFFER
);
2948 if (tex
->cmask_buffer
&& tex
->cmask_buffer
!= &tex
->resource
) {
2949 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
2950 tex
->cmask_buffer
, RADEON_USAGE_READWRITE
,
2954 if (tex
->dcc_separate_buffer
)
2955 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
2956 tex
->dcc_separate_buffer
,
2957 RADEON_USAGE_READWRITE
,
2960 /* Compute mutable surface parameters. */
2961 cb_color_base
= tex
->resource
.gpu_address
>> 8;
2964 cb_color_info
= cb
->cb_color_info
| tex
->cb_color_info
;
2965 cb_color_attrib
= cb
->cb_color_attrib
;
2967 if (tex
->fmask
.size
) {
2968 cb_color_fmask
= (tex
->resource
.gpu_address
+ tex
->fmask
.offset
) >> 8;
2969 cb_color_fmask
|= tex
->fmask
.tile_swizzle
;
2973 if (vi_dcc_enabled(tex
, cb
->base
.u
.tex
.level
)) {
2974 bool is_msaa_resolve_dst
= state
->cbufs
[0] &&
2975 state
->cbufs
[0]->texture
->nr_samples
> 1 &&
2976 state
->cbufs
[1] == &cb
->base
&&
2977 state
->cbufs
[1]->texture
->nr_samples
<= 1;
2979 if (!is_msaa_resolve_dst
)
2980 cb_color_info
|= S_028C70_DCC_ENABLE(1);
2982 cb_dcc_base
= ((!tex
->dcc_separate_buffer
? tex
->resource
.gpu_address
: 0) +
2983 tex
->dcc_offset
) >> 8;
2984 cb_dcc_base
|= tex
->surface
.tile_swizzle
;
2987 if (sctx
->b
.chip_class
>= GFX9
) {
2988 struct gfx9_surf_meta_flags meta
;
2990 if (tex
->dcc_offset
)
2991 meta
= tex
->surface
.u
.gfx9
.dcc
;
2993 meta
= tex
->surface
.u
.gfx9
.cmask
;
2995 /* Set mutable surface parameters. */
2996 cb_color_base
+= tex
->surface
.u
.gfx9
.surf_offset
>> 8;
2997 cb_color_base
|= tex
->surface
.tile_swizzle
;
2998 if (!tex
->fmask
.size
)
2999 cb_color_fmask
= cb_color_base
;
3000 cb_color_attrib
|= S_028C74_COLOR_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
3001 S_028C74_FMASK_SW_MODE(tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
) |
3002 S_028C74_RB_ALIGNED(meta
.rb_aligned
) |
3003 S_028C74_PIPE_ALIGNED(meta
.pipe_aligned
);
3005 radeon_set_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C, 15);
3006 radeon_emit(cs
, cb_color_base
); /* CB_COLOR0_BASE */
3007 radeon_emit(cs
, cb_color_base
>> 32); /* CB_COLOR0_BASE_EXT */
3008 radeon_emit(cs
, cb
->cb_color_attrib2
); /* CB_COLOR0_ATTRIB2 */
3009 radeon_emit(cs
, cb
->cb_color_view
); /* CB_COLOR0_VIEW */
3010 radeon_emit(cs
, cb_color_info
); /* CB_COLOR0_INFO */
3011 radeon_emit(cs
, cb_color_attrib
); /* CB_COLOR0_ATTRIB */
3012 radeon_emit(cs
, cb
->cb_dcc_control
); /* CB_COLOR0_DCC_CONTROL */
3013 radeon_emit(cs
, tex
->cmask
.base_address_reg
); /* CB_COLOR0_CMASK */
3014 radeon_emit(cs
, tex
->cmask
.base_address_reg
>> 32); /* CB_COLOR0_CMASK_BASE_EXT */
3015 radeon_emit(cs
, cb_color_fmask
); /* CB_COLOR0_FMASK */
3016 radeon_emit(cs
, cb_color_fmask
>> 32); /* CB_COLOR0_FMASK_BASE_EXT */
3017 radeon_emit(cs
, tex
->color_clear_value
[0]); /* CB_COLOR0_CLEAR_WORD0 */
3018 radeon_emit(cs
, tex
->color_clear_value
[1]); /* CB_COLOR0_CLEAR_WORD1 */
3019 radeon_emit(cs
, cb_dcc_base
); /* CB_COLOR0_DCC_BASE */
3020 radeon_emit(cs
, cb_dcc_base
>> 32); /* CB_COLOR0_DCC_BASE_EXT */
3022 radeon_set_context_reg(cs
, R_0287A0_CB_MRT0_EPITCH
+ i
* 4,
3023 S_0287A0_EPITCH(tex
->surface
.u
.gfx9
.surf
.epitch
));
3025 /* Compute mutable surface parameters (SI-CI-VI). */
3026 const struct legacy_surf_level
*level_info
=
3027 &tex
->surface
.u
.legacy
.level
[cb
->base
.u
.tex
.level
];
3028 unsigned pitch_tile_max
, slice_tile_max
, tile_mode_index
;
3029 unsigned cb_color_pitch
, cb_color_slice
, cb_color_fmask_slice
;
3031 cb_color_base
+= level_info
->offset
>> 8;
3032 /* Only macrotiled modes can set tile swizzle. */
3033 if (level_info
->mode
== RADEON_SURF_MODE_2D
)
3034 cb_color_base
|= tex
->surface
.tile_swizzle
;
3036 if (!tex
->fmask
.size
)
3037 cb_color_fmask
= cb_color_base
;
3039 cb_dcc_base
+= level_info
->dcc_offset
>> 8;
3041 pitch_tile_max
= level_info
->nblk_x
/ 8 - 1;
3042 slice_tile_max
= level_info
->nblk_x
*
3043 level_info
->nblk_y
/ 64 - 1;
3044 tile_mode_index
= si_tile_mode_index(tex
, cb
->base
.u
.tex
.level
, false);
3046 cb_color_attrib
|= S_028C74_TILE_MODE_INDEX(tile_mode_index
);
3047 cb_color_pitch
= S_028C64_TILE_MAX(pitch_tile_max
);
3048 cb_color_slice
= S_028C68_TILE_MAX(slice_tile_max
);
3050 if (tex
->fmask
.size
) {
3051 if (sctx
->b
.chip_class
>= CIK
)
3052 cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(tex
->fmask
.pitch_in_pixels
/ 8 - 1);
3053 cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tex
->fmask
.tile_mode_index
);
3054 cb_color_fmask_slice
= S_028C88_TILE_MAX(tex
->fmask
.slice_tile_max
);
3056 /* This must be set for fast clear to work without FMASK. */
3057 if (sctx
->b
.chip_class
>= CIK
)
3058 cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(pitch_tile_max
);
3059 cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index
);
3060 cb_color_fmask_slice
= S_028C88_TILE_MAX(slice_tile_max
);
3063 radeon_set_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C,
3064 sctx
->b
.chip_class
>= VI
? 14 : 13);
3065 radeon_emit(cs
, cb_color_base
); /* CB_COLOR0_BASE */
3066 radeon_emit(cs
, cb_color_pitch
); /* CB_COLOR0_PITCH */
3067 radeon_emit(cs
, cb_color_slice
); /* CB_COLOR0_SLICE */
3068 radeon_emit(cs
, cb
->cb_color_view
); /* CB_COLOR0_VIEW */
3069 radeon_emit(cs
, cb_color_info
); /* CB_COLOR0_INFO */
3070 radeon_emit(cs
, cb_color_attrib
); /* CB_COLOR0_ATTRIB */
3071 radeon_emit(cs
, cb
->cb_dcc_control
); /* CB_COLOR0_DCC_CONTROL */
3072 radeon_emit(cs
, tex
->cmask
.base_address_reg
); /* CB_COLOR0_CMASK */
3073 radeon_emit(cs
, tex
->cmask
.slice_tile_max
); /* CB_COLOR0_CMASK_SLICE */
3074 radeon_emit(cs
, cb_color_fmask
); /* CB_COLOR0_FMASK */
3075 radeon_emit(cs
, cb_color_fmask_slice
); /* CB_COLOR0_FMASK_SLICE */
3076 radeon_emit(cs
, tex
->color_clear_value
[0]); /* CB_COLOR0_CLEAR_WORD0 */
3077 radeon_emit(cs
, tex
->color_clear_value
[1]); /* CB_COLOR0_CLEAR_WORD1 */
3079 if (sctx
->b
.chip_class
>= VI
) /* R_028C94_CB_COLOR0_DCC_BASE */
3080 radeon_emit(cs
, cb_dcc_base
);
3084 if (sctx
->framebuffer
.dirty_cbufs
& (1 << i
))
3085 radeon_set_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C, 0);
3088 if (state
->zsbuf
&& sctx
->framebuffer
.dirty_zsbuf
) {
3089 struct r600_surface
*zb
= (struct r600_surface
*)state
->zsbuf
;
3090 struct r600_texture
*rtex
= (struct r600_texture
*)zb
->base
.texture
;
3092 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
3093 &rtex
->resource
, RADEON_USAGE_READWRITE
,
3094 zb
->base
.texture
->nr_samples
> 1 ?
3095 RADEON_PRIO_DEPTH_BUFFER_MSAA
:
3096 RADEON_PRIO_DEPTH_BUFFER
);
3098 if (sctx
->b
.chip_class
>= GFX9
) {
3099 radeon_set_context_reg_seq(cs
, R_028014_DB_HTILE_DATA_BASE
, 3);
3100 radeon_emit(cs
, zb
->db_htile_data_base
); /* DB_HTILE_DATA_BASE */
3101 radeon_emit(cs
, zb
->db_htile_data_base
>> 32); /* DB_HTILE_DATA_BASE_HI */
3102 radeon_emit(cs
, zb
->db_depth_size
); /* DB_DEPTH_SIZE */
3104 radeon_set_context_reg_seq(cs
, R_028038_DB_Z_INFO
, 10);
3105 radeon_emit(cs
, zb
->db_z_info
| /* DB_Z_INFO */
3106 S_028038_ZRANGE_PRECISION(rtex
->depth_clear_value
!= 0));
3107 radeon_emit(cs
, zb
->db_stencil_info
); /* DB_STENCIL_INFO */
3108 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_READ_BASE */
3109 radeon_emit(cs
, zb
->db_depth_base
>> 32); /* DB_Z_READ_BASE_HI */
3110 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_READ_BASE */
3111 radeon_emit(cs
, zb
->db_stencil_base
>> 32); /* DB_STENCIL_READ_BASE_HI */
3112 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_WRITE_BASE */
3113 radeon_emit(cs
, zb
->db_depth_base
>> 32); /* DB_Z_WRITE_BASE_HI */
3114 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_WRITE_BASE */
3115 radeon_emit(cs
, zb
->db_stencil_base
>> 32); /* DB_STENCIL_WRITE_BASE_HI */
3117 radeon_set_context_reg_seq(cs
, R_028068_DB_Z_INFO2
, 2);
3118 radeon_emit(cs
, zb
->db_z_info2
); /* DB_Z_INFO2 */
3119 radeon_emit(cs
, zb
->db_stencil_info2
); /* DB_STENCIL_INFO2 */
3121 radeon_set_context_reg(cs
, R_028014_DB_HTILE_DATA_BASE
, zb
->db_htile_data_base
);
3123 radeon_set_context_reg_seq(cs
, R_02803C_DB_DEPTH_INFO
, 9);
3124 radeon_emit(cs
, zb
->db_depth_info
); /* DB_DEPTH_INFO */
3125 radeon_emit(cs
, zb
->db_z_info
| /* DB_Z_INFO */
3126 S_028040_ZRANGE_PRECISION(rtex
->depth_clear_value
!= 0));
3127 radeon_emit(cs
, zb
->db_stencil_info
); /* DB_STENCIL_INFO */
3128 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_READ_BASE */
3129 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_READ_BASE */
3130 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_WRITE_BASE */
3131 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_WRITE_BASE */
3132 radeon_emit(cs
, zb
->db_depth_size
); /* DB_DEPTH_SIZE */
3133 radeon_emit(cs
, zb
->db_depth_slice
); /* DB_DEPTH_SLICE */
3136 radeon_set_context_reg_seq(cs
, R_028028_DB_STENCIL_CLEAR
, 2);
3137 radeon_emit(cs
, rtex
->stencil_clear_value
); /* R_028028_DB_STENCIL_CLEAR */
3138 radeon_emit(cs
, fui(rtex
->depth_clear_value
)); /* R_02802C_DB_DEPTH_CLEAR */
3140 radeon_set_context_reg(cs
, R_028008_DB_DEPTH_VIEW
, zb
->db_depth_view
);
3141 radeon_set_context_reg(cs
, R_028ABC_DB_HTILE_SURFACE
, zb
->db_htile_surface
);
3142 } else if (sctx
->framebuffer
.dirty_zsbuf
) {
3143 if (sctx
->b
.chip_class
>= GFX9
)
3144 radeon_set_context_reg_seq(cs
, R_028038_DB_Z_INFO
, 2);
3146 radeon_set_context_reg_seq(cs
, R_028040_DB_Z_INFO
, 2);
3148 radeon_emit(cs
, S_028040_FORMAT(V_028040_Z_INVALID
)); /* DB_Z_INFO */
3149 radeon_emit(cs
, S_028044_FORMAT(V_028044_STENCIL_INVALID
)); /* DB_STENCIL_INFO */
3152 /* Framebuffer dimensions. */
3153 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
3154 radeon_set_context_reg(cs
, R_028208_PA_SC_WINDOW_SCISSOR_BR
,
3155 S_028208_BR_X(state
->width
) | S_028208_BR_Y(state
->height
));
3157 if (sctx
->screen
->dfsm_allowed
) {
3158 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3159 radeon_emit(cs
, EVENT_TYPE(V_028A90_BREAK_BATCH
) | EVENT_INDEX(0));
3162 sctx
->framebuffer
.dirty_cbufs
= 0;
3163 sctx
->framebuffer
.dirty_zsbuf
= false;
3166 static void si_emit_msaa_sample_locs(struct si_context
*sctx
,
3167 struct r600_atom
*atom
)
3169 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
3170 unsigned nr_samples
= sctx
->framebuffer
.nr_samples
;
3171 bool has_msaa_sample_loc_bug
= sctx
->screen
->has_msaa_sample_loc_bug
;
3173 /* Smoothing (only possible with nr_samples == 1) uses the same
3174 * sample locations as the MSAA it simulates.
3176 if (nr_samples
<= 1 && sctx
->smoothing_enabled
)
3177 nr_samples
= SI_NUM_SMOOTH_AA_SAMPLES
;
3179 /* On Polaris, the small primitive filter uses the sample locations
3180 * even when MSAA is off, so we need to make sure they're set to 0.
3182 if (has_msaa_sample_loc_bug
)
3183 nr_samples
= MAX2(nr_samples
, 1);
3185 if (nr_samples
!= sctx
->msaa_sample_locs
.nr_samples
) {
3186 sctx
->msaa_sample_locs
.nr_samples
= nr_samples
;
3187 cayman_emit_msaa_sample_locs(cs
, nr_samples
);
3190 if (sctx
->b
.family
>= CHIP_POLARIS10
) {
3191 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
3192 unsigned small_prim_filter_cntl
=
3193 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
3195 S_028830_LINE_FILTER_DISABLE(sctx
->b
.family
<= CHIP_POLARIS12
);
3197 /* The alternative of setting sample locations to 0 would
3198 * require a DB flush to avoid Z errors, see
3199 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
3201 if (has_msaa_sample_loc_bug
&&
3202 sctx
->framebuffer
.nr_samples
> 1 &&
3203 rs
&& !rs
->multisample_enable
)
3204 small_prim_filter_cntl
&= C_028830_SMALL_PRIM_FILTER_ENABLE
;
3206 radeon_set_context_reg(cs
, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL
,
3207 small_prim_filter_cntl
);
3211 static bool si_out_of_order_rasterization(struct si_context
*sctx
)
3213 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
3214 struct si_state_dsa
*dsa
= sctx
->queued
.named
.dsa
;
3216 if (!sctx
->screen
->has_out_of_order_rast
)
3219 unsigned colormask
= sctx
->framebuffer
.colorbuf_enabled_4bit
;
3222 colormask
&= blend
->cb_target_enabled_4bit
;
3227 /* Conservative: No logic op. */
3228 if (colormask
&& blend
->logicop_enable
)
3231 struct si_dsa_order_invariance dsa_order_invariant
= {
3232 .zs
= true, .pass_set
= true, .pass_last
= false
3235 if (sctx
->framebuffer
.state
.zsbuf
) {
3236 struct r600_texture
*zstex
=
3237 (struct r600_texture
*)sctx
->framebuffer
.state
.zsbuf
->texture
;
3238 bool has_stencil
= zstex
->surface
.has_stencil
;
3239 dsa_order_invariant
= dsa
->order_invariance
[has_stencil
];
3240 if (!dsa_order_invariant
.zs
)
3243 /* The set of PS invocations is always order invariant,
3244 * except when early Z/S tests are requested. */
3245 if (sctx
->ps_shader
.cso
&&
3246 sctx
->ps_shader
.cso
->info
.writes_memory
&&
3247 sctx
->ps_shader
.cso
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
] &&
3248 !dsa_order_invariant
.pass_set
)
3251 if (sctx
->b
.num_perfect_occlusion_queries
!= 0 &&
3252 !dsa_order_invariant
.pass_set
)
3259 unsigned blendmask
= colormask
& blend
->blend_enable_4bit
;
3262 /* Only commutative blending. */
3263 if (blendmask
& ~blend
->commutative_4bit
)
3266 if (!dsa_order_invariant
.pass_set
)
3270 if (colormask
& ~blendmask
) {
3271 if (!dsa_order_invariant
.pass_last
)
3278 static void si_emit_msaa_config(struct si_context
*sctx
, struct r600_atom
*atom
)
3280 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
3281 unsigned num_tile_pipes
= sctx
->screen
->b
.info
.num_tile_pipes
;
3282 /* 33% faster rendering to linear color buffers */
3283 bool dst_is_linear
= sctx
->framebuffer
.any_dst_linear
;
3284 bool out_of_order_rast
= si_out_of_order_rasterization(sctx
);
3285 unsigned sc_mode_cntl_1
=
3286 S_028A4C_WALK_SIZE(dst_is_linear
) |
3287 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear
) |
3288 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes
== 2 ? 2 : 3) |
3289 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast
) |
3290 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
3292 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
3293 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
3294 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
3295 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
3296 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
3297 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
3299 cayman_emit_msaa_config(cs
, sctx
->framebuffer
.nr_samples
,
3300 sctx
->ps_iter_samples
,
3301 sctx
->smoothing_enabled
? SI_NUM_SMOOTH_AA_SAMPLES
: 0,
3304 /* GFX9: Flush DFSM when the AA mode changes. */
3305 if (sctx
->screen
->dfsm_allowed
) {
3306 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3307 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
3311 static void si_set_min_samples(struct pipe_context
*ctx
, unsigned min_samples
)
3313 struct si_context
*sctx
= (struct si_context
*)ctx
;
3315 if (sctx
->ps_iter_samples
== min_samples
)
3318 sctx
->ps_iter_samples
= min_samples
;
3319 sctx
->do_update_shaders
= true;
3321 if (sctx
->framebuffer
.nr_samples
> 1)
3322 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
3323 if (sctx
->screen
->dpbb_allowed
)
3324 si_mark_atom_dirty(sctx
, &sctx
->dpbb_state
);
3332 * Build the sampler view descriptor for a buffer texture.
3333 * @param state 256-bit descriptor; only the high 128 bits are filled in
3336 si_make_buffer_descriptor(struct si_screen
*screen
, struct r600_resource
*buf
,
3337 enum pipe_format format
,
3338 unsigned offset
, unsigned size
,
3341 const struct util_format_description
*desc
;
3344 unsigned num_records
;
3345 unsigned num_format
, data_format
;
3347 desc
= util_format_description(format
);
3348 first_non_void
= util_format_get_first_non_void_channel(format
);
3349 stride
= desc
->block
.bits
/ 8;
3350 num_format
= si_translate_buffer_numformat(&screen
->b
.b
, desc
, first_non_void
);
3351 data_format
= si_translate_buffer_dataformat(&screen
->b
.b
, desc
, first_non_void
);
3353 num_records
= size
/ stride
;
3354 num_records
= MIN2(num_records
, (buf
->b
.b
.width0
- offset
) / stride
);
3356 /* The NUM_RECORDS field has a different meaning depending on the chip,
3357 * instruction type, STRIDE, and SWIZZLE_ENABLE.
3360 * - If STRIDE == 0, it's in byte units.
3361 * - If STRIDE != 0, it's in units of STRIDE, used with inst.IDXEN.
3364 * - For SMEM and STRIDE == 0, it's in byte units.
3365 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3366 * - For VMEM and STRIDE == 0 or SWIZZLE_ENABLE == 0, it's in byte units.
3367 * - For VMEM and STRIDE != 0 and SWIZZLE_ENABLE == 1, it's in units of STRIDE.
3368 * NOTE: There is incompatibility between VMEM and SMEM opcodes due to SWIZZLE_-
3369 * ENABLE. The workaround is to set STRIDE = 0 if SWIZZLE_ENABLE == 0 when
3370 * using SMEM. This can be done in the shader by clearing STRIDE with s_and.
3371 * That way the same descriptor can be used by both SMEM and VMEM.
3374 * - For SMEM and STRIDE == 0, it's in byte units.
3375 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3376 * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
3377 * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
3379 if (screen
->b
.chip_class
>= GFX9
)
3380 /* When vindex == 0, LLVM sets IDXEN = 0, thus changing units
3381 * from STRIDE to bytes. This works around it by setting
3382 * NUM_RECORDS to at least the size of one element, so that
3383 * the first element is readable when IDXEN == 0.
3385 * TODO: Fix this in LLVM, but do we need a new intrinsic where
3386 * IDXEN is enforced?
3388 num_records
= num_records
? MAX2(num_records
, stride
) : 0;
3389 else if (screen
->b
.chip_class
== VI
)
3390 num_records
*= stride
;
3393 state
[5] = S_008F04_STRIDE(stride
);
3394 state
[6] = num_records
;
3395 state
[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc
->swizzle
[0])) |
3396 S_008F0C_DST_SEL_Y(si_map_swizzle(desc
->swizzle
[1])) |
3397 S_008F0C_DST_SEL_Z(si_map_swizzle(desc
->swizzle
[2])) |
3398 S_008F0C_DST_SEL_W(si_map_swizzle(desc
->swizzle
[3])) |
3399 S_008F0C_NUM_FORMAT(num_format
) |
3400 S_008F0C_DATA_FORMAT(data_format
);
3403 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle
[4])
3405 unsigned bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
3407 if (swizzle
[3] == PIPE_SWIZZLE_X
) {
3408 /* For the pre-defined border color values (white, opaque
3409 * black, transparent black), the only thing that matters is
3410 * that the alpha channel winds up in the correct place
3411 * (because the RGB channels are all the same) so either of
3412 * these enumerations will work.
3414 if (swizzle
[2] == PIPE_SWIZZLE_Y
)
3415 bc_swizzle
= V_008F20_BC_SWIZZLE_WZYX
;
3417 bc_swizzle
= V_008F20_BC_SWIZZLE_WXYZ
;
3418 } else if (swizzle
[0] == PIPE_SWIZZLE_X
) {
3419 if (swizzle
[1] == PIPE_SWIZZLE_Y
)
3420 bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
3422 bc_swizzle
= V_008F20_BC_SWIZZLE_XWYZ
;
3423 } else if (swizzle
[1] == PIPE_SWIZZLE_X
) {
3424 bc_swizzle
= V_008F20_BC_SWIZZLE_YXWZ
;
3425 } else if (swizzle
[2] == PIPE_SWIZZLE_X
) {
3426 bc_swizzle
= V_008F20_BC_SWIZZLE_ZYXW
;
3433 * Build the sampler view descriptor for a texture.
3436 si_make_texture_descriptor(struct si_screen
*screen
,
3437 struct r600_texture
*tex
,
3439 enum pipe_texture_target target
,
3440 enum pipe_format pipe_format
,
3441 const unsigned char state_swizzle
[4],
3442 unsigned first_level
, unsigned last_level
,
3443 unsigned first_layer
, unsigned last_layer
,
3444 unsigned width
, unsigned height
, unsigned depth
,
3446 uint32_t *fmask_state
)
3448 struct pipe_resource
*res
= &tex
->resource
.b
.b
;
3449 const struct util_format_description
*desc
;
3450 unsigned char swizzle
[4];
3452 unsigned num_format
, data_format
, type
;
3455 desc
= util_format_description(pipe_format
);
3457 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
) {
3458 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
3459 const unsigned char swizzle_yyyy
[4] = {1, 1, 1, 1};
3460 const unsigned char swizzle_wwww
[4] = {3, 3, 3, 3};
3462 switch (pipe_format
) {
3463 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
3464 case PIPE_FORMAT_X32_S8X24_UINT
:
3465 case PIPE_FORMAT_X8Z24_UNORM
:
3466 util_format_compose_swizzles(swizzle_yyyy
, state_swizzle
, swizzle
);
3468 case PIPE_FORMAT_X24S8_UINT
:
3470 * X24S8 is implemented as an 8_8_8_8 data format, to
3471 * fix texture gathers. This affects at least
3472 * GL45-CTS.texture_cube_map_array.sampling on VI.
3474 util_format_compose_swizzles(swizzle_wwww
, state_swizzle
, swizzle
);
3477 util_format_compose_swizzles(swizzle_xxxx
, state_swizzle
, swizzle
);
3480 util_format_compose_swizzles(desc
->swizzle
, state_swizzle
, swizzle
);
3483 first_non_void
= util_format_get_first_non_void_channel(pipe_format
);
3485 switch (pipe_format
) {
3486 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
3487 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3490 if (first_non_void
< 0) {
3491 if (util_format_is_compressed(pipe_format
)) {
3492 switch (pipe_format
) {
3493 case PIPE_FORMAT_DXT1_SRGB
:
3494 case PIPE_FORMAT_DXT1_SRGBA
:
3495 case PIPE_FORMAT_DXT3_SRGBA
:
3496 case PIPE_FORMAT_DXT5_SRGBA
:
3497 case PIPE_FORMAT_BPTC_SRGBA
:
3498 case PIPE_FORMAT_ETC2_SRGB8
:
3499 case PIPE_FORMAT_ETC2_SRGB8A1
:
3500 case PIPE_FORMAT_ETC2_SRGBA8
:
3501 num_format
= V_008F14_IMG_NUM_FORMAT_SRGB
;
3503 case PIPE_FORMAT_RGTC1_SNORM
:
3504 case PIPE_FORMAT_LATC1_SNORM
:
3505 case PIPE_FORMAT_RGTC2_SNORM
:
3506 case PIPE_FORMAT_LATC2_SNORM
:
3507 case PIPE_FORMAT_ETC2_R11_SNORM
:
3508 case PIPE_FORMAT_ETC2_RG11_SNORM
:
3509 /* implies float, so use SNORM/UNORM to determine
3510 whether data is signed or not */
3511 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
3512 num_format
= V_008F14_IMG_NUM_FORMAT_SNORM
;
3515 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3518 } else if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
3519 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3521 num_format
= V_008F14_IMG_NUM_FORMAT_FLOAT
;
3523 } else if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
) {
3524 num_format
= V_008F14_IMG_NUM_FORMAT_SRGB
;
3526 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3528 switch (desc
->channel
[first_non_void
].type
) {
3529 case UTIL_FORMAT_TYPE_FLOAT
:
3530 num_format
= V_008F14_IMG_NUM_FORMAT_FLOAT
;
3532 case UTIL_FORMAT_TYPE_SIGNED
:
3533 if (desc
->channel
[first_non_void
].normalized
)
3534 num_format
= V_008F14_IMG_NUM_FORMAT_SNORM
;
3535 else if (desc
->channel
[first_non_void
].pure_integer
)
3536 num_format
= V_008F14_IMG_NUM_FORMAT_SINT
;
3538 num_format
= V_008F14_IMG_NUM_FORMAT_SSCALED
;
3540 case UTIL_FORMAT_TYPE_UNSIGNED
:
3541 if (desc
->channel
[first_non_void
].normalized
)
3542 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3543 else if (desc
->channel
[first_non_void
].pure_integer
)
3544 num_format
= V_008F14_IMG_NUM_FORMAT_UINT
;
3546 num_format
= V_008F14_IMG_NUM_FORMAT_USCALED
;
3551 data_format
= si_translate_texformat(&screen
->b
.b
, pipe_format
, desc
, first_non_void
);
3552 if (data_format
== ~0) {
3556 /* S8 with Z32 HTILE needs a special format. */
3557 if (screen
->b
.chip_class
>= GFX9
&&
3558 pipe_format
== PIPE_FORMAT_S8_UINT
&&
3559 tex
->tc_compatible_htile
)
3560 data_format
= V_008F14_IMG_DATA_FORMAT_S8_32
;
3563 (res
->target
== PIPE_TEXTURE_CUBE
||
3564 res
->target
== PIPE_TEXTURE_CUBE_ARRAY
||
3565 (screen
->b
.chip_class
<= VI
&&
3566 res
->target
== PIPE_TEXTURE_3D
))) {
3567 /* For the purpose of shader images, treat cube maps and 3D
3568 * textures as 2D arrays. For 3D textures, the address
3569 * calculations for mipmaps are different, so we rely on the
3570 * caller to effectively disable mipmaps.
3572 type
= V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
3574 assert(res
->target
!= PIPE_TEXTURE_3D
|| (first_level
== 0 && last_level
== 0));
3576 type
= si_tex_dim(screen
, tex
, target
, res
->nr_samples
);
3579 if (type
== V_008F1C_SQ_RSRC_IMG_1D_ARRAY
) {
3581 depth
= res
->array_size
;
3582 } else if (type
== V_008F1C_SQ_RSRC_IMG_2D_ARRAY
||
3583 type
== V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
) {
3584 if (sampler
|| res
->target
!= PIPE_TEXTURE_3D
)
3585 depth
= res
->array_size
;
3586 } else if (type
== V_008F1C_SQ_RSRC_IMG_CUBE
)
3587 depth
= res
->array_size
/ 6;
3590 state
[1] = (S_008F14_DATA_FORMAT_GFX6(data_format
) |
3591 S_008F14_NUM_FORMAT_GFX6(num_format
));
3592 state
[2] = (S_008F18_WIDTH(width
- 1) |
3593 S_008F18_HEIGHT(height
- 1) |
3594 S_008F18_PERF_MOD(4));
3595 state
[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle
[0])) |
3596 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle
[1])) |
3597 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle
[2])) |
3598 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle
[3])) |
3599 S_008F1C_BASE_LEVEL(res
->nr_samples
> 1 ?
3601 S_008F1C_LAST_LEVEL(res
->nr_samples
> 1 ?
3602 util_logbase2(res
->nr_samples
) :
3604 S_008F1C_TYPE(type
));
3606 state
[5] = S_008F24_BASE_ARRAY(first_layer
);
3610 if (screen
->b
.chip_class
>= GFX9
) {
3611 unsigned bc_swizzle
= gfx9_border_color_swizzle(desc
->swizzle
);
3613 /* Depth is the the last accessible layer on Gfx9.
3614 * The hw doesn't need to know the total number of layers.
3616 if (type
== V_008F1C_SQ_RSRC_IMG_3D
)
3617 state
[4] |= S_008F20_DEPTH(depth
- 1);
3619 state
[4] |= S_008F20_DEPTH(last_layer
);
3621 state
[4] |= S_008F20_BC_SWIZZLE(bc_swizzle
);
3622 state
[5] |= S_008F24_MAX_MIP(res
->nr_samples
> 1 ?
3623 util_logbase2(res
->nr_samples
) :
3624 tex
->resource
.b
.b
.last_level
);
3626 state
[3] |= S_008F1C_POW2_PAD(res
->last_level
> 0);
3627 state
[4] |= S_008F20_DEPTH(depth
- 1);
3628 state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
3631 if (tex
->dcc_offset
) {
3632 unsigned swap
= r600_translate_colorswap(pipe_format
, false);
3634 state
[6] = S_008F28_ALPHA_IS_ON_MSB(swap
<= 1);
3636 /* The last dword is unused by hw. The shader uses it to clear
3637 * bits in the first dword of sampler state.
3639 if (screen
->b
.chip_class
<= CIK
&& res
->nr_samples
<= 1) {
3640 if (first_level
== last_level
)
3641 state
[7] = C_008F30_MAX_ANISO_RATIO
;
3643 state
[7] = 0xffffffff;
3647 /* Initialize the sampler view for FMASK. */
3648 if (tex
->fmask
.size
) {
3649 uint32_t data_format
, num_format
;
3651 va
= tex
->resource
.gpu_address
+ tex
->fmask
.offset
;
3653 if (screen
->b
.chip_class
>= GFX9
) {
3654 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK
;
3655 switch (res
->nr_samples
) {
3657 num_format
= V_008F14_IMG_FMASK_8_2_2
;
3660 num_format
= V_008F14_IMG_FMASK_8_4_4
;
3663 num_format
= V_008F14_IMG_FMASK_32_8_8
;
3666 unreachable("invalid nr_samples");
3669 switch (res
->nr_samples
) {
3671 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2
;
3674 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4
;
3677 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8
;
3680 unreachable("invalid nr_samples");
3682 num_format
= V_008F14_IMG_NUM_FORMAT_UINT
;
3685 fmask_state
[0] = (va
>> 8) | tex
->fmask
.tile_swizzle
;
3686 fmask_state
[1] = S_008F14_BASE_ADDRESS_HI(va
>> 40) |
3687 S_008F14_DATA_FORMAT_GFX6(data_format
) |
3688 S_008F14_NUM_FORMAT_GFX6(num_format
);
3689 fmask_state
[2] = S_008F18_WIDTH(width
- 1) |
3690 S_008F18_HEIGHT(height
- 1);
3691 fmask_state
[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X
) |
3692 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X
) |
3693 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X
) |
3694 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X
) |
3695 S_008F1C_TYPE(si_tex_dim(screen
, tex
, target
, 0));
3697 fmask_state
[5] = S_008F24_BASE_ARRAY(first_layer
);
3701 if (screen
->b
.chip_class
>= GFX9
) {
3702 fmask_state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
);
3703 fmask_state
[4] |= S_008F20_DEPTH(last_layer
) |
3704 S_008F20_PITCH_GFX9(tex
->surface
.u
.gfx9
.fmask
.epitch
);
3705 fmask_state
[5] |= S_008F24_META_PIPE_ALIGNED(tex
->surface
.u
.gfx9
.cmask
.pipe_aligned
) |
3706 S_008F24_META_RB_ALIGNED(tex
->surface
.u
.gfx9
.cmask
.rb_aligned
);
3708 fmask_state
[3] |= S_008F1C_TILING_INDEX(tex
->fmask
.tile_mode_index
);
3709 fmask_state
[4] |= S_008F20_DEPTH(depth
- 1) |
3710 S_008F20_PITCH_GFX6(tex
->fmask
.pitch_in_pixels
- 1);
3711 fmask_state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
3717 * Create a sampler view.
3719 * @param ctx context
3720 * @param texture texture
3721 * @param state sampler view template
3722 * @param width0 width0 override (for compressed textures as int)
3723 * @param height0 height0 override (for compressed textures as int)
3724 * @param force_level set the base address to the level (for compressed textures)
3726 struct pipe_sampler_view
*
3727 si_create_sampler_view_custom(struct pipe_context
*ctx
,
3728 struct pipe_resource
*texture
,
3729 const struct pipe_sampler_view
*state
,
3730 unsigned width0
, unsigned height0
,
3731 unsigned force_level
)
3733 struct si_context
*sctx
= (struct si_context
*)ctx
;
3734 struct si_sampler_view
*view
= CALLOC_STRUCT(si_sampler_view
);
3735 struct r600_texture
*tmp
= (struct r600_texture
*)texture
;
3736 unsigned base_level
, first_level
, last_level
;
3737 unsigned char state_swizzle
[4];
3738 unsigned height
, depth
, width
;
3739 unsigned last_layer
= state
->u
.tex
.last_layer
;
3740 enum pipe_format pipe_format
;
3741 const struct legacy_surf_level
*surflevel
;
3746 /* initialize base object */
3747 view
->base
= *state
;
3748 view
->base
.texture
= NULL
;
3749 view
->base
.reference
.count
= 1;
3750 view
->base
.context
= ctx
;
3753 pipe_resource_reference(&view
->base
.texture
, texture
);
3755 if (state
->format
== PIPE_FORMAT_X24S8_UINT
||
3756 state
->format
== PIPE_FORMAT_S8X24_UINT
||
3757 state
->format
== PIPE_FORMAT_X32_S8X24_UINT
||
3758 state
->format
== PIPE_FORMAT_S8_UINT
)
3759 view
->is_stencil_sampler
= true;
3761 /* Buffer resource. */
3762 if (texture
->target
== PIPE_BUFFER
) {
3763 si_make_buffer_descriptor(sctx
->screen
,
3764 (struct r600_resource
*)texture
,
3766 state
->u
.buf
.offset
,
3772 state_swizzle
[0] = state
->swizzle_r
;
3773 state_swizzle
[1] = state
->swizzle_g
;
3774 state_swizzle
[2] = state
->swizzle_b
;
3775 state_swizzle
[3] = state
->swizzle_a
;
3778 first_level
= state
->u
.tex
.first_level
;
3779 last_level
= state
->u
.tex
.last_level
;
3782 depth
= texture
->depth0
;
3784 if (sctx
->b
.chip_class
<= VI
&& force_level
) {
3785 assert(force_level
== first_level
&&
3786 force_level
== last_level
);
3787 base_level
= force_level
;
3790 width
= u_minify(width
, force_level
);
3791 height
= u_minify(height
, force_level
);
3792 depth
= u_minify(depth
, force_level
);
3795 /* This is not needed if state trackers set last_layer correctly. */
3796 if (state
->target
== PIPE_TEXTURE_1D
||
3797 state
->target
== PIPE_TEXTURE_2D
||
3798 state
->target
== PIPE_TEXTURE_RECT
||
3799 state
->target
== PIPE_TEXTURE_CUBE
)
3800 last_layer
= state
->u
.tex
.first_layer
;
3802 /* Texturing with separate depth and stencil. */
3803 pipe_format
= state
->format
;
3805 /* Depth/stencil texturing sometimes needs separate texture. */
3806 if (tmp
->is_depth
&& !r600_can_sample_zs(tmp
, view
->is_stencil_sampler
)) {
3807 if (!tmp
->flushed_depth_texture
&&
3808 !r600_init_flushed_depth_texture(ctx
, texture
, NULL
)) {
3809 pipe_resource_reference(&view
->base
.texture
, NULL
);
3814 assert(tmp
->flushed_depth_texture
);
3816 /* Override format for the case where the flushed texture
3817 * contains only Z or only S.
3819 if (tmp
->flushed_depth_texture
->resource
.b
.b
.format
!= tmp
->resource
.b
.b
.format
)
3820 pipe_format
= tmp
->flushed_depth_texture
->resource
.b
.b
.format
;
3822 tmp
= tmp
->flushed_depth_texture
;
3825 surflevel
= tmp
->surface
.u
.legacy
.level
;
3827 if (tmp
->db_compatible
) {
3828 if (!view
->is_stencil_sampler
)
3829 pipe_format
= tmp
->db_render_format
;
3831 switch (pipe_format
) {
3832 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
3833 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
3835 case PIPE_FORMAT_X8Z24_UNORM
:
3836 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
3837 /* Z24 is always stored like this for DB
3840 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
3842 case PIPE_FORMAT_X24S8_UINT
:
3843 case PIPE_FORMAT_S8X24_UINT
:
3844 case PIPE_FORMAT_X32_S8X24_UINT
:
3845 pipe_format
= PIPE_FORMAT_S8_UINT
;
3846 surflevel
= tmp
->surface
.u
.legacy
.stencil_level
;
3852 view
->dcc_incompatible
=
3853 vi_dcc_formats_are_incompatible(texture
,
3854 state
->u
.tex
.first_level
,
3857 si_make_texture_descriptor(sctx
->screen
, tmp
, true,
3858 state
->target
, pipe_format
, state_swizzle
,
3859 first_level
, last_level
,
3860 state
->u
.tex
.first_layer
, last_layer
,
3861 width
, height
, depth
,
3862 view
->state
, view
->fmask_state
);
3864 view
->base_level_info
= &surflevel
[base_level
];
3865 view
->base_level
= base_level
;
3866 view
->block_width
= util_format_get_blockwidth(pipe_format
);
3870 static struct pipe_sampler_view
*
3871 si_create_sampler_view(struct pipe_context
*ctx
,
3872 struct pipe_resource
*texture
,
3873 const struct pipe_sampler_view
*state
)
3875 return si_create_sampler_view_custom(ctx
, texture
, state
,
3876 texture
? texture
->width0
: 0,
3877 texture
? texture
->height0
: 0, 0);
3880 static void si_sampler_view_destroy(struct pipe_context
*ctx
,
3881 struct pipe_sampler_view
*state
)
3883 struct si_sampler_view
*view
= (struct si_sampler_view
*)state
;
3885 pipe_resource_reference(&state
->texture
, NULL
);
3889 static bool wrap_mode_uses_border_color(unsigned wrap
, bool linear_filter
)
3891 return wrap
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
||
3892 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
||
3894 (wrap
== PIPE_TEX_WRAP_CLAMP
||
3895 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP
));
3898 static bool sampler_state_needs_border_color(const struct pipe_sampler_state
*state
)
3900 bool linear_filter
= state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
||
3901 state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
;
3903 return (state
->border_color
.ui
[0] || state
->border_color
.ui
[1] ||
3904 state
->border_color
.ui
[2] || state
->border_color
.ui
[3]) &&
3905 (wrap_mode_uses_border_color(state
->wrap_s
, linear_filter
) ||
3906 wrap_mode_uses_border_color(state
->wrap_t
, linear_filter
) ||
3907 wrap_mode_uses_border_color(state
->wrap_r
, linear_filter
));
3910 static void *si_create_sampler_state(struct pipe_context
*ctx
,
3911 const struct pipe_sampler_state
*state
)
3913 struct si_context
*sctx
= (struct si_context
*)ctx
;
3914 struct r600_common_screen
*rscreen
= sctx
->b
.screen
;
3915 struct si_sampler_state
*rstate
= CALLOC_STRUCT(si_sampler_state
);
3916 unsigned border_color_type
, border_color_index
= 0;
3917 unsigned max_aniso
= rscreen
->force_aniso
>= 0 ? rscreen
->force_aniso
3918 : state
->max_anisotropy
;
3919 unsigned max_aniso_ratio
= r600_tex_aniso_filter(max_aniso
);
3925 if (!sampler_state_needs_border_color(state
))
3926 border_color_type
= V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
;
3927 else if (state
->border_color
.f
[0] == 0 &&
3928 state
->border_color
.f
[1] == 0 &&
3929 state
->border_color
.f
[2] == 0 &&
3930 state
->border_color
.f
[3] == 0)
3931 border_color_type
= V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
;
3932 else if (state
->border_color
.f
[0] == 0 &&
3933 state
->border_color
.f
[1] == 0 &&
3934 state
->border_color
.f
[2] == 0 &&
3935 state
->border_color
.f
[3] == 1)
3936 border_color_type
= V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK
;
3937 else if (state
->border_color
.f
[0] == 1 &&
3938 state
->border_color
.f
[1] == 1 &&
3939 state
->border_color
.f
[2] == 1 &&
3940 state
->border_color
.f
[3] == 1)
3941 border_color_type
= V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE
;
3945 border_color_type
= V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER
;
3947 /* Check if the border has been uploaded already. */
3948 for (i
= 0; i
< sctx
->border_color_count
; i
++)
3949 if (memcmp(&sctx
->border_color_table
[i
], &state
->border_color
,
3950 sizeof(state
->border_color
)) == 0)
3953 if (i
>= SI_MAX_BORDER_COLORS
) {
3954 /* Getting 4096 unique border colors is very unlikely. */
3955 fprintf(stderr
, "radeonsi: The border color table is full. "
3956 "Any new border colors will be just black. "
3957 "Please file a bug.\n");
3958 border_color_type
= V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
;
3960 if (i
== sctx
->border_color_count
) {
3961 /* Upload a new border color. */
3962 memcpy(&sctx
->border_color_table
[i
], &state
->border_color
,
3963 sizeof(state
->border_color
));
3964 util_memcpy_cpu_to_le32(&sctx
->border_color_map
[i
],
3965 &state
->border_color
,
3966 sizeof(state
->border_color
));
3967 sctx
->border_color_count
++;
3970 border_color_index
= i
;
3975 rstate
->magic
= SI_SAMPLER_STATE_MAGIC
;
3977 rstate
->val
[0] = (S_008F30_CLAMP_X(si_tex_wrap(state
->wrap_s
)) |
3978 S_008F30_CLAMP_Y(si_tex_wrap(state
->wrap_t
)) |
3979 S_008F30_CLAMP_Z(si_tex_wrap(state
->wrap_r
)) |
3980 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio
) |
3981 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state
->compare_func
)) |
3982 S_008F30_FORCE_UNNORMALIZED(!state
->normalized_coords
) |
3983 S_008F30_ANISO_THRESHOLD(max_aniso_ratio
>> 1) |
3984 S_008F30_ANISO_BIAS(max_aniso_ratio
) |
3985 S_008F30_DISABLE_CUBE_WRAP(!state
->seamless_cube_map
) |
3986 S_008F30_COMPAT_MODE(sctx
->b
.chip_class
>= VI
));
3987 rstate
->val
[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 8)) |
3988 S_008F34_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 8)) |
3989 S_008F34_PERF_MIP(max_aniso_ratio
? max_aniso_ratio
+ 6 : 0));
3990 rstate
->val
[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 8)) |
3991 S_008F38_XY_MAG_FILTER(eg_tex_filter(state
->mag_img_filter
, max_aniso
)) |
3992 S_008F38_XY_MIN_FILTER(eg_tex_filter(state
->min_img_filter
, max_aniso
)) |
3993 S_008F38_MIP_FILTER(si_tex_mipfilter(state
->min_mip_filter
)) |
3994 S_008F38_MIP_POINT_PRECLAMP(0) |
3995 S_008F38_DISABLE_LSB_CEIL(sctx
->b
.chip_class
<= VI
) |
3996 S_008F38_FILTER_PREC_FIX(1) |
3997 S_008F38_ANISO_OVERRIDE(sctx
->b
.chip_class
>= VI
));
3998 rstate
->val
[3] = S_008F3C_BORDER_COLOR_PTR(border_color_index
) |
3999 S_008F3C_BORDER_COLOR_TYPE(border_color_type
);
4003 static void si_set_sample_mask(struct pipe_context
*ctx
, unsigned sample_mask
)
4005 struct si_context
*sctx
= (struct si_context
*)ctx
;
4007 if (sctx
->sample_mask
.sample_mask
== (uint16_t)sample_mask
)
4010 sctx
->sample_mask
.sample_mask
= sample_mask
;
4011 si_mark_atom_dirty(sctx
, &sctx
->sample_mask
.atom
);
4014 static void si_emit_sample_mask(struct si_context
*sctx
, struct r600_atom
*atom
)
4016 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
4017 unsigned mask
= sctx
->sample_mask
.sample_mask
;
4019 /* Needed for line and polygon smoothing as well as for the Polaris
4020 * small primitive filter. We expect the state tracker to take care of
4023 assert(mask
== 0xffff || sctx
->framebuffer
.nr_samples
> 1 ||
4024 (mask
& 1 && sctx
->blitter
->running
));
4026 radeon_set_context_reg_seq(cs
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
4027 radeon_emit(cs
, mask
| (mask
<< 16));
4028 radeon_emit(cs
, mask
| (mask
<< 16));
4031 static void si_delete_sampler_state(struct pipe_context
*ctx
, void *state
)
4034 struct si_sampler_state
*s
= state
;
4036 assert(s
->magic
== SI_SAMPLER_STATE_MAGIC
);
4043 * Vertex elements & buffers
4046 static void *si_create_vertex_elements(struct pipe_context
*ctx
,
4048 const struct pipe_vertex_element
*elements
)
4050 struct si_screen
*sscreen
= (struct si_screen
*)ctx
->screen
;
4051 struct si_vertex_elements
*v
= CALLOC_STRUCT(si_vertex_elements
);
4052 bool used
[SI_NUM_VERTEX_BUFFERS
] = {};
4055 assert(count
<= SI_MAX_ATTRIBS
);
4060 v
->desc_list_byte_size
= align(count
* 16, SI_CPDMA_ALIGNMENT
);
4062 for (i
= 0; i
< count
; ++i
) {
4063 const struct util_format_description
*desc
;
4064 const struct util_format_channel_description
*channel
;
4065 unsigned data_format
, num_format
;
4067 unsigned vbo_index
= elements
[i
].vertex_buffer_index
;
4068 unsigned char swizzle
[4];
4070 if (vbo_index
>= SI_NUM_VERTEX_BUFFERS
) {
4075 if (elements
[i
].instance_divisor
) {
4076 v
->uses_instance_divisors
= true;
4077 v
->instance_divisors
[i
] = elements
[i
].instance_divisor
;
4079 if (v
->instance_divisors
[i
] == 1)
4080 v
->instance_divisor_is_one
|= 1u << i
;
4082 v
->instance_divisor_is_fetched
|= 1u << i
;
4085 if (!used
[vbo_index
]) {
4086 v
->first_vb_use_mask
|= 1 << i
;
4087 used
[vbo_index
] = true;
4090 desc
= util_format_description(elements
[i
].src_format
);
4091 first_non_void
= util_format_get_first_non_void_channel(elements
[i
].src_format
);
4092 data_format
= si_translate_buffer_dataformat(ctx
->screen
, desc
, first_non_void
);
4093 num_format
= si_translate_buffer_numformat(ctx
->screen
, desc
, first_non_void
);
4094 channel
= first_non_void
>= 0 ? &desc
->channel
[first_non_void
] : NULL
;
4095 memcpy(swizzle
, desc
->swizzle
, sizeof(swizzle
));
4097 v
->format_size
[i
] = desc
->block
.bits
/ 8;
4098 v
->src_offset
[i
] = elements
[i
].src_offset
;
4099 v
->vertex_buffer_index
[i
] = vbo_index
;
4101 /* The hardware always treats the 2-bit alpha channel as
4102 * unsigned, so a shader workaround is needed. The affected
4103 * chips are VI and older except Stoney (GFX8.1).
4105 if (data_format
== V_008F0C_BUF_DATA_FORMAT_2_10_10_10
&&
4106 sscreen
->b
.chip_class
<= VI
&&
4107 sscreen
->b
.family
!= CHIP_STONEY
) {
4108 if (num_format
== V_008F0C_BUF_NUM_FORMAT_SNORM
) {
4109 v
->fix_fetch
[i
] = SI_FIX_FETCH_A2_SNORM
;
4110 } else if (num_format
== V_008F0C_BUF_NUM_FORMAT_SSCALED
) {
4111 v
->fix_fetch
[i
] = SI_FIX_FETCH_A2_SSCALED
;
4112 } else if (num_format
== V_008F0C_BUF_NUM_FORMAT_SINT
) {
4113 /* This isn't actually used in OpenGL. */
4114 v
->fix_fetch
[i
] = SI_FIX_FETCH_A2_SINT
;
4116 } else if (channel
&& channel
->type
== UTIL_FORMAT_TYPE_FIXED
) {
4117 if (desc
->swizzle
[3] == PIPE_SWIZZLE_1
)
4118 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBX_32_FIXED
;
4120 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_32_FIXED
;
4121 } else if (channel
&& channel
->size
== 32 && !channel
->pure_integer
) {
4122 if (channel
->type
== UTIL_FORMAT_TYPE_SIGNED
) {
4123 if (channel
->normalized
) {
4124 if (desc
->swizzle
[3] == PIPE_SWIZZLE_1
)
4125 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBX_32_SNORM
;
4127 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_32_SNORM
;
4129 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_32_SSCALED
;
4131 } else if (channel
->type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
4132 if (channel
->normalized
) {
4133 if (desc
->swizzle
[3] == PIPE_SWIZZLE_1
)
4134 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBX_32_UNORM
;
4136 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_32_UNORM
;
4138 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_32_USCALED
;
4141 } else if (channel
&& channel
->size
== 64 &&
4142 channel
->type
== UTIL_FORMAT_TYPE_FLOAT
) {
4143 switch (desc
->nr_channels
) {
4146 v
->fix_fetch
[i
] = SI_FIX_FETCH_RG_64_FLOAT
;
4147 swizzle
[0] = PIPE_SWIZZLE_X
;
4148 swizzle
[1] = PIPE_SWIZZLE_Y
;
4149 swizzle
[2] = desc
->nr_channels
== 2 ? PIPE_SWIZZLE_Z
: PIPE_SWIZZLE_0
;
4150 swizzle
[3] = desc
->nr_channels
== 2 ? PIPE_SWIZZLE_W
: PIPE_SWIZZLE_0
;
4153 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGB_64_FLOAT
;
4154 swizzle
[0] = PIPE_SWIZZLE_X
; /* 3 loads */
4155 swizzle
[1] = PIPE_SWIZZLE_Y
;
4156 swizzle
[2] = PIPE_SWIZZLE_0
;
4157 swizzle
[3] = PIPE_SWIZZLE_0
;
4160 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_64_FLOAT
;
4161 swizzle
[0] = PIPE_SWIZZLE_X
; /* 2 loads */
4162 swizzle
[1] = PIPE_SWIZZLE_Y
;
4163 swizzle
[2] = PIPE_SWIZZLE_Z
;
4164 swizzle
[3] = PIPE_SWIZZLE_W
;
4169 } else if (channel
&& desc
->nr_channels
== 3) {
4170 assert(desc
->swizzle
[0] == PIPE_SWIZZLE_X
);
4172 if (channel
->size
== 8) {
4173 if (channel
->pure_integer
)
4174 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGB_8_INT
;
4176 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGB_8
;
4177 } else if (channel
->size
== 16) {
4178 if (channel
->pure_integer
)
4179 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGB_16_INT
;
4181 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGB_16
;
4185 v
->rsrc_word3
[i
] = S_008F0C_DST_SEL_X(si_map_swizzle(swizzle
[0])) |
4186 S_008F0C_DST_SEL_Y(si_map_swizzle(swizzle
[1])) |
4187 S_008F0C_DST_SEL_Z(si_map_swizzle(swizzle
[2])) |
4188 S_008F0C_DST_SEL_W(si_map_swizzle(swizzle
[3])) |
4189 S_008F0C_NUM_FORMAT(num_format
) |
4190 S_008F0C_DATA_FORMAT(data_format
);
4195 static void si_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
4197 struct si_context
*sctx
= (struct si_context
*)ctx
;
4198 struct si_vertex_elements
*old
= sctx
->vertex_elements
;
4199 struct si_vertex_elements
*v
= (struct si_vertex_elements
*)state
;
4201 sctx
->vertex_elements
= v
;
4202 sctx
->vertex_buffers_dirty
= true;
4206 old
->count
!= v
->count
||
4207 old
->uses_instance_divisors
!= v
->uses_instance_divisors
||
4208 v
->uses_instance_divisors
|| /* we don't check which divisors changed */
4209 memcmp(old
->fix_fetch
, v
->fix_fetch
, sizeof(v
->fix_fetch
[0]) * v
->count
)))
4210 sctx
->do_update_shaders
= true;
4212 if (v
&& v
->instance_divisor_is_fetched
) {
4213 struct pipe_constant_buffer cb
;
4216 cb
.user_buffer
= v
->instance_divisors
;
4217 cb
.buffer_offset
= 0;
4218 cb
.buffer_size
= sizeof(uint32_t) * v
->count
;
4219 si_set_rw_buffer(sctx
, SI_VS_CONST_INSTANCE_DIVISORS
, &cb
);
4223 static void si_delete_vertex_element(struct pipe_context
*ctx
, void *state
)
4225 struct si_context
*sctx
= (struct si_context
*)ctx
;
4227 if (sctx
->vertex_elements
== state
)
4228 sctx
->vertex_elements
= NULL
;
4232 static void si_set_vertex_buffers(struct pipe_context
*ctx
,
4233 unsigned start_slot
, unsigned count
,
4234 const struct pipe_vertex_buffer
*buffers
)
4236 struct si_context
*sctx
= (struct si_context
*)ctx
;
4237 struct pipe_vertex_buffer
*dst
= sctx
->vertex_buffer
+ start_slot
;
4240 assert(start_slot
+ count
<= ARRAY_SIZE(sctx
->vertex_buffer
));
4243 for (i
= 0; i
< count
; i
++) {
4244 const struct pipe_vertex_buffer
*src
= buffers
+ i
;
4245 struct pipe_vertex_buffer
*dsti
= dst
+ i
;
4246 struct pipe_resource
*buf
= src
->buffer
.resource
;
4248 pipe_resource_reference(&dsti
->buffer
.resource
, buf
);
4249 dsti
->buffer_offset
= src
->buffer_offset
;
4250 dsti
->stride
= src
->stride
;
4251 r600_context_add_resource_size(ctx
, buf
);
4253 r600_resource(buf
)->bind_history
|= PIPE_BIND_VERTEX_BUFFER
;
4256 for (i
= 0; i
< count
; i
++) {
4257 pipe_resource_reference(&dst
[i
].buffer
.resource
, NULL
);
4260 sctx
->vertex_buffers_dirty
= true;
4267 static void si_set_tess_state(struct pipe_context
*ctx
,
4268 const float default_outer_level
[4],
4269 const float default_inner_level
[2])
4271 struct si_context
*sctx
= (struct si_context
*)ctx
;
4272 struct pipe_constant_buffer cb
;
4275 memcpy(array
, default_outer_level
, sizeof(float) * 4);
4276 memcpy(array
+4, default_inner_level
, sizeof(float) * 2);
4279 cb
.user_buffer
= NULL
;
4280 cb
.buffer_size
= sizeof(array
);
4282 si_upload_const_buffer(sctx
, (struct r600_resource
**)&cb
.buffer
,
4283 (void*)array
, sizeof(array
),
4286 si_set_rw_buffer(sctx
, SI_HS_CONST_DEFAULT_TESS_LEVELS
, &cb
);
4287 pipe_resource_reference(&cb
.buffer
, NULL
);
4290 static void si_texture_barrier(struct pipe_context
*ctx
, unsigned flags
)
4292 struct si_context
*sctx
= (struct si_context
*)ctx
;
4294 si_update_fb_dirtiness_after_rendering(sctx
);
4296 /* Multisample surfaces are flushed in si_decompress_textures. */
4297 if (sctx
->framebuffer
.nr_samples
<= 1 &&
4298 sctx
->framebuffer
.state
.nr_cbufs
)
4299 si_make_CB_shader_coherent(sctx
, sctx
->framebuffer
.nr_samples
,
4300 sctx
->framebuffer
.CB_has_shader_readable_metadata
);
4303 /* This only ensures coherency for shader image/buffer stores. */
4304 static void si_memory_barrier(struct pipe_context
*ctx
, unsigned flags
)
4306 struct si_context
*sctx
= (struct si_context
*)ctx
;
4308 /* Subsequent commands must wait for all shader invocations to
4310 sctx
->b
.flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
|
4311 SI_CONTEXT_CS_PARTIAL_FLUSH
;
4313 if (flags
& PIPE_BARRIER_CONSTANT_BUFFER
)
4314 sctx
->b
.flags
|= SI_CONTEXT_INV_SMEM_L1
|
4315 SI_CONTEXT_INV_VMEM_L1
;
4317 if (flags
& (PIPE_BARRIER_VERTEX_BUFFER
|
4318 PIPE_BARRIER_SHADER_BUFFER
|
4319 PIPE_BARRIER_TEXTURE
|
4320 PIPE_BARRIER_IMAGE
|
4321 PIPE_BARRIER_STREAMOUT_BUFFER
|
4322 PIPE_BARRIER_GLOBAL_BUFFER
)) {
4323 /* As far as I can tell, L1 contents are written back to L2
4324 * automatically at end of shader, but the contents of other
4325 * L1 caches might still be stale. */
4326 sctx
->b
.flags
|= SI_CONTEXT_INV_VMEM_L1
;
4329 if (flags
& PIPE_BARRIER_INDEX_BUFFER
) {
4330 /* Indices are read through TC L2 since VI.
4333 if (sctx
->screen
->b
.chip_class
<= CIK
)
4334 sctx
->b
.flags
|= SI_CONTEXT_WRITEBACK_GLOBAL_L2
;
4337 /* MSAA color, any depth and any stencil are flushed in
4338 * si_decompress_textures when needed.
4340 if (flags
& PIPE_BARRIER_FRAMEBUFFER
&&
4341 sctx
->framebuffer
.nr_samples
<= 1 &&
4342 sctx
->framebuffer
.state
.nr_cbufs
) {
4343 sctx
->b
.flags
|= SI_CONTEXT_FLUSH_AND_INV_CB
;
4345 if (sctx
->b
.chip_class
<= VI
)
4346 sctx
->b
.flags
|= SI_CONTEXT_WRITEBACK_GLOBAL_L2
;
4349 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
4350 if (sctx
->screen
->b
.chip_class
<= VI
&&
4351 flags
& PIPE_BARRIER_INDIRECT_BUFFER
)
4352 sctx
->b
.flags
|= SI_CONTEXT_WRITEBACK_GLOBAL_L2
;
4355 static void *si_create_blend_custom(struct si_context
*sctx
, unsigned mode
)
4357 struct pipe_blend_state blend
;
4359 memset(&blend
, 0, sizeof(blend
));
4360 blend
.independent_blend_enable
= true;
4361 blend
.rt
[0].colormask
= 0xf;
4362 return si_create_blend_state_mode(&sctx
->b
.b
, &blend
, mode
);
4365 static void si_need_gfx_cs_space(struct pipe_context
*ctx
, unsigned num_dw
,
4366 bool include_draw_vbo
)
4368 si_need_cs_space((struct si_context
*)ctx
);
4371 static void si_init_config(struct si_context
*sctx
);
4373 void si_init_state_functions(struct si_context
*sctx
)
4375 si_init_external_atom(sctx
, &sctx
->b
.render_cond_atom
, &sctx
->atoms
.s
.render_cond
);
4376 si_init_external_atom(sctx
, &sctx
->b
.streamout
.begin_atom
, &sctx
->atoms
.s
.streamout_begin
);
4377 si_init_external_atom(sctx
, &sctx
->b
.streamout
.enable_atom
, &sctx
->atoms
.s
.streamout_enable
);
4378 si_init_external_atom(sctx
, &sctx
->b
.scissors
.atom
, &sctx
->atoms
.s
.scissors
);
4379 si_init_external_atom(sctx
, &sctx
->b
.viewports
.atom
, &sctx
->atoms
.s
.viewports
);
4381 si_init_atom(sctx
, &sctx
->framebuffer
.atom
, &sctx
->atoms
.s
.framebuffer
, si_emit_framebuffer_state
);
4382 si_init_atom(sctx
, &sctx
->msaa_sample_locs
.atom
, &sctx
->atoms
.s
.msaa_sample_locs
, si_emit_msaa_sample_locs
);
4383 si_init_atom(sctx
, &sctx
->db_render_state
, &sctx
->atoms
.s
.db_render_state
, si_emit_db_render_state
);
4384 si_init_atom(sctx
, &sctx
->dpbb_state
, &sctx
->atoms
.s
.dpbb_state
, si_emit_dpbb_state
);
4385 si_init_atom(sctx
, &sctx
->msaa_config
, &sctx
->atoms
.s
.msaa_config
, si_emit_msaa_config
);
4386 si_init_atom(sctx
, &sctx
->sample_mask
.atom
, &sctx
->atoms
.s
.sample_mask
, si_emit_sample_mask
);
4387 si_init_atom(sctx
, &sctx
->cb_render_state
, &sctx
->atoms
.s
.cb_render_state
, si_emit_cb_render_state
);
4388 si_init_atom(sctx
, &sctx
->blend_color
.atom
, &sctx
->atoms
.s
.blend_color
, si_emit_blend_color
);
4389 si_init_atom(sctx
, &sctx
->clip_regs
, &sctx
->atoms
.s
.clip_regs
, si_emit_clip_regs
);
4390 si_init_atom(sctx
, &sctx
->clip_state
.atom
, &sctx
->atoms
.s
.clip_state
, si_emit_clip_state
);
4391 si_init_atom(sctx
, &sctx
->stencil_ref
.atom
, &sctx
->atoms
.s
.stencil_ref
, si_emit_stencil_ref
);
4393 sctx
->b
.b
.create_blend_state
= si_create_blend_state
;
4394 sctx
->b
.b
.bind_blend_state
= si_bind_blend_state
;
4395 sctx
->b
.b
.delete_blend_state
= si_delete_blend_state
;
4396 sctx
->b
.b
.set_blend_color
= si_set_blend_color
;
4398 sctx
->b
.b
.create_rasterizer_state
= si_create_rs_state
;
4399 sctx
->b
.b
.bind_rasterizer_state
= si_bind_rs_state
;
4400 sctx
->b
.b
.delete_rasterizer_state
= si_delete_rs_state
;
4402 sctx
->b
.b
.create_depth_stencil_alpha_state
= si_create_dsa_state
;
4403 sctx
->b
.b
.bind_depth_stencil_alpha_state
= si_bind_dsa_state
;
4404 sctx
->b
.b
.delete_depth_stencil_alpha_state
= si_delete_dsa_state
;
4406 sctx
->custom_dsa_flush
= si_create_db_flush_dsa(sctx
);
4407 sctx
->custom_blend_resolve
= si_create_blend_custom(sctx
, V_028808_CB_RESOLVE
);
4408 sctx
->custom_blend_fmask_decompress
= si_create_blend_custom(sctx
, V_028808_CB_FMASK_DECOMPRESS
);
4409 sctx
->custom_blend_eliminate_fastclear
= si_create_blend_custom(sctx
, V_028808_CB_ELIMINATE_FAST_CLEAR
);
4410 sctx
->custom_blend_dcc_decompress
= si_create_blend_custom(sctx
, V_028808_CB_DCC_DECOMPRESS
);
4412 sctx
->b
.b
.set_clip_state
= si_set_clip_state
;
4413 sctx
->b
.b
.set_stencil_ref
= si_set_stencil_ref
;
4415 sctx
->b
.b
.set_framebuffer_state
= si_set_framebuffer_state
;
4416 sctx
->b
.b
.get_sample_position
= cayman_get_sample_position
;
4418 sctx
->b
.b
.create_sampler_state
= si_create_sampler_state
;
4419 sctx
->b
.b
.delete_sampler_state
= si_delete_sampler_state
;
4421 sctx
->b
.b
.create_sampler_view
= si_create_sampler_view
;
4422 sctx
->b
.b
.sampler_view_destroy
= si_sampler_view_destroy
;
4424 sctx
->b
.b
.set_sample_mask
= si_set_sample_mask
;
4426 sctx
->b
.b
.create_vertex_elements_state
= si_create_vertex_elements
;
4427 sctx
->b
.b
.bind_vertex_elements_state
= si_bind_vertex_elements
;
4428 sctx
->b
.b
.delete_vertex_elements_state
= si_delete_vertex_element
;
4429 sctx
->b
.b
.set_vertex_buffers
= si_set_vertex_buffers
;
4431 sctx
->b
.b
.texture_barrier
= si_texture_barrier
;
4432 sctx
->b
.b
.memory_barrier
= si_memory_barrier
;
4433 sctx
->b
.b
.set_min_samples
= si_set_min_samples
;
4434 sctx
->b
.b
.set_tess_state
= si_set_tess_state
;
4436 sctx
->b
.b
.set_active_query_state
= si_set_active_query_state
;
4437 sctx
->b
.set_occlusion_query_state
= si_set_occlusion_query_state
;
4438 sctx
->b
.save_qbo_state
= si_save_qbo_state
;
4439 sctx
->b
.need_gfx_cs_space
= si_need_gfx_cs_space
;
4441 sctx
->b
.b
.draw_vbo
= si_draw_vbo
;
4443 si_init_config(sctx
);
4446 static uint32_t si_get_bo_metadata_word1(struct r600_common_screen
*rscreen
)
4448 return (ATI_VENDOR_ID
<< 16) | rscreen
->info
.pci_id
;
4451 static void si_query_opaque_metadata(struct r600_common_screen
*rscreen
,
4452 struct r600_texture
*rtex
,
4453 struct radeon_bo_metadata
*md
)
4455 struct si_screen
*sscreen
= (struct si_screen
*)rscreen
;
4456 struct pipe_resource
*res
= &rtex
->resource
.b
.b
;
4457 static const unsigned char swizzle
[] = {
4463 uint32_t desc
[8], i
;
4464 bool is_array
= util_resource_is_array_texture(res
);
4466 /* DRM 2.x.x doesn't support this. */
4467 if (rscreen
->info
.drm_major
!= 3)
4470 assert(rtex
->dcc_separate_buffer
== NULL
);
4471 assert(rtex
->fmask
.size
== 0);
4473 /* Metadata image format format version 1:
4474 * [0] = 1 (metadata format identifier)
4475 * [1] = (VENDOR_ID << 16) | PCI_ID
4476 * [2:9] = image descriptor for the whole resource
4477 * [2] is always 0, because the base address is cleared
4478 * [9] is the DCC offset bits [39:8] from the beginning of
4480 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
4483 md
->metadata
[0] = 1; /* metadata image format version 1 */
4485 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
4486 md
->metadata
[1] = si_get_bo_metadata_word1(rscreen
);
4488 si_make_texture_descriptor(sscreen
, rtex
, true,
4489 res
->target
, res
->format
,
4490 swizzle
, 0, res
->last_level
, 0,
4491 is_array
? res
->array_size
- 1 : 0,
4492 res
->width0
, res
->height0
, res
->depth0
,
4495 si_set_mutable_tex_desc_fields(sscreen
, rtex
, &rtex
->surface
.u
.legacy
.level
[0],
4496 0, 0, rtex
->surface
.blk_w
, false, desc
);
4498 /* Clear the base address and set the relative DCC offset. */
4500 desc
[1] &= C_008F14_BASE_ADDRESS_HI
;
4501 desc
[7] = rtex
->dcc_offset
>> 8;
4503 /* Dwords [2:9] contain the image descriptor. */
4504 memcpy(&md
->metadata
[2], desc
, sizeof(desc
));
4505 md
->size_metadata
= 10 * 4;
4507 /* Dwords [10:..] contain the mipmap level offsets. */
4508 if (rscreen
->chip_class
<= VI
) {
4509 for (i
= 0; i
<= res
->last_level
; i
++)
4510 md
->metadata
[10+i
] = rtex
->surface
.u
.legacy
.level
[i
].offset
>> 8;
4512 md
->size_metadata
+= (1 + res
->last_level
) * 4;
4516 static void si_apply_opaque_metadata(struct r600_common_screen
*rscreen
,
4517 struct r600_texture
*rtex
,
4518 struct radeon_bo_metadata
*md
)
4520 uint32_t *desc
= &md
->metadata
[2];
4522 if (rscreen
->chip_class
< VI
)
4525 /* Return if DCC is enabled. The texture should be set up with it
4528 if (md
->size_metadata
>= 11 * 4 &&
4529 md
->metadata
[0] != 0 &&
4530 md
->metadata
[1] == si_get_bo_metadata_word1(rscreen
) &&
4531 G_008F28_COMPRESSION_EN(desc
[6])) {
4532 assert(rtex
->dcc_offset
== ((uint64_t)desc
[7] << 8));
4536 /* Disable DCC. These are always set by texture_from_handle and must
4539 rtex
->dcc_offset
= 0;
4542 void si_init_screen_state_functions(struct si_screen
*sscreen
)
4544 sscreen
->b
.b
.is_format_supported
= si_is_format_supported
;
4545 sscreen
->b
.query_opaque_metadata
= si_query_opaque_metadata
;
4546 sscreen
->b
.apply_opaque_metadata
= si_apply_opaque_metadata
;
4549 static void si_set_grbm_gfx_index(struct si_context
*sctx
,
4550 struct si_pm4_state
*pm4
, unsigned value
)
4552 unsigned reg
= sctx
->b
.chip_class
>= CIK
? R_030800_GRBM_GFX_INDEX
:
4554 si_pm4_set_reg(pm4
, reg
, value
);
4557 static void si_set_grbm_gfx_index_se(struct si_context
*sctx
,
4558 struct si_pm4_state
*pm4
, unsigned se
)
4560 assert(se
== ~0 || se
< sctx
->screen
->b
.info
.max_se
);
4561 si_set_grbm_gfx_index(sctx
, pm4
,
4562 (se
== ~0 ? S_030800_SE_BROADCAST_WRITES(1) :
4563 S_030800_SE_INDEX(se
)) |
4564 S_030800_SH_BROADCAST_WRITES(1) |
4565 S_030800_INSTANCE_BROADCAST_WRITES(1));
4569 si_write_harvested_raster_configs(struct si_context
*sctx
,
4570 struct si_pm4_state
*pm4
,
4571 unsigned raster_config
,
4572 unsigned raster_config_1
)
4574 unsigned sh_per_se
= MAX2(sctx
->screen
->b
.info
.max_sh_per_se
, 1);
4575 unsigned num_se
= MAX2(sctx
->screen
->b
.info
.max_se
, 1);
4576 unsigned rb_mask
= sctx
->screen
->b
.info
.enabled_rb_mask
;
4577 unsigned num_rb
= MIN2(sctx
->screen
->b
.info
.num_render_backends
, 16);
4578 unsigned rb_per_pkr
= MIN2(num_rb
/ num_se
/ sh_per_se
, 2);
4579 unsigned rb_per_se
= num_rb
/ num_se
;
4580 unsigned se_mask
[4];
4583 se_mask
[0] = ((1 << rb_per_se
) - 1);
4584 se_mask
[1] = (se_mask
[0] << rb_per_se
);
4585 se_mask
[2] = (se_mask
[1] << rb_per_se
);
4586 se_mask
[3] = (se_mask
[2] << rb_per_se
);
4588 se_mask
[0] &= rb_mask
;
4589 se_mask
[1] &= rb_mask
;
4590 se_mask
[2] &= rb_mask
;
4591 se_mask
[3] &= rb_mask
;
4593 assert(num_se
== 1 || num_se
== 2 || num_se
== 4);
4594 assert(sh_per_se
== 1 || sh_per_se
== 2);
4595 assert(rb_per_pkr
== 1 || rb_per_pkr
== 2);
4597 /* XXX: I can't figure out what the *_XSEL and *_YSEL
4598 * fields are for, so I'm leaving them as their default
4601 for (se
= 0; se
< num_se
; se
++) {
4602 unsigned raster_config_se
= raster_config
;
4603 unsigned pkr0_mask
= ((1 << rb_per_pkr
) - 1) << (se
* rb_per_se
);
4604 unsigned pkr1_mask
= pkr0_mask
<< rb_per_pkr
;
4605 int idx
= (se
/ 2) * 2;
4607 if ((num_se
> 1) && (!se_mask
[idx
] || !se_mask
[idx
+ 1])) {
4608 raster_config_se
&= C_028350_SE_MAP
;
4610 if (!se_mask
[idx
]) {
4612 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3
);
4615 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0
);
4619 pkr0_mask
&= rb_mask
;
4620 pkr1_mask
&= rb_mask
;
4621 if (rb_per_se
> 2 && (!pkr0_mask
|| !pkr1_mask
)) {
4622 raster_config_se
&= C_028350_PKR_MAP
;
4626 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3
);
4629 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0
);
4633 if (rb_per_se
>= 2) {
4634 unsigned rb0_mask
= 1 << (se
* rb_per_se
);
4635 unsigned rb1_mask
= rb0_mask
<< 1;
4637 rb0_mask
&= rb_mask
;
4638 rb1_mask
&= rb_mask
;
4639 if (!rb0_mask
|| !rb1_mask
) {
4640 raster_config_se
&= C_028350_RB_MAP_PKR0
;
4644 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3
);
4647 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0
);
4651 if (rb_per_se
> 2) {
4652 rb0_mask
= 1 << (se
* rb_per_se
+ rb_per_pkr
);
4653 rb1_mask
= rb0_mask
<< 1;
4654 rb0_mask
&= rb_mask
;
4655 rb1_mask
&= rb_mask
;
4656 if (!rb0_mask
|| !rb1_mask
) {
4657 raster_config_se
&= C_028350_RB_MAP_PKR1
;
4661 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3
);
4664 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0
);
4670 si_set_grbm_gfx_index_se(sctx
, pm4
, se
);
4671 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
, raster_config_se
);
4673 si_set_grbm_gfx_index(sctx
, pm4
, ~0);
4675 if (sctx
->b
.chip_class
>= CIK
) {
4676 if ((num_se
> 2) && ((!se_mask
[0] && !se_mask
[1]) ||
4677 (!se_mask
[2] && !se_mask
[3]))) {
4678 raster_config_1
&= C_028354_SE_PAIR_MAP
;
4680 if (!se_mask
[0] && !se_mask
[1]) {
4682 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3
);
4685 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0
);
4689 si_pm4_set_reg(pm4
, R_028354_PA_SC_RASTER_CONFIG_1
, raster_config_1
);
4693 static void si_set_raster_config(struct si_context
*sctx
, struct si_pm4_state
*pm4
)
4695 struct si_screen
*sscreen
= sctx
->screen
;
4696 unsigned num_rb
= MIN2(sctx
->screen
->b
.info
.num_render_backends
, 16);
4697 unsigned rb_mask
= sctx
->screen
->b
.info
.enabled_rb_mask
;
4698 unsigned raster_config
, raster_config_1
;
4700 switch (sctx
->b
.family
) {
4703 raster_config
= 0x2a00126a;
4704 raster_config_1
= 0x00000000;
4707 raster_config
= 0x0000124a;
4708 raster_config_1
= 0x00000000;
4711 raster_config
= 0x00000082;
4712 raster_config_1
= 0x00000000;
4715 raster_config
= 0x00000000;
4716 raster_config_1
= 0x00000000;
4719 raster_config
= 0x16000012;
4720 raster_config_1
= 0x00000000;
4723 raster_config
= 0x3a00161a;
4724 raster_config_1
= 0x0000002e;
4727 if (sscreen
->b
.info
.cik_macrotile_mode_array
[0] == 0x000000e8) {
4728 /* old kernels with old tiling config */
4729 raster_config
= 0x16000012;
4730 raster_config_1
= 0x0000002a;
4732 raster_config
= 0x3a00161a;
4733 raster_config_1
= 0x0000002e;
4736 case CHIP_POLARIS10
:
4737 raster_config
= 0x16000012;
4738 raster_config_1
= 0x0000002a;
4740 case CHIP_POLARIS11
:
4741 case CHIP_POLARIS12
:
4742 raster_config
= 0x16000012;
4743 raster_config_1
= 0x00000000;
4746 raster_config
= 0x16000012;
4747 raster_config_1
= 0x0000002a;
4751 raster_config
= 0x00000000;
4753 raster_config
= 0x00000002;
4754 raster_config_1
= 0x00000000;
4757 raster_config
= 0x00000002;
4758 raster_config_1
= 0x00000000;
4761 /* KV should be 0x00000002, but that causes problems with radeon */
4762 raster_config
= 0x00000000; /* 0x00000002 */
4763 raster_config_1
= 0x00000000;
4768 raster_config
= 0x00000000;
4769 raster_config_1
= 0x00000000;
4773 "radeonsi: Unknown GPU, using 0 for raster_config\n");
4774 raster_config
= 0x00000000;
4775 raster_config_1
= 0x00000000;
4778 if (!rb_mask
|| util_bitcount(rb_mask
) >= num_rb
) {
4779 /* Always use the default config when all backends are enabled
4780 * (or when we failed to determine the enabled backends).
4782 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
,
4784 if (sctx
->b
.chip_class
>= CIK
)
4785 si_pm4_set_reg(pm4
, R_028354_PA_SC_RASTER_CONFIG_1
,
4788 si_write_harvested_raster_configs(sctx
, pm4
, raster_config
, raster_config_1
);
4792 static void si_init_config(struct si_context
*sctx
)
4794 struct si_screen
*sscreen
= sctx
->screen
;
4795 uint64_t border_color_va
= sctx
->border_color_buffer
->gpu_address
;
4796 bool has_clear_state
= sscreen
->has_clear_state
;
4797 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
4799 /* Only SI can disable CLEAR_STATE for now. */
4800 assert(has_clear_state
|| sscreen
->b
.chip_class
== SI
);
4805 si_pm4_cmd_begin(pm4
, PKT3_CONTEXT_CONTROL
);
4806 si_pm4_cmd_add(pm4
, CONTEXT_CONTROL_LOAD_ENABLE(1));
4807 si_pm4_cmd_add(pm4
, CONTEXT_CONTROL_SHADOW_ENABLE(1));
4808 si_pm4_cmd_end(pm4
, false);
4810 if (has_clear_state
) {
4811 si_pm4_cmd_begin(pm4
, PKT3_CLEAR_STATE
);
4812 si_pm4_cmd_add(pm4
, 0);
4813 si_pm4_cmd_end(pm4
, false);
4816 if (sctx
->b
.chip_class
<= VI
)
4817 si_set_raster_config(sctx
, pm4
);
4819 si_pm4_set_reg(pm4
, R_028A18_VGT_HOS_MAX_TESS_LEVEL
, fui(64));
4820 if (!has_clear_state
)
4821 si_pm4_set_reg(pm4
, R_028A1C_VGT_HOS_MIN_TESS_LEVEL
, fui(0));
4823 /* FIXME calculate these values somehow ??? */
4824 if (sctx
->b
.chip_class
<= VI
) {
4825 si_pm4_set_reg(pm4
, R_028A54_VGT_GS_PER_ES
, SI_GS_PER_ES
);
4826 si_pm4_set_reg(pm4
, R_028A58_VGT_ES_PER_GS
, 0x40);
4829 if (!has_clear_state
) {
4830 si_pm4_set_reg(pm4
, R_028A5C_VGT_GS_PER_VS
, 0x2);
4831 si_pm4_set_reg(pm4
, R_028A8C_VGT_PRIMITIVEID_RESET
, 0x0);
4832 si_pm4_set_reg(pm4
, R_028B98_VGT_STRMOUT_BUFFER_CONFIG
, 0x0);
4835 si_pm4_set_reg(pm4
, R_028AA0_VGT_INSTANCE_STEP_RATE_0
, 1);
4836 if (!has_clear_state
)
4837 si_pm4_set_reg(pm4
, R_028AB8_VGT_VTX_CNT_EN
, 0x0);
4838 if (sctx
->b
.chip_class
< CIK
)
4839 si_pm4_set_reg(pm4
, R_008A14_PA_CL_ENHANCE
, S_008A14_NUM_CLIP_SEQ(3) |
4840 S_008A14_CLIP_VTX_REORDER_ENA(1));
4842 si_pm4_set_reg(pm4
, R_028BD4_PA_SC_CENTROID_PRIORITY_0
, 0x76543210);
4843 si_pm4_set_reg(pm4
, R_028BD8_PA_SC_CENTROID_PRIORITY_1
, 0xfedcba98);
4845 if (!has_clear_state
)
4846 si_pm4_set_reg(pm4
, R_02882C_PA_SU_PRIM_FILTER_CNTL
, 0);
4848 /* CLEAR_STATE doesn't clear these correctly on certain generations.
4849 * I don't know why. Deduced by trial and error.
4851 if (sctx
->b
.chip_class
<= CIK
) {
4852 si_pm4_set_reg(pm4
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
4853 si_pm4_set_reg(pm4
, R_028204_PA_SC_WINDOW_SCISSOR_TL
, S_028204_WINDOW_OFFSET_DISABLE(1));
4854 si_pm4_set_reg(pm4
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, S_028240_WINDOW_OFFSET_DISABLE(1));
4855 si_pm4_set_reg(pm4
, R_028244_PA_SC_GENERIC_SCISSOR_BR
,
4856 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
4857 si_pm4_set_reg(pm4
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 0);
4858 si_pm4_set_reg(pm4
, R_028034_PA_SC_SCREEN_SCISSOR_BR
,
4859 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
4862 if (!has_clear_state
) {
4863 si_pm4_set_reg(pm4
, R_02820C_PA_SC_CLIPRECT_RULE
, 0xFFFF);
4864 si_pm4_set_reg(pm4
, R_028230_PA_SC_EDGERULE
,
4865 S_028230_ER_TRI(0xA) |
4866 S_028230_ER_POINT(0xA) |
4867 S_028230_ER_RECT(0xA) |
4868 /* Required by DX10_DIAMOND_TEST_ENA: */
4869 S_028230_ER_LINE_LR(0x1A) |
4870 S_028230_ER_LINE_RL(0x26) |
4871 S_028230_ER_LINE_TB(0xA) |
4872 S_028230_ER_LINE_BT(0xA));
4873 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
4874 si_pm4_set_reg(pm4
, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET
, 0);
4875 si_pm4_set_reg(pm4
, R_028820_PA_CL_NANINF_CNTL
, 0);
4876 si_pm4_set_reg(pm4
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 0x0);
4877 si_pm4_set_reg(pm4
, R_028AC4_DB_SRESULTS_COMPARE_STATE1
, 0x0);
4878 si_pm4_set_reg(pm4
, R_028AC8_DB_PRELOAD_CONTROL
, 0x0);
4879 si_pm4_set_reg(pm4
, R_02800C_DB_RENDER_OVERRIDE
, 0);
4882 if (sctx
->b
.chip_class
>= GFX9
) {
4883 si_pm4_set_reg(pm4
, R_030920_VGT_MAX_VTX_INDX
, ~0);
4884 si_pm4_set_reg(pm4
, R_030924_VGT_MIN_VTX_INDX
, 0);
4885 si_pm4_set_reg(pm4
, R_030928_VGT_INDX_OFFSET
, 0);
4887 /* These registers, when written, also overwrite the CLEAR_STATE
4888 * context, so we can't rely on CLEAR_STATE setting them.
4889 * It would be an issue if there was another UMD changing them.
4891 si_pm4_set_reg(pm4
, R_028400_VGT_MAX_VTX_INDX
, ~0);
4892 si_pm4_set_reg(pm4
, R_028404_VGT_MIN_VTX_INDX
, 0);
4893 si_pm4_set_reg(pm4
, R_028408_VGT_INDX_OFFSET
, 0);
4896 if (sctx
->b
.chip_class
>= CIK
) {
4897 if (sctx
->b
.chip_class
>= GFX9
) {
4898 si_pm4_set_reg(pm4
, R_00B41C_SPI_SHADER_PGM_RSRC3_HS
, S_00B41C_CU_EN(0xffff));
4900 si_pm4_set_reg(pm4
, R_00B51C_SPI_SHADER_PGM_RSRC3_LS
, S_00B51C_CU_EN(0xffff));
4901 si_pm4_set_reg(pm4
, R_00B41C_SPI_SHADER_PGM_RSRC3_HS
, 0);
4902 si_pm4_set_reg(pm4
, R_00B31C_SPI_SHADER_PGM_RSRC3_ES
, S_00B31C_CU_EN(0xffff));
4904 /* If this is 0, Bonaire can hang even if GS isn't being used.
4905 * Other chips are unaffected. These are suboptimal values,
4906 * but we don't use on-chip GS.
4908 si_pm4_set_reg(pm4
, R_028A44_VGT_GS_ONCHIP_CNTL
,
4909 S_028A44_ES_VERTS_PER_SUBGRP(64) |
4910 S_028A44_GS_PRIMS_PER_SUBGRP(4));
4912 si_pm4_set_reg(pm4
, R_00B21C_SPI_SHADER_PGM_RSRC3_GS
, S_00B21C_CU_EN(0xffff));
4914 /* Compute LATE_ALLOC_VS.LIMIT. */
4915 unsigned num_cu_per_sh
= sscreen
->b
.info
.num_good_compute_units
/
4916 (sscreen
->b
.info
.max_se
*
4917 sscreen
->b
.info
.max_sh_per_se
);
4918 unsigned late_alloc_limit
; /* The limit is per SH. */
4920 if (sctx
->b
.family
== CHIP_KABINI
) {
4921 late_alloc_limit
= 0; /* Potential hang on Kabini. */
4922 } else if (num_cu_per_sh
<= 4) {
4923 /* Too few available compute units per SH. Disallowing
4924 * VS to run on one CU could hurt us more than late VS
4925 * allocation would help.
4927 * 2 is the highest safe number that allows us to keep
4930 late_alloc_limit
= 2;
4932 /* This is a good initial value, allowing 1 late_alloc
4933 * wave per SIMD on num_cu - 2.
4935 late_alloc_limit
= (num_cu_per_sh
- 2) * 4;
4937 /* The limit is 0-based, so 0 means 1. */
4938 assert(late_alloc_limit
> 0 && late_alloc_limit
<= 64);
4939 late_alloc_limit
-= 1;
4942 /* VS can't execute on one CU if the limit is > 2. */
4943 si_pm4_set_reg(pm4
, R_00B118_SPI_SHADER_PGM_RSRC3_VS
,
4944 S_00B118_CU_EN(late_alloc_limit
> 2 ? 0xfffe : 0xffff));
4945 si_pm4_set_reg(pm4
, R_00B11C_SPI_SHADER_LATE_ALLOC_VS
,
4946 S_00B11C_LIMIT(late_alloc_limit
));
4947 si_pm4_set_reg(pm4
, R_00B01C_SPI_SHADER_PGM_RSRC3_PS
, S_00B01C_CU_EN(0xffff));
4950 if (sctx
->b
.chip_class
>= VI
) {
4951 unsigned vgt_tess_distribution
;
4953 si_pm4_set_reg(pm4
, R_028424_CB_DCC_CONTROL
,
4954 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
4955 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
4957 vgt_tess_distribution
=
4958 S_028B50_ACCUM_ISOLINE(32) |
4959 S_028B50_ACCUM_TRI(11) |
4960 S_028B50_ACCUM_QUAD(11) |
4961 S_028B50_DONUT_SPLIT(16);
4963 /* Testing with Unigine Heaven extreme tesselation yielded best results
4964 * with TRAP_SPLIT = 3.
4966 if (sctx
->b
.family
== CHIP_FIJI
||
4967 sctx
->b
.family
>= CHIP_POLARIS10
)
4968 vgt_tess_distribution
|= S_028B50_TRAP_SPLIT(3);
4970 si_pm4_set_reg(pm4
, R_028B50_VGT_TESS_DISTRIBUTION
, vgt_tess_distribution
);
4971 } else if (!has_clear_state
) {
4972 si_pm4_set_reg(pm4
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
, 14);
4973 si_pm4_set_reg(pm4
, R_028C5C_VGT_OUT_DEALLOC_CNTL
, 16);
4976 si_pm4_set_reg(pm4
, R_028080_TA_BC_BASE_ADDR
, border_color_va
>> 8);
4977 if (sctx
->b
.chip_class
>= CIK
)
4978 si_pm4_set_reg(pm4
, R_028084_TA_BC_BASE_ADDR_HI
, border_color_va
>> 40);
4979 si_pm4_add_bo(pm4
, sctx
->border_color_buffer
, RADEON_USAGE_READ
,
4980 RADEON_PRIO_BORDER_COLORS
);
4982 if (sctx
->b
.chip_class
>= GFX9
) {
4983 unsigned num_se
= sscreen
->b
.info
.max_se
;
4984 unsigned pc_lines
= 0;
4986 switch (sctx
->b
.family
) {
4997 si_pm4_set_reg(pm4
, R_028C48_PA_SC_BINNER_CNTL_1
,
4998 S_028C48_MAX_ALLOC_COUNT(MIN2(128, pc_lines
/ (4 * num_se
))) |
4999 S_028C48_MAX_PRIM_PER_BATCH(1023));
5000 si_pm4_set_reg(pm4
, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
,
5001 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
5002 si_pm4_set_reg(pm4
, R_030968_VGT_INSTANCE_BASE_ID
, 0);
5005 si_pm4_upload_indirect_buffer(sctx
, pm4
);
5006 sctx
->init_config
= pm4
;