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radeonsi: reject some 3-component formats as buffer textures
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "sid.h"
29 #include "radeon/r600_cs.h"
30 #include "radeon/r600_query.h"
31
32 #include "util/u_dual_blend.h"
33 #include "util/u_format.h"
34 #include "util/u_format_s3tc.h"
35 #include "util/u_memory.h"
36 #include "util/u_resource.h"
37
38 /* Initialize an external atom (owned by ../radeon). */
39 static void
40 si_init_external_atom(struct si_context *sctx, struct r600_atom *atom,
41 struct r600_atom **list_elem)
42 {
43 atom->id = list_elem - sctx->atoms.array + 1;
44 *list_elem = atom;
45 }
46
47 /* Initialize an atom owned by radeonsi. */
48 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
49 struct r600_atom **list_elem,
50 void (*emit_func)(struct si_context *ctx, struct r600_atom *state))
51 {
52 atom->emit = (void*)emit_func;
53 atom->id = list_elem - sctx->atoms.array + 1; /* index+1 in the atom array */
54 *list_elem = atom;
55 }
56
57 static unsigned si_map_swizzle(unsigned swizzle)
58 {
59 switch (swizzle) {
60 case PIPE_SWIZZLE_Y:
61 return V_008F0C_SQ_SEL_Y;
62 case PIPE_SWIZZLE_Z:
63 return V_008F0C_SQ_SEL_Z;
64 case PIPE_SWIZZLE_W:
65 return V_008F0C_SQ_SEL_W;
66 case PIPE_SWIZZLE_0:
67 return V_008F0C_SQ_SEL_0;
68 case PIPE_SWIZZLE_1:
69 return V_008F0C_SQ_SEL_1;
70 default: /* PIPE_SWIZZLE_X */
71 return V_008F0C_SQ_SEL_X;
72 }
73 }
74
75 static uint32_t S_FIXED(float value, uint32_t frac_bits)
76 {
77 return value * (1 << frac_bits);
78 }
79
80 /* 12.4 fixed-point */
81 static unsigned si_pack_float_12p4(float x)
82 {
83 return x <= 0 ? 0 :
84 x >= 4096 ? 0xffff : x * 16;
85 }
86
87 /*
88 * Inferred framebuffer and blender state.
89 *
90 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
91 * if there is not enough PS outputs.
92 */
93 static void si_emit_cb_render_state(struct si_context *sctx, struct r600_atom *atom)
94 {
95 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
96 struct si_state_blend *blend = sctx->queued.named.blend;
97 uint32_t cb_target_mask, i;
98
99 /* CB_COLORn_INFO.FORMAT=INVALID disables empty colorbuffer slots. */
100 if (blend)
101 cb_target_mask = blend->cb_target_mask;
102 else
103 cb_target_mask = 0xffffffff;
104
105 /* Avoid a hang that happens when dual source blending is enabled
106 * but there is not enough color outputs. This is undefined behavior,
107 * so disable color writes completely.
108 *
109 * Reproducible with Unigine Heaven 4.0 and drirc missing.
110 */
111 if (blend && blend->dual_src_blend &&
112 sctx->ps_shader.cso &&
113 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
114 cb_target_mask = 0;
115
116 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, cb_target_mask);
117
118 /* STONEY-specific register settings. */
119 if (sctx->b.family == CHIP_STONEY) {
120 unsigned spi_shader_col_format =
121 sctx->ps_shader.cso ?
122 sctx->ps_shader.current->key.ps.epilog.spi_shader_col_format : 0;
123 unsigned sx_ps_downconvert = 0;
124 unsigned sx_blend_opt_epsilon = 0;
125 unsigned sx_blend_opt_control = 0;
126
127 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
128 struct r600_surface *surf =
129 (struct r600_surface*)sctx->framebuffer.state.cbufs[i];
130 unsigned format, swap, spi_format, colormask;
131 bool has_alpha, has_rgb;
132
133 if (!surf)
134 continue;
135
136 format = G_028C70_FORMAT(surf->cb_color_info);
137 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
138 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
139 colormask = (cb_target_mask >> (i * 4)) & 0xf;
140
141 /* Set if RGB and A are present. */
142 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
143
144 if (format == V_028C70_COLOR_8 ||
145 format == V_028C70_COLOR_16 ||
146 format == V_028C70_COLOR_32)
147 has_rgb = !has_alpha;
148 else
149 has_rgb = true;
150
151 /* Check the colormask and export format. */
152 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
153 has_rgb = false;
154 if (!(colormask & PIPE_MASK_A))
155 has_alpha = false;
156
157 if (spi_format == V_028714_SPI_SHADER_ZERO) {
158 has_rgb = false;
159 has_alpha = false;
160 }
161
162 /* Disable value checking for disabled channels. */
163 if (!has_rgb)
164 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
165 if (!has_alpha)
166 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
167
168 /* Enable down-conversion for 32bpp and smaller formats. */
169 switch (format) {
170 case V_028C70_COLOR_8:
171 case V_028C70_COLOR_8_8:
172 case V_028C70_COLOR_8_8_8_8:
173 /* For 1 and 2-channel formats, use the superset thereof. */
174 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
175 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
176 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
177 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
178 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
179 }
180 break;
181
182 case V_028C70_COLOR_5_6_5:
183 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
184 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
185 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
186 }
187 break;
188
189 case V_028C70_COLOR_1_5_5_5:
190 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
191 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
192 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
193 }
194 break;
195
196 case V_028C70_COLOR_4_4_4_4:
197 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
198 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
199 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
200 }
201 break;
202
203 case V_028C70_COLOR_32:
204 if (swap == V_0280A0_SWAP_STD &&
205 spi_format == V_028714_SPI_SHADER_32_R)
206 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
207 else if (swap == V_0280A0_SWAP_ALT_REV &&
208 spi_format == V_028714_SPI_SHADER_32_AR)
209 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
210 break;
211
212 case V_028C70_COLOR_16:
213 case V_028C70_COLOR_16_16:
214 /* For 1-channel formats, use the superset thereof. */
215 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
216 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
217 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
218 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
219 if (swap == V_0280A0_SWAP_STD ||
220 swap == V_0280A0_SWAP_STD_REV)
221 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
222 else
223 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
224 }
225 break;
226
227 case V_028C70_COLOR_10_11_11:
228 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
229 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
230 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
231 }
232 break;
233
234 case V_028C70_COLOR_2_10_10_10:
235 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
236 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
237 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
238 }
239 break;
240 }
241 }
242
243 if (sctx->screen->b.debug_flags & DBG_NO_RB_PLUS) {
244 sx_ps_downconvert = 0;
245 sx_blend_opt_epsilon = 0;
246 sx_blend_opt_control = 0;
247 }
248
249 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
250 radeon_emit(cs, sx_ps_downconvert); /* R_028754_SX_PS_DOWNCONVERT */
251 radeon_emit(cs, sx_blend_opt_epsilon); /* R_028758_SX_BLEND_OPT_EPSILON */
252 radeon_emit(cs, sx_blend_opt_control); /* R_02875C_SX_BLEND_OPT_CONTROL */
253 }
254 }
255
256 /*
257 * Blender functions
258 */
259
260 static uint32_t si_translate_blend_function(int blend_func)
261 {
262 switch (blend_func) {
263 case PIPE_BLEND_ADD:
264 return V_028780_COMB_DST_PLUS_SRC;
265 case PIPE_BLEND_SUBTRACT:
266 return V_028780_COMB_SRC_MINUS_DST;
267 case PIPE_BLEND_REVERSE_SUBTRACT:
268 return V_028780_COMB_DST_MINUS_SRC;
269 case PIPE_BLEND_MIN:
270 return V_028780_COMB_MIN_DST_SRC;
271 case PIPE_BLEND_MAX:
272 return V_028780_COMB_MAX_DST_SRC;
273 default:
274 R600_ERR("Unknown blend function %d\n", blend_func);
275 assert(0);
276 break;
277 }
278 return 0;
279 }
280
281 static uint32_t si_translate_blend_factor(int blend_fact)
282 {
283 switch (blend_fact) {
284 case PIPE_BLENDFACTOR_ONE:
285 return V_028780_BLEND_ONE;
286 case PIPE_BLENDFACTOR_SRC_COLOR:
287 return V_028780_BLEND_SRC_COLOR;
288 case PIPE_BLENDFACTOR_SRC_ALPHA:
289 return V_028780_BLEND_SRC_ALPHA;
290 case PIPE_BLENDFACTOR_DST_ALPHA:
291 return V_028780_BLEND_DST_ALPHA;
292 case PIPE_BLENDFACTOR_DST_COLOR:
293 return V_028780_BLEND_DST_COLOR;
294 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
295 return V_028780_BLEND_SRC_ALPHA_SATURATE;
296 case PIPE_BLENDFACTOR_CONST_COLOR:
297 return V_028780_BLEND_CONSTANT_COLOR;
298 case PIPE_BLENDFACTOR_CONST_ALPHA:
299 return V_028780_BLEND_CONSTANT_ALPHA;
300 case PIPE_BLENDFACTOR_ZERO:
301 return V_028780_BLEND_ZERO;
302 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
303 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
304 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
305 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
306 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
307 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
308 case PIPE_BLENDFACTOR_INV_DST_COLOR:
309 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
310 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
311 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
312 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
313 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
314 case PIPE_BLENDFACTOR_SRC1_COLOR:
315 return V_028780_BLEND_SRC1_COLOR;
316 case PIPE_BLENDFACTOR_SRC1_ALPHA:
317 return V_028780_BLEND_SRC1_ALPHA;
318 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
319 return V_028780_BLEND_INV_SRC1_COLOR;
320 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
321 return V_028780_BLEND_INV_SRC1_ALPHA;
322 default:
323 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
324 assert(0);
325 break;
326 }
327 return 0;
328 }
329
330 static uint32_t si_translate_blend_opt_function(int blend_func)
331 {
332 switch (blend_func) {
333 case PIPE_BLEND_ADD:
334 return V_028760_OPT_COMB_ADD;
335 case PIPE_BLEND_SUBTRACT:
336 return V_028760_OPT_COMB_SUBTRACT;
337 case PIPE_BLEND_REVERSE_SUBTRACT:
338 return V_028760_OPT_COMB_REVSUBTRACT;
339 case PIPE_BLEND_MIN:
340 return V_028760_OPT_COMB_MIN;
341 case PIPE_BLEND_MAX:
342 return V_028760_OPT_COMB_MAX;
343 default:
344 return V_028760_OPT_COMB_BLEND_DISABLED;
345 }
346 }
347
348 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
349 {
350 switch (blend_fact) {
351 case PIPE_BLENDFACTOR_ZERO:
352 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
353 case PIPE_BLENDFACTOR_ONE:
354 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
355 case PIPE_BLENDFACTOR_SRC_COLOR:
356 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
357 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
358 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
359 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
360 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
361 case PIPE_BLENDFACTOR_SRC_ALPHA:
362 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
363 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
364 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
365 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
366 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
367 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
368 default:
369 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
370 }
371 }
372
373 /**
374 * Get rid of DST in the blend factors by commuting the operands:
375 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
376 */
377 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
378 unsigned *dst_factor, unsigned expected_dst,
379 unsigned replacement_src)
380 {
381 if (*src_factor == expected_dst &&
382 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
383 *src_factor = PIPE_BLENDFACTOR_ZERO;
384 *dst_factor = replacement_src;
385
386 /* Commuting the operands requires reversing subtractions. */
387 if (*func == PIPE_BLEND_SUBTRACT)
388 *func = PIPE_BLEND_REVERSE_SUBTRACT;
389 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
390 *func = PIPE_BLEND_SUBTRACT;
391 }
392 }
393
394 static bool si_blend_factor_uses_dst(unsigned factor)
395 {
396 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
397 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
398 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
399 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
400 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
401 }
402
403 static void *si_create_blend_state_mode(struct pipe_context *ctx,
404 const struct pipe_blend_state *state,
405 unsigned mode)
406 {
407 struct si_context *sctx = (struct si_context*)ctx;
408 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
409 struct si_pm4_state *pm4 = &blend->pm4;
410 uint32_t sx_mrt_blend_opt[8] = {0};
411 uint32_t color_control = 0;
412
413 if (!blend)
414 return NULL;
415
416 blend->alpha_to_coverage = state->alpha_to_coverage;
417 blend->alpha_to_one = state->alpha_to_one;
418 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
419
420 if (state->logicop_enable) {
421 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
422 } else {
423 color_control |= S_028808_ROP3(0xcc);
424 }
425
426 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
427 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
428 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
429 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
430 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
431 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
432
433 if (state->alpha_to_coverage)
434 blend->need_src_alpha_4bit |= 0xf;
435
436 blend->cb_target_mask = 0;
437 for (int i = 0; i < 8; i++) {
438 /* state->rt entries > 0 only written if independent blending */
439 const int j = state->independent_blend_enable ? i : 0;
440
441 unsigned eqRGB = state->rt[j].rgb_func;
442 unsigned srcRGB = state->rt[j].rgb_src_factor;
443 unsigned dstRGB = state->rt[j].rgb_dst_factor;
444 unsigned eqA = state->rt[j].alpha_func;
445 unsigned srcA = state->rt[j].alpha_src_factor;
446 unsigned dstA = state->rt[j].alpha_dst_factor;
447
448 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
449 unsigned blend_cntl = 0;
450
451 sx_mrt_blend_opt[i] =
452 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
453 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
454
455 /* Only set dual source blending for MRT0 to avoid a hang. */
456 if (i >= 1 && blend->dual_src_blend)
457 continue;
458
459 /* Only addition and subtraction equations are supported with
460 * dual source blending.
461 */
462 if (blend->dual_src_blend &&
463 (eqRGB == PIPE_BLEND_MIN || eqRGB == PIPE_BLEND_MAX ||
464 eqA == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MAX)) {
465 assert(!"Unsupported equation for dual source blending");
466 continue;
467 }
468
469 if (!state->rt[j].colormask)
470 continue;
471
472 /* cb_render_state will disable unused ones */
473 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
474
475 if (!state->rt[j].blend_enable) {
476 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
477 continue;
478 }
479
480 /* Blending optimizations for Stoney.
481 * These transformations don't change the behavior.
482 *
483 * First, get rid of DST in the blend factors:
484 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
485 */
486 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
487 PIPE_BLENDFACTOR_DST_COLOR,
488 PIPE_BLENDFACTOR_SRC_COLOR);
489 si_blend_remove_dst(&eqA, &srcA, &dstA,
490 PIPE_BLENDFACTOR_DST_COLOR,
491 PIPE_BLENDFACTOR_SRC_COLOR);
492 si_blend_remove_dst(&eqA, &srcA, &dstA,
493 PIPE_BLENDFACTOR_DST_ALPHA,
494 PIPE_BLENDFACTOR_SRC_ALPHA);
495
496 /* Look up the ideal settings from tables. */
497 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
498 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
499 srcA_opt = si_translate_blend_opt_factor(srcA, true);
500 dstA_opt = si_translate_blend_opt_factor(dstA, true);
501
502 /* Handle interdependencies. */
503 if (si_blend_factor_uses_dst(srcRGB))
504 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
505 if (si_blend_factor_uses_dst(srcA))
506 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
507
508 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
509 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
510 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
511 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
512 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
513
514 /* Set the final value. */
515 sx_mrt_blend_opt[i] =
516 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
517 S_028760_COLOR_DST_OPT(dstRGB_opt) |
518 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
519 S_028760_ALPHA_SRC_OPT(srcA_opt) |
520 S_028760_ALPHA_DST_OPT(dstA_opt) |
521 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
522
523 /* Set blend state. */
524 blend_cntl |= S_028780_ENABLE(1);
525 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
526 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
527 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
528
529 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
530 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
531 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
532 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
533 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
534 }
535 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
536
537 blend->blend_enable_4bit |= 0xfu << (i * 4);
538
539 /* This is only important for formats without alpha. */
540 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
541 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
542 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
543 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
544 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
545 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
546 blend->need_src_alpha_4bit |= 0xfu << (i * 4);
547 }
548
549 if (blend->cb_target_mask) {
550 color_control |= S_028808_MODE(mode);
551 } else {
552 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
553 }
554
555 if (sctx->b.family == CHIP_STONEY) {
556 for (int i = 0; i < 8; i++)
557 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
558 sx_mrt_blend_opt[i]);
559
560 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
561 if (blend->dual_src_blend || state->logicop_enable ||
562 mode == V_028808_CB_RESOLVE)
563 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
564 }
565
566 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
567 return blend;
568 }
569
570 static void *si_create_blend_state(struct pipe_context *ctx,
571 const struct pipe_blend_state *state)
572 {
573 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
574 }
575
576 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
577 {
578 struct si_context *sctx = (struct si_context *)ctx;
579 si_pm4_bind_state(sctx, blend, (struct si_state_blend *)state);
580 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
581 sctx->do_update_shaders = true;
582 }
583
584 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
585 {
586 struct si_context *sctx = (struct si_context *)ctx;
587 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
588 }
589
590 static void si_set_blend_color(struct pipe_context *ctx,
591 const struct pipe_blend_color *state)
592 {
593 struct si_context *sctx = (struct si_context *)ctx;
594
595 if (memcmp(&sctx->blend_color.state, state, sizeof(*state)) == 0)
596 return;
597
598 sctx->blend_color.state = *state;
599 si_mark_atom_dirty(sctx, &sctx->blend_color.atom);
600 }
601
602 static void si_emit_blend_color(struct si_context *sctx, struct r600_atom *atom)
603 {
604 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
605
606 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
607 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
608 }
609
610 /*
611 * Clipping
612 */
613
614 static void si_set_clip_state(struct pipe_context *ctx,
615 const struct pipe_clip_state *state)
616 {
617 struct si_context *sctx = (struct si_context *)ctx;
618 struct pipe_constant_buffer cb;
619
620 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
621 return;
622
623 sctx->clip_state.state = *state;
624 si_mark_atom_dirty(sctx, &sctx->clip_state.atom);
625
626 cb.buffer = NULL;
627 cb.user_buffer = state->ucp;
628 cb.buffer_offset = 0;
629 cb.buffer_size = 4*4*8;
630 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
631 pipe_resource_reference(&cb.buffer, NULL);
632 }
633
634 static void si_emit_clip_state(struct si_context *sctx, struct r600_atom *atom)
635 {
636 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
637
638 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
639 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
640 }
641
642 #define SIX_BITS 0x3F
643
644 static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom)
645 {
646 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
647 struct tgsi_shader_info *info = si_get_vs_info(sctx);
648 unsigned window_space =
649 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
650 unsigned clipdist_mask =
651 info->writes_clipvertex ? SIX_BITS : info->clipdist_writemask;
652 unsigned total_mask = clipdist_mask | (info->culldist_writemask << info->num_written_clipdistance);
653
654 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
655 S_02881C_USE_VTX_POINT_SIZE(info->writes_psize) |
656 S_02881C_USE_VTX_EDGE_FLAG(info->writes_edgeflag) |
657 S_02881C_USE_VTX_RENDER_TARGET_INDX(info->writes_layer) |
658 S_02881C_USE_VTX_VIEWPORT_INDX(info->writes_viewport_index) |
659 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0F) != 0) |
660 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xF0) != 0) |
661 S_02881C_VS_OUT_MISC_VEC_ENA(info->writes_psize ||
662 info->writes_edgeflag ||
663 info->writes_layer ||
664 info->writes_viewport_index) |
665 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(1) |
666 (sctx->queued.named.rasterizer->clip_plane_enable &
667 clipdist_mask) | (info->culldist_writemask << 8));
668 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
669 sctx->queued.named.rasterizer->pa_cl_clip_cntl |
670 (clipdist_mask ? 0 :
671 sctx->queued.named.rasterizer->clip_plane_enable & SIX_BITS) |
672 S_028810_CLIP_DISABLE(window_space));
673
674 /* reuse needs to be set off if we write oViewport */
675 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF,
676 S_028AB4_REUSE_OFF(info->writes_viewport_index));
677 }
678
679 /*
680 * inferred state between framebuffer and rasterizer
681 */
682 static void si_update_poly_offset_state(struct si_context *sctx)
683 {
684 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
685
686 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf)
687 return;
688
689 /* Use the user format, not db_render_format, so that the polygon
690 * offset behaves as expected by applications.
691 */
692 switch (sctx->framebuffer.state.zsbuf->texture->format) {
693 case PIPE_FORMAT_Z16_UNORM:
694 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
695 break;
696 default: /* 24-bit */
697 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
698 break;
699 case PIPE_FORMAT_Z32_FLOAT:
700 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
701 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
702 break;
703 }
704 }
705
706 /*
707 * Rasterizer
708 */
709
710 static uint32_t si_translate_fill(uint32_t func)
711 {
712 switch(func) {
713 case PIPE_POLYGON_MODE_FILL:
714 return V_028814_X_DRAW_TRIANGLES;
715 case PIPE_POLYGON_MODE_LINE:
716 return V_028814_X_DRAW_LINES;
717 case PIPE_POLYGON_MODE_POINT:
718 return V_028814_X_DRAW_POINTS;
719 default:
720 assert(0);
721 return V_028814_X_DRAW_POINTS;
722 }
723 }
724
725 static void *si_create_rs_state(struct pipe_context *ctx,
726 const struct pipe_rasterizer_state *state)
727 {
728 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
729 struct si_pm4_state *pm4 = &rs->pm4;
730 unsigned tmp, i;
731 float psize_min, psize_max;
732
733 if (!rs) {
734 return NULL;
735 }
736
737 rs->scissor_enable = state->scissor;
738 rs->clip_halfz = state->clip_halfz;
739 rs->two_side = state->light_twoside;
740 rs->multisample_enable = state->multisample;
741 rs->force_persample_interp = state->force_persample_interp;
742 rs->clip_plane_enable = state->clip_plane_enable;
743 rs->line_stipple_enable = state->line_stipple_enable;
744 rs->poly_stipple_enable = state->poly_stipple_enable;
745 rs->line_smooth = state->line_smooth;
746 rs->poly_smooth = state->poly_smooth;
747 rs->uses_poly_offset = state->offset_point || state->offset_line ||
748 state->offset_tri;
749 rs->clamp_fragment_color = state->clamp_fragment_color;
750 rs->flatshade = state->flatshade;
751 rs->sprite_coord_enable = state->sprite_coord_enable;
752 rs->rasterizer_discard = state->rasterizer_discard;
753 rs->pa_sc_line_stipple = state->line_stipple_enable ?
754 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
755 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
756 rs->pa_cl_clip_cntl =
757 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
758 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
759 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
760 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
761 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
762
763 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
764 S_0286D4_FLAT_SHADE_ENA(1) |
765 S_0286D4_PNT_SPRITE_ENA(1) |
766 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
767 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
768 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
769 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
770 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
771
772 /* point size 12.4 fixed point */
773 tmp = (unsigned)(state->point_size * 8.0);
774 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
775
776 if (state->point_size_per_vertex) {
777 psize_min = util_get_min_point_size(state);
778 psize_max = 8192;
779 } else {
780 /* Force the point size to be as if the vertex output was disabled. */
781 psize_min = state->point_size;
782 psize_max = state->point_size;
783 }
784 /* Divide by two, because 0.5 = 1 pixel. */
785 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
786 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
787 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
788
789 tmp = (unsigned)state->line_width * 8;
790 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
791 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
792 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
793 S_028A48_MSAA_ENABLE(state->multisample ||
794 state->poly_smooth ||
795 state->line_smooth) |
796 S_028A48_VPORT_SCISSOR_ENABLE(1));
797
798 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
799 S_028BE4_PIX_CENTER(state->half_pixel_center) |
800 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
801
802 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
803 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
804 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
805 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
806 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
807 S_028814_FACE(!state->front_ccw) |
808 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
809 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
810 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
811 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
812 state->fill_back != PIPE_POLYGON_MODE_FILL) |
813 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
814 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
815 si_pm4_set_reg(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0 +
816 SI_SGPR_VS_STATE_BITS * 4, state->clamp_vertex_color);
817
818 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
819 for (i = 0; i < 3; i++) {
820 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
821 float offset_units = state->offset_units;
822 float offset_scale = state->offset_scale * 16.0f;
823 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
824
825 if (!state->offset_units_unscaled) {
826 switch (i) {
827 case 0: /* 16-bit zbuffer */
828 offset_units *= 4.0f;
829 pa_su_poly_offset_db_fmt_cntl =
830 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
831 break;
832 case 1: /* 24-bit zbuffer */
833 offset_units *= 2.0f;
834 pa_su_poly_offset_db_fmt_cntl =
835 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
836 break;
837 case 2: /* 32-bit zbuffer */
838 offset_units *= 1.0f;
839 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
840 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
841 break;
842 }
843 }
844
845 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
846 fui(offset_scale));
847 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
848 fui(offset_units));
849 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
850 fui(offset_scale));
851 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
852 fui(offset_units));
853 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
854 pa_su_poly_offset_db_fmt_cntl);
855 }
856
857 return rs;
858 }
859
860 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
861 {
862 struct si_context *sctx = (struct si_context *)ctx;
863 struct si_state_rasterizer *old_rs =
864 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
865 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
866
867 if (!state)
868 return;
869
870 if (sctx->framebuffer.nr_samples > 1 &&
871 (!old_rs || old_rs->multisample_enable != rs->multisample_enable)) {
872 si_mark_atom_dirty(sctx, &sctx->db_render_state);
873
874 if (sctx->b.family >= CHIP_POLARIS10)
875 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
876 }
877
878 r600_viewport_set_rast_deps(&sctx->b, rs->scissor_enable, rs->clip_halfz);
879
880 si_pm4_bind_state(sctx, rasterizer, rs);
881 si_update_poly_offset_state(sctx);
882
883 si_mark_atom_dirty(sctx, &sctx->clip_regs);
884 sctx->do_update_shaders = true;
885 }
886
887 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
888 {
889 struct si_context *sctx = (struct si_context *)ctx;
890
891 if (sctx->queued.named.rasterizer == state)
892 si_pm4_bind_state(sctx, poly_offset, NULL);
893 si_pm4_delete_state(sctx, rasterizer, (struct si_state_rasterizer *)state);
894 }
895
896 /*
897 * infeered state between dsa and stencil ref
898 */
899 static void si_emit_stencil_ref(struct si_context *sctx, struct r600_atom *atom)
900 {
901 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
902 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
903 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
904
905 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
906 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
907 S_028430_STENCILMASK(dsa->valuemask[0]) |
908 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
909 S_028430_STENCILOPVAL(1));
910 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
911 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
912 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
913 S_028434_STENCILOPVAL_BF(1));
914 }
915
916 static void si_set_stencil_ref(struct pipe_context *ctx,
917 const struct pipe_stencil_ref *state)
918 {
919 struct si_context *sctx = (struct si_context *)ctx;
920
921 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
922 return;
923
924 sctx->stencil_ref.state = *state;
925 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
926 }
927
928
929 /*
930 * DSA
931 */
932
933 static uint32_t si_translate_stencil_op(int s_op)
934 {
935 switch (s_op) {
936 case PIPE_STENCIL_OP_KEEP:
937 return V_02842C_STENCIL_KEEP;
938 case PIPE_STENCIL_OP_ZERO:
939 return V_02842C_STENCIL_ZERO;
940 case PIPE_STENCIL_OP_REPLACE:
941 return V_02842C_STENCIL_REPLACE_TEST;
942 case PIPE_STENCIL_OP_INCR:
943 return V_02842C_STENCIL_ADD_CLAMP;
944 case PIPE_STENCIL_OP_DECR:
945 return V_02842C_STENCIL_SUB_CLAMP;
946 case PIPE_STENCIL_OP_INCR_WRAP:
947 return V_02842C_STENCIL_ADD_WRAP;
948 case PIPE_STENCIL_OP_DECR_WRAP:
949 return V_02842C_STENCIL_SUB_WRAP;
950 case PIPE_STENCIL_OP_INVERT:
951 return V_02842C_STENCIL_INVERT;
952 default:
953 R600_ERR("Unknown stencil op %d", s_op);
954 assert(0);
955 break;
956 }
957 return 0;
958 }
959
960 static void *si_create_dsa_state(struct pipe_context *ctx,
961 const struct pipe_depth_stencil_alpha_state *state)
962 {
963 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
964 struct si_pm4_state *pm4 = &dsa->pm4;
965 unsigned db_depth_control;
966 uint32_t db_stencil_control = 0;
967
968 if (!dsa) {
969 return NULL;
970 }
971
972 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
973 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
974 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
975 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
976
977 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
978 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
979 S_028800_ZFUNC(state->depth.func) |
980 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
981
982 /* stencil */
983 if (state->stencil[0].enabled) {
984 db_depth_control |= S_028800_STENCIL_ENABLE(1);
985 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
986 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
987 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
988 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
989
990 if (state->stencil[1].enabled) {
991 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
992 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
993 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
994 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
995 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
996 }
997 }
998
999 /* alpha */
1000 if (state->alpha.enabled) {
1001 dsa->alpha_func = state->alpha.func;
1002
1003 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1004 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
1005 } else {
1006 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1007 }
1008
1009 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1010 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1011 if (state->depth.bounds_test) {
1012 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1013 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1014 }
1015
1016 return dsa;
1017 }
1018
1019 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1020 {
1021 struct si_context *sctx = (struct si_context *)ctx;
1022 struct si_state_dsa *dsa = state;
1023
1024 if (!state)
1025 return;
1026
1027 si_pm4_bind_state(sctx, dsa, dsa);
1028
1029 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1030 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1031 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1032 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1033 }
1034 sctx->do_update_shaders = true;
1035 }
1036
1037 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1038 {
1039 struct si_context *sctx = (struct si_context *)ctx;
1040 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1041 }
1042
1043 static void *si_create_db_flush_dsa(struct si_context *sctx)
1044 {
1045 struct pipe_depth_stencil_alpha_state dsa = {};
1046
1047 return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
1048 }
1049
1050 /* DB RENDER STATE */
1051
1052 static void si_set_active_query_state(struct pipe_context *ctx, boolean enable)
1053 {
1054 struct si_context *sctx = (struct si_context*)ctx;
1055
1056 /* Pipeline stat & streamout queries. */
1057 if (enable) {
1058 sctx->b.flags &= ~R600_CONTEXT_STOP_PIPELINE_STATS;
1059 sctx->b.flags |= R600_CONTEXT_START_PIPELINE_STATS;
1060 } else {
1061 sctx->b.flags &= ~R600_CONTEXT_START_PIPELINE_STATS;
1062 sctx->b.flags |= R600_CONTEXT_STOP_PIPELINE_STATS;
1063 }
1064
1065 /* Occlusion queries. */
1066 if (sctx->occlusion_queries_disabled != !enable) {
1067 sctx->occlusion_queries_disabled = !enable;
1068 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1069 }
1070 }
1071
1072 static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
1073 {
1074 struct si_context *sctx = (struct si_context*)ctx;
1075
1076 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1077 }
1078
1079 static void si_save_qbo_state(struct pipe_context *ctx, struct r600_qbo_state *st)
1080 {
1081 struct si_context *sctx = (struct si_context*)ctx;
1082
1083 st->saved_compute = sctx->cs_shader_state.program;
1084
1085 si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1086 si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
1087 }
1088
1089 static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
1090 {
1091 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1092 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1093 unsigned db_shader_control;
1094
1095 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1096
1097 /* DB_RENDER_CONTROL */
1098 if (sctx->dbcb_depth_copy_enabled ||
1099 sctx->dbcb_stencil_copy_enabled) {
1100 radeon_emit(cs,
1101 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1102 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1103 S_028000_COPY_CENTROID(1) |
1104 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
1105 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1106 radeon_emit(cs,
1107 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1108 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace));
1109 } else {
1110 radeon_emit(cs,
1111 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1112 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear));
1113 }
1114
1115 /* DB_COUNT_CONTROL (occlusion queries) */
1116 if (sctx->b.num_occlusion_queries > 0 &&
1117 !sctx->occlusion_queries_disabled) {
1118 bool perfect = sctx->b.num_perfect_occlusion_queries > 0;
1119
1120 if (sctx->b.chip_class >= CIK) {
1121 radeon_emit(cs,
1122 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1123 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
1124 S_028004_ZPASS_ENABLE(1) |
1125 S_028004_SLICE_EVEN_ENABLE(1) |
1126 S_028004_SLICE_ODD_ENABLE(1));
1127 } else {
1128 radeon_emit(cs,
1129 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1130 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
1131 }
1132 } else {
1133 /* Disable occlusion queries. */
1134 if (sctx->b.chip_class >= CIK) {
1135 radeon_emit(cs, 0);
1136 } else {
1137 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
1138 }
1139 }
1140
1141 /* DB_RENDER_OVERRIDE2 */
1142 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
1143 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1144 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1145 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4));
1146
1147 db_shader_control = sctx->ps_db_shader_control;
1148
1149 /* Bug workaround for smoothing (overrasterization) on SI. */
1150 if (sctx->b.chip_class == SI && sctx->smoothing_enabled) {
1151 db_shader_control &= C_02880C_Z_ORDER;
1152 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1153 }
1154
1155 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1156 if (sctx->framebuffer.nr_samples <= 1 || (rs && !rs->multisample_enable))
1157 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1158
1159 if (sctx->b.family == CHIP_STONEY &&
1160 sctx->screen->b.debug_flags & DBG_NO_RB_PLUS)
1161 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1162
1163 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
1164 db_shader_control);
1165 }
1166
1167 /*
1168 * format translation
1169 */
1170 static uint32_t si_translate_colorformat(enum pipe_format format)
1171 {
1172 const struct util_format_description *desc = util_format_description(format);
1173
1174 #define HAS_SIZE(x,y,z,w) \
1175 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1176 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1177
1178 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1179 return V_028C70_COLOR_10_11_11;
1180
1181 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1182 return V_028C70_COLOR_INVALID;
1183
1184 /* hw cannot support mixed formats (except depth/stencil, since
1185 * stencil is not written to). */
1186 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1187 return V_028C70_COLOR_INVALID;
1188
1189 switch (desc->nr_channels) {
1190 case 1:
1191 switch (desc->channel[0].size) {
1192 case 8:
1193 return V_028C70_COLOR_8;
1194 case 16:
1195 return V_028C70_COLOR_16;
1196 case 32:
1197 return V_028C70_COLOR_32;
1198 }
1199 break;
1200 case 2:
1201 if (desc->channel[0].size == desc->channel[1].size) {
1202 switch (desc->channel[0].size) {
1203 case 8:
1204 return V_028C70_COLOR_8_8;
1205 case 16:
1206 return V_028C70_COLOR_16_16;
1207 case 32:
1208 return V_028C70_COLOR_32_32;
1209 }
1210 } else if (HAS_SIZE(8,24,0,0)) {
1211 return V_028C70_COLOR_24_8;
1212 } else if (HAS_SIZE(24,8,0,0)) {
1213 return V_028C70_COLOR_8_24;
1214 }
1215 break;
1216 case 3:
1217 if (HAS_SIZE(5,6,5,0)) {
1218 return V_028C70_COLOR_5_6_5;
1219 } else if (HAS_SIZE(32,8,24,0)) {
1220 return V_028C70_COLOR_X24_8_32_FLOAT;
1221 }
1222 break;
1223 case 4:
1224 if (desc->channel[0].size == desc->channel[1].size &&
1225 desc->channel[0].size == desc->channel[2].size &&
1226 desc->channel[0].size == desc->channel[3].size) {
1227 switch (desc->channel[0].size) {
1228 case 4:
1229 return V_028C70_COLOR_4_4_4_4;
1230 case 8:
1231 return V_028C70_COLOR_8_8_8_8;
1232 case 16:
1233 return V_028C70_COLOR_16_16_16_16;
1234 case 32:
1235 return V_028C70_COLOR_32_32_32_32;
1236 }
1237 } else if (HAS_SIZE(5,5,5,1)) {
1238 return V_028C70_COLOR_1_5_5_5;
1239 } else if (HAS_SIZE(10,10,10,2)) {
1240 return V_028C70_COLOR_2_10_10_10;
1241 }
1242 break;
1243 }
1244 return V_028C70_COLOR_INVALID;
1245 }
1246
1247 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1248 {
1249 if (SI_BIG_ENDIAN) {
1250 switch(colorformat) {
1251 /* 8-bit buffers. */
1252 case V_028C70_COLOR_8:
1253 return V_028C70_ENDIAN_NONE;
1254
1255 /* 16-bit buffers. */
1256 case V_028C70_COLOR_5_6_5:
1257 case V_028C70_COLOR_1_5_5_5:
1258 case V_028C70_COLOR_4_4_4_4:
1259 case V_028C70_COLOR_16:
1260 case V_028C70_COLOR_8_8:
1261 return V_028C70_ENDIAN_8IN16;
1262
1263 /* 32-bit buffers. */
1264 case V_028C70_COLOR_8_8_8_8:
1265 case V_028C70_COLOR_2_10_10_10:
1266 case V_028C70_COLOR_8_24:
1267 case V_028C70_COLOR_24_8:
1268 case V_028C70_COLOR_16_16:
1269 return V_028C70_ENDIAN_8IN32;
1270
1271 /* 64-bit buffers. */
1272 case V_028C70_COLOR_16_16_16_16:
1273 return V_028C70_ENDIAN_8IN16;
1274
1275 case V_028C70_COLOR_32_32:
1276 return V_028C70_ENDIAN_8IN32;
1277
1278 /* 128-bit buffers. */
1279 case V_028C70_COLOR_32_32_32_32:
1280 return V_028C70_ENDIAN_8IN32;
1281 default:
1282 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1283 }
1284 } else {
1285 return V_028C70_ENDIAN_NONE;
1286 }
1287 }
1288
1289 static uint32_t si_translate_dbformat(enum pipe_format format)
1290 {
1291 switch (format) {
1292 case PIPE_FORMAT_Z16_UNORM:
1293 return V_028040_Z_16;
1294 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1295 case PIPE_FORMAT_X8Z24_UNORM:
1296 case PIPE_FORMAT_Z24X8_UNORM:
1297 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1298 return V_028040_Z_24; /* deprecated on SI */
1299 case PIPE_FORMAT_Z32_FLOAT:
1300 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1301 return V_028040_Z_32_FLOAT;
1302 default:
1303 return V_028040_Z_INVALID;
1304 }
1305 }
1306
1307 /*
1308 * Texture translation
1309 */
1310
1311 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1312 enum pipe_format format,
1313 const struct util_format_description *desc,
1314 int first_non_void)
1315 {
1316 struct si_screen *sscreen = (struct si_screen*)screen;
1317 bool enable_compressed_formats = (sscreen->b.info.drm_major == 2 &&
1318 sscreen->b.info.drm_minor >= 31) ||
1319 sscreen->b.info.drm_major == 3;
1320 bool uniform = true;
1321 int i;
1322
1323 /* Colorspace (return non-RGB formats directly). */
1324 switch (desc->colorspace) {
1325 /* Depth stencil formats */
1326 case UTIL_FORMAT_COLORSPACE_ZS:
1327 switch (format) {
1328 case PIPE_FORMAT_Z16_UNORM:
1329 return V_008F14_IMG_DATA_FORMAT_16;
1330 case PIPE_FORMAT_X24S8_UINT:
1331 case PIPE_FORMAT_Z24X8_UNORM:
1332 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1333 return V_008F14_IMG_DATA_FORMAT_8_24;
1334 case PIPE_FORMAT_X8Z24_UNORM:
1335 case PIPE_FORMAT_S8X24_UINT:
1336 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1337 return V_008F14_IMG_DATA_FORMAT_24_8;
1338 case PIPE_FORMAT_S8_UINT:
1339 return V_008F14_IMG_DATA_FORMAT_8;
1340 case PIPE_FORMAT_Z32_FLOAT:
1341 return V_008F14_IMG_DATA_FORMAT_32;
1342 case PIPE_FORMAT_X32_S8X24_UINT:
1343 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1344 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1345 default:
1346 goto out_unknown;
1347 }
1348
1349 case UTIL_FORMAT_COLORSPACE_YUV:
1350 goto out_unknown; /* TODO */
1351
1352 case UTIL_FORMAT_COLORSPACE_SRGB:
1353 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1354 goto out_unknown;
1355 break;
1356
1357 default:
1358 break;
1359 }
1360
1361 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1362 if (!enable_compressed_formats)
1363 goto out_unknown;
1364
1365 switch (format) {
1366 case PIPE_FORMAT_RGTC1_SNORM:
1367 case PIPE_FORMAT_LATC1_SNORM:
1368 case PIPE_FORMAT_RGTC1_UNORM:
1369 case PIPE_FORMAT_LATC1_UNORM:
1370 return V_008F14_IMG_DATA_FORMAT_BC4;
1371 case PIPE_FORMAT_RGTC2_SNORM:
1372 case PIPE_FORMAT_LATC2_SNORM:
1373 case PIPE_FORMAT_RGTC2_UNORM:
1374 case PIPE_FORMAT_LATC2_UNORM:
1375 return V_008F14_IMG_DATA_FORMAT_BC5;
1376 default:
1377 goto out_unknown;
1378 }
1379 }
1380
1381 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1382 sscreen->b.family == CHIP_STONEY) {
1383 switch (format) {
1384 case PIPE_FORMAT_ETC1_RGB8:
1385 case PIPE_FORMAT_ETC2_RGB8:
1386 case PIPE_FORMAT_ETC2_SRGB8:
1387 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1388 case PIPE_FORMAT_ETC2_RGB8A1:
1389 case PIPE_FORMAT_ETC2_SRGB8A1:
1390 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1391 case PIPE_FORMAT_ETC2_RGBA8:
1392 case PIPE_FORMAT_ETC2_SRGBA8:
1393 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1394 case PIPE_FORMAT_ETC2_R11_UNORM:
1395 case PIPE_FORMAT_ETC2_R11_SNORM:
1396 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1397 case PIPE_FORMAT_ETC2_RG11_UNORM:
1398 case PIPE_FORMAT_ETC2_RG11_SNORM:
1399 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1400 default:
1401 goto out_unknown;
1402 }
1403 }
1404
1405 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1406 if (!enable_compressed_formats)
1407 goto out_unknown;
1408
1409 switch (format) {
1410 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1411 case PIPE_FORMAT_BPTC_SRGBA:
1412 return V_008F14_IMG_DATA_FORMAT_BC7;
1413 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1414 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1415 return V_008F14_IMG_DATA_FORMAT_BC6;
1416 default:
1417 goto out_unknown;
1418 }
1419 }
1420
1421 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1422 switch (format) {
1423 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1424 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1425 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1426 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1427 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1428 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1429 default:
1430 goto out_unknown;
1431 }
1432 }
1433
1434 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1435 if (!enable_compressed_formats)
1436 goto out_unknown;
1437
1438 if (!util_format_s3tc_enabled) {
1439 goto out_unknown;
1440 }
1441
1442 switch (format) {
1443 case PIPE_FORMAT_DXT1_RGB:
1444 case PIPE_FORMAT_DXT1_RGBA:
1445 case PIPE_FORMAT_DXT1_SRGB:
1446 case PIPE_FORMAT_DXT1_SRGBA:
1447 return V_008F14_IMG_DATA_FORMAT_BC1;
1448 case PIPE_FORMAT_DXT3_RGBA:
1449 case PIPE_FORMAT_DXT3_SRGBA:
1450 return V_008F14_IMG_DATA_FORMAT_BC2;
1451 case PIPE_FORMAT_DXT5_RGBA:
1452 case PIPE_FORMAT_DXT5_SRGBA:
1453 return V_008F14_IMG_DATA_FORMAT_BC3;
1454 default:
1455 goto out_unknown;
1456 }
1457 }
1458
1459 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1460 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1461 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1462 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1463 }
1464
1465 /* R8G8Bx_SNORM - TODO CxV8U8 */
1466
1467 /* hw cannot support mixed formats (except depth/stencil, since only
1468 * depth is read).*/
1469 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1470 goto out_unknown;
1471
1472 /* See whether the components are of the same size. */
1473 for (i = 1; i < desc->nr_channels; i++) {
1474 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1475 }
1476
1477 /* Non-uniform formats. */
1478 if (!uniform) {
1479 switch(desc->nr_channels) {
1480 case 3:
1481 if (desc->channel[0].size == 5 &&
1482 desc->channel[1].size == 6 &&
1483 desc->channel[2].size == 5) {
1484 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1485 }
1486 goto out_unknown;
1487 case 4:
1488 if (desc->channel[0].size == 5 &&
1489 desc->channel[1].size == 5 &&
1490 desc->channel[2].size == 5 &&
1491 desc->channel[3].size == 1) {
1492 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1493 }
1494 if (desc->channel[0].size == 10 &&
1495 desc->channel[1].size == 10 &&
1496 desc->channel[2].size == 10 &&
1497 desc->channel[3].size == 2) {
1498 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1499 }
1500 goto out_unknown;
1501 }
1502 goto out_unknown;
1503 }
1504
1505 if (first_non_void < 0 || first_non_void > 3)
1506 goto out_unknown;
1507
1508 /* uniform formats */
1509 switch (desc->channel[first_non_void].size) {
1510 case 4:
1511 switch (desc->nr_channels) {
1512 #if 0 /* Not supported for render targets */
1513 case 2:
1514 return V_008F14_IMG_DATA_FORMAT_4_4;
1515 #endif
1516 case 4:
1517 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1518 }
1519 break;
1520 case 8:
1521 switch (desc->nr_channels) {
1522 case 1:
1523 return V_008F14_IMG_DATA_FORMAT_8;
1524 case 2:
1525 return V_008F14_IMG_DATA_FORMAT_8_8;
1526 case 4:
1527 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1528 }
1529 break;
1530 case 16:
1531 switch (desc->nr_channels) {
1532 case 1:
1533 return V_008F14_IMG_DATA_FORMAT_16;
1534 case 2:
1535 return V_008F14_IMG_DATA_FORMAT_16_16;
1536 case 4:
1537 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1538 }
1539 break;
1540 case 32:
1541 switch (desc->nr_channels) {
1542 case 1:
1543 return V_008F14_IMG_DATA_FORMAT_32;
1544 case 2:
1545 return V_008F14_IMG_DATA_FORMAT_32_32;
1546 #if 0 /* Not supported for render targets */
1547 case 3:
1548 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1549 #endif
1550 case 4:
1551 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1552 }
1553 }
1554
1555 out_unknown:
1556 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1557 return ~0;
1558 }
1559
1560 static unsigned si_tex_wrap(unsigned wrap)
1561 {
1562 switch (wrap) {
1563 default:
1564 case PIPE_TEX_WRAP_REPEAT:
1565 return V_008F30_SQ_TEX_WRAP;
1566 case PIPE_TEX_WRAP_CLAMP:
1567 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1568 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1569 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1570 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1571 return V_008F30_SQ_TEX_CLAMP_BORDER;
1572 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1573 return V_008F30_SQ_TEX_MIRROR;
1574 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1575 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1576 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1577 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1578 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1579 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1580 }
1581 }
1582
1583 static unsigned si_tex_mipfilter(unsigned filter)
1584 {
1585 switch (filter) {
1586 case PIPE_TEX_MIPFILTER_NEAREST:
1587 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1588 case PIPE_TEX_MIPFILTER_LINEAR:
1589 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1590 default:
1591 case PIPE_TEX_MIPFILTER_NONE:
1592 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1593 }
1594 }
1595
1596 static unsigned si_tex_compare(unsigned compare)
1597 {
1598 switch (compare) {
1599 default:
1600 case PIPE_FUNC_NEVER:
1601 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1602 case PIPE_FUNC_LESS:
1603 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1604 case PIPE_FUNC_EQUAL:
1605 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1606 case PIPE_FUNC_LEQUAL:
1607 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1608 case PIPE_FUNC_GREATER:
1609 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1610 case PIPE_FUNC_NOTEQUAL:
1611 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1612 case PIPE_FUNC_GEQUAL:
1613 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1614 case PIPE_FUNC_ALWAYS:
1615 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1616 }
1617 }
1618
1619 static unsigned si_tex_dim(unsigned res_target, unsigned view_target,
1620 unsigned nr_samples)
1621 {
1622 if (view_target == PIPE_TEXTURE_CUBE ||
1623 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1624 res_target = view_target;
1625 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1626 else if (res_target == PIPE_TEXTURE_CUBE ||
1627 res_target == PIPE_TEXTURE_CUBE_ARRAY)
1628 res_target = PIPE_TEXTURE_2D_ARRAY;
1629
1630 switch (res_target) {
1631 default:
1632 case PIPE_TEXTURE_1D:
1633 return V_008F1C_SQ_RSRC_IMG_1D;
1634 case PIPE_TEXTURE_1D_ARRAY:
1635 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1636 case PIPE_TEXTURE_2D:
1637 case PIPE_TEXTURE_RECT:
1638 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1639 V_008F1C_SQ_RSRC_IMG_2D;
1640 case PIPE_TEXTURE_2D_ARRAY:
1641 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1642 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1643 case PIPE_TEXTURE_3D:
1644 return V_008F1C_SQ_RSRC_IMG_3D;
1645 case PIPE_TEXTURE_CUBE:
1646 case PIPE_TEXTURE_CUBE_ARRAY:
1647 return V_008F1C_SQ_RSRC_IMG_CUBE;
1648 }
1649 }
1650
1651 /*
1652 * Format support testing
1653 */
1654
1655 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1656 {
1657 return si_translate_texformat(screen, format, util_format_description(format),
1658 util_format_get_first_non_void_channel(format)) != ~0U;
1659 }
1660
1661 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1662 const struct util_format_description *desc,
1663 int first_non_void)
1664 {
1665 unsigned type;
1666 int i;
1667
1668 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1669 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1670
1671 assert(first_non_void >= 0);
1672 type = desc->channel[first_non_void].type;
1673
1674 if (type == UTIL_FORMAT_TYPE_FIXED)
1675 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1676
1677 if (desc->nr_channels == 4 &&
1678 desc->channel[0].size == 10 &&
1679 desc->channel[1].size == 10 &&
1680 desc->channel[2].size == 10 &&
1681 desc->channel[3].size == 2)
1682 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1683
1684 /* See whether the components are of the same size. */
1685 for (i = 0; i < desc->nr_channels; i++) {
1686 if (desc->channel[first_non_void].size != desc->channel[i].size)
1687 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1688 }
1689
1690 switch (desc->channel[first_non_void].size) {
1691 case 8:
1692 switch (desc->nr_channels) {
1693 case 1:
1694 return V_008F0C_BUF_DATA_FORMAT_8;
1695 case 2:
1696 return V_008F0C_BUF_DATA_FORMAT_8_8;
1697 case 3:
1698 case 4:
1699 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1700 }
1701 break;
1702 case 16:
1703 switch (desc->nr_channels) {
1704 case 1:
1705 return V_008F0C_BUF_DATA_FORMAT_16;
1706 case 2:
1707 return V_008F0C_BUF_DATA_FORMAT_16_16;
1708 case 3:
1709 case 4:
1710 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1711 }
1712 break;
1713 case 32:
1714 /* From the Southern Islands ISA documentation about MTBUF:
1715 * 'Memory reads of data in memory that is 32 or 64 bits do not
1716 * undergo any format conversion.'
1717 */
1718 if (type != UTIL_FORMAT_TYPE_FLOAT &&
1719 !desc->channel[first_non_void].pure_integer)
1720 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1721
1722 switch (desc->nr_channels) {
1723 case 1:
1724 return V_008F0C_BUF_DATA_FORMAT_32;
1725 case 2:
1726 return V_008F0C_BUF_DATA_FORMAT_32_32;
1727 case 3:
1728 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1729 case 4:
1730 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1731 }
1732 break;
1733 }
1734
1735 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1736 }
1737
1738 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1739 const struct util_format_description *desc,
1740 int first_non_void)
1741 {
1742 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1743 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1744
1745 assert(first_non_void >= 0);
1746
1747 switch (desc->channel[first_non_void].type) {
1748 case UTIL_FORMAT_TYPE_SIGNED:
1749 if (desc->channel[first_non_void].normalized)
1750 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1751 else if (desc->channel[first_non_void].pure_integer)
1752 return V_008F0C_BUF_NUM_FORMAT_SINT;
1753 else
1754 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1755 break;
1756 case UTIL_FORMAT_TYPE_UNSIGNED:
1757 if (desc->channel[first_non_void].normalized)
1758 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1759 else if (desc->channel[first_non_void].pure_integer)
1760 return V_008F0C_BUF_NUM_FORMAT_UINT;
1761 else
1762 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1763 break;
1764 case UTIL_FORMAT_TYPE_FLOAT:
1765 default:
1766 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1767 }
1768 }
1769
1770 static unsigned si_is_vertex_format_supported(struct pipe_screen *screen,
1771 enum pipe_format format,
1772 unsigned usage)
1773 {
1774 const struct util_format_description *desc;
1775 int first_non_void;
1776 unsigned data_format;
1777
1778 assert((usage & ~(PIPE_BIND_SHADER_IMAGE |
1779 PIPE_BIND_SAMPLER_VIEW |
1780 PIPE_BIND_VERTEX_BUFFER)) == 0);
1781
1782 desc = util_format_description(format);
1783
1784 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
1785 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
1786 * for read-only access (with caveats surrounding bounds checks), but
1787 * obviously fails for write access which we have to implement for
1788 * shader images. Luckily, OpenGL doesn't expect this to be supported
1789 * anyway, and so the only impact is on PBO uploads / downloads, which
1790 * shouldn't be expected to be fast for GL_RGB anyway.
1791 */
1792 if (desc->block.bits == 3 * 8 ||
1793 desc->block.bits == 3 * 16) {
1794 if (usage & (PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW)) {
1795 usage &= ~(PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW);
1796 if (!usage)
1797 return 0;
1798 }
1799 }
1800
1801 first_non_void = util_format_get_first_non_void_channel(format);
1802 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1803 if (data_format == V_008F0C_BUF_DATA_FORMAT_INVALID)
1804 return 0;
1805
1806 return usage;
1807 }
1808
1809 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1810 {
1811 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1812 r600_translate_colorswap(format, false) != ~0U;
1813 }
1814
1815 static bool si_is_zs_format_supported(enum pipe_format format)
1816 {
1817 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1818 }
1819
1820 static boolean si_is_format_supported(struct pipe_screen *screen,
1821 enum pipe_format format,
1822 enum pipe_texture_target target,
1823 unsigned sample_count,
1824 unsigned usage)
1825 {
1826 unsigned retval = 0;
1827
1828 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1829 R600_ERR("r600: unsupported texture type %d\n", target);
1830 return false;
1831 }
1832
1833 if (!util_format_is_supported(format, usage))
1834 return false;
1835
1836 if (sample_count > 1) {
1837 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
1838 return false;
1839
1840 if (usage & PIPE_BIND_SHADER_IMAGE)
1841 return false;
1842
1843 switch (sample_count) {
1844 case 2:
1845 case 4:
1846 case 8:
1847 break;
1848 case 16:
1849 if (format == PIPE_FORMAT_NONE)
1850 return true;
1851 else
1852 return false;
1853 default:
1854 return false;
1855 }
1856 }
1857
1858 if (usage & (PIPE_BIND_SAMPLER_VIEW |
1859 PIPE_BIND_SHADER_IMAGE)) {
1860 if (target == PIPE_BUFFER) {
1861 retval |= si_is_vertex_format_supported(
1862 screen, format, usage & (PIPE_BIND_SAMPLER_VIEW |
1863 PIPE_BIND_SHADER_IMAGE));
1864 } else {
1865 if (si_is_sampler_format_supported(screen, format))
1866 retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
1867 PIPE_BIND_SHADER_IMAGE);
1868 }
1869 }
1870
1871 if ((usage & (PIPE_BIND_RENDER_TARGET |
1872 PIPE_BIND_DISPLAY_TARGET |
1873 PIPE_BIND_SCANOUT |
1874 PIPE_BIND_SHARED |
1875 PIPE_BIND_BLENDABLE)) &&
1876 si_is_colorbuffer_format_supported(format)) {
1877 retval |= usage &
1878 (PIPE_BIND_RENDER_TARGET |
1879 PIPE_BIND_DISPLAY_TARGET |
1880 PIPE_BIND_SCANOUT |
1881 PIPE_BIND_SHARED);
1882 if (!util_format_is_pure_integer(format) &&
1883 !util_format_is_depth_or_stencil(format))
1884 retval |= usage & PIPE_BIND_BLENDABLE;
1885 }
1886
1887 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1888 si_is_zs_format_supported(format)) {
1889 retval |= PIPE_BIND_DEPTH_STENCIL;
1890 }
1891
1892 if (usage & PIPE_BIND_VERTEX_BUFFER) {
1893 retval |= si_is_vertex_format_supported(screen, format,
1894 PIPE_BIND_VERTEX_BUFFER);
1895 }
1896
1897 if ((usage & PIPE_BIND_LINEAR) &&
1898 !util_format_is_compressed(format) &&
1899 !(usage & PIPE_BIND_DEPTH_STENCIL))
1900 retval |= PIPE_BIND_LINEAR;
1901
1902 return retval == usage;
1903 }
1904
1905 /*
1906 * framebuffer handling
1907 */
1908
1909 static void si_choose_spi_color_formats(struct r600_surface *surf,
1910 unsigned format, unsigned swap,
1911 unsigned ntype, bool is_depth)
1912 {
1913 /* Alpha is needed for alpha-to-coverage.
1914 * Blending may be with or without alpha.
1915 */
1916 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
1917 unsigned alpha = 0; /* exports alpha, but may not support blending */
1918 unsigned blend = 0; /* supports blending, but may not export alpha */
1919 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
1920
1921 /* Choose the SPI color formats. These are required values for Stoney/RB+.
1922 * Other chips have multiple choices, though they are not necessarily better.
1923 */
1924 switch (format) {
1925 case V_028C70_COLOR_5_6_5:
1926 case V_028C70_COLOR_1_5_5_5:
1927 case V_028C70_COLOR_5_5_5_1:
1928 case V_028C70_COLOR_4_4_4_4:
1929 case V_028C70_COLOR_10_11_11:
1930 case V_028C70_COLOR_11_11_10:
1931 case V_028C70_COLOR_8:
1932 case V_028C70_COLOR_8_8:
1933 case V_028C70_COLOR_8_8_8_8:
1934 case V_028C70_COLOR_10_10_10_2:
1935 case V_028C70_COLOR_2_10_10_10:
1936 if (ntype == V_028C70_NUMBER_UINT)
1937 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
1938 else if (ntype == V_028C70_NUMBER_SINT)
1939 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
1940 else
1941 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
1942 break;
1943
1944 case V_028C70_COLOR_16:
1945 case V_028C70_COLOR_16_16:
1946 case V_028C70_COLOR_16_16_16_16:
1947 if (ntype == V_028C70_NUMBER_UNORM ||
1948 ntype == V_028C70_NUMBER_SNORM) {
1949 /* UNORM16 and SNORM16 don't support blending */
1950 if (ntype == V_028C70_NUMBER_UNORM)
1951 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
1952 else
1953 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
1954
1955 /* Use 32 bits per channel for blending. */
1956 if (format == V_028C70_COLOR_16) {
1957 if (swap == V_028C70_SWAP_STD) { /* R */
1958 blend = V_028714_SPI_SHADER_32_R;
1959 blend_alpha = V_028714_SPI_SHADER_32_AR;
1960 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
1961 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
1962 else
1963 assert(0);
1964 } else if (format == V_028C70_COLOR_16_16) {
1965 if (swap == V_028C70_SWAP_STD) { /* RG */
1966 blend = V_028714_SPI_SHADER_32_GR;
1967 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
1968 } else if (swap == V_028C70_SWAP_ALT) /* RA */
1969 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
1970 else
1971 assert(0);
1972 } else /* 16_16_16_16 */
1973 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
1974 } else if (ntype == V_028C70_NUMBER_UINT)
1975 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
1976 else if (ntype == V_028C70_NUMBER_SINT)
1977 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
1978 else if (ntype == V_028C70_NUMBER_FLOAT)
1979 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
1980 else
1981 assert(0);
1982 break;
1983
1984 case V_028C70_COLOR_32:
1985 if (swap == V_028C70_SWAP_STD) { /* R */
1986 blend = normal = V_028714_SPI_SHADER_32_R;
1987 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
1988 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
1989 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
1990 else
1991 assert(0);
1992 break;
1993
1994 case V_028C70_COLOR_32_32:
1995 if (swap == V_028C70_SWAP_STD) { /* RG */
1996 blend = normal = V_028714_SPI_SHADER_32_GR;
1997 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
1998 } else if (swap == V_028C70_SWAP_ALT) /* RA */
1999 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2000 else
2001 assert(0);
2002 break;
2003
2004 case V_028C70_COLOR_32_32_32_32:
2005 case V_028C70_COLOR_8_24:
2006 case V_028C70_COLOR_24_8:
2007 case V_028C70_COLOR_X24_8_32_FLOAT:
2008 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2009 break;
2010
2011 default:
2012 assert(0);
2013 return;
2014 }
2015
2016 /* The DB->CB copy needs 32_ABGR. */
2017 if (is_depth)
2018 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2019
2020 surf->spi_shader_col_format = normal;
2021 surf->spi_shader_col_format_alpha = alpha;
2022 surf->spi_shader_col_format_blend = blend;
2023 surf->spi_shader_col_format_blend_alpha = blend_alpha;
2024 }
2025
2026 static void si_initialize_color_surface(struct si_context *sctx,
2027 struct r600_surface *surf)
2028 {
2029 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2030 unsigned color_info, color_attrib, color_view;
2031 unsigned format, swap, ntype, endian;
2032 const struct util_format_description *desc;
2033 int i;
2034 unsigned blend_clamp = 0, blend_bypass = 0;
2035
2036 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2037 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
2038
2039 desc = util_format_description(surf->base.format);
2040 for (i = 0; i < 4; i++) {
2041 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2042 break;
2043 }
2044 }
2045 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
2046 ntype = V_028C70_NUMBER_FLOAT;
2047 } else {
2048 ntype = V_028C70_NUMBER_UNORM;
2049 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2050 ntype = V_028C70_NUMBER_SRGB;
2051 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2052 if (desc->channel[i].pure_integer) {
2053 ntype = V_028C70_NUMBER_SINT;
2054 } else {
2055 assert(desc->channel[i].normalized);
2056 ntype = V_028C70_NUMBER_SNORM;
2057 }
2058 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2059 if (desc->channel[i].pure_integer) {
2060 ntype = V_028C70_NUMBER_UINT;
2061 } else {
2062 assert(desc->channel[i].normalized);
2063 ntype = V_028C70_NUMBER_UNORM;
2064 }
2065 }
2066 }
2067
2068 format = si_translate_colorformat(surf->base.format);
2069 if (format == V_028C70_COLOR_INVALID) {
2070 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2071 }
2072 assert(format != V_028C70_COLOR_INVALID);
2073 swap = r600_translate_colorswap(surf->base.format, false);
2074 endian = si_colorformat_endian_swap(format);
2075
2076 /* blend clamp should be set for all NORM/SRGB types */
2077 if (ntype == V_028C70_NUMBER_UNORM ||
2078 ntype == V_028C70_NUMBER_SNORM ||
2079 ntype == V_028C70_NUMBER_SRGB)
2080 blend_clamp = 1;
2081
2082 /* set blend bypass according to docs if SINT/UINT or
2083 8/24 COLOR variants */
2084 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2085 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2086 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2087 blend_clamp = 0;
2088 blend_bypass = 1;
2089 }
2090
2091 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
2092 (format == V_028C70_COLOR_8 ||
2093 format == V_028C70_COLOR_8_8 ||
2094 format == V_028C70_COLOR_8_8_8_8))
2095 surf->color_is_int8 = true;
2096
2097 color_info = S_028C70_FORMAT(format) |
2098 S_028C70_COMP_SWAP(swap) |
2099 S_028C70_BLEND_CLAMP(blend_clamp) |
2100 S_028C70_BLEND_BYPASS(blend_bypass) |
2101 S_028C70_SIMPLE_FLOAT(1) |
2102 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2103 ntype != V_028C70_NUMBER_SNORM &&
2104 ntype != V_028C70_NUMBER_SRGB &&
2105 format != V_028C70_COLOR_8_24 &&
2106 format != V_028C70_COLOR_24_8) |
2107 S_028C70_NUMBER_TYPE(ntype) |
2108 S_028C70_ENDIAN(endian);
2109
2110 /* Intensity is implemented as Red, so treat it that way. */
2111 color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2112 util_format_is_intensity(surf->base.format));
2113
2114 if (rtex->resource.b.b.nr_samples > 1) {
2115 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
2116
2117 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2118 S_028C74_NUM_FRAGMENTS(log_samples);
2119
2120 if (rtex->fmask.size) {
2121 color_info |= S_028C70_COMPRESSION(1);
2122 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
2123
2124 if (sctx->b.chip_class == SI) {
2125 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2126 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2127 }
2128 }
2129 }
2130
2131 surf->cb_color_view = color_view;
2132 surf->cb_color_info = color_info;
2133 surf->cb_color_attrib = color_attrib;
2134
2135 if (sctx->b.chip_class >= VI) {
2136 unsigned max_uncompressed_block_size = 2;
2137
2138 if (rtex->resource.b.b.nr_samples > 1) {
2139 if (rtex->surface.bpe == 1)
2140 max_uncompressed_block_size = 0;
2141 else if (rtex->surface.bpe == 2)
2142 max_uncompressed_block_size = 1;
2143 }
2144
2145 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2146 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2147 }
2148
2149 /* This must be set for fast clear to work without FMASK. */
2150 if (!rtex->fmask.size && sctx->b.chip_class == SI) {
2151 unsigned bankh = util_logbase2(rtex->surface.bankh);
2152 surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2153 }
2154
2155 /* Determine pixel shader export format */
2156 si_choose_spi_color_formats(surf, format, swap, ntype, rtex->is_depth);
2157
2158 surf->color_initialized = true;
2159 }
2160
2161 static void si_init_depth_surface(struct si_context *sctx,
2162 struct r600_surface *surf)
2163 {
2164 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2165 unsigned level = surf->base.u.tex.level;
2166 struct radeon_surf_level *levelinfo = &rtex->surface.level[level];
2167 unsigned format;
2168 uint32_t z_info, s_info, db_depth_info;
2169 uint64_t z_offs, s_offs;
2170 uint32_t db_htile_data_base, db_htile_surface;
2171
2172 format = si_translate_dbformat(rtex->db_render_format);
2173
2174 if (format == V_028040_Z_INVALID) {
2175 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
2176 }
2177 assert(format != V_028040_Z_INVALID);
2178
2179 s_offs = z_offs = rtex->resource.gpu_address;
2180 z_offs += rtex->surface.level[level].offset;
2181 s_offs += rtex->surface.stencil_level[level].offset;
2182
2183 db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!rtex->tc_compatible_htile);
2184
2185 z_info = S_028040_FORMAT(format);
2186 if (rtex->resource.b.b.nr_samples > 1) {
2187 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
2188 }
2189
2190 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
2191 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
2192 else
2193 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
2194
2195 if (sctx->b.chip_class >= CIK) {
2196 struct radeon_info *info = &sctx->screen->b.info;
2197 unsigned index = rtex->surface.tiling_index[level];
2198 unsigned stencil_index = rtex->surface.stencil_tiling_index[level];
2199 unsigned macro_index = rtex->surface.macro_tile_index;
2200 unsigned tile_mode = info->si_tile_mode_array[index];
2201 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2202 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2203
2204 db_depth_info |=
2205 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2206 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2207 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2208 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2209 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2210 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2211 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2212 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2213 } else {
2214 unsigned tile_mode_index = si_tile_mode_index(rtex, level, false);
2215 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2216 tile_mode_index = si_tile_mode_index(rtex, level, true);
2217 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2218 }
2219
2220 /* HiZ aka depth buffer htile */
2221 /* use htile only for first level */
2222 if (rtex->htile_buffer && !level) {
2223 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2224 S_028040_ALLOW_EXPCLEAR(1);
2225
2226 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
2227 /* Workaround: For a not yet understood reason, the
2228 * combination of MSAA, fast stencil clear and stencil
2229 * decompress messes with subsequent stencil buffer
2230 * uses. Problem was reproduced on Verde, Bonaire,
2231 * Tonga, and Carrizo.
2232 *
2233 * Disabling EXPCLEAR works around the problem.
2234 *
2235 * Check piglit's arb_texture_multisample-stencil-clear
2236 * test if you want to try changing this.
2237 */
2238 if (rtex->resource.b.b.nr_samples <= 1)
2239 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2240 } else if (!rtex->tc_compatible_htile) {
2241 /* Use all of the htile_buffer for depth if there's no stencil.
2242 * This must not be set when TC-compatible HTILE is enabled
2243 * due to a hw bug.
2244 */
2245 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2246 }
2247
2248 uint64_t va = rtex->htile_buffer->gpu_address;
2249 db_htile_data_base = va >> 8;
2250 db_htile_surface = S_028ABC_FULL_CACHE(1);
2251
2252 if (rtex->tc_compatible_htile) {
2253 db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
2254
2255 switch (rtex->resource.b.b.nr_samples) {
2256 case 0:
2257 case 1:
2258 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2259 break;
2260 case 2:
2261 case 4:
2262 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2263 break;
2264 case 8:
2265 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2266 break;
2267 default:
2268 assert(0);
2269 }
2270 }
2271 } else {
2272 db_htile_data_base = 0;
2273 db_htile_surface = 0;
2274 }
2275
2276 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2277
2278 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2279 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2280 surf->db_htile_data_base = db_htile_data_base;
2281 surf->db_depth_info = db_depth_info;
2282 surf->db_z_info = z_info;
2283 surf->db_stencil_info = s_info;
2284 surf->db_depth_base = z_offs >> 8;
2285 surf->db_stencil_base = s_offs >> 8;
2286 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2287 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2288 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2289 levelinfo->nblk_y) / 64 - 1);
2290 surf->db_htile_surface = db_htile_surface;
2291
2292 surf->depth_initialized = true;
2293 }
2294
2295 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
2296 {
2297 for (int i = 0; i < state->nr_cbufs; ++i) {
2298 struct r600_surface *surf = NULL;
2299 struct r600_texture *rtex;
2300
2301 if (!state->cbufs[i])
2302 continue;
2303 surf = (struct r600_surface*)state->cbufs[i];
2304 rtex = (struct r600_texture*)surf->base.texture;
2305
2306 p_atomic_dec(&rtex->framebuffers_bound);
2307 }
2308 }
2309
2310 static void si_set_framebuffer_state(struct pipe_context *ctx,
2311 const struct pipe_framebuffer_state *state)
2312 {
2313 struct si_context *sctx = (struct si_context *)ctx;
2314 struct pipe_constant_buffer constbuf = {0};
2315 struct r600_surface *surf = NULL;
2316 struct r600_texture *rtex;
2317 bool old_any_dst_linear = sctx->framebuffer.any_dst_linear;
2318 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2319 int i;
2320
2321 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
2322 if (!sctx->framebuffer.state.cbufs[i])
2323 continue;
2324
2325 rtex = (struct r600_texture*)sctx->framebuffer.state.cbufs[i]->texture;
2326 if (rtex->dcc_gather_statistics)
2327 vi_separate_dcc_stop_query(ctx, rtex);
2328 }
2329
2330 /* Only flush TC when changing the framebuffer state, because
2331 * the only client not using TC that can change textures is
2332 * the framebuffer.
2333 *
2334 * Flush all CB and DB caches here because all buffers can be used
2335 * for write by both TC (with shader image stores) and CB/DB.
2336 */
2337 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
2338 SI_CONTEXT_INV_GLOBAL_L2 |
2339 SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER |
2340 SI_CONTEXT_CS_PARTIAL_FLUSH;
2341
2342 /* Take the maximum of the old and new count. If the new count is lower,
2343 * dirtying is needed to disable the unbound colorbuffers.
2344 */
2345 sctx->framebuffer.dirty_cbufs |=
2346 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2347 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2348
2349 si_dec_framebuffer_counters(&sctx->framebuffer.state);
2350 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2351
2352 sctx->framebuffer.spi_shader_col_format = 0;
2353 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2354 sctx->framebuffer.spi_shader_col_format_blend = 0;
2355 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2356 sctx->framebuffer.color_is_int8 = 0;
2357
2358 sctx->framebuffer.compressed_cb_mask = 0;
2359 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2360 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2361 sctx->framebuffer.any_dst_linear = false;
2362
2363 for (i = 0; i < state->nr_cbufs; i++) {
2364 if (!state->cbufs[i])
2365 continue;
2366
2367 surf = (struct r600_surface*)state->cbufs[i];
2368 rtex = (struct r600_texture*)surf->base.texture;
2369
2370 if (!surf->color_initialized) {
2371 si_initialize_color_surface(sctx, surf);
2372 }
2373
2374 sctx->framebuffer.spi_shader_col_format |=
2375 surf->spi_shader_col_format << (i * 4);
2376 sctx->framebuffer.spi_shader_col_format_alpha |=
2377 surf->spi_shader_col_format_alpha << (i * 4);
2378 sctx->framebuffer.spi_shader_col_format_blend |=
2379 surf->spi_shader_col_format_blend << (i * 4);
2380 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2381 surf->spi_shader_col_format_blend_alpha << (i * 4);
2382
2383 if (surf->color_is_int8)
2384 sctx->framebuffer.color_is_int8 |= 1 << i;
2385
2386 if (rtex->fmask.size) {
2387 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2388 }
2389
2390 if (rtex->surface.is_linear)
2391 sctx->framebuffer.any_dst_linear = true;
2392
2393 r600_context_add_resource_size(ctx, surf->base.texture);
2394
2395 p_atomic_inc(&rtex->framebuffers_bound);
2396
2397 if (rtex->dcc_gather_statistics) {
2398 /* Dirty tracking must be enabled for DCC usage analysis. */
2399 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2400 vi_separate_dcc_start_query(ctx, rtex);
2401 }
2402 }
2403
2404 if (state->zsbuf) {
2405 surf = (struct r600_surface*)state->zsbuf;
2406 rtex = (struct r600_texture*)surf->base.texture;
2407
2408 if (!surf->depth_initialized) {
2409 si_init_depth_surface(sctx, surf);
2410 }
2411 r600_context_add_resource_size(ctx, surf->base.texture);
2412 }
2413
2414 si_update_poly_offset_state(sctx);
2415 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2416 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
2417
2418 if (sctx->framebuffer.any_dst_linear != old_any_dst_linear)
2419 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2420
2421 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2422 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2423 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2424
2425 /* Set sample locations as fragment shader constants. */
2426 switch (sctx->framebuffer.nr_samples) {
2427 case 1:
2428 constbuf.user_buffer = sctx->b.sample_locations_1x;
2429 break;
2430 case 2:
2431 constbuf.user_buffer = sctx->b.sample_locations_2x;
2432 break;
2433 case 4:
2434 constbuf.user_buffer = sctx->b.sample_locations_4x;
2435 break;
2436 case 8:
2437 constbuf.user_buffer = sctx->b.sample_locations_8x;
2438 break;
2439 case 16:
2440 constbuf.user_buffer = sctx->b.sample_locations_16x;
2441 break;
2442 default:
2443 R600_ERR("Requested an invalid number of samples %i.\n",
2444 sctx->framebuffer.nr_samples);
2445 assert(0);
2446 }
2447 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2448 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
2449
2450 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
2451 }
2452
2453 sctx->need_check_render_feedback = true;
2454 sctx->do_update_shaders = true;
2455 }
2456
2457 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
2458 {
2459 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2460 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2461 unsigned i, nr_cbufs = state->nr_cbufs;
2462 struct r600_texture *tex = NULL;
2463 struct r600_surface *cb = NULL;
2464 unsigned cb_color_info = 0;
2465
2466 /* Colorbuffers. */
2467 for (i = 0; i < nr_cbufs; i++) {
2468 const struct radeon_surf_level *level_info;
2469 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
2470 unsigned cb_color_base, cb_color_fmask, cb_color_attrib;
2471 unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
2472
2473 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2474 continue;
2475
2476 cb = (struct r600_surface*)state->cbufs[i];
2477 if (!cb) {
2478 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2479 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2480 continue;
2481 }
2482
2483 tex = (struct r600_texture *)cb->base.texture;
2484 level_info = &tex->surface.level[cb->base.u.tex.level];
2485 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2486 &tex->resource, RADEON_USAGE_READWRITE,
2487 tex->resource.b.b.nr_samples > 1 ?
2488 RADEON_PRIO_COLOR_BUFFER_MSAA :
2489 RADEON_PRIO_COLOR_BUFFER);
2490
2491 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2492 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2493 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2494 RADEON_PRIO_CMASK);
2495 }
2496
2497 if (tex->dcc_separate_buffer)
2498 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2499 tex->dcc_separate_buffer,
2500 RADEON_USAGE_READWRITE,
2501 RADEON_PRIO_DCC);
2502
2503 /* Compute mutable surface parameters. */
2504 pitch_tile_max = level_info->nblk_x / 8 - 1;
2505 slice_tile_max = level_info->nblk_x *
2506 level_info->nblk_y / 64 - 1;
2507 tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false);
2508
2509 cb_color_base = (tex->resource.gpu_address + level_info->offset) >> 8;
2510 cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
2511 cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
2512 cb_color_attrib = cb->cb_color_attrib |
2513 S_028C74_TILE_MODE_INDEX(tile_mode_index);
2514
2515 if (tex->fmask.size) {
2516 if (sctx->b.chip_class >= CIK)
2517 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->fmask.pitch_in_pixels / 8 - 1);
2518 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->fmask.tile_mode_index);
2519 cb_color_fmask = (tex->resource.gpu_address + tex->fmask.offset) >> 8;
2520 cb_color_fmask_slice = S_028C88_TILE_MAX(tex->fmask.slice_tile_max);
2521 } else {
2522 /* This must be set for fast clear to work without FMASK. */
2523 if (sctx->b.chip_class >= CIK)
2524 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
2525 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
2526 cb_color_fmask = cb_color_base;
2527 cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
2528 }
2529
2530 cb_color_info = cb->cb_color_info | tex->cb_color_info;
2531
2532 if (tex->dcc_offset && cb->base.u.tex.level < tex->surface.num_dcc_levels) {
2533 bool is_msaa_resolve_dst = state->cbufs[0] &&
2534 state->cbufs[0]->texture->nr_samples > 1 &&
2535 state->cbufs[1] == &cb->base &&
2536 state->cbufs[1]->texture->nr_samples <= 1;
2537
2538 if (!is_msaa_resolve_dst)
2539 cb_color_info |= S_028C70_DCC_ENABLE(1);
2540 }
2541
2542 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
2543 sctx->b.chip_class >= VI ? 14 : 13);
2544 radeon_emit(cs, cb_color_base); /* R_028C60_CB_COLOR0_BASE */
2545 radeon_emit(cs, cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
2546 radeon_emit(cs, cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
2547 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
2548 radeon_emit(cs, cb_color_info); /* R_028C70_CB_COLOR0_INFO */
2549 radeon_emit(cs, cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
2550 radeon_emit(cs, cb->cb_dcc_control); /* R_028C78_CB_COLOR0_DCC_CONTROL */
2551 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
2552 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
2553 radeon_emit(cs, cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
2554 radeon_emit(cs, cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
2555 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
2556 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
2557
2558 if (sctx->b.chip_class >= VI) /* R_028C94_CB_COLOR0_DCC_BASE */
2559 radeon_emit(cs, ((!tex->dcc_separate_buffer ? tex->resource.gpu_address : 0) +
2560 tex->dcc_offset +
2561 tex->surface.level[cb->base.u.tex.level].dcc_offset) >> 8);
2562 }
2563 for (; i < 8 ; i++)
2564 if (sctx->framebuffer.dirty_cbufs & (1 << i))
2565 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
2566
2567 /* ZS buffer. */
2568 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
2569 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
2570 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
2571
2572 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2573 &rtex->resource, RADEON_USAGE_READWRITE,
2574 zb->base.texture->nr_samples > 1 ?
2575 RADEON_PRIO_DEPTH_BUFFER_MSAA :
2576 RADEON_PRIO_DEPTH_BUFFER);
2577
2578 if (zb->db_htile_data_base) {
2579 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2580 rtex->htile_buffer, RADEON_USAGE_READWRITE,
2581 RADEON_PRIO_HTILE);
2582 }
2583
2584 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
2585 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
2586
2587 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
2588 radeon_emit(cs, zb->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
2589 radeon_emit(cs, zb->db_z_info | /* R_028040_DB_Z_INFO */
2590 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
2591 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
2592 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
2593 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
2594 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
2595 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
2596 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
2597 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
2598
2599 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
2600 radeon_emit(cs, rtex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
2601 radeon_emit(cs, fui(rtex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
2602
2603 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
2604 } else if (sctx->framebuffer.dirty_zsbuf) {
2605 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
2606 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
2607 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
2608 }
2609
2610 /* Framebuffer dimensions. */
2611 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2612 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2613 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
2614
2615 sctx->framebuffer.dirty_cbufs = 0;
2616 sctx->framebuffer.dirty_zsbuf = false;
2617 }
2618
2619 static void si_emit_msaa_sample_locs(struct si_context *sctx,
2620 struct r600_atom *atom)
2621 {
2622 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2623 unsigned nr_samples = sctx->framebuffer.nr_samples;
2624
2625 /* Smoothing (only possible with nr_samples == 1) uses the same
2626 * sample locations as the MSAA it simulates.
2627 */
2628 if (nr_samples <= 1 && sctx->smoothing_enabled)
2629 nr_samples = SI_NUM_SMOOTH_AA_SAMPLES;
2630
2631 /* On Polaris, the small primitive filter uses the sample locations
2632 * even when MSAA is off, so we need to make sure they're set to 0.
2633 */
2634 if ((nr_samples > 1 || sctx->b.family >= CHIP_POLARIS10) &&
2635 (nr_samples != sctx->msaa_sample_locs.nr_samples)) {
2636 sctx->msaa_sample_locs.nr_samples = nr_samples;
2637 cayman_emit_msaa_sample_locs(cs, nr_samples);
2638 }
2639
2640 if (sctx->b.family >= CHIP_POLARIS10) {
2641 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
2642 unsigned small_prim_filter_cntl =
2643 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
2644 S_028830_LINE_FILTER_DISABLE(1); /* line bug */
2645
2646 /* The alternative of setting sample locations to 0 would
2647 * require a DB flush to avoid Z errors, see
2648 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
2649 */
2650 if (sctx->framebuffer.nr_samples > 1 && rs && !rs->multisample_enable)
2651 small_prim_filter_cntl &= C_028830_SMALL_PRIM_FILTER_ENABLE;
2652
2653 radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
2654 small_prim_filter_cntl);
2655 }
2656 }
2657
2658 static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom)
2659 {
2660 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2661 unsigned num_tile_pipes = sctx->screen->b.info.num_tile_pipes;
2662 /* 33% faster rendering to linear color buffers */
2663 bool dst_is_linear = sctx->framebuffer.any_dst_linear;
2664 unsigned sc_mode_cntl_1 =
2665 S_028A4C_WALK_SIZE(dst_is_linear) |
2666 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear) |
2667 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
2668 /* always 1: */
2669 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
2670 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
2671 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
2672 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
2673 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
2674 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
2675
2676 cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples,
2677 sctx->ps_iter_samples,
2678 sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0,
2679 sc_mode_cntl_1);
2680 }
2681
2682 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
2683 {
2684 struct si_context *sctx = (struct si_context *)ctx;
2685
2686 if (sctx->ps_iter_samples == min_samples)
2687 return;
2688
2689 sctx->ps_iter_samples = min_samples;
2690 sctx->do_update_shaders = true;
2691
2692 if (sctx->framebuffer.nr_samples > 1)
2693 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2694 }
2695
2696 /*
2697 * Samplers
2698 */
2699
2700 /**
2701 * Build the sampler view descriptor for a buffer texture.
2702 * @param state 256-bit descriptor; only the high 128 bits are filled in
2703 */
2704 void
2705 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
2706 enum pipe_format format,
2707 unsigned offset, unsigned size,
2708 uint32_t *state)
2709 {
2710 const struct util_format_description *desc;
2711 int first_non_void;
2712 unsigned stride;
2713 unsigned num_records;
2714 unsigned num_format, data_format;
2715
2716 desc = util_format_description(format);
2717 first_non_void = util_format_get_first_non_void_channel(format);
2718 stride = desc->block.bits / 8;
2719 num_format = si_translate_buffer_numformat(&screen->b.b, desc, first_non_void);
2720 data_format = si_translate_buffer_dataformat(&screen->b.b, desc, first_non_void);
2721
2722 num_records = size / stride;
2723 num_records = MIN2(num_records, (buf->b.b.width0 - offset) / stride);
2724
2725 if (screen->b.chip_class >= VI)
2726 num_records *= stride;
2727
2728 state[4] = 0;
2729 state[5] = S_008F04_STRIDE(stride);
2730 state[6] = num_records;
2731 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2732 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2733 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2734 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2735 S_008F0C_NUM_FORMAT(num_format) |
2736 S_008F0C_DATA_FORMAT(data_format);
2737 }
2738
2739 /**
2740 * Build the sampler view descriptor for a texture.
2741 */
2742 void
2743 si_make_texture_descriptor(struct si_screen *screen,
2744 struct r600_texture *tex,
2745 bool sampler,
2746 enum pipe_texture_target target,
2747 enum pipe_format pipe_format,
2748 const unsigned char state_swizzle[4],
2749 unsigned first_level, unsigned last_level,
2750 unsigned first_layer, unsigned last_layer,
2751 unsigned width, unsigned height, unsigned depth,
2752 uint32_t *state,
2753 uint32_t *fmask_state)
2754 {
2755 struct pipe_resource *res = &tex->resource.b.b;
2756 const struct util_format_description *desc;
2757 unsigned char swizzle[4];
2758 int first_non_void;
2759 unsigned num_format, data_format, type;
2760 uint64_t va;
2761
2762 desc = util_format_description(pipe_format);
2763
2764 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2765 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2766 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2767
2768 switch (pipe_format) {
2769 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2770 case PIPE_FORMAT_X24S8_UINT:
2771 case PIPE_FORMAT_X32_S8X24_UINT:
2772 case PIPE_FORMAT_X8Z24_UNORM:
2773 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
2774 break;
2775 default:
2776 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
2777 }
2778 } else {
2779 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2780 }
2781
2782 first_non_void = util_format_get_first_non_void_channel(pipe_format);
2783
2784 switch (pipe_format) {
2785 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2786 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2787 break;
2788 default:
2789 if (first_non_void < 0) {
2790 if (util_format_is_compressed(pipe_format)) {
2791 switch (pipe_format) {
2792 case PIPE_FORMAT_DXT1_SRGB:
2793 case PIPE_FORMAT_DXT1_SRGBA:
2794 case PIPE_FORMAT_DXT3_SRGBA:
2795 case PIPE_FORMAT_DXT5_SRGBA:
2796 case PIPE_FORMAT_BPTC_SRGBA:
2797 case PIPE_FORMAT_ETC2_SRGB8:
2798 case PIPE_FORMAT_ETC2_SRGB8A1:
2799 case PIPE_FORMAT_ETC2_SRGBA8:
2800 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2801 break;
2802 case PIPE_FORMAT_RGTC1_SNORM:
2803 case PIPE_FORMAT_LATC1_SNORM:
2804 case PIPE_FORMAT_RGTC2_SNORM:
2805 case PIPE_FORMAT_LATC2_SNORM:
2806 case PIPE_FORMAT_ETC2_R11_SNORM:
2807 case PIPE_FORMAT_ETC2_RG11_SNORM:
2808 /* implies float, so use SNORM/UNORM to determine
2809 whether data is signed or not */
2810 case PIPE_FORMAT_BPTC_RGB_FLOAT:
2811 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2812 break;
2813 default:
2814 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2815 break;
2816 }
2817 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
2818 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2819 } else {
2820 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2821 }
2822 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
2823 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2824 } else {
2825 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2826
2827 switch (desc->channel[first_non_void].type) {
2828 case UTIL_FORMAT_TYPE_FLOAT:
2829 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2830 break;
2831 case UTIL_FORMAT_TYPE_SIGNED:
2832 if (desc->channel[first_non_void].normalized)
2833 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2834 else if (desc->channel[first_non_void].pure_integer)
2835 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
2836 else
2837 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
2838 break;
2839 case UTIL_FORMAT_TYPE_UNSIGNED:
2840 if (desc->channel[first_non_void].normalized)
2841 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2842 else if (desc->channel[first_non_void].pure_integer)
2843 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
2844 else
2845 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
2846 }
2847 }
2848 }
2849
2850 data_format = si_translate_texformat(&screen->b.b, pipe_format, desc, first_non_void);
2851 if (data_format == ~0) {
2852 data_format = 0;
2853 }
2854
2855 if (!sampler &&
2856 (res->target == PIPE_TEXTURE_CUBE ||
2857 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
2858 res->target == PIPE_TEXTURE_3D)) {
2859 /* For the purpose of shader images, treat cube maps and 3D
2860 * textures as 2D arrays. For 3D textures, the address
2861 * calculations for mipmaps are different, so we rely on the
2862 * caller to effectively disable mipmaps.
2863 */
2864 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
2865
2866 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
2867 } else {
2868 type = si_tex_dim(res->target, target, res->nr_samples);
2869 }
2870
2871 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
2872 height = 1;
2873 depth = res->array_size;
2874 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
2875 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
2876 if (sampler || res->target != PIPE_TEXTURE_3D)
2877 depth = res->array_size;
2878 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
2879 depth = res->array_size / 6;
2880
2881 state[0] = 0;
2882 state[1] = (S_008F14_DATA_FORMAT(data_format) |
2883 S_008F14_NUM_FORMAT(num_format));
2884 state[2] = (S_008F18_WIDTH(width - 1) |
2885 S_008F18_HEIGHT(height - 1) |
2886 S_008F18_PERF_MOD(4));
2887 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2888 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2889 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2890 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2891 S_008F1C_BASE_LEVEL(res->nr_samples > 1 ?
2892 0 : first_level) |
2893 S_008F1C_LAST_LEVEL(res->nr_samples > 1 ?
2894 util_logbase2(res->nr_samples) :
2895 last_level) |
2896 S_008F1C_POW2_PAD(res->last_level > 0) |
2897 S_008F1C_TYPE(type));
2898 state[4] = S_008F20_DEPTH(depth - 1);
2899 state[5] = (S_008F24_BASE_ARRAY(first_layer) |
2900 S_008F24_LAST_ARRAY(last_layer));
2901 state[6] = 0;
2902 state[7] = 0;
2903
2904 if (tex->dcc_offset) {
2905 unsigned swap = r600_translate_colorswap(pipe_format, false);
2906
2907 state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
2908 } else {
2909 /* The last dword is unused by hw. The shader uses it to clear
2910 * bits in the first dword of sampler state.
2911 */
2912 if (screen->b.chip_class <= CIK && res->nr_samples <= 1) {
2913 if (first_level == last_level)
2914 state[7] = C_008F30_MAX_ANISO_RATIO;
2915 else
2916 state[7] = 0xffffffff;
2917 }
2918 }
2919
2920 /* Initialize the sampler view for FMASK. */
2921 if (tex->fmask.size) {
2922 uint32_t fmask_format;
2923
2924 va = tex->resource.gpu_address + tex->fmask.offset;
2925
2926 switch (res->nr_samples) {
2927 case 2:
2928 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
2929 break;
2930 case 4:
2931 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
2932 break;
2933 case 8:
2934 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
2935 break;
2936 default:
2937 assert(0);
2938 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
2939 }
2940
2941 fmask_state[0] = va >> 8;
2942 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
2943 S_008F14_DATA_FORMAT(fmask_format) |
2944 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT);
2945 fmask_state[2] = S_008F18_WIDTH(width - 1) |
2946 S_008F18_HEIGHT(height - 1);
2947 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
2948 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
2949 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
2950 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
2951 S_008F1C_TILING_INDEX(tex->fmask.tile_mode_index) |
2952 S_008F1C_TYPE(si_tex_dim(res->target, target, 0));
2953 fmask_state[4] = S_008F20_DEPTH(depth - 1) |
2954 S_008F20_PITCH(tex->fmask.pitch_in_pixels - 1);
2955 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer) |
2956 S_008F24_LAST_ARRAY(last_layer);
2957 fmask_state[6] = 0;
2958 fmask_state[7] = 0;
2959 }
2960 }
2961
2962 /**
2963 * Create a sampler view.
2964 *
2965 * @param ctx context
2966 * @param texture texture
2967 * @param state sampler view template
2968 * @param width0 width0 override (for compressed textures as int)
2969 * @param height0 height0 override (for compressed textures as int)
2970 * @param force_level set the base address to the level (for compressed textures)
2971 */
2972 struct pipe_sampler_view *
2973 si_create_sampler_view_custom(struct pipe_context *ctx,
2974 struct pipe_resource *texture,
2975 const struct pipe_sampler_view *state,
2976 unsigned width0, unsigned height0,
2977 unsigned force_level)
2978 {
2979 struct si_context *sctx = (struct si_context*)ctx;
2980 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
2981 struct r600_texture *tmp = (struct r600_texture*)texture;
2982 unsigned base_level, first_level, last_level;
2983 unsigned char state_swizzle[4];
2984 unsigned height, depth, width;
2985 unsigned last_layer = state->u.tex.last_layer;
2986 enum pipe_format pipe_format;
2987 const struct radeon_surf_level *surflevel;
2988
2989 if (!view)
2990 return NULL;
2991
2992 /* initialize base object */
2993 view->base = *state;
2994 view->base.texture = NULL;
2995 view->base.reference.count = 1;
2996 view->base.context = ctx;
2997
2998 assert(texture);
2999 pipe_resource_reference(&view->base.texture, texture);
3000
3001 if (state->format == PIPE_FORMAT_X24S8_UINT ||
3002 state->format == PIPE_FORMAT_S8X24_UINT ||
3003 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
3004 state->format == PIPE_FORMAT_S8_UINT)
3005 view->is_stencil_sampler = true;
3006
3007 /* Buffer resource. */
3008 if (texture->target == PIPE_BUFFER) {
3009 si_make_buffer_descriptor(sctx->screen,
3010 (struct r600_resource *)texture,
3011 state->format,
3012 state->u.buf.offset,
3013 state->u.buf.size,
3014 view->state);
3015 return &view->base;
3016 }
3017
3018 state_swizzle[0] = state->swizzle_r;
3019 state_swizzle[1] = state->swizzle_g;
3020 state_swizzle[2] = state->swizzle_b;
3021 state_swizzle[3] = state->swizzle_a;
3022
3023 base_level = 0;
3024 first_level = state->u.tex.first_level;
3025 last_level = state->u.tex.last_level;
3026 width = width0;
3027 height = height0;
3028 depth = texture->depth0;
3029
3030 if (force_level) {
3031 assert(force_level == first_level &&
3032 force_level == last_level);
3033 base_level = force_level;
3034 first_level = 0;
3035 last_level = 0;
3036 width = u_minify(width, force_level);
3037 height = u_minify(height, force_level);
3038 depth = u_minify(depth, force_level);
3039 }
3040
3041 /* This is not needed if state trackers set last_layer correctly. */
3042 if (state->target == PIPE_TEXTURE_1D ||
3043 state->target == PIPE_TEXTURE_2D ||
3044 state->target == PIPE_TEXTURE_RECT ||
3045 state->target == PIPE_TEXTURE_CUBE)
3046 last_layer = state->u.tex.first_layer;
3047
3048 /* Texturing with separate depth and stencil. */
3049 pipe_format = state->format;
3050
3051 /* Depth/stencil texturing sometimes needs separate texture. */
3052 if (tmp->is_depth && !r600_can_sample_zs(tmp, view->is_stencil_sampler)) {
3053 if (!tmp->flushed_depth_texture &&
3054 !r600_init_flushed_depth_texture(ctx, texture, NULL)) {
3055 pipe_resource_reference(&view->base.texture, NULL);
3056 FREE(view);
3057 return NULL;
3058 }
3059
3060 assert(tmp->flushed_depth_texture);
3061
3062 /* Override format for the case where the flushed texture
3063 * contains only Z or only S.
3064 */
3065 if (tmp->flushed_depth_texture->resource.b.b.format != tmp->resource.b.b.format)
3066 pipe_format = tmp->flushed_depth_texture->resource.b.b.format;
3067
3068 tmp = tmp->flushed_depth_texture;
3069 }
3070
3071 surflevel = tmp->surface.level;
3072
3073 if (tmp->db_compatible) {
3074 if (!view->is_stencil_sampler)
3075 pipe_format = tmp->db_render_format;
3076
3077 switch (pipe_format) {
3078 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
3079 pipe_format = PIPE_FORMAT_Z32_FLOAT;
3080 break;
3081 case PIPE_FORMAT_X8Z24_UNORM:
3082 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3083 /* Z24 is always stored like this for DB
3084 * compatibility.
3085 */
3086 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
3087 break;
3088 case PIPE_FORMAT_X24S8_UINT:
3089 case PIPE_FORMAT_S8X24_UINT:
3090 case PIPE_FORMAT_X32_S8X24_UINT:
3091 pipe_format = PIPE_FORMAT_S8_UINT;
3092 surflevel = tmp->surface.stencil_level;
3093 break;
3094 default:;
3095 }
3096 }
3097
3098 vi_dcc_disable_if_incompatible_format(&sctx->b, texture,
3099 state->u.tex.first_level,
3100 state->format);
3101
3102 si_make_texture_descriptor(sctx->screen, tmp, true,
3103 state->target, pipe_format, state_swizzle,
3104 first_level, last_level,
3105 state->u.tex.first_layer, last_layer,
3106 width, height, depth,
3107 view->state, view->fmask_state);
3108
3109 view->base_level_info = &surflevel[base_level];
3110 view->base_level = base_level;
3111 view->block_width = util_format_get_blockwidth(pipe_format);
3112 return &view->base;
3113 }
3114
3115 static struct pipe_sampler_view *
3116 si_create_sampler_view(struct pipe_context *ctx,
3117 struct pipe_resource *texture,
3118 const struct pipe_sampler_view *state)
3119 {
3120 return si_create_sampler_view_custom(ctx, texture, state,
3121 texture ? texture->width0 : 0,
3122 texture ? texture->height0 : 0, 0);
3123 }
3124
3125 static void si_sampler_view_destroy(struct pipe_context *ctx,
3126 struct pipe_sampler_view *state)
3127 {
3128 struct si_sampler_view *view = (struct si_sampler_view *)state;
3129
3130 pipe_resource_reference(&state->texture, NULL);
3131 FREE(view);
3132 }
3133
3134 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
3135 {
3136 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
3137 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
3138 (linear_filter &&
3139 (wrap == PIPE_TEX_WRAP_CLAMP ||
3140 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
3141 }
3142
3143 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
3144 {
3145 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
3146 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
3147
3148 return (state->border_color.ui[0] || state->border_color.ui[1] ||
3149 state->border_color.ui[2] || state->border_color.ui[3]) &&
3150 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
3151 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
3152 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
3153 }
3154
3155 static void *si_create_sampler_state(struct pipe_context *ctx,
3156 const struct pipe_sampler_state *state)
3157 {
3158 struct si_context *sctx = (struct si_context *)ctx;
3159 struct r600_common_screen *rscreen = sctx->b.screen;
3160 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
3161 unsigned border_color_type, border_color_index = 0;
3162 unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
3163 : state->max_anisotropy;
3164 unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso);
3165
3166 if (!rstate) {
3167 return NULL;
3168 }
3169
3170 if (!sampler_state_needs_border_color(state))
3171 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3172 else if (state->border_color.f[0] == 0 &&
3173 state->border_color.f[1] == 0 &&
3174 state->border_color.f[2] == 0 &&
3175 state->border_color.f[3] == 0)
3176 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3177 else if (state->border_color.f[0] == 0 &&
3178 state->border_color.f[1] == 0 &&
3179 state->border_color.f[2] == 0 &&
3180 state->border_color.f[3] == 1)
3181 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3182 else if (state->border_color.f[0] == 1 &&
3183 state->border_color.f[1] == 1 &&
3184 state->border_color.f[2] == 1 &&
3185 state->border_color.f[3] == 1)
3186 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3187 else {
3188 int i;
3189
3190 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
3191
3192 /* Check if the border has been uploaded already. */
3193 for (i = 0; i < sctx->border_color_count; i++)
3194 if (memcmp(&sctx->border_color_table[i], &state->border_color,
3195 sizeof(state->border_color)) == 0)
3196 break;
3197
3198 if (i >= SI_MAX_BORDER_COLORS) {
3199 /* Getting 4096 unique border colors is very unlikely. */
3200 fprintf(stderr, "radeonsi: The border color table is full. "
3201 "Any new border colors will be just black. "
3202 "Please file a bug.\n");
3203 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3204 } else {
3205 if (i == sctx->border_color_count) {
3206 /* Upload a new border color. */
3207 memcpy(&sctx->border_color_table[i], &state->border_color,
3208 sizeof(state->border_color));
3209 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
3210 &state->border_color,
3211 sizeof(state->border_color));
3212 sctx->border_color_count++;
3213 }
3214
3215 border_color_index = i;
3216 }
3217 }
3218
3219 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
3220 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
3221 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
3222 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3223 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
3224 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
3225 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
3226 S_008F30_ANISO_BIAS(max_aniso_ratio) |
3227 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
3228 S_008F30_COMPAT_MODE(sctx->b.chip_class >= VI));
3229 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
3230 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)) |
3231 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
3232 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
3233 S_008F38_XY_MAG_FILTER(eg_tex_filter(state->mag_img_filter, max_aniso)) |
3234 S_008F38_XY_MIN_FILTER(eg_tex_filter(state->min_img_filter, max_aniso)) |
3235 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
3236 S_008F38_MIP_POINT_PRECLAMP(1) |
3237 S_008F38_DISABLE_LSB_CEIL(1) |
3238 S_008F38_FILTER_PREC_FIX(1) |
3239 S_008F38_ANISO_OVERRIDE(sctx->b.chip_class >= VI));
3240 rstate->val[3] = S_008F3C_BORDER_COLOR_PTR(border_color_index) |
3241 S_008F3C_BORDER_COLOR_TYPE(border_color_type);
3242 return rstate;
3243 }
3244
3245 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
3246 {
3247 struct si_context *sctx = (struct si_context *)ctx;
3248
3249 if (sctx->sample_mask.sample_mask == (uint16_t)sample_mask)
3250 return;
3251
3252 sctx->sample_mask.sample_mask = sample_mask;
3253 si_mark_atom_dirty(sctx, &sctx->sample_mask.atom);
3254 }
3255
3256 static void si_emit_sample_mask(struct si_context *sctx, struct r600_atom *atom)
3257 {
3258 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
3259 unsigned mask = sctx->sample_mask.sample_mask;
3260
3261 /* Needed for line and polygon smoothing as well as for the Polaris
3262 * small primitive filter. We expect the state tracker to take care of
3263 * this for us.
3264 */
3265 assert(mask == 0xffff || sctx->framebuffer.nr_samples > 1 ||
3266 (mask & 1 && sctx->blitter->running));
3267
3268 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3269 radeon_emit(cs, mask | (mask << 16));
3270 radeon_emit(cs, mask | (mask << 16));
3271 }
3272
3273 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
3274 {
3275 free(state);
3276 }
3277
3278 /*
3279 * Vertex elements & buffers
3280 */
3281
3282 static void *si_create_vertex_elements(struct pipe_context *ctx,
3283 unsigned count,
3284 const struct pipe_vertex_element *elements)
3285 {
3286 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
3287 int i;
3288
3289 assert(count <= SI_MAX_ATTRIBS);
3290 if (!v)
3291 return NULL;
3292
3293 v->count = count;
3294 for (i = 0; i < count; ++i) {
3295 const struct util_format_description *desc;
3296 unsigned data_format, num_format;
3297 int first_non_void;
3298
3299 desc = util_format_description(elements[i].src_format);
3300 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
3301 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
3302 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
3303
3304 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3305 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3306 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3307 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
3308 S_008F0C_NUM_FORMAT(num_format) |
3309 S_008F0C_DATA_FORMAT(data_format);
3310 v->format_size[i] = desc->block.bits / 8;
3311
3312 /* The hardware always treats the 2-bit alpha channel as
3313 * unsigned, so a shader workaround is needed.
3314 */
3315 if (data_format == V_008F0C_BUF_DATA_FORMAT_2_10_10_10) {
3316 if (num_format == V_008F0C_BUF_NUM_FORMAT_SNORM) {
3317 v->fix_fetch |= SI_FIX_FETCH_A2_SNORM << (2 * i);
3318 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SSCALED) {
3319 v->fix_fetch |= SI_FIX_FETCH_A2_SSCALED << (2 * i);
3320 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SINT) {
3321 /* This isn't actually used in OpenGL. */
3322 v->fix_fetch |= SI_FIX_FETCH_A2_SINT << (2 * i);
3323 }
3324 }
3325 }
3326 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
3327
3328 return v;
3329 }
3330
3331 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
3332 {
3333 struct si_context *sctx = (struct si_context *)ctx;
3334 struct si_vertex_element *v = (struct si_vertex_element*)state;
3335
3336 sctx->vertex_elements = v;
3337 sctx->vertex_buffers_dirty = true;
3338 sctx->do_update_shaders = true;
3339 }
3340
3341 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
3342 {
3343 struct si_context *sctx = (struct si_context *)ctx;
3344
3345 if (sctx->vertex_elements == state)
3346 sctx->vertex_elements = NULL;
3347 FREE(state);
3348 }
3349
3350 static void si_set_vertex_buffers(struct pipe_context *ctx,
3351 unsigned start_slot, unsigned count,
3352 const struct pipe_vertex_buffer *buffers)
3353 {
3354 struct si_context *sctx = (struct si_context *)ctx;
3355 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
3356 int i;
3357
3358 assert(start_slot + count <= ARRAY_SIZE(sctx->vertex_buffer));
3359
3360 if (buffers) {
3361 for (i = 0; i < count; i++) {
3362 const struct pipe_vertex_buffer *src = buffers + i;
3363 struct pipe_vertex_buffer *dsti = dst + i;
3364 struct pipe_resource *buf = src->buffer;
3365
3366 pipe_resource_reference(&dsti->buffer, buf);
3367 dsti->buffer_offset = src->buffer_offset;
3368 dsti->stride = src->stride;
3369 r600_context_add_resource_size(ctx, buf);
3370 if (buf)
3371 r600_resource(buf)->bind_history |= PIPE_BIND_VERTEX_BUFFER;
3372 }
3373 } else {
3374 for (i = 0; i < count; i++) {
3375 pipe_resource_reference(&dst[i].buffer, NULL);
3376 }
3377 }
3378 sctx->vertex_buffers_dirty = true;
3379 }
3380
3381 static void si_set_index_buffer(struct pipe_context *ctx,
3382 const struct pipe_index_buffer *ib)
3383 {
3384 struct si_context *sctx = (struct si_context *)ctx;
3385
3386 if (ib) {
3387 struct pipe_resource *buf = ib->buffer;
3388
3389 pipe_resource_reference(&sctx->index_buffer.buffer, buf);
3390 memcpy(&sctx->index_buffer, ib, sizeof(*ib));
3391 r600_context_add_resource_size(ctx, buf);
3392 if (buf)
3393 r600_resource(buf)->bind_history |= PIPE_BIND_INDEX_BUFFER;
3394 } else {
3395 pipe_resource_reference(&sctx->index_buffer.buffer, NULL);
3396 }
3397 }
3398
3399 /*
3400 * Misc
3401 */
3402
3403 static void si_set_tess_state(struct pipe_context *ctx,
3404 const float default_outer_level[4],
3405 const float default_inner_level[2])
3406 {
3407 struct si_context *sctx = (struct si_context *)ctx;
3408 struct pipe_constant_buffer cb;
3409 float array[8];
3410
3411 memcpy(array, default_outer_level, sizeof(float) * 4);
3412 memcpy(array+4, default_inner_level, sizeof(float) * 2);
3413
3414 cb.buffer = NULL;
3415 cb.user_buffer = NULL;
3416 cb.buffer_size = sizeof(array);
3417
3418 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
3419 (void*)array, sizeof(array),
3420 &cb.buffer_offset);
3421
3422 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
3423 pipe_resource_reference(&cb.buffer, NULL);
3424 }
3425
3426 static void si_texture_barrier(struct pipe_context *ctx)
3427 {
3428 struct si_context *sctx = (struct si_context *)ctx;
3429
3430 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
3431 SI_CONTEXT_INV_GLOBAL_L2 |
3432 SI_CONTEXT_FLUSH_AND_INV_CB |
3433 SI_CONTEXT_CS_PARTIAL_FLUSH;
3434 }
3435
3436 /* This only ensures coherency for shader image/buffer stores. */
3437 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
3438 {
3439 struct si_context *sctx = (struct si_context *)ctx;
3440
3441 /* Subsequent commands must wait for all shader invocations to
3442 * complete. */
3443 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
3444 SI_CONTEXT_CS_PARTIAL_FLUSH;
3445
3446 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
3447 sctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 |
3448 SI_CONTEXT_INV_VMEM_L1;
3449
3450 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
3451 PIPE_BARRIER_SHADER_BUFFER |
3452 PIPE_BARRIER_TEXTURE |
3453 PIPE_BARRIER_IMAGE |
3454 PIPE_BARRIER_STREAMOUT_BUFFER |
3455 PIPE_BARRIER_GLOBAL_BUFFER)) {
3456 /* As far as I can tell, L1 contents are written back to L2
3457 * automatically at end of shader, but the contents of other
3458 * L1 caches might still be stale. */
3459 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
3460 }
3461
3462 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
3463 /* Indices are read through TC L2 since VI.
3464 * L1 isn't used.
3465 */
3466 if (sctx->screen->b.chip_class <= CIK)
3467 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
3468 }
3469
3470 if (flags & PIPE_BARRIER_FRAMEBUFFER)
3471 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER;
3472
3473 if (flags & (PIPE_BARRIER_FRAMEBUFFER |
3474 PIPE_BARRIER_INDIRECT_BUFFER))
3475 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
3476 }
3477
3478 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
3479 {
3480 struct pipe_blend_state blend;
3481
3482 memset(&blend, 0, sizeof(blend));
3483 blend.independent_blend_enable = true;
3484 blend.rt[0].colormask = 0xf;
3485 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
3486 }
3487
3488 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
3489 bool include_draw_vbo)
3490 {
3491 si_need_cs_space((struct si_context*)ctx);
3492 }
3493
3494 static void si_init_config(struct si_context *sctx);
3495
3496 void si_init_state_functions(struct si_context *sctx)
3497 {
3498 si_init_external_atom(sctx, &sctx->b.render_cond_atom, &sctx->atoms.s.render_cond);
3499 si_init_external_atom(sctx, &sctx->b.streamout.begin_atom, &sctx->atoms.s.streamout_begin);
3500 si_init_external_atom(sctx, &sctx->b.streamout.enable_atom, &sctx->atoms.s.streamout_enable);
3501 si_init_external_atom(sctx, &sctx->b.scissors.atom, &sctx->atoms.s.scissors);
3502 si_init_external_atom(sctx, &sctx->b.viewports.atom, &sctx->atoms.s.viewports);
3503
3504 si_init_atom(sctx, &sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state);
3505 si_init_atom(sctx, &sctx->msaa_sample_locs.atom, &sctx->atoms.s.msaa_sample_locs, si_emit_msaa_sample_locs);
3506 si_init_atom(sctx, &sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state);
3507 si_init_atom(sctx, &sctx->msaa_config, &sctx->atoms.s.msaa_config, si_emit_msaa_config);
3508 si_init_atom(sctx, &sctx->sample_mask.atom, &sctx->atoms.s.sample_mask, si_emit_sample_mask);
3509 si_init_atom(sctx, &sctx->cb_render_state, &sctx->atoms.s.cb_render_state, si_emit_cb_render_state);
3510 si_init_atom(sctx, &sctx->blend_color.atom, &sctx->atoms.s.blend_color, si_emit_blend_color);
3511 si_init_atom(sctx, &sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs);
3512 si_init_atom(sctx, &sctx->clip_state.atom, &sctx->atoms.s.clip_state, si_emit_clip_state);
3513 si_init_atom(sctx, &sctx->stencil_ref.atom, &sctx->atoms.s.stencil_ref, si_emit_stencil_ref);
3514
3515 sctx->b.b.create_blend_state = si_create_blend_state;
3516 sctx->b.b.bind_blend_state = si_bind_blend_state;
3517 sctx->b.b.delete_blend_state = si_delete_blend_state;
3518 sctx->b.b.set_blend_color = si_set_blend_color;
3519
3520 sctx->b.b.create_rasterizer_state = si_create_rs_state;
3521 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
3522 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
3523
3524 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
3525 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
3526 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
3527
3528 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
3529 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
3530 sctx->custom_blend_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
3531 sctx->custom_blend_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
3532 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
3533
3534 sctx->b.b.set_clip_state = si_set_clip_state;
3535 sctx->b.b.set_stencil_ref = si_set_stencil_ref;
3536
3537 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
3538 sctx->b.b.get_sample_position = cayman_get_sample_position;
3539
3540 sctx->b.b.create_sampler_state = si_create_sampler_state;
3541 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
3542
3543 sctx->b.b.create_sampler_view = si_create_sampler_view;
3544 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
3545
3546 sctx->b.b.set_sample_mask = si_set_sample_mask;
3547
3548 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
3549 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
3550 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
3551 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
3552 sctx->b.b.set_index_buffer = si_set_index_buffer;
3553
3554 sctx->b.b.texture_barrier = si_texture_barrier;
3555 sctx->b.b.memory_barrier = si_memory_barrier;
3556 sctx->b.b.set_min_samples = si_set_min_samples;
3557 sctx->b.b.set_tess_state = si_set_tess_state;
3558
3559 sctx->b.b.set_active_query_state = si_set_active_query_state;
3560 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
3561 sctx->b.save_qbo_state = si_save_qbo_state;
3562 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
3563
3564 sctx->b.b.draw_vbo = si_draw_vbo;
3565
3566 si_init_config(sctx);
3567 }
3568
3569 static uint32_t si_get_bo_metadata_word1(struct r600_common_screen *rscreen)
3570 {
3571 return (ATI_VENDOR_ID << 16) | rscreen->info.pci_id;
3572 }
3573
3574 static void si_query_opaque_metadata(struct r600_common_screen *rscreen,
3575 struct r600_texture *rtex,
3576 struct radeon_bo_metadata *md)
3577 {
3578 struct si_screen *sscreen = (struct si_screen*)rscreen;
3579 struct pipe_resource *res = &rtex->resource.b.b;
3580 static const unsigned char swizzle[] = {
3581 PIPE_SWIZZLE_X,
3582 PIPE_SWIZZLE_Y,
3583 PIPE_SWIZZLE_Z,
3584 PIPE_SWIZZLE_W
3585 };
3586 uint32_t desc[8], i;
3587 bool is_array = util_resource_is_array_texture(res);
3588
3589 /* DRM 2.x.x doesn't support this. */
3590 if (rscreen->info.drm_major != 3)
3591 return;
3592
3593 assert(rtex->dcc_separate_buffer == NULL);
3594 assert(rtex->fmask.size == 0);
3595
3596 /* Metadata image format format version 1:
3597 * [0] = 1 (metadata format identifier)
3598 * [1] = (VENDOR_ID << 16) | PCI_ID
3599 * [2:9] = image descriptor for the whole resource
3600 * [2] is always 0, because the base address is cleared
3601 * [9] is the DCC offset bits [39:8] from the beginning of
3602 * the buffer
3603 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
3604 */
3605
3606 md->metadata[0] = 1; /* metadata image format version 1 */
3607
3608 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
3609 md->metadata[1] = si_get_bo_metadata_word1(rscreen);
3610
3611 si_make_texture_descriptor(sscreen, rtex, true,
3612 res->target, res->format,
3613 swizzle, 0, res->last_level, 0,
3614 is_array ? res->array_size - 1 : 0,
3615 res->width0, res->height0, res->depth0,
3616 desc, NULL);
3617
3618 si_set_mutable_tex_desc_fields(rtex, &rtex->surface.level[0], 0, 0,
3619 rtex->surface.blk_w, false, desc);
3620
3621 /* Clear the base address and set the relative DCC offset. */
3622 desc[0] = 0;
3623 desc[1] &= C_008F14_BASE_ADDRESS_HI;
3624 desc[7] = rtex->dcc_offset >> 8;
3625
3626 /* Dwords [2:9] contain the image descriptor. */
3627 memcpy(&md->metadata[2], desc, sizeof(desc));
3628
3629 /* Dwords [10:..] contain the mipmap level offsets. */
3630 for (i = 0; i <= res->last_level; i++)
3631 md->metadata[10+i] = rtex->surface.level[i].offset >> 8;
3632
3633 md->size_metadata = (11 + res->last_level) * 4;
3634 }
3635
3636 static void si_apply_opaque_metadata(struct r600_common_screen *rscreen,
3637 struct r600_texture *rtex,
3638 struct radeon_bo_metadata *md)
3639 {
3640 uint32_t *desc = &md->metadata[2];
3641
3642 if (rscreen->chip_class < VI)
3643 return;
3644
3645 /* Return if DCC is enabled. The texture should be set up with it
3646 * already.
3647 */
3648 if (md->size_metadata >= 11 * 4 &&
3649 md->metadata[0] != 0 &&
3650 md->metadata[1] == si_get_bo_metadata_word1(rscreen) &&
3651 G_008F28_COMPRESSION_EN(desc[6])) {
3652 assert(rtex->dcc_offset == ((uint64_t)desc[7] << 8));
3653 return;
3654 }
3655
3656 /* Disable DCC. These are always set by texture_from_handle and must
3657 * be cleared here.
3658 */
3659 rtex->dcc_offset = 0;
3660 }
3661
3662 void si_init_screen_state_functions(struct si_screen *sscreen)
3663 {
3664 sscreen->b.b.is_format_supported = si_is_format_supported;
3665 sscreen->b.query_opaque_metadata = si_query_opaque_metadata;
3666 sscreen->b.apply_opaque_metadata = si_apply_opaque_metadata;
3667 }
3668
3669 static void
3670 si_write_harvested_raster_configs(struct si_context *sctx,
3671 struct si_pm4_state *pm4,
3672 unsigned raster_config,
3673 unsigned raster_config_1)
3674 {
3675 unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1);
3676 unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1);
3677 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
3678 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
3679 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
3680 unsigned rb_per_se = num_rb / num_se;
3681 unsigned se_mask[4];
3682 unsigned se;
3683
3684 se_mask[0] = ((1 << rb_per_se) - 1);
3685 se_mask[1] = (se_mask[0] << rb_per_se);
3686 se_mask[2] = (se_mask[1] << rb_per_se);
3687 se_mask[3] = (se_mask[2] << rb_per_se);
3688
3689 se_mask[0] &= rb_mask;
3690 se_mask[1] &= rb_mask;
3691 se_mask[2] &= rb_mask;
3692 se_mask[3] &= rb_mask;
3693
3694 assert(num_se == 1 || num_se == 2 || num_se == 4);
3695 assert(sh_per_se == 1 || sh_per_se == 2);
3696 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
3697
3698 /* XXX: I can't figure out what the *_XSEL and *_YSEL
3699 * fields are for, so I'm leaving them as their default
3700 * values. */
3701
3702 for (se = 0; se < num_se; se++) {
3703 unsigned raster_config_se = raster_config;
3704 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
3705 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
3706 int idx = (se / 2) * 2;
3707
3708 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
3709 raster_config_se &= C_028350_SE_MAP;
3710
3711 if (!se_mask[idx]) {
3712 raster_config_se |=
3713 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
3714 } else {
3715 raster_config_se |=
3716 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
3717 }
3718 }
3719
3720 pkr0_mask &= rb_mask;
3721 pkr1_mask &= rb_mask;
3722 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
3723 raster_config_se &= C_028350_PKR_MAP;
3724
3725 if (!pkr0_mask) {
3726 raster_config_se |=
3727 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
3728 } else {
3729 raster_config_se |=
3730 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
3731 }
3732 }
3733
3734 if (rb_per_se >= 2) {
3735 unsigned rb0_mask = 1 << (se * rb_per_se);
3736 unsigned rb1_mask = rb0_mask << 1;
3737
3738 rb0_mask &= rb_mask;
3739 rb1_mask &= rb_mask;
3740 if (!rb0_mask || !rb1_mask) {
3741 raster_config_se &= C_028350_RB_MAP_PKR0;
3742
3743 if (!rb0_mask) {
3744 raster_config_se |=
3745 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
3746 } else {
3747 raster_config_se |=
3748 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
3749 }
3750 }
3751
3752 if (rb_per_se > 2) {
3753 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
3754 rb1_mask = rb0_mask << 1;
3755 rb0_mask &= rb_mask;
3756 rb1_mask &= rb_mask;
3757 if (!rb0_mask || !rb1_mask) {
3758 raster_config_se &= C_028350_RB_MAP_PKR1;
3759
3760 if (!rb0_mask) {
3761 raster_config_se |=
3762 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
3763 } else {
3764 raster_config_se |=
3765 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
3766 }
3767 }
3768 }
3769 }
3770
3771 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
3772 if (sctx->b.chip_class < CIK)
3773 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3774 SE_INDEX(se) | SH_BROADCAST_WRITES |
3775 INSTANCE_BROADCAST_WRITES);
3776 else
3777 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
3778 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
3779 S_030800_INSTANCE_BROADCAST_WRITES(1));
3780 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
3781 }
3782
3783 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
3784 if (sctx->b.chip_class < CIK)
3785 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3786 SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
3787 INSTANCE_BROADCAST_WRITES);
3788 else {
3789 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
3790 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
3791 S_030800_INSTANCE_BROADCAST_WRITES(1));
3792
3793 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
3794 (!se_mask[2] && !se_mask[3]))) {
3795 raster_config_1 &= C_028354_SE_PAIR_MAP;
3796
3797 if (!se_mask[0] && !se_mask[1]) {
3798 raster_config_1 |=
3799 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
3800 } else {
3801 raster_config_1 |=
3802 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
3803 }
3804 }
3805
3806 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
3807 }
3808 }
3809
3810 static void si_init_config(struct si_context *sctx)
3811 {
3812 struct si_screen *sscreen = sctx->screen;
3813 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
3814 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
3815 unsigned raster_config, raster_config_1;
3816 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
3817 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3818
3819 if (!pm4)
3820 return;
3821
3822 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
3823 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
3824 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
3825 si_pm4_cmd_end(pm4, false);
3826
3827 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
3828 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
3829
3830 /* FIXME calculate these values somehow ??? */
3831 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
3832 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
3833 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
3834
3835 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
3836 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3837
3838 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
3839 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
3840 if (sctx->b.chip_class < CIK)
3841 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
3842 S_008A14_CLIP_VTX_REORDER_ENA(1));
3843
3844 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
3845 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
3846
3847 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
3848
3849 switch (sctx->screen->b.family) {
3850 case CHIP_TAHITI:
3851 case CHIP_PITCAIRN:
3852 raster_config = 0x2a00126a;
3853 raster_config_1 = 0x00000000;
3854 break;
3855 case CHIP_VERDE:
3856 raster_config = 0x0000124a;
3857 raster_config_1 = 0x00000000;
3858 break;
3859 case CHIP_OLAND:
3860 raster_config = 0x00000082;
3861 raster_config_1 = 0x00000000;
3862 break;
3863 case CHIP_HAINAN:
3864 raster_config = 0x00000000;
3865 raster_config_1 = 0x00000000;
3866 break;
3867 case CHIP_BONAIRE:
3868 raster_config = 0x16000012;
3869 raster_config_1 = 0x00000000;
3870 break;
3871 case CHIP_HAWAII:
3872 raster_config = 0x3a00161a;
3873 raster_config_1 = 0x0000002e;
3874 break;
3875 case CHIP_FIJI:
3876 if (sscreen->b.info.cik_macrotile_mode_array[0] == 0x000000e8) {
3877 /* old kernels with old tiling config */
3878 raster_config = 0x16000012;
3879 raster_config_1 = 0x0000002a;
3880 } else {
3881 raster_config = 0x3a00161a;
3882 raster_config_1 = 0x0000002e;
3883 }
3884 break;
3885 case CHIP_POLARIS10:
3886 raster_config = 0x16000012;
3887 raster_config_1 = 0x0000002a;
3888 break;
3889 case CHIP_POLARIS11:
3890 raster_config = 0x16000012;
3891 raster_config_1 = 0x00000000;
3892 break;
3893 case CHIP_TONGA:
3894 raster_config = 0x16000012;
3895 raster_config_1 = 0x0000002a;
3896 break;
3897 case CHIP_ICELAND:
3898 if (num_rb == 1)
3899 raster_config = 0x00000000;
3900 else
3901 raster_config = 0x00000002;
3902 raster_config_1 = 0x00000000;
3903 break;
3904 case CHIP_CARRIZO:
3905 raster_config = 0x00000002;
3906 raster_config_1 = 0x00000000;
3907 break;
3908 case CHIP_KAVERI:
3909 /* KV should be 0x00000002, but that causes problems with radeon */
3910 raster_config = 0x00000000; /* 0x00000002 */
3911 raster_config_1 = 0x00000000;
3912 break;
3913 case CHIP_KABINI:
3914 case CHIP_MULLINS:
3915 case CHIP_STONEY:
3916 raster_config = 0x00000000;
3917 raster_config_1 = 0x00000000;
3918 break;
3919 default:
3920 fprintf(stderr,
3921 "radeonsi: Unknown GPU, using 0 for raster_config\n");
3922 raster_config = 0x00000000;
3923 raster_config_1 = 0x00000000;
3924 break;
3925 }
3926
3927 /* Always use the default config when all backends are enabled
3928 * (or when we failed to determine the enabled backends).
3929 */
3930 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
3931 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
3932 raster_config);
3933 if (sctx->b.chip_class >= CIK)
3934 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
3935 raster_config_1);
3936 } else {
3937 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
3938 }
3939
3940 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
3941 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
3942 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
3943 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
3944 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
3945 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
3946 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
3947
3948 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
3949 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
3950 S_028230_ER_TRI(0xA) |
3951 S_028230_ER_POINT(0xA) |
3952 S_028230_ER_RECT(0xA) |
3953 /* Required by DX10_DIAMOND_TEST_ENA: */
3954 S_028230_ER_LINE_LR(0x1A) |
3955 S_028230_ER_LINE_RL(0x26) |
3956 S_028230_ER_LINE_TB(0xA) |
3957 S_028230_ER_LINE_BT(0xA));
3958 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
3959 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
3960 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
3961 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
3962 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
3963 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
3964 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 0);
3965
3966 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
3967 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
3968 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
3969
3970 if (sctx->b.chip_class >= CIK) {
3971 /* If this is 0, Bonaire can hang even if GS isn't being used.
3972 * Other chips are unaffected. These are suboptimal values,
3973 * but we don't use on-chip GS.
3974 */
3975 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
3976 S_028A44_ES_VERTS_PER_SUBGRP(64) |
3977 S_028A44_GS_PRIMS_PER_SUBGRP(4));
3978
3979 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff));
3980 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
3981 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xffff));
3982 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
3983
3984 if (sscreen->b.info.num_good_compute_units /
3985 (sscreen->b.info.max_se * sscreen->b.info.max_sh_per_se) <= 4) {
3986 /* Too few available compute units per SH. Disallowing
3987 * VS to run on CU0 could hurt us more than late VS
3988 * allocation would help.
3989 *
3990 * LATE_ALLOC_VS = 2 is the highest safe number.
3991 */
3992 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
3993 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
3994 } else {
3995 /* Set LATE_ALLOC_VS == 31. It should be less than
3996 * the number of scratch waves. Limitations:
3997 * - VS can't execute on CU0.
3998 * - If HS writes outputs to LDS, LS can't execute on CU0.
3999 */
4000 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xfffe));
4001 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
4002 }
4003
4004 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
4005 }
4006
4007 if (sctx->b.chip_class >= VI) {
4008 unsigned vgt_tess_distribution;
4009
4010 si_pm4_set_reg(pm4, R_028424_CB_DCC_CONTROL,
4011 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
4012 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
4013 if (sctx->b.family < CHIP_POLARIS10)
4014 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
4015 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
4016
4017 vgt_tess_distribution =
4018 S_028B50_ACCUM_ISOLINE(32) |
4019 S_028B50_ACCUM_TRI(11) |
4020 S_028B50_ACCUM_QUAD(11) |
4021 S_028B50_DONUT_SPLIT(16);
4022
4023 /* Testing with Unigine Heaven extreme tesselation yielded best results
4024 * with TRAP_SPLIT = 3.
4025 */
4026 if (sctx->b.family == CHIP_FIJI ||
4027 sctx->b.family >= CHIP_POLARIS10)
4028 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
4029
4030 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution);
4031 } else {
4032 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
4033 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
4034 }
4035
4036 if (sctx->b.family == CHIP_STONEY)
4037 si_pm4_set_reg(pm4, R_028C40_PA_SC_SHADER_CONTROL, 0);
4038
4039 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
4040 if (sctx->b.chip_class >= CIK)
4041 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, border_color_va >> 40);
4042 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
4043 RADEON_PRIO_BORDER_COLORS);
4044
4045 si_pm4_upload_indirect_buffer(sctx, pm4);
4046 sctx->init_config = pm4;
4047 }