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36dce3815398e2097e093bea061f24fa529489d2
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "gfx9d.h"
27 #include "si_query.h"
28
29 #include "util/u_dual_blend.h"
30 #include "util/u_format.h"
31 #include "util/u_format_s3tc.h"
32 #include "util/u_memory.h"
33 #include "util/u_resource.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/fast_idiv_by_const.h"
36
37 static unsigned si_map_swizzle(unsigned swizzle)
38 {
39 switch (swizzle) {
40 case PIPE_SWIZZLE_Y:
41 return V_008F0C_SQ_SEL_Y;
42 case PIPE_SWIZZLE_Z:
43 return V_008F0C_SQ_SEL_Z;
44 case PIPE_SWIZZLE_W:
45 return V_008F0C_SQ_SEL_W;
46 case PIPE_SWIZZLE_0:
47 return V_008F0C_SQ_SEL_0;
48 case PIPE_SWIZZLE_1:
49 return V_008F0C_SQ_SEL_1;
50 default: /* PIPE_SWIZZLE_X */
51 return V_008F0C_SQ_SEL_X;
52 }
53 }
54
55 /* 12.4 fixed-point */
56 static unsigned si_pack_float_12p4(float x)
57 {
58 return x <= 0 ? 0 :
59 x >= 4096 ? 0xffff : x * 16;
60 }
61
62 /*
63 * Inferred framebuffer and blender state.
64 *
65 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
66 * if there is not enough PS outputs.
67 */
68 static void si_emit_cb_render_state(struct si_context *sctx)
69 {
70 struct radeon_cmdbuf *cs = sctx->gfx_cs;
71 struct si_state_blend *blend = sctx->queued.named.blend;
72 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
73 * but you never know. */
74 uint32_t cb_target_mask = sctx->framebuffer.colorbuf_enabled_4bit;
75 unsigned i;
76
77 if (blend)
78 cb_target_mask &= blend->cb_target_mask;
79
80 /* Avoid a hang that happens when dual source blending is enabled
81 * but there is not enough color outputs. This is undefined behavior,
82 * so disable color writes completely.
83 *
84 * Reproducible with Unigine Heaven 4.0 and drirc missing.
85 */
86 if (blend && blend->dual_src_blend &&
87 sctx->ps_shader.cso &&
88 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
89 cb_target_mask = 0;
90
91 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
92 * I think we don't have to do anything between IBs.
93 */
94 if (sctx->screen->dfsm_allowed &&
95 sctx->last_cb_target_mask != cb_target_mask) {
96 sctx->last_cb_target_mask = cb_target_mask;
97
98 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
99 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
100 }
101
102 unsigned initial_cdw = cs->current.cdw;
103 radeon_opt_set_context_reg(sctx, R_028238_CB_TARGET_MASK,
104 SI_TRACKED_CB_TARGET_MASK, cb_target_mask);
105
106 if (sctx->chip_class >= VI) {
107 /* DCC MSAA workaround for blending.
108 * Alternatively, we can set CB_COLORi_DCC_CONTROL.OVERWRITE_-
109 * COMBINER_DISABLE, but that would be more complicated.
110 */
111 bool oc_disable = (sctx->chip_class == VI ||
112 sctx->chip_class == GFX9) &&
113 blend &&
114 blend->blend_enable_4bit & cb_target_mask &&
115 sctx->framebuffer.nr_samples >= 2;
116
117 radeon_opt_set_context_reg(
118 sctx, R_028424_CB_DCC_CONTROL,
119 SI_TRACKED_CB_DCC_CONTROL,
120 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
121 S_028424_OVERWRITE_COMBINER_WATERMARK(4) |
122 S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable));
123 }
124
125 /* RB+ register settings. */
126 if (sctx->screen->rbplus_allowed) {
127 unsigned spi_shader_col_format =
128 sctx->ps_shader.cso ?
129 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format : 0;
130 unsigned sx_ps_downconvert = 0;
131 unsigned sx_blend_opt_epsilon = 0;
132 unsigned sx_blend_opt_control = 0;
133
134 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
135 struct si_surface *surf =
136 (struct si_surface*)sctx->framebuffer.state.cbufs[i];
137 unsigned format, swap, spi_format, colormask;
138 bool has_alpha, has_rgb;
139
140 if (!surf)
141 continue;
142
143 format = G_028C70_FORMAT(surf->cb_color_info);
144 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
145 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
146 colormask = (cb_target_mask >> (i * 4)) & 0xf;
147
148 /* Set if RGB and A are present. */
149 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
150
151 if (format == V_028C70_COLOR_8 ||
152 format == V_028C70_COLOR_16 ||
153 format == V_028C70_COLOR_32)
154 has_rgb = !has_alpha;
155 else
156 has_rgb = true;
157
158 /* Check the colormask and export format. */
159 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
160 has_rgb = false;
161 if (!(colormask & PIPE_MASK_A))
162 has_alpha = false;
163
164 if (spi_format == V_028714_SPI_SHADER_ZERO) {
165 has_rgb = false;
166 has_alpha = false;
167 }
168
169 /* Disable value checking for disabled channels. */
170 if (!has_rgb)
171 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
172 if (!has_alpha)
173 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
174
175 /* Enable down-conversion for 32bpp and smaller formats. */
176 switch (format) {
177 case V_028C70_COLOR_8:
178 case V_028C70_COLOR_8_8:
179 case V_028C70_COLOR_8_8_8_8:
180 /* For 1 and 2-channel formats, use the superset thereof. */
181 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
182 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
183 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
184 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
185 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
186 }
187 break;
188
189 case V_028C70_COLOR_5_6_5:
190 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
191 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
192 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
193 }
194 break;
195
196 case V_028C70_COLOR_1_5_5_5:
197 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
198 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
199 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
200 }
201 break;
202
203 case V_028C70_COLOR_4_4_4_4:
204 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
205 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
206 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
207 }
208 break;
209
210 case V_028C70_COLOR_32:
211 if (swap == V_028C70_SWAP_STD &&
212 spi_format == V_028714_SPI_SHADER_32_R)
213 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
214 else if (swap == V_028C70_SWAP_ALT_REV &&
215 spi_format == V_028714_SPI_SHADER_32_AR)
216 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
217 break;
218
219 case V_028C70_COLOR_16:
220 case V_028C70_COLOR_16_16:
221 /* For 1-channel formats, use the superset thereof. */
222 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
223 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
224 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
225 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
226 if (swap == V_028C70_SWAP_STD ||
227 swap == V_028C70_SWAP_STD_REV)
228 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
229 else
230 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
231 }
232 break;
233
234 case V_028C70_COLOR_10_11_11:
235 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
236 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
237 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
238 }
239 break;
240
241 case V_028C70_COLOR_2_10_10_10:
242 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
243 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
244 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
245 }
246 break;
247 }
248 }
249
250 /* SX_PS_DOWNCONVERT, SX_BLEND_OPT_EPSILON, SX_BLEND_OPT_CONTROL */
251 radeon_opt_set_context_reg3(sctx, R_028754_SX_PS_DOWNCONVERT,
252 SI_TRACKED_SX_PS_DOWNCONVERT,
253 sx_ps_downconvert, sx_blend_opt_epsilon,
254 sx_blend_opt_control);
255 }
256 if (initial_cdw != cs->current.cdw)
257 sctx->context_roll_counter++;
258 }
259
260 /*
261 * Blender functions
262 */
263
264 static uint32_t si_translate_blend_function(int blend_func)
265 {
266 switch (blend_func) {
267 case PIPE_BLEND_ADD:
268 return V_028780_COMB_DST_PLUS_SRC;
269 case PIPE_BLEND_SUBTRACT:
270 return V_028780_COMB_SRC_MINUS_DST;
271 case PIPE_BLEND_REVERSE_SUBTRACT:
272 return V_028780_COMB_DST_MINUS_SRC;
273 case PIPE_BLEND_MIN:
274 return V_028780_COMB_MIN_DST_SRC;
275 case PIPE_BLEND_MAX:
276 return V_028780_COMB_MAX_DST_SRC;
277 default:
278 PRINT_ERR("Unknown blend function %d\n", blend_func);
279 assert(0);
280 break;
281 }
282 return 0;
283 }
284
285 static uint32_t si_translate_blend_factor(int blend_fact)
286 {
287 switch (blend_fact) {
288 case PIPE_BLENDFACTOR_ONE:
289 return V_028780_BLEND_ONE;
290 case PIPE_BLENDFACTOR_SRC_COLOR:
291 return V_028780_BLEND_SRC_COLOR;
292 case PIPE_BLENDFACTOR_SRC_ALPHA:
293 return V_028780_BLEND_SRC_ALPHA;
294 case PIPE_BLENDFACTOR_DST_ALPHA:
295 return V_028780_BLEND_DST_ALPHA;
296 case PIPE_BLENDFACTOR_DST_COLOR:
297 return V_028780_BLEND_DST_COLOR;
298 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
299 return V_028780_BLEND_SRC_ALPHA_SATURATE;
300 case PIPE_BLENDFACTOR_CONST_COLOR:
301 return V_028780_BLEND_CONSTANT_COLOR;
302 case PIPE_BLENDFACTOR_CONST_ALPHA:
303 return V_028780_BLEND_CONSTANT_ALPHA;
304 case PIPE_BLENDFACTOR_ZERO:
305 return V_028780_BLEND_ZERO;
306 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
307 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
308 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
309 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
310 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
311 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
312 case PIPE_BLENDFACTOR_INV_DST_COLOR:
313 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
314 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
315 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
316 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
317 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
318 case PIPE_BLENDFACTOR_SRC1_COLOR:
319 return V_028780_BLEND_SRC1_COLOR;
320 case PIPE_BLENDFACTOR_SRC1_ALPHA:
321 return V_028780_BLEND_SRC1_ALPHA;
322 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
323 return V_028780_BLEND_INV_SRC1_COLOR;
324 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
325 return V_028780_BLEND_INV_SRC1_ALPHA;
326 default:
327 PRINT_ERR("Bad blend factor %d not supported!\n", blend_fact);
328 assert(0);
329 break;
330 }
331 return 0;
332 }
333
334 static uint32_t si_translate_blend_opt_function(int blend_func)
335 {
336 switch (blend_func) {
337 case PIPE_BLEND_ADD:
338 return V_028760_OPT_COMB_ADD;
339 case PIPE_BLEND_SUBTRACT:
340 return V_028760_OPT_COMB_SUBTRACT;
341 case PIPE_BLEND_REVERSE_SUBTRACT:
342 return V_028760_OPT_COMB_REVSUBTRACT;
343 case PIPE_BLEND_MIN:
344 return V_028760_OPT_COMB_MIN;
345 case PIPE_BLEND_MAX:
346 return V_028760_OPT_COMB_MAX;
347 default:
348 return V_028760_OPT_COMB_BLEND_DISABLED;
349 }
350 }
351
352 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
353 {
354 switch (blend_fact) {
355 case PIPE_BLENDFACTOR_ZERO:
356 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
357 case PIPE_BLENDFACTOR_ONE:
358 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
359 case PIPE_BLENDFACTOR_SRC_COLOR:
360 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
361 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
362 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
363 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
364 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
365 case PIPE_BLENDFACTOR_SRC_ALPHA:
366 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
367 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
368 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
369 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
370 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
371 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
372 default:
373 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
374 }
375 }
376
377 static void si_blend_check_commutativity(struct si_screen *sscreen,
378 struct si_state_blend *blend,
379 enum pipe_blend_func func,
380 enum pipe_blendfactor src,
381 enum pipe_blendfactor dst,
382 unsigned chanmask)
383 {
384 /* Src factor is allowed when it does not depend on Dst */
385 static const uint32_t src_allowed =
386 (1u << PIPE_BLENDFACTOR_ONE) |
387 (1u << PIPE_BLENDFACTOR_SRC_COLOR) |
388 (1u << PIPE_BLENDFACTOR_SRC_ALPHA) |
389 (1u << PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE) |
390 (1u << PIPE_BLENDFACTOR_CONST_COLOR) |
391 (1u << PIPE_BLENDFACTOR_CONST_ALPHA) |
392 (1u << PIPE_BLENDFACTOR_SRC1_COLOR) |
393 (1u << PIPE_BLENDFACTOR_SRC1_ALPHA) |
394 (1u << PIPE_BLENDFACTOR_ZERO) |
395 (1u << PIPE_BLENDFACTOR_INV_SRC_COLOR) |
396 (1u << PIPE_BLENDFACTOR_INV_SRC_ALPHA) |
397 (1u << PIPE_BLENDFACTOR_INV_CONST_COLOR) |
398 (1u << PIPE_BLENDFACTOR_INV_CONST_ALPHA) |
399 (1u << PIPE_BLENDFACTOR_INV_SRC1_COLOR) |
400 (1u << PIPE_BLENDFACTOR_INV_SRC1_ALPHA);
401
402 if (dst == PIPE_BLENDFACTOR_ONE &&
403 (src_allowed & (1u << src))) {
404 /* Addition is commutative, but floating point addition isn't
405 * associative: subtle changes can be introduced via different
406 * rounding.
407 *
408 * Out-of-order is also non-deterministic, which means that
409 * this breaks OpenGL invariance requirements. So only enable
410 * out-of-order additive blending if explicitly allowed by a
411 * setting.
412 */
413 if (func == PIPE_BLEND_MAX || func == PIPE_BLEND_MIN ||
414 (func == PIPE_BLEND_ADD && sscreen->commutative_blend_add))
415 blend->commutative_4bit |= chanmask;
416 }
417 }
418
419 /**
420 * Get rid of DST in the blend factors by commuting the operands:
421 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
422 */
423 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
424 unsigned *dst_factor, unsigned expected_dst,
425 unsigned replacement_src)
426 {
427 if (*src_factor == expected_dst &&
428 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
429 *src_factor = PIPE_BLENDFACTOR_ZERO;
430 *dst_factor = replacement_src;
431
432 /* Commuting the operands requires reversing subtractions. */
433 if (*func == PIPE_BLEND_SUBTRACT)
434 *func = PIPE_BLEND_REVERSE_SUBTRACT;
435 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
436 *func = PIPE_BLEND_SUBTRACT;
437 }
438 }
439
440 static bool si_blend_factor_uses_dst(unsigned factor)
441 {
442 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
443 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
444 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
445 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
446 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
447 }
448
449 static void *si_create_blend_state_mode(struct pipe_context *ctx,
450 const struct pipe_blend_state *state,
451 unsigned mode)
452 {
453 struct si_context *sctx = (struct si_context*)ctx;
454 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
455 struct si_pm4_state *pm4 = &blend->pm4;
456 uint32_t sx_mrt_blend_opt[8] = {0};
457 uint32_t color_control = 0;
458
459 if (!blend)
460 return NULL;
461
462 blend->alpha_to_coverage = state->alpha_to_coverage;
463 blend->alpha_to_one = state->alpha_to_one;
464 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
465 blend->logicop_enable = state->logicop_enable;
466
467 if (state->logicop_enable) {
468 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
469 } else {
470 color_control |= S_028808_ROP3(0xcc);
471 }
472
473 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
474 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
475 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
476 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
477 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
478 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
479
480 if (state->alpha_to_coverage)
481 blend->need_src_alpha_4bit |= 0xf;
482
483 blend->cb_target_mask = 0;
484 blend->cb_target_enabled_4bit = 0;
485
486 for (int i = 0; i < 8; i++) {
487 /* state->rt entries > 0 only written if independent blending */
488 const int j = state->independent_blend_enable ? i : 0;
489
490 unsigned eqRGB = state->rt[j].rgb_func;
491 unsigned srcRGB = state->rt[j].rgb_src_factor;
492 unsigned dstRGB = state->rt[j].rgb_dst_factor;
493 unsigned eqA = state->rt[j].alpha_func;
494 unsigned srcA = state->rt[j].alpha_src_factor;
495 unsigned dstA = state->rt[j].alpha_dst_factor;
496
497 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
498 unsigned blend_cntl = 0;
499
500 sx_mrt_blend_opt[i] =
501 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
502 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
503
504 /* Only set dual source blending for MRT0 to avoid a hang. */
505 if (i >= 1 && blend->dual_src_blend) {
506 /* Vulkan does this for dual source blending. */
507 if (i == 1)
508 blend_cntl |= S_028780_ENABLE(1);
509
510 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
511 continue;
512 }
513
514 /* Only addition and subtraction equations are supported with
515 * dual source blending.
516 */
517 if (blend->dual_src_blend &&
518 (eqRGB == PIPE_BLEND_MIN || eqRGB == PIPE_BLEND_MAX ||
519 eqA == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MAX)) {
520 assert(!"Unsupported equation for dual source blending");
521 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
522 continue;
523 }
524
525 /* cb_render_state will disable unused ones */
526 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
527 if (state->rt[j].colormask)
528 blend->cb_target_enabled_4bit |= 0xf << (4 * i);
529
530 if (!state->rt[j].colormask || !state->rt[j].blend_enable) {
531 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
532 continue;
533 }
534
535 si_blend_check_commutativity(sctx->screen, blend,
536 eqRGB, srcRGB, dstRGB, 0x7 << (4 * i));
537 si_blend_check_commutativity(sctx->screen, blend,
538 eqA, srcA, dstA, 0x8 << (4 * i));
539
540 /* Blending optimizations for RB+.
541 * These transformations don't change the behavior.
542 *
543 * First, get rid of DST in the blend factors:
544 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
545 */
546 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
547 PIPE_BLENDFACTOR_DST_COLOR,
548 PIPE_BLENDFACTOR_SRC_COLOR);
549 si_blend_remove_dst(&eqA, &srcA, &dstA,
550 PIPE_BLENDFACTOR_DST_COLOR,
551 PIPE_BLENDFACTOR_SRC_COLOR);
552 si_blend_remove_dst(&eqA, &srcA, &dstA,
553 PIPE_BLENDFACTOR_DST_ALPHA,
554 PIPE_BLENDFACTOR_SRC_ALPHA);
555
556 /* Look up the ideal settings from tables. */
557 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
558 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
559 srcA_opt = si_translate_blend_opt_factor(srcA, true);
560 dstA_opt = si_translate_blend_opt_factor(dstA, true);
561
562 /* Handle interdependencies. */
563 if (si_blend_factor_uses_dst(srcRGB))
564 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
565 if (si_blend_factor_uses_dst(srcA))
566 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
567
568 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
569 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
570 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
571 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
572 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
573
574 /* Set the final value. */
575 sx_mrt_blend_opt[i] =
576 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
577 S_028760_COLOR_DST_OPT(dstRGB_opt) |
578 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
579 S_028760_ALPHA_SRC_OPT(srcA_opt) |
580 S_028760_ALPHA_DST_OPT(dstA_opt) |
581 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
582
583 /* Set blend state. */
584 blend_cntl |= S_028780_ENABLE(1);
585 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
586 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
587 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
588
589 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
590 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
591 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
592 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
593 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
594 }
595 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
596
597 blend->blend_enable_4bit |= 0xfu << (i * 4);
598
599 /* This is only important for formats without alpha. */
600 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
601 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
602 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
603 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
604 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
605 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
606 blend->need_src_alpha_4bit |= 0xfu << (i * 4);
607 }
608
609 if (blend->cb_target_mask) {
610 color_control |= S_028808_MODE(mode);
611 } else {
612 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
613 }
614
615 if (sctx->screen->rbplus_allowed) {
616 /* Disable RB+ blend optimizations for dual source blending.
617 * Vulkan does this.
618 */
619 if (blend->dual_src_blend) {
620 for (int i = 0; i < 8; i++) {
621 sx_mrt_blend_opt[i] =
622 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
623 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
624 }
625 }
626
627 for (int i = 0; i < 8; i++)
628 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
629 sx_mrt_blend_opt[i]);
630
631 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
632 if (blend->dual_src_blend || state->logicop_enable ||
633 mode == V_028808_CB_RESOLVE)
634 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
635 }
636
637 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
638 return blend;
639 }
640
641 static void *si_create_blend_state(struct pipe_context *ctx,
642 const struct pipe_blend_state *state)
643 {
644 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
645 }
646
647 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
648 {
649 struct si_context *sctx = (struct si_context *)ctx;
650 struct si_state_blend *old_blend = sctx->queued.named.blend;
651 struct si_state_blend *blend = (struct si_state_blend *)state;
652
653 if (!state)
654 return;
655
656 si_pm4_bind_state(sctx, blend, state);
657
658 if (!old_blend ||
659 old_blend->cb_target_mask != blend->cb_target_mask ||
660 old_blend->dual_src_blend != blend->dual_src_blend ||
661 (old_blend->blend_enable_4bit != blend->blend_enable_4bit &&
662 sctx->framebuffer.nr_samples >= 2 &&
663 sctx->screen->dcc_msaa_allowed))
664 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
665
666 if (!old_blend ||
667 old_blend->cb_target_mask != blend->cb_target_mask ||
668 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
669 old_blend->alpha_to_one != blend->alpha_to_one ||
670 old_blend->dual_src_blend != blend->dual_src_blend ||
671 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
672 old_blend->need_src_alpha_4bit != blend->need_src_alpha_4bit)
673 sctx->do_update_shaders = true;
674
675 if (sctx->screen->dpbb_allowed &&
676 (!old_blend ||
677 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
678 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
679 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit))
680 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
681
682 if (sctx->screen->has_out_of_order_rast &&
683 (!old_blend ||
684 (old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
685 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit ||
686 old_blend->commutative_4bit != blend->commutative_4bit ||
687 old_blend->logicop_enable != blend->logicop_enable)))
688 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
689 }
690
691 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
692 {
693 struct si_context *sctx = (struct si_context *)ctx;
694 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
695 }
696
697 static void si_set_blend_color(struct pipe_context *ctx,
698 const struct pipe_blend_color *state)
699 {
700 struct si_context *sctx = (struct si_context *)ctx;
701 static const struct pipe_blend_color zeros;
702
703 sctx->blend_color.state = *state;
704 sctx->blend_color.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
705 si_mark_atom_dirty(sctx, &sctx->atoms.s.blend_color);
706 }
707
708 static void si_emit_blend_color(struct si_context *sctx)
709 {
710 struct radeon_cmdbuf *cs = sctx->gfx_cs;
711
712 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
713 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
714 }
715
716 /*
717 * Clipping
718 */
719
720 static void si_set_clip_state(struct pipe_context *ctx,
721 const struct pipe_clip_state *state)
722 {
723 struct si_context *sctx = (struct si_context *)ctx;
724 struct pipe_constant_buffer cb;
725 static const struct pipe_clip_state zeros;
726
727 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
728 return;
729
730 sctx->clip_state.state = *state;
731 sctx->clip_state.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
732 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_state);
733
734 cb.buffer = NULL;
735 cb.user_buffer = state->ucp;
736 cb.buffer_offset = 0;
737 cb.buffer_size = 4*4*8;
738 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
739 pipe_resource_reference(&cb.buffer, NULL);
740 }
741
742 static void si_emit_clip_state(struct si_context *sctx)
743 {
744 struct radeon_cmdbuf *cs = sctx->gfx_cs;
745
746 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
747 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
748 }
749
750 static void si_emit_clip_regs(struct si_context *sctx)
751 {
752 struct si_shader *vs = si_get_vs_state(sctx);
753 struct si_shader_selector *vs_sel = vs->selector;
754 struct tgsi_shader_info *info = &vs_sel->info;
755 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
756 unsigned window_space =
757 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
758 unsigned clipdist_mask = vs_sel->clipdist_mask;
759 unsigned ucp_mask = clipdist_mask ? 0 : rs->clip_plane_enable & SIX_BITS;
760 unsigned culldist_mask = vs_sel->culldist_mask;
761 unsigned total_mask;
762
763 if (vs->key.opt.clip_disable) {
764 assert(!info->culldist_writemask);
765 clipdist_mask = 0;
766 culldist_mask = 0;
767 }
768 total_mask = clipdist_mask | culldist_mask;
769
770 /* Clip distances on points have no effect, so need to be implemented
771 * as cull distances. This applies for the clipvertex case as well.
772 *
773 * Setting this for primitives other than points should have no adverse
774 * effects.
775 */
776 clipdist_mask &= rs->clip_plane_enable;
777 culldist_mask |= clipdist_mask;
778
779 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
780 radeon_opt_set_context_reg(sctx, R_02881C_PA_CL_VS_OUT_CNTL,
781 SI_TRACKED_PA_CL_VS_OUT_CNTL,
782 vs_sel->pa_cl_vs_out_cntl |
783 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0F) != 0) |
784 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xF0) != 0) |
785 clipdist_mask | (culldist_mask << 8));
786 radeon_opt_set_context_reg(sctx, R_028810_PA_CL_CLIP_CNTL,
787 SI_TRACKED_PA_CL_CLIP_CNTL,
788 rs->pa_cl_clip_cntl |
789 ucp_mask |
790 S_028810_CLIP_DISABLE(window_space));
791
792 if (initial_cdw != sctx->gfx_cs->current.cdw)
793 sctx->context_roll_counter++;
794 }
795
796 /*
797 * inferred state between framebuffer and rasterizer
798 */
799 static void si_update_poly_offset_state(struct si_context *sctx)
800 {
801 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
802
803 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf) {
804 si_pm4_bind_state(sctx, poly_offset, NULL);
805 return;
806 }
807
808 /* Use the user format, not db_render_format, so that the polygon
809 * offset behaves as expected by applications.
810 */
811 switch (sctx->framebuffer.state.zsbuf->texture->format) {
812 case PIPE_FORMAT_Z16_UNORM:
813 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
814 break;
815 default: /* 24-bit */
816 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
817 break;
818 case PIPE_FORMAT_Z32_FLOAT:
819 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
820 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
821 break;
822 }
823 }
824
825 /*
826 * Rasterizer
827 */
828
829 static uint32_t si_translate_fill(uint32_t func)
830 {
831 switch(func) {
832 case PIPE_POLYGON_MODE_FILL:
833 return V_028814_X_DRAW_TRIANGLES;
834 case PIPE_POLYGON_MODE_LINE:
835 return V_028814_X_DRAW_LINES;
836 case PIPE_POLYGON_MODE_POINT:
837 return V_028814_X_DRAW_POINTS;
838 default:
839 assert(0);
840 return V_028814_X_DRAW_POINTS;
841 }
842 }
843
844 static void *si_create_rs_state(struct pipe_context *ctx,
845 const struct pipe_rasterizer_state *state)
846 {
847 struct si_screen *sscreen = ((struct si_context *)ctx)->screen;
848 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
849 struct si_pm4_state *pm4 = &rs->pm4;
850 unsigned tmp, i;
851 float psize_min, psize_max;
852
853 if (!rs) {
854 return NULL;
855 }
856
857 rs->scissor_enable = state->scissor;
858 rs->clip_halfz = state->clip_halfz;
859 rs->two_side = state->light_twoside;
860 rs->multisample_enable = state->multisample;
861 rs->force_persample_interp = state->force_persample_interp;
862 rs->clip_plane_enable = state->clip_plane_enable;
863 rs->half_pixel_center = state->half_pixel_center;
864 rs->line_stipple_enable = state->line_stipple_enable;
865 rs->poly_stipple_enable = state->poly_stipple_enable;
866 rs->line_smooth = state->line_smooth;
867 rs->line_width = state->line_width;
868 rs->poly_smooth = state->poly_smooth;
869 rs->uses_poly_offset = state->offset_point || state->offset_line ||
870 state->offset_tri;
871 rs->clamp_fragment_color = state->clamp_fragment_color;
872 rs->clamp_vertex_color = state->clamp_vertex_color;
873 rs->flatshade = state->flatshade;
874 rs->sprite_coord_enable = state->sprite_coord_enable;
875 rs->rasterizer_discard = state->rasterizer_discard;
876 rs->pa_sc_line_stipple = state->line_stipple_enable ?
877 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
878 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
879 rs->pa_cl_clip_cntl =
880 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
881 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip_near) |
882 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip_far) |
883 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
884 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
885
886 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
887 S_0286D4_FLAT_SHADE_ENA(1) |
888 S_0286D4_PNT_SPRITE_ENA(state->point_quad_rasterization) |
889 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
890 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
891 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
892 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
893 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
894
895 /* point size 12.4 fixed point */
896 tmp = (unsigned)(state->point_size * 8.0);
897 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
898
899 if (state->point_size_per_vertex) {
900 psize_min = util_get_min_point_size(state);
901 psize_max = SI_MAX_POINT_SIZE;
902 } else {
903 /* Force the point size to be as if the vertex output was disabled. */
904 psize_min = state->point_size;
905 psize_max = state->point_size;
906 }
907 rs->max_point_size = psize_max;
908
909 /* Divide by two, because 0.5 = 1 pixel. */
910 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
911 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
912 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
913
914 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL,
915 S_028A08_WIDTH(si_pack_float_12p4(state->line_width/2)));
916 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
917 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
918 S_028A48_MSAA_ENABLE(state->multisample ||
919 state->poly_smooth ||
920 state->line_smooth) |
921 S_028A48_VPORT_SCISSOR_ENABLE(1) |
922 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen->info.chip_class >= GFX9));
923
924 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
925 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
926 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
927 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
928 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
929 S_028814_FACE(!state->front_ccw) |
930 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
931 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
932 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
933 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
934 state->fill_back != PIPE_POLYGON_MODE_FILL) |
935 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
936 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
937
938 if (!rs->uses_poly_offset)
939 return rs;
940
941 rs->pm4_poly_offset = CALLOC(3, sizeof(struct si_pm4_state));
942 if (!rs->pm4_poly_offset) {
943 FREE(rs);
944 return NULL;
945 }
946
947 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
948 for (i = 0; i < 3; i++) {
949 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
950 float offset_units = state->offset_units;
951 float offset_scale = state->offset_scale * 16.0f;
952 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
953
954 if (!state->offset_units_unscaled) {
955 switch (i) {
956 case 0: /* 16-bit zbuffer */
957 offset_units *= 4.0f;
958 pa_su_poly_offset_db_fmt_cntl =
959 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
960 break;
961 case 1: /* 24-bit zbuffer */
962 offset_units *= 2.0f;
963 pa_su_poly_offset_db_fmt_cntl =
964 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
965 break;
966 case 2: /* 32-bit zbuffer */
967 offset_units *= 1.0f;
968 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
969 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
970 break;
971 }
972 }
973
974 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
975 fui(offset_scale));
976 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
977 fui(offset_units));
978 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
979 fui(offset_scale));
980 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
981 fui(offset_units));
982 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
983 pa_su_poly_offset_db_fmt_cntl);
984 }
985
986 return rs;
987 }
988
989 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
990 {
991 struct si_context *sctx = (struct si_context *)ctx;
992 struct si_state_rasterizer *old_rs =
993 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
994 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
995
996 if (!state)
997 return;
998
999 if (!old_rs || old_rs->multisample_enable != rs->multisample_enable) {
1000 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1001
1002 /* Update the small primitive filter workaround if necessary. */
1003 if (sctx->screen->has_msaa_sample_loc_bug &&
1004 sctx->framebuffer.nr_samples > 1)
1005 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
1006 }
1007
1008 sctx->current_vs_state &= C_VS_STATE_CLAMP_VERTEX_COLOR;
1009 sctx->current_vs_state |= S_VS_STATE_CLAMP_VERTEX_COLOR(rs->clamp_vertex_color);
1010
1011 si_pm4_bind_state(sctx, rasterizer, rs);
1012 si_update_poly_offset_state(sctx);
1013
1014 if (!old_rs ||
1015 old_rs->scissor_enable != rs->scissor_enable) {
1016 sctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
1017 si_mark_atom_dirty(sctx, &sctx->atoms.s.scissors);
1018 }
1019
1020 if (!old_rs ||
1021 old_rs->line_width != rs->line_width ||
1022 old_rs->max_point_size != rs->max_point_size ||
1023 old_rs->half_pixel_center != rs->half_pixel_center)
1024 si_mark_atom_dirty(sctx, &sctx->atoms.s.guardband);
1025
1026 if (!old_rs ||
1027 old_rs->clip_halfz != rs->clip_halfz) {
1028 sctx->viewports.depth_range_dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
1029 si_mark_atom_dirty(sctx, &sctx->atoms.s.viewports);
1030 }
1031
1032 if (!old_rs ||
1033 old_rs->clip_plane_enable != rs->clip_plane_enable ||
1034 old_rs->pa_cl_clip_cntl != rs->pa_cl_clip_cntl)
1035 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
1036
1037 sctx->ia_multi_vgt_param_key.u.line_stipple_enabled =
1038 rs->line_stipple_enable;
1039
1040 if (!old_rs ||
1041 old_rs->clip_plane_enable != rs->clip_plane_enable ||
1042 old_rs->rasterizer_discard != rs->rasterizer_discard ||
1043 old_rs->sprite_coord_enable != rs->sprite_coord_enable ||
1044 old_rs->flatshade != rs->flatshade ||
1045 old_rs->two_side != rs->two_side ||
1046 old_rs->multisample_enable != rs->multisample_enable ||
1047 old_rs->poly_stipple_enable != rs->poly_stipple_enable ||
1048 old_rs->poly_smooth != rs->poly_smooth ||
1049 old_rs->line_smooth != rs->line_smooth ||
1050 old_rs->clamp_fragment_color != rs->clamp_fragment_color ||
1051 old_rs->force_persample_interp != rs->force_persample_interp)
1052 sctx->do_update_shaders = true;
1053 }
1054
1055 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
1056 {
1057 struct si_context *sctx = (struct si_context *)ctx;
1058 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
1059
1060 if (sctx->queued.named.rasterizer == state)
1061 si_pm4_bind_state(sctx, poly_offset, NULL);
1062
1063 FREE(rs->pm4_poly_offset);
1064 si_pm4_delete_state(sctx, rasterizer, rs);
1065 }
1066
1067 /*
1068 * infeered state between dsa and stencil ref
1069 */
1070 static void si_emit_stencil_ref(struct si_context *sctx)
1071 {
1072 struct radeon_cmdbuf *cs = sctx->gfx_cs;
1073 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
1074 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
1075
1076 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
1077 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
1078 S_028430_STENCILMASK(dsa->valuemask[0]) |
1079 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
1080 S_028430_STENCILOPVAL(1));
1081 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
1082 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
1083 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
1084 S_028434_STENCILOPVAL_BF(1));
1085 }
1086
1087 static void si_set_stencil_ref(struct pipe_context *ctx,
1088 const struct pipe_stencil_ref *state)
1089 {
1090 struct si_context *sctx = (struct si_context *)ctx;
1091
1092 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
1093 return;
1094
1095 sctx->stencil_ref.state = *state;
1096 si_mark_atom_dirty(sctx, &sctx->atoms.s.stencil_ref);
1097 }
1098
1099
1100 /*
1101 * DSA
1102 */
1103
1104 static uint32_t si_translate_stencil_op(int s_op)
1105 {
1106 switch (s_op) {
1107 case PIPE_STENCIL_OP_KEEP:
1108 return V_02842C_STENCIL_KEEP;
1109 case PIPE_STENCIL_OP_ZERO:
1110 return V_02842C_STENCIL_ZERO;
1111 case PIPE_STENCIL_OP_REPLACE:
1112 return V_02842C_STENCIL_REPLACE_TEST;
1113 case PIPE_STENCIL_OP_INCR:
1114 return V_02842C_STENCIL_ADD_CLAMP;
1115 case PIPE_STENCIL_OP_DECR:
1116 return V_02842C_STENCIL_SUB_CLAMP;
1117 case PIPE_STENCIL_OP_INCR_WRAP:
1118 return V_02842C_STENCIL_ADD_WRAP;
1119 case PIPE_STENCIL_OP_DECR_WRAP:
1120 return V_02842C_STENCIL_SUB_WRAP;
1121 case PIPE_STENCIL_OP_INVERT:
1122 return V_02842C_STENCIL_INVERT;
1123 default:
1124 PRINT_ERR("Unknown stencil op %d", s_op);
1125 assert(0);
1126 break;
1127 }
1128 return 0;
1129 }
1130
1131 static bool si_dsa_writes_stencil(const struct pipe_stencil_state *s)
1132 {
1133 return s->enabled && s->writemask &&
1134 (s->fail_op != PIPE_STENCIL_OP_KEEP ||
1135 s->zfail_op != PIPE_STENCIL_OP_KEEP ||
1136 s->zpass_op != PIPE_STENCIL_OP_KEEP);
1137 }
1138
1139 static bool si_order_invariant_stencil_op(enum pipe_stencil_op op)
1140 {
1141 /* REPLACE is normally order invariant, except when the stencil
1142 * reference value is written by the fragment shader. Tracking this
1143 * interaction does not seem worth the effort, so be conservative. */
1144 return op != PIPE_STENCIL_OP_INCR &&
1145 op != PIPE_STENCIL_OP_DECR &&
1146 op != PIPE_STENCIL_OP_REPLACE;
1147 }
1148
1149 /* Compute whether, assuming Z writes are disabled, this stencil state is order
1150 * invariant in the sense that the set of passing fragments as well as the
1151 * final stencil buffer result does not depend on the order of fragments. */
1152 static bool si_order_invariant_stencil_state(const struct pipe_stencil_state *state)
1153 {
1154 return !state->enabled || !state->writemask ||
1155 /* The following assumes that Z writes are disabled. */
1156 (state->func == PIPE_FUNC_ALWAYS &&
1157 si_order_invariant_stencil_op(state->zpass_op) &&
1158 si_order_invariant_stencil_op(state->zfail_op)) ||
1159 (state->func == PIPE_FUNC_NEVER &&
1160 si_order_invariant_stencil_op(state->fail_op));
1161 }
1162
1163 static void *si_create_dsa_state(struct pipe_context *ctx,
1164 const struct pipe_depth_stencil_alpha_state *state)
1165 {
1166 struct si_context *sctx = (struct si_context *)ctx;
1167 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
1168 struct si_pm4_state *pm4 = &dsa->pm4;
1169 unsigned db_depth_control;
1170 uint32_t db_stencil_control = 0;
1171
1172 if (!dsa) {
1173 return NULL;
1174 }
1175
1176 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
1177 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
1178 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
1179 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
1180
1181 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
1182 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
1183 S_028800_ZFUNC(state->depth.func) |
1184 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
1185
1186 /* stencil */
1187 if (state->stencil[0].enabled) {
1188 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1189 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
1190 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
1191 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
1192 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
1193
1194 if (state->stencil[1].enabled) {
1195 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1196 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1197 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
1198 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
1199 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
1200 }
1201 }
1202
1203 /* alpha */
1204 if (state->alpha.enabled) {
1205 dsa->alpha_func = state->alpha.func;
1206
1207 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1208 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
1209 } else {
1210 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1211 }
1212
1213 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1214 if (state->stencil[0].enabled)
1215 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1216 if (state->depth.bounds_test) {
1217 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1218 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1219 }
1220
1221 dsa->depth_enabled = state->depth.enabled;
1222 dsa->depth_write_enabled = state->depth.enabled &&
1223 state->depth.writemask;
1224 dsa->stencil_enabled = state->stencil[0].enabled;
1225 dsa->stencil_write_enabled = state->stencil[0].enabled &&
1226 (si_dsa_writes_stencil(&state->stencil[0]) ||
1227 si_dsa_writes_stencil(&state->stencil[1]));
1228 dsa->db_can_write = dsa->depth_write_enabled ||
1229 dsa->stencil_write_enabled;
1230
1231 bool zfunc_is_ordered =
1232 state->depth.func == PIPE_FUNC_NEVER ||
1233 state->depth.func == PIPE_FUNC_LESS ||
1234 state->depth.func == PIPE_FUNC_LEQUAL ||
1235 state->depth.func == PIPE_FUNC_GREATER ||
1236 state->depth.func == PIPE_FUNC_GEQUAL;
1237
1238 bool nozwrite_and_order_invariant_stencil =
1239 !dsa->db_can_write ||
1240 (!dsa->depth_write_enabled &&
1241 si_order_invariant_stencil_state(&state->stencil[0]) &&
1242 si_order_invariant_stencil_state(&state->stencil[1]));
1243
1244 dsa->order_invariance[1].zs =
1245 nozwrite_and_order_invariant_stencil ||
1246 (!dsa->stencil_write_enabled && zfunc_is_ordered);
1247 dsa->order_invariance[0].zs = !dsa->depth_write_enabled || zfunc_is_ordered;
1248
1249 dsa->order_invariance[1].pass_set =
1250 nozwrite_and_order_invariant_stencil ||
1251 (!dsa->stencil_write_enabled &&
1252 (state->depth.func == PIPE_FUNC_ALWAYS ||
1253 state->depth.func == PIPE_FUNC_NEVER));
1254 dsa->order_invariance[0].pass_set =
1255 !dsa->depth_write_enabled ||
1256 (state->depth.func == PIPE_FUNC_ALWAYS ||
1257 state->depth.func == PIPE_FUNC_NEVER);
1258
1259 dsa->order_invariance[1].pass_last =
1260 sctx->screen->assume_no_z_fights &&
1261 !dsa->stencil_write_enabled &&
1262 dsa->depth_write_enabled && zfunc_is_ordered;
1263 dsa->order_invariance[0].pass_last =
1264 sctx->screen->assume_no_z_fights &&
1265 dsa->depth_write_enabled && zfunc_is_ordered;
1266
1267 return dsa;
1268 }
1269
1270 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1271 {
1272 struct si_context *sctx = (struct si_context *)ctx;
1273 struct si_state_dsa *old_dsa = sctx->queued.named.dsa;
1274 struct si_state_dsa *dsa = state;
1275
1276 if (!state)
1277 return;
1278
1279 si_pm4_bind_state(sctx, dsa, dsa);
1280
1281 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1282 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1283 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1284 si_mark_atom_dirty(sctx, &sctx->atoms.s.stencil_ref);
1285 }
1286
1287 if (!old_dsa || old_dsa->alpha_func != dsa->alpha_func)
1288 sctx->do_update_shaders = true;
1289
1290 if (sctx->screen->dpbb_allowed &&
1291 (!old_dsa ||
1292 (old_dsa->depth_enabled != dsa->depth_enabled ||
1293 old_dsa->stencil_enabled != dsa->stencil_enabled ||
1294 old_dsa->db_can_write != dsa->db_can_write)))
1295 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
1296
1297 if (sctx->screen->has_out_of_order_rast &&
1298 (!old_dsa ||
1299 memcmp(old_dsa->order_invariance, dsa->order_invariance,
1300 sizeof(old_dsa->order_invariance))))
1301 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
1302 }
1303
1304 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1305 {
1306 struct si_context *sctx = (struct si_context *)ctx;
1307 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1308 }
1309
1310 static void *si_create_db_flush_dsa(struct si_context *sctx)
1311 {
1312 struct pipe_depth_stencil_alpha_state dsa = {};
1313
1314 return sctx->b.create_depth_stencil_alpha_state(&sctx->b, &dsa);
1315 }
1316
1317 /* DB RENDER STATE */
1318
1319 static void si_set_active_query_state(struct pipe_context *ctx, boolean enable)
1320 {
1321 struct si_context *sctx = (struct si_context*)ctx;
1322
1323 /* Pipeline stat & streamout queries. */
1324 if (enable) {
1325 sctx->flags &= ~SI_CONTEXT_STOP_PIPELINE_STATS;
1326 sctx->flags |= SI_CONTEXT_START_PIPELINE_STATS;
1327 } else {
1328 sctx->flags &= ~SI_CONTEXT_START_PIPELINE_STATS;
1329 sctx->flags |= SI_CONTEXT_STOP_PIPELINE_STATS;
1330 }
1331
1332 /* Occlusion queries. */
1333 if (sctx->occlusion_queries_disabled != !enable) {
1334 sctx->occlusion_queries_disabled = !enable;
1335 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1336 }
1337 }
1338
1339 void si_set_occlusion_query_state(struct si_context *sctx,
1340 bool old_perfect_enable)
1341 {
1342 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1343
1344 bool perfect_enable = sctx->num_perfect_occlusion_queries != 0;
1345
1346 if (perfect_enable != old_perfect_enable)
1347 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
1348 }
1349
1350 void si_save_qbo_state(struct si_context *sctx, struct si_qbo_state *st)
1351 {
1352 st->saved_compute = sctx->cs_shader_state.program;
1353
1354 si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1355 si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
1356 }
1357
1358 static void si_emit_db_render_state(struct si_context *sctx)
1359 {
1360 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1361 unsigned db_shader_control, db_render_control, db_count_control;
1362 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1363
1364 /* DB_RENDER_CONTROL */
1365 if (sctx->dbcb_depth_copy_enabled ||
1366 sctx->dbcb_stencil_copy_enabled) {
1367 db_render_control =
1368 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1369 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1370 S_028000_COPY_CENTROID(1) |
1371 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample);
1372 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1373 db_render_control =
1374 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1375 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace);
1376 } else {
1377 db_render_control =
1378 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1379 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear);
1380 }
1381
1382 /* DB_COUNT_CONTROL (occlusion queries) */
1383 if (sctx->num_occlusion_queries > 0 &&
1384 !sctx->occlusion_queries_disabled) {
1385 bool perfect = sctx->num_perfect_occlusion_queries > 0;
1386
1387 if (sctx->chip_class >= CIK) {
1388 unsigned log_sample_rate = sctx->framebuffer.log_samples;
1389
1390 /* Stoney doesn't increment occlusion query counters
1391 * if the sample rate is 16x. Use 8x sample rate instead.
1392 */
1393 if (sctx->family == CHIP_STONEY)
1394 log_sample_rate = MIN2(log_sample_rate, 3);
1395
1396 db_count_control =
1397 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1398 S_028004_SAMPLE_RATE(log_sample_rate) |
1399 S_028004_ZPASS_ENABLE(1) |
1400 S_028004_SLICE_EVEN_ENABLE(1) |
1401 S_028004_SLICE_ODD_ENABLE(1);
1402 } else {
1403 db_count_control =
1404 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1405 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples);
1406 }
1407 } else {
1408 /* Disable occlusion queries. */
1409 if (sctx->chip_class >= CIK) {
1410 db_count_control = 0;
1411 } else {
1412 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1413 }
1414 }
1415
1416 radeon_opt_set_context_reg2(sctx, R_028000_DB_RENDER_CONTROL,
1417 SI_TRACKED_DB_RENDER_CONTROL, db_render_control,
1418 db_count_control);
1419
1420 /* DB_RENDER_OVERRIDE2 */
1421 radeon_opt_set_context_reg(sctx, R_028010_DB_RENDER_OVERRIDE2,
1422 SI_TRACKED_DB_RENDER_OVERRIDE2,
1423 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1424 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1425 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4));
1426
1427 db_shader_control = sctx->ps_db_shader_control;
1428
1429 /* Bug workaround for smoothing (overrasterization) on SI. */
1430 if (sctx->chip_class == SI && sctx->smoothing_enabled) {
1431 db_shader_control &= C_02880C_Z_ORDER;
1432 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1433 }
1434
1435 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1436 if (!rs->multisample_enable)
1437 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1438
1439 if (sctx->screen->has_rbplus &&
1440 !sctx->screen->rbplus_allowed)
1441 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1442
1443 radeon_opt_set_context_reg(sctx, R_02880C_DB_SHADER_CONTROL,
1444 SI_TRACKED_DB_SHADER_CONTROL, db_shader_control);
1445
1446 if (initial_cdw != sctx->gfx_cs->current.cdw)
1447 sctx->context_roll_counter++;
1448 }
1449
1450 /*
1451 * format translation
1452 */
1453 static uint32_t si_translate_colorformat(enum pipe_format format)
1454 {
1455 const struct util_format_description *desc = util_format_description(format);
1456 if (!desc)
1457 return V_028C70_COLOR_INVALID;
1458
1459 #define HAS_SIZE(x,y,z,w) \
1460 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1461 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1462
1463 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1464 return V_028C70_COLOR_10_11_11;
1465
1466 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1467 return V_028C70_COLOR_INVALID;
1468
1469 /* hw cannot support mixed formats (except depth/stencil, since
1470 * stencil is not written to). */
1471 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1472 return V_028C70_COLOR_INVALID;
1473
1474 switch (desc->nr_channels) {
1475 case 1:
1476 switch (desc->channel[0].size) {
1477 case 8:
1478 return V_028C70_COLOR_8;
1479 case 16:
1480 return V_028C70_COLOR_16;
1481 case 32:
1482 return V_028C70_COLOR_32;
1483 }
1484 break;
1485 case 2:
1486 if (desc->channel[0].size == desc->channel[1].size) {
1487 switch (desc->channel[0].size) {
1488 case 8:
1489 return V_028C70_COLOR_8_8;
1490 case 16:
1491 return V_028C70_COLOR_16_16;
1492 case 32:
1493 return V_028C70_COLOR_32_32;
1494 }
1495 } else if (HAS_SIZE(8,24,0,0)) {
1496 return V_028C70_COLOR_24_8;
1497 } else if (HAS_SIZE(24,8,0,0)) {
1498 return V_028C70_COLOR_8_24;
1499 }
1500 break;
1501 case 3:
1502 if (HAS_SIZE(5,6,5,0)) {
1503 return V_028C70_COLOR_5_6_5;
1504 } else if (HAS_SIZE(32,8,24,0)) {
1505 return V_028C70_COLOR_X24_8_32_FLOAT;
1506 }
1507 break;
1508 case 4:
1509 if (desc->channel[0].size == desc->channel[1].size &&
1510 desc->channel[0].size == desc->channel[2].size &&
1511 desc->channel[0].size == desc->channel[3].size) {
1512 switch (desc->channel[0].size) {
1513 case 4:
1514 return V_028C70_COLOR_4_4_4_4;
1515 case 8:
1516 return V_028C70_COLOR_8_8_8_8;
1517 case 16:
1518 return V_028C70_COLOR_16_16_16_16;
1519 case 32:
1520 return V_028C70_COLOR_32_32_32_32;
1521 }
1522 } else if (HAS_SIZE(5,5,5,1)) {
1523 return V_028C70_COLOR_1_5_5_5;
1524 } else if (HAS_SIZE(1,5,5,5)) {
1525 return V_028C70_COLOR_5_5_5_1;
1526 } else if (HAS_SIZE(10,10,10,2)) {
1527 return V_028C70_COLOR_2_10_10_10;
1528 }
1529 break;
1530 }
1531 return V_028C70_COLOR_INVALID;
1532 }
1533
1534 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1535 {
1536 if (SI_BIG_ENDIAN) {
1537 switch(colorformat) {
1538 /* 8-bit buffers. */
1539 case V_028C70_COLOR_8:
1540 return V_028C70_ENDIAN_NONE;
1541
1542 /* 16-bit buffers. */
1543 case V_028C70_COLOR_5_6_5:
1544 case V_028C70_COLOR_1_5_5_5:
1545 case V_028C70_COLOR_4_4_4_4:
1546 case V_028C70_COLOR_16:
1547 case V_028C70_COLOR_8_8:
1548 return V_028C70_ENDIAN_8IN16;
1549
1550 /* 32-bit buffers. */
1551 case V_028C70_COLOR_8_8_8_8:
1552 case V_028C70_COLOR_2_10_10_10:
1553 case V_028C70_COLOR_8_24:
1554 case V_028C70_COLOR_24_8:
1555 case V_028C70_COLOR_16_16:
1556 return V_028C70_ENDIAN_8IN32;
1557
1558 /* 64-bit buffers. */
1559 case V_028C70_COLOR_16_16_16_16:
1560 return V_028C70_ENDIAN_8IN16;
1561
1562 case V_028C70_COLOR_32_32:
1563 return V_028C70_ENDIAN_8IN32;
1564
1565 /* 128-bit buffers. */
1566 case V_028C70_COLOR_32_32_32_32:
1567 return V_028C70_ENDIAN_8IN32;
1568 default:
1569 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1570 }
1571 } else {
1572 return V_028C70_ENDIAN_NONE;
1573 }
1574 }
1575
1576 static uint32_t si_translate_dbformat(enum pipe_format format)
1577 {
1578 switch (format) {
1579 case PIPE_FORMAT_Z16_UNORM:
1580 return V_028040_Z_16;
1581 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1582 case PIPE_FORMAT_X8Z24_UNORM:
1583 case PIPE_FORMAT_Z24X8_UNORM:
1584 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1585 return V_028040_Z_24; /* deprecated on SI */
1586 case PIPE_FORMAT_Z32_FLOAT:
1587 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1588 return V_028040_Z_32_FLOAT;
1589 default:
1590 return V_028040_Z_INVALID;
1591 }
1592 }
1593
1594 /*
1595 * Texture translation
1596 */
1597
1598 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1599 enum pipe_format format,
1600 const struct util_format_description *desc,
1601 int first_non_void)
1602 {
1603 struct si_screen *sscreen = (struct si_screen*)screen;
1604 bool uniform = true;
1605 int i;
1606
1607 /* Colorspace (return non-RGB formats directly). */
1608 switch (desc->colorspace) {
1609 /* Depth stencil formats */
1610 case UTIL_FORMAT_COLORSPACE_ZS:
1611 switch (format) {
1612 case PIPE_FORMAT_Z16_UNORM:
1613 return V_008F14_IMG_DATA_FORMAT_16;
1614 case PIPE_FORMAT_X24S8_UINT:
1615 case PIPE_FORMAT_S8X24_UINT:
1616 /*
1617 * Implemented as an 8_8_8_8 data format to fix texture
1618 * gathers in stencil sampling. This affects at least
1619 * GL45-CTS.texture_cube_map_array.sampling on VI.
1620 */
1621 if (sscreen->info.chip_class <= VI)
1622 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1623
1624 if (format == PIPE_FORMAT_X24S8_UINT)
1625 return V_008F14_IMG_DATA_FORMAT_8_24;
1626 else
1627 return V_008F14_IMG_DATA_FORMAT_24_8;
1628 case PIPE_FORMAT_Z24X8_UNORM:
1629 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1630 return V_008F14_IMG_DATA_FORMAT_8_24;
1631 case PIPE_FORMAT_X8Z24_UNORM:
1632 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1633 return V_008F14_IMG_DATA_FORMAT_24_8;
1634 case PIPE_FORMAT_S8_UINT:
1635 return V_008F14_IMG_DATA_FORMAT_8;
1636 case PIPE_FORMAT_Z32_FLOAT:
1637 return V_008F14_IMG_DATA_FORMAT_32;
1638 case PIPE_FORMAT_X32_S8X24_UINT:
1639 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1640 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1641 default:
1642 goto out_unknown;
1643 }
1644
1645 case UTIL_FORMAT_COLORSPACE_YUV:
1646 goto out_unknown; /* TODO */
1647
1648 case UTIL_FORMAT_COLORSPACE_SRGB:
1649 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1650 goto out_unknown;
1651 break;
1652
1653 default:
1654 break;
1655 }
1656
1657 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1658 if (!sscreen->info.has_format_bc1_through_bc7)
1659 goto out_unknown;
1660
1661 switch (format) {
1662 case PIPE_FORMAT_RGTC1_SNORM:
1663 case PIPE_FORMAT_LATC1_SNORM:
1664 case PIPE_FORMAT_RGTC1_UNORM:
1665 case PIPE_FORMAT_LATC1_UNORM:
1666 return V_008F14_IMG_DATA_FORMAT_BC4;
1667 case PIPE_FORMAT_RGTC2_SNORM:
1668 case PIPE_FORMAT_LATC2_SNORM:
1669 case PIPE_FORMAT_RGTC2_UNORM:
1670 case PIPE_FORMAT_LATC2_UNORM:
1671 return V_008F14_IMG_DATA_FORMAT_BC5;
1672 default:
1673 goto out_unknown;
1674 }
1675 }
1676
1677 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1678 (sscreen->info.family == CHIP_STONEY ||
1679 sscreen->info.family == CHIP_VEGA10 ||
1680 sscreen->info.family == CHIP_RAVEN)) {
1681 switch (format) {
1682 case PIPE_FORMAT_ETC1_RGB8:
1683 case PIPE_FORMAT_ETC2_RGB8:
1684 case PIPE_FORMAT_ETC2_SRGB8:
1685 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1686 case PIPE_FORMAT_ETC2_RGB8A1:
1687 case PIPE_FORMAT_ETC2_SRGB8A1:
1688 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1689 case PIPE_FORMAT_ETC2_RGBA8:
1690 case PIPE_FORMAT_ETC2_SRGBA8:
1691 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1692 case PIPE_FORMAT_ETC2_R11_UNORM:
1693 case PIPE_FORMAT_ETC2_R11_SNORM:
1694 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1695 case PIPE_FORMAT_ETC2_RG11_UNORM:
1696 case PIPE_FORMAT_ETC2_RG11_SNORM:
1697 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1698 default:
1699 goto out_unknown;
1700 }
1701 }
1702
1703 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1704 if (!sscreen->info.has_format_bc1_through_bc7)
1705 goto out_unknown;
1706
1707 switch (format) {
1708 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1709 case PIPE_FORMAT_BPTC_SRGBA:
1710 return V_008F14_IMG_DATA_FORMAT_BC7;
1711 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1712 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1713 return V_008F14_IMG_DATA_FORMAT_BC6;
1714 default:
1715 goto out_unknown;
1716 }
1717 }
1718
1719 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1720 switch (format) {
1721 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1722 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1723 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1724 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1725 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1726 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1727 default:
1728 goto out_unknown;
1729 }
1730 }
1731
1732 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1733 if (!sscreen->info.has_format_bc1_through_bc7)
1734 goto out_unknown;
1735
1736 switch (format) {
1737 case PIPE_FORMAT_DXT1_RGB:
1738 case PIPE_FORMAT_DXT1_RGBA:
1739 case PIPE_FORMAT_DXT1_SRGB:
1740 case PIPE_FORMAT_DXT1_SRGBA:
1741 return V_008F14_IMG_DATA_FORMAT_BC1;
1742 case PIPE_FORMAT_DXT3_RGBA:
1743 case PIPE_FORMAT_DXT3_SRGBA:
1744 return V_008F14_IMG_DATA_FORMAT_BC2;
1745 case PIPE_FORMAT_DXT5_RGBA:
1746 case PIPE_FORMAT_DXT5_SRGBA:
1747 return V_008F14_IMG_DATA_FORMAT_BC3;
1748 default:
1749 goto out_unknown;
1750 }
1751 }
1752
1753 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1754 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1755 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1756 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1757 }
1758
1759 /* R8G8Bx_SNORM - TODO CxV8U8 */
1760
1761 /* hw cannot support mixed formats (except depth/stencil, since only
1762 * depth is read).*/
1763 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1764 goto out_unknown;
1765
1766 /* See whether the components are of the same size. */
1767 for (i = 1; i < desc->nr_channels; i++) {
1768 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1769 }
1770
1771 /* Non-uniform formats. */
1772 if (!uniform) {
1773 switch(desc->nr_channels) {
1774 case 3:
1775 if (desc->channel[0].size == 5 &&
1776 desc->channel[1].size == 6 &&
1777 desc->channel[2].size == 5) {
1778 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1779 }
1780 goto out_unknown;
1781 case 4:
1782 if (desc->channel[0].size == 5 &&
1783 desc->channel[1].size == 5 &&
1784 desc->channel[2].size == 5 &&
1785 desc->channel[3].size == 1) {
1786 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1787 }
1788 if (desc->channel[0].size == 1 &&
1789 desc->channel[1].size == 5 &&
1790 desc->channel[2].size == 5 &&
1791 desc->channel[3].size == 5) {
1792 return V_008F14_IMG_DATA_FORMAT_5_5_5_1;
1793 }
1794 if (desc->channel[0].size == 10 &&
1795 desc->channel[1].size == 10 &&
1796 desc->channel[2].size == 10 &&
1797 desc->channel[3].size == 2) {
1798 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1799 }
1800 goto out_unknown;
1801 }
1802 goto out_unknown;
1803 }
1804
1805 if (first_non_void < 0 || first_non_void > 3)
1806 goto out_unknown;
1807
1808 /* uniform formats */
1809 switch (desc->channel[first_non_void].size) {
1810 case 4:
1811 switch (desc->nr_channels) {
1812 #if 0 /* Not supported for render targets */
1813 case 2:
1814 return V_008F14_IMG_DATA_FORMAT_4_4;
1815 #endif
1816 case 4:
1817 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1818 }
1819 break;
1820 case 8:
1821 switch (desc->nr_channels) {
1822 case 1:
1823 return V_008F14_IMG_DATA_FORMAT_8;
1824 case 2:
1825 return V_008F14_IMG_DATA_FORMAT_8_8;
1826 case 4:
1827 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1828 }
1829 break;
1830 case 16:
1831 switch (desc->nr_channels) {
1832 case 1:
1833 return V_008F14_IMG_DATA_FORMAT_16;
1834 case 2:
1835 return V_008F14_IMG_DATA_FORMAT_16_16;
1836 case 4:
1837 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1838 }
1839 break;
1840 case 32:
1841 switch (desc->nr_channels) {
1842 case 1:
1843 return V_008F14_IMG_DATA_FORMAT_32;
1844 case 2:
1845 return V_008F14_IMG_DATA_FORMAT_32_32;
1846 #if 0 /* Not supported for render targets */
1847 case 3:
1848 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1849 #endif
1850 case 4:
1851 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1852 }
1853 }
1854
1855 out_unknown:
1856 return ~0;
1857 }
1858
1859 static unsigned si_tex_wrap(unsigned wrap)
1860 {
1861 switch (wrap) {
1862 default:
1863 case PIPE_TEX_WRAP_REPEAT:
1864 return V_008F30_SQ_TEX_WRAP;
1865 case PIPE_TEX_WRAP_CLAMP:
1866 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1867 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1868 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1869 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1870 return V_008F30_SQ_TEX_CLAMP_BORDER;
1871 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1872 return V_008F30_SQ_TEX_MIRROR;
1873 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1874 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1875 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1876 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1877 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1878 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1879 }
1880 }
1881
1882 static unsigned si_tex_mipfilter(unsigned filter)
1883 {
1884 switch (filter) {
1885 case PIPE_TEX_MIPFILTER_NEAREST:
1886 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1887 case PIPE_TEX_MIPFILTER_LINEAR:
1888 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1889 default:
1890 case PIPE_TEX_MIPFILTER_NONE:
1891 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1892 }
1893 }
1894
1895 static unsigned si_tex_compare(unsigned compare)
1896 {
1897 switch (compare) {
1898 default:
1899 case PIPE_FUNC_NEVER:
1900 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1901 case PIPE_FUNC_LESS:
1902 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1903 case PIPE_FUNC_EQUAL:
1904 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1905 case PIPE_FUNC_LEQUAL:
1906 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1907 case PIPE_FUNC_GREATER:
1908 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1909 case PIPE_FUNC_NOTEQUAL:
1910 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1911 case PIPE_FUNC_GEQUAL:
1912 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1913 case PIPE_FUNC_ALWAYS:
1914 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1915 }
1916 }
1917
1918 static unsigned si_tex_dim(struct si_screen *sscreen, struct si_texture *tex,
1919 unsigned view_target, unsigned nr_samples)
1920 {
1921 unsigned res_target = tex->buffer.b.b.target;
1922
1923 if (view_target == PIPE_TEXTURE_CUBE ||
1924 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1925 res_target = view_target;
1926 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1927 else if (res_target == PIPE_TEXTURE_CUBE ||
1928 res_target == PIPE_TEXTURE_CUBE_ARRAY)
1929 res_target = PIPE_TEXTURE_2D_ARRAY;
1930
1931 /* GFX9 allocates 1D textures as 2D. */
1932 if ((res_target == PIPE_TEXTURE_1D ||
1933 res_target == PIPE_TEXTURE_1D_ARRAY) &&
1934 sscreen->info.chip_class >= GFX9 &&
1935 tex->surface.u.gfx9.resource_type == RADEON_RESOURCE_2D) {
1936 if (res_target == PIPE_TEXTURE_1D)
1937 res_target = PIPE_TEXTURE_2D;
1938 else
1939 res_target = PIPE_TEXTURE_2D_ARRAY;
1940 }
1941
1942 switch (res_target) {
1943 default:
1944 case PIPE_TEXTURE_1D:
1945 return V_008F1C_SQ_RSRC_IMG_1D;
1946 case PIPE_TEXTURE_1D_ARRAY:
1947 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1948 case PIPE_TEXTURE_2D:
1949 case PIPE_TEXTURE_RECT:
1950 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1951 V_008F1C_SQ_RSRC_IMG_2D;
1952 case PIPE_TEXTURE_2D_ARRAY:
1953 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1954 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1955 case PIPE_TEXTURE_3D:
1956 return V_008F1C_SQ_RSRC_IMG_3D;
1957 case PIPE_TEXTURE_CUBE:
1958 case PIPE_TEXTURE_CUBE_ARRAY:
1959 return V_008F1C_SQ_RSRC_IMG_CUBE;
1960 }
1961 }
1962
1963 /*
1964 * Format support testing
1965 */
1966
1967 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1968 {
1969 const struct util_format_description *desc = util_format_description(format);
1970 if (!desc)
1971 return false;
1972
1973 return si_translate_texformat(screen, format, desc,
1974 util_format_get_first_non_void_channel(format)) != ~0U;
1975 }
1976
1977 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1978 const struct util_format_description *desc,
1979 int first_non_void)
1980 {
1981 int i;
1982
1983 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1984 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1985
1986 assert(first_non_void >= 0);
1987
1988 if (desc->nr_channels == 4 &&
1989 desc->channel[0].size == 10 &&
1990 desc->channel[1].size == 10 &&
1991 desc->channel[2].size == 10 &&
1992 desc->channel[3].size == 2)
1993 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1994
1995 /* See whether the components are of the same size. */
1996 for (i = 0; i < desc->nr_channels; i++) {
1997 if (desc->channel[first_non_void].size != desc->channel[i].size)
1998 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1999 }
2000
2001 switch (desc->channel[first_non_void].size) {
2002 case 8:
2003 switch (desc->nr_channels) {
2004 case 1:
2005 case 3: /* 3 loads */
2006 return V_008F0C_BUF_DATA_FORMAT_8;
2007 case 2:
2008 return V_008F0C_BUF_DATA_FORMAT_8_8;
2009 case 4:
2010 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
2011 }
2012 break;
2013 case 16:
2014 switch (desc->nr_channels) {
2015 case 1:
2016 case 3: /* 3 loads */
2017 return V_008F0C_BUF_DATA_FORMAT_16;
2018 case 2:
2019 return V_008F0C_BUF_DATA_FORMAT_16_16;
2020 case 4:
2021 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
2022 }
2023 break;
2024 case 32:
2025 switch (desc->nr_channels) {
2026 case 1:
2027 return V_008F0C_BUF_DATA_FORMAT_32;
2028 case 2:
2029 return V_008F0C_BUF_DATA_FORMAT_32_32;
2030 case 3:
2031 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
2032 case 4:
2033 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2034 }
2035 break;
2036 case 64:
2037 /* Legacy double formats. */
2038 switch (desc->nr_channels) {
2039 case 1: /* 1 load */
2040 return V_008F0C_BUF_DATA_FORMAT_32_32;
2041 case 2: /* 1 load */
2042 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2043 case 3: /* 3 loads */
2044 return V_008F0C_BUF_DATA_FORMAT_32_32;
2045 case 4: /* 2 loads */
2046 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2047 }
2048 break;
2049 }
2050
2051 return V_008F0C_BUF_DATA_FORMAT_INVALID;
2052 }
2053
2054 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
2055 const struct util_format_description *desc,
2056 int first_non_void)
2057 {
2058 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
2059 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2060
2061 assert(first_non_void >= 0);
2062
2063 switch (desc->channel[first_non_void].type) {
2064 case UTIL_FORMAT_TYPE_SIGNED:
2065 case UTIL_FORMAT_TYPE_FIXED:
2066 if (desc->channel[first_non_void].size >= 32 ||
2067 desc->channel[first_non_void].pure_integer)
2068 return V_008F0C_BUF_NUM_FORMAT_SINT;
2069 else if (desc->channel[first_non_void].normalized)
2070 return V_008F0C_BUF_NUM_FORMAT_SNORM;
2071 else
2072 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
2073 break;
2074 case UTIL_FORMAT_TYPE_UNSIGNED:
2075 if (desc->channel[first_non_void].size >= 32 ||
2076 desc->channel[first_non_void].pure_integer)
2077 return V_008F0C_BUF_NUM_FORMAT_UINT;
2078 else if (desc->channel[first_non_void].normalized)
2079 return V_008F0C_BUF_NUM_FORMAT_UNORM;
2080 else
2081 return V_008F0C_BUF_NUM_FORMAT_USCALED;
2082 break;
2083 case UTIL_FORMAT_TYPE_FLOAT:
2084 default:
2085 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2086 }
2087 }
2088
2089 static unsigned si_is_vertex_format_supported(struct pipe_screen *screen,
2090 enum pipe_format format,
2091 unsigned usage)
2092 {
2093 const struct util_format_description *desc;
2094 int first_non_void;
2095 unsigned data_format;
2096
2097 assert((usage & ~(PIPE_BIND_SHADER_IMAGE |
2098 PIPE_BIND_SAMPLER_VIEW |
2099 PIPE_BIND_VERTEX_BUFFER)) == 0);
2100
2101 desc = util_format_description(format);
2102 if (!desc)
2103 return 0;
2104
2105 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
2106 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
2107 * for read-only access (with caveats surrounding bounds checks), but
2108 * obviously fails for write access which we have to implement for
2109 * shader images. Luckily, OpenGL doesn't expect this to be supported
2110 * anyway, and so the only impact is on PBO uploads / downloads, which
2111 * shouldn't be expected to be fast for GL_RGB anyway.
2112 */
2113 if (desc->block.bits == 3 * 8 ||
2114 desc->block.bits == 3 * 16) {
2115 if (usage & (PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW)) {
2116 usage &= ~(PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW);
2117 if (!usage)
2118 return 0;
2119 }
2120 }
2121
2122 first_non_void = util_format_get_first_non_void_channel(format);
2123 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
2124 if (data_format == V_008F0C_BUF_DATA_FORMAT_INVALID)
2125 return 0;
2126
2127 return usage;
2128 }
2129
2130 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
2131 {
2132 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
2133 si_translate_colorswap(format, false) != ~0U;
2134 }
2135
2136 static bool si_is_zs_format_supported(enum pipe_format format)
2137 {
2138 return si_translate_dbformat(format) != V_028040_Z_INVALID;
2139 }
2140
2141 static boolean si_is_format_supported(struct pipe_screen *screen,
2142 enum pipe_format format,
2143 enum pipe_texture_target target,
2144 unsigned sample_count,
2145 unsigned storage_sample_count,
2146 unsigned usage)
2147 {
2148 struct si_screen *sscreen = (struct si_screen *)screen;
2149 unsigned retval = 0;
2150
2151 if (target >= PIPE_MAX_TEXTURE_TYPES) {
2152 PRINT_ERR("r600: unsupported texture type %d\n", target);
2153 return false;
2154 }
2155
2156 if (MAX2(1, sample_count) < MAX2(1, storage_sample_count))
2157 return false;
2158
2159 if (sample_count > 1) {
2160 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
2161 return false;
2162
2163 if (usage & PIPE_BIND_SHADER_IMAGE)
2164 return false;
2165
2166 /* Only power-of-two sample counts are supported. */
2167 if (!util_is_power_of_two_or_zero(sample_count) ||
2168 !util_is_power_of_two_or_zero(storage_sample_count))
2169 return false;
2170
2171 /* MSAA support without framebuffer attachments. */
2172 if (format == PIPE_FORMAT_NONE && sample_count <= 16)
2173 return true;
2174
2175 if (!sscreen->info.has_eqaa_surface_allocator ||
2176 util_format_is_depth_or_stencil(format)) {
2177 /* Color without EQAA or depth/stencil. */
2178 if (sample_count > 8 ||
2179 sample_count != storage_sample_count)
2180 return false;
2181 } else {
2182 /* Color with EQAA. */
2183 if (sample_count > 16 ||
2184 storage_sample_count > 8)
2185 return false;
2186 }
2187 }
2188
2189 if (usage & (PIPE_BIND_SAMPLER_VIEW |
2190 PIPE_BIND_SHADER_IMAGE)) {
2191 if (target == PIPE_BUFFER) {
2192 retval |= si_is_vertex_format_supported(
2193 screen, format, usage & (PIPE_BIND_SAMPLER_VIEW |
2194 PIPE_BIND_SHADER_IMAGE));
2195 } else {
2196 if (si_is_sampler_format_supported(screen, format))
2197 retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
2198 PIPE_BIND_SHADER_IMAGE);
2199 }
2200 }
2201
2202 if ((usage & (PIPE_BIND_RENDER_TARGET |
2203 PIPE_BIND_DISPLAY_TARGET |
2204 PIPE_BIND_SCANOUT |
2205 PIPE_BIND_SHARED |
2206 PIPE_BIND_BLENDABLE)) &&
2207 si_is_colorbuffer_format_supported(format)) {
2208 retval |= usage &
2209 (PIPE_BIND_RENDER_TARGET |
2210 PIPE_BIND_DISPLAY_TARGET |
2211 PIPE_BIND_SCANOUT |
2212 PIPE_BIND_SHARED);
2213 if (!util_format_is_pure_integer(format) &&
2214 !util_format_is_depth_or_stencil(format))
2215 retval |= usage & PIPE_BIND_BLENDABLE;
2216 }
2217
2218 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
2219 si_is_zs_format_supported(format)) {
2220 retval |= PIPE_BIND_DEPTH_STENCIL;
2221 }
2222
2223 if (usage & PIPE_BIND_VERTEX_BUFFER) {
2224 retval |= si_is_vertex_format_supported(screen, format,
2225 PIPE_BIND_VERTEX_BUFFER);
2226 }
2227
2228 if ((usage & PIPE_BIND_LINEAR) &&
2229 !util_format_is_compressed(format) &&
2230 !(usage & PIPE_BIND_DEPTH_STENCIL))
2231 retval |= PIPE_BIND_LINEAR;
2232
2233 return retval == usage;
2234 }
2235
2236 /*
2237 * framebuffer handling
2238 */
2239
2240 static void si_choose_spi_color_formats(struct si_surface *surf,
2241 unsigned format, unsigned swap,
2242 unsigned ntype, bool is_depth)
2243 {
2244 /* Alpha is needed for alpha-to-coverage.
2245 * Blending may be with or without alpha.
2246 */
2247 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
2248 unsigned alpha = 0; /* exports alpha, but may not support blending */
2249 unsigned blend = 0; /* supports blending, but may not export alpha */
2250 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
2251
2252 /* Choose the SPI color formats. These are required values for RB+.
2253 * Other chips have multiple choices, though they are not necessarily better.
2254 */
2255 switch (format) {
2256 case V_028C70_COLOR_5_6_5:
2257 case V_028C70_COLOR_1_5_5_5:
2258 case V_028C70_COLOR_5_5_5_1:
2259 case V_028C70_COLOR_4_4_4_4:
2260 case V_028C70_COLOR_10_11_11:
2261 case V_028C70_COLOR_11_11_10:
2262 case V_028C70_COLOR_8:
2263 case V_028C70_COLOR_8_8:
2264 case V_028C70_COLOR_8_8_8_8:
2265 case V_028C70_COLOR_10_10_10_2:
2266 case V_028C70_COLOR_2_10_10_10:
2267 if (ntype == V_028C70_NUMBER_UINT)
2268 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2269 else if (ntype == V_028C70_NUMBER_SINT)
2270 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2271 else
2272 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2273 break;
2274
2275 case V_028C70_COLOR_16:
2276 case V_028C70_COLOR_16_16:
2277 case V_028C70_COLOR_16_16_16_16:
2278 if (ntype == V_028C70_NUMBER_UNORM ||
2279 ntype == V_028C70_NUMBER_SNORM) {
2280 /* UNORM16 and SNORM16 don't support blending */
2281 if (ntype == V_028C70_NUMBER_UNORM)
2282 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
2283 else
2284 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
2285
2286 /* Use 32 bits per channel for blending. */
2287 if (format == V_028C70_COLOR_16) {
2288 if (swap == V_028C70_SWAP_STD) { /* R */
2289 blend = V_028714_SPI_SHADER_32_R;
2290 blend_alpha = V_028714_SPI_SHADER_32_AR;
2291 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2292 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2293 else
2294 assert(0);
2295 } else if (format == V_028C70_COLOR_16_16) {
2296 if (swap == V_028C70_SWAP_STD) { /* RG */
2297 blend = V_028714_SPI_SHADER_32_GR;
2298 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2299 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2300 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2301 else
2302 assert(0);
2303 } else /* 16_16_16_16 */
2304 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2305 } else if (ntype == V_028C70_NUMBER_UINT)
2306 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2307 else if (ntype == V_028C70_NUMBER_SINT)
2308 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2309 else if (ntype == V_028C70_NUMBER_FLOAT)
2310 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2311 else
2312 assert(0);
2313 break;
2314
2315 case V_028C70_COLOR_32:
2316 if (swap == V_028C70_SWAP_STD) { /* R */
2317 blend = normal = V_028714_SPI_SHADER_32_R;
2318 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
2319 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2320 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2321 else
2322 assert(0);
2323 break;
2324
2325 case V_028C70_COLOR_32_32:
2326 if (swap == V_028C70_SWAP_STD) { /* RG */
2327 blend = normal = V_028714_SPI_SHADER_32_GR;
2328 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2329 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2330 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2331 else
2332 assert(0);
2333 break;
2334
2335 case V_028C70_COLOR_32_32_32_32:
2336 case V_028C70_COLOR_8_24:
2337 case V_028C70_COLOR_24_8:
2338 case V_028C70_COLOR_X24_8_32_FLOAT:
2339 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2340 break;
2341
2342 default:
2343 assert(0);
2344 return;
2345 }
2346
2347 /* The DB->CB copy needs 32_ABGR. */
2348 if (is_depth)
2349 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2350
2351 surf->spi_shader_col_format = normal;
2352 surf->spi_shader_col_format_alpha = alpha;
2353 surf->spi_shader_col_format_blend = blend;
2354 surf->spi_shader_col_format_blend_alpha = blend_alpha;
2355 }
2356
2357 static void si_initialize_color_surface(struct si_context *sctx,
2358 struct si_surface *surf)
2359 {
2360 struct si_texture *tex = (struct si_texture*)surf->base.texture;
2361 unsigned color_info, color_attrib;
2362 unsigned format, swap, ntype, endian;
2363 const struct util_format_description *desc;
2364 int firstchan;
2365 unsigned blend_clamp = 0, blend_bypass = 0;
2366
2367 desc = util_format_description(surf->base.format);
2368 for (firstchan = 0; firstchan < 4; firstchan++) {
2369 if (desc->channel[firstchan].type != UTIL_FORMAT_TYPE_VOID) {
2370 break;
2371 }
2372 }
2373 if (firstchan == 4 || desc->channel[firstchan].type == UTIL_FORMAT_TYPE_FLOAT) {
2374 ntype = V_028C70_NUMBER_FLOAT;
2375 } else {
2376 ntype = V_028C70_NUMBER_UNORM;
2377 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2378 ntype = V_028C70_NUMBER_SRGB;
2379 else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_SIGNED) {
2380 if (desc->channel[firstchan].pure_integer) {
2381 ntype = V_028C70_NUMBER_SINT;
2382 } else {
2383 assert(desc->channel[firstchan].normalized);
2384 ntype = V_028C70_NUMBER_SNORM;
2385 }
2386 } else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2387 if (desc->channel[firstchan].pure_integer) {
2388 ntype = V_028C70_NUMBER_UINT;
2389 } else {
2390 assert(desc->channel[firstchan].normalized);
2391 ntype = V_028C70_NUMBER_UNORM;
2392 }
2393 }
2394 }
2395
2396 format = si_translate_colorformat(surf->base.format);
2397 if (format == V_028C70_COLOR_INVALID) {
2398 PRINT_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2399 }
2400 assert(format != V_028C70_COLOR_INVALID);
2401 swap = si_translate_colorswap(surf->base.format, false);
2402 endian = si_colorformat_endian_swap(format);
2403
2404 /* blend clamp should be set for all NORM/SRGB types */
2405 if (ntype == V_028C70_NUMBER_UNORM ||
2406 ntype == V_028C70_NUMBER_SNORM ||
2407 ntype == V_028C70_NUMBER_SRGB)
2408 blend_clamp = 1;
2409
2410 /* set blend bypass according to docs if SINT/UINT or
2411 8/24 COLOR variants */
2412 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2413 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2414 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2415 blend_clamp = 0;
2416 blend_bypass = 1;
2417 }
2418
2419 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) {
2420 if (format == V_028C70_COLOR_8 ||
2421 format == V_028C70_COLOR_8_8 ||
2422 format == V_028C70_COLOR_8_8_8_8)
2423 surf->color_is_int8 = true;
2424 else if (format == V_028C70_COLOR_10_10_10_2 ||
2425 format == V_028C70_COLOR_2_10_10_10)
2426 surf->color_is_int10 = true;
2427 }
2428
2429 color_info = S_028C70_FORMAT(format) |
2430 S_028C70_COMP_SWAP(swap) |
2431 S_028C70_BLEND_CLAMP(blend_clamp) |
2432 S_028C70_BLEND_BYPASS(blend_bypass) |
2433 S_028C70_SIMPLE_FLOAT(1) |
2434 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2435 ntype != V_028C70_NUMBER_SNORM &&
2436 ntype != V_028C70_NUMBER_SRGB &&
2437 format != V_028C70_COLOR_8_24 &&
2438 format != V_028C70_COLOR_24_8) |
2439 S_028C70_NUMBER_TYPE(ntype) |
2440 S_028C70_ENDIAN(endian);
2441
2442 /* Intensity is implemented as Red, so treat it that way. */
2443 color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2444 util_format_is_intensity(surf->base.format));
2445
2446 if (tex->buffer.b.b.nr_samples > 1) {
2447 unsigned log_samples = util_logbase2(tex->buffer.b.b.nr_samples);
2448 unsigned log_fragments = util_logbase2(tex->buffer.b.b.nr_storage_samples);
2449
2450 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2451 S_028C74_NUM_FRAGMENTS(log_fragments);
2452
2453 if (tex->surface.fmask_size) {
2454 color_info |= S_028C70_COMPRESSION(1);
2455 unsigned fmask_bankh = util_logbase2(tex->surface.u.legacy.fmask.bankh);
2456
2457 if (sctx->chip_class == SI) {
2458 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2459 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2460 }
2461 }
2462 }
2463
2464 if (sctx->chip_class >= VI) {
2465 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
2466 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
2467
2468 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2469 64 for APU because all of our APUs to date use DIMMs which have
2470 a request granularity size of 64B while all other chips have a
2471 32B request size */
2472 if (!sctx->screen->info.has_dedicated_vram)
2473 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
2474
2475 if (tex->buffer.b.b.nr_storage_samples > 1) {
2476 if (tex->surface.bpe == 1)
2477 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
2478 else if (tex->surface.bpe == 2)
2479 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
2480 }
2481
2482 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2483 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
2484 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2485 }
2486
2487 /* This must be set for fast clear to work without FMASK. */
2488 if (!tex->surface.fmask_size && sctx->chip_class == SI) {
2489 unsigned bankh = util_logbase2(tex->surface.u.legacy.bankh);
2490 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2491 }
2492
2493 unsigned color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2494 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
2495
2496 if (sctx->chip_class >= GFX9) {
2497 unsigned mip0_depth = util_max_layer(&tex->buffer.b.b, 0);
2498
2499 color_view |= S_028C6C_MIP_LEVEL(surf->base.u.tex.level);
2500 color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
2501 S_028C74_RESOURCE_TYPE(tex->surface.u.gfx9.resource_type);
2502 surf->cb_color_attrib2 = S_028C68_MIP0_WIDTH(surf->width0 - 1) |
2503 S_028C68_MIP0_HEIGHT(surf->height0 - 1) |
2504 S_028C68_MAX_MIP(tex->buffer.b.b.last_level);
2505 }
2506
2507 surf->cb_color_view = color_view;
2508 surf->cb_color_info = color_info;
2509 surf->cb_color_attrib = color_attrib;
2510
2511 /* Determine pixel shader export format */
2512 si_choose_spi_color_formats(surf, format, swap, ntype, tex->is_depth);
2513
2514 surf->color_initialized = true;
2515 }
2516
2517 static void si_init_depth_surface(struct si_context *sctx,
2518 struct si_surface *surf)
2519 {
2520 struct si_texture *tex = (struct si_texture*)surf->base.texture;
2521 unsigned level = surf->base.u.tex.level;
2522 unsigned format, stencil_format;
2523 uint32_t z_info, s_info;
2524
2525 format = si_translate_dbformat(tex->db_render_format);
2526 stencil_format = tex->surface.has_stencil ?
2527 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
2528
2529 assert(format != V_028040_Z_INVALID);
2530 if (format == V_028040_Z_INVALID)
2531 PRINT_ERR("Invalid DB format: %d, disabling DB.\n", tex->buffer.b.b.format);
2532
2533 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2534 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2535 surf->db_htile_data_base = 0;
2536 surf->db_htile_surface = 0;
2537
2538 if (sctx->chip_class >= GFX9) {
2539 assert(tex->surface.u.gfx9.surf_offset == 0);
2540 surf->db_depth_base = tex->buffer.gpu_address >> 8;
2541 surf->db_stencil_base = (tex->buffer.gpu_address +
2542 tex->surface.u.gfx9.stencil_offset) >> 8;
2543 z_info = S_028038_FORMAT(format) |
2544 S_028038_NUM_SAMPLES(util_logbase2(tex->buffer.b.b.nr_samples)) |
2545 S_028038_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
2546 S_028038_MAXMIP(tex->buffer.b.b.last_level);
2547 s_info = S_02803C_FORMAT(stencil_format) |
2548 S_02803C_SW_MODE(tex->surface.u.gfx9.stencil.swizzle_mode);
2549 surf->db_z_info2 = S_028068_EPITCH(tex->surface.u.gfx9.surf.epitch);
2550 surf->db_stencil_info2 = S_02806C_EPITCH(tex->surface.u.gfx9.stencil.epitch);
2551 surf->db_depth_view |= S_028008_MIPID(level);
2552 surf->db_depth_size = S_02801C_X_MAX(tex->buffer.b.b.width0 - 1) |
2553 S_02801C_Y_MAX(tex->buffer.b.b.height0 - 1);
2554
2555 if (si_htile_enabled(tex, level)) {
2556 z_info |= S_028038_TILE_SURFACE_ENABLE(1) |
2557 S_028038_ALLOW_EXPCLEAR(1);
2558
2559 if (tex->tc_compatible_htile) {
2560 unsigned max_zplanes = 4;
2561
2562 if (tex->db_render_format == PIPE_FORMAT_Z16_UNORM &&
2563 tex->buffer.b.b.nr_samples > 1)
2564 max_zplanes = 2;
2565
2566 z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1) |
2567 S_028038_ITERATE_FLUSH(1);
2568 s_info |= S_02803C_ITERATE_FLUSH(1);
2569 }
2570
2571 if (tex->surface.has_stencil) {
2572 /* Stencil buffer workaround ported from the SI-CI-VI code.
2573 * See that for explanation.
2574 */
2575 s_info |= S_02803C_ALLOW_EXPCLEAR(tex->buffer.b.b.nr_samples <= 1);
2576 } else {
2577 /* Use all HTILE for depth if there's no stencil. */
2578 s_info |= S_02803C_TILE_STENCIL_DISABLE(1);
2579 }
2580
2581 surf->db_htile_data_base = (tex->buffer.gpu_address +
2582 tex->htile_offset) >> 8;
2583 surf->db_htile_surface = S_028ABC_FULL_CACHE(1) |
2584 S_028ABC_PIPE_ALIGNED(tex->surface.u.gfx9.htile.pipe_aligned) |
2585 S_028ABC_RB_ALIGNED(tex->surface.u.gfx9.htile.rb_aligned);
2586 }
2587 } else {
2588 /* SI-CI-VI */
2589 struct legacy_surf_level *levelinfo = &tex->surface.u.legacy.level[level];
2590
2591 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2592
2593 surf->db_depth_base = (tex->buffer.gpu_address +
2594 tex->surface.u.legacy.level[level].offset) >> 8;
2595 surf->db_stencil_base = (tex->buffer.gpu_address +
2596 tex->surface.u.legacy.stencil_level[level].offset) >> 8;
2597
2598 z_info = S_028040_FORMAT(format) |
2599 S_028040_NUM_SAMPLES(util_logbase2(tex->buffer.b.b.nr_samples));
2600 s_info = S_028044_FORMAT(stencil_format);
2601 surf->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!tex->tc_compatible_htile);
2602
2603 if (sctx->chip_class >= CIK) {
2604 struct radeon_info *info = &sctx->screen->info;
2605 unsigned index = tex->surface.u.legacy.tiling_index[level];
2606 unsigned stencil_index = tex->surface.u.legacy.stencil_tiling_index[level];
2607 unsigned macro_index = tex->surface.u.legacy.macro_tile_index;
2608 unsigned tile_mode = info->si_tile_mode_array[index];
2609 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2610 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2611
2612 surf->db_depth_info |=
2613 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2614 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2615 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2616 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2617 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2618 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2619 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2620 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2621 } else {
2622 unsigned tile_mode_index = si_tile_mode_index(tex, level, false);
2623 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2624 tile_mode_index = si_tile_mode_index(tex, level, true);
2625 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2626 }
2627
2628 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2629 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2630 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2631 levelinfo->nblk_y) / 64 - 1);
2632
2633 if (si_htile_enabled(tex, level)) {
2634 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2635 S_028040_ALLOW_EXPCLEAR(1);
2636
2637 if (tex->surface.has_stencil) {
2638 /* Workaround: For a not yet understood reason, the
2639 * combination of MSAA, fast stencil clear and stencil
2640 * decompress messes with subsequent stencil buffer
2641 * uses. Problem was reproduced on Verde, Bonaire,
2642 * Tonga, and Carrizo.
2643 *
2644 * Disabling EXPCLEAR works around the problem.
2645 *
2646 * Check piglit's arb_texture_multisample-stencil-clear
2647 * test if you want to try changing this.
2648 */
2649 if (tex->buffer.b.b.nr_samples <= 1)
2650 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2651 } else if (!tex->tc_compatible_htile) {
2652 /* Use all of the htile_buffer for depth if there's no stencil.
2653 * This must not be set when TC-compatible HTILE is enabled
2654 * due to a hw bug.
2655 */
2656 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2657 }
2658
2659 surf->db_htile_data_base = (tex->buffer.gpu_address +
2660 tex->htile_offset) >> 8;
2661 surf->db_htile_surface = S_028ABC_FULL_CACHE(1);
2662
2663 if (tex->tc_compatible_htile) {
2664 surf->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
2665
2666 /* 0 = full compression. N = only compress up to N-1 Z planes. */
2667 if (tex->buffer.b.b.nr_samples <= 1)
2668 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2669 else if (tex->buffer.b.b.nr_samples <= 4)
2670 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2671 else
2672 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2673 }
2674 }
2675 }
2676
2677 surf->db_z_info = z_info;
2678 surf->db_stencil_info = s_info;
2679
2680 surf->depth_initialized = true;
2681 }
2682
2683 void si_update_fb_dirtiness_after_rendering(struct si_context *sctx)
2684 {
2685 if (sctx->decompression_enabled)
2686 return;
2687
2688 if (sctx->framebuffer.state.zsbuf) {
2689 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
2690 struct si_texture *tex = (struct si_texture *)surf->texture;
2691
2692 tex->dirty_level_mask |= 1 << surf->u.tex.level;
2693
2694 if (tex->surface.has_stencil)
2695 tex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
2696 }
2697
2698 unsigned compressed_cb_mask = sctx->framebuffer.compressed_cb_mask;
2699 while (compressed_cb_mask) {
2700 unsigned i = u_bit_scan(&compressed_cb_mask);
2701 struct pipe_surface *surf = sctx->framebuffer.state.cbufs[i];
2702 struct si_texture *tex = (struct si_texture*)surf->texture;
2703
2704 if (tex->surface.fmask_size)
2705 tex->dirty_level_mask |= 1 << surf->u.tex.level;
2706 if (tex->dcc_gather_statistics)
2707 tex->separate_dcc_dirty = true;
2708 }
2709 }
2710
2711 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
2712 {
2713 for (int i = 0; i < state->nr_cbufs; ++i) {
2714 struct si_surface *surf = NULL;
2715 struct si_texture *tex;
2716
2717 if (!state->cbufs[i])
2718 continue;
2719 surf = (struct si_surface*)state->cbufs[i];
2720 tex = (struct si_texture*)surf->base.texture;
2721
2722 p_atomic_dec(&tex->framebuffers_bound);
2723 }
2724 }
2725
2726 static void si_set_framebuffer_state(struct pipe_context *ctx,
2727 const struct pipe_framebuffer_state *state)
2728 {
2729 struct si_context *sctx = (struct si_context *)ctx;
2730 struct si_surface *surf = NULL;
2731 struct si_texture *tex;
2732 bool old_any_dst_linear = sctx->framebuffer.any_dst_linear;
2733 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2734 unsigned old_colorbuf_enabled_4bit = sctx->framebuffer.colorbuf_enabled_4bit;
2735 bool old_has_zsbuf = !!sctx->framebuffer.state.zsbuf;
2736 bool old_has_stencil =
2737 old_has_zsbuf &&
2738 ((struct si_texture*)sctx->framebuffer.state.zsbuf->texture)->surface.has_stencil;
2739 bool unbound = false;
2740 int i;
2741
2742 /* Reject zero-sized framebuffers due to a hw bug on SI that occurs
2743 * when PA_SU_HARDWARE_SCREEN_OFFSET != 0 and any_scissor.BR_X/Y <= 0.
2744 * We could implement the full workaround here, but it's a useless case.
2745 */
2746 if ((!state->width || !state->height) && (state->nr_cbufs || state->zsbuf)) {
2747 unreachable("the framebuffer shouldn't have zero area");
2748 return;
2749 }
2750
2751 si_update_fb_dirtiness_after_rendering(sctx);
2752
2753 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
2754 if (!sctx->framebuffer.state.cbufs[i])
2755 continue;
2756
2757 tex = (struct si_texture*)sctx->framebuffer.state.cbufs[i]->texture;
2758 if (tex->dcc_gather_statistics)
2759 vi_separate_dcc_stop_query(sctx, tex);
2760 }
2761
2762 /* Disable DCC if the formats are incompatible. */
2763 for (i = 0; i < state->nr_cbufs; i++) {
2764 if (!state->cbufs[i])
2765 continue;
2766
2767 surf = (struct si_surface*)state->cbufs[i];
2768 tex = (struct si_texture*)surf->base.texture;
2769
2770 if (!surf->dcc_incompatible)
2771 continue;
2772
2773 /* Since the DCC decompression calls back into set_framebuffer-
2774 * _state, we need to unbind the framebuffer, so that
2775 * vi_separate_dcc_stop_query isn't called twice with the same
2776 * color buffer.
2777 */
2778 if (!unbound) {
2779 util_copy_framebuffer_state(&sctx->framebuffer.state, NULL);
2780 unbound = true;
2781 }
2782
2783 if (vi_dcc_enabled(tex, surf->base.u.tex.level))
2784 if (!si_texture_disable_dcc(sctx, tex))
2785 si_decompress_dcc(sctx, tex);
2786
2787 surf->dcc_incompatible = false;
2788 }
2789
2790 /* Only flush TC when changing the framebuffer state, because
2791 * the only client not using TC that can change textures is
2792 * the framebuffer.
2793 *
2794 * Wait for compute shaders because of possible transitions:
2795 * - FB write -> shader read
2796 * - shader write -> FB read
2797 *
2798 * DB caches are flushed on demand (using si_decompress_textures).
2799 *
2800 * When MSAA is enabled, CB and TC caches are flushed on demand
2801 * (after FMASK decompression). Shader write -> FB read transitions
2802 * cannot happen for MSAA textures, because MSAA shader images are
2803 * not supported.
2804 *
2805 * Only flush and wait for CB if there is actually a bound color buffer.
2806 */
2807 if (sctx->framebuffer.uncompressed_cb_mask)
2808 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
2809 sctx->framebuffer.CB_has_shader_readable_metadata);
2810
2811 sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
2812
2813 /* u_blitter doesn't invoke depth decompression when it does multiple
2814 * blits in a row, but the only case when it matters for DB is when
2815 * doing generate_mipmap. So here we flush DB manually between
2816 * individual generate_mipmap blits.
2817 * Note that lower mipmap levels aren't compressed.
2818 */
2819 if (sctx->generate_mipmap_for_depth) {
2820 si_make_DB_shader_coherent(sctx, 1, false,
2821 sctx->framebuffer.DB_has_shader_readable_metadata);
2822 } else if (sctx->chip_class == GFX9) {
2823 /* It appears that DB metadata "leaks" in a sequence of:
2824 * - depth clear
2825 * - DCC decompress for shader image writes (with DB disabled)
2826 * - render with DEPTH_BEFORE_SHADER=1
2827 * Flushing DB metadata works around the problem.
2828 */
2829 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB_META;
2830 }
2831
2832 /* Take the maximum of the old and new count. If the new count is lower,
2833 * dirtying is needed to disable the unbound colorbuffers.
2834 */
2835 sctx->framebuffer.dirty_cbufs |=
2836 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2837 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2838
2839 si_dec_framebuffer_counters(&sctx->framebuffer.state);
2840 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2841
2842 sctx->framebuffer.colorbuf_enabled_4bit = 0;
2843 sctx->framebuffer.spi_shader_col_format = 0;
2844 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2845 sctx->framebuffer.spi_shader_col_format_blend = 0;
2846 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2847 sctx->framebuffer.color_is_int8 = 0;
2848 sctx->framebuffer.color_is_int10 = 0;
2849
2850 sctx->framebuffer.compressed_cb_mask = 0;
2851 sctx->framebuffer.uncompressed_cb_mask = 0;
2852 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2853 sctx->framebuffer.nr_color_samples = sctx->framebuffer.nr_samples;
2854 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2855 sctx->framebuffer.any_dst_linear = false;
2856 sctx->framebuffer.CB_has_shader_readable_metadata = false;
2857 sctx->framebuffer.DB_has_shader_readable_metadata = false;
2858
2859 for (i = 0; i < state->nr_cbufs; i++) {
2860 if (!state->cbufs[i])
2861 continue;
2862
2863 surf = (struct si_surface*)state->cbufs[i];
2864 tex = (struct si_texture*)surf->base.texture;
2865
2866 if (!surf->color_initialized) {
2867 si_initialize_color_surface(sctx, surf);
2868 }
2869
2870 sctx->framebuffer.colorbuf_enabled_4bit |= 0xf << (i * 4);
2871 sctx->framebuffer.spi_shader_col_format |=
2872 surf->spi_shader_col_format << (i * 4);
2873 sctx->framebuffer.spi_shader_col_format_alpha |=
2874 surf->spi_shader_col_format_alpha << (i * 4);
2875 sctx->framebuffer.spi_shader_col_format_blend |=
2876 surf->spi_shader_col_format_blend << (i * 4);
2877 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2878 surf->spi_shader_col_format_blend_alpha << (i * 4);
2879
2880 if (surf->color_is_int8)
2881 sctx->framebuffer.color_is_int8 |= 1 << i;
2882 if (surf->color_is_int10)
2883 sctx->framebuffer.color_is_int10 |= 1 << i;
2884
2885 if (tex->surface.fmask_size)
2886 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2887 else
2888 sctx->framebuffer.uncompressed_cb_mask |= 1 << i;
2889
2890 /* Don't update nr_color_samples for non-AA buffers.
2891 * (e.g. destination of MSAA resolve)
2892 */
2893 if (tex->buffer.b.b.nr_samples >= 2 &&
2894 tex->buffer.b.b.nr_storage_samples < tex->buffer.b.b.nr_samples) {
2895 sctx->framebuffer.nr_color_samples =
2896 MIN2(sctx->framebuffer.nr_color_samples,
2897 tex->buffer.b.b.nr_storage_samples);
2898 sctx->framebuffer.nr_color_samples =
2899 MAX2(1, sctx->framebuffer.nr_color_samples);
2900 }
2901
2902 if (tex->surface.is_linear)
2903 sctx->framebuffer.any_dst_linear = true;
2904
2905 if (vi_dcc_enabled(tex, surf->base.u.tex.level))
2906 sctx->framebuffer.CB_has_shader_readable_metadata = true;
2907
2908 si_context_add_resource_size(sctx, surf->base.texture);
2909
2910 p_atomic_inc(&tex->framebuffers_bound);
2911
2912 if (tex->dcc_gather_statistics) {
2913 /* Dirty tracking must be enabled for DCC usage analysis. */
2914 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2915 vi_separate_dcc_start_query(sctx, tex);
2916 }
2917 }
2918
2919 struct si_texture *zstex = NULL;
2920
2921 if (state->zsbuf) {
2922 surf = (struct si_surface*)state->zsbuf;
2923 zstex = (struct si_texture*)surf->base.texture;
2924
2925 if (!surf->depth_initialized) {
2926 si_init_depth_surface(sctx, surf);
2927 }
2928
2929 if (vi_tc_compat_htile_enabled(zstex, surf->base.u.tex.level))
2930 sctx->framebuffer.DB_has_shader_readable_metadata = true;
2931
2932 si_context_add_resource_size(sctx, surf->base.texture);
2933 }
2934
2935 si_update_ps_colorbuf0_slot(sctx);
2936 si_update_poly_offset_state(sctx);
2937 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
2938 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
2939
2940 if (sctx->screen->dpbb_allowed)
2941 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
2942
2943 if (sctx->framebuffer.any_dst_linear != old_any_dst_linear)
2944 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2945
2946 if (sctx->screen->has_out_of_order_rast &&
2947 (sctx->framebuffer.colorbuf_enabled_4bit != old_colorbuf_enabled_4bit ||
2948 !!sctx->framebuffer.state.zsbuf != old_has_zsbuf ||
2949 (zstex && zstex->surface.has_stencil != old_has_stencil)))
2950 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2951
2952 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2953 struct pipe_constant_buffer constbuf = {0};
2954
2955 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2956 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
2957
2958 constbuf.buffer = sctx->sample_pos_buffer;
2959
2960 /* Set sample locations as fragment shader constants. */
2961 switch (sctx->framebuffer.nr_samples) {
2962 case 1:
2963 constbuf.buffer_offset = 0;
2964 break;
2965 case 2:
2966 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x2 -
2967 (ubyte*)sctx->sample_positions.x1;
2968 break;
2969 case 4:
2970 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x4 -
2971 (ubyte*)sctx->sample_positions.x1;
2972 break;
2973 case 8:
2974 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x8 -
2975 (ubyte*)sctx->sample_positions.x1;
2976 break;
2977 case 16:
2978 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x16 -
2979 (ubyte*)sctx->sample_positions.x1;
2980 break;
2981 default:
2982 PRINT_ERR("Requested an invalid number of samples %i.\n",
2983 sctx->framebuffer.nr_samples);
2984 assert(0);
2985 }
2986 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2987 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
2988
2989 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
2990 }
2991
2992 sctx->do_update_shaders = true;
2993
2994 if (!sctx->decompression_enabled) {
2995 /* Prevent textures decompression when the framebuffer state
2996 * changes come from the decompression passes themselves.
2997 */
2998 sctx->need_check_render_feedback = true;
2999 }
3000 }
3001
3002 static void si_emit_framebuffer_state(struct si_context *sctx)
3003 {
3004 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3005 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
3006 unsigned i, nr_cbufs = state->nr_cbufs;
3007 struct si_texture *tex = NULL;
3008 struct si_surface *cb = NULL;
3009 unsigned cb_color_info = 0;
3010
3011 /* Colorbuffers. */
3012 for (i = 0; i < nr_cbufs; i++) {
3013 uint64_t cb_color_base, cb_color_fmask, cb_color_cmask, cb_dcc_base;
3014 unsigned cb_color_attrib;
3015
3016 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
3017 continue;
3018
3019 cb = (struct si_surface*)state->cbufs[i];
3020 if (!cb) {
3021 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
3022 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
3023 continue;
3024 }
3025
3026 tex = (struct si_texture *)cb->base.texture;
3027 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3028 &tex->buffer, RADEON_USAGE_READWRITE,
3029 tex->buffer.b.b.nr_samples > 1 ?
3030 RADEON_PRIO_COLOR_BUFFER_MSAA :
3031 RADEON_PRIO_COLOR_BUFFER);
3032
3033 if (tex->cmask_buffer && tex->cmask_buffer != &tex->buffer) {
3034 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3035 tex->cmask_buffer, RADEON_USAGE_READWRITE,
3036 RADEON_PRIO_SEPARATE_META);
3037 }
3038
3039 if (tex->dcc_separate_buffer)
3040 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3041 tex->dcc_separate_buffer,
3042 RADEON_USAGE_READWRITE,
3043 RADEON_PRIO_SEPARATE_META);
3044
3045 /* Compute mutable surface parameters. */
3046 cb_color_base = tex->buffer.gpu_address >> 8;
3047 cb_color_fmask = 0;
3048 cb_color_cmask = tex->cmask_base_address_reg;
3049 cb_dcc_base = 0;
3050 cb_color_info = cb->cb_color_info | tex->cb_color_info;
3051 cb_color_attrib = cb->cb_color_attrib;
3052
3053 if (cb->base.u.tex.level > 0)
3054 cb_color_info &= C_028C70_FAST_CLEAR;
3055
3056 if (tex->surface.fmask_size) {
3057 cb_color_fmask = (tex->buffer.gpu_address + tex->fmask_offset) >> 8;
3058 cb_color_fmask |= tex->surface.fmask_tile_swizzle;
3059 }
3060
3061 /* Set up DCC. */
3062 if (vi_dcc_enabled(tex, cb->base.u.tex.level)) {
3063 bool is_msaa_resolve_dst = state->cbufs[0] &&
3064 state->cbufs[0]->texture->nr_samples > 1 &&
3065 state->cbufs[1] == &cb->base &&
3066 state->cbufs[1]->texture->nr_samples <= 1;
3067
3068 if (!is_msaa_resolve_dst)
3069 cb_color_info |= S_028C70_DCC_ENABLE(1);
3070
3071 cb_dcc_base = ((!tex->dcc_separate_buffer ? tex->buffer.gpu_address : 0) +
3072 tex->dcc_offset) >> 8;
3073 cb_dcc_base |= tex->surface.tile_swizzle;
3074 }
3075
3076 if (sctx->chip_class >= GFX9) {
3077 struct gfx9_surf_meta_flags meta;
3078
3079 if (tex->dcc_offset)
3080 meta = tex->surface.u.gfx9.dcc;
3081 else
3082 meta = tex->surface.u.gfx9.cmask;
3083
3084 /* Set mutable surface parameters. */
3085 cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
3086 cb_color_base |= tex->surface.tile_swizzle;
3087 if (!tex->surface.fmask_size)
3088 cb_color_fmask = cb_color_base;
3089 if (cb->base.u.tex.level > 0)
3090 cb_color_cmask = cb_color_base;
3091 cb_color_attrib |= S_028C74_COLOR_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
3092 S_028C74_FMASK_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
3093 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3094 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3095
3096 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 15);
3097 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3098 radeon_emit(cs, S_028C64_BASE_256B(cb_color_base >> 32)); /* CB_COLOR0_BASE_EXT */
3099 radeon_emit(cs, cb->cb_color_attrib2); /* CB_COLOR0_ATTRIB2 */
3100 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3101 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3102 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3103 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3104 radeon_emit(cs, cb_color_cmask); /* CB_COLOR0_CMASK */
3105 radeon_emit(cs, S_028C80_BASE_256B(cb_color_cmask >> 32)); /* CB_COLOR0_CMASK_BASE_EXT */
3106 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3107 radeon_emit(cs, S_028C88_BASE_256B(cb_color_fmask >> 32)); /* CB_COLOR0_FMASK_BASE_EXT */
3108 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3109 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3110 radeon_emit(cs, cb_dcc_base); /* CB_COLOR0_DCC_BASE */
3111 radeon_emit(cs, S_028C98_BASE_256B(cb_dcc_base >> 32)); /* CB_COLOR0_DCC_BASE_EXT */
3112
3113 radeon_set_context_reg(cs, R_0287A0_CB_MRT0_EPITCH + i * 4,
3114 S_0287A0_EPITCH(tex->surface.u.gfx9.surf.epitch));
3115 } else {
3116 /* Compute mutable surface parameters (SI-CI-VI). */
3117 const struct legacy_surf_level *level_info =
3118 &tex->surface.u.legacy.level[cb->base.u.tex.level];
3119 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3120 unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
3121
3122 cb_color_base += level_info->offset >> 8;
3123 /* Only macrotiled modes can set tile swizzle. */
3124 if (level_info->mode == RADEON_SURF_MODE_2D)
3125 cb_color_base |= tex->surface.tile_swizzle;
3126
3127 if (!tex->surface.fmask_size)
3128 cb_color_fmask = cb_color_base;
3129 if (cb->base.u.tex.level > 0)
3130 cb_color_cmask = cb_color_base;
3131 if (cb_dcc_base)
3132 cb_dcc_base += level_info->dcc_offset >> 8;
3133
3134 pitch_tile_max = level_info->nblk_x / 8 - 1;
3135 slice_tile_max = level_info->nblk_x *
3136 level_info->nblk_y / 64 - 1;
3137 tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false);
3138
3139 cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3140 cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3141 cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3142
3143 if (tex->surface.fmask_size) {
3144 if (sctx->chip_class >= CIK)
3145 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->surface.u.legacy.fmask.pitch_in_pixels / 8 - 1);
3146 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->surface.u.legacy.fmask.tiling_index);
3147 cb_color_fmask_slice = S_028C88_TILE_MAX(tex->surface.u.legacy.fmask.slice_tile_max);
3148 } else {
3149 /* This must be set for fast clear to work without FMASK. */
3150 if (sctx->chip_class >= CIK)
3151 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3152 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3153 cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3154 }
3155
3156 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
3157 sctx->chip_class >= VI ? 14 : 13);
3158 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3159 radeon_emit(cs, cb_color_pitch); /* CB_COLOR0_PITCH */
3160 radeon_emit(cs, cb_color_slice); /* CB_COLOR0_SLICE */
3161 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3162 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3163 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3164 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3165 radeon_emit(cs, cb_color_cmask); /* CB_COLOR0_CMASK */
3166 radeon_emit(cs, tex->surface.u.legacy.cmask_slice_tile_max); /* CB_COLOR0_CMASK_SLICE */
3167 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3168 radeon_emit(cs, cb_color_fmask_slice); /* CB_COLOR0_FMASK_SLICE */
3169 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3170 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3171
3172 if (sctx->chip_class >= VI) /* R_028C94_CB_COLOR0_DCC_BASE */
3173 radeon_emit(cs, cb_dcc_base);
3174 }
3175 }
3176 for (; i < 8 ; i++)
3177 if (sctx->framebuffer.dirty_cbufs & (1 << i))
3178 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
3179
3180 /* ZS buffer. */
3181 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
3182 struct si_surface *zb = (struct si_surface*)state->zsbuf;
3183 struct si_texture *tex = (struct si_texture*)zb->base.texture;
3184
3185 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3186 &tex->buffer, RADEON_USAGE_READWRITE,
3187 zb->base.texture->nr_samples > 1 ?
3188 RADEON_PRIO_DEPTH_BUFFER_MSAA :
3189 RADEON_PRIO_DEPTH_BUFFER);
3190
3191 if (sctx->chip_class >= GFX9) {
3192 radeon_set_context_reg_seq(cs, R_028014_DB_HTILE_DATA_BASE, 3);
3193 radeon_emit(cs, zb->db_htile_data_base); /* DB_HTILE_DATA_BASE */
3194 radeon_emit(cs, S_028018_BASE_HI(zb->db_htile_data_base >> 32)); /* DB_HTILE_DATA_BASE_HI */
3195 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
3196
3197 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 10);
3198 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3199 S_028038_ZRANGE_PRECISION(tex->depth_clear_value != 0));
3200 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3201 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3202 radeon_emit(cs, S_028044_BASE_HI(zb->db_depth_base >> 32)); /* DB_Z_READ_BASE_HI */
3203 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3204 radeon_emit(cs, S_02804C_BASE_HI(zb->db_stencil_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
3205 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3206 radeon_emit(cs, S_028054_BASE_HI(zb->db_depth_base >> 32)); /* DB_Z_WRITE_BASE_HI */
3207 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3208 radeon_emit(cs, S_02805C_BASE_HI(zb->db_stencil_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
3209
3210 radeon_set_context_reg_seq(cs, R_028068_DB_Z_INFO2, 2);
3211 radeon_emit(cs, zb->db_z_info2); /* DB_Z_INFO2 */
3212 radeon_emit(cs, zb->db_stencil_info2); /* DB_STENCIL_INFO2 */
3213 } else {
3214 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
3215
3216 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
3217 radeon_emit(cs, zb->db_depth_info); /* DB_DEPTH_INFO */
3218 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3219 S_028040_ZRANGE_PRECISION(tex->depth_clear_value != 0));
3220 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3221 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3222 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3223 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3224 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3225 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
3226 radeon_emit(cs, zb->db_depth_slice); /* DB_DEPTH_SLICE */
3227 }
3228
3229 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
3230 radeon_emit(cs, tex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
3231 radeon_emit(cs, fui(tex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
3232
3233 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
3234 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
3235 } else if (sctx->framebuffer.dirty_zsbuf) {
3236 if (sctx->chip_class >= GFX9)
3237 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 2);
3238 else
3239 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
3240
3241 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
3242 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
3243 }
3244
3245 /* Framebuffer dimensions. */
3246 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
3247 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
3248 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
3249
3250 if (sctx->screen->dfsm_allowed) {
3251 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3252 radeon_emit(cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
3253 }
3254
3255 sctx->framebuffer.dirty_cbufs = 0;
3256 sctx->framebuffer.dirty_zsbuf = false;
3257 }
3258
3259 static void si_emit_msaa_sample_locs(struct si_context *sctx)
3260 {
3261 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3262 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3263 unsigned nr_samples = sctx->framebuffer.nr_samples;
3264 bool has_msaa_sample_loc_bug = sctx->screen->has_msaa_sample_loc_bug;
3265
3266 /* Smoothing (only possible with nr_samples == 1) uses the same
3267 * sample locations as the MSAA it simulates.
3268 */
3269 if (nr_samples <= 1 && sctx->smoothing_enabled)
3270 nr_samples = SI_NUM_SMOOTH_AA_SAMPLES;
3271
3272 /* On Polaris, the small primitive filter uses the sample locations
3273 * even when MSAA is off, so we need to make sure they're set to 0.
3274 */
3275 if ((nr_samples >= 2 || has_msaa_sample_loc_bug) &&
3276 nr_samples != sctx->sample_locs_num_samples) {
3277 sctx->sample_locs_num_samples = nr_samples;
3278 si_emit_sample_locations(cs, nr_samples);
3279 }
3280
3281 if (sctx->family >= CHIP_POLARIS10) {
3282 unsigned small_prim_filter_cntl =
3283 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
3284 /* line bug */
3285 S_028830_LINE_FILTER_DISABLE(sctx->family <= CHIP_POLARIS12);
3286
3287 /* The alternative of setting sample locations to 0 would
3288 * require a DB flush to avoid Z errors, see
3289 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
3290 */
3291 if (has_msaa_sample_loc_bug &&
3292 sctx->framebuffer.nr_samples > 1 &&
3293 !rs->multisample_enable)
3294 small_prim_filter_cntl &= C_028830_SMALL_PRIM_FILTER_ENABLE;
3295
3296 radeon_opt_set_context_reg(sctx,
3297 R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
3298 SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL,
3299 small_prim_filter_cntl);
3300 }
3301
3302 /* The exclusion bits can be set to improve rasterization efficiency
3303 * if no sample lies on the pixel boundary (-8 sample offset).
3304 */
3305 bool exclusion = sctx->chip_class >= CIK &&
3306 (!rs->multisample_enable || nr_samples != 16);
3307 radeon_opt_set_context_reg(sctx, R_02882C_PA_SU_PRIM_FILTER_CNTL,
3308 SI_TRACKED_PA_SU_PRIM_FILTER_CNTL,
3309 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) |
3310 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion));
3311 }
3312
3313 static bool si_out_of_order_rasterization(struct si_context *sctx)
3314 {
3315 struct si_state_blend *blend = sctx->queued.named.blend;
3316 struct si_state_dsa *dsa = sctx->queued.named.dsa;
3317
3318 if (!sctx->screen->has_out_of_order_rast)
3319 return false;
3320
3321 unsigned colormask = sctx->framebuffer.colorbuf_enabled_4bit;
3322
3323 if (blend) {
3324 colormask &= blend->cb_target_enabled_4bit;
3325 } else {
3326 colormask = 0;
3327 }
3328
3329 /* Conservative: No logic op. */
3330 if (colormask && blend->logicop_enable)
3331 return false;
3332
3333 struct si_dsa_order_invariance dsa_order_invariant = {
3334 .zs = true, .pass_set = true, .pass_last = false
3335 };
3336
3337 if (sctx->framebuffer.state.zsbuf) {
3338 struct si_texture *zstex =
3339 (struct si_texture*)sctx->framebuffer.state.zsbuf->texture;
3340 bool has_stencil = zstex->surface.has_stencil;
3341 dsa_order_invariant = dsa->order_invariance[has_stencil];
3342 if (!dsa_order_invariant.zs)
3343 return false;
3344
3345 /* The set of PS invocations is always order invariant,
3346 * except when early Z/S tests are requested. */
3347 if (sctx->ps_shader.cso &&
3348 sctx->ps_shader.cso->info.writes_memory &&
3349 sctx->ps_shader.cso->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] &&
3350 !dsa_order_invariant.pass_set)
3351 return false;
3352
3353 if (sctx->num_perfect_occlusion_queries != 0 &&
3354 !dsa_order_invariant.pass_set)
3355 return false;
3356 }
3357
3358 if (!colormask)
3359 return true;
3360
3361 unsigned blendmask = colormask & blend->blend_enable_4bit;
3362
3363 if (blendmask) {
3364 /* Only commutative blending. */
3365 if (blendmask & ~blend->commutative_4bit)
3366 return false;
3367
3368 if (!dsa_order_invariant.pass_set)
3369 return false;
3370 }
3371
3372 if (colormask & ~blendmask) {
3373 if (!dsa_order_invariant.pass_last)
3374 return false;
3375 }
3376
3377 return true;
3378 }
3379
3380 static void si_emit_msaa_config(struct si_context *sctx)
3381 {
3382 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3383 unsigned num_tile_pipes = sctx->screen->info.num_tile_pipes;
3384 /* 33% faster rendering to linear color buffers */
3385 bool dst_is_linear = sctx->framebuffer.any_dst_linear;
3386 bool out_of_order_rast = si_out_of_order_rasterization(sctx);
3387 unsigned sc_mode_cntl_1 =
3388 S_028A4C_WALK_SIZE(dst_is_linear) |
3389 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear) |
3390 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
3391 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
3392 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
3393 /* always 1: */
3394 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
3395 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
3396 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
3397 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
3398 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
3399 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
3400 unsigned db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3401 S_028804_INCOHERENT_EQAA_READS(1) |
3402 S_028804_INTERPOLATE_COMP_Z(1) |
3403 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
3404 unsigned coverage_samples, color_samples, z_samples;
3405
3406 /* S: Coverage samples (up to 16x):
3407 * - Scan conversion samples (PA_SC_AA_CONFIG.MSAA_NUM_SAMPLES)
3408 * - CB FMASK samples (CB_COLORi_ATTRIB.NUM_SAMPLES)
3409 *
3410 * Z: Z/S samples (up to 8x, must be <= coverage samples and >= color samples):
3411 * - Value seen by DB (DB_Z_INFO.NUM_SAMPLES)
3412 * - Value seen by CB, must be correct even if Z/S is unbound (DB_EQAA.MAX_ANCHOR_SAMPLES)
3413 * # Missing samples are derived from Z planes if Z is compressed (up to 16x quality), or
3414 * # from the closest defined sample if Z is uncompressed (same quality as the number of
3415 * # Z samples).
3416 *
3417 * F: Color samples (up to 8x, must be <= coverage samples):
3418 * - CB color samples (CB_COLORi_ATTRIB.NUM_FRAGMENTS)
3419 * - PS iter samples (DB_EQAA.PS_ITER_SAMPLES)
3420 *
3421 * Can be anything between coverage and color samples:
3422 * - SampleMaskIn samples (PA_SC_AA_CONFIG.MSAA_EXPOSED_SAMPLES)
3423 * - SampleMaskOut samples (DB_EQAA.MASK_EXPORT_NUM_SAMPLES)
3424 * - Alpha-to-coverage samples (DB_EQAA.ALPHA_TO_MASK_NUM_SAMPLES)
3425 * - Occlusion query samples (DB_COUNT_CONTROL.SAMPLE_RATE)
3426 * # All are currently set the same as coverage samples.
3427 *
3428 * If color samples < coverage samples, FMASK has a higher bpp to store an "unknown"
3429 * flag for undefined color samples. A shader-based resolve must handle unknowns
3430 * or mask them out with AND. Unknowns can also be guessed from neighbors via
3431 * an edge-detect shader-based resolve, which is required to make "color samples = 1"
3432 * useful. The CB resolve always drops unknowns.
3433 *
3434 * Sensible AA configurations:
3435 * EQAA 16s 8z 8f - might look the same as 16x MSAA if Z is compressed
3436 * EQAA 16s 8z 4f - might look the same as 16x MSAA if Z is compressed
3437 * EQAA 16s 4z 4f - might look the same as 16x MSAA if Z is compressed
3438 * EQAA 8s 8z 8f = 8x MSAA
3439 * EQAA 8s 8z 4f - might look the same as 8x MSAA
3440 * EQAA 8s 8z 2f - might look the same as 8x MSAA with low-density geometry
3441 * EQAA 8s 4z 4f - might look the same as 8x MSAA if Z is compressed
3442 * EQAA 8s 4z 2f - might look the same as 8x MSAA with low-density geometry if Z is compressed
3443 * EQAA 4s 4z 4f = 4x MSAA
3444 * EQAA 4s 4z 2f - might look the same as 4x MSAA with low-density geometry
3445 * EQAA 2s 2z 2f = 2x MSAA
3446 */
3447 if (sctx->framebuffer.nr_samples > 1) {
3448 coverage_samples = sctx->framebuffer.nr_samples;
3449 color_samples = sctx->framebuffer.nr_color_samples;
3450
3451 if (sctx->framebuffer.state.zsbuf) {
3452 z_samples = sctx->framebuffer.state.zsbuf->texture->nr_samples;
3453 z_samples = MAX2(1, z_samples);
3454 } else {
3455 z_samples = coverage_samples;
3456 }
3457 } else if (sctx->smoothing_enabled) {
3458 coverage_samples = color_samples = z_samples = SI_NUM_SMOOTH_AA_SAMPLES;
3459 } else {
3460 coverage_samples = color_samples = z_samples = 1;
3461 }
3462
3463 /* Required by OpenGL line rasterization.
3464 *
3465 * TODO: We should also enable perpendicular endcaps for AA lines,
3466 * but that requires implementing line stippling in the pixel
3467 * shader. SC can only do line stippling with axis-aligned
3468 * endcaps.
3469 */
3470 unsigned sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
3471 unsigned sc_aa_config = 0;
3472
3473 if (coverage_samples > 1) {
3474 /* distance from the pixel center, indexed by log2(nr_samples) */
3475 static unsigned max_dist[] = {
3476 0, /* unused */
3477 4, /* 2x MSAA */
3478 6, /* 4x MSAA */
3479 7, /* 8x MSAA */
3480 8, /* 16x MSAA */
3481 };
3482 unsigned log_samples = util_logbase2(coverage_samples);
3483 unsigned log_z_samples = util_logbase2(z_samples);
3484 unsigned ps_iter_samples = si_get_ps_iter_samples(sctx);
3485 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
3486
3487 sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1);
3488 sc_aa_config = S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
3489 S_028BE0_MAX_SAMPLE_DIST(max_dist[log_samples]) |
3490 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples);
3491
3492 if (sctx->framebuffer.nr_samples > 1) {
3493 db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples) |
3494 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
3495 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
3496 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
3497 sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
3498 } else if (sctx->smoothing_enabled) {
3499 db_eqaa |= S_028804_OVERRASTERIZATION_AMOUNT(log_samples);
3500 }
3501 }
3502
3503 unsigned initial_cdw = cs->current.cdw;
3504
3505 /* R_028BDC_PA_SC_LINE_CNTL, R_028BE0_PA_SC_AA_CONFIG */
3506 radeon_opt_set_context_reg2(sctx, R_028BDC_PA_SC_LINE_CNTL,
3507 SI_TRACKED_PA_SC_LINE_CNTL, sc_line_cntl,
3508 sc_aa_config);
3509 /* R_028804_DB_EQAA */
3510 radeon_opt_set_context_reg(sctx, R_028804_DB_EQAA, SI_TRACKED_DB_EQAA,
3511 db_eqaa);
3512 /* R_028A4C_PA_SC_MODE_CNTL_1 */
3513 radeon_opt_set_context_reg(sctx, R_028A4C_PA_SC_MODE_CNTL_1,
3514 SI_TRACKED_PA_SC_MODE_CNTL_1, sc_mode_cntl_1);
3515
3516 if (initial_cdw != cs->current.cdw) {
3517 sctx->context_roll_counter++;
3518
3519 /* GFX9: Flush DFSM when the AA mode changes. */
3520 if (sctx->screen->dfsm_allowed) {
3521 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3522 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
3523 }
3524 }
3525 }
3526
3527 void si_update_ps_iter_samples(struct si_context *sctx)
3528 {
3529 if (sctx->framebuffer.nr_samples > 1)
3530 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3531 if (sctx->screen->dpbb_allowed)
3532 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
3533 }
3534
3535 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
3536 {
3537 struct si_context *sctx = (struct si_context *)ctx;
3538
3539 /* The hardware can only do sample shading with 2^n samples. */
3540 min_samples = util_next_power_of_two(min_samples);
3541
3542 if (sctx->ps_iter_samples == min_samples)
3543 return;
3544
3545 sctx->ps_iter_samples = min_samples;
3546 sctx->do_update_shaders = true;
3547
3548 si_update_ps_iter_samples(sctx);
3549 }
3550
3551 /*
3552 * Samplers
3553 */
3554
3555 /**
3556 * Build the sampler view descriptor for a buffer texture.
3557 * @param state 256-bit descriptor; only the high 128 bits are filled in
3558 */
3559 void
3560 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
3561 enum pipe_format format,
3562 unsigned offset, unsigned size,
3563 uint32_t *state)
3564 {
3565 const struct util_format_description *desc;
3566 int first_non_void;
3567 unsigned stride;
3568 unsigned num_records;
3569 unsigned num_format, data_format;
3570
3571 desc = util_format_description(format);
3572 first_non_void = util_format_get_first_non_void_channel(format);
3573 stride = desc->block.bits / 8;
3574 num_format = si_translate_buffer_numformat(&screen->b, desc, first_non_void);
3575 data_format = si_translate_buffer_dataformat(&screen->b, desc, first_non_void);
3576
3577 num_records = size / stride;
3578 num_records = MIN2(num_records, (buf->b.b.width0 - offset) / stride);
3579
3580 /* The NUM_RECORDS field has a different meaning depending on the chip,
3581 * instruction type, STRIDE, and SWIZZLE_ENABLE.
3582 *
3583 * SI-CIK:
3584 * - If STRIDE == 0, it's in byte units.
3585 * - If STRIDE != 0, it's in units of STRIDE, used with inst.IDXEN.
3586 *
3587 * VI:
3588 * - For SMEM and STRIDE == 0, it's in byte units.
3589 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3590 * - For VMEM and STRIDE == 0 or SWIZZLE_ENABLE == 0, it's in byte units.
3591 * - For VMEM and STRIDE != 0 and SWIZZLE_ENABLE == 1, it's in units of STRIDE.
3592 * NOTE: There is incompatibility between VMEM and SMEM opcodes due to SWIZZLE_-
3593 * ENABLE. The workaround is to set STRIDE = 0 if SWIZZLE_ENABLE == 0 when
3594 * using SMEM. This can be done in the shader by clearing STRIDE with s_and.
3595 * That way the same descriptor can be used by both SMEM and VMEM.
3596 *
3597 * GFX9:
3598 * - For SMEM and STRIDE == 0, it's in byte units.
3599 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3600 * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
3601 * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
3602 */
3603 if (screen->info.chip_class >= GFX9)
3604 /* When vindex == 0, LLVM sets IDXEN = 0, thus changing units
3605 * from STRIDE to bytes. This works around it by setting
3606 * NUM_RECORDS to at least the size of one element, so that
3607 * the first element is readable when IDXEN == 0.
3608 *
3609 * TODO: Fix this in LLVM, but do we need a new intrinsic where
3610 * IDXEN is enforced?
3611 */
3612 num_records = num_records ? MAX2(num_records, stride) : 0;
3613 else if (screen->info.chip_class == VI)
3614 num_records *= stride;
3615
3616 state[4] = 0;
3617 state[5] = S_008F04_STRIDE(stride);
3618 state[6] = num_records;
3619 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3620 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3621 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3622 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
3623 S_008F0C_NUM_FORMAT(num_format) |
3624 S_008F0C_DATA_FORMAT(data_format);
3625 }
3626
3627 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle[4])
3628 {
3629 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3630
3631 if (swizzle[3] == PIPE_SWIZZLE_X) {
3632 /* For the pre-defined border color values (white, opaque
3633 * black, transparent black), the only thing that matters is
3634 * that the alpha channel winds up in the correct place
3635 * (because the RGB channels are all the same) so either of
3636 * these enumerations will work.
3637 */
3638 if (swizzle[2] == PIPE_SWIZZLE_Y)
3639 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
3640 else
3641 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
3642 } else if (swizzle[0] == PIPE_SWIZZLE_X) {
3643 if (swizzle[1] == PIPE_SWIZZLE_Y)
3644 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3645 else
3646 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
3647 } else if (swizzle[1] == PIPE_SWIZZLE_X) {
3648 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
3649 } else if (swizzle[2] == PIPE_SWIZZLE_X) {
3650 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
3651 }
3652
3653 return bc_swizzle;
3654 }
3655
3656 /**
3657 * Build the sampler view descriptor for a texture.
3658 */
3659 void
3660 si_make_texture_descriptor(struct si_screen *screen,
3661 struct si_texture *tex,
3662 bool sampler,
3663 enum pipe_texture_target target,
3664 enum pipe_format pipe_format,
3665 const unsigned char state_swizzle[4],
3666 unsigned first_level, unsigned last_level,
3667 unsigned first_layer, unsigned last_layer,
3668 unsigned width, unsigned height, unsigned depth,
3669 uint32_t *state,
3670 uint32_t *fmask_state)
3671 {
3672 struct pipe_resource *res = &tex->buffer.b.b;
3673 const struct util_format_description *desc;
3674 unsigned char swizzle[4];
3675 int first_non_void;
3676 unsigned num_format, data_format, type, num_samples;
3677 uint64_t va;
3678
3679 desc = util_format_description(pipe_format);
3680
3681 num_samples = desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS ?
3682 MAX2(1, res->nr_samples) :
3683 MAX2(1, res->nr_storage_samples);
3684
3685 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
3686 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
3687 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
3688 const unsigned char swizzle_wwww[4] = {3, 3, 3, 3};
3689
3690 switch (pipe_format) {
3691 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3692 case PIPE_FORMAT_X32_S8X24_UINT:
3693 case PIPE_FORMAT_X8Z24_UNORM:
3694 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3695 break;
3696 case PIPE_FORMAT_X24S8_UINT:
3697 /*
3698 * X24S8 is implemented as an 8_8_8_8 data format, to
3699 * fix texture gathers. This affects at least
3700 * GL45-CTS.texture_cube_map_array.sampling on VI.
3701 */
3702 if (screen->info.chip_class <= VI)
3703 util_format_compose_swizzles(swizzle_wwww, state_swizzle, swizzle);
3704 else
3705 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3706 break;
3707 default:
3708 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
3709 }
3710 } else {
3711 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
3712 }
3713
3714 first_non_void = util_format_get_first_non_void_channel(pipe_format);
3715
3716 switch (pipe_format) {
3717 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3718 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3719 break;
3720 default:
3721 if (first_non_void < 0) {
3722 if (util_format_is_compressed(pipe_format)) {
3723 switch (pipe_format) {
3724 case PIPE_FORMAT_DXT1_SRGB:
3725 case PIPE_FORMAT_DXT1_SRGBA:
3726 case PIPE_FORMAT_DXT3_SRGBA:
3727 case PIPE_FORMAT_DXT5_SRGBA:
3728 case PIPE_FORMAT_BPTC_SRGBA:
3729 case PIPE_FORMAT_ETC2_SRGB8:
3730 case PIPE_FORMAT_ETC2_SRGB8A1:
3731 case PIPE_FORMAT_ETC2_SRGBA8:
3732 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3733 break;
3734 case PIPE_FORMAT_RGTC1_SNORM:
3735 case PIPE_FORMAT_LATC1_SNORM:
3736 case PIPE_FORMAT_RGTC2_SNORM:
3737 case PIPE_FORMAT_LATC2_SNORM:
3738 case PIPE_FORMAT_ETC2_R11_SNORM:
3739 case PIPE_FORMAT_ETC2_RG11_SNORM:
3740 /* implies float, so use SNORM/UNORM to determine
3741 whether data is signed or not */
3742 case PIPE_FORMAT_BPTC_RGB_FLOAT:
3743 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3744 break;
3745 default:
3746 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3747 break;
3748 }
3749 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
3750 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3751 } else {
3752 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3753 }
3754 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
3755 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3756 } else {
3757 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3758
3759 switch (desc->channel[first_non_void].type) {
3760 case UTIL_FORMAT_TYPE_FLOAT:
3761 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3762 break;
3763 case UTIL_FORMAT_TYPE_SIGNED:
3764 if (desc->channel[first_non_void].normalized)
3765 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3766 else if (desc->channel[first_non_void].pure_integer)
3767 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
3768 else
3769 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
3770 break;
3771 case UTIL_FORMAT_TYPE_UNSIGNED:
3772 if (desc->channel[first_non_void].normalized)
3773 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3774 else if (desc->channel[first_non_void].pure_integer)
3775 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3776 else
3777 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
3778 }
3779 }
3780 }
3781
3782 data_format = si_translate_texformat(&screen->b, pipe_format, desc, first_non_void);
3783 if (data_format == ~0) {
3784 data_format = 0;
3785 }
3786
3787 /* S8 with Z32 HTILE needs a special format. */
3788 if (screen->info.chip_class >= GFX9 &&
3789 pipe_format == PIPE_FORMAT_S8_UINT &&
3790 tex->tc_compatible_htile)
3791 data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
3792
3793 if (!sampler &&
3794 (res->target == PIPE_TEXTURE_CUBE ||
3795 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
3796 (screen->info.chip_class <= VI &&
3797 res->target == PIPE_TEXTURE_3D))) {
3798 /* For the purpose of shader images, treat cube maps and 3D
3799 * textures as 2D arrays. For 3D textures, the address
3800 * calculations for mipmaps are different, so we rely on the
3801 * caller to effectively disable mipmaps.
3802 */
3803 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
3804
3805 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
3806 } else {
3807 type = si_tex_dim(screen, tex, target, num_samples);
3808 }
3809
3810 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
3811 height = 1;
3812 depth = res->array_size;
3813 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
3814 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
3815 if (sampler || res->target != PIPE_TEXTURE_3D)
3816 depth = res->array_size;
3817 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
3818 depth = res->array_size / 6;
3819
3820 state[0] = 0;
3821 state[1] = (S_008F14_DATA_FORMAT_GFX6(data_format) |
3822 S_008F14_NUM_FORMAT_GFX6(num_format));
3823 state[2] = (S_008F18_WIDTH(width - 1) |
3824 S_008F18_HEIGHT(height - 1) |
3825 S_008F18_PERF_MOD(4));
3826 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
3827 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
3828 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
3829 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
3830 S_008F1C_BASE_LEVEL(num_samples > 1 ? 0 : first_level) |
3831 S_008F1C_LAST_LEVEL(num_samples > 1 ?
3832 util_logbase2(num_samples) :
3833 last_level) |
3834 S_008F1C_TYPE(type));
3835 state[4] = 0;
3836 state[5] = S_008F24_BASE_ARRAY(first_layer);
3837 state[6] = 0;
3838 state[7] = 0;
3839
3840 if (screen->info.chip_class >= GFX9) {
3841 unsigned bc_swizzle = gfx9_border_color_swizzle(desc->swizzle);
3842
3843 /* Depth is the the last accessible layer on Gfx9.
3844 * The hw doesn't need to know the total number of layers.
3845 */
3846 if (type == V_008F1C_SQ_RSRC_IMG_3D)
3847 state[4] |= S_008F20_DEPTH(depth - 1);
3848 else
3849 state[4] |= S_008F20_DEPTH(last_layer);
3850
3851 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
3852 state[5] |= S_008F24_MAX_MIP(num_samples > 1 ?
3853 util_logbase2(num_samples) :
3854 tex->buffer.b.b.last_level);
3855 } else {
3856 state[3] |= S_008F1C_POW2_PAD(res->last_level > 0);
3857 state[4] |= S_008F20_DEPTH(depth - 1);
3858 state[5] |= S_008F24_LAST_ARRAY(last_layer);
3859 }
3860
3861 if (tex->dcc_offset) {
3862 state[6] = S_008F28_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(pipe_format));
3863 } else {
3864 /* The last dword is unused by hw. The shader uses it to clear
3865 * bits in the first dword of sampler state.
3866 */
3867 if (screen->info.chip_class <= CIK && res->nr_samples <= 1) {
3868 if (first_level == last_level)
3869 state[7] = C_008F30_MAX_ANISO_RATIO;
3870 else
3871 state[7] = 0xffffffff;
3872 }
3873 }
3874
3875 /* Initialize the sampler view for FMASK. */
3876 if (tex->surface.fmask_size) {
3877 uint32_t data_format, num_format;
3878
3879 va = tex->buffer.gpu_address + tex->fmask_offset;
3880
3881 #define FMASK(s,f) (((unsigned)(MAX2(1, s)) * 16) + (MAX2(1, f)))
3882 if (screen->info.chip_class >= GFX9) {
3883 data_format = V_008F14_IMG_DATA_FORMAT_FMASK;
3884 switch (FMASK(res->nr_samples, res->nr_storage_samples)) {
3885 case FMASK(2,1):
3886 num_format = V_008F14_IMG_FMASK_8_2_1;
3887 break;
3888 case FMASK(2,2):
3889 num_format = V_008F14_IMG_FMASK_8_2_2;
3890 break;
3891 case FMASK(4,1):
3892 num_format = V_008F14_IMG_FMASK_8_4_1;
3893 break;
3894 case FMASK(4,2):
3895 num_format = V_008F14_IMG_FMASK_8_4_2;
3896 break;
3897 case FMASK(4,4):
3898 num_format = V_008F14_IMG_FMASK_8_4_4;
3899 break;
3900 case FMASK(8,1):
3901 num_format = V_008F14_IMG_FMASK_8_8_1;
3902 break;
3903 case FMASK(8,2):
3904 num_format = V_008F14_IMG_FMASK_16_8_2;
3905 break;
3906 case FMASK(8,4):
3907 num_format = V_008F14_IMG_FMASK_32_8_4;
3908 break;
3909 case FMASK(8,8):
3910 num_format = V_008F14_IMG_FMASK_32_8_8;
3911 break;
3912 case FMASK(16,1):
3913 num_format = V_008F14_IMG_FMASK_16_16_1;
3914 break;
3915 case FMASK(16,2):
3916 num_format = V_008F14_IMG_FMASK_32_16_2;
3917 break;
3918 case FMASK(16,4):
3919 num_format = V_008F14_IMG_FMASK_64_16_4;
3920 break;
3921 case FMASK(16,8):
3922 num_format = V_008F14_IMG_FMASK_64_16_8;
3923 break;
3924 default:
3925 unreachable("invalid nr_samples");
3926 }
3927 } else {
3928 switch (FMASK(res->nr_samples, res->nr_storage_samples)) {
3929 case FMASK(2,1):
3930 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F1;
3931 break;
3932 case FMASK(2,2):
3933 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
3934 break;
3935 case FMASK(4,1):
3936 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F1;
3937 break;
3938 case FMASK(4,2):
3939 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F2;
3940 break;
3941 case FMASK(4,4):
3942 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
3943 break;
3944 case FMASK(8,1):
3945 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S8_F1;
3946 break;
3947 case FMASK(8,2):
3948 data_format = V_008F14_IMG_DATA_FORMAT_FMASK16_S8_F2;
3949 break;
3950 case FMASK(8,4):
3951 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F4;
3952 break;
3953 case FMASK(8,8):
3954 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
3955 break;
3956 case FMASK(16,1):
3957 data_format = V_008F14_IMG_DATA_FORMAT_FMASK16_S16_F1;
3958 break;
3959 case FMASK(16,2):
3960 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S16_F2;
3961 break;
3962 case FMASK(16,4):
3963 data_format = V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F4;
3964 break;
3965 case FMASK(16,8):
3966 data_format = V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F8;
3967 break;
3968 default:
3969 unreachable("invalid nr_samples");
3970 }
3971 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3972 }
3973 #undef FMASK
3974
3975 fmask_state[0] = (va >> 8) | tex->surface.fmask_tile_swizzle;
3976 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
3977 S_008F14_DATA_FORMAT_GFX6(data_format) |
3978 S_008F14_NUM_FORMAT_GFX6(num_format);
3979 fmask_state[2] = S_008F18_WIDTH(width - 1) |
3980 S_008F18_HEIGHT(height - 1);
3981 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
3982 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
3983 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
3984 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
3985 S_008F1C_TYPE(si_tex_dim(screen, tex, target, 0));
3986 fmask_state[4] = 0;
3987 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
3988 fmask_state[6] = 0;
3989 fmask_state[7] = 0;
3990
3991 if (screen->info.chip_class >= GFX9) {
3992 fmask_state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode);
3993 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
3994 S_008F20_PITCH_GFX9(tex->surface.u.gfx9.fmask.epitch);
3995 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned) |
3996 S_008F24_META_RB_ALIGNED(tex->surface.u.gfx9.cmask.rb_aligned);
3997 } else {
3998 fmask_state[3] |= S_008F1C_TILING_INDEX(tex->surface.u.legacy.fmask.tiling_index);
3999 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
4000 S_008F20_PITCH_GFX6(tex->surface.u.legacy.fmask.pitch_in_pixels - 1);
4001 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
4002 }
4003 }
4004 }
4005
4006 /**
4007 * Create a sampler view.
4008 *
4009 * @param ctx context
4010 * @param texture texture
4011 * @param state sampler view template
4012 * @param width0 width0 override (for compressed textures as int)
4013 * @param height0 height0 override (for compressed textures as int)
4014 * @param force_level set the base address to the level (for compressed textures)
4015 */
4016 struct pipe_sampler_view *
4017 si_create_sampler_view_custom(struct pipe_context *ctx,
4018 struct pipe_resource *texture,
4019 const struct pipe_sampler_view *state,
4020 unsigned width0, unsigned height0,
4021 unsigned force_level)
4022 {
4023 struct si_context *sctx = (struct si_context*)ctx;
4024 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
4025 struct si_texture *tex = (struct si_texture*)texture;
4026 unsigned base_level, first_level, last_level;
4027 unsigned char state_swizzle[4];
4028 unsigned height, depth, width;
4029 unsigned last_layer = state->u.tex.last_layer;
4030 enum pipe_format pipe_format;
4031 const struct legacy_surf_level *surflevel;
4032
4033 if (!view)
4034 return NULL;
4035
4036 /* initialize base object */
4037 view->base = *state;
4038 view->base.texture = NULL;
4039 view->base.reference.count = 1;
4040 view->base.context = ctx;
4041
4042 assert(texture);
4043 pipe_resource_reference(&view->base.texture, texture);
4044
4045 if (state->format == PIPE_FORMAT_X24S8_UINT ||
4046 state->format == PIPE_FORMAT_S8X24_UINT ||
4047 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
4048 state->format == PIPE_FORMAT_S8_UINT)
4049 view->is_stencil_sampler = true;
4050
4051 /* Buffer resource. */
4052 if (texture->target == PIPE_BUFFER) {
4053 si_make_buffer_descriptor(sctx->screen,
4054 r600_resource(texture),
4055 state->format,
4056 state->u.buf.offset,
4057 state->u.buf.size,
4058 view->state);
4059 return &view->base;
4060 }
4061
4062 state_swizzle[0] = state->swizzle_r;
4063 state_swizzle[1] = state->swizzle_g;
4064 state_swizzle[2] = state->swizzle_b;
4065 state_swizzle[3] = state->swizzle_a;
4066
4067 base_level = 0;
4068 first_level = state->u.tex.first_level;
4069 last_level = state->u.tex.last_level;
4070 width = width0;
4071 height = height0;
4072 depth = texture->depth0;
4073
4074 if (sctx->chip_class <= VI && force_level) {
4075 assert(force_level == first_level &&
4076 force_level == last_level);
4077 base_level = force_level;
4078 first_level = 0;
4079 last_level = 0;
4080 width = u_minify(width, force_level);
4081 height = u_minify(height, force_level);
4082 depth = u_minify(depth, force_level);
4083 }
4084
4085 /* This is not needed if state trackers set last_layer correctly. */
4086 if (state->target == PIPE_TEXTURE_1D ||
4087 state->target == PIPE_TEXTURE_2D ||
4088 state->target == PIPE_TEXTURE_RECT ||
4089 state->target == PIPE_TEXTURE_CUBE)
4090 last_layer = state->u.tex.first_layer;
4091
4092 /* Texturing with separate depth and stencil. */
4093 pipe_format = state->format;
4094
4095 /* Depth/stencil texturing sometimes needs separate texture. */
4096 if (tex->is_depth && !si_can_sample_zs(tex, view->is_stencil_sampler)) {
4097 if (!tex->flushed_depth_texture &&
4098 !si_init_flushed_depth_texture(ctx, texture, NULL)) {
4099 pipe_resource_reference(&view->base.texture, NULL);
4100 FREE(view);
4101 return NULL;
4102 }
4103
4104 assert(tex->flushed_depth_texture);
4105
4106 /* Override format for the case where the flushed texture
4107 * contains only Z or only S.
4108 */
4109 if (tex->flushed_depth_texture->buffer.b.b.format != tex->buffer.b.b.format)
4110 pipe_format = tex->flushed_depth_texture->buffer.b.b.format;
4111
4112 tex = tex->flushed_depth_texture;
4113 }
4114
4115 surflevel = tex->surface.u.legacy.level;
4116
4117 if (tex->db_compatible) {
4118 if (!view->is_stencil_sampler)
4119 pipe_format = tex->db_render_format;
4120
4121 switch (pipe_format) {
4122 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
4123 pipe_format = PIPE_FORMAT_Z32_FLOAT;
4124 break;
4125 case PIPE_FORMAT_X8Z24_UNORM:
4126 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
4127 /* Z24 is always stored like this for DB
4128 * compatibility.
4129 */
4130 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
4131 break;
4132 case PIPE_FORMAT_X24S8_UINT:
4133 case PIPE_FORMAT_S8X24_UINT:
4134 case PIPE_FORMAT_X32_S8X24_UINT:
4135 pipe_format = PIPE_FORMAT_S8_UINT;
4136 surflevel = tex->surface.u.legacy.stencil_level;
4137 break;
4138 default:;
4139 }
4140 }
4141
4142 view->dcc_incompatible =
4143 vi_dcc_formats_are_incompatible(texture,
4144 state->u.tex.first_level,
4145 state->format);
4146
4147 si_make_texture_descriptor(sctx->screen, tex, true,
4148 state->target, pipe_format, state_swizzle,
4149 first_level, last_level,
4150 state->u.tex.first_layer, last_layer,
4151 width, height, depth,
4152 view->state, view->fmask_state);
4153
4154 unsigned num_format = G_008F14_NUM_FORMAT_GFX6(view->state[1]);
4155 view->is_integer =
4156 num_format == V_008F14_IMG_NUM_FORMAT_USCALED ||
4157 num_format == V_008F14_IMG_NUM_FORMAT_SSCALED ||
4158 num_format == V_008F14_IMG_NUM_FORMAT_UINT ||
4159 num_format == V_008F14_IMG_NUM_FORMAT_SINT;
4160 view->base_level_info = &surflevel[base_level];
4161 view->base_level = base_level;
4162 view->block_width = util_format_get_blockwidth(pipe_format);
4163 return &view->base;
4164 }
4165
4166 static struct pipe_sampler_view *
4167 si_create_sampler_view(struct pipe_context *ctx,
4168 struct pipe_resource *texture,
4169 const struct pipe_sampler_view *state)
4170 {
4171 return si_create_sampler_view_custom(ctx, texture, state,
4172 texture ? texture->width0 : 0,
4173 texture ? texture->height0 : 0, 0);
4174 }
4175
4176 static void si_sampler_view_destroy(struct pipe_context *ctx,
4177 struct pipe_sampler_view *state)
4178 {
4179 struct si_sampler_view *view = (struct si_sampler_view *)state;
4180
4181 pipe_resource_reference(&state->texture, NULL);
4182 FREE(view);
4183 }
4184
4185 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
4186 {
4187 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
4188 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
4189 (linear_filter &&
4190 (wrap == PIPE_TEX_WRAP_CLAMP ||
4191 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
4192 }
4193
4194 static uint32_t si_translate_border_color(struct si_context *sctx,
4195 const struct pipe_sampler_state *state,
4196 const union pipe_color_union *color,
4197 bool is_integer)
4198 {
4199 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
4200 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
4201
4202 if (!wrap_mode_uses_border_color(state->wrap_s, linear_filter) &&
4203 !wrap_mode_uses_border_color(state->wrap_t, linear_filter) &&
4204 !wrap_mode_uses_border_color(state->wrap_r, linear_filter))
4205 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK);
4206
4207 #define simple_border_types(elt) \
4208 do { \
4209 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4210 color->elt[2] == 0 && color->elt[3] == 0) \
4211 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK); \
4212 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4213 color->elt[2] == 0 && color->elt[3] == 1) \
4214 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK); \
4215 if (color->elt[0] == 1 && color->elt[1] == 1 && \
4216 color->elt[2] == 1 && color->elt[3] == 1) \
4217 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE); \
4218 } while (false)
4219
4220 if (is_integer)
4221 simple_border_types(ui);
4222 else
4223 simple_border_types(f);
4224
4225 #undef simple_border_types
4226
4227 int i;
4228
4229 /* Check if the border has been uploaded already. */
4230 for (i = 0; i < sctx->border_color_count; i++)
4231 if (memcmp(&sctx->border_color_table[i], color,
4232 sizeof(*color)) == 0)
4233 break;
4234
4235 if (i >= SI_MAX_BORDER_COLORS) {
4236 /* Getting 4096 unique border colors is very unlikely. */
4237 fprintf(stderr, "radeonsi: The border color table is full. "
4238 "Any new border colors will be just black. "
4239 "Please file a bug.\n");
4240 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK);
4241 }
4242
4243 if (i == sctx->border_color_count) {
4244 /* Upload a new border color. */
4245 memcpy(&sctx->border_color_table[i], color,
4246 sizeof(*color));
4247 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
4248 color, sizeof(*color));
4249 sctx->border_color_count++;
4250 }
4251
4252 return S_008F3C_BORDER_COLOR_PTR(i) |
4253 S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER);
4254 }
4255
4256 static inline int S_FIXED(float value, unsigned frac_bits)
4257 {
4258 return value * (1 << frac_bits);
4259 }
4260
4261 static inline unsigned si_tex_filter(unsigned filter, unsigned max_aniso)
4262 {
4263 if (filter == PIPE_TEX_FILTER_LINEAR)
4264 return max_aniso > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
4265 : V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
4266 else
4267 return max_aniso > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
4268 : V_008F38_SQ_TEX_XY_FILTER_POINT;
4269 }
4270
4271 static inline unsigned si_tex_aniso_filter(unsigned filter)
4272 {
4273 if (filter < 2)
4274 return 0;
4275 if (filter < 4)
4276 return 1;
4277 if (filter < 8)
4278 return 2;
4279 if (filter < 16)
4280 return 3;
4281 return 4;
4282 }
4283
4284 static void *si_create_sampler_state(struct pipe_context *ctx,
4285 const struct pipe_sampler_state *state)
4286 {
4287 struct si_context *sctx = (struct si_context *)ctx;
4288 struct si_screen *sscreen = sctx->screen;
4289 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
4290 unsigned max_aniso = sscreen->force_aniso >= 0 ? sscreen->force_aniso
4291 : state->max_anisotropy;
4292 unsigned max_aniso_ratio = si_tex_aniso_filter(max_aniso);
4293 union pipe_color_union clamped_border_color;
4294
4295 if (!rstate) {
4296 return NULL;
4297 }
4298
4299 #ifdef DEBUG
4300 rstate->magic = SI_SAMPLER_STATE_MAGIC;
4301 #endif
4302 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
4303 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
4304 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
4305 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4306 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
4307 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
4308 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4309 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4310 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
4311 S_008F30_COMPAT_MODE(sctx->chip_class >= VI));
4312 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
4313 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)) |
4314 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4315 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
4316 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter, max_aniso)) |
4317 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter, max_aniso)) |
4318 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
4319 S_008F38_MIP_POINT_PRECLAMP(0) |
4320 S_008F38_DISABLE_LSB_CEIL(sctx->chip_class <= VI) |
4321 S_008F38_FILTER_PREC_FIX(1) |
4322 S_008F38_ANISO_OVERRIDE(sctx->chip_class >= VI));
4323 rstate->val[3] = si_translate_border_color(sctx, state, &state->border_color, false);
4324
4325 /* Create sampler resource for integer textures. */
4326 memcpy(rstate->integer_val, rstate->val, sizeof(rstate->val));
4327 rstate->integer_val[3] = si_translate_border_color(sctx, state, &state->border_color, true);
4328
4329 /* Create sampler resource for upgraded depth textures. */
4330 memcpy(rstate->upgraded_depth_val, rstate->val, sizeof(rstate->val));
4331
4332 for (unsigned i = 0; i < 4; ++i) {
4333 /* Use channel 0 on purpose, so that we can use OPAQUE_WHITE
4334 * when the border color is 1.0. */
4335 clamped_border_color.f[i] = CLAMP(state->border_color.f[0], 0, 1);
4336 }
4337
4338 if (memcmp(&state->border_color, &clamped_border_color, sizeof(clamped_border_color)) == 0)
4339 rstate->upgraded_depth_val[3] |= S_008F3C_UPGRADED_DEPTH(1);
4340 else
4341 rstate->upgraded_depth_val[3] =
4342 si_translate_border_color(sctx, state, &clamped_border_color, false) |
4343 S_008F3C_UPGRADED_DEPTH(1);
4344
4345 return rstate;
4346 }
4347
4348 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
4349 {
4350 struct si_context *sctx = (struct si_context *)ctx;
4351
4352 if (sctx->sample_mask == (uint16_t)sample_mask)
4353 return;
4354
4355 sctx->sample_mask = sample_mask;
4356 si_mark_atom_dirty(sctx, &sctx->atoms.s.sample_mask);
4357 }
4358
4359 static void si_emit_sample_mask(struct si_context *sctx)
4360 {
4361 struct radeon_cmdbuf *cs = sctx->gfx_cs;
4362 unsigned mask = sctx->sample_mask;
4363
4364 /* Needed for line and polygon smoothing as well as for the Polaris
4365 * small primitive filter. We expect the state tracker to take care of
4366 * this for us.
4367 */
4368 assert(mask == 0xffff || sctx->framebuffer.nr_samples > 1 ||
4369 (mask & 1 && sctx->blitter->running));
4370
4371 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
4372 radeon_emit(cs, mask | (mask << 16));
4373 radeon_emit(cs, mask | (mask << 16));
4374 }
4375
4376 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
4377 {
4378 #ifdef DEBUG
4379 struct si_sampler_state *s = state;
4380
4381 assert(s->magic == SI_SAMPLER_STATE_MAGIC);
4382 s->magic = 0;
4383 #endif
4384 free(state);
4385 }
4386
4387 /*
4388 * Vertex elements & buffers
4389 */
4390
4391 struct util_fast_udiv_info32 {
4392 unsigned multiplier; /* the "magic number" multiplier */
4393 unsigned pre_shift; /* shift for the dividend before multiplying */
4394 unsigned post_shift; /* shift for the dividend after multiplying */
4395 int increment; /* 0 or 1; if set then increment the numerator, using one of
4396 the two strategies */
4397 };
4398
4399 static struct util_fast_udiv_info32
4400 util_compute_fast_udiv_info32(uint32_t D, unsigned num_bits)
4401 {
4402 struct util_fast_udiv_info info =
4403 util_compute_fast_udiv_info(D, num_bits, 32);
4404
4405 struct util_fast_udiv_info32 result = {
4406 info.multiplier,
4407 info.pre_shift,
4408 info.post_shift,
4409 info.increment,
4410 };
4411 return result;
4412 }
4413
4414 static void *si_create_vertex_elements(struct pipe_context *ctx,
4415 unsigned count,
4416 const struct pipe_vertex_element *elements)
4417 {
4418 struct si_screen *sscreen = (struct si_screen*)ctx->screen;
4419 struct si_vertex_elements *v = CALLOC_STRUCT(si_vertex_elements);
4420 bool used[SI_NUM_VERTEX_BUFFERS] = {};
4421 struct util_fast_udiv_info32 divisor_factors[SI_MAX_ATTRIBS] = {};
4422 STATIC_ASSERT(sizeof(struct util_fast_udiv_info32) == 16);
4423 STATIC_ASSERT(sizeof(divisor_factors[0].multiplier) == 4);
4424 STATIC_ASSERT(sizeof(divisor_factors[0].pre_shift) == 4);
4425 STATIC_ASSERT(sizeof(divisor_factors[0].post_shift) == 4);
4426 STATIC_ASSERT(sizeof(divisor_factors[0].increment) == 4);
4427 int i;
4428
4429 assert(count <= SI_MAX_ATTRIBS);
4430 if (!v)
4431 return NULL;
4432
4433 v->count = count;
4434 v->desc_list_byte_size = align(count * 16, SI_CPDMA_ALIGNMENT);
4435
4436 for (i = 0; i < count; ++i) {
4437 const struct util_format_description *desc;
4438 const struct util_format_channel_description *channel;
4439 unsigned data_format, num_format;
4440 int first_non_void;
4441 unsigned vbo_index = elements[i].vertex_buffer_index;
4442 unsigned char swizzle[4];
4443
4444 if (vbo_index >= SI_NUM_VERTEX_BUFFERS) {
4445 FREE(v);
4446 return NULL;
4447 }
4448
4449 unsigned instance_divisor = elements[i].instance_divisor;
4450 if (instance_divisor) {
4451 v->uses_instance_divisors = true;
4452
4453 if (instance_divisor == 1) {
4454 v->instance_divisor_is_one |= 1u << i;
4455 } else {
4456 v->instance_divisor_is_fetched |= 1u << i;
4457 divisor_factors[i] =
4458 util_compute_fast_udiv_info32(instance_divisor, 32);
4459 }
4460 }
4461
4462 if (!used[vbo_index]) {
4463 v->first_vb_use_mask |= 1 << i;
4464 used[vbo_index] = true;
4465 }
4466
4467 desc = util_format_description(elements[i].src_format);
4468 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
4469 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
4470 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
4471 channel = first_non_void >= 0 ? &desc->channel[first_non_void] : NULL;
4472 memcpy(swizzle, desc->swizzle, sizeof(swizzle));
4473
4474 v->format_size[i] = desc->block.bits / 8;
4475 v->src_offset[i] = elements[i].src_offset;
4476 v->vertex_buffer_index[i] = vbo_index;
4477
4478 /* The hardware always treats the 2-bit alpha channel as
4479 * unsigned, so a shader workaround is needed. The affected
4480 * chips are VI and older except Stoney (GFX8.1).
4481 */
4482 if (data_format == V_008F0C_BUF_DATA_FORMAT_2_10_10_10 &&
4483 sscreen->info.chip_class <= VI &&
4484 sscreen->info.family != CHIP_STONEY) {
4485 if (num_format == V_008F0C_BUF_NUM_FORMAT_SNORM) {
4486 v->fix_fetch[i] = SI_FIX_FETCH_A2_SNORM;
4487 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SSCALED) {
4488 v->fix_fetch[i] = SI_FIX_FETCH_A2_SSCALED;
4489 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SINT) {
4490 /* This isn't actually used in OpenGL. */
4491 v->fix_fetch[i] = SI_FIX_FETCH_A2_SINT;
4492 }
4493 } else if (channel && channel->type == UTIL_FORMAT_TYPE_FIXED) {
4494 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
4495 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_FIXED;
4496 else
4497 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_FIXED;
4498 } else if (channel && channel->size == 32 && !channel->pure_integer) {
4499 if (channel->type == UTIL_FORMAT_TYPE_SIGNED) {
4500 if (channel->normalized) {
4501 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
4502 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_SNORM;
4503 else
4504 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SNORM;
4505 } else {
4506 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SSCALED;
4507 }
4508 } else if (channel->type == UTIL_FORMAT_TYPE_UNSIGNED) {
4509 if (channel->normalized) {
4510 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
4511 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_UNORM;
4512 else
4513 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_UNORM;
4514 } else {
4515 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_USCALED;
4516 }
4517 }
4518 } else if (channel && channel->size == 64 &&
4519 channel->type == UTIL_FORMAT_TYPE_FLOAT) {
4520 switch (desc->nr_channels) {
4521 case 1:
4522 case 2:
4523 v->fix_fetch[i] = SI_FIX_FETCH_RG_64_FLOAT;
4524 swizzle[0] = PIPE_SWIZZLE_X;
4525 swizzle[1] = PIPE_SWIZZLE_Y;
4526 swizzle[2] = desc->nr_channels == 2 ? PIPE_SWIZZLE_Z : PIPE_SWIZZLE_0;
4527 swizzle[3] = desc->nr_channels == 2 ? PIPE_SWIZZLE_W : PIPE_SWIZZLE_0;
4528 break;
4529 case 3:
4530 v->fix_fetch[i] = SI_FIX_FETCH_RGB_64_FLOAT;
4531 swizzle[0] = PIPE_SWIZZLE_X; /* 3 loads */
4532 swizzle[1] = PIPE_SWIZZLE_Y;
4533 swizzle[2] = PIPE_SWIZZLE_0;
4534 swizzle[3] = PIPE_SWIZZLE_0;
4535 break;
4536 case 4:
4537 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_64_FLOAT;
4538 swizzle[0] = PIPE_SWIZZLE_X; /* 2 loads */
4539 swizzle[1] = PIPE_SWIZZLE_Y;
4540 swizzle[2] = PIPE_SWIZZLE_Z;
4541 swizzle[3] = PIPE_SWIZZLE_W;
4542 break;
4543 default:
4544 assert(0);
4545 }
4546 } else if (channel && desc->nr_channels == 3) {
4547 assert(desc->swizzle[0] == PIPE_SWIZZLE_X);
4548
4549 if (channel->size == 8) {
4550 if (channel->pure_integer)
4551 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8_INT;
4552 else
4553 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8;
4554 } else if (channel->size == 16) {
4555 if (channel->pure_integer)
4556 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16_INT;
4557 else
4558 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16;
4559 }
4560 }
4561
4562 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
4563 S_008F0C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
4564 S_008F0C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
4565 S_008F0C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
4566 S_008F0C_NUM_FORMAT(num_format) |
4567 S_008F0C_DATA_FORMAT(data_format);
4568 }
4569
4570 if (v->instance_divisor_is_fetched) {
4571 unsigned num_divisors = util_last_bit(v->instance_divisor_is_fetched);
4572
4573 v->instance_divisor_factor_buffer =
4574 (struct r600_resource*)
4575 pipe_buffer_create(&sscreen->b, 0, PIPE_USAGE_DEFAULT,
4576 num_divisors * sizeof(divisor_factors[0]));
4577 if (!v->instance_divisor_factor_buffer) {
4578 FREE(v);
4579 return NULL;
4580 }
4581 void *map = sscreen->ws->buffer_map(v->instance_divisor_factor_buffer->buf,
4582 NULL, PIPE_TRANSFER_WRITE);
4583 memcpy(map , divisor_factors, num_divisors * sizeof(divisor_factors[0]));
4584 }
4585 return v;
4586 }
4587
4588 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
4589 {
4590 struct si_context *sctx = (struct si_context *)ctx;
4591 struct si_vertex_elements *old = sctx->vertex_elements;
4592 struct si_vertex_elements *v = (struct si_vertex_elements*)state;
4593
4594 sctx->vertex_elements = v;
4595 sctx->vertex_buffers_dirty = true;
4596
4597 if (v &&
4598 (!old ||
4599 old->count != v->count ||
4600 old->uses_instance_divisors != v->uses_instance_divisors ||
4601 v->uses_instance_divisors || /* we don't check which divisors changed */
4602 memcmp(old->fix_fetch, v->fix_fetch, sizeof(v->fix_fetch[0]) * v->count)))
4603 sctx->do_update_shaders = true;
4604
4605 if (v && v->instance_divisor_is_fetched) {
4606 struct pipe_constant_buffer cb;
4607
4608 cb.buffer = &v->instance_divisor_factor_buffer->b.b;
4609 cb.user_buffer = NULL;
4610 cb.buffer_offset = 0;
4611 cb.buffer_size = 0xffffffff;
4612 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS, &cb);
4613 }
4614 }
4615
4616 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
4617 {
4618 struct si_context *sctx = (struct si_context *)ctx;
4619 struct si_vertex_elements *v = (struct si_vertex_elements*)state;
4620
4621 if (sctx->vertex_elements == state)
4622 sctx->vertex_elements = NULL;
4623 r600_resource_reference(&v->instance_divisor_factor_buffer, NULL);
4624 FREE(state);
4625 }
4626
4627 static void si_set_vertex_buffers(struct pipe_context *ctx,
4628 unsigned start_slot, unsigned count,
4629 const struct pipe_vertex_buffer *buffers)
4630 {
4631 struct si_context *sctx = (struct si_context *)ctx;
4632 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
4633 int i;
4634
4635 assert(start_slot + count <= ARRAY_SIZE(sctx->vertex_buffer));
4636
4637 if (buffers) {
4638 for (i = 0; i < count; i++) {
4639 const struct pipe_vertex_buffer *src = buffers + i;
4640 struct pipe_vertex_buffer *dsti = dst + i;
4641 struct pipe_resource *buf = src->buffer.resource;
4642
4643 pipe_resource_reference(&dsti->buffer.resource, buf);
4644 dsti->buffer_offset = src->buffer_offset;
4645 dsti->stride = src->stride;
4646 si_context_add_resource_size(sctx, buf);
4647 if (buf)
4648 r600_resource(buf)->bind_history |= PIPE_BIND_VERTEX_BUFFER;
4649 }
4650 } else {
4651 for (i = 0; i < count; i++) {
4652 pipe_resource_reference(&dst[i].buffer.resource, NULL);
4653 }
4654 }
4655 sctx->vertex_buffers_dirty = true;
4656 }
4657
4658 /*
4659 * Misc
4660 */
4661
4662 static void si_set_tess_state(struct pipe_context *ctx,
4663 const float default_outer_level[4],
4664 const float default_inner_level[2])
4665 {
4666 struct si_context *sctx = (struct si_context *)ctx;
4667 struct pipe_constant_buffer cb;
4668 float array[8];
4669
4670 memcpy(array, default_outer_level, sizeof(float) * 4);
4671 memcpy(array+4, default_inner_level, sizeof(float) * 2);
4672
4673 cb.buffer = NULL;
4674 cb.user_buffer = NULL;
4675 cb.buffer_size = sizeof(array);
4676
4677 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
4678 (void*)array, sizeof(array),
4679 &cb.buffer_offset);
4680
4681 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
4682 pipe_resource_reference(&cb.buffer, NULL);
4683 }
4684
4685 static void si_texture_barrier(struct pipe_context *ctx, unsigned flags)
4686 {
4687 struct si_context *sctx = (struct si_context *)ctx;
4688
4689 si_update_fb_dirtiness_after_rendering(sctx);
4690
4691 /* Multisample surfaces are flushed in si_decompress_textures. */
4692 if (sctx->framebuffer.uncompressed_cb_mask)
4693 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
4694 sctx->framebuffer.CB_has_shader_readable_metadata);
4695 }
4696
4697 /* This only ensures coherency for shader image/buffer stores. */
4698 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
4699 {
4700 struct si_context *sctx = (struct si_context *)ctx;
4701
4702 /* Subsequent commands must wait for all shader invocations to
4703 * complete. */
4704 sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
4705 SI_CONTEXT_CS_PARTIAL_FLUSH;
4706
4707 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
4708 sctx->flags |= SI_CONTEXT_INV_SMEM_L1 |
4709 SI_CONTEXT_INV_VMEM_L1;
4710
4711 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
4712 PIPE_BARRIER_SHADER_BUFFER |
4713 PIPE_BARRIER_TEXTURE |
4714 PIPE_BARRIER_IMAGE |
4715 PIPE_BARRIER_STREAMOUT_BUFFER |
4716 PIPE_BARRIER_GLOBAL_BUFFER)) {
4717 /* As far as I can tell, L1 contents are written back to L2
4718 * automatically at end of shader, but the contents of other
4719 * L1 caches might still be stale. */
4720 sctx->flags |= SI_CONTEXT_INV_VMEM_L1;
4721 }
4722
4723 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
4724 /* Indices are read through TC L2 since VI.
4725 * L1 isn't used.
4726 */
4727 if (sctx->screen->info.chip_class <= CIK)
4728 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4729 }
4730
4731 /* MSAA color, any depth and any stencil are flushed in
4732 * si_decompress_textures when needed.
4733 */
4734 if (flags & PIPE_BARRIER_FRAMEBUFFER &&
4735 sctx->framebuffer.uncompressed_cb_mask) {
4736 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
4737
4738 if (sctx->chip_class <= VI)
4739 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4740 }
4741
4742 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
4743 if (sctx->screen->info.chip_class <= VI &&
4744 flags & PIPE_BARRIER_INDIRECT_BUFFER)
4745 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4746 }
4747
4748 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
4749 {
4750 struct pipe_blend_state blend;
4751
4752 memset(&blend, 0, sizeof(blend));
4753 blend.independent_blend_enable = true;
4754 blend.rt[0].colormask = 0xf;
4755 return si_create_blend_state_mode(&sctx->b, &blend, mode);
4756 }
4757
4758 static void si_init_config(struct si_context *sctx);
4759
4760 void si_init_state_functions(struct si_context *sctx)
4761 {
4762 sctx->atoms.s.framebuffer.emit = si_emit_framebuffer_state;
4763 sctx->atoms.s.msaa_sample_locs.emit = si_emit_msaa_sample_locs;
4764 sctx->atoms.s.db_render_state.emit = si_emit_db_render_state;
4765 sctx->atoms.s.dpbb_state.emit = si_emit_dpbb_state;
4766 sctx->atoms.s.msaa_config.emit = si_emit_msaa_config;
4767 sctx->atoms.s.sample_mask.emit = si_emit_sample_mask;
4768 sctx->atoms.s.cb_render_state.emit = si_emit_cb_render_state;
4769 sctx->atoms.s.blend_color.emit = si_emit_blend_color;
4770 sctx->atoms.s.clip_regs.emit = si_emit_clip_regs;
4771 sctx->atoms.s.clip_state.emit = si_emit_clip_state;
4772 sctx->atoms.s.stencil_ref.emit = si_emit_stencil_ref;
4773
4774 sctx->b.create_blend_state = si_create_blend_state;
4775 sctx->b.bind_blend_state = si_bind_blend_state;
4776 sctx->b.delete_blend_state = si_delete_blend_state;
4777 sctx->b.set_blend_color = si_set_blend_color;
4778
4779 sctx->b.create_rasterizer_state = si_create_rs_state;
4780 sctx->b.bind_rasterizer_state = si_bind_rs_state;
4781 sctx->b.delete_rasterizer_state = si_delete_rs_state;
4782
4783 sctx->b.create_depth_stencil_alpha_state = si_create_dsa_state;
4784 sctx->b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
4785 sctx->b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
4786
4787 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
4788 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
4789 sctx->custom_blend_fmask_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
4790 sctx->custom_blend_eliminate_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
4791 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
4792
4793 sctx->b.set_clip_state = si_set_clip_state;
4794 sctx->b.set_stencil_ref = si_set_stencil_ref;
4795
4796 sctx->b.set_framebuffer_state = si_set_framebuffer_state;
4797
4798 sctx->b.create_sampler_state = si_create_sampler_state;
4799 sctx->b.delete_sampler_state = si_delete_sampler_state;
4800
4801 sctx->b.create_sampler_view = si_create_sampler_view;
4802 sctx->b.sampler_view_destroy = si_sampler_view_destroy;
4803
4804 sctx->b.set_sample_mask = si_set_sample_mask;
4805
4806 sctx->b.create_vertex_elements_state = si_create_vertex_elements;
4807 sctx->b.bind_vertex_elements_state = si_bind_vertex_elements;
4808 sctx->b.delete_vertex_elements_state = si_delete_vertex_element;
4809 sctx->b.set_vertex_buffers = si_set_vertex_buffers;
4810
4811 sctx->b.texture_barrier = si_texture_barrier;
4812 sctx->b.memory_barrier = si_memory_barrier;
4813 sctx->b.set_min_samples = si_set_min_samples;
4814 sctx->b.set_tess_state = si_set_tess_state;
4815
4816 sctx->b.set_active_query_state = si_set_active_query_state;
4817
4818 sctx->b.draw_vbo = si_draw_vbo;
4819
4820 si_init_config(sctx);
4821 }
4822
4823 void si_init_screen_state_functions(struct si_screen *sscreen)
4824 {
4825 sscreen->b.is_format_supported = si_is_format_supported;
4826 }
4827
4828 static void si_set_grbm_gfx_index(struct si_context *sctx,
4829 struct si_pm4_state *pm4, unsigned value)
4830 {
4831 unsigned reg = sctx->chip_class >= CIK ? R_030800_GRBM_GFX_INDEX :
4832 R_00802C_GRBM_GFX_INDEX;
4833 si_pm4_set_reg(pm4, reg, value);
4834 }
4835
4836 static void si_set_grbm_gfx_index_se(struct si_context *sctx,
4837 struct si_pm4_state *pm4, unsigned se)
4838 {
4839 assert(se == ~0 || se < sctx->screen->info.max_se);
4840 si_set_grbm_gfx_index(sctx, pm4,
4841 (se == ~0 ? S_030800_SE_BROADCAST_WRITES(1) :
4842 S_030800_SE_INDEX(se)) |
4843 S_030800_SH_BROADCAST_WRITES(1) |
4844 S_030800_INSTANCE_BROADCAST_WRITES(1));
4845 }
4846
4847 static void
4848 si_write_harvested_raster_configs(struct si_context *sctx,
4849 struct si_pm4_state *pm4,
4850 unsigned raster_config,
4851 unsigned raster_config_1)
4852 {
4853 unsigned num_se = MAX2(sctx->screen->info.max_se, 1);
4854 unsigned raster_config_se[4];
4855 unsigned se;
4856
4857 ac_get_harvested_configs(&sctx->screen->info,
4858 raster_config,
4859 &raster_config_1,
4860 raster_config_se);
4861
4862 for (se = 0; se < num_se; se++) {
4863 si_set_grbm_gfx_index_se(sctx, pm4, se);
4864 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se[se]);
4865 }
4866 si_set_grbm_gfx_index(sctx, pm4, ~0);
4867
4868 if (sctx->chip_class >= CIK) {
4869 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
4870 }
4871 }
4872
4873 static void si_set_raster_config(struct si_context *sctx, struct si_pm4_state *pm4)
4874 {
4875 struct si_screen *sscreen = sctx->screen;
4876 unsigned num_rb = MIN2(sscreen->info.num_render_backends, 16);
4877 unsigned rb_mask = sscreen->info.enabled_rb_mask;
4878 unsigned raster_config = sscreen->pa_sc_raster_config;
4879 unsigned raster_config_1 = sscreen->pa_sc_raster_config_1;
4880
4881 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
4882 /* Always use the default config when all backends are enabled
4883 * (or when we failed to determine the enabled backends).
4884 */
4885 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
4886 raster_config);
4887 if (sctx->chip_class >= CIK)
4888 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
4889 raster_config_1);
4890 } else {
4891 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
4892 }
4893 }
4894
4895 static void si_init_config(struct si_context *sctx)
4896 {
4897 struct si_screen *sscreen = sctx->screen;
4898 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
4899 bool has_clear_state = sscreen->has_clear_state;
4900 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
4901
4902 /* SI, radeon kernel disabled CLEAR_STATE. */
4903 assert(has_clear_state || sscreen->info.chip_class == SI ||
4904 sscreen->info.drm_major != 3);
4905
4906 if (!pm4)
4907 return;
4908
4909 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
4910 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
4911 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
4912 si_pm4_cmd_end(pm4, false);
4913
4914 if (has_clear_state) {
4915 si_pm4_cmd_begin(pm4, PKT3_CLEAR_STATE);
4916 si_pm4_cmd_add(pm4, 0);
4917 si_pm4_cmd_end(pm4, false);
4918 }
4919
4920 if (sctx->chip_class <= VI)
4921 si_set_raster_config(sctx, pm4);
4922
4923 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
4924 if (!has_clear_state)
4925 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
4926
4927 /* FIXME calculate these values somehow ??? */
4928 if (sctx->chip_class <= VI) {
4929 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
4930 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
4931 }
4932
4933 if (!has_clear_state) {
4934 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
4935 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
4936 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
4937 }
4938
4939 si_pm4_set_reg(pm4, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
4940 if (!has_clear_state)
4941 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
4942 if (sctx->chip_class < CIK)
4943 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
4944 S_008A14_CLIP_VTX_REORDER_ENA(1));
4945
4946 /* CLEAR_STATE doesn't clear these correctly on certain generations.
4947 * I don't know why. Deduced by trial and error.
4948 */
4949 if (sctx->chip_class <= CIK) {
4950 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
4951 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
4952 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
4953 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
4954 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
4955 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
4956 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
4957 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
4958 }
4959
4960 if (!has_clear_state) {
4961 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
4962 S_028230_ER_TRI(0xA) |
4963 S_028230_ER_POINT(0xA) |
4964 S_028230_ER_RECT(0xA) |
4965 /* Required by DX10_DIAMOND_TEST_ENA: */
4966 S_028230_ER_LINE_LR(0x1A) |
4967 S_028230_ER_LINE_RL(0x26) |
4968 S_028230_ER_LINE_TB(0xA) |
4969 S_028230_ER_LINE_BT(0xA));
4970 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
4971 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
4972 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
4973 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
4974 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 0);
4975 }
4976
4977 if (sctx->chip_class >= GFX9) {
4978 si_pm4_set_reg(pm4, R_030920_VGT_MAX_VTX_INDX, ~0);
4979 si_pm4_set_reg(pm4, R_030924_VGT_MIN_VTX_INDX, 0);
4980 si_pm4_set_reg(pm4, R_030928_VGT_INDX_OFFSET, 0);
4981 } else {
4982 /* These registers, when written, also overwrite the CLEAR_STATE
4983 * context, so we can't rely on CLEAR_STATE setting them.
4984 * It would be an issue if there was another UMD changing them.
4985 */
4986 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
4987 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
4988 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
4989 }
4990
4991 if (sctx->chip_class >= CIK) {
4992 if (sctx->chip_class >= GFX9) {
4993 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
4994 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
4995 } else {
4996 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS,
4997 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
4998 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
4999 S_00B41C_WAVE_LIMIT(0x3F));
5000 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES,
5001 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
5002
5003 /* If this is 0, Bonaire can hang even if GS isn't being used.
5004 * Other chips are unaffected. These are suboptimal values,
5005 * but we don't use on-chip GS.
5006 */
5007 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
5008 S_028A44_ES_VERTS_PER_SUBGRP(64) |
5009 S_028A44_GS_PRIMS_PER_SUBGRP(4));
5010 }
5011 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
5012 S_00B21C_CU_EN(0xffff) | S_00B21C_WAVE_LIMIT(0x3F));
5013
5014 /* Compute LATE_ALLOC_VS.LIMIT. */
5015 unsigned num_cu_per_sh = sscreen->info.num_good_cu_per_sh;
5016 unsigned late_alloc_limit; /* The limit is per SH. */
5017
5018 if (sctx->family == CHIP_KABINI) {
5019 late_alloc_limit = 0; /* Potential hang on Kabini. */
5020 } else if (num_cu_per_sh <= 4) {
5021 /* Too few available compute units per SH. Disallowing
5022 * VS to run on one CU could hurt us more than late VS
5023 * allocation would help.
5024 *
5025 * 2 is the highest safe number that allows us to keep
5026 * all CUs enabled.
5027 */
5028 late_alloc_limit = 2;
5029 } else {
5030 /* This is a good initial value, allowing 1 late_alloc
5031 * wave per SIMD on num_cu - 2.
5032 */
5033 late_alloc_limit = (num_cu_per_sh - 2) * 4;
5034
5035 /* The limit is 0-based, so 0 means 1. */
5036 assert(late_alloc_limit > 0 && late_alloc_limit <= 64);
5037 late_alloc_limit -= 1;
5038 }
5039
5040 /* VS can't execute on one CU if the limit is > 2. */
5041 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
5042 S_00B118_CU_EN(late_alloc_limit > 2 ? 0xfffe : 0xffff) |
5043 S_00B118_WAVE_LIMIT(0x3F));
5044 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS,
5045 S_00B11C_LIMIT(late_alloc_limit));
5046 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
5047 S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
5048 }
5049
5050 if (sctx->chip_class >= VI) {
5051 unsigned vgt_tess_distribution;
5052
5053 vgt_tess_distribution =
5054 S_028B50_ACCUM_ISOLINE(32) |
5055 S_028B50_ACCUM_TRI(11) |
5056 S_028B50_ACCUM_QUAD(11) |
5057 S_028B50_DONUT_SPLIT(16);
5058
5059 /* Testing with Unigine Heaven extreme tesselation yielded best results
5060 * with TRAP_SPLIT = 3.
5061 */
5062 if (sctx->family == CHIP_FIJI ||
5063 sctx->family >= CHIP_POLARIS10)
5064 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
5065
5066 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution);
5067 } else if (!has_clear_state) {
5068 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
5069 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
5070 }
5071
5072 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
5073 if (sctx->chip_class >= CIK) {
5074 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI,
5075 S_028084_ADDRESS(border_color_va >> 40));
5076 }
5077 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
5078 RADEON_PRIO_BORDER_COLORS);
5079
5080 if (sctx->chip_class >= GFX9) {
5081 unsigned num_se = sscreen->info.max_se;
5082 unsigned pc_lines = 0;
5083
5084 switch (sctx->family) {
5085 case CHIP_VEGA10:
5086 case CHIP_VEGA12:
5087 case CHIP_VEGA20:
5088 pc_lines = 4096;
5089 break;
5090 case CHIP_RAVEN:
5091 pc_lines = 1024;
5092 break;
5093 default:
5094 assert(0);
5095 }
5096
5097 si_pm4_set_reg(pm4, R_028C48_PA_SC_BINNER_CNTL_1,
5098 S_028C48_MAX_ALLOC_COUNT(MIN2(128, pc_lines / (4 * num_se))) |
5099 S_028C48_MAX_PRIM_PER_BATCH(1023));
5100 si_pm4_set_reg(pm4, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
5101 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
5102 si_pm4_set_reg(pm4, R_030968_VGT_INSTANCE_BASE_ID, 0);
5103 }
5104
5105 si_pm4_upload_indirect_buffer(sctx, pm4);
5106 sctx->init_config = pm4;
5107 }