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radeonsi: Bump SI_PM4_MAX_DW.
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "util/u_memory.h"
28 #include "util/u_framebuffer.h"
29 #include "util/u_blitter.h"
30 #include "util/u_helpers.h"
31 #include "util/u_math.h"
32 #include "util/u_pack_color.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "radeonsi_pipe.h"
35 #include "radeonsi_shader.h"
36 #include "si_state.h"
37 #include "sid.h"
38
39 /*
40 * inferred framebuffer and blender state
41 */
42 static void si_update_fb_blend_state(struct r600_context *rctx)
43 {
44 struct si_pm4_state *pm4;
45 struct si_state_blend *blend = rctx->queued.named.blend;
46 uint32_t mask;
47
48 if (blend == NULL)
49 return;
50
51 pm4 = CALLOC_STRUCT(si_pm4_state);
52 if (pm4 == NULL)
53 return;
54
55 mask = (1ULL << ((unsigned)rctx->framebuffer.nr_cbufs * 4)) - 1;
56 mask &= blend->cb_target_mask;
57 si_pm4_set_reg(pm4, R_028238_CB_TARGET_MASK, mask);
58
59 si_pm4_set_state(rctx, fb_blend, pm4);
60 }
61
62 /*
63 * Blender functions
64 */
65
66 static uint32_t si_translate_blend_function(int blend_func)
67 {
68 switch (blend_func) {
69 case PIPE_BLEND_ADD:
70 return V_028780_COMB_DST_PLUS_SRC;
71 case PIPE_BLEND_SUBTRACT:
72 return V_028780_COMB_SRC_MINUS_DST;
73 case PIPE_BLEND_REVERSE_SUBTRACT:
74 return V_028780_COMB_DST_MINUS_SRC;
75 case PIPE_BLEND_MIN:
76 return V_028780_COMB_MIN_DST_SRC;
77 case PIPE_BLEND_MAX:
78 return V_028780_COMB_MAX_DST_SRC;
79 default:
80 R600_ERR("Unknown blend function %d\n", blend_func);
81 assert(0);
82 break;
83 }
84 return 0;
85 }
86
87 static uint32_t si_translate_blend_factor(int blend_fact)
88 {
89 switch (blend_fact) {
90 case PIPE_BLENDFACTOR_ONE:
91 return V_028780_BLEND_ONE;
92 case PIPE_BLENDFACTOR_SRC_COLOR:
93 return V_028780_BLEND_SRC_COLOR;
94 case PIPE_BLENDFACTOR_SRC_ALPHA:
95 return V_028780_BLEND_SRC_ALPHA;
96 case PIPE_BLENDFACTOR_DST_ALPHA:
97 return V_028780_BLEND_DST_ALPHA;
98 case PIPE_BLENDFACTOR_DST_COLOR:
99 return V_028780_BLEND_DST_COLOR;
100 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
101 return V_028780_BLEND_SRC_ALPHA_SATURATE;
102 case PIPE_BLENDFACTOR_CONST_COLOR:
103 return V_028780_BLEND_CONSTANT_COLOR;
104 case PIPE_BLENDFACTOR_CONST_ALPHA:
105 return V_028780_BLEND_CONSTANT_ALPHA;
106 case PIPE_BLENDFACTOR_ZERO:
107 return V_028780_BLEND_ZERO;
108 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
109 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
110 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
111 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
112 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
113 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
114 case PIPE_BLENDFACTOR_INV_DST_COLOR:
115 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
116 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
117 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
118 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
119 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
120 case PIPE_BLENDFACTOR_SRC1_COLOR:
121 return V_028780_BLEND_SRC1_COLOR;
122 case PIPE_BLENDFACTOR_SRC1_ALPHA:
123 return V_028780_BLEND_SRC1_ALPHA;
124 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
125 return V_028780_BLEND_INV_SRC1_COLOR;
126 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
127 return V_028780_BLEND_INV_SRC1_ALPHA;
128 default:
129 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
130 assert(0);
131 break;
132 }
133 return 0;
134 }
135
136 static void *si_create_blend_state(struct pipe_context *ctx,
137 const struct pipe_blend_state *state)
138 {
139 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
140 struct si_pm4_state *pm4 = &blend->pm4;
141
142 uint32_t color_control;
143
144 if (blend == NULL)
145 return NULL;
146
147 color_control = S_028808_MODE(V_028808_CB_NORMAL);
148 if (state->logicop_enable) {
149 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
150 } else {
151 color_control |= S_028808_ROP3(0xcc);
152 }
153 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
154
155 si_pm4_set_reg(pm4, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, ~0);
156 si_pm4_set_reg(pm4, R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, ~0);
157
158 blend->cb_target_mask = 0;
159 for (int i = 0; i < 8; i++) {
160 /* state->rt entries > 0 only written if independent blending */
161 const int j = state->independent_blend_enable ? i : 0;
162
163 unsigned eqRGB = state->rt[j].rgb_func;
164 unsigned srcRGB = state->rt[j].rgb_src_factor;
165 unsigned dstRGB = state->rt[j].rgb_dst_factor;
166 unsigned eqA = state->rt[j].alpha_func;
167 unsigned srcA = state->rt[j].alpha_src_factor;
168 unsigned dstA = state->rt[j].alpha_dst_factor;
169
170 unsigned blend_cntl = 0;
171
172 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
173 blend->cb_target_mask |= state->rt[j].colormask << (4 * i);
174
175 if (!state->rt[j].blend_enable) {
176 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
177 continue;
178 }
179
180 blend_cntl |= S_028780_ENABLE(1);
181 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
182 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
183 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
184
185 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
186 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
187 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
188 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
189 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
190 }
191 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
192 }
193
194 return blend;
195 }
196
197 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
198 {
199 struct r600_context *rctx = (struct r600_context *)ctx;
200 si_pm4_bind_state(rctx, blend, (struct si_state_blend *)state);
201 si_update_fb_blend_state(rctx);
202 }
203
204 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
205 {
206 struct r600_context *rctx = (struct r600_context *)ctx;
207 si_pm4_delete_state(rctx, blend, (struct si_state_blend *)state);
208 }
209
210 static void si_set_blend_color(struct pipe_context *ctx,
211 const struct pipe_blend_color *state)
212 {
213 struct r600_context *rctx = (struct r600_context *)ctx;
214 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
215
216 if (pm4 == NULL)
217 return;
218
219 si_pm4_set_reg(pm4, R_028414_CB_BLEND_RED, fui(state->color[0]));
220 si_pm4_set_reg(pm4, R_028418_CB_BLEND_GREEN, fui(state->color[1]));
221 si_pm4_set_reg(pm4, R_02841C_CB_BLEND_BLUE, fui(state->color[2]));
222 si_pm4_set_reg(pm4, R_028420_CB_BLEND_ALPHA, fui(state->color[3]));
223
224 si_pm4_set_state(rctx, blend_color, pm4);
225 }
226
227 /*
228 * Clipping, scissors and viewport
229 */
230
231 static void si_set_clip_state(struct pipe_context *ctx,
232 const struct pipe_clip_state *state)
233 {
234 struct r600_context *rctx = (struct r600_context *)ctx;
235 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
236
237 if (pm4 == NULL)
238 return;
239
240 for (int i = 0; i < 6; i++) {
241 si_pm4_set_reg(pm4, R_0285BC_PA_CL_UCP_0_X + i * 16,
242 fui(state->ucp[i][0]));
243 si_pm4_set_reg(pm4, R_0285C0_PA_CL_UCP_0_Y + i * 16,
244 fui(state->ucp[i][1]));
245 si_pm4_set_reg(pm4, R_0285C4_PA_CL_UCP_0_Z + i * 16,
246 fui(state->ucp[i][2]));
247 si_pm4_set_reg(pm4, R_0285C8_PA_CL_UCP_0_W + i * 16,
248 fui(state->ucp[i][3]));
249 }
250
251 si_pm4_set_state(rctx, clip, pm4);
252 }
253
254 static void si_set_scissor_state(struct pipe_context *ctx,
255 const struct pipe_scissor_state *state)
256 {
257 struct r600_context *rctx = (struct r600_context *)ctx;
258 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
259 uint32_t tl, br;
260
261 if (pm4 == NULL)
262 return;
263
264 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny);
265 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
266 si_pm4_set_reg(pm4, R_028210_PA_SC_CLIPRECT_0_TL, tl);
267 si_pm4_set_reg(pm4, R_028214_PA_SC_CLIPRECT_0_BR, br);
268 si_pm4_set_reg(pm4, R_028218_PA_SC_CLIPRECT_1_TL, tl);
269 si_pm4_set_reg(pm4, R_02821C_PA_SC_CLIPRECT_1_BR, br);
270 si_pm4_set_reg(pm4, R_028220_PA_SC_CLIPRECT_2_TL, tl);
271 si_pm4_set_reg(pm4, R_028224_PA_SC_CLIPRECT_2_BR, br);
272 si_pm4_set_reg(pm4, R_028228_PA_SC_CLIPRECT_3_TL, tl);
273 si_pm4_set_reg(pm4, R_02822C_PA_SC_CLIPRECT_3_BR, br);
274
275 si_pm4_set_state(rctx, scissor, pm4);
276 }
277
278 static void si_set_viewport_state(struct pipe_context *ctx,
279 const struct pipe_viewport_state *state)
280 {
281 struct r600_context *rctx = (struct r600_context *)ctx;
282 struct si_state_viewport *viewport = CALLOC_STRUCT(si_state_viewport);
283 struct si_pm4_state *pm4 = &viewport->pm4;
284
285 if (viewport == NULL)
286 return;
287
288 viewport->viewport = *state;
289 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000);
290 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000);
291 si_pm4_set_reg(pm4, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
292 si_pm4_set_reg(pm4, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
293 si_pm4_set_reg(pm4, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
294 si_pm4_set_reg(pm4, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
295 si_pm4_set_reg(pm4, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
296 si_pm4_set_reg(pm4, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
297 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
298
299 si_pm4_set_state(rctx, viewport, viewport);
300 }
301
302 /*
303 * inferred state between framebuffer and rasterizer
304 */
305 static void si_update_fb_rs_state(struct r600_context *rctx)
306 {
307 struct si_state_rasterizer *rs = rctx->queued.named.rasterizer;
308 struct si_pm4_state *pm4;
309 unsigned offset_db_fmt_cntl = 0, depth;
310 float offset_units;
311
312 if (!rs || !rctx->framebuffer.zsbuf)
313 return;
314
315 offset_units = rctx->queued.named.rasterizer->offset_units;
316 switch (rctx->framebuffer.zsbuf->texture->format) {
317 case PIPE_FORMAT_Z24X8_UNORM:
318 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
319 depth = -24;
320 offset_units *= 2.0f;
321 break;
322 case PIPE_FORMAT_Z32_FLOAT:
323 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
324 depth = -23;
325 offset_units *= 1.0f;
326 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
327 break;
328 case PIPE_FORMAT_Z16_UNORM:
329 depth = -16;
330 offset_units *= 4.0f;
331 break;
332 default:
333 return;
334 }
335
336 pm4 = CALLOC_STRUCT(si_pm4_state);
337 /* FIXME some of those reg can be computed with cso */
338 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
339 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
340 fui(rctx->queued.named.rasterizer->offset_scale));
341 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units));
342 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
343 fui(rctx->queued.named.rasterizer->offset_scale));
344 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units));
345 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, offset_db_fmt_cntl);
346
347 si_pm4_set_state(rctx, fb_rs, pm4);
348 }
349
350 /*
351 * Rasterizer
352 */
353
354 static uint32_t si_translate_fill(uint32_t func)
355 {
356 switch(func) {
357 case PIPE_POLYGON_MODE_FILL:
358 return V_028814_X_DRAW_TRIANGLES;
359 case PIPE_POLYGON_MODE_LINE:
360 return V_028814_X_DRAW_LINES;
361 case PIPE_POLYGON_MODE_POINT:
362 return V_028814_X_DRAW_POINTS;
363 default:
364 assert(0);
365 return V_028814_X_DRAW_POINTS;
366 }
367 }
368
369 static void *si_create_rs_state(struct pipe_context *ctx,
370 const struct pipe_rasterizer_state *state)
371 {
372 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
373 struct si_pm4_state *pm4 = &rs->pm4;
374 unsigned tmp;
375 unsigned prov_vtx = 1, polygon_dual_mode;
376 unsigned clip_rule;
377 float psize_min, psize_max;
378
379 if (rs == NULL) {
380 return NULL;
381 }
382
383 rs->two_side = state->light_twoside;
384
385 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
386 state->fill_back != PIPE_POLYGON_MODE_FILL);
387
388 if (state->flatshade_first)
389 prov_vtx = 0;
390
391 rs->flatshade = state->flatshade;
392 rs->sprite_coord_enable = state->sprite_coord_enable;
393 rs->pa_sc_line_stipple = state->line_stipple_enable ?
394 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
395 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
396 rs->pa_su_sc_mode_cntl =
397 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
398 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
399 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
400 S_028814_FACE(!state->front_ccw) |
401 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
402 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
403 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
404 S_028814_POLY_MODE(polygon_dual_mode) |
405 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
406 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back));
407 rs->pa_cl_clip_cntl =
408 S_028810_PS_UCP_MODE(3) |
409 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
410 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
411 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
412 rs->pa_cl_vs_out_cntl =
413 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
414 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex);
415
416 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
417
418 /* offset */
419 rs->offset_units = state->offset_units;
420 rs->offset_scale = state->offset_scale * 12.0f;
421
422 /* XXX: Flat shading hangs the GPU */
423 tmp = S_0286D4_FLAT_SHADE_ENA(0);
424 if (state->sprite_coord_enable) {
425 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
426 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
427 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
428 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
429 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1);
430 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
431 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
432 }
433 }
434 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
435
436 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0x00000000);
437 /* point size 12.4 fixed point */
438 tmp = (unsigned)(state->point_size * 8.0);
439 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
440
441 if (state->point_size_per_vertex) {
442 psize_min = util_get_min_point_size(state);
443 psize_max = 8192;
444 } else {
445 /* Force the point size to be as if the vertex output was disabled. */
446 psize_min = state->point_size;
447 psize_max = state->point_size;
448 }
449 /* Divide by two, because 0.5 = 1 pixel. */
450 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
451 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
452 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
453
454 tmp = (unsigned)state->line_width * 8;
455 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
456 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
457 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable));
458
459 si_pm4_set_reg(pm4, R_028BDC_PA_SC_LINE_CNTL, 0x00000400);
460 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
461 S_028BE4_PIX_CENTER(state->gl_rasterization_rules));
462 si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000);
463 si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000);
464 si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000);
465 si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000);
466
467 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
468 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule);
469
470 return rs;
471 }
472
473 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
474 {
475 struct r600_context *rctx = (struct r600_context *)ctx;
476 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
477
478 if (state == NULL)
479 return;
480
481 // TODO
482 rctx->sprite_coord_enable = rs->sprite_coord_enable;
483 rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
484 rctx->pa_su_sc_mode_cntl = rs->pa_su_sc_mode_cntl;
485 rctx->pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
486 rctx->pa_cl_vs_out_cntl = rs->pa_cl_vs_out_cntl;
487
488 si_pm4_bind_state(rctx, rasterizer, rs);
489 si_update_fb_rs_state(rctx);
490 }
491
492 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
493 {
494 struct r600_context *rctx = (struct r600_context *)ctx;
495 si_pm4_delete_state(rctx, rasterizer, (struct si_state_rasterizer *)state);
496 }
497
498 /*
499 * infeered state between dsa and stencil ref
500 */
501 static void si_update_dsa_stencil_ref(struct r600_context *rctx)
502 {
503 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
504 struct pipe_stencil_ref *ref = &rctx->stencil_ref;
505 struct si_state_dsa *dsa = rctx->queued.named.dsa;
506
507 if (pm4 == NULL)
508 return;
509
510 si_pm4_set_reg(pm4, R_028430_DB_STENCILREFMASK,
511 S_028430_STENCILTESTVAL(ref->ref_value[0]) |
512 S_028430_STENCILMASK(dsa->valuemask[0]) |
513 S_028430_STENCILWRITEMASK(dsa->writemask[0]));
514 si_pm4_set_reg(pm4, R_028434_DB_STENCILREFMASK_BF,
515 S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
516 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
517 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]));
518
519 si_pm4_set_state(rctx, dsa_stencil_ref, pm4);
520 }
521
522 static void si_set_pipe_stencil_ref(struct pipe_context *ctx,
523 const struct pipe_stencil_ref *state)
524 {
525 struct r600_context *rctx = (struct r600_context *)ctx;
526 rctx->stencil_ref = *state;
527 si_update_dsa_stencil_ref(rctx);
528 }
529
530
531 /*
532 * DSA
533 */
534
535 static uint32_t si_translate_stencil_op(int s_op)
536 {
537 switch (s_op) {
538 case PIPE_STENCIL_OP_KEEP:
539 return V_02842C_STENCIL_KEEP;
540 case PIPE_STENCIL_OP_ZERO:
541 return V_02842C_STENCIL_ZERO;
542 case PIPE_STENCIL_OP_REPLACE:
543 return V_02842C_STENCIL_REPLACE_TEST;
544 case PIPE_STENCIL_OP_INCR:
545 return V_02842C_STENCIL_ADD_CLAMP;
546 case PIPE_STENCIL_OP_DECR:
547 return V_02842C_STENCIL_SUB_CLAMP;
548 case PIPE_STENCIL_OP_INCR_WRAP:
549 return V_02842C_STENCIL_ADD_WRAP;
550 case PIPE_STENCIL_OP_DECR_WRAP:
551 return V_02842C_STENCIL_SUB_WRAP;
552 case PIPE_STENCIL_OP_INVERT:
553 return V_02842C_STENCIL_INVERT;
554 default:
555 R600_ERR("Unknown stencil op %d", s_op);
556 assert(0);
557 break;
558 }
559 return 0;
560 }
561
562 static void *si_create_dsa_state(struct pipe_context *ctx,
563 const struct pipe_depth_stencil_alpha_state *state)
564 {
565 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
566 struct si_pm4_state *pm4 = &dsa->pm4;
567 unsigned db_depth_control;
568 unsigned db_render_override, db_render_control;
569 uint32_t db_stencil_control = 0;
570
571 if (dsa == NULL) {
572 return NULL;
573 }
574
575 dsa->valuemask[0] = state->stencil[0].valuemask;
576 dsa->valuemask[1] = state->stencil[1].valuemask;
577 dsa->writemask[0] = state->stencil[0].writemask;
578 dsa->writemask[1] = state->stencil[1].writemask;
579
580 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
581 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
582 S_028800_ZFUNC(state->depth.func);
583
584 /* stencil */
585 if (state->stencil[0].enabled) {
586 db_depth_control |= S_028800_STENCIL_ENABLE(1);
587 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
588 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
589 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
590 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
591
592 if (state->stencil[1].enabled) {
593 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
594 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
595 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
596 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
597 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
598 }
599 }
600
601 /* alpha */
602 if (state->alpha.enabled) {
603 dsa->alpha_func = state->alpha.func;
604 dsa->alpha_ref = state->alpha.ref_value;
605 } else {
606 dsa->alpha_func = PIPE_FUNC_ALWAYS;
607 }
608
609 /* misc */
610 db_render_control = 0;
611 db_render_override = S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
612 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
613 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
614 /* TODO db_render_override depends on query */
615 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, 0x00000000);
616 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, 0x00000000);
617 si_pm4_set_reg(pm4, R_028028_DB_STENCIL_CLEAR, 0x00000000);
618 si_pm4_set_reg(pm4, R_02802C_DB_DEPTH_CLEAR, 0x3F800000);
619 //si_pm4_set_reg(pm4, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control);
620 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
621 si_pm4_set_reg(pm4, R_028000_DB_RENDER_CONTROL, db_render_control);
622 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
623 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
624 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
625 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
626 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
627 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00);
628 dsa->db_render_override = db_render_override;
629
630 return dsa;
631 }
632
633 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
634 {
635 struct r600_context *rctx = (struct r600_context *)ctx;
636 struct si_state_dsa *dsa = state;
637
638 if (state == NULL)
639 return;
640
641 si_pm4_bind_state(rctx, dsa, dsa);
642 si_update_dsa_stencil_ref(rctx);
643 }
644
645 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
646 {
647 struct r600_context *rctx = (struct r600_context *)ctx;
648 si_pm4_delete_state(rctx, dsa, (struct si_state_dsa *)state);
649 }
650
651 static void *si_create_db_flush_dsa(struct r600_context *rctx)
652 {
653 struct pipe_depth_stencil_alpha_state dsa;
654 struct si_state_dsa *state;
655
656 memset(&dsa, 0, sizeof(dsa));
657
658 state = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
659 si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL,
660 S_028000_DEPTH_COPY(1) |
661 S_028000_STENCIL_COPY(1) |
662 S_028000_COPY_CENTROID(1));
663 return state;
664 }
665
666 /*
667 * format translation
668 */
669 static uint32_t si_translate_colorformat(enum pipe_format format)
670 {
671 switch (format) {
672 /* 8-bit buffers. */
673 case PIPE_FORMAT_A8_UNORM:
674 case PIPE_FORMAT_A8_SNORM:
675 case PIPE_FORMAT_A8_UINT:
676 case PIPE_FORMAT_A8_SINT:
677 case PIPE_FORMAT_I8_UNORM:
678 case PIPE_FORMAT_I8_SNORM:
679 case PIPE_FORMAT_I8_UINT:
680 case PIPE_FORMAT_I8_SINT:
681 case PIPE_FORMAT_L8_UNORM:
682 case PIPE_FORMAT_L8_SNORM:
683 case PIPE_FORMAT_L8_UINT:
684 case PIPE_FORMAT_L8_SINT:
685 case PIPE_FORMAT_L8_SRGB:
686 case PIPE_FORMAT_R8_UNORM:
687 case PIPE_FORMAT_R8_SNORM:
688 case PIPE_FORMAT_R8_UINT:
689 case PIPE_FORMAT_R8_SINT:
690 return V_028C70_COLOR_8;
691
692 /* 16-bit buffers. */
693 case PIPE_FORMAT_B5G6R5_UNORM:
694 return V_028C70_COLOR_5_6_5;
695
696 case PIPE_FORMAT_B5G5R5A1_UNORM:
697 case PIPE_FORMAT_B5G5R5X1_UNORM:
698 return V_028C70_COLOR_1_5_5_5;
699
700 case PIPE_FORMAT_B4G4R4A4_UNORM:
701 case PIPE_FORMAT_B4G4R4X4_UNORM:
702 return V_028C70_COLOR_4_4_4_4;
703
704 case PIPE_FORMAT_L8A8_UNORM:
705 case PIPE_FORMAT_L8A8_SNORM:
706 case PIPE_FORMAT_L8A8_UINT:
707 case PIPE_FORMAT_L8A8_SINT:
708 case PIPE_FORMAT_L8A8_SRGB:
709 case PIPE_FORMAT_R8G8_SNORM:
710 case PIPE_FORMAT_R8G8_UNORM:
711 case PIPE_FORMAT_R8G8_UINT:
712 case PIPE_FORMAT_R8G8_SINT:
713 return V_028C70_COLOR_8_8;
714
715 case PIPE_FORMAT_Z16_UNORM:
716 case PIPE_FORMAT_R16_UNORM:
717 case PIPE_FORMAT_R16_SNORM:
718 case PIPE_FORMAT_R16_UINT:
719 case PIPE_FORMAT_R16_SINT:
720 case PIPE_FORMAT_R16_FLOAT:
721 case PIPE_FORMAT_L16_UNORM:
722 case PIPE_FORMAT_L16_SNORM:
723 case PIPE_FORMAT_L16_FLOAT:
724 case PIPE_FORMAT_I16_UNORM:
725 case PIPE_FORMAT_I16_SNORM:
726 case PIPE_FORMAT_I16_FLOAT:
727 case PIPE_FORMAT_A16_UNORM:
728 case PIPE_FORMAT_A16_SNORM:
729 case PIPE_FORMAT_A16_FLOAT:
730 return V_028C70_COLOR_16;
731
732 /* 32-bit buffers. */
733 case PIPE_FORMAT_A8B8G8R8_SRGB:
734 case PIPE_FORMAT_A8B8G8R8_UNORM:
735 case PIPE_FORMAT_A8R8G8B8_UNORM:
736 case PIPE_FORMAT_B8G8R8A8_SRGB:
737 case PIPE_FORMAT_B8G8R8A8_UNORM:
738 case PIPE_FORMAT_B8G8R8X8_UNORM:
739 case PIPE_FORMAT_R8G8B8A8_SNORM:
740 case PIPE_FORMAT_R8G8B8A8_UNORM:
741 case PIPE_FORMAT_R8G8B8X8_UNORM:
742 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
743 case PIPE_FORMAT_X8B8G8R8_UNORM:
744 case PIPE_FORMAT_X8R8G8B8_UNORM:
745 case PIPE_FORMAT_R8G8B8_UNORM:
746 case PIPE_FORMAT_R8G8B8A8_SSCALED:
747 case PIPE_FORMAT_R8G8B8A8_USCALED:
748 case PIPE_FORMAT_R8G8B8A8_SINT:
749 case PIPE_FORMAT_R8G8B8A8_UINT:
750 return V_028C70_COLOR_8_8_8_8;
751
752 case PIPE_FORMAT_R10G10B10A2_UNORM:
753 case PIPE_FORMAT_R10G10B10X2_SNORM:
754 case PIPE_FORMAT_B10G10R10A2_UNORM:
755 case PIPE_FORMAT_B10G10R10A2_UINT:
756 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
757 return V_028C70_COLOR_2_10_10_10;
758
759 case PIPE_FORMAT_Z24X8_UNORM:
760 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
761 return V_028C70_COLOR_8_24;
762
763 case PIPE_FORMAT_X8Z24_UNORM:
764 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
765 return V_028C70_COLOR_24_8;
766
767 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
768 return V_028C70_COLOR_X24_8_32_FLOAT;
769
770 case PIPE_FORMAT_I32_FLOAT:
771 case PIPE_FORMAT_L32_FLOAT:
772 case PIPE_FORMAT_R32_FLOAT:
773 case PIPE_FORMAT_A32_FLOAT:
774 case PIPE_FORMAT_Z32_FLOAT:
775 return V_028C70_COLOR_32;
776
777 case PIPE_FORMAT_L16A16_UNORM:
778 case PIPE_FORMAT_L16A16_SNORM:
779 case PIPE_FORMAT_L16A16_FLOAT:
780 case PIPE_FORMAT_R16G16_SSCALED:
781 case PIPE_FORMAT_R16G16_UNORM:
782 case PIPE_FORMAT_R16G16_SNORM:
783 case PIPE_FORMAT_R16G16_UINT:
784 case PIPE_FORMAT_R16G16_SINT:
785 case PIPE_FORMAT_R16G16_FLOAT:
786 return V_028C70_COLOR_16_16;
787
788 case PIPE_FORMAT_R11G11B10_FLOAT:
789 return V_028C70_COLOR_10_11_11;
790
791 /* 64-bit buffers. */
792 case PIPE_FORMAT_R16G16B16_USCALED:
793 case PIPE_FORMAT_R16G16B16_SSCALED:
794 case PIPE_FORMAT_R16G16B16A16_UINT:
795 case PIPE_FORMAT_R16G16B16A16_SINT:
796 case PIPE_FORMAT_R16G16B16A16_USCALED:
797 case PIPE_FORMAT_R16G16B16A16_SSCALED:
798 case PIPE_FORMAT_R16G16B16A16_UNORM:
799 case PIPE_FORMAT_R16G16B16A16_SNORM:
800 case PIPE_FORMAT_R16G16B16_FLOAT:
801 case PIPE_FORMAT_R16G16B16A16_FLOAT:
802 return V_028C70_COLOR_16_16_16_16;
803
804 case PIPE_FORMAT_L32A32_FLOAT:
805 case PIPE_FORMAT_R32G32_FLOAT:
806 case PIPE_FORMAT_R32G32_USCALED:
807 case PIPE_FORMAT_R32G32_SSCALED:
808 case PIPE_FORMAT_R32G32_SINT:
809 case PIPE_FORMAT_R32G32_UINT:
810 return V_028C70_COLOR_32_32;
811
812 /* 128-bit buffers. */
813 case PIPE_FORMAT_R32G32B32A32_SNORM:
814 case PIPE_FORMAT_R32G32B32A32_UNORM:
815 case PIPE_FORMAT_R32G32B32A32_SSCALED:
816 case PIPE_FORMAT_R32G32B32A32_USCALED:
817 case PIPE_FORMAT_R32G32B32A32_SINT:
818 case PIPE_FORMAT_R32G32B32A32_UINT:
819 case PIPE_FORMAT_R32G32B32A32_FLOAT:
820 return V_028C70_COLOR_32_32_32_32;
821
822 /* YUV buffers. */
823 case PIPE_FORMAT_UYVY:
824 case PIPE_FORMAT_YUYV:
825 /* 96-bit buffers. */
826 case PIPE_FORMAT_R32G32B32_FLOAT:
827 /* 8-bit buffers. */
828 case PIPE_FORMAT_L4A4_UNORM:
829 case PIPE_FORMAT_R4A4_UNORM:
830 case PIPE_FORMAT_A4R4_UNORM:
831 default:
832 return ~0U; /* Unsupported. */
833 }
834 }
835
836 static uint32_t si_translate_colorswap(enum pipe_format format)
837 {
838 switch (format) {
839 /* 8-bit buffers. */
840 case PIPE_FORMAT_L4A4_UNORM:
841 case PIPE_FORMAT_A4R4_UNORM:
842 return V_028C70_SWAP_ALT;
843
844 case PIPE_FORMAT_A8_UNORM:
845 case PIPE_FORMAT_A8_SNORM:
846 case PIPE_FORMAT_A8_UINT:
847 case PIPE_FORMAT_A8_SINT:
848 case PIPE_FORMAT_R4A4_UNORM:
849 return V_028C70_SWAP_ALT_REV;
850 case PIPE_FORMAT_I8_UNORM:
851 case PIPE_FORMAT_I8_SNORM:
852 case PIPE_FORMAT_L8_UNORM:
853 case PIPE_FORMAT_L8_SNORM:
854 case PIPE_FORMAT_I8_UINT:
855 case PIPE_FORMAT_I8_SINT:
856 case PIPE_FORMAT_L8_UINT:
857 case PIPE_FORMAT_L8_SINT:
858 case PIPE_FORMAT_L8_SRGB:
859 case PIPE_FORMAT_R8_UNORM:
860 case PIPE_FORMAT_R8_SNORM:
861 case PIPE_FORMAT_R8_UINT:
862 case PIPE_FORMAT_R8_SINT:
863 return V_028C70_SWAP_STD;
864
865 /* 16-bit buffers. */
866 case PIPE_FORMAT_B5G6R5_UNORM:
867 return V_028C70_SWAP_STD_REV;
868
869 case PIPE_FORMAT_B5G5R5A1_UNORM:
870 case PIPE_FORMAT_B5G5R5X1_UNORM:
871 return V_028C70_SWAP_ALT;
872
873 case PIPE_FORMAT_B4G4R4A4_UNORM:
874 case PIPE_FORMAT_B4G4R4X4_UNORM:
875 return V_028C70_SWAP_ALT;
876
877 case PIPE_FORMAT_Z16_UNORM:
878 return V_028C70_SWAP_STD;
879
880 case PIPE_FORMAT_L8A8_UNORM:
881 case PIPE_FORMAT_L8A8_SNORM:
882 case PIPE_FORMAT_L8A8_UINT:
883 case PIPE_FORMAT_L8A8_SINT:
884 case PIPE_FORMAT_L8A8_SRGB:
885 return V_028C70_SWAP_ALT;
886 case PIPE_FORMAT_R8G8_SNORM:
887 case PIPE_FORMAT_R8G8_UNORM:
888 case PIPE_FORMAT_R8G8_UINT:
889 case PIPE_FORMAT_R8G8_SINT:
890 return V_028C70_SWAP_STD;
891
892 case PIPE_FORMAT_I16_UNORM:
893 case PIPE_FORMAT_I16_SNORM:
894 case PIPE_FORMAT_I16_FLOAT:
895 case PIPE_FORMAT_L16_UNORM:
896 case PIPE_FORMAT_L16_SNORM:
897 case PIPE_FORMAT_L16_FLOAT:
898 case PIPE_FORMAT_R16_UNORM:
899 case PIPE_FORMAT_R16_SNORM:
900 case PIPE_FORMAT_R16_UINT:
901 case PIPE_FORMAT_R16_SINT:
902 case PIPE_FORMAT_R16_FLOAT:
903 return V_028C70_SWAP_STD;
904
905 case PIPE_FORMAT_A16_UNORM:
906 case PIPE_FORMAT_A16_SNORM:
907 case PIPE_FORMAT_A16_FLOAT:
908 return V_028C70_SWAP_ALT_REV;
909
910 /* 32-bit buffers. */
911 case PIPE_FORMAT_A8B8G8R8_SRGB:
912 return V_028C70_SWAP_STD_REV;
913 case PIPE_FORMAT_B8G8R8A8_SRGB:
914 return V_028C70_SWAP_ALT;
915
916 case PIPE_FORMAT_B8G8R8A8_UNORM:
917 case PIPE_FORMAT_B8G8R8X8_UNORM:
918 return V_028C70_SWAP_ALT;
919
920 case PIPE_FORMAT_A8R8G8B8_UNORM:
921 case PIPE_FORMAT_X8R8G8B8_UNORM:
922 return V_028C70_SWAP_ALT_REV;
923 case PIPE_FORMAT_R8G8B8A8_SNORM:
924 case PIPE_FORMAT_R8G8B8A8_UNORM:
925 case PIPE_FORMAT_R8G8B8A8_SSCALED:
926 case PIPE_FORMAT_R8G8B8A8_USCALED:
927 case PIPE_FORMAT_R8G8B8A8_SINT:
928 case PIPE_FORMAT_R8G8B8A8_UINT:
929 case PIPE_FORMAT_R8G8B8X8_UNORM:
930 return V_028C70_SWAP_STD;
931
932 case PIPE_FORMAT_A8B8G8R8_UNORM:
933 case PIPE_FORMAT_X8B8G8R8_UNORM:
934 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
935 return V_028C70_SWAP_STD_REV;
936
937 case PIPE_FORMAT_Z24X8_UNORM:
938 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
939 return V_028C70_SWAP_STD;
940
941 case PIPE_FORMAT_X8Z24_UNORM:
942 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
943 return V_028C70_SWAP_STD;
944
945 case PIPE_FORMAT_R10G10B10A2_UNORM:
946 case PIPE_FORMAT_R10G10B10X2_SNORM:
947 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
948 return V_028C70_SWAP_STD;
949
950 case PIPE_FORMAT_B10G10R10A2_UNORM:
951 case PIPE_FORMAT_B10G10R10A2_UINT:
952 return V_028C70_SWAP_ALT;
953
954 case PIPE_FORMAT_R11G11B10_FLOAT:
955 case PIPE_FORMAT_I32_FLOAT:
956 case PIPE_FORMAT_L32_FLOAT:
957 case PIPE_FORMAT_R32_FLOAT:
958 case PIPE_FORMAT_R32_UINT:
959 case PIPE_FORMAT_R32_SINT:
960 case PIPE_FORMAT_Z32_FLOAT:
961 case PIPE_FORMAT_R16G16_FLOAT:
962 case PIPE_FORMAT_R16G16_UNORM:
963 case PIPE_FORMAT_R16G16_SNORM:
964 case PIPE_FORMAT_R16G16_UINT:
965 case PIPE_FORMAT_R16G16_SINT:
966 return V_028C70_SWAP_STD;
967
968 case PIPE_FORMAT_L16A16_UNORM:
969 case PIPE_FORMAT_L16A16_SNORM:
970 case PIPE_FORMAT_L16A16_FLOAT:
971 return V_028C70_SWAP_ALT;
972
973 case PIPE_FORMAT_A32_FLOAT:
974 return V_028C70_SWAP_ALT_REV;
975
976 /* 64-bit buffers. */
977 case PIPE_FORMAT_R32G32_FLOAT:
978 case PIPE_FORMAT_R32G32_UINT:
979 case PIPE_FORMAT_R32G32_SINT:
980 case PIPE_FORMAT_R16G16B16A16_UNORM:
981 case PIPE_FORMAT_R16G16B16A16_SNORM:
982 case PIPE_FORMAT_R16G16B16A16_USCALED:
983 case PIPE_FORMAT_R16G16B16A16_SSCALED:
984 case PIPE_FORMAT_R16G16B16A16_UINT:
985 case PIPE_FORMAT_R16G16B16A16_SINT:
986 case PIPE_FORMAT_R16G16B16A16_FLOAT:
987 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
988 return V_028C70_SWAP_STD;
989
990 case PIPE_FORMAT_L32A32_FLOAT:
991 return V_028C70_SWAP_ALT;
992
993 /* 128-bit buffers. */
994 case PIPE_FORMAT_R32G32B32A32_FLOAT:
995 case PIPE_FORMAT_R32G32B32A32_SNORM:
996 case PIPE_FORMAT_R32G32B32A32_UNORM:
997 case PIPE_FORMAT_R32G32B32A32_SSCALED:
998 case PIPE_FORMAT_R32G32B32A32_USCALED:
999 case PIPE_FORMAT_R32G32B32A32_SINT:
1000 case PIPE_FORMAT_R32G32B32A32_UINT:
1001 return V_028C70_SWAP_STD;
1002 default:
1003 R600_ERR("unsupported colorswap format %d\n", format);
1004 return ~0U;
1005 }
1006 return ~0U;
1007 }
1008
1009 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1010 {
1011 if (R600_BIG_ENDIAN) {
1012 switch(colorformat) {
1013 /* 8-bit buffers. */
1014 case V_028C70_COLOR_8:
1015 return V_028C70_ENDIAN_NONE;
1016
1017 /* 16-bit buffers. */
1018 case V_028C70_COLOR_5_6_5:
1019 case V_028C70_COLOR_1_5_5_5:
1020 case V_028C70_COLOR_4_4_4_4:
1021 case V_028C70_COLOR_16:
1022 case V_028C70_COLOR_8_8:
1023 return V_028C70_ENDIAN_8IN16;
1024
1025 /* 32-bit buffers. */
1026 case V_028C70_COLOR_8_8_8_8:
1027 case V_028C70_COLOR_2_10_10_10:
1028 case V_028C70_COLOR_8_24:
1029 case V_028C70_COLOR_24_8:
1030 case V_028C70_COLOR_16_16:
1031 return V_028C70_ENDIAN_8IN32;
1032
1033 /* 64-bit buffers. */
1034 case V_028C70_COLOR_16_16_16_16:
1035 return V_028C70_ENDIAN_8IN16;
1036
1037 case V_028C70_COLOR_32_32:
1038 return V_028C70_ENDIAN_8IN32;
1039
1040 /* 128-bit buffers. */
1041 case V_028C70_COLOR_32_32_32_32:
1042 return V_028C70_ENDIAN_8IN32;
1043 default:
1044 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1045 }
1046 } else {
1047 return V_028C70_ENDIAN_NONE;
1048 }
1049 }
1050
1051 /* Returns the size in bits of the widest component of a CB format */
1052 static unsigned si_colorformat_max_comp_size(uint32_t colorformat)
1053 {
1054 switch(colorformat) {
1055 case V_028C70_COLOR_4_4_4_4:
1056 return 4;
1057
1058 case V_028C70_COLOR_1_5_5_5:
1059 case V_028C70_COLOR_5_5_5_1:
1060 return 5;
1061
1062 case V_028C70_COLOR_5_6_5:
1063 return 6;
1064
1065 case V_028C70_COLOR_8:
1066 case V_028C70_COLOR_8_8:
1067 case V_028C70_COLOR_8_8_8_8:
1068 return 8;
1069
1070 case V_028C70_COLOR_10_10_10_2:
1071 case V_028C70_COLOR_2_10_10_10:
1072 return 10;
1073
1074 case V_028C70_COLOR_10_11_11:
1075 case V_028C70_COLOR_11_11_10:
1076 return 11;
1077
1078 case V_028C70_COLOR_16:
1079 case V_028C70_COLOR_16_16:
1080 case V_028C70_COLOR_16_16_16_16:
1081 return 16;
1082
1083 case V_028C70_COLOR_8_24:
1084 case V_028C70_COLOR_24_8:
1085 return 24;
1086
1087 case V_028C70_COLOR_32:
1088 case V_028C70_COLOR_32_32:
1089 case V_028C70_COLOR_32_32_32_32:
1090 case V_028C70_COLOR_X24_8_32_FLOAT:
1091 return 32;
1092 }
1093
1094 assert(!"Unknown maximum component size");
1095 return 0;
1096 }
1097
1098 static uint32_t si_translate_dbformat(enum pipe_format format)
1099 {
1100 switch (format) {
1101 //case PIPE_FORMAT_Z16_UNORM:
1102 // return V_028040_Z_16;
1103 case PIPE_FORMAT_Z24X8_UNORM:
1104 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1105 return V_028040_Z_24; /* XXX no longer supported on SI */
1106 case PIPE_FORMAT_Z32_FLOAT:
1107 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1108 return V_028040_Z_32_FLOAT;
1109 default:
1110 return ~0U;
1111 }
1112 }
1113
1114 /*
1115 * Texture translation
1116 */
1117
1118 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1119 enum pipe_format format,
1120 const struct util_format_description *desc,
1121 int first_non_void)
1122 {
1123 boolean uniform = TRUE;
1124 int i;
1125
1126 /* Colorspace (return non-RGB formats directly). */
1127 switch (desc->colorspace) {
1128 /* Depth stencil formats */
1129 case UTIL_FORMAT_COLORSPACE_ZS:
1130 switch (format) {
1131 case PIPE_FORMAT_Z16_UNORM:
1132 return V_008F14_IMG_DATA_FORMAT_16;
1133 case PIPE_FORMAT_X24S8_UINT:
1134 case PIPE_FORMAT_Z24X8_UNORM:
1135 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1136 return V_008F14_IMG_DATA_FORMAT_24_8;
1137 case PIPE_FORMAT_S8X24_UINT:
1138 case PIPE_FORMAT_X8Z24_UNORM:
1139 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1140 return V_008F14_IMG_DATA_FORMAT_8_24;
1141 case PIPE_FORMAT_S8_UINT:
1142 return V_008F14_IMG_DATA_FORMAT_8;
1143 case PIPE_FORMAT_Z32_FLOAT:
1144 return V_008F14_IMG_DATA_FORMAT_32;
1145 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1146 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1147 default:
1148 goto out_unknown;
1149 }
1150
1151 case UTIL_FORMAT_COLORSPACE_YUV:
1152 goto out_unknown; /* TODO */
1153
1154 case UTIL_FORMAT_COLORSPACE_SRGB:
1155 break;
1156
1157 default:
1158 break;
1159 }
1160
1161 /* TODO compressed formats */
1162
1163 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1164 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1165 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1166 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1167 }
1168
1169 /* R8G8Bx_SNORM - TODO CxV8U8 */
1170
1171 /* See whether the components are of the same size. */
1172 for (i = 1; i < desc->nr_channels; i++) {
1173 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1174 }
1175
1176 /* Non-uniform formats. */
1177 if (!uniform) {
1178 switch(desc->nr_channels) {
1179 case 3:
1180 if (desc->channel[0].size == 5 &&
1181 desc->channel[1].size == 6 &&
1182 desc->channel[2].size == 5) {
1183 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1184 }
1185 goto out_unknown;
1186 case 4:
1187 if (desc->channel[0].size == 5 &&
1188 desc->channel[1].size == 5 &&
1189 desc->channel[2].size == 5 &&
1190 desc->channel[3].size == 1) {
1191 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1192 }
1193 if (desc->channel[0].size == 10 &&
1194 desc->channel[1].size == 10 &&
1195 desc->channel[2].size == 10 &&
1196 desc->channel[3].size == 2) {
1197 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1198 }
1199 goto out_unknown;
1200 }
1201 goto out_unknown;
1202 }
1203
1204 if (first_non_void < 0 || first_non_void > 3)
1205 goto out_unknown;
1206
1207 /* uniform formats */
1208 switch (desc->channel[first_non_void].size) {
1209 case 4:
1210 switch (desc->nr_channels) {
1211 #if 0 /* Not supported for render targets */
1212 case 2:
1213 return V_008F14_IMG_DATA_FORMAT_4_4;
1214 #endif
1215 case 4:
1216 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1217 }
1218 break;
1219 case 8:
1220 switch (desc->nr_channels) {
1221 case 1:
1222 return V_008F14_IMG_DATA_FORMAT_8;
1223 case 2:
1224 return V_008F14_IMG_DATA_FORMAT_8_8;
1225 case 4:
1226 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1227 }
1228 break;
1229 case 16:
1230 switch (desc->nr_channels) {
1231 case 1:
1232 return V_008F14_IMG_DATA_FORMAT_16;
1233 case 2:
1234 return V_008F14_IMG_DATA_FORMAT_16_16;
1235 case 4:
1236 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1237 }
1238 break;
1239 case 32:
1240 switch (desc->nr_channels) {
1241 case 1:
1242 return V_008F14_IMG_DATA_FORMAT_32;
1243 case 2:
1244 return V_008F14_IMG_DATA_FORMAT_32_32;
1245 #if 0 /* Not supported for render targets */
1246 case 3:
1247 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1248 #endif
1249 case 4:
1250 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1251 }
1252 }
1253
1254 out_unknown:
1255 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1256 return ~0;
1257 }
1258
1259 static unsigned si_tex_wrap(unsigned wrap)
1260 {
1261 switch (wrap) {
1262 default:
1263 case PIPE_TEX_WRAP_REPEAT:
1264 return V_008F30_SQ_TEX_WRAP;
1265 case PIPE_TEX_WRAP_CLAMP:
1266 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1267 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1268 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1269 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1270 return V_008F30_SQ_TEX_CLAMP_BORDER;
1271 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1272 return V_008F30_SQ_TEX_MIRROR;
1273 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1274 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1275 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1276 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1277 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1278 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1279 }
1280 }
1281
1282 static unsigned si_tex_filter(unsigned filter)
1283 {
1284 switch (filter) {
1285 default:
1286 case PIPE_TEX_FILTER_NEAREST:
1287 return V_008F38_SQ_TEX_XY_FILTER_POINT;
1288 case PIPE_TEX_FILTER_LINEAR:
1289 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
1290 }
1291 }
1292
1293 static unsigned si_tex_mipfilter(unsigned filter)
1294 {
1295 switch (filter) {
1296 case PIPE_TEX_MIPFILTER_NEAREST:
1297 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1298 case PIPE_TEX_MIPFILTER_LINEAR:
1299 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1300 default:
1301 case PIPE_TEX_MIPFILTER_NONE:
1302 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1303 }
1304 }
1305
1306 static unsigned si_tex_compare(unsigned compare)
1307 {
1308 switch (compare) {
1309 default:
1310 case PIPE_FUNC_NEVER:
1311 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1312 case PIPE_FUNC_LESS:
1313 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1314 case PIPE_FUNC_EQUAL:
1315 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1316 case PIPE_FUNC_LEQUAL:
1317 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1318 case PIPE_FUNC_GREATER:
1319 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1320 case PIPE_FUNC_NOTEQUAL:
1321 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1322 case PIPE_FUNC_GEQUAL:
1323 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1324 case PIPE_FUNC_ALWAYS:
1325 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1326 }
1327 }
1328
1329 static unsigned si_tex_dim(unsigned dim)
1330 {
1331 switch (dim) {
1332 default:
1333 case PIPE_TEXTURE_1D:
1334 return V_008F1C_SQ_RSRC_IMG_1D;
1335 case PIPE_TEXTURE_1D_ARRAY:
1336 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1337 case PIPE_TEXTURE_2D:
1338 case PIPE_TEXTURE_RECT:
1339 return V_008F1C_SQ_RSRC_IMG_2D;
1340 case PIPE_TEXTURE_2D_ARRAY:
1341 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1342 case PIPE_TEXTURE_3D:
1343 return V_008F1C_SQ_RSRC_IMG_3D;
1344 case PIPE_TEXTURE_CUBE:
1345 return V_008F1C_SQ_RSRC_IMG_CUBE;
1346 }
1347 }
1348
1349 /*
1350 * Format support testing
1351 */
1352
1353 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1354 {
1355 return si_translate_texformat(screen, format, util_format_description(format),
1356 util_format_get_first_non_void_channel(format)) != ~0U;
1357 }
1358
1359 static uint32_t si_translate_vertexformat(struct pipe_screen *screen,
1360 enum pipe_format format,
1361 const struct util_format_description *desc,
1362 int first_non_void)
1363 {
1364 unsigned type = desc->channel[first_non_void].type;
1365 int i;
1366
1367 if (type == UTIL_FORMAT_TYPE_FIXED)
1368 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1369
1370 /* See whether the components are of the same size. */
1371 for (i = 0; i < desc->nr_channels; i++) {
1372 if (desc->channel[first_non_void].size != desc->channel[i].size)
1373 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1374 }
1375
1376 switch (desc->channel[first_non_void].size) {
1377 case 8:
1378 switch (desc->nr_channels) {
1379 case 1:
1380 return V_008F0C_BUF_DATA_FORMAT_8;
1381 case 2:
1382 return V_008F0C_BUF_DATA_FORMAT_8_8;
1383 case 3:
1384 case 4:
1385 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1386 }
1387 break;
1388 case 16:
1389 switch (desc->nr_channels) {
1390 case 1:
1391 return V_008F0C_BUF_DATA_FORMAT_16;
1392 case 2:
1393 return V_008F0C_BUF_DATA_FORMAT_16_16;
1394 case 3:
1395 case 4:
1396 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1397 }
1398 break;
1399 case 32:
1400 if (type != UTIL_FORMAT_TYPE_FLOAT)
1401 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1402
1403 switch (desc->nr_channels) {
1404 case 1:
1405 return V_008F0C_BUF_DATA_FORMAT_32;
1406 case 2:
1407 return V_008F0C_BUF_DATA_FORMAT_32_32;
1408 case 3:
1409 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1410 case 4:
1411 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1412 }
1413 break;
1414 }
1415
1416 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1417 }
1418
1419 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
1420 {
1421 const struct util_format_description *desc;
1422 int first_non_void;
1423 unsigned data_format;
1424
1425 desc = util_format_description(format);
1426 first_non_void = util_format_get_first_non_void_channel(format);
1427 data_format = si_translate_vertexformat(screen, format, desc, first_non_void);
1428 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
1429 }
1430
1431 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1432 {
1433 return si_translate_colorformat(format) != ~0U &&
1434 si_translate_colorswap(format) != ~0U;
1435 }
1436
1437 static bool si_is_zs_format_supported(enum pipe_format format)
1438 {
1439 return si_translate_dbformat(format) != ~0U;
1440 }
1441
1442 boolean si_is_format_supported(struct pipe_screen *screen,
1443 enum pipe_format format,
1444 enum pipe_texture_target target,
1445 unsigned sample_count,
1446 unsigned usage)
1447 {
1448 unsigned retval = 0;
1449
1450 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1451 R600_ERR("r600: unsupported texture type %d\n", target);
1452 return FALSE;
1453 }
1454
1455 if (!util_format_is_supported(format, usage))
1456 return FALSE;
1457
1458 /* Multisample */
1459 if (sample_count > 1)
1460 return FALSE;
1461
1462 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
1463 si_is_sampler_format_supported(screen, format)) {
1464 retval |= PIPE_BIND_SAMPLER_VIEW;
1465 }
1466
1467 if ((usage & (PIPE_BIND_RENDER_TARGET |
1468 PIPE_BIND_DISPLAY_TARGET |
1469 PIPE_BIND_SCANOUT |
1470 PIPE_BIND_SHARED)) &&
1471 si_is_colorbuffer_format_supported(format)) {
1472 retval |= usage &
1473 (PIPE_BIND_RENDER_TARGET |
1474 PIPE_BIND_DISPLAY_TARGET |
1475 PIPE_BIND_SCANOUT |
1476 PIPE_BIND_SHARED);
1477 }
1478
1479 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1480 si_is_zs_format_supported(format)) {
1481 retval |= PIPE_BIND_DEPTH_STENCIL;
1482 }
1483
1484 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
1485 si_is_vertex_format_supported(screen, format)) {
1486 retval |= PIPE_BIND_VERTEX_BUFFER;
1487 }
1488
1489 if (usage & PIPE_BIND_TRANSFER_READ)
1490 retval |= PIPE_BIND_TRANSFER_READ;
1491 if (usage & PIPE_BIND_TRANSFER_WRITE)
1492 retval |= PIPE_BIND_TRANSFER_WRITE;
1493
1494 return retval == usage;
1495 }
1496
1497 /*
1498 * framebuffer handling
1499 */
1500
1501 static void si_cb(struct r600_context *rctx, struct si_pm4_state *pm4,
1502 const struct pipe_framebuffer_state *state, int cb)
1503 {
1504 struct r600_resource_texture *rtex;
1505 struct r600_surface *surf;
1506 unsigned level = state->cbufs[cb]->u.tex.level;
1507 unsigned pitch, slice;
1508 unsigned color_info, color_attrib;
1509 unsigned format, swap, ntype, endian;
1510 uint64_t offset;
1511 unsigned blocksize;
1512 const struct util_format_description *desc;
1513 int i;
1514 unsigned blend_clamp = 0, blend_bypass = 0;
1515 unsigned max_comp_size;
1516
1517 surf = (struct r600_surface *)state->cbufs[cb];
1518 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
1519 blocksize = util_format_get_blocksize(rtex->real_format);
1520
1521 if (rtex->depth)
1522 rctx->have_depth_fb = TRUE;
1523
1524 if (rtex->depth && !rtex->is_flushing_texture) {
1525 r600_texture_depth_flush(&rctx->context, state->cbufs[cb]->texture, TRUE);
1526 rtex = rtex->flushed_depth_texture;
1527 }
1528
1529 offset = rtex->surface.level[level].offset;
1530 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1531 offset += rtex->surface.level[level].slice_size *
1532 state->cbufs[cb]->u.tex.first_layer;
1533 }
1534 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1535 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1536 if (slice) {
1537 slice = slice - 1;
1538 }
1539
1540 color_attrib = S_028C74_TILE_MODE_INDEX(8);
1541 switch (rtex->surface.level[level].mode) {
1542 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1543 color_attrib = S_028C74_TILE_MODE_INDEX(8);
1544 break;
1545 case RADEON_SURF_MODE_1D:
1546 color_attrib = S_028C74_TILE_MODE_INDEX(9);
1547 break;
1548 case RADEON_SURF_MODE_2D:
1549 if (rtex->resource.b.b.bind & PIPE_BIND_SCANOUT) {
1550 switch (blocksize) {
1551 case 1:
1552 color_attrib = S_028C74_TILE_MODE_INDEX(10);
1553 break;
1554 case 2:
1555 color_attrib = S_028C74_TILE_MODE_INDEX(11);
1556 break;
1557 case 4:
1558 color_attrib = S_028C74_TILE_MODE_INDEX(12);
1559 break;
1560 }
1561 break;
1562 } else switch (blocksize) {
1563 case 1:
1564 color_attrib = S_028C74_TILE_MODE_INDEX(14);
1565 break;
1566 case 2:
1567 color_attrib = S_028C74_TILE_MODE_INDEX(15);
1568 break;
1569 case 4:
1570 color_attrib = S_028C74_TILE_MODE_INDEX(16);
1571 break;
1572 case 8:
1573 color_attrib = S_028C74_TILE_MODE_INDEX(17);
1574 break;
1575 default:
1576 color_attrib = S_028C74_TILE_MODE_INDEX(13);
1577 }
1578 break;
1579 }
1580
1581 desc = util_format_description(surf->base.format);
1582 for (i = 0; i < 4; i++) {
1583 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1584 break;
1585 }
1586 }
1587 if (desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1588 ntype = V_028C70_NUMBER_FLOAT;
1589 } else {
1590 ntype = V_028C70_NUMBER_UNORM;
1591 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1592 ntype = V_028C70_NUMBER_SRGB;
1593 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1594 if (desc->channel[i].normalized)
1595 ntype = V_028C70_NUMBER_SNORM;
1596 else if (desc->channel[i].pure_integer)
1597 ntype = V_028C70_NUMBER_SINT;
1598 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1599 if (desc->channel[i].normalized)
1600 ntype = V_028C70_NUMBER_UNORM;
1601 else if (desc->channel[i].pure_integer)
1602 ntype = V_028C70_NUMBER_UINT;
1603 }
1604 }
1605
1606 format = si_translate_colorformat(surf->base.format);
1607 swap = si_translate_colorswap(surf->base.format);
1608 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1609 endian = V_028C70_ENDIAN_NONE;
1610 } else {
1611 endian = si_colorformat_endian_swap(format);
1612 }
1613
1614 /* blend clamp should be set for all NORM/SRGB types */
1615 if (ntype == V_028C70_NUMBER_UNORM ||
1616 ntype == V_028C70_NUMBER_SNORM ||
1617 ntype == V_028C70_NUMBER_SRGB)
1618 blend_clamp = 1;
1619
1620 /* set blend bypass according to docs if SINT/UINT or
1621 8/24 COLOR variants */
1622 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1623 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1624 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1625 blend_clamp = 0;
1626 blend_bypass = 1;
1627 }
1628
1629 color_info = S_028C70_FORMAT(format) |
1630 S_028C70_COMP_SWAP(swap) |
1631 S_028C70_BLEND_CLAMP(blend_clamp) |
1632 S_028C70_BLEND_BYPASS(blend_bypass) |
1633 S_028C70_NUMBER_TYPE(ntype) |
1634 S_028C70_ENDIAN(endian);
1635
1636 offset += r600_resource_va(rctx->context.screen, state->cbufs[cb]->texture);
1637 offset >>= 8;
1638
1639 /* FIXME handle enabling of CB beyond BASE8 which has different offset */
1640 si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE);
1641 si_pm4_set_reg(pm4, R_028C60_CB_COLOR0_BASE + cb * 0x3C, offset);
1642 si_pm4_set_reg(pm4, R_028C64_CB_COLOR0_PITCH + cb * 0x3C, S_028C64_TILE_MAX(pitch));
1643 si_pm4_set_reg(pm4, R_028C68_CB_COLOR0_SLICE + cb * 0x3C, S_028C68_TILE_MAX(slice));
1644
1645 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1646 si_pm4_set_reg(pm4, R_028C6C_CB_COLOR0_VIEW + cb * 0x3C, 0x00000000);
1647 } else {
1648 si_pm4_set_reg(pm4, R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1649 S_028C6C_SLICE_START(state->cbufs[cb]->u.tex.first_layer) |
1650 S_028C6C_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer));
1651 }
1652 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + cb * 0x3C, color_info);
1653 si_pm4_set_reg(pm4, R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C, color_attrib);
1654
1655 /* Determine pixel shader export format */
1656 max_comp_size = si_colorformat_max_comp_size(format);
1657 if (ntype == V_028C70_NUMBER_SRGB ||
1658 ((ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM) &&
1659 max_comp_size <= 10) ||
1660 (ntype == V_028C70_NUMBER_FLOAT && max_comp_size <= 16)) {
1661 rctx->export_16bpc |= 1 << cb;
1662 rctx->spi_shader_col_format |= V_028714_SPI_SHADER_FP16_ABGR << (4 * cb);
1663 } else
1664 rctx->spi_shader_col_format |= V_028714_SPI_SHADER_32_ABGR << (4 * cb);
1665 }
1666
1667 static void si_db(struct r600_context *rctx, struct si_pm4_state *pm4,
1668 const struct pipe_framebuffer_state *state)
1669 {
1670 struct r600_resource_texture *rtex;
1671 struct r600_surface *surf;
1672 unsigned level, pitch, slice, format;
1673 uint32_t z_info, s_info;
1674 uint64_t z_offs, s_offs;
1675
1676 if (state->zsbuf == NULL) {
1677 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, 0);
1678 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, 0);
1679 return;
1680 }
1681
1682 surf = (struct r600_surface *)state->zsbuf;
1683 level = surf->base.u.tex.level;
1684 rtex = (struct r600_resource_texture*)surf->base.texture;
1685
1686 format = si_translate_dbformat(rtex->real_format);
1687
1688 z_offs = r600_resource_va(rctx->context.screen, surf->base.texture);
1689 z_offs += rtex->surface.level[level].offset;
1690
1691 s_offs = r600_resource_va(rctx->context.screen, surf->base.texture);
1692 s_offs += rtex->surface.stencil_offset;
1693 z_offs += rtex->surface.level[level].offset / 4;
1694
1695 z_offs >>= 8;
1696 s_offs >>= 8;
1697
1698 pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
1699 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1700 if (slice) {
1701 slice = slice - 1;
1702 }
1703
1704 z_info = S_028040_FORMAT(format);
1705 s_info = S_028044_FORMAT(1);
1706
1707 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_1D) {
1708 z_info |= S_028040_TILE_MODE_INDEX(4);
1709 s_info |= S_028044_TILE_MODE_INDEX(4);
1710
1711 } else if (rtex->surface.level[level].mode == RADEON_SURF_MODE_2D) {
1712 switch (format) {
1713 case V_028040_Z_16:
1714 z_info |= S_028040_TILE_MODE_INDEX(5);
1715 s_info |= S_028044_TILE_MODE_INDEX(5);
1716 break;
1717 case V_028040_Z_24:
1718 case V_028040_Z_32_FLOAT:
1719 z_info |= S_028040_TILE_MODE_INDEX(6);
1720 s_info |= S_028044_TILE_MODE_INDEX(6);
1721 break;
1722 default:
1723 z_info |= S_028040_TILE_MODE_INDEX(7);
1724 s_info |= S_028044_TILE_MODE_INDEX(7);
1725 }
1726
1727 } else {
1728 R600_ERR("Invalid DB tiling mode %d!\n",
1729 rtex->surface.level[level].mode);
1730 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, 0);
1731 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, 0);
1732 return;
1733 }
1734
1735 si_pm4_set_reg(pm4, R_028008_DB_DEPTH_VIEW,
1736 S_028008_SLICE_START(state->zsbuf->u.tex.first_layer) |
1737 S_028008_SLICE_MAX(state->zsbuf->u.tex.last_layer));
1738
1739 si_pm4_set_reg(pm4, R_02803C_DB_DEPTH_INFO, 0x1);
1740 if (format != ~0U) {
1741 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, z_info);
1742
1743 } else {
1744 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, 0);
1745 }
1746
1747 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
1748 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, s_info);
1749 } else {
1750 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, 0);
1751 }
1752
1753 si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE);
1754 si_pm4_set_reg(pm4, R_028048_DB_Z_READ_BASE, z_offs);
1755 si_pm4_set_reg(pm4, R_02804C_DB_STENCIL_READ_BASE, s_offs);
1756 si_pm4_set_reg(pm4, R_028050_DB_Z_WRITE_BASE, z_offs);
1757 si_pm4_set_reg(pm4, R_028054_DB_STENCIL_WRITE_BASE, s_offs);
1758
1759 si_pm4_set_reg(pm4, R_028058_DB_DEPTH_SIZE, S_028058_PITCH_TILE_MAX(pitch));
1760 si_pm4_set_reg(pm4, R_02805C_DB_DEPTH_SLICE, S_02805C_SLICE_TILE_MAX(slice));
1761 }
1762
1763 static void si_set_framebuffer_state(struct pipe_context *ctx,
1764 const struct pipe_framebuffer_state *state)
1765 {
1766 struct r600_context *rctx = (struct r600_context *)ctx;
1767 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
1768 uint32_t shader_mask, tl, br;
1769 int tl_x, tl_y, br_x, br_y;
1770
1771 if (pm4 == NULL)
1772 return;
1773
1774 si_pm4_inval_fb_cache(pm4, state->nr_cbufs);
1775
1776 if (state->zsbuf)
1777 si_pm4_inval_zsbuf_cache(pm4);
1778
1779 util_copy_framebuffer_state(&rctx->framebuffer, state);
1780
1781 /* build states */
1782 rctx->have_depth_fb = 0;
1783 rctx->export_16bpc = 0;
1784 rctx->spi_shader_col_format = 0;
1785 for (int i = 0; i < state->nr_cbufs; i++) {
1786 si_cb(rctx, pm4, state, i);
1787 }
1788 assert(!(rctx->export_16bpc & ~0xff));
1789 si_db(rctx, pm4, state);
1790
1791 shader_mask = 0;
1792 for (int i = 0; i < state->nr_cbufs; i++) {
1793 shader_mask |= 0xf << (i * 4);
1794 }
1795 tl_x = 0;
1796 tl_y = 0;
1797 br_x = state->width;
1798 br_y = state->height;
1799
1800 tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
1801 br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
1802
1803 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, tl);
1804 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR, br);
1805 si_pm4_set_reg(pm4, R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl);
1806 si_pm4_set_reg(pm4, R_028254_PA_SC_VPORT_SCISSOR_0_BR, br);
1807 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, tl);
1808 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR, br);
1809 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, tl);
1810 si_pm4_set_reg(pm4, R_028208_PA_SC_WINDOW_SCISSOR_BR, br);
1811 si_pm4_set_reg(pm4, R_028200_PA_SC_WINDOW_OFFSET, 0x00000000);
1812 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
1813 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, shader_mask);
1814 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT,
1815 rctx->spi_shader_col_format);
1816 si_pm4_set_reg(pm4, R_028BE0_PA_SC_AA_CONFIG, 0x00000000);
1817
1818 si_pm4_set_state(rctx, framebuffer, pm4);
1819 si_update_fb_rs_state(rctx);
1820 si_update_fb_blend_state(rctx);
1821 }
1822
1823 /*
1824 * shaders
1825 */
1826
1827 /* Compute the key for the hw shader variant */
1828 static INLINE struct si_shader_key si_shader_selector_key(struct pipe_context *ctx,
1829 struct si_pipe_shader_selector *sel)
1830 {
1831 struct r600_context *rctx = (struct r600_context *)ctx;
1832 struct si_shader_key key;
1833 memset(&key, 0, sizeof(key));
1834
1835 if (sel->type == PIPE_SHADER_FRAGMENT) {
1836 if (sel->fs_write_all)
1837 key.nr_cbufs = rctx->framebuffer.nr_cbufs;
1838 key.export_16bpc = rctx->export_16bpc;
1839 if (rctx->queued.named.rasterizer) {
1840 key.color_two_side = rctx->queued.named.rasterizer->two_side;
1841 /*key.flatshade = rctx->queued.named.rasterizer->flatshade;*/
1842 }
1843 if (rctx->queued.named.dsa) {
1844 key.alpha_func = rctx->queued.named.dsa->alpha_func;
1845 key.alpha_ref = rctx->queued.named.dsa->alpha_ref;
1846 } else {
1847 key.alpha_func = PIPE_FUNC_ALWAYS;
1848 }
1849 }
1850
1851 return key;
1852 }
1853
1854 /* Select the hw shader variant depending on the current state.
1855 * (*dirty) is set to 1 if current variant was changed */
1856 int si_shader_select(struct pipe_context *ctx,
1857 struct si_pipe_shader_selector *sel,
1858 unsigned *dirty)
1859 {
1860 struct si_shader_key key;
1861 struct si_pipe_shader * shader = NULL;
1862 int r;
1863
1864 key = si_shader_selector_key(ctx, sel);
1865
1866 /* Check if we don't need to change anything.
1867 * This path is also used for most shaders that don't need multiple
1868 * variants, it will cost just a computation of the key and this
1869 * test. */
1870 if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
1871 return 0;
1872 }
1873
1874 /* lookup if we have other variants in the list */
1875 if (sel->num_shaders > 1) {
1876 struct si_pipe_shader *p = sel->current, *c = p->next_variant;
1877
1878 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
1879 p = c;
1880 c = c->next_variant;
1881 }
1882
1883 if (c) {
1884 p->next_variant = c->next_variant;
1885 shader = c;
1886 }
1887 }
1888
1889 if (unlikely(!shader)) {
1890 shader = CALLOC(1, sizeof(struct si_pipe_shader));
1891 shader->selector = sel;
1892
1893 r = si_pipe_shader_create(ctx, shader, key);
1894 if (unlikely(r)) {
1895 R600_ERR("Failed to build shader variant (type=%u) %d\n",
1896 sel->type, r);
1897 sel->current = NULL;
1898 return r;
1899 }
1900
1901 /* We don't know the value of fs_write_all property until we built
1902 * at least one variant, so we may need to recompute the key (include
1903 * rctx->framebuffer.nr_cbufs) after building first variant. */
1904 if (sel->type == PIPE_SHADER_FRAGMENT &&
1905 sel->num_shaders == 0 &&
1906 shader->shader.fs_write_all) {
1907 sel->fs_write_all = 1;
1908 key = si_shader_selector_key(ctx, sel);
1909 }
1910
1911 shader->key = key;
1912 sel->num_shaders++;
1913 }
1914
1915 if (dirty)
1916 *dirty = 1;
1917
1918 shader->next_variant = sel->current;
1919 sel->current = shader;
1920
1921 return 0;
1922 }
1923
1924 static void *si_create_shader_state(struct pipe_context *ctx,
1925 const struct pipe_shader_state *state,
1926 unsigned pipe_shader_type)
1927 {
1928 struct si_pipe_shader_selector *sel = CALLOC_STRUCT(si_pipe_shader_selector);
1929 int r;
1930
1931 sel->type = pipe_shader_type;
1932 sel->tokens = tgsi_dup_tokens(state->tokens);
1933 sel->so = state->stream_output;
1934
1935 r = si_shader_select(ctx, sel, NULL);
1936 if (r) {
1937 free(sel);
1938 return NULL;
1939 }
1940
1941 return sel;
1942 }
1943
1944 static void *si_create_fs_state(struct pipe_context *ctx,
1945 const struct pipe_shader_state *state)
1946 {
1947 return si_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
1948 }
1949
1950 static void *si_create_vs_state(struct pipe_context *ctx,
1951 const struct pipe_shader_state *state)
1952 {
1953 return si_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
1954 }
1955
1956 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
1957 {
1958 struct r600_context *rctx = (struct r600_context *)ctx;
1959 struct si_pipe_shader_selector *sel = state;
1960
1961 if (rctx->vs_shader == sel)
1962 return;
1963
1964 rctx->vs_shader = sel;
1965
1966 if (sel && sel->current)
1967 si_pm4_bind_state(rctx, vs, sel->current->pm4);
1968 else
1969 si_pm4_bind_state(rctx, vs, rctx->dummy_pixel_shader->pm4);
1970 }
1971
1972 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
1973 {
1974 struct r600_context *rctx = (struct r600_context *)ctx;
1975 struct si_pipe_shader_selector *sel = state;
1976
1977 if (rctx->ps_shader == sel)
1978 return;
1979
1980 rctx->ps_shader = sel;
1981
1982 if (sel && sel->current)
1983 si_pm4_bind_state(rctx, ps, sel->current->pm4);
1984 else
1985 si_pm4_bind_state(rctx, ps, rctx->dummy_pixel_shader->pm4);
1986 }
1987
1988 static void si_delete_shader_selector(struct pipe_context *ctx,
1989 struct si_pipe_shader_selector *sel)
1990 {
1991 struct r600_context *rctx = (struct r600_context *)ctx;
1992 struct si_pipe_shader *p = sel->current, *c;
1993
1994 while (p) {
1995 c = p->next_variant;
1996 si_pm4_delete_state(rctx, vs, p->pm4);
1997 si_pipe_shader_destroy(ctx, p);
1998 free(p);
1999 p = c;
2000 }
2001
2002 free(sel->tokens);
2003 free(sel);
2004 }
2005
2006 static void si_delete_vs_shader(struct pipe_context *ctx, void *state)
2007 {
2008 struct r600_context *rctx = (struct r600_context *)ctx;
2009 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state;
2010
2011 if (rctx->vs_shader == sel) {
2012 rctx->vs_shader = NULL;
2013 }
2014
2015 si_delete_shader_selector(ctx, sel);
2016 }
2017
2018 static void si_delete_ps_shader(struct pipe_context *ctx, void *state)
2019 {
2020 struct r600_context *rctx = (struct r600_context *)ctx;
2021 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state;
2022
2023 if (rctx->ps_shader == sel) {
2024 rctx->ps_shader = NULL;
2025 }
2026
2027 si_delete_shader_selector(ctx, sel);
2028 }
2029
2030 /*
2031 * Samplers
2032 */
2033
2034 static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx,
2035 struct pipe_resource *texture,
2036 const struct pipe_sampler_view *state)
2037 {
2038 struct si_pipe_sampler_view *view = CALLOC_STRUCT(si_pipe_sampler_view);
2039 struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
2040 const struct util_format_description *desc = util_format_description(state->format);
2041 unsigned blocksize = util_format_get_blocksize(tmp->real_format);
2042 unsigned format, num_format, /*endian,*/ tiling_index;
2043 uint32_t pitch = 0;
2044 unsigned char state_swizzle[4], swizzle[4];
2045 unsigned height, depth, width;
2046 int first_non_void;
2047 uint64_t va;
2048
2049 if (view == NULL)
2050 return NULL;
2051
2052 /* initialize base object */
2053 view->base = *state;
2054 view->base.texture = NULL;
2055 pipe_reference(NULL, &texture->reference);
2056 view->base.texture = texture;
2057 view->base.reference.count = 1;
2058 view->base.context = ctx;
2059
2060 state_swizzle[0] = state->swizzle_r;
2061 state_swizzle[1] = state->swizzle_g;
2062 state_swizzle[2] = state->swizzle_b;
2063 state_swizzle[3] = state->swizzle_a;
2064 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2065
2066 first_non_void = util_format_get_first_non_void_channel(state->format);
2067 switch (desc->channel[first_non_void].type) {
2068 case UTIL_FORMAT_TYPE_FLOAT:
2069 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2070 break;
2071 case UTIL_FORMAT_TYPE_SIGNED:
2072 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2073 break;
2074 case UTIL_FORMAT_TYPE_UNSIGNED:
2075 default:
2076 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2077 }
2078
2079 format = si_translate_texformat(ctx->screen, state->format, desc, first_non_void);
2080 if (format == ~0) {
2081 format = 0;
2082 }
2083
2084 if (tmp->depth && !tmp->is_flushing_texture) {
2085 r600_texture_depth_flush(ctx, texture, TRUE);
2086 tmp = tmp->flushed_depth_texture;
2087 }
2088
2089 /* not supported any more */
2090 //endian = si_colorformat_endian_swap(format);
2091
2092 width = tmp->surface.level[0].npix_x;
2093 height = tmp->surface.level[0].npix_y;
2094 depth = tmp->surface.level[0].npix_z;
2095 pitch = tmp->surface.level[0].nblk_x * util_format_get_blockwidth(state->format);
2096
2097 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
2098 height = 1;
2099 depth = texture->array_size;
2100 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
2101 depth = texture->array_size;
2102 }
2103
2104 tiling_index = 8;
2105 switch (tmp->surface.level[0].mode) {
2106 case RADEON_SURF_MODE_LINEAR_ALIGNED:
2107 tiling_index = 8;
2108 break;
2109 case RADEON_SURF_MODE_1D:
2110 tiling_index = 9;
2111 break;
2112 case RADEON_SURF_MODE_2D:
2113 if (tmp->resource.b.b.bind & PIPE_BIND_SCANOUT) {
2114 switch (blocksize) {
2115 case 1:
2116 tiling_index = 10;
2117 break;
2118 case 2:
2119 tiling_index = 11;
2120 break;
2121 case 4:
2122 tiling_index = 12;
2123 break;
2124 }
2125 break;
2126 } else switch (blocksize) {
2127 case 1:
2128 tiling_index = 14;
2129 break;
2130 case 2:
2131 tiling_index = 15;
2132 break;
2133 case 4:
2134 tiling_index = 16;
2135 break;
2136 case 8:
2137 tiling_index = 17;
2138 break;
2139 default:
2140 tiling_index = 13;
2141 }
2142 break;
2143 }
2144
2145 va = r600_resource_va(ctx->screen, texture);
2146 va += tmp->surface.level[0].offset;
2147 view->state[0] = va >> 8;
2148 view->state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) |
2149 S_008F14_DATA_FORMAT(format) |
2150 S_008F14_NUM_FORMAT(num_format));
2151 view->state[2] = (S_008F18_WIDTH(width - 1) |
2152 S_008F18_HEIGHT(height - 1));
2153 view->state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2154 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2155 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2156 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2157 S_008F1C_BASE_LEVEL(state->u.tex.first_level) |
2158 S_008F1C_LAST_LEVEL(state->u.tex.last_level) |
2159 S_008F1C_TILING_INDEX(tiling_index) |
2160 S_008F1C_POW2_PAD(texture->last_level > 0) |
2161 S_008F1C_TYPE(si_tex_dim(texture->target)));
2162 view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
2163 view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2164 S_008F24_LAST_ARRAY(state->u.tex.last_layer));
2165 view->state[6] = 0;
2166 view->state[7] = 0;
2167
2168 return &view->base;
2169 }
2170
2171 static void si_sampler_view_destroy(struct pipe_context *ctx,
2172 struct pipe_sampler_view *state)
2173 {
2174 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
2175
2176 pipe_resource_reference(&state->texture, NULL);
2177 FREE(resource);
2178 }
2179
2180 static void *si_create_sampler_state(struct pipe_context *ctx,
2181 const struct pipe_sampler_state *state)
2182 {
2183 struct si_pipe_sampler_state *rstate = CALLOC_STRUCT(si_pipe_sampler_state);
2184 union util_color uc;
2185 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
2186 unsigned border_color_type;
2187
2188 if (rstate == NULL) {
2189 return NULL;
2190 }
2191
2192 util_pack_color(state->border_color.f, PIPE_FORMAT_A8R8G8B8_UNORM, &uc);
2193 switch (uc.ui) {
2194 case 0x000000FF:
2195 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
2196 break;
2197 case 0x00000000:
2198 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
2199 break;
2200 case 0xFFFFFFFF:
2201 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
2202 break;
2203 default: /* Use border color pointer */
2204 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
2205 }
2206
2207 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
2208 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
2209 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
2210 (state->max_anisotropy & 0x7) << 9 | /* XXX */
2211 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
2212 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
2213 aniso_flag_offset << 16 | /* XXX */
2214 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map));
2215 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
2216 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
2217 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
2218 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter)) |
2219 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter)) |
2220 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)));
2221 rstate->val[3] = S_008F3C_BORDER_COLOR_TYPE(border_color_type);
2222
2223 if (border_color_type == V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2224 memcpy(rstate->border_color, state->border_color.f,
2225 sizeof(rstate->border_color));
2226 }
2227
2228 return rstate;
2229 }
2230
2231 static struct si_pm4_state *si_set_sampler_view(struct r600_context *rctx,
2232 unsigned count,
2233 struct pipe_sampler_view **views,
2234 struct r600_textures_info *samplers,
2235 unsigned user_data_reg)
2236 {
2237 struct si_pipe_sampler_view **resource = (struct si_pipe_sampler_view **)views;
2238 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
2239 int i, j;
2240 int has_depth = 0;
2241
2242 if (!count)
2243 goto out;
2244
2245 si_pm4_inval_texture_cache(pm4);
2246
2247 si_pm4_sh_data_begin(pm4);
2248 for (i = 0; i < count; i++) {
2249 pipe_sampler_view_reference(
2250 (struct pipe_sampler_view **)&samplers->views[i],
2251 views[i]);
2252
2253 if (views[i]) {
2254 struct r600_resource_texture *tex = (void *)resource[i]->base.texture;
2255
2256 si_pm4_add_bo(pm4, &tex->resource, RADEON_USAGE_READ);
2257 }
2258
2259 for (j = 0; j < Elements(resource[i]->state); ++j) {
2260 si_pm4_sh_data_add(pm4, resource[i] ? resource[i]->state[j] : 0);
2261 }
2262 }
2263
2264 for (i = count; i < NUM_TEX_UNITS; i++) {
2265 if (samplers->views[i])
2266 pipe_sampler_view_reference((struct pipe_sampler_view **)&samplers->views[i], NULL);
2267 }
2268
2269 si_pm4_sh_data_end(pm4, user_data_reg, SI_SGPR_RESOURCE);
2270
2271 out:
2272 rctx->have_depth_texture = has_depth;
2273 rctx->ps_samplers.n_views = count;
2274 return pm4;
2275 }
2276
2277 static void si_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
2278 struct pipe_sampler_view **views)
2279 {
2280 struct r600_context *rctx = (struct r600_context *)ctx;
2281 struct si_pm4_state *pm4;
2282
2283 pm4 = si_set_sampler_view(rctx, count, views, &rctx->vs_samplers,
2284 R_00B130_SPI_SHADER_USER_DATA_VS_0);
2285 si_pm4_set_state(rctx, vs_sampler_views, pm4);
2286 }
2287
2288 static void si_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
2289 struct pipe_sampler_view **views)
2290 {
2291 struct r600_context *rctx = (struct r600_context *)ctx;
2292 struct si_pm4_state *pm4;
2293
2294 pm4 = si_set_sampler_view(rctx, count, views, &rctx->ps_samplers,
2295 R_00B030_SPI_SHADER_USER_DATA_PS_0);
2296 si_pm4_set_state(rctx, ps_sampler_views, pm4);
2297 }
2298
2299 static struct si_pm4_state *si_bind_sampler(struct r600_context *rctx, unsigned count,
2300 void **states,
2301 struct r600_textures_info *samplers,
2302 unsigned user_data_reg)
2303 {
2304 struct si_pipe_sampler_state **rstates = (struct si_pipe_sampler_state **)states;
2305 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
2306 uint32_t *border_color_table = NULL;
2307 int i, j;
2308
2309 if (!count)
2310 goto out;
2311
2312 si_pm4_inval_texture_cache(pm4);
2313
2314 si_pm4_sh_data_begin(pm4);
2315 for (i = 0; i < count; i++) {
2316 if (rstates[i] &&
2317 G_008F3C_BORDER_COLOR_TYPE(rstates[i]->val[3]) ==
2318 V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2319 if (!rctx->border_color_table ||
2320 ((rctx->border_color_offset + count - i) &
2321 C_008F3C_BORDER_COLOR_PTR)) {
2322 si_resource_reference(&rctx->border_color_table, NULL);
2323 rctx->border_color_offset = 0;
2324
2325 rctx->border_color_table =
2326 si_resource_create_custom(&rctx->screen->screen,
2327 PIPE_USAGE_STAGING,
2328 4096 * 4 * 4);
2329 }
2330
2331 if (!border_color_table) {
2332 border_color_table =
2333 rctx->ws->buffer_map(rctx->border_color_table->cs_buf,
2334 rctx->cs,
2335 PIPE_TRANSFER_WRITE |
2336 PIPE_TRANSFER_UNSYNCHRONIZED);
2337 }
2338
2339 for (j = 0; j < 4; j++) {
2340 union fi border_color;
2341
2342 border_color.f = rstates[i]->border_color[j];
2343 border_color_table[4 * rctx->border_color_offset + j] =
2344 util_le32_to_cpu(border_color.i);
2345 }
2346
2347 rstates[i]->val[3] &= C_008F3C_BORDER_COLOR_PTR;
2348 rstates[i]->val[3] |= S_008F3C_BORDER_COLOR_PTR(rctx->border_color_offset++);
2349 }
2350
2351 for (j = 0; j < Elements(rstates[i]->val); ++j) {
2352 si_pm4_sh_data_add(pm4, rstates[i] ? rstates[i]->val[j] : 0);
2353 }
2354 }
2355 si_pm4_sh_data_end(pm4, user_data_reg, SI_SGPR_SAMPLER);
2356
2357 if (border_color_table) {
2358 uint64_t va_offset =
2359 r600_resource_va(&rctx->screen->screen,
2360 (void*)rctx->border_color_table);
2361
2362 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, va_offset >> 8);
2363 rctx->ws->buffer_unmap(rctx->border_color_table->cs_buf);
2364 si_pm4_add_bo(pm4, rctx->border_color_table, RADEON_USAGE_READ);
2365 }
2366
2367 memcpy(samplers->samplers, states, sizeof(void*) * count);
2368
2369 out:
2370 samplers->n_samplers = count;
2371 return pm4;
2372 }
2373
2374 static void si_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
2375 {
2376 struct r600_context *rctx = (struct r600_context *)ctx;
2377 struct si_pm4_state *pm4;
2378
2379 pm4 = si_bind_sampler(rctx, count, states, &rctx->vs_samplers,
2380 R_00B130_SPI_SHADER_USER_DATA_VS_0);
2381 si_pm4_set_state(rctx, vs_sampler, pm4);
2382 }
2383
2384 static void si_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
2385 {
2386 struct r600_context *rctx = (struct r600_context *)ctx;
2387 struct si_pm4_state *pm4;
2388
2389 pm4 = si_bind_sampler(rctx, count, states, &rctx->ps_samplers,
2390 R_00B030_SPI_SHADER_USER_DATA_PS_0);
2391 si_pm4_set_state(rctx, ps_sampler, pm4);
2392 }
2393
2394 static void si_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
2395 {
2396 }
2397
2398 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
2399 {
2400 free(state);
2401 }
2402
2403 /*
2404 * Constants
2405 */
2406 static void si_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
2407 struct pipe_constant_buffer *cb)
2408 {
2409 struct r600_context *rctx = (struct r600_context *)ctx;
2410 struct si_resource *rbuffer = cb ? si_resource(cb->buffer) : NULL;
2411 struct si_pm4_state *pm4;
2412 uint64_t va_offset;
2413 uint32_t reg, offset;
2414
2415 /* Note that the state tracker can unbind constant buffers by
2416 * passing NULL here.
2417 */
2418 if (cb == NULL)
2419 return;
2420
2421 pm4 = CALLOC_STRUCT(si_pm4_state);
2422 si_pm4_inval_shader_cache(pm4);
2423
2424 if (cb->user_buffer)
2425 r600_upload_const_buffer(rctx, &rbuffer, cb->user_buffer, cb->buffer_size, &offset);
2426 else
2427 offset = 0;
2428 va_offset = r600_resource_va(ctx->screen, (void*)rbuffer);
2429 va_offset += offset;
2430
2431 si_pm4_add_bo(pm4, rbuffer, RADEON_USAGE_READ);
2432
2433 switch (shader) {
2434 case PIPE_SHADER_VERTEX:
2435 reg = R_00B130_SPI_SHADER_USER_DATA_VS_0 + SI_SGPR_CONST * 4;
2436 si_pm4_set_reg(pm4, reg, va_offset);
2437 si_pm4_set_reg(pm4, reg + 4, va_offset >> 32);
2438 si_pm4_set_state(rctx, vs_const, pm4);
2439 break;
2440
2441 case PIPE_SHADER_FRAGMENT:
2442 reg = R_00B030_SPI_SHADER_USER_DATA_PS_0 + SI_SGPR_CONST * 4;
2443 si_pm4_set_reg(pm4, reg, va_offset);
2444 si_pm4_set_reg(pm4, reg + 4, va_offset >> 32);
2445 si_pm4_set_state(rctx, ps_const, pm4);
2446 break;
2447
2448 default:
2449 R600_ERR("unsupported %d\n", shader);
2450 }
2451
2452 if (cb->buffer != &rbuffer->b.b)
2453 si_resource_reference(&rbuffer, NULL);
2454 }
2455
2456 /*
2457 * Vertex elements & buffers
2458 */
2459
2460 static void *si_create_vertex_elements(struct pipe_context *ctx,
2461 unsigned count,
2462 const struct pipe_vertex_element *elements)
2463 {
2464 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
2465 int i;
2466
2467 assert(count < PIPE_MAX_ATTRIBS);
2468 if (!v)
2469 return NULL;
2470
2471 v->count = count;
2472 for (i = 0; i < count; ++i) {
2473 const struct util_format_description *desc;
2474 unsigned data_format, num_format;
2475 int first_non_void;
2476
2477 desc = util_format_description(elements[i].src_format);
2478 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
2479 data_format = si_translate_vertexformat(ctx->screen, elements[i].src_format,
2480 desc, first_non_void);
2481
2482 switch (desc->channel[first_non_void].type) {
2483 case UTIL_FORMAT_TYPE_FIXED:
2484 num_format = V_008F0C_BUF_NUM_FORMAT_USCALED; /* XXX */
2485 break;
2486 case UTIL_FORMAT_TYPE_SIGNED:
2487 num_format = V_008F0C_BUF_NUM_FORMAT_SNORM;
2488 break;
2489 case UTIL_FORMAT_TYPE_UNSIGNED:
2490 num_format = V_008F0C_BUF_NUM_FORMAT_UNORM;
2491 break;
2492 case UTIL_FORMAT_TYPE_FLOAT:
2493 default:
2494 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2495 }
2496
2497 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2498 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2499 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2500 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2501 S_008F0C_NUM_FORMAT(num_format) |
2502 S_008F0C_DATA_FORMAT(data_format);
2503 }
2504 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
2505
2506 return v;
2507 }
2508
2509 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
2510 {
2511 struct r600_context *rctx = (struct r600_context *)ctx;
2512 struct si_vertex_element *v = (struct si_vertex_element*)state;
2513
2514 rctx->vertex_elements = v;
2515 }
2516
2517 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
2518 {
2519 struct r600_context *rctx = (struct r600_context *)ctx;
2520
2521 if (rctx->vertex_elements == state)
2522 rctx->vertex_elements = NULL;
2523 FREE(state);
2524 }
2525
2526 static void si_set_vertex_buffers(struct pipe_context *ctx, unsigned start_slot, unsigned count,
2527 const struct pipe_vertex_buffer *buffers)
2528 {
2529 struct r600_context *rctx = (struct r600_context *)ctx;
2530
2531 util_set_vertex_buffers_count(rctx->vertex_buffer, &rctx->nr_vertex_buffers, buffers, start_slot, count);
2532 }
2533
2534 static void si_set_index_buffer(struct pipe_context *ctx,
2535 const struct pipe_index_buffer *ib)
2536 {
2537 struct r600_context *rctx = (struct r600_context *)ctx;
2538
2539 if (ib) {
2540 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
2541 memcpy(&rctx->index_buffer, ib, sizeof(*ib));
2542 } else {
2543 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
2544 }
2545 }
2546
2547 /*
2548 * Misc
2549 */
2550 static void si_set_polygon_stipple(struct pipe_context *ctx,
2551 const struct pipe_poly_stipple *state)
2552 {
2553 }
2554
2555 static void si_texture_barrier(struct pipe_context *ctx)
2556 {
2557 struct r600_context *rctx = (struct r600_context *)ctx;
2558 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
2559
2560 si_pm4_inval_texture_cache(pm4);
2561 si_pm4_inval_fb_cache(pm4, rctx->framebuffer.nr_cbufs);
2562 si_pm4_set_state(rctx, texture_barrier, pm4);
2563 }
2564
2565 void si_init_state_functions(struct r600_context *rctx)
2566 {
2567 rctx->context.create_blend_state = si_create_blend_state;
2568 rctx->context.bind_blend_state = si_bind_blend_state;
2569 rctx->context.delete_blend_state = si_delete_blend_state;
2570 rctx->context.set_blend_color = si_set_blend_color;
2571
2572 rctx->context.create_rasterizer_state = si_create_rs_state;
2573 rctx->context.bind_rasterizer_state = si_bind_rs_state;
2574 rctx->context.delete_rasterizer_state = si_delete_rs_state;
2575
2576 rctx->context.create_depth_stencil_alpha_state = si_create_dsa_state;
2577 rctx->context.bind_depth_stencil_alpha_state = si_bind_dsa_state;
2578 rctx->context.delete_depth_stencil_alpha_state = si_delete_dsa_state;
2579 rctx->custom_dsa_flush = si_create_db_flush_dsa(rctx);
2580
2581 rctx->context.set_clip_state = si_set_clip_state;
2582 rctx->context.set_scissor_state = si_set_scissor_state;
2583 rctx->context.set_viewport_state = si_set_viewport_state;
2584 rctx->context.set_stencil_ref = si_set_pipe_stencil_ref;
2585
2586 rctx->context.set_framebuffer_state = si_set_framebuffer_state;
2587
2588 rctx->context.create_vs_state = si_create_vs_state;
2589 rctx->context.create_fs_state = si_create_fs_state;
2590 rctx->context.bind_vs_state = si_bind_vs_shader;
2591 rctx->context.bind_fs_state = si_bind_ps_shader;
2592 rctx->context.delete_vs_state = si_delete_vs_shader;
2593 rctx->context.delete_fs_state = si_delete_ps_shader;
2594
2595 rctx->context.create_sampler_state = si_create_sampler_state;
2596 rctx->context.bind_vertex_sampler_states = si_bind_vs_sampler;
2597 rctx->context.bind_fragment_sampler_states = si_bind_ps_sampler;
2598 rctx->context.delete_sampler_state = si_delete_sampler_state;
2599
2600 rctx->context.create_sampler_view = si_create_sampler_view;
2601 rctx->context.set_vertex_sampler_views = si_set_vs_sampler_view;
2602 rctx->context.set_fragment_sampler_views = si_set_ps_sampler_view;
2603 rctx->context.sampler_view_destroy = si_sampler_view_destroy;
2604
2605 rctx->context.set_sample_mask = si_set_sample_mask;
2606
2607 rctx->context.set_constant_buffer = si_set_constant_buffer;
2608
2609 rctx->context.create_vertex_elements_state = si_create_vertex_elements;
2610 rctx->context.bind_vertex_elements_state = si_bind_vertex_elements;
2611 rctx->context.delete_vertex_elements_state = si_delete_vertex_element;
2612 rctx->context.set_vertex_buffers = si_set_vertex_buffers;
2613 rctx->context.set_index_buffer = si_set_index_buffer;
2614
2615 rctx->context.create_stream_output_target = si_create_so_target;
2616 rctx->context.stream_output_target_destroy = si_so_target_destroy;
2617 rctx->context.set_stream_output_targets = si_set_so_targets;
2618
2619 rctx->context.texture_barrier = si_texture_barrier;
2620 rctx->context.set_polygon_stipple = si_set_polygon_stipple;
2621
2622 rctx->context.draw_vbo = si_draw_vbo;
2623 }
2624
2625 void si_init_config(struct r600_context *rctx)
2626 {
2627 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
2628
2629 si_cmd_context_control(pm4);
2630
2631 si_pm4_set_reg(pm4, R_028A4C_PA_SC_MODE_CNTL_1, 0x0);
2632
2633 si_pm4_set_reg(pm4, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0);
2634 si_pm4_set_reg(pm4, R_028A14_VGT_HOS_CNTL, 0x0);
2635 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0);
2636 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0);
2637 si_pm4_set_reg(pm4, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0);
2638 si_pm4_set_reg(pm4, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0);
2639 si_pm4_set_reg(pm4, R_028A28_VGT_GROUP_FIRST_DECR, 0x0);
2640 si_pm4_set_reg(pm4, R_028A2C_VGT_GROUP_DECR, 0x0);
2641 si_pm4_set_reg(pm4, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0);
2642 si_pm4_set_reg(pm4, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0);
2643 si_pm4_set_reg(pm4, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0);
2644 si_pm4_set_reg(pm4, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0);
2645 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, 0x0);
2646 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0x0);
2647 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
2648 si_pm4_set_reg(pm4, R_028B94_VGT_STRMOUT_CONFIG, 0x0);
2649 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
2650 si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM,
2651 S_028AA8_SWITCH_ON_EOP(1) |
2652 S_028AA8_PARTIAL_VS_WAVE_ON(1) |
2653 S_028AA8_PRIMGROUP_SIZE(63));
2654 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0x00000000);
2655 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
2656 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2657
2658 si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, 0);
2659 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
2660 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
2661
2662 si_pm4_set_reg(pm4, R_028804_DB_EQAA, 0x110000);
2663
2664 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
2665
2666 si_pm4_set_state(rctx, init, pm4);
2667 }