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radeonsi: use r600_resource() typecast helper
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "gfx9d.h"
27 #include "si_query.h"
28
29 #include "util/u_dual_blend.h"
30 #include "util/u_format.h"
31 #include "util/u_format_s3tc.h"
32 #include "util/u_memory.h"
33 #include "util/u_resource.h"
34 #include "util/u_upload_mgr.h"
35
36 static unsigned si_map_swizzle(unsigned swizzle)
37 {
38 switch (swizzle) {
39 case PIPE_SWIZZLE_Y:
40 return V_008F0C_SQ_SEL_Y;
41 case PIPE_SWIZZLE_Z:
42 return V_008F0C_SQ_SEL_Z;
43 case PIPE_SWIZZLE_W:
44 return V_008F0C_SQ_SEL_W;
45 case PIPE_SWIZZLE_0:
46 return V_008F0C_SQ_SEL_0;
47 case PIPE_SWIZZLE_1:
48 return V_008F0C_SQ_SEL_1;
49 default: /* PIPE_SWIZZLE_X */
50 return V_008F0C_SQ_SEL_X;
51 }
52 }
53
54 /* 12.4 fixed-point */
55 static unsigned si_pack_float_12p4(float x)
56 {
57 return x <= 0 ? 0 :
58 x >= 4096 ? 0xffff : x * 16;
59 }
60
61 /*
62 * Inferred framebuffer and blender state.
63 *
64 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
65 * if there is not enough PS outputs.
66 */
67 static void si_emit_cb_render_state(struct si_context *sctx)
68 {
69 struct radeon_winsys_cs *cs = sctx->gfx_cs;
70 struct si_state_blend *blend = sctx->queued.named.blend;
71 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
72 * but you never know. */
73 uint32_t cb_target_mask = sctx->framebuffer.colorbuf_enabled_4bit;
74 unsigned i;
75
76 if (blend)
77 cb_target_mask &= blend->cb_target_mask;
78
79 /* Avoid a hang that happens when dual source blending is enabled
80 * but there is not enough color outputs. This is undefined behavior,
81 * so disable color writes completely.
82 *
83 * Reproducible with Unigine Heaven 4.0 and drirc missing.
84 */
85 if (blend && blend->dual_src_blend &&
86 sctx->ps_shader.cso &&
87 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
88 cb_target_mask = 0;
89
90 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, cb_target_mask);
91
92 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
93 * I think we don't have to do anything between IBs.
94 */
95 if (sctx->screen->dfsm_allowed &&
96 sctx->last_cb_target_mask != cb_target_mask) {
97 sctx->last_cb_target_mask = cb_target_mask;
98
99 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
100 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
101 }
102
103 if (sctx->chip_class >= VI) {
104 /* DCC MSAA workaround for blending.
105 * Alternatively, we can set CB_COLORi_DCC_CONTROL.OVERWRITE_-
106 * COMBINER_DISABLE, but that would be more complicated.
107 */
108 bool oc_disable = (sctx->chip_class == VI ||
109 sctx->chip_class == GFX9) &&
110 blend &&
111 blend->blend_enable_4bit & cb_target_mask &&
112 sctx->framebuffer.nr_samples >= 2;
113
114 radeon_set_context_reg(cs, R_028424_CB_DCC_CONTROL,
115 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
116 S_028424_OVERWRITE_COMBINER_WATERMARK(4) |
117 S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable));
118 }
119
120 /* RB+ register settings. */
121 if (sctx->screen->rbplus_allowed) {
122 unsigned spi_shader_col_format =
123 sctx->ps_shader.cso ?
124 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format : 0;
125 unsigned sx_ps_downconvert = 0;
126 unsigned sx_blend_opt_epsilon = 0;
127 unsigned sx_blend_opt_control = 0;
128
129 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
130 struct r600_surface *surf =
131 (struct r600_surface*)sctx->framebuffer.state.cbufs[i];
132 unsigned format, swap, spi_format, colormask;
133 bool has_alpha, has_rgb;
134
135 if (!surf)
136 continue;
137
138 format = G_028C70_FORMAT(surf->cb_color_info);
139 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
140 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
141 colormask = (cb_target_mask >> (i * 4)) & 0xf;
142
143 /* Set if RGB and A are present. */
144 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
145
146 if (format == V_028C70_COLOR_8 ||
147 format == V_028C70_COLOR_16 ||
148 format == V_028C70_COLOR_32)
149 has_rgb = !has_alpha;
150 else
151 has_rgb = true;
152
153 /* Check the colormask and export format. */
154 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
155 has_rgb = false;
156 if (!(colormask & PIPE_MASK_A))
157 has_alpha = false;
158
159 if (spi_format == V_028714_SPI_SHADER_ZERO) {
160 has_rgb = false;
161 has_alpha = false;
162 }
163
164 /* Disable value checking for disabled channels. */
165 if (!has_rgb)
166 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
167 if (!has_alpha)
168 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
169
170 /* Enable down-conversion for 32bpp and smaller formats. */
171 switch (format) {
172 case V_028C70_COLOR_8:
173 case V_028C70_COLOR_8_8:
174 case V_028C70_COLOR_8_8_8_8:
175 /* For 1 and 2-channel formats, use the superset thereof. */
176 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
177 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
178 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
179 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
180 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
181 }
182 break;
183
184 case V_028C70_COLOR_5_6_5:
185 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
186 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
187 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
188 }
189 break;
190
191 case V_028C70_COLOR_1_5_5_5:
192 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
193 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
194 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
195 }
196 break;
197
198 case V_028C70_COLOR_4_4_4_4:
199 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
200 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
201 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
202 }
203 break;
204
205 case V_028C70_COLOR_32:
206 if (swap == V_028C70_SWAP_STD &&
207 spi_format == V_028714_SPI_SHADER_32_R)
208 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
209 else if (swap == V_028C70_SWAP_ALT_REV &&
210 spi_format == V_028714_SPI_SHADER_32_AR)
211 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
212 break;
213
214 case V_028C70_COLOR_16:
215 case V_028C70_COLOR_16_16:
216 /* For 1-channel formats, use the superset thereof. */
217 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
218 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
219 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
220 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
221 if (swap == V_028C70_SWAP_STD ||
222 swap == V_028C70_SWAP_STD_REV)
223 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
224 else
225 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
226 }
227 break;
228
229 case V_028C70_COLOR_10_11_11:
230 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
231 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
232 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
233 }
234 break;
235
236 case V_028C70_COLOR_2_10_10_10:
237 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
238 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
239 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
240 }
241 break;
242 }
243 }
244
245 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
246 radeon_emit(cs, sx_ps_downconvert); /* R_028754_SX_PS_DOWNCONVERT */
247 radeon_emit(cs, sx_blend_opt_epsilon); /* R_028758_SX_BLEND_OPT_EPSILON */
248 radeon_emit(cs, sx_blend_opt_control); /* R_02875C_SX_BLEND_OPT_CONTROL */
249 }
250 }
251
252 /*
253 * Blender functions
254 */
255
256 static uint32_t si_translate_blend_function(int blend_func)
257 {
258 switch (blend_func) {
259 case PIPE_BLEND_ADD:
260 return V_028780_COMB_DST_PLUS_SRC;
261 case PIPE_BLEND_SUBTRACT:
262 return V_028780_COMB_SRC_MINUS_DST;
263 case PIPE_BLEND_REVERSE_SUBTRACT:
264 return V_028780_COMB_DST_MINUS_SRC;
265 case PIPE_BLEND_MIN:
266 return V_028780_COMB_MIN_DST_SRC;
267 case PIPE_BLEND_MAX:
268 return V_028780_COMB_MAX_DST_SRC;
269 default:
270 PRINT_ERR("Unknown blend function %d\n", blend_func);
271 assert(0);
272 break;
273 }
274 return 0;
275 }
276
277 static uint32_t si_translate_blend_factor(int blend_fact)
278 {
279 switch (blend_fact) {
280 case PIPE_BLENDFACTOR_ONE:
281 return V_028780_BLEND_ONE;
282 case PIPE_BLENDFACTOR_SRC_COLOR:
283 return V_028780_BLEND_SRC_COLOR;
284 case PIPE_BLENDFACTOR_SRC_ALPHA:
285 return V_028780_BLEND_SRC_ALPHA;
286 case PIPE_BLENDFACTOR_DST_ALPHA:
287 return V_028780_BLEND_DST_ALPHA;
288 case PIPE_BLENDFACTOR_DST_COLOR:
289 return V_028780_BLEND_DST_COLOR;
290 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
291 return V_028780_BLEND_SRC_ALPHA_SATURATE;
292 case PIPE_BLENDFACTOR_CONST_COLOR:
293 return V_028780_BLEND_CONSTANT_COLOR;
294 case PIPE_BLENDFACTOR_CONST_ALPHA:
295 return V_028780_BLEND_CONSTANT_ALPHA;
296 case PIPE_BLENDFACTOR_ZERO:
297 return V_028780_BLEND_ZERO;
298 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
299 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
300 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
301 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
302 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
303 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
304 case PIPE_BLENDFACTOR_INV_DST_COLOR:
305 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
306 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
307 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
308 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
309 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
310 case PIPE_BLENDFACTOR_SRC1_COLOR:
311 return V_028780_BLEND_SRC1_COLOR;
312 case PIPE_BLENDFACTOR_SRC1_ALPHA:
313 return V_028780_BLEND_SRC1_ALPHA;
314 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
315 return V_028780_BLEND_INV_SRC1_COLOR;
316 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
317 return V_028780_BLEND_INV_SRC1_ALPHA;
318 default:
319 PRINT_ERR("Bad blend factor %d not supported!\n", blend_fact);
320 assert(0);
321 break;
322 }
323 return 0;
324 }
325
326 static uint32_t si_translate_blend_opt_function(int blend_func)
327 {
328 switch (blend_func) {
329 case PIPE_BLEND_ADD:
330 return V_028760_OPT_COMB_ADD;
331 case PIPE_BLEND_SUBTRACT:
332 return V_028760_OPT_COMB_SUBTRACT;
333 case PIPE_BLEND_REVERSE_SUBTRACT:
334 return V_028760_OPT_COMB_REVSUBTRACT;
335 case PIPE_BLEND_MIN:
336 return V_028760_OPT_COMB_MIN;
337 case PIPE_BLEND_MAX:
338 return V_028760_OPT_COMB_MAX;
339 default:
340 return V_028760_OPT_COMB_BLEND_DISABLED;
341 }
342 }
343
344 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
345 {
346 switch (blend_fact) {
347 case PIPE_BLENDFACTOR_ZERO:
348 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
349 case PIPE_BLENDFACTOR_ONE:
350 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
351 case PIPE_BLENDFACTOR_SRC_COLOR:
352 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
353 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
354 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
355 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
356 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
357 case PIPE_BLENDFACTOR_SRC_ALPHA:
358 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
359 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
360 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
361 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
362 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
363 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
364 default:
365 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
366 }
367 }
368
369 static void si_blend_check_commutativity(struct si_screen *sscreen,
370 struct si_state_blend *blend,
371 enum pipe_blend_func func,
372 enum pipe_blendfactor src,
373 enum pipe_blendfactor dst,
374 unsigned chanmask)
375 {
376 /* Src factor is allowed when it does not depend on Dst */
377 static const uint32_t src_allowed =
378 (1u << PIPE_BLENDFACTOR_ONE) |
379 (1u << PIPE_BLENDFACTOR_SRC_COLOR) |
380 (1u << PIPE_BLENDFACTOR_SRC_ALPHA) |
381 (1u << PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE) |
382 (1u << PIPE_BLENDFACTOR_CONST_COLOR) |
383 (1u << PIPE_BLENDFACTOR_CONST_ALPHA) |
384 (1u << PIPE_BLENDFACTOR_SRC1_COLOR) |
385 (1u << PIPE_BLENDFACTOR_SRC1_ALPHA) |
386 (1u << PIPE_BLENDFACTOR_ZERO) |
387 (1u << PIPE_BLENDFACTOR_INV_SRC_COLOR) |
388 (1u << PIPE_BLENDFACTOR_INV_SRC_ALPHA) |
389 (1u << PIPE_BLENDFACTOR_INV_CONST_COLOR) |
390 (1u << PIPE_BLENDFACTOR_INV_CONST_ALPHA) |
391 (1u << PIPE_BLENDFACTOR_INV_SRC1_COLOR) |
392 (1u << PIPE_BLENDFACTOR_INV_SRC1_ALPHA);
393
394 if (dst == PIPE_BLENDFACTOR_ONE &&
395 (src_allowed & (1u << src))) {
396 /* Addition is commutative, but floating point addition isn't
397 * associative: subtle changes can be introduced via different
398 * rounding.
399 *
400 * Out-of-order is also non-deterministic, which means that
401 * this breaks OpenGL invariance requirements. So only enable
402 * out-of-order additive blending if explicitly allowed by a
403 * setting.
404 */
405 if (func == PIPE_BLEND_MAX || func == PIPE_BLEND_MIN ||
406 (func == PIPE_BLEND_ADD && sscreen->commutative_blend_add))
407 blend->commutative_4bit |= chanmask;
408 }
409 }
410
411 /**
412 * Get rid of DST in the blend factors by commuting the operands:
413 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
414 */
415 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
416 unsigned *dst_factor, unsigned expected_dst,
417 unsigned replacement_src)
418 {
419 if (*src_factor == expected_dst &&
420 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
421 *src_factor = PIPE_BLENDFACTOR_ZERO;
422 *dst_factor = replacement_src;
423
424 /* Commuting the operands requires reversing subtractions. */
425 if (*func == PIPE_BLEND_SUBTRACT)
426 *func = PIPE_BLEND_REVERSE_SUBTRACT;
427 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
428 *func = PIPE_BLEND_SUBTRACT;
429 }
430 }
431
432 static bool si_blend_factor_uses_dst(unsigned factor)
433 {
434 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
435 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
436 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
437 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
438 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
439 }
440
441 static void *si_create_blend_state_mode(struct pipe_context *ctx,
442 const struct pipe_blend_state *state,
443 unsigned mode)
444 {
445 struct si_context *sctx = (struct si_context*)ctx;
446 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
447 struct si_pm4_state *pm4 = &blend->pm4;
448 uint32_t sx_mrt_blend_opt[8] = {0};
449 uint32_t color_control = 0;
450
451 if (!blend)
452 return NULL;
453
454 blend->alpha_to_coverage = state->alpha_to_coverage;
455 blend->alpha_to_one = state->alpha_to_one;
456 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
457 blend->logicop_enable = state->logicop_enable;
458
459 if (state->logicop_enable) {
460 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
461 } else {
462 color_control |= S_028808_ROP3(0xcc);
463 }
464
465 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
466 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
467 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
468 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
469 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
470 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
471
472 if (state->alpha_to_coverage)
473 blend->need_src_alpha_4bit |= 0xf;
474
475 blend->cb_target_mask = 0;
476 blend->cb_target_enabled_4bit = 0;
477
478 for (int i = 0; i < 8; i++) {
479 /* state->rt entries > 0 only written if independent blending */
480 const int j = state->independent_blend_enable ? i : 0;
481
482 unsigned eqRGB = state->rt[j].rgb_func;
483 unsigned srcRGB = state->rt[j].rgb_src_factor;
484 unsigned dstRGB = state->rt[j].rgb_dst_factor;
485 unsigned eqA = state->rt[j].alpha_func;
486 unsigned srcA = state->rt[j].alpha_src_factor;
487 unsigned dstA = state->rt[j].alpha_dst_factor;
488
489 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
490 unsigned blend_cntl = 0;
491
492 sx_mrt_blend_opt[i] =
493 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
494 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
495
496 /* Only set dual source blending for MRT0 to avoid a hang. */
497 if (i >= 1 && blend->dual_src_blend) {
498 /* Vulkan does this for dual source blending. */
499 if (i == 1)
500 blend_cntl |= S_028780_ENABLE(1);
501
502 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
503 continue;
504 }
505
506 /* Only addition and subtraction equations are supported with
507 * dual source blending.
508 */
509 if (blend->dual_src_blend &&
510 (eqRGB == PIPE_BLEND_MIN || eqRGB == PIPE_BLEND_MAX ||
511 eqA == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MAX)) {
512 assert(!"Unsupported equation for dual source blending");
513 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
514 continue;
515 }
516
517 /* cb_render_state will disable unused ones */
518 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
519 if (state->rt[j].colormask)
520 blend->cb_target_enabled_4bit |= 0xf << (4 * i);
521
522 if (!state->rt[j].colormask || !state->rt[j].blend_enable) {
523 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
524 continue;
525 }
526
527 si_blend_check_commutativity(sctx->screen, blend,
528 eqRGB, srcRGB, dstRGB, 0x7 << (4 * i));
529 si_blend_check_commutativity(sctx->screen, blend,
530 eqA, srcA, dstA, 0x8 << (4 * i));
531
532 /* Blending optimizations for RB+.
533 * These transformations don't change the behavior.
534 *
535 * First, get rid of DST in the blend factors:
536 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
537 */
538 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
539 PIPE_BLENDFACTOR_DST_COLOR,
540 PIPE_BLENDFACTOR_SRC_COLOR);
541 si_blend_remove_dst(&eqA, &srcA, &dstA,
542 PIPE_BLENDFACTOR_DST_COLOR,
543 PIPE_BLENDFACTOR_SRC_COLOR);
544 si_blend_remove_dst(&eqA, &srcA, &dstA,
545 PIPE_BLENDFACTOR_DST_ALPHA,
546 PIPE_BLENDFACTOR_SRC_ALPHA);
547
548 /* Look up the ideal settings from tables. */
549 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
550 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
551 srcA_opt = si_translate_blend_opt_factor(srcA, true);
552 dstA_opt = si_translate_blend_opt_factor(dstA, true);
553
554 /* Handle interdependencies. */
555 if (si_blend_factor_uses_dst(srcRGB))
556 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
557 if (si_blend_factor_uses_dst(srcA))
558 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
559
560 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
561 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
562 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
563 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
564 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
565
566 /* Set the final value. */
567 sx_mrt_blend_opt[i] =
568 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
569 S_028760_COLOR_DST_OPT(dstRGB_opt) |
570 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
571 S_028760_ALPHA_SRC_OPT(srcA_opt) |
572 S_028760_ALPHA_DST_OPT(dstA_opt) |
573 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
574
575 /* Set blend state. */
576 blend_cntl |= S_028780_ENABLE(1);
577 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
578 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
579 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
580
581 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
582 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
583 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
584 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
585 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
586 }
587 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
588
589 blend->blend_enable_4bit |= 0xfu << (i * 4);
590
591 /* This is only important for formats without alpha. */
592 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
593 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
594 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
595 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
596 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
597 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
598 blend->need_src_alpha_4bit |= 0xfu << (i * 4);
599 }
600
601 if (blend->cb_target_mask) {
602 color_control |= S_028808_MODE(mode);
603 } else {
604 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
605 }
606
607 if (sctx->screen->rbplus_allowed) {
608 /* Disable RB+ blend optimizations for dual source blending.
609 * Vulkan does this.
610 */
611 if (blend->dual_src_blend) {
612 for (int i = 0; i < 8; i++) {
613 sx_mrt_blend_opt[i] =
614 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
615 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
616 }
617 }
618
619 for (int i = 0; i < 8; i++)
620 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
621 sx_mrt_blend_opt[i]);
622
623 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
624 if (blend->dual_src_blend || state->logicop_enable ||
625 mode == V_028808_CB_RESOLVE)
626 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
627 }
628
629 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
630 return blend;
631 }
632
633 static void *si_create_blend_state(struct pipe_context *ctx,
634 const struct pipe_blend_state *state)
635 {
636 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
637 }
638
639 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
640 {
641 struct si_context *sctx = (struct si_context *)ctx;
642 struct si_state_blend *old_blend = sctx->queued.named.blend;
643 struct si_state_blend *blend = (struct si_state_blend *)state;
644
645 if (!state)
646 return;
647
648 si_pm4_bind_state(sctx, blend, state);
649
650 if (!old_blend ||
651 old_blend->cb_target_mask != blend->cb_target_mask ||
652 old_blend->dual_src_blend != blend->dual_src_blend ||
653 (old_blend->blend_enable_4bit != blend->blend_enable_4bit &&
654 sctx->framebuffer.nr_samples >= 2 &&
655 sctx->screen->dcc_msaa_allowed))
656 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
657
658 if (!old_blend ||
659 old_blend->cb_target_mask != blend->cb_target_mask ||
660 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
661 old_blend->alpha_to_one != blend->alpha_to_one ||
662 old_blend->dual_src_blend != blend->dual_src_blend ||
663 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
664 old_blend->need_src_alpha_4bit != blend->need_src_alpha_4bit)
665 sctx->do_update_shaders = true;
666
667 if (sctx->screen->dpbb_allowed &&
668 (!old_blend ||
669 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
670 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
671 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit))
672 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
673
674 if (sctx->screen->has_out_of_order_rast &&
675 (!old_blend ||
676 (old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
677 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit ||
678 old_blend->commutative_4bit != blend->commutative_4bit ||
679 old_blend->logicop_enable != blend->logicop_enable)))
680 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
681 }
682
683 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
684 {
685 struct si_context *sctx = (struct si_context *)ctx;
686 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
687 }
688
689 static void si_set_blend_color(struct pipe_context *ctx,
690 const struct pipe_blend_color *state)
691 {
692 struct si_context *sctx = (struct si_context *)ctx;
693 static const struct pipe_blend_color zeros;
694
695 sctx->blend_color.state = *state;
696 sctx->blend_color.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
697 si_mark_atom_dirty(sctx, &sctx->atoms.s.blend_color);
698 }
699
700 static void si_emit_blend_color(struct si_context *sctx)
701 {
702 struct radeon_winsys_cs *cs = sctx->gfx_cs;
703
704 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
705 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
706 }
707
708 /*
709 * Clipping
710 */
711
712 static void si_set_clip_state(struct pipe_context *ctx,
713 const struct pipe_clip_state *state)
714 {
715 struct si_context *sctx = (struct si_context *)ctx;
716 struct pipe_constant_buffer cb;
717 static const struct pipe_clip_state zeros;
718
719 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
720 return;
721
722 sctx->clip_state.state = *state;
723 sctx->clip_state.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
724 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_state);
725
726 cb.buffer = NULL;
727 cb.user_buffer = state->ucp;
728 cb.buffer_offset = 0;
729 cb.buffer_size = 4*4*8;
730 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
731 pipe_resource_reference(&cb.buffer, NULL);
732 }
733
734 static void si_emit_clip_state(struct si_context *sctx)
735 {
736 struct radeon_winsys_cs *cs = sctx->gfx_cs;
737
738 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
739 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
740 }
741
742 static void si_emit_clip_regs(struct si_context *sctx)
743 {
744 struct radeon_winsys_cs *cs = sctx->gfx_cs;
745 struct si_shader *vs = si_get_vs_state(sctx);
746 struct si_shader_selector *vs_sel = vs->selector;
747 struct tgsi_shader_info *info = &vs_sel->info;
748 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
749 unsigned window_space =
750 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
751 unsigned clipdist_mask = vs_sel->clipdist_mask;
752 unsigned ucp_mask = clipdist_mask ? 0 : rs->clip_plane_enable & SIX_BITS;
753 unsigned culldist_mask = vs_sel->culldist_mask;
754 unsigned total_mask;
755
756 if (vs->key.opt.clip_disable) {
757 assert(!info->culldist_writemask);
758 clipdist_mask = 0;
759 culldist_mask = 0;
760 }
761 total_mask = clipdist_mask | culldist_mask;
762
763 /* Clip distances on points have no effect, so need to be implemented
764 * as cull distances. This applies for the clipvertex case as well.
765 *
766 * Setting this for primitives other than points should have no adverse
767 * effects.
768 */
769 clipdist_mask &= rs->clip_plane_enable;
770 culldist_mask |= clipdist_mask;
771
772 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
773 vs_sel->pa_cl_vs_out_cntl |
774 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0F) != 0) |
775 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xF0) != 0) |
776 clipdist_mask | (culldist_mask << 8));
777 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
778 rs->pa_cl_clip_cntl |
779 ucp_mask |
780 S_028810_CLIP_DISABLE(window_space));
781 }
782
783 /*
784 * inferred state between framebuffer and rasterizer
785 */
786 static void si_update_poly_offset_state(struct si_context *sctx)
787 {
788 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
789
790 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf) {
791 si_pm4_bind_state(sctx, poly_offset, NULL);
792 return;
793 }
794
795 /* Use the user format, not db_render_format, so that the polygon
796 * offset behaves as expected by applications.
797 */
798 switch (sctx->framebuffer.state.zsbuf->texture->format) {
799 case PIPE_FORMAT_Z16_UNORM:
800 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
801 break;
802 default: /* 24-bit */
803 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
804 break;
805 case PIPE_FORMAT_Z32_FLOAT:
806 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
807 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
808 break;
809 }
810 }
811
812 /*
813 * Rasterizer
814 */
815
816 static uint32_t si_translate_fill(uint32_t func)
817 {
818 switch(func) {
819 case PIPE_POLYGON_MODE_FILL:
820 return V_028814_X_DRAW_TRIANGLES;
821 case PIPE_POLYGON_MODE_LINE:
822 return V_028814_X_DRAW_LINES;
823 case PIPE_POLYGON_MODE_POINT:
824 return V_028814_X_DRAW_POINTS;
825 default:
826 assert(0);
827 return V_028814_X_DRAW_POINTS;
828 }
829 }
830
831 static void *si_create_rs_state(struct pipe_context *ctx,
832 const struct pipe_rasterizer_state *state)
833 {
834 struct si_screen *sscreen = ((struct si_context *)ctx)->screen;
835 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
836 struct si_pm4_state *pm4 = &rs->pm4;
837 unsigned tmp, i;
838 float psize_min, psize_max;
839
840 if (!rs) {
841 return NULL;
842 }
843
844 rs->scissor_enable = state->scissor;
845 rs->clip_halfz = state->clip_halfz;
846 rs->two_side = state->light_twoside;
847 rs->multisample_enable = state->multisample;
848 rs->force_persample_interp = state->force_persample_interp;
849 rs->clip_plane_enable = state->clip_plane_enable;
850 rs->line_stipple_enable = state->line_stipple_enable;
851 rs->poly_stipple_enable = state->poly_stipple_enable;
852 rs->line_smooth = state->line_smooth;
853 rs->line_width = state->line_width;
854 rs->poly_smooth = state->poly_smooth;
855 rs->uses_poly_offset = state->offset_point || state->offset_line ||
856 state->offset_tri;
857 rs->clamp_fragment_color = state->clamp_fragment_color;
858 rs->clamp_vertex_color = state->clamp_vertex_color;
859 rs->flatshade = state->flatshade;
860 rs->sprite_coord_enable = state->sprite_coord_enable;
861 rs->rasterizer_discard = state->rasterizer_discard;
862 rs->pa_sc_line_stipple = state->line_stipple_enable ?
863 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
864 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
865 rs->pa_cl_clip_cntl =
866 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
867 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
868 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
869 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
870 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
871
872 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
873 S_0286D4_FLAT_SHADE_ENA(1) |
874 S_0286D4_PNT_SPRITE_ENA(state->point_quad_rasterization) |
875 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
876 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
877 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
878 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
879 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
880
881 /* point size 12.4 fixed point */
882 tmp = (unsigned)(state->point_size * 8.0);
883 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
884
885 if (state->point_size_per_vertex) {
886 psize_min = util_get_min_point_size(state);
887 psize_max = 8192;
888 } else {
889 /* Force the point size to be as if the vertex output was disabled. */
890 psize_min = state->point_size;
891 psize_max = state->point_size;
892 }
893 rs->max_point_size = psize_max;
894
895 /* Divide by two, because 0.5 = 1 pixel. */
896 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
897 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
898 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
899
900 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL,
901 S_028A08_WIDTH(si_pack_float_12p4(state->line_width/2)));
902 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
903 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
904 S_028A48_MSAA_ENABLE(state->multisample ||
905 state->poly_smooth ||
906 state->line_smooth) |
907 S_028A48_VPORT_SCISSOR_ENABLE(1) |
908 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen->info.chip_class >= GFX9));
909
910 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
911 S_028BE4_PIX_CENTER(state->half_pixel_center) |
912 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
913
914 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
915 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
916 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
917 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
918 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
919 S_028814_FACE(!state->front_ccw) |
920 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
921 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
922 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
923 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
924 state->fill_back != PIPE_POLYGON_MODE_FILL) |
925 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
926 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
927
928 if (!rs->uses_poly_offset)
929 return rs;
930
931 rs->pm4_poly_offset = CALLOC(3, sizeof(struct si_pm4_state));
932 if (!rs->pm4_poly_offset) {
933 FREE(rs);
934 return NULL;
935 }
936
937 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
938 for (i = 0; i < 3; i++) {
939 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
940 float offset_units = state->offset_units;
941 float offset_scale = state->offset_scale * 16.0f;
942 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
943
944 if (!state->offset_units_unscaled) {
945 switch (i) {
946 case 0: /* 16-bit zbuffer */
947 offset_units *= 4.0f;
948 pa_su_poly_offset_db_fmt_cntl =
949 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
950 break;
951 case 1: /* 24-bit zbuffer */
952 offset_units *= 2.0f;
953 pa_su_poly_offset_db_fmt_cntl =
954 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
955 break;
956 case 2: /* 32-bit zbuffer */
957 offset_units *= 1.0f;
958 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
959 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
960 break;
961 }
962 }
963
964 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
965 fui(offset_scale));
966 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
967 fui(offset_units));
968 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
969 fui(offset_scale));
970 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
971 fui(offset_units));
972 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
973 pa_su_poly_offset_db_fmt_cntl);
974 }
975
976 return rs;
977 }
978
979 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
980 {
981 struct si_context *sctx = (struct si_context *)ctx;
982 struct si_state_rasterizer *old_rs =
983 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
984 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
985
986 if (!state)
987 return;
988
989 if (!old_rs || old_rs->multisample_enable != rs->multisample_enable) {
990 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
991
992 /* Update the small primitive filter workaround if necessary. */
993 if (sctx->screen->has_msaa_sample_loc_bug &&
994 sctx->framebuffer.nr_samples > 1)
995 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
996 }
997
998 sctx->current_vs_state &= C_VS_STATE_CLAMP_VERTEX_COLOR;
999 sctx->current_vs_state |= S_VS_STATE_CLAMP_VERTEX_COLOR(rs->clamp_vertex_color);
1000
1001 si_pm4_bind_state(sctx, rasterizer, rs);
1002 si_update_poly_offset_state(sctx);
1003
1004 if (!old_rs ||
1005 (old_rs->scissor_enable != rs->scissor_enable ||
1006 old_rs->line_width != rs->line_width ||
1007 old_rs->max_point_size != rs->max_point_size)) {
1008 sctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
1009 si_mark_atom_dirty(sctx, &sctx->atoms.s.scissors);
1010 }
1011
1012 if (!old_rs ||
1013 old_rs->clip_halfz != rs->clip_halfz) {
1014 sctx->viewports.depth_range_dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
1015 si_mark_atom_dirty(sctx, &sctx->atoms.s.viewports);
1016 }
1017
1018 if (!old_rs ||
1019 old_rs->clip_plane_enable != rs->clip_plane_enable ||
1020 old_rs->pa_cl_clip_cntl != rs->pa_cl_clip_cntl)
1021 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
1022
1023 sctx->ia_multi_vgt_param_key.u.line_stipple_enabled =
1024 rs->line_stipple_enable;
1025
1026 if (!old_rs ||
1027 old_rs->clip_plane_enable != rs->clip_plane_enable ||
1028 old_rs->rasterizer_discard != rs->rasterizer_discard ||
1029 old_rs->sprite_coord_enable != rs->sprite_coord_enable ||
1030 old_rs->flatshade != rs->flatshade ||
1031 old_rs->two_side != rs->two_side ||
1032 old_rs->multisample_enable != rs->multisample_enable ||
1033 old_rs->poly_stipple_enable != rs->poly_stipple_enable ||
1034 old_rs->poly_smooth != rs->poly_smooth ||
1035 old_rs->line_smooth != rs->line_smooth ||
1036 old_rs->clamp_fragment_color != rs->clamp_fragment_color ||
1037 old_rs->force_persample_interp != rs->force_persample_interp)
1038 sctx->do_update_shaders = true;
1039 }
1040
1041 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
1042 {
1043 struct si_context *sctx = (struct si_context *)ctx;
1044 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
1045
1046 if (sctx->queued.named.rasterizer == state)
1047 si_pm4_bind_state(sctx, poly_offset, NULL);
1048
1049 FREE(rs->pm4_poly_offset);
1050 si_pm4_delete_state(sctx, rasterizer, rs);
1051 }
1052
1053 /*
1054 * infeered state between dsa and stencil ref
1055 */
1056 static void si_emit_stencil_ref(struct si_context *sctx)
1057 {
1058 struct radeon_winsys_cs *cs = sctx->gfx_cs;
1059 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
1060 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
1061
1062 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
1063 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
1064 S_028430_STENCILMASK(dsa->valuemask[0]) |
1065 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
1066 S_028430_STENCILOPVAL(1));
1067 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
1068 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
1069 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
1070 S_028434_STENCILOPVAL_BF(1));
1071 }
1072
1073 static void si_set_stencil_ref(struct pipe_context *ctx,
1074 const struct pipe_stencil_ref *state)
1075 {
1076 struct si_context *sctx = (struct si_context *)ctx;
1077
1078 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
1079 return;
1080
1081 sctx->stencil_ref.state = *state;
1082 si_mark_atom_dirty(sctx, &sctx->atoms.s.stencil_ref);
1083 }
1084
1085
1086 /*
1087 * DSA
1088 */
1089
1090 static uint32_t si_translate_stencil_op(int s_op)
1091 {
1092 switch (s_op) {
1093 case PIPE_STENCIL_OP_KEEP:
1094 return V_02842C_STENCIL_KEEP;
1095 case PIPE_STENCIL_OP_ZERO:
1096 return V_02842C_STENCIL_ZERO;
1097 case PIPE_STENCIL_OP_REPLACE:
1098 return V_02842C_STENCIL_REPLACE_TEST;
1099 case PIPE_STENCIL_OP_INCR:
1100 return V_02842C_STENCIL_ADD_CLAMP;
1101 case PIPE_STENCIL_OP_DECR:
1102 return V_02842C_STENCIL_SUB_CLAMP;
1103 case PIPE_STENCIL_OP_INCR_WRAP:
1104 return V_02842C_STENCIL_ADD_WRAP;
1105 case PIPE_STENCIL_OP_DECR_WRAP:
1106 return V_02842C_STENCIL_SUB_WRAP;
1107 case PIPE_STENCIL_OP_INVERT:
1108 return V_02842C_STENCIL_INVERT;
1109 default:
1110 PRINT_ERR("Unknown stencil op %d", s_op);
1111 assert(0);
1112 break;
1113 }
1114 return 0;
1115 }
1116
1117 static bool si_dsa_writes_stencil(const struct pipe_stencil_state *s)
1118 {
1119 return s->enabled && s->writemask &&
1120 (s->fail_op != PIPE_STENCIL_OP_KEEP ||
1121 s->zfail_op != PIPE_STENCIL_OP_KEEP ||
1122 s->zpass_op != PIPE_STENCIL_OP_KEEP);
1123 }
1124
1125 static bool si_order_invariant_stencil_op(enum pipe_stencil_op op)
1126 {
1127 /* REPLACE is normally order invariant, except when the stencil
1128 * reference value is written by the fragment shader. Tracking this
1129 * interaction does not seem worth the effort, so be conservative. */
1130 return op != PIPE_STENCIL_OP_INCR &&
1131 op != PIPE_STENCIL_OP_DECR &&
1132 op != PIPE_STENCIL_OP_REPLACE;
1133 }
1134
1135 /* Compute whether, assuming Z writes are disabled, this stencil state is order
1136 * invariant in the sense that the set of passing fragments as well as the
1137 * final stencil buffer result does not depend on the order of fragments. */
1138 static bool si_order_invariant_stencil_state(const struct pipe_stencil_state *state)
1139 {
1140 return !state->enabled || !state->writemask ||
1141 /* The following assumes that Z writes are disabled. */
1142 (state->func == PIPE_FUNC_ALWAYS &&
1143 si_order_invariant_stencil_op(state->zpass_op) &&
1144 si_order_invariant_stencil_op(state->zfail_op)) ||
1145 (state->func == PIPE_FUNC_NEVER &&
1146 si_order_invariant_stencil_op(state->fail_op));
1147 }
1148
1149 static void *si_create_dsa_state(struct pipe_context *ctx,
1150 const struct pipe_depth_stencil_alpha_state *state)
1151 {
1152 struct si_context *sctx = (struct si_context *)ctx;
1153 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
1154 struct si_pm4_state *pm4 = &dsa->pm4;
1155 unsigned db_depth_control;
1156 uint32_t db_stencil_control = 0;
1157
1158 if (!dsa) {
1159 return NULL;
1160 }
1161
1162 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
1163 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
1164 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
1165 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
1166
1167 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
1168 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
1169 S_028800_ZFUNC(state->depth.func) |
1170 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
1171
1172 /* stencil */
1173 if (state->stencil[0].enabled) {
1174 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1175 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
1176 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
1177 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
1178 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
1179
1180 if (state->stencil[1].enabled) {
1181 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1182 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1183 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
1184 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
1185 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
1186 }
1187 }
1188
1189 /* alpha */
1190 if (state->alpha.enabled) {
1191 dsa->alpha_func = state->alpha.func;
1192
1193 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1194 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
1195 } else {
1196 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1197 }
1198
1199 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1200 if (state->stencil[0].enabled)
1201 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1202 if (state->depth.bounds_test) {
1203 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1204 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1205 }
1206
1207 dsa->depth_enabled = state->depth.enabled;
1208 dsa->depth_write_enabled = state->depth.enabled &&
1209 state->depth.writemask;
1210 dsa->stencil_enabled = state->stencil[0].enabled;
1211 dsa->stencil_write_enabled = state->stencil[0].enabled &&
1212 (si_dsa_writes_stencil(&state->stencil[0]) ||
1213 si_dsa_writes_stencil(&state->stencil[1]));
1214 dsa->db_can_write = dsa->depth_write_enabled ||
1215 dsa->stencil_write_enabled;
1216
1217 bool zfunc_is_ordered =
1218 state->depth.func == PIPE_FUNC_NEVER ||
1219 state->depth.func == PIPE_FUNC_LESS ||
1220 state->depth.func == PIPE_FUNC_LEQUAL ||
1221 state->depth.func == PIPE_FUNC_GREATER ||
1222 state->depth.func == PIPE_FUNC_GEQUAL;
1223
1224 bool nozwrite_and_order_invariant_stencil =
1225 !dsa->db_can_write ||
1226 (!dsa->depth_write_enabled &&
1227 si_order_invariant_stencil_state(&state->stencil[0]) &&
1228 si_order_invariant_stencil_state(&state->stencil[1]));
1229
1230 dsa->order_invariance[1].zs =
1231 nozwrite_and_order_invariant_stencil ||
1232 (!dsa->stencil_write_enabled && zfunc_is_ordered);
1233 dsa->order_invariance[0].zs = !dsa->depth_write_enabled || zfunc_is_ordered;
1234
1235 dsa->order_invariance[1].pass_set =
1236 nozwrite_and_order_invariant_stencil ||
1237 (!dsa->stencil_write_enabled &&
1238 (state->depth.func == PIPE_FUNC_ALWAYS ||
1239 state->depth.func == PIPE_FUNC_NEVER));
1240 dsa->order_invariance[0].pass_set =
1241 !dsa->depth_write_enabled ||
1242 (state->depth.func == PIPE_FUNC_ALWAYS ||
1243 state->depth.func == PIPE_FUNC_NEVER);
1244
1245 dsa->order_invariance[1].pass_last =
1246 sctx->screen->assume_no_z_fights &&
1247 !dsa->stencil_write_enabled &&
1248 dsa->depth_write_enabled && zfunc_is_ordered;
1249 dsa->order_invariance[0].pass_last =
1250 sctx->screen->assume_no_z_fights &&
1251 dsa->depth_write_enabled && zfunc_is_ordered;
1252
1253 return dsa;
1254 }
1255
1256 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1257 {
1258 struct si_context *sctx = (struct si_context *)ctx;
1259 struct si_state_dsa *old_dsa = sctx->queued.named.dsa;
1260 struct si_state_dsa *dsa = state;
1261
1262 if (!state)
1263 return;
1264
1265 si_pm4_bind_state(sctx, dsa, dsa);
1266
1267 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1268 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1269 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1270 si_mark_atom_dirty(sctx, &sctx->atoms.s.stencil_ref);
1271 }
1272
1273 if (!old_dsa || old_dsa->alpha_func != dsa->alpha_func)
1274 sctx->do_update_shaders = true;
1275
1276 if (sctx->screen->dpbb_allowed &&
1277 (!old_dsa ||
1278 (old_dsa->depth_enabled != dsa->depth_enabled ||
1279 old_dsa->stencil_enabled != dsa->stencil_enabled ||
1280 old_dsa->db_can_write != dsa->db_can_write)))
1281 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
1282
1283 if (sctx->screen->has_out_of_order_rast &&
1284 (!old_dsa ||
1285 memcmp(old_dsa->order_invariance, dsa->order_invariance,
1286 sizeof(old_dsa->order_invariance))))
1287 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
1288 }
1289
1290 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1291 {
1292 struct si_context *sctx = (struct si_context *)ctx;
1293 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1294 }
1295
1296 static void *si_create_db_flush_dsa(struct si_context *sctx)
1297 {
1298 struct pipe_depth_stencil_alpha_state dsa = {};
1299
1300 return sctx->b.create_depth_stencil_alpha_state(&sctx->b, &dsa);
1301 }
1302
1303 /* DB RENDER STATE */
1304
1305 static void si_set_active_query_state(struct pipe_context *ctx, boolean enable)
1306 {
1307 struct si_context *sctx = (struct si_context*)ctx;
1308
1309 /* Pipeline stat & streamout queries. */
1310 if (enable) {
1311 sctx->flags &= ~SI_CONTEXT_STOP_PIPELINE_STATS;
1312 sctx->flags |= SI_CONTEXT_START_PIPELINE_STATS;
1313 } else {
1314 sctx->flags &= ~SI_CONTEXT_START_PIPELINE_STATS;
1315 sctx->flags |= SI_CONTEXT_STOP_PIPELINE_STATS;
1316 }
1317
1318 /* Occlusion queries. */
1319 if (sctx->occlusion_queries_disabled != !enable) {
1320 sctx->occlusion_queries_disabled = !enable;
1321 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1322 }
1323 }
1324
1325 void si_set_occlusion_query_state(struct si_context *sctx,
1326 bool old_perfect_enable)
1327 {
1328 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1329
1330 bool perfect_enable = sctx->num_perfect_occlusion_queries != 0;
1331
1332 if (perfect_enable != old_perfect_enable)
1333 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
1334 }
1335
1336 void si_save_qbo_state(struct si_context *sctx, struct si_qbo_state *st)
1337 {
1338 st->saved_compute = sctx->cs_shader_state.program;
1339
1340 si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1341 si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
1342 }
1343
1344 static void si_emit_db_render_state(struct si_context *sctx)
1345 {
1346 struct radeon_winsys_cs *cs = sctx->gfx_cs;
1347 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1348 unsigned db_shader_control;
1349
1350 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1351
1352 /* DB_RENDER_CONTROL */
1353 if (sctx->dbcb_depth_copy_enabled ||
1354 sctx->dbcb_stencil_copy_enabled) {
1355 radeon_emit(cs,
1356 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1357 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1358 S_028000_COPY_CENTROID(1) |
1359 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
1360 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1361 radeon_emit(cs,
1362 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1363 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace));
1364 } else {
1365 radeon_emit(cs,
1366 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1367 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear));
1368 }
1369
1370 /* DB_COUNT_CONTROL (occlusion queries) */
1371 if (sctx->num_occlusion_queries > 0 &&
1372 !sctx->occlusion_queries_disabled) {
1373 bool perfect = sctx->num_perfect_occlusion_queries > 0;
1374
1375 if (sctx->chip_class >= CIK) {
1376 radeon_emit(cs,
1377 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1378 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
1379 S_028004_ZPASS_ENABLE(1) |
1380 S_028004_SLICE_EVEN_ENABLE(1) |
1381 S_028004_SLICE_ODD_ENABLE(1));
1382 } else {
1383 radeon_emit(cs,
1384 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1385 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
1386 }
1387 } else {
1388 /* Disable occlusion queries. */
1389 if (sctx->chip_class >= CIK) {
1390 radeon_emit(cs, 0);
1391 } else {
1392 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
1393 }
1394 }
1395
1396 /* DB_RENDER_OVERRIDE2 */
1397 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
1398 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1399 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1400 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4));
1401
1402 db_shader_control = sctx->ps_db_shader_control;
1403
1404 /* Bug workaround for smoothing (overrasterization) on SI. */
1405 if (sctx->chip_class == SI && sctx->smoothing_enabled) {
1406 db_shader_control &= C_02880C_Z_ORDER;
1407 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1408 }
1409
1410 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1411 if (!rs || !rs->multisample_enable)
1412 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1413
1414 if (sctx->screen->has_rbplus &&
1415 !sctx->screen->rbplus_allowed)
1416 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1417
1418 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
1419 db_shader_control);
1420 }
1421
1422 /*
1423 * format translation
1424 */
1425 static uint32_t si_translate_colorformat(enum pipe_format format)
1426 {
1427 const struct util_format_description *desc = util_format_description(format);
1428 if (!desc)
1429 return V_028C70_COLOR_INVALID;
1430
1431 #define HAS_SIZE(x,y,z,w) \
1432 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1433 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1434
1435 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1436 return V_028C70_COLOR_10_11_11;
1437
1438 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1439 return V_028C70_COLOR_INVALID;
1440
1441 /* hw cannot support mixed formats (except depth/stencil, since
1442 * stencil is not written to). */
1443 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1444 return V_028C70_COLOR_INVALID;
1445
1446 switch (desc->nr_channels) {
1447 case 1:
1448 switch (desc->channel[0].size) {
1449 case 8:
1450 return V_028C70_COLOR_8;
1451 case 16:
1452 return V_028C70_COLOR_16;
1453 case 32:
1454 return V_028C70_COLOR_32;
1455 }
1456 break;
1457 case 2:
1458 if (desc->channel[0].size == desc->channel[1].size) {
1459 switch (desc->channel[0].size) {
1460 case 8:
1461 return V_028C70_COLOR_8_8;
1462 case 16:
1463 return V_028C70_COLOR_16_16;
1464 case 32:
1465 return V_028C70_COLOR_32_32;
1466 }
1467 } else if (HAS_SIZE(8,24,0,0)) {
1468 return V_028C70_COLOR_24_8;
1469 } else if (HAS_SIZE(24,8,0,0)) {
1470 return V_028C70_COLOR_8_24;
1471 }
1472 break;
1473 case 3:
1474 if (HAS_SIZE(5,6,5,0)) {
1475 return V_028C70_COLOR_5_6_5;
1476 } else if (HAS_SIZE(32,8,24,0)) {
1477 return V_028C70_COLOR_X24_8_32_FLOAT;
1478 }
1479 break;
1480 case 4:
1481 if (desc->channel[0].size == desc->channel[1].size &&
1482 desc->channel[0].size == desc->channel[2].size &&
1483 desc->channel[0].size == desc->channel[3].size) {
1484 switch (desc->channel[0].size) {
1485 case 4:
1486 return V_028C70_COLOR_4_4_4_4;
1487 case 8:
1488 return V_028C70_COLOR_8_8_8_8;
1489 case 16:
1490 return V_028C70_COLOR_16_16_16_16;
1491 case 32:
1492 return V_028C70_COLOR_32_32_32_32;
1493 }
1494 } else if (HAS_SIZE(5,5,5,1)) {
1495 return V_028C70_COLOR_1_5_5_5;
1496 } else if (HAS_SIZE(1,5,5,5)) {
1497 return V_028C70_COLOR_5_5_5_1;
1498 } else if (HAS_SIZE(10,10,10,2)) {
1499 return V_028C70_COLOR_2_10_10_10;
1500 }
1501 break;
1502 }
1503 return V_028C70_COLOR_INVALID;
1504 }
1505
1506 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1507 {
1508 if (SI_BIG_ENDIAN) {
1509 switch(colorformat) {
1510 /* 8-bit buffers. */
1511 case V_028C70_COLOR_8:
1512 return V_028C70_ENDIAN_NONE;
1513
1514 /* 16-bit buffers. */
1515 case V_028C70_COLOR_5_6_5:
1516 case V_028C70_COLOR_1_5_5_5:
1517 case V_028C70_COLOR_4_4_4_4:
1518 case V_028C70_COLOR_16:
1519 case V_028C70_COLOR_8_8:
1520 return V_028C70_ENDIAN_8IN16;
1521
1522 /* 32-bit buffers. */
1523 case V_028C70_COLOR_8_8_8_8:
1524 case V_028C70_COLOR_2_10_10_10:
1525 case V_028C70_COLOR_8_24:
1526 case V_028C70_COLOR_24_8:
1527 case V_028C70_COLOR_16_16:
1528 return V_028C70_ENDIAN_8IN32;
1529
1530 /* 64-bit buffers. */
1531 case V_028C70_COLOR_16_16_16_16:
1532 return V_028C70_ENDIAN_8IN16;
1533
1534 case V_028C70_COLOR_32_32:
1535 return V_028C70_ENDIAN_8IN32;
1536
1537 /* 128-bit buffers. */
1538 case V_028C70_COLOR_32_32_32_32:
1539 return V_028C70_ENDIAN_8IN32;
1540 default:
1541 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1542 }
1543 } else {
1544 return V_028C70_ENDIAN_NONE;
1545 }
1546 }
1547
1548 static uint32_t si_translate_dbformat(enum pipe_format format)
1549 {
1550 switch (format) {
1551 case PIPE_FORMAT_Z16_UNORM:
1552 return V_028040_Z_16;
1553 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1554 case PIPE_FORMAT_X8Z24_UNORM:
1555 case PIPE_FORMAT_Z24X8_UNORM:
1556 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1557 return V_028040_Z_24; /* deprecated on SI */
1558 case PIPE_FORMAT_Z32_FLOAT:
1559 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1560 return V_028040_Z_32_FLOAT;
1561 default:
1562 return V_028040_Z_INVALID;
1563 }
1564 }
1565
1566 /*
1567 * Texture translation
1568 */
1569
1570 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1571 enum pipe_format format,
1572 const struct util_format_description *desc,
1573 int first_non_void)
1574 {
1575 struct si_screen *sscreen = (struct si_screen*)screen;
1576 bool enable_compressed_formats = (sscreen->info.drm_major == 2 &&
1577 sscreen->info.drm_minor >= 31) ||
1578 sscreen->info.drm_major == 3;
1579 bool uniform = true;
1580 int i;
1581
1582 /* Colorspace (return non-RGB formats directly). */
1583 switch (desc->colorspace) {
1584 /* Depth stencil formats */
1585 case UTIL_FORMAT_COLORSPACE_ZS:
1586 switch (format) {
1587 case PIPE_FORMAT_Z16_UNORM:
1588 return V_008F14_IMG_DATA_FORMAT_16;
1589 case PIPE_FORMAT_X24S8_UINT:
1590 case PIPE_FORMAT_S8X24_UINT:
1591 /*
1592 * Implemented as an 8_8_8_8 data format to fix texture
1593 * gathers in stencil sampling. This affects at least
1594 * GL45-CTS.texture_cube_map_array.sampling on VI.
1595 */
1596 if (sscreen->info.chip_class <= VI)
1597 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1598
1599 if (format == PIPE_FORMAT_X24S8_UINT)
1600 return V_008F14_IMG_DATA_FORMAT_8_24;
1601 else
1602 return V_008F14_IMG_DATA_FORMAT_24_8;
1603 case PIPE_FORMAT_Z24X8_UNORM:
1604 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1605 return V_008F14_IMG_DATA_FORMAT_8_24;
1606 case PIPE_FORMAT_X8Z24_UNORM:
1607 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1608 return V_008F14_IMG_DATA_FORMAT_24_8;
1609 case PIPE_FORMAT_S8_UINT:
1610 return V_008F14_IMG_DATA_FORMAT_8;
1611 case PIPE_FORMAT_Z32_FLOAT:
1612 return V_008F14_IMG_DATA_FORMAT_32;
1613 case PIPE_FORMAT_X32_S8X24_UINT:
1614 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1615 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1616 default:
1617 goto out_unknown;
1618 }
1619
1620 case UTIL_FORMAT_COLORSPACE_YUV:
1621 goto out_unknown; /* TODO */
1622
1623 case UTIL_FORMAT_COLORSPACE_SRGB:
1624 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1625 goto out_unknown;
1626 break;
1627
1628 default:
1629 break;
1630 }
1631
1632 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1633 if (!enable_compressed_formats)
1634 goto out_unknown;
1635
1636 switch (format) {
1637 case PIPE_FORMAT_RGTC1_SNORM:
1638 case PIPE_FORMAT_LATC1_SNORM:
1639 case PIPE_FORMAT_RGTC1_UNORM:
1640 case PIPE_FORMAT_LATC1_UNORM:
1641 return V_008F14_IMG_DATA_FORMAT_BC4;
1642 case PIPE_FORMAT_RGTC2_SNORM:
1643 case PIPE_FORMAT_LATC2_SNORM:
1644 case PIPE_FORMAT_RGTC2_UNORM:
1645 case PIPE_FORMAT_LATC2_UNORM:
1646 return V_008F14_IMG_DATA_FORMAT_BC5;
1647 default:
1648 goto out_unknown;
1649 }
1650 }
1651
1652 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1653 (sscreen->info.family == CHIP_STONEY ||
1654 sscreen->info.family == CHIP_VEGA10 ||
1655 sscreen->info.family == CHIP_RAVEN)) {
1656 switch (format) {
1657 case PIPE_FORMAT_ETC1_RGB8:
1658 case PIPE_FORMAT_ETC2_RGB8:
1659 case PIPE_FORMAT_ETC2_SRGB8:
1660 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1661 case PIPE_FORMAT_ETC2_RGB8A1:
1662 case PIPE_FORMAT_ETC2_SRGB8A1:
1663 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1664 case PIPE_FORMAT_ETC2_RGBA8:
1665 case PIPE_FORMAT_ETC2_SRGBA8:
1666 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1667 case PIPE_FORMAT_ETC2_R11_UNORM:
1668 case PIPE_FORMAT_ETC2_R11_SNORM:
1669 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1670 case PIPE_FORMAT_ETC2_RG11_UNORM:
1671 case PIPE_FORMAT_ETC2_RG11_SNORM:
1672 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1673 default:
1674 goto out_unknown;
1675 }
1676 }
1677
1678 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1679 if (!enable_compressed_formats)
1680 goto out_unknown;
1681
1682 switch (format) {
1683 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1684 case PIPE_FORMAT_BPTC_SRGBA:
1685 return V_008F14_IMG_DATA_FORMAT_BC7;
1686 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1687 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1688 return V_008F14_IMG_DATA_FORMAT_BC6;
1689 default:
1690 goto out_unknown;
1691 }
1692 }
1693
1694 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1695 switch (format) {
1696 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1697 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1698 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1699 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1700 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1701 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1702 default:
1703 goto out_unknown;
1704 }
1705 }
1706
1707 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1708 if (!enable_compressed_formats)
1709 goto out_unknown;
1710
1711 switch (format) {
1712 case PIPE_FORMAT_DXT1_RGB:
1713 case PIPE_FORMAT_DXT1_RGBA:
1714 case PIPE_FORMAT_DXT1_SRGB:
1715 case PIPE_FORMAT_DXT1_SRGBA:
1716 return V_008F14_IMG_DATA_FORMAT_BC1;
1717 case PIPE_FORMAT_DXT3_RGBA:
1718 case PIPE_FORMAT_DXT3_SRGBA:
1719 return V_008F14_IMG_DATA_FORMAT_BC2;
1720 case PIPE_FORMAT_DXT5_RGBA:
1721 case PIPE_FORMAT_DXT5_SRGBA:
1722 return V_008F14_IMG_DATA_FORMAT_BC3;
1723 default:
1724 goto out_unknown;
1725 }
1726 }
1727
1728 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1729 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1730 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1731 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1732 }
1733
1734 /* R8G8Bx_SNORM - TODO CxV8U8 */
1735
1736 /* hw cannot support mixed formats (except depth/stencil, since only
1737 * depth is read).*/
1738 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1739 goto out_unknown;
1740
1741 /* See whether the components are of the same size. */
1742 for (i = 1; i < desc->nr_channels; i++) {
1743 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1744 }
1745
1746 /* Non-uniform formats. */
1747 if (!uniform) {
1748 switch(desc->nr_channels) {
1749 case 3:
1750 if (desc->channel[0].size == 5 &&
1751 desc->channel[1].size == 6 &&
1752 desc->channel[2].size == 5) {
1753 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1754 }
1755 goto out_unknown;
1756 case 4:
1757 if (desc->channel[0].size == 5 &&
1758 desc->channel[1].size == 5 &&
1759 desc->channel[2].size == 5 &&
1760 desc->channel[3].size == 1) {
1761 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1762 }
1763 if (desc->channel[0].size == 1 &&
1764 desc->channel[1].size == 5 &&
1765 desc->channel[2].size == 5 &&
1766 desc->channel[3].size == 5) {
1767 return V_008F14_IMG_DATA_FORMAT_5_5_5_1;
1768 }
1769 if (desc->channel[0].size == 10 &&
1770 desc->channel[1].size == 10 &&
1771 desc->channel[2].size == 10 &&
1772 desc->channel[3].size == 2) {
1773 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1774 }
1775 goto out_unknown;
1776 }
1777 goto out_unknown;
1778 }
1779
1780 if (first_non_void < 0 || first_non_void > 3)
1781 goto out_unknown;
1782
1783 /* uniform formats */
1784 switch (desc->channel[first_non_void].size) {
1785 case 4:
1786 switch (desc->nr_channels) {
1787 #if 0 /* Not supported for render targets */
1788 case 2:
1789 return V_008F14_IMG_DATA_FORMAT_4_4;
1790 #endif
1791 case 4:
1792 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1793 }
1794 break;
1795 case 8:
1796 switch (desc->nr_channels) {
1797 case 1:
1798 return V_008F14_IMG_DATA_FORMAT_8;
1799 case 2:
1800 return V_008F14_IMG_DATA_FORMAT_8_8;
1801 case 4:
1802 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1803 }
1804 break;
1805 case 16:
1806 switch (desc->nr_channels) {
1807 case 1:
1808 return V_008F14_IMG_DATA_FORMAT_16;
1809 case 2:
1810 return V_008F14_IMG_DATA_FORMAT_16_16;
1811 case 4:
1812 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1813 }
1814 break;
1815 case 32:
1816 switch (desc->nr_channels) {
1817 case 1:
1818 return V_008F14_IMG_DATA_FORMAT_32;
1819 case 2:
1820 return V_008F14_IMG_DATA_FORMAT_32_32;
1821 #if 0 /* Not supported for render targets */
1822 case 3:
1823 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1824 #endif
1825 case 4:
1826 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1827 }
1828 }
1829
1830 out_unknown:
1831 return ~0;
1832 }
1833
1834 static unsigned si_tex_wrap(unsigned wrap)
1835 {
1836 switch (wrap) {
1837 default:
1838 case PIPE_TEX_WRAP_REPEAT:
1839 return V_008F30_SQ_TEX_WRAP;
1840 case PIPE_TEX_WRAP_CLAMP:
1841 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1842 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1843 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1844 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1845 return V_008F30_SQ_TEX_CLAMP_BORDER;
1846 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1847 return V_008F30_SQ_TEX_MIRROR;
1848 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1849 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1850 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1851 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1852 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1853 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1854 }
1855 }
1856
1857 static unsigned si_tex_mipfilter(unsigned filter)
1858 {
1859 switch (filter) {
1860 case PIPE_TEX_MIPFILTER_NEAREST:
1861 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1862 case PIPE_TEX_MIPFILTER_LINEAR:
1863 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1864 default:
1865 case PIPE_TEX_MIPFILTER_NONE:
1866 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1867 }
1868 }
1869
1870 static unsigned si_tex_compare(unsigned compare)
1871 {
1872 switch (compare) {
1873 default:
1874 case PIPE_FUNC_NEVER:
1875 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1876 case PIPE_FUNC_LESS:
1877 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1878 case PIPE_FUNC_EQUAL:
1879 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1880 case PIPE_FUNC_LEQUAL:
1881 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1882 case PIPE_FUNC_GREATER:
1883 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1884 case PIPE_FUNC_NOTEQUAL:
1885 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1886 case PIPE_FUNC_GEQUAL:
1887 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1888 case PIPE_FUNC_ALWAYS:
1889 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1890 }
1891 }
1892
1893 static unsigned si_tex_dim(struct si_screen *sscreen, struct r600_texture *rtex,
1894 unsigned view_target, unsigned nr_samples)
1895 {
1896 unsigned res_target = rtex->resource.b.b.target;
1897
1898 if (view_target == PIPE_TEXTURE_CUBE ||
1899 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1900 res_target = view_target;
1901 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1902 else if (res_target == PIPE_TEXTURE_CUBE ||
1903 res_target == PIPE_TEXTURE_CUBE_ARRAY)
1904 res_target = PIPE_TEXTURE_2D_ARRAY;
1905
1906 /* GFX9 allocates 1D textures as 2D. */
1907 if ((res_target == PIPE_TEXTURE_1D ||
1908 res_target == PIPE_TEXTURE_1D_ARRAY) &&
1909 sscreen->info.chip_class >= GFX9 &&
1910 rtex->surface.u.gfx9.resource_type == RADEON_RESOURCE_2D) {
1911 if (res_target == PIPE_TEXTURE_1D)
1912 res_target = PIPE_TEXTURE_2D;
1913 else
1914 res_target = PIPE_TEXTURE_2D_ARRAY;
1915 }
1916
1917 switch (res_target) {
1918 default:
1919 case PIPE_TEXTURE_1D:
1920 return V_008F1C_SQ_RSRC_IMG_1D;
1921 case PIPE_TEXTURE_1D_ARRAY:
1922 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1923 case PIPE_TEXTURE_2D:
1924 case PIPE_TEXTURE_RECT:
1925 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1926 V_008F1C_SQ_RSRC_IMG_2D;
1927 case PIPE_TEXTURE_2D_ARRAY:
1928 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1929 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1930 case PIPE_TEXTURE_3D:
1931 return V_008F1C_SQ_RSRC_IMG_3D;
1932 case PIPE_TEXTURE_CUBE:
1933 case PIPE_TEXTURE_CUBE_ARRAY:
1934 return V_008F1C_SQ_RSRC_IMG_CUBE;
1935 }
1936 }
1937
1938 /*
1939 * Format support testing
1940 */
1941
1942 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1943 {
1944 const struct util_format_description *desc = util_format_description(format);
1945 if (!desc)
1946 return false;
1947
1948 return si_translate_texformat(screen, format, desc,
1949 util_format_get_first_non_void_channel(format)) != ~0U;
1950 }
1951
1952 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1953 const struct util_format_description *desc,
1954 int first_non_void)
1955 {
1956 int i;
1957
1958 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1959 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1960
1961 assert(first_non_void >= 0);
1962
1963 if (desc->nr_channels == 4 &&
1964 desc->channel[0].size == 10 &&
1965 desc->channel[1].size == 10 &&
1966 desc->channel[2].size == 10 &&
1967 desc->channel[3].size == 2)
1968 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1969
1970 /* See whether the components are of the same size. */
1971 for (i = 0; i < desc->nr_channels; i++) {
1972 if (desc->channel[first_non_void].size != desc->channel[i].size)
1973 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1974 }
1975
1976 switch (desc->channel[first_non_void].size) {
1977 case 8:
1978 switch (desc->nr_channels) {
1979 case 1:
1980 case 3: /* 3 loads */
1981 return V_008F0C_BUF_DATA_FORMAT_8;
1982 case 2:
1983 return V_008F0C_BUF_DATA_FORMAT_8_8;
1984 case 4:
1985 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1986 }
1987 break;
1988 case 16:
1989 switch (desc->nr_channels) {
1990 case 1:
1991 case 3: /* 3 loads */
1992 return V_008F0C_BUF_DATA_FORMAT_16;
1993 case 2:
1994 return V_008F0C_BUF_DATA_FORMAT_16_16;
1995 case 4:
1996 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1997 }
1998 break;
1999 case 32:
2000 switch (desc->nr_channels) {
2001 case 1:
2002 return V_008F0C_BUF_DATA_FORMAT_32;
2003 case 2:
2004 return V_008F0C_BUF_DATA_FORMAT_32_32;
2005 case 3:
2006 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
2007 case 4:
2008 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2009 }
2010 break;
2011 case 64:
2012 /* Legacy double formats. */
2013 switch (desc->nr_channels) {
2014 case 1: /* 1 load */
2015 return V_008F0C_BUF_DATA_FORMAT_32_32;
2016 case 2: /* 1 load */
2017 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2018 case 3: /* 3 loads */
2019 return V_008F0C_BUF_DATA_FORMAT_32_32;
2020 case 4: /* 2 loads */
2021 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2022 }
2023 break;
2024 }
2025
2026 return V_008F0C_BUF_DATA_FORMAT_INVALID;
2027 }
2028
2029 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
2030 const struct util_format_description *desc,
2031 int first_non_void)
2032 {
2033 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
2034 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2035
2036 assert(first_non_void >= 0);
2037
2038 switch (desc->channel[first_non_void].type) {
2039 case UTIL_FORMAT_TYPE_SIGNED:
2040 case UTIL_FORMAT_TYPE_FIXED:
2041 if (desc->channel[first_non_void].size >= 32 ||
2042 desc->channel[first_non_void].pure_integer)
2043 return V_008F0C_BUF_NUM_FORMAT_SINT;
2044 else if (desc->channel[first_non_void].normalized)
2045 return V_008F0C_BUF_NUM_FORMAT_SNORM;
2046 else
2047 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
2048 break;
2049 case UTIL_FORMAT_TYPE_UNSIGNED:
2050 if (desc->channel[first_non_void].size >= 32 ||
2051 desc->channel[first_non_void].pure_integer)
2052 return V_008F0C_BUF_NUM_FORMAT_UINT;
2053 else if (desc->channel[first_non_void].normalized)
2054 return V_008F0C_BUF_NUM_FORMAT_UNORM;
2055 else
2056 return V_008F0C_BUF_NUM_FORMAT_USCALED;
2057 break;
2058 case UTIL_FORMAT_TYPE_FLOAT:
2059 default:
2060 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2061 }
2062 }
2063
2064 static unsigned si_is_vertex_format_supported(struct pipe_screen *screen,
2065 enum pipe_format format,
2066 unsigned usage)
2067 {
2068 const struct util_format_description *desc;
2069 int first_non_void;
2070 unsigned data_format;
2071
2072 assert((usage & ~(PIPE_BIND_SHADER_IMAGE |
2073 PIPE_BIND_SAMPLER_VIEW |
2074 PIPE_BIND_VERTEX_BUFFER)) == 0);
2075
2076 desc = util_format_description(format);
2077 if (!desc)
2078 return 0;
2079
2080 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
2081 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
2082 * for read-only access (with caveats surrounding bounds checks), but
2083 * obviously fails for write access which we have to implement for
2084 * shader images. Luckily, OpenGL doesn't expect this to be supported
2085 * anyway, and so the only impact is on PBO uploads / downloads, which
2086 * shouldn't be expected to be fast for GL_RGB anyway.
2087 */
2088 if (desc->block.bits == 3 * 8 ||
2089 desc->block.bits == 3 * 16) {
2090 if (usage & (PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW)) {
2091 usage &= ~(PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW);
2092 if (!usage)
2093 return 0;
2094 }
2095 }
2096
2097 first_non_void = util_format_get_first_non_void_channel(format);
2098 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
2099 if (data_format == V_008F0C_BUF_DATA_FORMAT_INVALID)
2100 return 0;
2101
2102 return usage;
2103 }
2104
2105 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
2106 {
2107 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
2108 si_translate_colorswap(format, false) != ~0U;
2109 }
2110
2111 static bool si_is_zs_format_supported(enum pipe_format format)
2112 {
2113 return si_translate_dbformat(format) != V_028040_Z_INVALID;
2114 }
2115
2116 static boolean si_is_format_supported(struct pipe_screen *screen,
2117 enum pipe_format format,
2118 enum pipe_texture_target target,
2119 unsigned sample_count,
2120 unsigned usage)
2121 {
2122 unsigned retval = 0;
2123
2124 if (target >= PIPE_MAX_TEXTURE_TYPES) {
2125 PRINT_ERR("r600: unsupported texture type %d\n", target);
2126 return false;
2127 }
2128
2129 if (!util_format_is_supported(format, usage))
2130 return false;
2131
2132 if (sample_count > 1) {
2133 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
2134 return false;
2135
2136 if (usage & PIPE_BIND_SHADER_IMAGE)
2137 return false;
2138
2139 switch (sample_count) {
2140 case 2:
2141 case 4:
2142 case 8:
2143 break;
2144 case 16:
2145 if (format == PIPE_FORMAT_NONE)
2146 return true;
2147 else
2148 return false;
2149 default:
2150 return false;
2151 }
2152 }
2153
2154 if (usage & (PIPE_BIND_SAMPLER_VIEW |
2155 PIPE_BIND_SHADER_IMAGE)) {
2156 if (target == PIPE_BUFFER) {
2157 retval |= si_is_vertex_format_supported(
2158 screen, format, usage & (PIPE_BIND_SAMPLER_VIEW |
2159 PIPE_BIND_SHADER_IMAGE));
2160 } else {
2161 if (si_is_sampler_format_supported(screen, format))
2162 retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
2163 PIPE_BIND_SHADER_IMAGE);
2164 }
2165 }
2166
2167 if ((usage & (PIPE_BIND_RENDER_TARGET |
2168 PIPE_BIND_DISPLAY_TARGET |
2169 PIPE_BIND_SCANOUT |
2170 PIPE_BIND_SHARED |
2171 PIPE_BIND_BLENDABLE)) &&
2172 si_is_colorbuffer_format_supported(format)) {
2173 retval |= usage &
2174 (PIPE_BIND_RENDER_TARGET |
2175 PIPE_BIND_DISPLAY_TARGET |
2176 PIPE_BIND_SCANOUT |
2177 PIPE_BIND_SHARED);
2178 if (!util_format_is_pure_integer(format) &&
2179 !util_format_is_depth_or_stencil(format))
2180 retval |= usage & PIPE_BIND_BLENDABLE;
2181 }
2182
2183 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
2184 si_is_zs_format_supported(format)) {
2185 retval |= PIPE_BIND_DEPTH_STENCIL;
2186 }
2187
2188 if (usage & PIPE_BIND_VERTEX_BUFFER) {
2189 retval |= si_is_vertex_format_supported(screen, format,
2190 PIPE_BIND_VERTEX_BUFFER);
2191 }
2192
2193 if ((usage & PIPE_BIND_LINEAR) &&
2194 !util_format_is_compressed(format) &&
2195 !(usage & PIPE_BIND_DEPTH_STENCIL))
2196 retval |= PIPE_BIND_LINEAR;
2197
2198 return retval == usage;
2199 }
2200
2201 /*
2202 * framebuffer handling
2203 */
2204
2205 static void si_choose_spi_color_formats(struct r600_surface *surf,
2206 unsigned format, unsigned swap,
2207 unsigned ntype, bool is_depth)
2208 {
2209 /* Alpha is needed for alpha-to-coverage.
2210 * Blending may be with or without alpha.
2211 */
2212 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
2213 unsigned alpha = 0; /* exports alpha, but may not support blending */
2214 unsigned blend = 0; /* supports blending, but may not export alpha */
2215 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
2216
2217 /* Choose the SPI color formats. These are required values for RB+.
2218 * Other chips have multiple choices, though they are not necessarily better.
2219 */
2220 switch (format) {
2221 case V_028C70_COLOR_5_6_5:
2222 case V_028C70_COLOR_1_5_5_5:
2223 case V_028C70_COLOR_5_5_5_1:
2224 case V_028C70_COLOR_4_4_4_4:
2225 case V_028C70_COLOR_10_11_11:
2226 case V_028C70_COLOR_11_11_10:
2227 case V_028C70_COLOR_8:
2228 case V_028C70_COLOR_8_8:
2229 case V_028C70_COLOR_8_8_8_8:
2230 case V_028C70_COLOR_10_10_10_2:
2231 case V_028C70_COLOR_2_10_10_10:
2232 if (ntype == V_028C70_NUMBER_UINT)
2233 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2234 else if (ntype == V_028C70_NUMBER_SINT)
2235 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2236 else
2237 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2238 break;
2239
2240 case V_028C70_COLOR_16:
2241 case V_028C70_COLOR_16_16:
2242 case V_028C70_COLOR_16_16_16_16:
2243 if (ntype == V_028C70_NUMBER_UNORM ||
2244 ntype == V_028C70_NUMBER_SNORM) {
2245 /* UNORM16 and SNORM16 don't support blending */
2246 if (ntype == V_028C70_NUMBER_UNORM)
2247 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
2248 else
2249 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
2250
2251 /* Use 32 bits per channel for blending. */
2252 if (format == V_028C70_COLOR_16) {
2253 if (swap == V_028C70_SWAP_STD) { /* R */
2254 blend = V_028714_SPI_SHADER_32_R;
2255 blend_alpha = V_028714_SPI_SHADER_32_AR;
2256 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2257 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2258 else
2259 assert(0);
2260 } else if (format == V_028C70_COLOR_16_16) {
2261 if (swap == V_028C70_SWAP_STD) { /* RG */
2262 blend = V_028714_SPI_SHADER_32_GR;
2263 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2264 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2265 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2266 else
2267 assert(0);
2268 } else /* 16_16_16_16 */
2269 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2270 } else if (ntype == V_028C70_NUMBER_UINT)
2271 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2272 else if (ntype == V_028C70_NUMBER_SINT)
2273 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2274 else if (ntype == V_028C70_NUMBER_FLOAT)
2275 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2276 else
2277 assert(0);
2278 break;
2279
2280 case V_028C70_COLOR_32:
2281 if (swap == V_028C70_SWAP_STD) { /* R */
2282 blend = normal = V_028714_SPI_SHADER_32_R;
2283 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
2284 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2285 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2286 else
2287 assert(0);
2288 break;
2289
2290 case V_028C70_COLOR_32_32:
2291 if (swap == V_028C70_SWAP_STD) { /* RG */
2292 blend = normal = V_028714_SPI_SHADER_32_GR;
2293 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2294 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2295 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2296 else
2297 assert(0);
2298 break;
2299
2300 case V_028C70_COLOR_32_32_32_32:
2301 case V_028C70_COLOR_8_24:
2302 case V_028C70_COLOR_24_8:
2303 case V_028C70_COLOR_X24_8_32_FLOAT:
2304 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2305 break;
2306
2307 default:
2308 assert(0);
2309 return;
2310 }
2311
2312 /* The DB->CB copy needs 32_ABGR. */
2313 if (is_depth)
2314 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2315
2316 surf->spi_shader_col_format = normal;
2317 surf->spi_shader_col_format_alpha = alpha;
2318 surf->spi_shader_col_format_blend = blend;
2319 surf->spi_shader_col_format_blend_alpha = blend_alpha;
2320 }
2321
2322 static void si_initialize_color_surface(struct si_context *sctx,
2323 struct r600_surface *surf)
2324 {
2325 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2326 unsigned color_info, color_attrib;
2327 unsigned format, swap, ntype, endian;
2328 const struct util_format_description *desc;
2329 int firstchan;
2330 unsigned blend_clamp = 0, blend_bypass = 0;
2331
2332 desc = util_format_description(surf->base.format);
2333 for (firstchan = 0; firstchan < 4; firstchan++) {
2334 if (desc->channel[firstchan].type != UTIL_FORMAT_TYPE_VOID) {
2335 break;
2336 }
2337 }
2338 if (firstchan == 4 || desc->channel[firstchan].type == UTIL_FORMAT_TYPE_FLOAT) {
2339 ntype = V_028C70_NUMBER_FLOAT;
2340 } else {
2341 ntype = V_028C70_NUMBER_UNORM;
2342 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2343 ntype = V_028C70_NUMBER_SRGB;
2344 else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_SIGNED) {
2345 if (desc->channel[firstchan].pure_integer) {
2346 ntype = V_028C70_NUMBER_SINT;
2347 } else {
2348 assert(desc->channel[firstchan].normalized);
2349 ntype = V_028C70_NUMBER_SNORM;
2350 }
2351 } else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2352 if (desc->channel[firstchan].pure_integer) {
2353 ntype = V_028C70_NUMBER_UINT;
2354 } else {
2355 assert(desc->channel[firstchan].normalized);
2356 ntype = V_028C70_NUMBER_UNORM;
2357 }
2358 }
2359 }
2360
2361 format = si_translate_colorformat(surf->base.format);
2362 if (format == V_028C70_COLOR_INVALID) {
2363 PRINT_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2364 }
2365 assert(format != V_028C70_COLOR_INVALID);
2366 swap = si_translate_colorswap(surf->base.format, false);
2367 endian = si_colorformat_endian_swap(format);
2368
2369 /* blend clamp should be set for all NORM/SRGB types */
2370 if (ntype == V_028C70_NUMBER_UNORM ||
2371 ntype == V_028C70_NUMBER_SNORM ||
2372 ntype == V_028C70_NUMBER_SRGB)
2373 blend_clamp = 1;
2374
2375 /* set blend bypass according to docs if SINT/UINT or
2376 8/24 COLOR variants */
2377 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2378 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2379 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2380 blend_clamp = 0;
2381 blend_bypass = 1;
2382 }
2383
2384 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) {
2385 if (format == V_028C70_COLOR_8 ||
2386 format == V_028C70_COLOR_8_8 ||
2387 format == V_028C70_COLOR_8_8_8_8)
2388 surf->color_is_int8 = true;
2389 else if (format == V_028C70_COLOR_10_10_10_2 ||
2390 format == V_028C70_COLOR_2_10_10_10)
2391 surf->color_is_int10 = true;
2392 }
2393
2394 color_info = S_028C70_FORMAT(format) |
2395 S_028C70_COMP_SWAP(swap) |
2396 S_028C70_BLEND_CLAMP(blend_clamp) |
2397 S_028C70_BLEND_BYPASS(blend_bypass) |
2398 S_028C70_SIMPLE_FLOAT(1) |
2399 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2400 ntype != V_028C70_NUMBER_SNORM &&
2401 ntype != V_028C70_NUMBER_SRGB &&
2402 format != V_028C70_COLOR_8_24 &&
2403 format != V_028C70_COLOR_24_8) |
2404 S_028C70_NUMBER_TYPE(ntype) |
2405 S_028C70_ENDIAN(endian);
2406
2407 /* Intensity is implemented as Red, so treat it that way. */
2408 color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2409 util_format_is_intensity(surf->base.format));
2410
2411 if (rtex->resource.b.b.nr_samples > 1) {
2412 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
2413
2414 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2415 S_028C74_NUM_FRAGMENTS(log_samples);
2416
2417 if (rtex->fmask.size) {
2418 color_info |= S_028C70_COMPRESSION(1);
2419 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
2420
2421 if (sctx->chip_class == SI) {
2422 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2423 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2424 }
2425 }
2426 }
2427
2428 if (sctx->chip_class >= VI) {
2429 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
2430 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
2431
2432 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2433 64 for APU because all of our APUs to date use DIMMs which have
2434 a request granularity size of 64B while all other chips have a
2435 32B request size */
2436 if (!sctx->screen->info.has_dedicated_vram)
2437 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
2438
2439 if (rtex->resource.b.b.nr_samples > 1) {
2440 if (rtex->surface.bpe == 1)
2441 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
2442 else if (rtex->surface.bpe == 2)
2443 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
2444 }
2445
2446 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2447 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
2448 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2449 }
2450
2451 /* This must be set for fast clear to work without FMASK. */
2452 if (!rtex->fmask.size && sctx->chip_class == SI) {
2453 unsigned bankh = util_logbase2(rtex->surface.u.legacy.bankh);
2454 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2455 }
2456
2457 unsigned color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2458 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
2459
2460 if (sctx->chip_class >= GFX9) {
2461 unsigned mip0_depth = util_max_layer(&rtex->resource.b.b, 0);
2462
2463 color_view |= S_028C6C_MIP_LEVEL(surf->base.u.tex.level);
2464 color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
2465 S_028C74_RESOURCE_TYPE(rtex->surface.u.gfx9.resource_type);
2466 surf->cb_color_attrib2 = S_028C68_MIP0_WIDTH(surf->width0 - 1) |
2467 S_028C68_MIP0_HEIGHT(surf->height0 - 1) |
2468 S_028C68_MAX_MIP(rtex->resource.b.b.last_level);
2469 }
2470
2471 surf->cb_color_view = color_view;
2472 surf->cb_color_info = color_info;
2473 surf->cb_color_attrib = color_attrib;
2474
2475 /* Determine pixel shader export format */
2476 si_choose_spi_color_formats(surf, format, swap, ntype, rtex->is_depth);
2477
2478 surf->color_initialized = true;
2479 }
2480
2481 static void si_init_depth_surface(struct si_context *sctx,
2482 struct r600_surface *surf)
2483 {
2484 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2485 unsigned level = surf->base.u.tex.level;
2486 unsigned format, stencil_format;
2487 uint32_t z_info, s_info;
2488
2489 format = si_translate_dbformat(rtex->db_render_format);
2490 stencil_format = rtex->surface.has_stencil ?
2491 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
2492
2493 assert(format != V_028040_Z_INVALID);
2494 if (format == V_028040_Z_INVALID)
2495 PRINT_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
2496
2497 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2498 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2499 surf->db_htile_data_base = 0;
2500 surf->db_htile_surface = 0;
2501
2502 if (sctx->chip_class >= GFX9) {
2503 assert(rtex->surface.u.gfx9.surf_offset == 0);
2504 surf->db_depth_base = rtex->resource.gpu_address >> 8;
2505 surf->db_stencil_base = (rtex->resource.gpu_address +
2506 rtex->surface.u.gfx9.stencil_offset) >> 8;
2507 z_info = S_028038_FORMAT(format) |
2508 S_028038_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples)) |
2509 S_028038_SW_MODE(rtex->surface.u.gfx9.surf.swizzle_mode) |
2510 S_028038_MAXMIP(rtex->resource.b.b.last_level);
2511 s_info = S_02803C_FORMAT(stencil_format) |
2512 S_02803C_SW_MODE(rtex->surface.u.gfx9.stencil.swizzle_mode);
2513 surf->db_z_info2 = S_028068_EPITCH(rtex->surface.u.gfx9.surf.epitch);
2514 surf->db_stencil_info2 = S_02806C_EPITCH(rtex->surface.u.gfx9.stencil.epitch);
2515 surf->db_depth_view |= S_028008_MIPID(level);
2516 surf->db_depth_size = S_02801C_X_MAX(rtex->resource.b.b.width0 - 1) |
2517 S_02801C_Y_MAX(rtex->resource.b.b.height0 - 1);
2518
2519 if (si_htile_enabled(rtex, level)) {
2520 z_info |= S_028038_TILE_SURFACE_ENABLE(1) |
2521 S_028038_ALLOW_EXPCLEAR(1);
2522
2523 if (rtex->tc_compatible_htile) {
2524 unsigned max_zplanes = 4;
2525
2526 if (rtex->db_render_format == PIPE_FORMAT_Z16_UNORM &&
2527 rtex->resource.b.b.nr_samples > 1)
2528 max_zplanes = 2;
2529
2530 z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1) |
2531 S_028038_ITERATE_FLUSH(1);
2532 s_info |= S_02803C_ITERATE_FLUSH(1);
2533 }
2534
2535 if (rtex->surface.has_stencil) {
2536 /* Stencil buffer workaround ported from the SI-CI-VI code.
2537 * See that for explanation.
2538 */
2539 s_info |= S_02803C_ALLOW_EXPCLEAR(rtex->resource.b.b.nr_samples <= 1);
2540 } else {
2541 /* Use all HTILE for depth if there's no stencil. */
2542 s_info |= S_02803C_TILE_STENCIL_DISABLE(1);
2543 }
2544
2545 surf->db_htile_data_base = (rtex->resource.gpu_address +
2546 rtex->htile_offset) >> 8;
2547 surf->db_htile_surface = S_028ABC_FULL_CACHE(1) |
2548 S_028ABC_PIPE_ALIGNED(rtex->surface.u.gfx9.htile.pipe_aligned) |
2549 S_028ABC_RB_ALIGNED(rtex->surface.u.gfx9.htile.rb_aligned);
2550 }
2551 } else {
2552 /* SI-CI-VI */
2553 struct legacy_surf_level *levelinfo = &rtex->surface.u.legacy.level[level];
2554
2555 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2556
2557 surf->db_depth_base = (rtex->resource.gpu_address +
2558 rtex->surface.u.legacy.level[level].offset) >> 8;
2559 surf->db_stencil_base = (rtex->resource.gpu_address +
2560 rtex->surface.u.legacy.stencil_level[level].offset) >> 8;
2561
2562 z_info = S_028040_FORMAT(format) |
2563 S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
2564 s_info = S_028044_FORMAT(stencil_format);
2565 surf->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!rtex->tc_compatible_htile);
2566
2567 if (sctx->chip_class >= CIK) {
2568 struct radeon_info *info = &sctx->screen->info;
2569 unsigned index = rtex->surface.u.legacy.tiling_index[level];
2570 unsigned stencil_index = rtex->surface.u.legacy.stencil_tiling_index[level];
2571 unsigned macro_index = rtex->surface.u.legacy.macro_tile_index;
2572 unsigned tile_mode = info->si_tile_mode_array[index];
2573 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2574 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2575
2576 surf->db_depth_info |=
2577 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2578 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2579 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2580 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2581 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2582 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2583 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2584 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2585 } else {
2586 unsigned tile_mode_index = si_tile_mode_index(rtex, level, false);
2587 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2588 tile_mode_index = si_tile_mode_index(rtex, level, true);
2589 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2590 }
2591
2592 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2593 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2594 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2595 levelinfo->nblk_y) / 64 - 1);
2596
2597 if (si_htile_enabled(rtex, level)) {
2598 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2599 S_028040_ALLOW_EXPCLEAR(1);
2600
2601 if (rtex->surface.has_stencil) {
2602 /* Workaround: For a not yet understood reason, the
2603 * combination of MSAA, fast stencil clear and stencil
2604 * decompress messes with subsequent stencil buffer
2605 * uses. Problem was reproduced on Verde, Bonaire,
2606 * Tonga, and Carrizo.
2607 *
2608 * Disabling EXPCLEAR works around the problem.
2609 *
2610 * Check piglit's arb_texture_multisample-stencil-clear
2611 * test if you want to try changing this.
2612 */
2613 if (rtex->resource.b.b.nr_samples <= 1)
2614 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2615 } else if (!rtex->tc_compatible_htile) {
2616 /* Use all of the htile_buffer for depth if there's no stencil.
2617 * This must not be set when TC-compatible HTILE is enabled
2618 * due to a hw bug.
2619 */
2620 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2621 }
2622
2623 surf->db_htile_data_base = (rtex->resource.gpu_address +
2624 rtex->htile_offset) >> 8;
2625 surf->db_htile_surface = S_028ABC_FULL_CACHE(1);
2626
2627 if (rtex->tc_compatible_htile) {
2628 surf->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
2629
2630 if (rtex->resource.b.b.nr_samples <= 1)
2631 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2632 else if (rtex->resource.b.b.nr_samples <= 4)
2633 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2634 else
2635 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2636 }
2637 }
2638 }
2639
2640 surf->db_z_info = z_info;
2641 surf->db_stencil_info = s_info;
2642
2643 surf->depth_initialized = true;
2644 }
2645
2646 void si_update_fb_dirtiness_after_rendering(struct si_context *sctx)
2647 {
2648 if (sctx->decompression_enabled)
2649 return;
2650
2651 if (sctx->framebuffer.state.zsbuf) {
2652 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
2653 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
2654
2655 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
2656
2657 if (rtex->surface.has_stencil)
2658 rtex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
2659 }
2660
2661 unsigned compressed_cb_mask = sctx->framebuffer.compressed_cb_mask;
2662 while (compressed_cb_mask) {
2663 unsigned i = u_bit_scan(&compressed_cb_mask);
2664 struct pipe_surface *surf = sctx->framebuffer.state.cbufs[i];
2665 struct r600_texture *rtex = (struct r600_texture*)surf->texture;
2666
2667 if (rtex->fmask.size)
2668 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
2669 if (rtex->dcc_gather_statistics)
2670 rtex->separate_dcc_dirty = true;
2671 }
2672 }
2673
2674 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
2675 {
2676 for (int i = 0; i < state->nr_cbufs; ++i) {
2677 struct r600_surface *surf = NULL;
2678 struct r600_texture *rtex;
2679
2680 if (!state->cbufs[i])
2681 continue;
2682 surf = (struct r600_surface*)state->cbufs[i];
2683 rtex = (struct r600_texture*)surf->base.texture;
2684
2685 p_atomic_dec(&rtex->framebuffers_bound);
2686 }
2687 }
2688
2689 static void si_set_framebuffer_state(struct pipe_context *ctx,
2690 const struct pipe_framebuffer_state *state)
2691 {
2692 struct si_context *sctx = (struct si_context *)ctx;
2693 struct pipe_constant_buffer constbuf = {0};
2694 struct r600_surface *surf = NULL;
2695 struct r600_texture *rtex;
2696 bool old_any_dst_linear = sctx->framebuffer.any_dst_linear;
2697 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2698 unsigned old_colorbuf_enabled_4bit = sctx->framebuffer.colorbuf_enabled_4bit;
2699 bool old_has_zsbuf = !!sctx->framebuffer.state.zsbuf;
2700 bool old_has_stencil =
2701 old_has_zsbuf &&
2702 ((struct r600_texture*)sctx->framebuffer.state.zsbuf->texture)->surface.has_stencil;
2703 bool unbound = false;
2704 int i;
2705
2706 si_update_fb_dirtiness_after_rendering(sctx);
2707
2708 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
2709 if (!sctx->framebuffer.state.cbufs[i])
2710 continue;
2711
2712 rtex = (struct r600_texture*)sctx->framebuffer.state.cbufs[i]->texture;
2713 if (rtex->dcc_gather_statistics)
2714 vi_separate_dcc_stop_query(sctx, rtex);
2715 }
2716
2717 /* Disable DCC if the formats are incompatible. */
2718 for (i = 0; i < state->nr_cbufs; i++) {
2719 if (!state->cbufs[i])
2720 continue;
2721
2722 surf = (struct r600_surface*)state->cbufs[i];
2723 rtex = (struct r600_texture*)surf->base.texture;
2724
2725 if (!surf->dcc_incompatible)
2726 continue;
2727
2728 /* Since the DCC decompression calls back into set_framebuffer-
2729 * _state, we need to unbind the framebuffer, so that
2730 * vi_separate_dcc_stop_query isn't called twice with the same
2731 * color buffer.
2732 */
2733 if (!unbound) {
2734 util_copy_framebuffer_state(&sctx->framebuffer.state, NULL);
2735 unbound = true;
2736 }
2737
2738 if (vi_dcc_enabled(rtex, surf->base.u.tex.level))
2739 if (!si_texture_disable_dcc(sctx, rtex))
2740 si_decompress_dcc(sctx, rtex);
2741
2742 surf->dcc_incompatible = false;
2743 }
2744
2745 /* Only flush TC when changing the framebuffer state, because
2746 * the only client not using TC that can change textures is
2747 * the framebuffer.
2748 *
2749 * Wait for compute shaders because of possible transitions:
2750 * - FB write -> shader read
2751 * - shader write -> FB read
2752 *
2753 * DB caches are flushed on demand (using si_decompress_textures).
2754 *
2755 * When MSAA is enabled, CB and TC caches are flushed on demand
2756 * (after FMASK decompression). Shader write -> FB read transitions
2757 * cannot happen for MSAA textures, because MSAA shader images are
2758 * not supported.
2759 *
2760 * Only flush and wait for CB if there is actually a bound color buffer.
2761 */
2762 if (sctx->framebuffer.uncompressed_cb_mask)
2763 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
2764 sctx->framebuffer.CB_has_shader_readable_metadata);
2765
2766 sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
2767
2768 /* u_blitter doesn't invoke depth decompression when it does multiple
2769 * blits in a row, but the only case when it matters for DB is when
2770 * doing generate_mipmap. So here we flush DB manually between
2771 * individual generate_mipmap blits.
2772 * Note that lower mipmap levels aren't compressed.
2773 */
2774 if (sctx->generate_mipmap_for_depth) {
2775 si_make_DB_shader_coherent(sctx, 1, false,
2776 sctx->framebuffer.DB_has_shader_readable_metadata);
2777 } else if (sctx->chip_class == GFX9) {
2778 /* It appears that DB metadata "leaks" in a sequence of:
2779 * - depth clear
2780 * - DCC decompress for shader image writes (with DB disabled)
2781 * - render with DEPTH_BEFORE_SHADER=1
2782 * Flushing DB metadata works around the problem.
2783 */
2784 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB_META;
2785 }
2786
2787 /* Take the maximum of the old and new count. If the new count is lower,
2788 * dirtying is needed to disable the unbound colorbuffers.
2789 */
2790 sctx->framebuffer.dirty_cbufs |=
2791 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2792 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2793
2794 si_dec_framebuffer_counters(&sctx->framebuffer.state);
2795 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2796
2797 sctx->framebuffer.colorbuf_enabled_4bit = 0;
2798 sctx->framebuffer.spi_shader_col_format = 0;
2799 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2800 sctx->framebuffer.spi_shader_col_format_blend = 0;
2801 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2802 sctx->framebuffer.color_is_int8 = 0;
2803 sctx->framebuffer.color_is_int10 = 0;
2804
2805 sctx->framebuffer.compressed_cb_mask = 0;
2806 sctx->framebuffer.uncompressed_cb_mask = 0;
2807 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2808 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2809 sctx->framebuffer.any_dst_linear = false;
2810 sctx->framebuffer.CB_has_shader_readable_metadata = false;
2811 sctx->framebuffer.DB_has_shader_readable_metadata = false;
2812
2813 for (i = 0; i < state->nr_cbufs; i++) {
2814 if (!state->cbufs[i])
2815 continue;
2816
2817 surf = (struct r600_surface*)state->cbufs[i];
2818 rtex = (struct r600_texture*)surf->base.texture;
2819
2820 if (!surf->color_initialized) {
2821 si_initialize_color_surface(sctx, surf);
2822 }
2823
2824 sctx->framebuffer.colorbuf_enabled_4bit |= 0xf << (i * 4);
2825 sctx->framebuffer.spi_shader_col_format |=
2826 surf->spi_shader_col_format << (i * 4);
2827 sctx->framebuffer.spi_shader_col_format_alpha |=
2828 surf->spi_shader_col_format_alpha << (i * 4);
2829 sctx->framebuffer.spi_shader_col_format_blend |=
2830 surf->spi_shader_col_format_blend << (i * 4);
2831 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2832 surf->spi_shader_col_format_blend_alpha << (i * 4);
2833
2834 if (surf->color_is_int8)
2835 sctx->framebuffer.color_is_int8 |= 1 << i;
2836 if (surf->color_is_int10)
2837 sctx->framebuffer.color_is_int10 |= 1 << i;
2838
2839 if (rtex->fmask.size)
2840 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2841 else
2842 sctx->framebuffer.uncompressed_cb_mask |= 1 << i;
2843
2844 if (rtex->surface.is_linear)
2845 sctx->framebuffer.any_dst_linear = true;
2846
2847 if (vi_dcc_enabled(rtex, surf->base.u.tex.level))
2848 sctx->framebuffer.CB_has_shader_readable_metadata = true;
2849
2850 si_context_add_resource_size(sctx, surf->base.texture);
2851
2852 p_atomic_inc(&rtex->framebuffers_bound);
2853
2854 if (rtex->dcc_gather_statistics) {
2855 /* Dirty tracking must be enabled for DCC usage analysis. */
2856 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2857 vi_separate_dcc_start_query(sctx, rtex);
2858 }
2859 }
2860
2861 struct r600_texture *zstex = NULL;
2862
2863 if (state->zsbuf) {
2864 surf = (struct r600_surface*)state->zsbuf;
2865 zstex = (struct r600_texture*)surf->base.texture;
2866
2867 if (!surf->depth_initialized) {
2868 si_init_depth_surface(sctx, surf);
2869 }
2870
2871 if (vi_tc_compat_htile_enabled(zstex, surf->base.u.tex.level))
2872 sctx->framebuffer.DB_has_shader_readable_metadata = true;
2873
2874 si_context_add_resource_size(sctx, surf->base.texture);
2875 }
2876
2877 si_update_ps_colorbuf0_slot(sctx);
2878 si_update_poly_offset_state(sctx);
2879 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
2880 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
2881
2882 if (sctx->screen->dpbb_allowed)
2883 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
2884
2885 if (sctx->framebuffer.any_dst_linear != old_any_dst_linear)
2886 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2887
2888 if (sctx->screen->has_out_of_order_rast &&
2889 (sctx->framebuffer.colorbuf_enabled_4bit != old_colorbuf_enabled_4bit ||
2890 !!sctx->framebuffer.state.zsbuf != old_has_zsbuf ||
2891 (zstex && zstex->surface.has_stencil != old_has_stencil)))
2892 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2893
2894 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2895 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2896 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
2897
2898 /* Set sample locations as fragment shader constants. */
2899 switch (sctx->framebuffer.nr_samples) {
2900 case 1:
2901 constbuf.user_buffer = sctx->sample_locations_1x;
2902 break;
2903 case 2:
2904 constbuf.user_buffer = sctx->sample_locations_2x;
2905 break;
2906 case 4:
2907 constbuf.user_buffer = sctx->sample_locations_4x;
2908 break;
2909 case 8:
2910 constbuf.user_buffer = sctx->sample_locations_8x;
2911 break;
2912 case 16:
2913 constbuf.user_buffer = sctx->sample_locations_16x;
2914 break;
2915 default:
2916 PRINT_ERR("Requested an invalid number of samples %i.\n",
2917 sctx->framebuffer.nr_samples);
2918 assert(0);
2919 }
2920 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2921 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
2922
2923 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
2924 }
2925
2926 sctx->do_update_shaders = true;
2927
2928 if (!sctx->decompression_enabled) {
2929 /* Prevent textures decompression when the framebuffer state
2930 * changes come from the decompression passes themselves.
2931 */
2932 sctx->need_check_render_feedback = true;
2933 }
2934 }
2935
2936 static void si_emit_framebuffer_state(struct si_context *sctx)
2937 {
2938 struct radeon_winsys_cs *cs = sctx->gfx_cs;
2939 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2940 unsigned i, nr_cbufs = state->nr_cbufs;
2941 struct r600_texture *tex = NULL;
2942 struct r600_surface *cb = NULL;
2943 unsigned cb_color_info = 0;
2944
2945 /* Colorbuffers. */
2946 for (i = 0; i < nr_cbufs; i++) {
2947 uint64_t cb_color_base, cb_color_fmask, cb_color_cmask, cb_dcc_base;
2948 unsigned cb_color_attrib;
2949
2950 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2951 continue;
2952
2953 cb = (struct r600_surface*)state->cbufs[i];
2954 if (!cb) {
2955 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2956 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2957 continue;
2958 }
2959
2960 tex = (struct r600_texture *)cb->base.texture;
2961 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
2962 &tex->resource, RADEON_USAGE_READWRITE,
2963 tex->resource.b.b.nr_samples > 1 ?
2964 RADEON_PRIO_COLOR_BUFFER_MSAA :
2965 RADEON_PRIO_COLOR_BUFFER);
2966
2967 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2968 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
2969 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2970 RADEON_PRIO_CMASK);
2971 }
2972
2973 if (tex->dcc_separate_buffer)
2974 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
2975 tex->dcc_separate_buffer,
2976 RADEON_USAGE_READWRITE,
2977 RADEON_PRIO_DCC);
2978
2979 /* Compute mutable surface parameters. */
2980 cb_color_base = tex->resource.gpu_address >> 8;
2981 cb_color_fmask = 0;
2982 cb_color_cmask = tex->cmask.base_address_reg;
2983 cb_dcc_base = 0;
2984 cb_color_info = cb->cb_color_info | tex->cb_color_info;
2985 cb_color_attrib = cb->cb_color_attrib;
2986
2987 if (cb->base.u.tex.level > 0)
2988 cb_color_info &= C_028C70_FAST_CLEAR;
2989
2990 if (tex->fmask.size) {
2991 cb_color_fmask = (tex->resource.gpu_address + tex->fmask.offset) >> 8;
2992 cb_color_fmask |= tex->fmask.tile_swizzle;
2993 }
2994
2995 /* Set up DCC. */
2996 if (vi_dcc_enabled(tex, cb->base.u.tex.level)) {
2997 bool is_msaa_resolve_dst = state->cbufs[0] &&
2998 state->cbufs[0]->texture->nr_samples > 1 &&
2999 state->cbufs[1] == &cb->base &&
3000 state->cbufs[1]->texture->nr_samples <= 1;
3001
3002 if (!is_msaa_resolve_dst)
3003 cb_color_info |= S_028C70_DCC_ENABLE(1);
3004
3005 cb_dcc_base = ((!tex->dcc_separate_buffer ? tex->resource.gpu_address : 0) +
3006 tex->dcc_offset) >> 8;
3007 cb_dcc_base |= tex->surface.tile_swizzle;
3008 }
3009
3010 if (sctx->chip_class >= GFX9) {
3011 struct gfx9_surf_meta_flags meta;
3012
3013 if (tex->dcc_offset)
3014 meta = tex->surface.u.gfx9.dcc;
3015 else
3016 meta = tex->surface.u.gfx9.cmask;
3017
3018 /* Set mutable surface parameters. */
3019 cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
3020 cb_color_base |= tex->surface.tile_swizzle;
3021 if (!tex->fmask.size)
3022 cb_color_fmask = cb_color_base;
3023 if (cb->base.u.tex.level > 0)
3024 cb_color_cmask = cb_color_base;
3025 cb_color_attrib |= S_028C74_COLOR_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
3026 S_028C74_FMASK_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
3027 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3028 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3029
3030 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 15);
3031 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3032 radeon_emit(cs, S_028C64_BASE_256B(cb_color_base >> 32)); /* CB_COLOR0_BASE_EXT */
3033 radeon_emit(cs, cb->cb_color_attrib2); /* CB_COLOR0_ATTRIB2 */
3034 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3035 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3036 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3037 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3038 radeon_emit(cs, cb_color_cmask); /* CB_COLOR0_CMASK */
3039 radeon_emit(cs, S_028C80_BASE_256B(cb_color_cmask >> 32)); /* CB_COLOR0_CMASK_BASE_EXT */
3040 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3041 radeon_emit(cs, S_028C88_BASE_256B(cb_color_fmask >> 32)); /* CB_COLOR0_FMASK_BASE_EXT */
3042 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3043 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3044 radeon_emit(cs, cb_dcc_base); /* CB_COLOR0_DCC_BASE */
3045 radeon_emit(cs, S_028C98_BASE_256B(cb_dcc_base >> 32)); /* CB_COLOR0_DCC_BASE_EXT */
3046
3047 radeon_set_context_reg(cs, R_0287A0_CB_MRT0_EPITCH + i * 4,
3048 S_0287A0_EPITCH(tex->surface.u.gfx9.surf.epitch));
3049 } else {
3050 /* Compute mutable surface parameters (SI-CI-VI). */
3051 const struct legacy_surf_level *level_info =
3052 &tex->surface.u.legacy.level[cb->base.u.tex.level];
3053 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3054 unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
3055
3056 cb_color_base += level_info->offset >> 8;
3057 /* Only macrotiled modes can set tile swizzle. */
3058 if (level_info->mode == RADEON_SURF_MODE_2D)
3059 cb_color_base |= tex->surface.tile_swizzle;
3060
3061 if (!tex->fmask.size)
3062 cb_color_fmask = cb_color_base;
3063 if (cb->base.u.tex.level > 0)
3064 cb_color_cmask = cb_color_base;
3065 if (cb_dcc_base)
3066 cb_dcc_base += level_info->dcc_offset >> 8;
3067
3068 pitch_tile_max = level_info->nblk_x / 8 - 1;
3069 slice_tile_max = level_info->nblk_x *
3070 level_info->nblk_y / 64 - 1;
3071 tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false);
3072
3073 cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3074 cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3075 cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3076
3077 if (tex->fmask.size) {
3078 if (sctx->chip_class >= CIK)
3079 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->fmask.pitch_in_pixels / 8 - 1);
3080 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->fmask.tile_mode_index);
3081 cb_color_fmask_slice = S_028C88_TILE_MAX(tex->fmask.slice_tile_max);
3082 } else {
3083 /* This must be set for fast clear to work without FMASK. */
3084 if (sctx->chip_class >= CIK)
3085 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3086 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3087 cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3088 }
3089
3090 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
3091 sctx->chip_class >= VI ? 14 : 13);
3092 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3093 radeon_emit(cs, cb_color_pitch); /* CB_COLOR0_PITCH */
3094 radeon_emit(cs, cb_color_slice); /* CB_COLOR0_SLICE */
3095 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3096 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3097 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3098 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3099 radeon_emit(cs, cb_color_cmask); /* CB_COLOR0_CMASK */
3100 radeon_emit(cs, tex->cmask.slice_tile_max); /* CB_COLOR0_CMASK_SLICE */
3101 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3102 radeon_emit(cs, cb_color_fmask_slice); /* CB_COLOR0_FMASK_SLICE */
3103 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3104 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3105
3106 if (sctx->chip_class >= VI) /* R_028C94_CB_COLOR0_DCC_BASE */
3107 radeon_emit(cs, cb_dcc_base);
3108 }
3109 }
3110 for (; i < 8 ; i++)
3111 if (sctx->framebuffer.dirty_cbufs & (1 << i))
3112 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
3113
3114 /* ZS buffer. */
3115 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
3116 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
3117 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
3118
3119 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3120 &rtex->resource, RADEON_USAGE_READWRITE,
3121 zb->base.texture->nr_samples > 1 ?
3122 RADEON_PRIO_DEPTH_BUFFER_MSAA :
3123 RADEON_PRIO_DEPTH_BUFFER);
3124
3125 if (sctx->chip_class >= GFX9) {
3126 radeon_set_context_reg_seq(cs, R_028014_DB_HTILE_DATA_BASE, 3);
3127 radeon_emit(cs, zb->db_htile_data_base); /* DB_HTILE_DATA_BASE */
3128 radeon_emit(cs, S_028018_BASE_HI(zb->db_htile_data_base >> 32)); /* DB_HTILE_DATA_BASE_HI */
3129 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
3130
3131 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 10);
3132 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3133 S_028038_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
3134 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3135 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3136 radeon_emit(cs, S_028044_BASE_HI(zb->db_depth_base >> 32)); /* DB_Z_READ_BASE_HI */
3137 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3138 radeon_emit(cs, S_02804C_BASE_HI(zb->db_stencil_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
3139 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3140 radeon_emit(cs, S_028054_BASE_HI(zb->db_depth_base >> 32)); /* DB_Z_WRITE_BASE_HI */
3141 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3142 radeon_emit(cs, S_02805C_BASE_HI(zb->db_stencil_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
3143
3144 radeon_set_context_reg_seq(cs, R_028068_DB_Z_INFO2, 2);
3145 radeon_emit(cs, zb->db_z_info2); /* DB_Z_INFO2 */
3146 radeon_emit(cs, zb->db_stencil_info2); /* DB_STENCIL_INFO2 */
3147 } else {
3148 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
3149
3150 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
3151 radeon_emit(cs, zb->db_depth_info); /* DB_DEPTH_INFO */
3152 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3153 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
3154 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3155 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3156 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3157 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3158 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3159 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
3160 radeon_emit(cs, zb->db_depth_slice); /* DB_DEPTH_SLICE */
3161 }
3162
3163 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
3164 radeon_emit(cs, rtex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
3165 radeon_emit(cs, fui(rtex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
3166
3167 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
3168 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
3169 } else if (sctx->framebuffer.dirty_zsbuf) {
3170 if (sctx->chip_class >= GFX9)
3171 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 2);
3172 else
3173 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
3174
3175 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
3176 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
3177 }
3178
3179 /* Framebuffer dimensions. */
3180 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
3181 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
3182 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
3183
3184 if (sctx->screen->dfsm_allowed) {
3185 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3186 radeon_emit(cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
3187 }
3188
3189 sctx->framebuffer.dirty_cbufs = 0;
3190 sctx->framebuffer.dirty_zsbuf = false;
3191 }
3192
3193 static void si_emit_msaa_sample_locs(struct si_context *sctx)
3194 {
3195 struct radeon_winsys_cs *cs = sctx->gfx_cs;
3196 unsigned nr_samples = sctx->framebuffer.nr_samples;
3197 bool has_msaa_sample_loc_bug = sctx->screen->has_msaa_sample_loc_bug;
3198
3199 /* Smoothing (only possible with nr_samples == 1) uses the same
3200 * sample locations as the MSAA it simulates.
3201 */
3202 if (nr_samples <= 1 && sctx->smoothing_enabled)
3203 nr_samples = SI_NUM_SMOOTH_AA_SAMPLES;
3204
3205 /* On Polaris, the small primitive filter uses the sample locations
3206 * even when MSAA is off, so we need to make sure they're set to 0.
3207 */
3208 if (has_msaa_sample_loc_bug)
3209 nr_samples = MAX2(nr_samples, 1);
3210
3211 if (nr_samples != sctx->sample_locs_num_samples) {
3212 sctx->sample_locs_num_samples = nr_samples;
3213 si_emit_sample_locations(cs, nr_samples);
3214 }
3215
3216 if (sctx->family >= CHIP_POLARIS10) {
3217 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3218 unsigned small_prim_filter_cntl =
3219 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
3220 /* line bug */
3221 S_028830_LINE_FILTER_DISABLE(sctx->family <= CHIP_POLARIS12);
3222
3223 /* The alternative of setting sample locations to 0 would
3224 * require a DB flush to avoid Z errors, see
3225 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
3226 */
3227 if (has_msaa_sample_loc_bug &&
3228 sctx->framebuffer.nr_samples > 1 &&
3229 rs && !rs->multisample_enable)
3230 small_prim_filter_cntl &= C_028830_SMALL_PRIM_FILTER_ENABLE;
3231
3232 radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
3233 small_prim_filter_cntl);
3234 }
3235 }
3236
3237 static bool si_out_of_order_rasterization(struct si_context *sctx)
3238 {
3239 struct si_state_blend *blend = sctx->queued.named.blend;
3240 struct si_state_dsa *dsa = sctx->queued.named.dsa;
3241
3242 if (!sctx->screen->has_out_of_order_rast)
3243 return false;
3244
3245 unsigned colormask = sctx->framebuffer.colorbuf_enabled_4bit;
3246
3247 if (blend) {
3248 colormask &= blend->cb_target_enabled_4bit;
3249 } else {
3250 colormask = 0;
3251 }
3252
3253 /* Conservative: No logic op. */
3254 if (colormask && blend->logicop_enable)
3255 return false;
3256
3257 struct si_dsa_order_invariance dsa_order_invariant = {
3258 .zs = true, .pass_set = true, .pass_last = false
3259 };
3260
3261 if (sctx->framebuffer.state.zsbuf) {
3262 struct r600_texture *zstex =
3263 (struct r600_texture*)sctx->framebuffer.state.zsbuf->texture;
3264 bool has_stencil = zstex->surface.has_stencil;
3265 dsa_order_invariant = dsa->order_invariance[has_stencil];
3266 if (!dsa_order_invariant.zs)
3267 return false;
3268
3269 /* The set of PS invocations is always order invariant,
3270 * except when early Z/S tests are requested. */
3271 if (sctx->ps_shader.cso &&
3272 sctx->ps_shader.cso->info.writes_memory &&
3273 sctx->ps_shader.cso->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] &&
3274 !dsa_order_invariant.pass_set)
3275 return false;
3276
3277 if (sctx->num_perfect_occlusion_queries != 0 &&
3278 !dsa_order_invariant.pass_set)
3279 return false;
3280 }
3281
3282 if (!colormask)
3283 return true;
3284
3285 unsigned blendmask = colormask & blend->blend_enable_4bit;
3286
3287 if (blendmask) {
3288 /* Only commutative blending. */
3289 if (blendmask & ~blend->commutative_4bit)
3290 return false;
3291
3292 if (!dsa_order_invariant.pass_set)
3293 return false;
3294 }
3295
3296 if (colormask & ~blendmask) {
3297 if (!dsa_order_invariant.pass_last)
3298 return false;
3299 }
3300
3301 return true;
3302 }
3303
3304 static void si_emit_msaa_config(struct si_context *sctx)
3305 {
3306 struct radeon_winsys_cs *cs = sctx->gfx_cs;
3307 unsigned num_tile_pipes = sctx->screen->info.num_tile_pipes;
3308 /* 33% faster rendering to linear color buffers */
3309 bool dst_is_linear = sctx->framebuffer.any_dst_linear;
3310 bool out_of_order_rast = si_out_of_order_rasterization(sctx);
3311 unsigned sc_mode_cntl_1 =
3312 S_028A4C_WALK_SIZE(dst_is_linear) |
3313 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear) |
3314 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
3315 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
3316 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
3317 /* always 1: */
3318 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
3319 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
3320 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
3321 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
3322 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
3323 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
3324
3325 int setup_samples = sctx->framebuffer.nr_samples > 1 ? sctx->framebuffer.nr_samples :
3326 sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0;
3327
3328 /* Required by OpenGL line rasterization.
3329 *
3330 * TODO: We should also enable perpendicular endcaps for AA lines,
3331 * but that requires implementing line stippling in the pixel
3332 * shader. SC can only do line stippling with axis-aligned
3333 * endcaps.
3334 */
3335 unsigned sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
3336
3337 if (setup_samples > 1) {
3338 /* distance from the pixel center, indexed by log2(nr_samples) */
3339 static unsigned max_dist[] = {
3340 0, /* unused */
3341 4, /* 2x MSAA */
3342 6, /* 4x MSAA */
3343 7, /* 8x MSAA */
3344 8, /* 16x MSAA */
3345 };
3346 unsigned log_samples = util_logbase2(setup_samples);
3347 unsigned ps_iter_samples = si_get_ps_iter_samples(sctx);
3348 unsigned log_ps_iter_samples =
3349 util_logbase2(util_next_power_of_two(ps_iter_samples));
3350
3351 radeon_set_context_reg_seq(cs, R_028BDC_PA_SC_LINE_CNTL, 2);
3352 radeon_emit(cs, sc_line_cntl |
3353 S_028BDC_EXPAND_LINE_WIDTH(1)); /* CM_R_028BDC_PA_SC_LINE_CNTL */
3354 radeon_emit(cs, S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
3355 S_028BE0_MAX_SAMPLE_DIST(max_dist[log_samples]) |
3356 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples)); /* CM_R_028BE0_PA_SC_AA_CONFIG */
3357
3358 if (sctx->framebuffer.nr_samples > 1) {
3359 radeon_set_context_reg(cs, R_028804_DB_EQAA,
3360 S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
3361 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
3362 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
3363 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples) |
3364 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3365 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
3366 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1,
3367 S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1) |
3368 sc_mode_cntl_1);
3369 } else if (sctx->smoothing_enabled) {
3370 radeon_set_context_reg(cs, R_028804_DB_EQAA,
3371 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3372 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1) |
3373 S_028804_OVERRASTERIZATION_AMOUNT(log_samples));
3374 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1,
3375 sc_mode_cntl_1);
3376 }
3377 } else {
3378 radeon_set_context_reg_seq(cs, R_028BDC_PA_SC_LINE_CNTL, 2);
3379 radeon_emit(cs, sc_line_cntl); /* CM_R_028BDC_PA_SC_LINE_CNTL */
3380 radeon_emit(cs, 0); /* CM_R_028BE0_PA_SC_AA_CONFIG */
3381
3382 radeon_set_context_reg(cs, R_028804_DB_EQAA,
3383 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3384 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
3385 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1,
3386 sc_mode_cntl_1);
3387 }
3388
3389 /* GFX9: Flush DFSM when the AA mode changes. */
3390 if (sctx->screen->dfsm_allowed) {
3391 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3392 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
3393 }
3394 }
3395
3396 void si_update_ps_iter_samples(struct si_context *sctx)
3397 {
3398 if (sctx->framebuffer.nr_samples > 1)
3399 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3400 if (sctx->screen->dpbb_allowed)
3401 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
3402 }
3403
3404 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
3405 {
3406 struct si_context *sctx = (struct si_context *)ctx;
3407
3408 if (sctx->ps_iter_samples == min_samples)
3409 return;
3410
3411 sctx->ps_iter_samples = min_samples;
3412 sctx->do_update_shaders = true;
3413
3414 si_update_ps_iter_samples(sctx);
3415 }
3416
3417 /*
3418 * Samplers
3419 */
3420
3421 /**
3422 * Build the sampler view descriptor for a buffer texture.
3423 * @param state 256-bit descriptor; only the high 128 bits are filled in
3424 */
3425 void
3426 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
3427 enum pipe_format format,
3428 unsigned offset, unsigned size,
3429 uint32_t *state)
3430 {
3431 const struct util_format_description *desc;
3432 int first_non_void;
3433 unsigned stride;
3434 unsigned num_records;
3435 unsigned num_format, data_format;
3436
3437 desc = util_format_description(format);
3438 first_non_void = util_format_get_first_non_void_channel(format);
3439 stride = desc->block.bits / 8;
3440 num_format = si_translate_buffer_numformat(&screen->b, desc, first_non_void);
3441 data_format = si_translate_buffer_dataformat(&screen->b, desc, first_non_void);
3442
3443 num_records = size / stride;
3444 num_records = MIN2(num_records, (buf->b.b.width0 - offset) / stride);
3445
3446 /* The NUM_RECORDS field has a different meaning depending on the chip,
3447 * instruction type, STRIDE, and SWIZZLE_ENABLE.
3448 *
3449 * SI-CIK:
3450 * - If STRIDE == 0, it's in byte units.
3451 * - If STRIDE != 0, it's in units of STRIDE, used with inst.IDXEN.
3452 *
3453 * VI:
3454 * - For SMEM and STRIDE == 0, it's in byte units.
3455 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3456 * - For VMEM and STRIDE == 0 or SWIZZLE_ENABLE == 0, it's in byte units.
3457 * - For VMEM and STRIDE != 0 and SWIZZLE_ENABLE == 1, it's in units of STRIDE.
3458 * NOTE: There is incompatibility between VMEM and SMEM opcodes due to SWIZZLE_-
3459 * ENABLE. The workaround is to set STRIDE = 0 if SWIZZLE_ENABLE == 0 when
3460 * using SMEM. This can be done in the shader by clearing STRIDE with s_and.
3461 * That way the same descriptor can be used by both SMEM and VMEM.
3462 *
3463 * GFX9:
3464 * - For SMEM and STRIDE == 0, it's in byte units.
3465 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3466 * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
3467 * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
3468 */
3469 if (screen->info.chip_class >= GFX9)
3470 /* When vindex == 0, LLVM sets IDXEN = 0, thus changing units
3471 * from STRIDE to bytes. This works around it by setting
3472 * NUM_RECORDS to at least the size of one element, so that
3473 * the first element is readable when IDXEN == 0.
3474 *
3475 * TODO: Fix this in LLVM, but do we need a new intrinsic where
3476 * IDXEN is enforced?
3477 */
3478 num_records = num_records ? MAX2(num_records, stride) : 0;
3479 else if (screen->info.chip_class == VI)
3480 num_records *= stride;
3481
3482 state[4] = 0;
3483 state[5] = S_008F04_STRIDE(stride);
3484 state[6] = num_records;
3485 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3486 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3487 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3488 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
3489 S_008F0C_NUM_FORMAT(num_format) |
3490 S_008F0C_DATA_FORMAT(data_format);
3491 }
3492
3493 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle[4])
3494 {
3495 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3496
3497 if (swizzle[3] == PIPE_SWIZZLE_X) {
3498 /* For the pre-defined border color values (white, opaque
3499 * black, transparent black), the only thing that matters is
3500 * that the alpha channel winds up in the correct place
3501 * (because the RGB channels are all the same) so either of
3502 * these enumerations will work.
3503 */
3504 if (swizzle[2] == PIPE_SWIZZLE_Y)
3505 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
3506 else
3507 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
3508 } else if (swizzle[0] == PIPE_SWIZZLE_X) {
3509 if (swizzle[1] == PIPE_SWIZZLE_Y)
3510 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3511 else
3512 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
3513 } else if (swizzle[1] == PIPE_SWIZZLE_X) {
3514 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
3515 } else if (swizzle[2] == PIPE_SWIZZLE_X) {
3516 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
3517 }
3518
3519 return bc_swizzle;
3520 }
3521
3522 /**
3523 * Build the sampler view descriptor for a texture.
3524 */
3525 void
3526 si_make_texture_descriptor(struct si_screen *screen,
3527 struct r600_texture *tex,
3528 bool sampler,
3529 enum pipe_texture_target target,
3530 enum pipe_format pipe_format,
3531 const unsigned char state_swizzle[4],
3532 unsigned first_level, unsigned last_level,
3533 unsigned first_layer, unsigned last_layer,
3534 unsigned width, unsigned height, unsigned depth,
3535 uint32_t *state,
3536 uint32_t *fmask_state)
3537 {
3538 struct pipe_resource *res = &tex->resource.b.b;
3539 const struct util_format_description *desc;
3540 unsigned char swizzle[4];
3541 int first_non_void;
3542 unsigned num_format, data_format, type;
3543 uint64_t va;
3544
3545 desc = util_format_description(pipe_format);
3546
3547 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
3548 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
3549 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
3550 const unsigned char swizzle_wwww[4] = {3, 3, 3, 3};
3551
3552 switch (pipe_format) {
3553 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3554 case PIPE_FORMAT_X32_S8X24_UINT:
3555 case PIPE_FORMAT_X8Z24_UNORM:
3556 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3557 break;
3558 case PIPE_FORMAT_X24S8_UINT:
3559 /*
3560 * X24S8 is implemented as an 8_8_8_8 data format, to
3561 * fix texture gathers. This affects at least
3562 * GL45-CTS.texture_cube_map_array.sampling on VI.
3563 */
3564 if (screen->info.chip_class <= VI)
3565 util_format_compose_swizzles(swizzle_wwww, state_swizzle, swizzle);
3566 else
3567 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3568 break;
3569 default:
3570 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
3571 }
3572 } else {
3573 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
3574 }
3575
3576 first_non_void = util_format_get_first_non_void_channel(pipe_format);
3577
3578 switch (pipe_format) {
3579 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3580 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3581 break;
3582 default:
3583 if (first_non_void < 0) {
3584 if (util_format_is_compressed(pipe_format)) {
3585 switch (pipe_format) {
3586 case PIPE_FORMAT_DXT1_SRGB:
3587 case PIPE_FORMAT_DXT1_SRGBA:
3588 case PIPE_FORMAT_DXT3_SRGBA:
3589 case PIPE_FORMAT_DXT5_SRGBA:
3590 case PIPE_FORMAT_BPTC_SRGBA:
3591 case PIPE_FORMAT_ETC2_SRGB8:
3592 case PIPE_FORMAT_ETC2_SRGB8A1:
3593 case PIPE_FORMAT_ETC2_SRGBA8:
3594 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3595 break;
3596 case PIPE_FORMAT_RGTC1_SNORM:
3597 case PIPE_FORMAT_LATC1_SNORM:
3598 case PIPE_FORMAT_RGTC2_SNORM:
3599 case PIPE_FORMAT_LATC2_SNORM:
3600 case PIPE_FORMAT_ETC2_R11_SNORM:
3601 case PIPE_FORMAT_ETC2_RG11_SNORM:
3602 /* implies float, so use SNORM/UNORM to determine
3603 whether data is signed or not */
3604 case PIPE_FORMAT_BPTC_RGB_FLOAT:
3605 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3606 break;
3607 default:
3608 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3609 break;
3610 }
3611 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
3612 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3613 } else {
3614 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3615 }
3616 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
3617 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3618 } else {
3619 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3620
3621 switch (desc->channel[first_non_void].type) {
3622 case UTIL_FORMAT_TYPE_FLOAT:
3623 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3624 break;
3625 case UTIL_FORMAT_TYPE_SIGNED:
3626 if (desc->channel[first_non_void].normalized)
3627 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3628 else if (desc->channel[first_non_void].pure_integer)
3629 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
3630 else
3631 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
3632 break;
3633 case UTIL_FORMAT_TYPE_UNSIGNED:
3634 if (desc->channel[first_non_void].normalized)
3635 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3636 else if (desc->channel[first_non_void].pure_integer)
3637 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3638 else
3639 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
3640 }
3641 }
3642 }
3643
3644 data_format = si_translate_texformat(&screen->b, pipe_format, desc, first_non_void);
3645 if (data_format == ~0) {
3646 data_format = 0;
3647 }
3648
3649 /* S8 with Z32 HTILE needs a special format. */
3650 if (screen->info.chip_class >= GFX9 &&
3651 pipe_format == PIPE_FORMAT_S8_UINT &&
3652 tex->tc_compatible_htile)
3653 data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
3654
3655 if (!sampler &&
3656 (res->target == PIPE_TEXTURE_CUBE ||
3657 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
3658 (screen->info.chip_class <= VI &&
3659 res->target == PIPE_TEXTURE_3D))) {
3660 /* For the purpose of shader images, treat cube maps and 3D
3661 * textures as 2D arrays. For 3D textures, the address
3662 * calculations for mipmaps are different, so we rely on the
3663 * caller to effectively disable mipmaps.
3664 */
3665 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
3666
3667 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
3668 } else {
3669 type = si_tex_dim(screen, tex, target, res->nr_samples);
3670 }
3671
3672 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
3673 height = 1;
3674 depth = res->array_size;
3675 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
3676 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
3677 if (sampler || res->target != PIPE_TEXTURE_3D)
3678 depth = res->array_size;
3679 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
3680 depth = res->array_size / 6;
3681
3682 state[0] = 0;
3683 state[1] = (S_008F14_DATA_FORMAT_GFX6(data_format) |
3684 S_008F14_NUM_FORMAT_GFX6(num_format));
3685 state[2] = (S_008F18_WIDTH(width - 1) |
3686 S_008F18_HEIGHT(height - 1) |
3687 S_008F18_PERF_MOD(4));
3688 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
3689 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
3690 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
3691 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
3692 S_008F1C_BASE_LEVEL(res->nr_samples > 1 ?
3693 0 : first_level) |
3694 S_008F1C_LAST_LEVEL(res->nr_samples > 1 ?
3695 util_logbase2(res->nr_samples) :
3696 last_level) |
3697 S_008F1C_TYPE(type));
3698 state[4] = 0;
3699 state[5] = S_008F24_BASE_ARRAY(first_layer);
3700 state[6] = 0;
3701 state[7] = 0;
3702
3703 if (screen->info.chip_class >= GFX9) {
3704 unsigned bc_swizzle = gfx9_border_color_swizzle(desc->swizzle);
3705
3706 /* Depth is the the last accessible layer on Gfx9.
3707 * The hw doesn't need to know the total number of layers.
3708 */
3709 if (type == V_008F1C_SQ_RSRC_IMG_3D)
3710 state[4] |= S_008F20_DEPTH(depth - 1);
3711 else
3712 state[4] |= S_008F20_DEPTH(last_layer);
3713
3714 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
3715 state[5] |= S_008F24_MAX_MIP(res->nr_samples > 1 ?
3716 util_logbase2(res->nr_samples) :
3717 tex->resource.b.b.last_level);
3718 } else {
3719 state[3] |= S_008F1C_POW2_PAD(res->last_level > 0);
3720 state[4] |= S_008F20_DEPTH(depth - 1);
3721 state[5] |= S_008F24_LAST_ARRAY(last_layer);
3722 }
3723
3724 if (tex->dcc_offset) {
3725 state[6] = S_008F28_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(pipe_format));
3726 } else {
3727 /* The last dword is unused by hw. The shader uses it to clear
3728 * bits in the first dword of sampler state.
3729 */
3730 if (screen->info.chip_class <= CIK && res->nr_samples <= 1) {
3731 if (first_level == last_level)
3732 state[7] = C_008F30_MAX_ANISO_RATIO;
3733 else
3734 state[7] = 0xffffffff;
3735 }
3736 }
3737
3738 /* Initialize the sampler view for FMASK. */
3739 if (tex->fmask.size) {
3740 uint32_t data_format, num_format;
3741
3742 va = tex->resource.gpu_address + tex->fmask.offset;
3743
3744 if (screen->info.chip_class >= GFX9) {
3745 data_format = V_008F14_IMG_DATA_FORMAT_FMASK;
3746 switch (res->nr_samples) {
3747 case 2:
3748 num_format = V_008F14_IMG_FMASK_8_2_2;
3749 break;
3750 case 4:
3751 num_format = V_008F14_IMG_FMASK_8_4_4;
3752 break;
3753 case 8:
3754 num_format = V_008F14_IMG_FMASK_32_8_8;
3755 break;
3756 default:
3757 unreachable("invalid nr_samples");
3758 }
3759 } else {
3760 switch (res->nr_samples) {
3761 case 2:
3762 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
3763 break;
3764 case 4:
3765 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
3766 break;
3767 case 8:
3768 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
3769 break;
3770 default:
3771 unreachable("invalid nr_samples");
3772 }
3773 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3774 }
3775
3776 fmask_state[0] = (va >> 8) | tex->fmask.tile_swizzle;
3777 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
3778 S_008F14_DATA_FORMAT_GFX6(data_format) |
3779 S_008F14_NUM_FORMAT_GFX6(num_format);
3780 fmask_state[2] = S_008F18_WIDTH(width - 1) |
3781 S_008F18_HEIGHT(height - 1);
3782 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
3783 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
3784 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
3785 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
3786 S_008F1C_TYPE(si_tex_dim(screen, tex, target, 0));
3787 fmask_state[4] = 0;
3788 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
3789 fmask_state[6] = 0;
3790 fmask_state[7] = 0;
3791
3792 if (screen->info.chip_class >= GFX9) {
3793 fmask_state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode);
3794 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
3795 S_008F20_PITCH_GFX9(tex->surface.u.gfx9.fmask.epitch);
3796 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned) |
3797 S_008F24_META_RB_ALIGNED(tex->surface.u.gfx9.cmask.rb_aligned);
3798 } else {
3799 fmask_state[3] |= S_008F1C_TILING_INDEX(tex->fmask.tile_mode_index);
3800 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
3801 S_008F20_PITCH_GFX6(tex->fmask.pitch_in_pixels - 1);
3802 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
3803 }
3804 }
3805 }
3806
3807 /**
3808 * Create a sampler view.
3809 *
3810 * @param ctx context
3811 * @param texture texture
3812 * @param state sampler view template
3813 * @param width0 width0 override (for compressed textures as int)
3814 * @param height0 height0 override (for compressed textures as int)
3815 * @param force_level set the base address to the level (for compressed textures)
3816 */
3817 struct pipe_sampler_view *
3818 si_create_sampler_view_custom(struct pipe_context *ctx,
3819 struct pipe_resource *texture,
3820 const struct pipe_sampler_view *state,
3821 unsigned width0, unsigned height0,
3822 unsigned force_level)
3823 {
3824 struct si_context *sctx = (struct si_context*)ctx;
3825 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
3826 struct r600_texture *tmp = (struct r600_texture*)texture;
3827 unsigned base_level, first_level, last_level;
3828 unsigned char state_swizzle[4];
3829 unsigned height, depth, width;
3830 unsigned last_layer = state->u.tex.last_layer;
3831 enum pipe_format pipe_format;
3832 const struct legacy_surf_level *surflevel;
3833
3834 if (!view)
3835 return NULL;
3836
3837 /* initialize base object */
3838 view->base = *state;
3839 view->base.texture = NULL;
3840 view->base.reference.count = 1;
3841 view->base.context = ctx;
3842
3843 assert(texture);
3844 pipe_resource_reference(&view->base.texture, texture);
3845
3846 if (state->format == PIPE_FORMAT_X24S8_UINT ||
3847 state->format == PIPE_FORMAT_S8X24_UINT ||
3848 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
3849 state->format == PIPE_FORMAT_S8_UINT)
3850 view->is_stencil_sampler = true;
3851
3852 /* Buffer resource. */
3853 if (texture->target == PIPE_BUFFER) {
3854 si_make_buffer_descriptor(sctx->screen,
3855 r600_resource(texture),
3856 state->format,
3857 state->u.buf.offset,
3858 state->u.buf.size,
3859 view->state);
3860 return &view->base;
3861 }
3862
3863 state_swizzle[0] = state->swizzle_r;
3864 state_swizzle[1] = state->swizzle_g;
3865 state_swizzle[2] = state->swizzle_b;
3866 state_swizzle[3] = state->swizzle_a;
3867
3868 base_level = 0;
3869 first_level = state->u.tex.first_level;
3870 last_level = state->u.tex.last_level;
3871 width = width0;
3872 height = height0;
3873 depth = texture->depth0;
3874
3875 if (sctx->chip_class <= VI && force_level) {
3876 assert(force_level == first_level &&
3877 force_level == last_level);
3878 base_level = force_level;
3879 first_level = 0;
3880 last_level = 0;
3881 width = u_minify(width, force_level);
3882 height = u_minify(height, force_level);
3883 depth = u_minify(depth, force_level);
3884 }
3885
3886 /* This is not needed if state trackers set last_layer correctly. */
3887 if (state->target == PIPE_TEXTURE_1D ||
3888 state->target == PIPE_TEXTURE_2D ||
3889 state->target == PIPE_TEXTURE_RECT ||
3890 state->target == PIPE_TEXTURE_CUBE)
3891 last_layer = state->u.tex.first_layer;
3892
3893 /* Texturing with separate depth and stencil. */
3894 pipe_format = state->format;
3895
3896 /* Depth/stencil texturing sometimes needs separate texture. */
3897 if (tmp->is_depth && !si_can_sample_zs(tmp, view->is_stencil_sampler)) {
3898 if (!tmp->flushed_depth_texture &&
3899 !si_init_flushed_depth_texture(ctx, texture, NULL)) {
3900 pipe_resource_reference(&view->base.texture, NULL);
3901 FREE(view);
3902 return NULL;
3903 }
3904
3905 assert(tmp->flushed_depth_texture);
3906
3907 /* Override format for the case where the flushed texture
3908 * contains only Z or only S.
3909 */
3910 if (tmp->flushed_depth_texture->resource.b.b.format != tmp->resource.b.b.format)
3911 pipe_format = tmp->flushed_depth_texture->resource.b.b.format;
3912
3913 tmp = tmp->flushed_depth_texture;
3914 }
3915
3916 surflevel = tmp->surface.u.legacy.level;
3917
3918 if (tmp->db_compatible) {
3919 if (!view->is_stencil_sampler)
3920 pipe_format = tmp->db_render_format;
3921
3922 switch (pipe_format) {
3923 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
3924 pipe_format = PIPE_FORMAT_Z32_FLOAT;
3925 break;
3926 case PIPE_FORMAT_X8Z24_UNORM:
3927 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3928 /* Z24 is always stored like this for DB
3929 * compatibility.
3930 */
3931 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
3932 break;
3933 case PIPE_FORMAT_X24S8_UINT:
3934 case PIPE_FORMAT_S8X24_UINT:
3935 case PIPE_FORMAT_X32_S8X24_UINT:
3936 pipe_format = PIPE_FORMAT_S8_UINT;
3937 surflevel = tmp->surface.u.legacy.stencil_level;
3938 break;
3939 default:;
3940 }
3941 }
3942
3943 view->dcc_incompatible =
3944 vi_dcc_formats_are_incompatible(texture,
3945 state->u.tex.first_level,
3946 state->format);
3947
3948 si_make_texture_descriptor(sctx->screen, tmp, true,
3949 state->target, pipe_format, state_swizzle,
3950 first_level, last_level,
3951 state->u.tex.first_layer, last_layer,
3952 width, height, depth,
3953 view->state, view->fmask_state);
3954
3955 unsigned num_format = G_008F14_NUM_FORMAT_GFX6(view->state[1]);
3956 view->is_integer =
3957 num_format == V_008F14_IMG_NUM_FORMAT_USCALED ||
3958 num_format == V_008F14_IMG_NUM_FORMAT_SSCALED ||
3959 num_format == V_008F14_IMG_NUM_FORMAT_UINT ||
3960 num_format == V_008F14_IMG_NUM_FORMAT_SINT;
3961 view->base_level_info = &surflevel[base_level];
3962 view->base_level = base_level;
3963 view->block_width = util_format_get_blockwidth(pipe_format);
3964 return &view->base;
3965 }
3966
3967 static struct pipe_sampler_view *
3968 si_create_sampler_view(struct pipe_context *ctx,
3969 struct pipe_resource *texture,
3970 const struct pipe_sampler_view *state)
3971 {
3972 return si_create_sampler_view_custom(ctx, texture, state,
3973 texture ? texture->width0 : 0,
3974 texture ? texture->height0 : 0, 0);
3975 }
3976
3977 static void si_sampler_view_destroy(struct pipe_context *ctx,
3978 struct pipe_sampler_view *state)
3979 {
3980 struct si_sampler_view *view = (struct si_sampler_view *)state;
3981
3982 pipe_resource_reference(&state->texture, NULL);
3983 FREE(view);
3984 }
3985
3986 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
3987 {
3988 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
3989 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
3990 (linear_filter &&
3991 (wrap == PIPE_TEX_WRAP_CLAMP ||
3992 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
3993 }
3994
3995 static uint32_t si_translate_border_color(struct si_context *sctx,
3996 const struct pipe_sampler_state *state,
3997 const union pipe_color_union *color,
3998 bool is_integer)
3999 {
4000 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
4001 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
4002
4003 if (!wrap_mode_uses_border_color(state->wrap_s, linear_filter) &&
4004 !wrap_mode_uses_border_color(state->wrap_t, linear_filter) &&
4005 !wrap_mode_uses_border_color(state->wrap_r, linear_filter))
4006 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK);
4007
4008 #define simple_border_types(elt) \
4009 do { \
4010 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4011 color->elt[2] == 0 && color->elt[3] == 0) \
4012 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK); \
4013 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4014 color->elt[2] == 0 && color->elt[3] == 1) \
4015 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK); \
4016 if (color->elt[0] == 1 && color->elt[1] == 1 && \
4017 color->elt[2] == 1 && color->elt[3] == 1) \
4018 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE); \
4019 } while (false)
4020
4021 if (is_integer)
4022 simple_border_types(ui);
4023 else
4024 simple_border_types(f);
4025
4026 #undef simple_border_types
4027
4028 int i;
4029
4030 /* Check if the border has been uploaded already. */
4031 for (i = 0; i < sctx->border_color_count; i++)
4032 if (memcmp(&sctx->border_color_table[i], color,
4033 sizeof(*color)) == 0)
4034 break;
4035
4036 if (i >= SI_MAX_BORDER_COLORS) {
4037 /* Getting 4096 unique border colors is very unlikely. */
4038 fprintf(stderr, "radeonsi: The border color table is full. "
4039 "Any new border colors will be just black. "
4040 "Please file a bug.\n");
4041 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK);
4042 }
4043
4044 if (i == sctx->border_color_count) {
4045 /* Upload a new border color. */
4046 memcpy(&sctx->border_color_table[i], color,
4047 sizeof(*color));
4048 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
4049 color, sizeof(*color));
4050 sctx->border_color_count++;
4051 }
4052
4053 return S_008F3C_BORDER_COLOR_PTR(i) |
4054 S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER);
4055 }
4056
4057 static inline int S_FIXED(float value, unsigned frac_bits)
4058 {
4059 return value * (1 << frac_bits);
4060 }
4061
4062 static inline unsigned si_tex_filter(unsigned filter, unsigned max_aniso)
4063 {
4064 if (filter == PIPE_TEX_FILTER_LINEAR)
4065 return max_aniso > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
4066 : V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
4067 else
4068 return max_aniso > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
4069 : V_008F38_SQ_TEX_XY_FILTER_POINT;
4070 }
4071
4072 static inline unsigned si_tex_aniso_filter(unsigned filter)
4073 {
4074 if (filter < 2)
4075 return 0;
4076 if (filter < 4)
4077 return 1;
4078 if (filter < 8)
4079 return 2;
4080 if (filter < 16)
4081 return 3;
4082 return 4;
4083 }
4084
4085 static void *si_create_sampler_state(struct pipe_context *ctx,
4086 const struct pipe_sampler_state *state)
4087 {
4088 struct si_context *sctx = (struct si_context *)ctx;
4089 struct si_screen *sscreen = sctx->screen;
4090 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
4091 unsigned max_aniso = sscreen->force_aniso >= 0 ? sscreen->force_aniso
4092 : state->max_anisotropy;
4093 unsigned max_aniso_ratio = si_tex_aniso_filter(max_aniso);
4094 union pipe_color_union clamped_border_color;
4095
4096 if (!rstate) {
4097 return NULL;
4098 }
4099
4100 #ifdef DEBUG
4101 rstate->magic = SI_SAMPLER_STATE_MAGIC;
4102 #endif
4103 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
4104 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
4105 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
4106 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4107 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
4108 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
4109 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4110 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4111 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
4112 S_008F30_COMPAT_MODE(sctx->chip_class >= VI));
4113 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
4114 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)) |
4115 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4116 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
4117 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter, max_aniso)) |
4118 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter, max_aniso)) |
4119 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
4120 S_008F38_MIP_POINT_PRECLAMP(0) |
4121 S_008F38_DISABLE_LSB_CEIL(sctx->chip_class <= VI) |
4122 S_008F38_FILTER_PREC_FIX(1) |
4123 S_008F38_ANISO_OVERRIDE(sctx->chip_class >= VI));
4124 rstate->val[3] = si_translate_border_color(sctx, state, &state->border_color, false);
4125
4126 /* Create sampler resource for integer textures. */
4127 memcpy(rstate->integer_val, rstate->val, sizeof(rstate->val));
4128 rstate->integer_val[3] = si_translate_border_color(sctx, state, &state->border_color, true);
4129
4130 /* Create sampler resource for upgraded depth textures. */
4131 memcpy(rstate->upgraded_depth_val, rstate->val, sizeof(rstate->val));
4132
4133 for (unsigned i = 0; i < 4; ++i) {
4134 /* Use channel 0 on purpose, so that we can use OPAQUE_WHITE
4135 * when the border color is 1.0. */
4136 clamped_border_color.f[i] = CLAMP(state->border_color.f[0], 0, 1);
4137 }
4138
4139 if (memcmp(&state->border_color, &clamped_border_color, sizeof(clamped_border_color)) == 0)
4140 rstate->upgraded_depth_val[3] |= S_008F3C_UPGRADED_DEPTH(1);
4141 else
4142 rstate->upgraded_depth_val[3] =
4143 si_translate_border_color(sctx, state, &clamped_border_color, false) |
4144 S_008F3C_UPGRADED_DEPTH(1);
4145
4146 return rstate;
4147 }
4148
4149 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
4150 {
4151 struct si_context *sctx = (struct si_context *)ctx;
4152
4153 if (sctx->sample_mask == (uint16_t)sample_mask)
4154 return;
4155
4156 sctx->sample_mask = sample_mask;
4157 si_mark_atom_dirty(sctx, &sctx->atoms.s.sample_mask);
4158 }
4159
4160 static void si_emit_sample_mask(struct si_context *sctx)
4161 {
4162 struct radeon_winsys_cs *cs = sctx->gfx_cs;
4163 unsigned mask = sctx->sample_mask;
4164
4165 /* Needed for line and polygon smoothing as well as for the Polaris
4166 * small primitive filter. We expect the state tracker to take care of
4167 * this for us.
4168 */
4169 assert(mask == 0xffff || sctx->framebuffer.nr_samples > 1 ||
4170 (mask & 1 && sctx->blitter->running));
4171
4172 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
4173 radeon_emit(cs, mask | (mask << 16));
4174 radeon_emit(cs, mask | (mask << 16));
4175 }
4176
4177 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
4178 {
4179 #ifdef DEBUG
4180 struct si_sampler_state *s = state;
4181
4182 assert(s->magic == SI_SAMPLER_STATE_MAGIC);
4183 s->magic = 0;
4184 #endif
4185 free(state);
4186 }
4187
4188 /*
4189 * Vertex elements & buffers
4190 */
4191
4192 static void *si_create_vertex_elements(struct pipe_context *ctx,
4193 unsigned count,
4194 const struct pipe_vertex_element *elements)
4195 {
4196 struct si_screen *sscreen = (struct si_screen*)ctx->screen;
4197 struct si_vertex_elements *v = CALLOC_STRUCT(si_vertex_elements);
4198 bool used[SI_NUM_VERTEX_BUFFERS] = {};
4199 int i;
4200
4201 assert(count <= SI_MAX_ATTRIBS);
4202 if (!v)
4203 return NULL;
4204
4205 v->count = count;
4206 v->desc_list_byte_size = align(count * 16, SI_CPDMA_ALIGNMENT);
4207
4208 for (i = 0; i < count; ++i) {
4209 const struct util_format_description *desc;
4210 const struct util_format_channel_description *channel;
4211 unsigned data_format, num_format;
4212 int first_non_void;
4213 unsigned vbo_index = elements[i].vertex_buffer_index;
4214 unsigned char swizzle[4];
4215
4216 if (vbo_index >= SI_NUM_VERTEX_BUFFERS) {
4217 FREE(v);
4218 return NULL;
4219 }
4220
4221 if (elements[i].instance_divisor) {
4222 v->uses_instance_divisors = true;
4223 v->instance_divisors[i] = elements[i].instance_divisor;
4224
4225 if (v->instance_divisors[i] == 1)
4226 v->instance_divisor_is_one |= 1u << i;
4227 else
4228 v->instance_divisor_is_fetched |= 1u << i;
4229 }
4230
4231 if (!used[vbo_index]) {
4232 v->first_vb_use_mask |= 1 << i;
4233 used[vbo_index] = true;
4234 }
4235
4236 desc = util_format_description(elements[i].src_format);
4237 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
4238 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
4239 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
4240 channel = first_non_void >= 0 ? &desc->channel[first_non_void] : NULL;
4241 memcpy(swizzle, desc->swizzle, sizeof(swizzle));
4242
4243 v->format_size[i] = desc->block.bits / 8;
4244 v->src_offset[i] = elements[i].src_offset;
4245 v->vertex_buffer_index[i] = vbo_index;
4246
4247 /* The hardware always treats the 2-bit alpha channel as
4248 * unsigned, so a shader workaround is needed. The affected
4249 * chips are VI and older except Stoney (GFX8.1).
4250 */
4251 if (data_format == V_008F0C_BUF_DATA_FORMAT_2_10_10_10 &&
4252 sscreen->info.chip_class <= VI &&
4253 sscreen->info.family != CHIP_STONEY) {
4254 if (num_format == V_008F0C_BUF_NUM_FORMAT_SNORM) {
4255 v->fix_fetch[i] = SI_FIX_FETCH_A2_SNORM;
4256 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SSCALED) {
4257 v->fix_fetch[i] = SI_FIX_FETCH_A2_SSCALED;
4258 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SINT) {
4259 /* This isn't actually used in OpenGL. */
4260 v->fix_fetch[i] = SI_FIX_FETCH_A2_SINT;
4261 }
4262 } else if (channel && channel->type == UTIL_FORMAT_TYPE_FIXED) {
4263 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
4264 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_FIXED;
4265 else
4266 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_FIXED;
4267 } else if (channel && channel->size == 32 && !channel->pure_integer) {
4268 if (channel->type == UTIL_FORMAT_TYPE_SIGNED) {
4269 if (channel->normalized) {
4270 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
4271 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_SNORM;
4272 else
4273 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SNORM;
4274 } else {
4275 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SSCALED;
4276 }
4277 } else if (channel->type == UTIL_FORMAT_TYPE_UNSIGNED) {
4278 if (channel->normalized) {
4279 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
4280 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_UNORM;
4281 else
4282 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_UNORM;
4283 } else {
4284 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_USCALED;
4285 }
4286 }
4287 } else if (channel && channel->size == 64 &&
4288 channel->type == UTIL_FORMAT_TYPE_FLOAT) {
4289 switch (desc->nr_channels) {
4290 case 1:
4291 case 2:
4292 v->fix_fetch[i] = SI_FIX_FETCH_RG_64_FLOAT;
4293 swizzle[0] = PIPE_SWIZZLE_X;
4294 swizzle[1] = PIPE_SWIZZLE_Y;
4295 swizzle[2] = desc->nr_channels == 2 ? PIPE_SWIZZLE_Z : PIPE_SWIZZLE_0;
4296 swizzle[3] = desc->nr_channels == 2 ? PIPE_SWIZZLE_W : PIPE_SWIZZLE_0;
4297 break;
4298 case 3:
4299 v->fix_fetch[i] = SI_FIX_FETCH_RGB_64_FLOAT;
4300 swizzle[0] = PIPE_SWIZZLE_X; /* 3 loads */
4301 swizzle[1] = PIPE_SWIZZLE_Y;
4302 swizzle[2] = PIPE_SWIZZLE_0;
4303 swizzle[3] = PIPE_SWIZZLE_0;
4304 break;
4305 case 4:
4306 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_64_FLOAT;
4307 swizzle[0] = PIPE_SWIZZLE_X; /* 2 loads */
4308 swizzle[1] = PIPE_SWIZZLE_Y;
4309 swizzle[2] = PIPE_SWIZZLE_Z;
4310 swizzle[3] = PIPE_SWIZZLE_W;
4311 break;
4312 default:
4313 assert(0);
4314 }
4315 } else if (channel && desc->nr_channels == 3) {
4316 assert(desc->swizzle[0] == PIPE_SWIZZLE_X);
4317
4318 if (channel->size == 8) {
4319 if (channel->pure_integer)
4320 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8_INT;
4321 else
4322 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8;
4323 } else if (channel->size == 16) {
4324 if (channel->pure_integer)
4325 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16_INT;
4326 else
4327 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16;
4328 }
4329 }
4330
4331 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
4332 S_008F0C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
4333 S_008F0C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
4334 S_008F0C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
4335 S_008F0C_NUM_FORMAT(num_format) |
4336 S_008F0C_DATA_FORMAT(data_format);
4337 }
4338 return v;
4339 }
4340
4341 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
4342 {
4343 struct si_context *sctx = (struct si_context *)ctx;
4344 struct si_vertex_elements *old = sctx->vertex_elements;
4345 struct si_vertex_elements *v = (struct si_vertex_elements*)state;
4346
4347 sctx->vertex_elements = v;
4348 sctx->vertex_buffers_dirty = true;
4349
4350 if (v &&
4351 (!old ||
4352 old->count != v->count ||
4353 old->uses_instance_divisors != v->uses_instance_divisors ||
4354 v->uses_instance_divisors || /* we don't check which divisors changed */
4355 memcmp(old->fix_fetch, v->fix_fetch, sizeof(v->fix_fetch[0]) * v->count)))
4356 sctx->do_update_shaders = true;
4357
4358 if (v && v->instance_divisor_is_fetched) {
4359 struct pipe_constant_buffer cb;
4360
4361 cb.buffer = NULL;
4362 cb.user_buffer = v->instance_divisors;
4363 cb.buffer_offset = 0;
4364 cb.buffer_size = sizeof(uint32_t) * v->count;
4365 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS, &cb);
4366 }
4367 }
4368
4369 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
4370 {
4371 struct si_context *sctx = (struct si_context *)ctx;
4372
4373 if (sctx->vertex_elements == state)
4374 sctx->vertex_elements = NULL;
4375 FREE(state);
4376 }
4377
4378 static void si_set_vertex_buffers(struct pipe_context *ctx,
4379 unsigned start_slot, unsigned count,
4380 const struct pipe_vertex_buffer *buffers)
4381 {
4382 struct si_context *sctx = (struct si_context *)ctx;
4383 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
4384 int i;
4385
4386 assert(start_slot + count <= ARRAY_SIZE(sctx->vertex_buffer));
4387
4388 if (buffers) {
4389 for (i = 0; i < count; i++) {
4390 const struct pipe_vertex_buffer *src = buffers + i;
4391 struct pipe_vertex_buffer *dsti = dst + i;
4392 struct pipe_resource *buf = src->buffer.resource;
4393
4394 pipe_resource_reference(&dsti->buffer.resource, buf);
4395 dsti->buffer_offset = src->buffer_offset;
4396 dsti->stride = src->stride;
4397 si_context_add_resource_size(sctx, buf);
4398 if (buf)
4399 r600_resource(buf)->bind_history |= PIPE_BIND_VERTEX_BUFFER;
4400 }
4401 } else {
4402 for (i = 0; i < count; i++) {
4403 pipe_resource_reference(&dst[i].buffer.resource, NULL);
4404 }
4405 }
4406 sctx->vertex_buffers_dirty = true;
4407 }
4408
4409 /*
4410 * Misc
4411 */
4412
4413 static void si_set_tess_state(struct pipe_context *ctx,
4414 const float default_outer_level[4],
4415 const float default_inner_level[2])
4416 {
4417 struct si_context *sctx = (struct si_context *)ctx;
4418 struct pipe_constant_buffer cb;
4419 float array[8];
4420
4421 memcpy(array, default_outer_level, sizeof(float) * 4);
4422 memcpy(array+4, default_inner_level, sizeof(float) * 2);
4423
4424 cb.buffer = NULL;
4425 cb.user_buffer = NULL;
4426 cb.buffer_size = sizeof(array);
4427
4428 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
4429 (void*)array, sizeof(array),
4430 &cb.buffer_offset);
4431
4432 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
4433 pipe_resource_reference(&cb.buffer, NULL);
4434 }
4435
4436 static void si_texture_barrier(struct pipe_context *ctx, unsigned flags)
4437 {
4438 struct si_context *sctx = (struct si_context *)ctx;
4439
4440 si_update_fb_dirtiness_after_rendering(sctx);
4441
4442 /* Multisample surfaces are flushed in si_decompress_textures. */
4443 if (sctx->framebuffer.uncompressed_cb_mask)
4444 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
4445 sctx->framebuffer.CB_has_shader_readable_metadata);
4446 }
4447
4448 /* This only ensures coherency for shader image/buffer stores. */
4449 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
4450 {
4451 struct si_context *sctx = (struct si_context *)ctx;
4452
4453 /* Subsequent commands must wait for all shader invocations to
4454 * complete. */
4455 sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
4456 SI_CONTEXT_CS_PARTIAL_FLUSH;
4457
4458 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
4459 sctx->flags |= SI_CONTEXT_INV_SMEM_L1 |
4460 SI_CONTEXT_INV_VMEM_L1;
4461
4462 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
4463 PIPE_BARRIER_SHADER_BUFFER |
4464 PIPE_BARRIER_TEXTURE |
4465 PIPE_BARRIER_IMAGE |
4466 PIPE_BARRIER_STREAMOUT_BUFFER |
4467 PIPE_BARRIER_GLOBAL_BUFFER)) {
4468 /* As far as I can tell, L1 contents are written back to L2
4469 * automatically at end of shader, but the contents of other
4470 * L1 caches might still be stale. */
4471 sctx->flags |= SI_CONTEXT_INV_VMEM_L1;
4472 }
4473
4474 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
4475 /* Indices are read through TC L2 since VI.
4476 * L1 isn't used.
4477 */
4478 if (sctx->screen->info.chip_class <= CIK)
4479 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4480 }
4481
4482 /* MSAA color, any depth and any stencil are flushed in
4483 * si_decompress_textures when needed.
4484 */
4485 if (flags & PIPE_BARRIER_FRAMEBUFFER &&
4486 sctx->framebuffer.uncompressed_cb_mask) {
4487 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
4488
4489 if (sctx->chip_class <= VI)
4490 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4491 }
4492
4493 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
4494 if (sctx->screen->info.chip_class <= VI &&
4495 flags & PIPE_BARRIER_INDIRECT_BUFFER)
4496 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4497 }
4498
4499 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
4500 {
4501 struct pipe_blend_state blend;
4502
4503 memset(&blend, 0, sizeof(blend));
4504 blend.independent_blend_enable = true;
4505 blend.rt[0].colormask = 0xf;
4506 return si_create_blend_state_mode(&sctx->b, &blend, mode);
4507 }
4508
4509 static void si_init_config(struct si_context *sctx);
4510
4511 void si_init_state_functions(struct si_context *sctx)
4512 {
4513 sctx->atoms.s.framebuffer.emit = si_emit_framebuffer_state;
4514 sctx->atoms.s.msaa_sample_locs.emit = si_emit_msaa_sample_locs;
4515 sctx->atoms.s.db_render_state.emit = si_emit_db_render_state;
4516 sctx->atoms.s.dpbb_state.emit = si_emit_dpbb_state;
4517 sctx->atoms.s.msaa_config.emit = si_emit_msaa_config;
4518 sctx->atoms.s.sample_mask.emit = si_emit_sample_mask;
4519 sctx->atoms.s.cb_render_state.emit = si_emit_cb_render_state;
4520 sctx->atoms.s.blend_color.emit = si_emit_blend_color;
4521 sctx->atoms.s.clip_regs.emit = si_emit_clip_regs;
4522 sctx->atoms.s.clip_state.emit = si_emit_clip_state;
4523 sctx->atoms.s.stencil_ref.emit = si_emit_stencil_ref;
4524
4525 sctx->b.create_blend_state = si_create_blend_state;
4526 sctx->b.bind_blend_state = si_bind_blend_state;
4527 sctx->b.delete_blend_state = si_delete_blend_state;
4528 sctx->b.set_blend_color = si_set_blend_color;
4529
4530 sctx->b.create_rasterizer_state = si_create_rs_state;
4531 sctx->b.bind_rasterizer_state = si_bind_rs_state;
4532 sctx->b.delete_rasterizer_state = si_delete_rs_state;
4533
4534 sctx->b.create_depth_stencil_alpha_state = si_create_dsa_state;
4535 sctx->b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
4536 sctx->b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
4537
4538 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
4539 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
4540 sctx->custom_blend_fmask_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
4541 sctx->custom_blend_eliminate_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
4542 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
4543
4544 sctx->b.set_clip_state = si_set_clip_state;
4545 sctx->b.set_stencil_ref = si_set_stencil_ref;
4546
4547 sctx->b.set_framebuffer_state = si_set_framebuffer_state;
4548
4549 sctx->b.create_sampler_state = si_create_sampler_state;
4550 sctx->b.delete_sampler_state = si_delete_sampler_state;
4551
4552 sctx->b.create_sampler_view = si_create_sampler_view;
4553 sctx->b.sampler_view_destroy = si_sampler_view_destroy;
4554
4555 sctx->b.set_sample_mask = si_set_sample_mask;
4556
4557 sctx->b.create_vertex_elements_state = si_create_vertex_elements;
4558 sctx->b.bind_vertex_elements_state = si_bind_vertex_elements;
4559 sctx->b.delete_vertex_elements_state = si_delete_vertex_element;
4560 sctx->b.set_vertex_buffers = si_set_vertex_buffers;
4561
4562 sctx->b.texture_barrier = si_texture_barrier;
4563 sctx->b.memory_barrier = si_memory_barrier;
4564 sctx->b.set_min_samples = si_set_min_samples;
4565 sctx->b.set_tess_state = si_set_tess_state;
4566
4567 sctx->b.set_active_query_state = si_set_active_query_state;
4568
4569 sctx->b.draw_vbo = si_draw_vbo;
4570
4571 si_init_config(sctx);
4572 }
4573
4574 void si_init_screen_state_functions(struct si_screen *sscreen)
4575 {
4576 sscreen->b.is_format_supported = si_is_format_supported;
4577 }
4578
4579 static void si_set_grbm_gfx_index(struct si_context *sctx,
4580 struct si_pm4_state *pm4, unsigned value)
4581 {
4582 unsigned reg = sctx->chip_class >= CIK ? R_030800_GRBM_GFX_INDEX :
4583 R_00802C_GRBM_GFX_INDEX;
4584 si_pm4_set_reg(pm4, reg, value);
4585 }
4586
4587 static void si_set_grbm_gfx_index_se(struct si_context *sctx,
4588 struct si_pm4_state *pm4, unsigned se)
4589 {
4590 assert(se == ~0 || se < sctx->screen->info.max_se);
4591 si_set_grbm_gfx_index(sctx, pm4,
4592 (se == ~0 ? S_030800_SE_BROADCAST_WRITES(1) :
4593 S_030800_SE_INDEX(se)) |
4594 S_030800_SH_BROADCAST_WRITES(1) |
4595 S_030800_INSTANCE_BROADCAST_WRITES(1));
4596 }
4597
4598 static void
4599 si_write_harvested_raster_configs(struct si_context *sctx,
4600 struct si_pm4_state *pm4,
4601 unsigned raster_config,
4602 unsigned raster_config_1)
4603 {
4604 unsigned num_se = MAX2(sctx->screen->info.max_se, 1);
4605 unsigned raster_config_se[4];
4606 unsigned se;
4607
4608 ac_get_harvested_configs(&sctx->screen->info,
4609 raster_config,
4610 &raster_config_1,
4611 raster_config_se);
4612
4613 for (se = 0; se < num_se; se++) {
4614 si_set_grbm_gfx_index_se(sctx, pm4, se);
4615 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se[se]);
4616 }
4617 si_set_grbm_gfx_index(sctx, pm4, ~0);
4618
4619 if (sctx->chip_class >= CIK) {
4620 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
4621 }
4622 }
4623
4624 static void si_set_raster_config(struct si_context *sctx, struct si_pm4_state *pm4)
4625 {
4626 unsigned num_rb = MIN2(sctx->screen->info.num_render_backends, 16);
4627 unsigned rb_mask = sctx->screen->info.enabled_rb_mask;
4628 unsigned raster_config, raster_config_1;
4629
4630 ac_get_raster_config(&sctx->screen->info,
4631 &raster_config,
4632 &raster_config_1);
4633
4634 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
4635 /* Always use the default config when all backends are enabled
4636 * (or when we failed to determine the enabled backends).
4637 */
4638 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
4639 raster_config);
4640 if (sctx->chip_class >= CIK)
4641 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
4642 raster_config_1);
4643 } else {
4644 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
4645 }
4646 }
4647
4648 static void si_init_config(struct si_context *sctx)
4649 {
4650 struct si_screen *sscreen = sctx->screen;
4651 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
4652 bool has_clear_state = sscreen->has_clear_state;
4653 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
4654
4655 /* Only SI can disable CLEAR_STATE for now. */
4656 assert(has_clear_state || sscreen->info.chip_class == SI);
4657
4658 if (!pm4)
4659 return;
4660
4661 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
4662 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
4663 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
4664 si_pm4_cmd_end(pm4, false);
4665
4666 if (has_clear_state) {
4667 si_pm4_cmd_begin(pm4, PKT3_CLEAR_STATE);
4668 si_pm4_cmd_add(pm4, 0);
4669 si_pm4_cmd_end(pm4, false);
4670 }
4671
4672 if (sctx->chip_class <= VI)
4673 si_set_raster_config(sctx, pm4);
4674
4675 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
4676 if (!has_clear_state)
4677 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
4678
4679 /* FIXME calculate these values somehow ??? */
4680 if (sctx->chip_class <= VI) {
4681 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
4682 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
4683 }
4684
4685 if (!has_clear_state) {
4686 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
4687 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
4688 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
4689 }
4690
4691 si_pm4_set_reg(pm4, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
4692 if (!has_clear_state)
4693 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
4694 if (sctx->chip_class < CIK)
4695 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
4696 S_008A14_CLIP_VTX_REORDER_ENA(1));
4697
4698 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
4699 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
4700
4701 if (!has_clear_state)
4702 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
4703
4704 /* CLEAR_STATE doesn't clear these correctly on certain generations.
4705 * I don't know why. Deduced by trial and error.
4706 */
4707 if (sctx->chip_class <= CIK) {
4708 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
4709 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
4710 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
4711 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
4712 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
4713 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
4714 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
4715 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
4716 }
4717
4718 if (!has_clear_state) {
4719 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
4720 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
4721 S_028230_ER_TRI(0xA) |
4722 S_028230_ER_POINT(0xA) |
4723 S_028230_ER_RECT(0xA) |
4724 /* Required by DX10_DIAMOND_TEST_ENA: */
4725 S_028230_ER_LINE_LR(0x1A) |
4726 S_028230_ER_LINE_RL(0x26) |
4727 S_028230_ER_LINE_TB(0xA) |
4728 S_028230_ER_LINE_BT(0xA));
4729 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
4730 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
4731 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
4732 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
4733 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
4734 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
4735 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 0);
4736 }
4737
4738 if (sctx->chip_class >= GFX9) {
4739 si_pm4_set_reg(pm4, R_030920_VGT_MAX_VTX_INDX, ~0);
4740 si_pm4_set_reg(pm4, R_030924_VGT_MIN_VTX_INDX, 0);
4741 si_pm4_set_reg(pm4, R_030928_VGT_INDX_OFFSET, 0);
4742 } else {
4743 /* These registers, when written, also overwrite the CLEAR_STATE
4744 * context, so we can't rely on CLEAR_STATE setting them.
4745 * It would be an issue if there was another UMD changing them.
4746 */
4747 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
4748 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
4749 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
4750 }
4751
4752 if (sctx->chip_class >= CIK) {
4753 if (sctx->chip_class >= GFX9) {
4754 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
4755 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
4756 } else {
4757 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS,
4758 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
4759 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
4760 S_00B41C_WAVE_LIMIT(0x3F));
4761 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES,
4762 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
4763
4764 /* If this is 0, Bonaire can hang even if GS isn't being used.
4765 * Other chips are unaffected. These are suboptimal values,
4766 * but we don't use on-chip GS.
4767 */
4768 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
4769 S_028A44_ES_VERTS_PER_SUBGRP(64) |
4770 S_028A44_GS_PRIMS_PER_SUBGRP(4));
4771 }
4772 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
4773 S_00B21C_CU_EN(0xffff) | S_00B21C_WAVE_LIMIT(0x3F));
4774
4775 /* Compute LATE_ALLOC_VS.LIMIT. */
4776 unsigned num_cu_per_sh = sscreen->info.num_good_compute_units /
4777 (sscreen->info.max_se *
4778 sscreen->info.max_sh_per_se);
4779 unsigned late_alloc_limit; /* The limit is per SH. */
4780
4781 if (sctx->family == CHIP_KABINI) {
4782 late_alloc_limit = 0; /* Potential hang on Kabini. */
4783 } else if (num_cu_per_sh <= 4) {
4784 /* Too few available compute units per SH. Disallowing
4785 * VS to run on one CU could hurt us more than late VS
4786 * allocation would help.
4787 *
4788 * 2 is the highest safe number that allows us to keep
4789 * all CUs enabled.
4790 */
4791 late_alloc_limit = 2;
4792 } else {
4793 /* This is a good initial value, allowing 1 late_alloc
4794 * wave per SIMD on num_cu - 2.
4795 */
4796 late_alloc_limit = (num_cu_per_sh - 2) * 4;
4797
4798 /* The limit is 0-based, so 0 means 1. */
4799 assert(late_alloc_limit > 0 && late_alloc_limit <= 64);
4800 late_alloc_limit -= 1;
4801 }
4802
4803 /* VS can't execute on one CU if the limit is > 2. */
4804 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
4805 S_00B118_CU_EN(late_alloc_limit > 2 ? 0xfffe : 0xffff) |
4806 S_00B118_WAVE_LIMIT(0x3F));
4807 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS,
4808 S_00B11C_LIMIT(late_alloc_limit));
4809 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
4810 S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
4811 }
4812
4813 if (sctx->chip_class >= VI) {
4814 unsigned vgt_tess_distribution;
4815
4816 vgt_tess_distribution =
4817 S_028B50_ACCUM_ISOLINE(32) |
4818 S_028B50_ACCUM_TRI(11) |
4819 S_028B50_ACCUM_QUAD(11) |
4820 S_028B50_DONUT_SPLIT(16);
4821
4822 /* Testing with Unigine Heaven extreme tesselation yielded best results
4823 * with TRAP_SPLIT = 3.
4824 */
4825 if (sctx->family == CHIP_FIJI ||
4826 sctx->family >= CHIP_POLARIS10)
4827 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
4828
4829 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution);
4830 } else if (!has_clear_state) {
4831 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
4832 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
4833 }
4834
4835 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
4836 if (sctx->chip_class >= CIK) {
4837 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI,
4838 S_028084_ADDRESS(border_color_va >> 40));
4839 }
4840 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
4841 RADEON_PRIO_BORDER_COLORS);
4842
4843 if (sctx->chip_class >= GFX9) {
4844 unsigned num_se = sscreen->info.max_se;
4845 unsigned pc_lines = 0;
4846
4847 switch (sctx->family) {
4848 case CHIP_VEGA10:
4849 case CHIP_VEGA12:
4850 pc_lines = 4096;
4851 break;
4852 case CHIP_RAVEN:
4853 pc_lines = 1024;
4854 break;
4855 default:
4856 assert(0);
4857 }
4858
4859 si_pm4_set_reg(pm4, R_028C48_PA_SC_BINNER_CNTL_1,
4860 S_028C48_MAX_ALLOC_COUNT(MIN2(128, pc_lines / (4 * num_se))) |
4861 S_028C48_MAX_PRIM_PER_BATCH(1023));
4862 si_pm4_set_reg(pm4, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
4863 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
4864 si_pm4_set_reg(pm4, R_030968_VGT_INSTANCE_BASE_ID, 0);
4865 }
4866
4867 si_pm4_upload_indirect_buffer(sctx, pm4);
4868 sctx->init_config = pm4;
4869 }