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gallium/radeon: make S_FIXED function signed and move it to shared code
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "sid.h"
29 #include "gfx9d.h"
30 #include "radeon/r600_cs.h"
31 #include "radeon/r600_query.h"
32
33 #include "util/u_dual_blend.h"
34 #include "util/u_format.h"
35 #include "util/u_format_s3tc.h"
36 #include "util/u_memory.h"
37 #include "util/u_resource.h"
38 #include "util/u_upload_mgr.h"
39
40 /* Initialize an external atom (owned by ../radeon). */
41 static void
42 si_init_external_atom(struct si_context *sctx, struct r600_atom *atom,
43 struct r600_atom **list_elem)
44 {
45 atom->id = list_elem - sctx->atoms.array;
46 *list_elem = atom;
47 }
48
49 /* Initialize an atom owned by radeonsi. */
50 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
51 struct r600_atom **list_elem,
52 void (*emit_func)(struct si_context *ctx, struct r600_atom *state))
53 {
54 atom->emit = (void*)emit_func;
55 atom->id = list_elem - sctx->atoms.array;
56 *list_elem = atom;
57 }
58
59 static unsigned si_map_swizzle(unsigned swizzle)
60 {
61 switch (swizzle) {
62 case PIPE_SWIZZLE_Y:
63 return V_008F0C_SQ_SEL_Y;
64 case PIPE_SWIZZLE_Z:
65 return V_008F0C_SQ_SEL_Z;
66 case PIPE_SWIZZLE_W:
67 return V_008F0C_SQ_SEL_W;
68 case PIPE_SWIZZLE_0:
69 return V_008F0C_SQ_SEL_0;
70 case PIPE_SWIZZLE_1:
71 return V_008F0C_SQ_SEL_1;
72 default: /* PIPE_SWIZZLE_X */
73 return V_008F0C_SQ_SEL_X;
74 }
75 }
76
77 /* 12.4 fixed-point */
78 static unsigned si_pack_float_12p4(float x)
79 {
80 return x <= 0 ? 0 :
81 x >= 4096 ? 0xffff : x * 16;
82 }
83
84 /*
85 * Inferred framebuffer and blender state.
86 *
87 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
88 * if there is not enough PS outputs.
89 */
90 static void si_emit_cb_render_state(struct si_context *sctx, struct r600_atom *atom)
91 {
92 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
93 struct si_state_blend *blend = sctx->queued.named.blend;
94 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
95 * but you never know. */
96 uint32_t cb_target_mask = sctx->framebuffer.colorbuf_enabled_4bit;
97 unsigned i;
98
99 if (blend)
100 cb_target_mask &= blend->cb_target_mask;
101
102 /* Avoid a hang that happens when dual source blending is enabled
103 * but there is not enough color outputs. This is undefined behavior,
104 * so disable color writes completely.
105 *
106 * Reproducible with Unigine Heaven 4.0 and drirc missing.
107 */
108 if (blend && blend->dual_src_blend &&
109 sctx->ps_shader.cso &&
110 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
111 cb_target_mask = 0;
112
113 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, cb_target_mask);
114
115 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
116 * I think we don't have to do anything between IBs.
117 */
118 if (sctx->b.chip_class >= GFX9 &&
119 sctx->last_cb_target_mask != cb_target_mask) {
120 sctx->last_cb_target_mask = cb_target_mask;
121
122 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
123 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
124 }
125
126 /* RB+ register settings. */
127 if (sctx->screen->b.rbplus_allowed) {
128 unsigned spi_shader_col_format =
129 sctx->ps_shader.cso ?
130 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format : 0;
131 unsigned sx_ps_downconvert = 0;
132 unsigned sx_blend_opt_epsilon = 0;
133 unsigned sx_blend_opt_control = 0;
134
135 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
136 struct r600_surface *surf =
137 (struct r600_surface*)sctx->framebuffer.state.cbufs[i];
138 unsigned format, swap, spi_format, colormask;
139 bool has_alpha, has_rgb;
140
141 if (!surf)
142 continue;
143
144 format = G_028C70_FORMAT(surf->cb_color_info);
145 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
146 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
147 colormask = (cb_target_mask >> (i * 4)) & 0xf;
148
149 /* Set if RGB and A are present. */
150 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
151
152 if (format == V_028C70_COLOR_8 ||
153 format == V_028C70_COLOR_16 ||
154 format == V_028C70_COLOR_32)
155 has_rgb = !has_alpha;
156 else
157 has_rgb = true;
158
159 /* Check the colormask and export format. */
160 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
161 has_rgb = false;
162 if (!(colormask & PIPE_MASK_A))
163 has_alpha = false;
164
165 if (spi_format == V_028714_SPI_SHADER_ZERO) {
166 has_rgb = false;
167 has_alpha = false;
168 }
169
170 /* Disable value checking for disabled channels. */
171 if (!has_rgb)
172 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
173 if (!has_alpha)
174 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
175
176 /* Enable down-conversion for 32bpp and smaller formats. */
177 switch (format) {
178 case V_028C70_COLOR_8:
179 case V_028C70_COLOR_8_8:
180 case V_028C70_COLOR_8_8_8_8:
181 /* For 1 and 2-channel formats, use the superset thereof. */
182 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
183 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
184 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
185 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
186 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
187 }
188 break;
189
190 case V_028C70_COLOR_5_6_5:
191 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
192 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
193 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
194 }
195 break;
196
197 case V_028C70_COLOR_1_5_5_5:
198 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
199 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
200 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
201 }
202 break;
203
204 case V_028C70_COLOR_4_4_4_4:
205 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
206 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
207 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
208 }
209 break;
210
211 case V_028C70_COLOR_32:
212 if (swap == V_0280A0_SWAP_STD &&
213 spi_format == V_028714_SPI_SHADER_32_R)
214 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
215 else if (swap == V_0280A0_SWAP_ALT_REV &&
216 spi_format == V_028714_SPI_SHADER_32_AR)
217 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
218 break;
219
220 case V_028C70_COLOR_16:
221 case V_028C70_COLOR_16_16:
222 /* For 1-channel formats, use the superset thereof. */
223 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
224 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
225 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
226 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
227 if (swap == V_0280A0_SWAP_STD ||
228 swap == V_0280A0_SWAP_STD_REV)
229 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
230 else
231 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
232 }
233 break;
234
235 case V_028C70_COLOR_10_11_11:
236 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
237 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
238 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
239 }
240 break;
241
242 case V_028C70_COLOR_2_10_10_10:
243 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
244 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
245 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
246 }
247 break;
248 }
249 }
250
251 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
252 radeon_emit(cs, sx_ps_downconvert); /* R_028754_SX_PS_DOWNCONVERT */
253 radeon_emit(cs, sx_blend_opt_epsilon); /* R_028758_SX_BLEND_OPT_EPSILON */
254 radeon_emit(cs, sx_blend_opt_control); /* R_02875C_SX_BLEND_OPT_CONTROL */
255 } else if (sctx->screen->b.has_rbplus) {
256 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
257 radeon_emit(cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
258 radeon_emit(cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
259 radeon_emit(cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
260 }
261 }
262
263 /*
264 * Blender functions
265 */
266
267 static uint32_t si_translate_blend_function(int blend_func)
268 {
269 switch (blend_func) {
270 case PIPE_BLEND_ADD:
271 return V_028780_COMB_DST_PLUS_SRC;
272 case PIPE_BLEND_SUBTRACT:
273 return V_028780_COMB_SRC_MINUS_DST;
274 case PIPE_BLEND_REVERSE_SUBTRACT:
275 return V_028780_COMB_DST_MINUS_SRC;
276 case PIPE_BLEND_MIN:
277 return V_028780_COMB_MIN_DST_SRC;
278 case PIPE_BLEND_MAX:
279 return V_028780_COMB_MAX_DST_SRC;
280 default:
281 R600_ERR("Unknown blend function %d\n", blend_func);
282 assert(0);
283 break;
284 }
285 return 0;
286 }
287
288 static uint32_t si_translate_blend_factor(int blend_fact)
289 {
290 switch (blend_fact) {
291 case PIPE_BLENDFACTOR_ONE:
292 return V_028780_BLEND_ONE;
293 case PIPE_BLENDFACTOR_SRC_COLOR:
294 return V_028780_BLEND_SRC_COLOR;
295 case PIPE_BLENDFACTOR_SRC_ALPHA:
296 return V_028780_BLEND_SRC_ALPHA;
297 case PIPE_BLENDFACTOR_DST_ALPHA:
298 return V_028780_BLEND_DST_ALPHA;
299 case PIPE_BLENDFACTOR_DST_COLOR:
300 return V_028780_BLEND_DST_COLOR;
301 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
302 return V_028780_BLEND_SRC_ALPHA_SATURATE;
303 case PIPE_BLENDFACTOR_CONST_COLOR:
304 return V_028780_BLEND_CONSTANT_COLOR;
305 case PIPE_BLENDFACTOR_CONST_ALPHA:
306 return V_028780_BLEND_CONSTANT_ALPHA;
307 case PIPE_BLENDFACTOR_ZERO:
308 return V_028780_BLEND_ZERO;
309 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
310 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
311 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
312 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
313 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
314 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
315 case PIPE_BLENDFACTOR_INV_DST_COLOR:
316 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
317 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
318 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
319 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
320 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
321 case PIPE_BLENDFACTOR_SRC1_COLOR:
322 return V_028780_BLEND_SRC1_COLOR;
323 case PIPE_BLENDFACTOR_SRC1_ALPHA:
324 return V_028780_BLEND_SRC1_ALPHA;
325 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
326 return V_028780_BLEND_INV_SRC1_COLOR;
327 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
328 return V_028780_BLEND_INV_SRC1_ALPHA;
329 default:
330 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
331 assert(0);
332 break;
333 }
334 return 0;
335 }
336
337 static uint32_t si_translate_blend_opt_function(int blend_func)
338 {
339 switch (blend_func) {
340 case PIPE_BLEND_ADD:
341 return V_028760_OPT_COMB_ADD;
342 case PIPE_BLEND_SUBTRACT:
343 return V_028760_OPT_COMB_SUBTRACT;
344 case PIPE_BLEND_REVERSE_SUBTRACT:
345 return V_028760_OPT_COMB_REVSUBTRACT;
346 case PIPE_BLEND_MIN:
347 return V_028760_OPT_COMB_MIN;
348 case PIPE_BLEND_MAX:
349 return V_028760_OPT_COMB_MAX;
350 default:
351 return V_028760_OPT_COMB_BLEND_DISABLED;
352 }
353 }
354
355 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
356 {
357 switch (blend_fact) {
358 case PIPE_BLENDFACTOR_ZERO:
359 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
360 case PIPE_BLENDFACTOR_ONE:
361 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
362 case PIPE_BLENDFACTOR_SRC_COLOR:
363 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
364 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
365 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
366 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
367 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
368 case PIPE_BLENDFACTOR_SRC_ALPHA:
369 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
370 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
371 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
372 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
373 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
374 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
375 default:
376 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
377 }
378 }
379
380 /**
381 * Get rid of DST in the blend factors by commuting the operands:
382 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
383 */
384 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
385 unsigned *dst_factor, unsigned expected_dst,
386 unsigned replacement_src)
387 {
388 if (*src_factor == expected_dst &&
389 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
390 *src_factor = PIPE_BLENDFACTOR_ZERO;
391 *dst_factor = replacement_src;
392
393 /* Commuting the operands requires reversing subtractions. */
394 if (*func == PIPE_BLEND_SUBTRACT)
395 *func = PIPE_BLEND_REVERSE_SUBTRACT;
396 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
397 *func = PIPE_BLEND_SUBTRACT;
398 }
399 }
400
401 static bool si_blend_factor_uses_dst(unsigned factor)
402 {
403 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
404 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
405 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
406 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
407 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
408 }
409
410 static void *si_create_blend_state_mode(struct pipe_context *ctx,
411 const struct pipe_blend_state *state,
412 unsigned mode)
413 {
414 struct si_context *sctx = (struct si_context*)ctx;
415 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
416 struct si_pm4_state *pm4 = &blend->pm4;
417 uint32_t sx_mrt_blend_opt[8] = {0};
418 uint32_t color_control = 0;
419
420 if (!blend)
421 return NULL;
422
423 blend->alpha_to_coverage = state->alpha_to_coverage;
424 blend->alpha_to_one = state->alpha_to_one;
425 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
426
427 if (state->logicop_enable) {
428 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
429 } else {
430 color_control |= S_028808_ROP3(0xcc);
431 }
432
433 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
434 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
435 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
436 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
437 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
438 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
439
440 if (state->alpha_to_coverage)
441 blend->need_src_alpha_4bit |= 0xf;
442
443 blend->cb_target_mask = 0;
444 for (int i = 0; i < 8; i++) {
445 /* state->rt entries > 0 only written if independent blending */
446 const int j = state->independent_blend_enable ? i : 0;
447
448 unsigned eqRGB = state->rt[j].rgb_func;
449 unsigned srcRGB = state->rt[j].rgb_src_factor;
450 unsigned dstRGB = state->rt[j].rgb_dst_factor;
451 unsigned eqA = state->rt[j].alpha_func;
452 unsigned srcA = state->rt[j].alpha_src_factor;
453 unsigned dstA = state->rt[j].alpha_dst_factor;
454
455 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
456 unsigned blend_cntl = 0;
457
458 sx_mrt_blend_opt[i] =
459 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
460 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
461
462 /* Only set dual source blending for MRT0 to avoid a hang. */
463 if (i >= 1 && blend->dual_src_blend) {
464 /* Vulkan does this for dual source blending. */
465 if (i == 1)
466 blend_cntl |= S_028780_ENABLE(1);
467
468 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
469 continue;
470 }
471
472 /* Only addition and subtraction equations are supported with
473 * dual source blending.
474 */
475 if (blend->dual_src_blend &&
476 (eqRGB == PIPE_BLEND_MIN || eqRGB == PIPE_BLEND_MAX ||
477 eqA == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MAX)) {
478 assert(!"Unsupported equation for dual source blending");
479 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
480 continue;
481 }
482
483 /* cb_render_state will disable unused ones */
484 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
485
486 if (!state->rt[j].colormask || !state->rt[j].blend_enable) {
487 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
488 continue;
489 }
490
491 /* Blending optimizations for RB+.
492 * These transformations don't change the behavior.
493 *
494 * First, get rid of DST in the blend factors:
495 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
496 */
497 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
498 PIPE_BLENDFACTOR_DST_COLOR,
499 PIPE_BLENDFACTOR_SRC_COLOR);
500 si_blend_remove_dst(&eqA, &srcA, &dstA,
501 PIPE_BLENDFACTOR_DST_COLOR,
502 PIPE_BLENDFACTOR_SRC_COLOR);
503 si_blend_remove_dst(&eqA, &srcA, &dstA,
504 PIPE_BLENDFACTOR_DST_ALPHA,
505 PIPE_BLENDFACTOR_SRC_ALPHA);
506
507 /* Look up the ideal settings from tables. */
508 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
509 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
510 srcA_opt = si_translate_blend_opt_factor(srcA, true);
511 dstA_opt = si_translate_blend_opt_factor(dstA, true);
512
513 /* Handle interdependencies. */
514 if (si_blend_factor_uses_dst(srcRGB))
515 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
516 if (si_blend_factor_uses_dst(srcA))
517 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
518
519 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
520 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
521 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
522 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
523 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
524
525 /* Set the final value. */
526 sx_mrt_blend_opt[i] =
527 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
528 S_028760_COLOR_DST_OPT(dstRGB_opt) |
529 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
530 S_028760_ALPHA_SRC_OPT(srcA_opt) |
531 S_028760_ALPHA_DST_OPT(dstA_opt) |
532 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
533
534 /* Set blend state. */
535 blend_cntl |= S_028780_ENABLE(1);
536 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
537 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
538 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
539
540 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
541 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
542 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
543 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
544 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
545 }
546 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
547
548 blend->blend_enable_4bit |= 0xfu << (i * 4);
549
550 /* This is only important for formats without alpha. */
551 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
552 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
553 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
554 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
555 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
556 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
557 blend->need_src_alpha_4bit |= 0xfu << (i * 4);
558 }
559
560 if (blend->cb_target_mask) {
561 color_control |= S_028808_MODE(mode);
562 } else {
563 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
564 }
565
566 if (sctx->screen->b.has_rbplus) {
567 /* Disable RB+ blend optimizations for dual source blending.
568 * Vulkan does this.
569 */
570 if (blend->dual_src_blend) {
571 for (int i = 0; i < 8; i++) {
572 sx_mrt_blend_opt[i] =
573 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
574 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
575 }
576 }
577
578 for (int i = 0; i < 8; i++)
579 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
580 sx_mrt_blend_opt[i]);
581
582 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
583 if (blend->dual_src_blend || state->logicop_enable ||
584 mode == V_028808_CB_RESOLVE)
585 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
586 }
587
588 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
589 return blend;
590 }
591
592 static void *si_create_blend_state(struct pipe_context *ctx,
593 const struct pipe_blend_state *state)
594 {
595 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
596 }
597
598 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
599 {
600 struct si_context *sctx = (struct si_context *)ctx;
601 struct si_state_blend *old_blend = sctx->queued.named.blend;
602 struct si_state_blend *blend = (struct si_state_blend *)state;
603
604 if (!state)
605 return;
606
607 if (!old_blend ||
608 old_blend->cb_target_mask != blend->cb_target_mask ||
609 old_blend->dual_src_blend != blend->dual_src_blend)
610 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
611
612 si_pm4_bind_state(sctx, blend, state);
613
614 if (!old_blend ||
615 old_blend->cb_target_mask != blend->cb_target_mask ||
616 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
617 old_blend->alpha_to_one != blend->alpha_to_one ||
618 old_blend->dual_src_blend != blend->dual_src_blend ||
619 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
620 old_blend->need_src_alpha_4bit != blend->need_src_alpha_4bit)
621 sctx->do_update_shaders = true;
622 }
623
624 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
625 {
626 struct si_context *sctx = (struct si_context *)ctx;
627 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
628 }
629
630 static void si_set_blend_color(struct pipe_context *ctx,
631 const struct pipe_blend_color *state)
632 {
633 struct si_context *sctx = (struct si_context *)ctx;
634
635 sctx->blend_color.state = *state;
636 si_mark_atom_dirty(sctx, &sctx->blend_color.atom);
637 }
638
639 static void si_emit_blend_color(struct si_context *sctx, struct r600_atom *atom)
640 {
641 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
642
643 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
644 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
645 }
646
647 /*
648 * Clipping
649 */
650
651 static void si_set_clip_state(struct pipe_context *ctx,
652 const struct pipe_clip_state *state)
653 {
654 struct si_context *sctx = (struct si_context *)ctx;
655 struct pipe_constant_buffer cb;
656
657 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
658 return;
659
660 sctx->clip_state.state = *state;
661 si_mark_atom_dirty(sctx, &sctx->clip_state.atom);
662
663 cb.buffer = NULL;
664 cb.user_buffer = state->ucp;
665 cb.buffer_offset = 0;
666 cb.buffer_size = 4*4*8;
667 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
668 pipe_resource_reference(&cb.buffer, NULL);
669 }
670
671 static void si_emit_clip_state(struct si_context *sctx, struct r600_atom *atom)
672 {
673 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
674
675 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
676 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
677 }
678
679 static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom)
680 {
681 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
682 struct si_shader *vs = si_get_vs_state(sctx);
683 struct si_shader_selector *vs_sel = vs->selector;
684 struct tgsi_shader_info *info = &vs_sel->info;
685 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
686 unsigned window_space =
687 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
688 unsigned clipdist_mask = vs_sel->clipdist_mask;
689 unsigned ucp_mask = clipdist_mask ? 0 : rs->clip_plane_enable & SIX_BITS;
690 unsigned culldist_mask = vs_sel->culldist_mask;
691 unsigned total_mask;
692
693 if (vs->key.opt.clip_disable) {
694 assert(!info->culldist_writemask);
695 clipdist_mask = 0;
696 culldist_mask = 0;
697 }
698 total_mask = clipdist_mask | culldist_mask;
699
700 /* Clip distances on points have no effect, so need to be implemented
701 * as cull distances. This applies for the clipvertex case as well.
702 *
703 * Setting this for primitives other than points should have no adverse
704 * effects.
705 */
706 clipdist_mask &= rs->clip_plane_enable;
707 culldist_mask |= clipdist_mask;
708
709 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
710 vs_sel->pa_cl_vs_out_cntl |
711 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0F) != 0) |
712 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xF0) != 0) |
713 clipdist_mask | (culldist_mask << 8));
714 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
715 rs->pa_cl_clip_cntl |
716 ucp_mask |
717 S_028810_CLIP_DISABLE(window_space));
718
719 if (sctx->b.chip_class <= VI) {
720 /* reuse needs to be set off if we write oViewport */
721 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF,
722 S_028AB4_REUSE_OFF(info->writes_viewport_index));
723 }
724 }
725
726 /*
727 * inferred state between framebuffer and rasterizer
728 */
729 static void si_update_poly_offset_state(struct si_context *sctx)
730 {
731 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
732
733 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf) {
734 si_pm4_bind_state(sctx, poly_offset, NULL);
735 return;
736 }
737
738 /* Use the user format, not db_render_format, so that the polygon
739 * offset behaves as expected by applications.
740 */
741 switch (sctx->framebuffer.state.zsbuf->texture->format) {
742 case PIPE_FORMAT_Z16_UNORM:
743 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
744 break;
745 default: /* 24-bit */
746 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
747 break;
748 case PIPE_FORMAT_Z32_FLOAT:
749 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
750 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
751 break;
752 }
753 }
754
755 /*
756 * Rasterizer
757 */
758
759 static uint32_t si_translate_fill(uint32_t func)
760 {
761 switch(func) {
762 case PIPE_POLYGON_MODE_FILL:
763 return V_028814_X_DRAW_TRIANGLES;
764 case PIPE_POLYGON_MODE_LINE:
765 return V_028814_X_DRAW_LINES;
766 case PIPE_POLYGON_MODE_POINT:
767 return V_028814_X_DRAW_POINTS;
768 default:
769 assert(0);
770 return V_028814_X_DRAW_POINTS;
771 }
772 }
773
774 static void *si_create_rs_state(struct pipe_context *ctx,
775 const struct pipe_rasterizer_state *state)
776 {
777 struct si_screen *sscreen = ((struct si_context *)ctx)->screen;
778 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
779 struct si_pm4_state *pm4 = &rs->pm4;
780 unsigned tmp, i;
781 float psize_min, psize_max;
782
783 if (!rs) {
784 return NULL;
785 }
786
787 rs->scissor_enable = state->scissor;
788 rs->clip_halfz = state->clip_halfz;
789 rs->two_side = state->light_twoside;
790 rs->multisample_enable = state->multisample;
791 rs->force_persample_interp = state->force_persample_interp;
792 rs->clip_plane_enable = state->clip_plane_enable;
793 rs->line_stipple_enable = state->line_stipple_enable;
794 rs->poly_stipple_enable = state->poly_stipple_enable;
795 rs->line_smooth = state->line_smooth;
796 rs->poly_smooth = state->poly_smooth;
797 rs->uses_poly_offset = state->offset_point || state->offset_line ||
798 state->offset_tri;
799 rs->clamp_fragment_color = state->clamp_fragment_color;
800 rs->clamp_vertex_color = state->clamp_vertex_color;
801 rs->flatshade = state->flatshade;
802 rs->sprite_coord_enable = state->sprite_coord_enable;
803 rs->rasterizer_discard = state->rasterizer_discard;
804 rs->pa_sc_line_stipple = state->line_stipple_enable ?
805 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
806 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
807 rs->pa_cl_clip_cntl =
808 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
809 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
810 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
811 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
812 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
813
814 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
815 S_0286D4_FLAT_SHADE_ENA(1) |
816 S_0286D4_PNT_SPRITE_ENA(1) |
817 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
818 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
819 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
820 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
821 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
822
823 /* point size 12.4 fixed point */
824 tmp = (unsigned)(state->point_size * 8.0);
825 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
826
827 if (state->point_size_per_vertex) {
828 psize_min = util_get_min_point_size(state);
829 psize_max = 8192;
830 } else {
831 /* Force the point size to be as if the vertex output was disabled. */
832 psize_min = state->point_size;
833 psize_max = state->point_size;
834 }
835 /* Divide by two, because 0.5 = 1 pixel. */
836 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
837 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
838 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
839
840 tmp = (unsigned)state->line_width * 8;
841 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
842 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
843 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
844 S_028A48_MSAA_ENABLE(state->multisample ||
845 state->poly_smooth ||
846 state->line_smooth) |
847 S_028A48_VPORT_SCISSOR_ENABLE(1) |
848 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen->b.chip_class >= GFX9));
849
850 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
851 S_028BE4_PIX_CENTER(state->half_pixel_center) |
852 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
853
854 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
855 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
856 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
857 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
858 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
859 S_028814_FACE(!state->front_ccw) |
860 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
861 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
862 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
863 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
864 state->fill_back != PIPE_POLYGON_MODE_FILL) |
865 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
866 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
867
868 if (!rs->uses_poly_offset)
869 return rs;
870
871 rs->pm4_poly_offset = CALLOC(3, sizeof(struct si_pm4_state));
872 if (!rs->pm4_poly_offset) {
873 FREE(rs);
874 return NULL;
875 }
876
877 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
878 for (i = 0; i < 3; i++) {
879 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
880 float offset_units = state->offset_units;
881 float offset_scale = state->offset_scale * 16.0f;
882 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
883
884 if (!state->offset_units_unscaled) {
885 switch (i) {
886 case 0: /* 16-bit zbuffer */
887 offset_units *= 4.0f;
888 pa_su_poly_offset_db_fmt_cntl =
889 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
890 break;
891 case 1: /* 24-bit zbuffer */
892 offset_units *= 2.0f;
893 pa_su_poly_offset_db_fmt_cntl =
894 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
895 break;
896 case 2: /* 32-bit zbuffer */
897 offset_units *= 1.0f;
898 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
899 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
900 break;
901 }
902 }
903
904 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
905 fui(offset_scale));
906 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
907 fui(offset_units));
908 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
909 fui(offset_scale));
910 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
911 fui(offset_units));
912 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
913 pa_su_poly_offset_db_fmt_cntl);
914 }
915
916 return rs;
917 }
918
919 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
920 {
921 struct si_context *sctx = (struct si_context *)ctx;
922 struct si_state_rasterizer *old_rs =
923 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
924 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
925
926 if (!state)
927 return;
928
929 if (!old_rs || old_rs->multisample_enable != rs->multisample_enable) {
930 si_mark_atom_dirty(sctx, &sctx->db_render_state);
931
932 /* Update the small primitive filter workaround if necessary. */
933 if (sctx->screen->has_msaa_sample_loc_bug &&
934 sctx->framebuffer.nr_samples > 1)
935 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
936 }
937
938 sctx->current_vs_state &= C_VS_STATE_CLAMP_VERTEX_COLOR;
939 sctx->current_vs_state |= S_VS_STATE_CLAMP_VERTEX_COLOR(rs->clamp_vertex_color);
940
941 r600_viewport_set_rast_deps(&sctx->b, rs->scissor_enable, rs->clip_halfz);
942
943 si_pm4_bind_state(sctx, rasterizer, rs);
944 si_update_poly_offset_state(sctx);
945
946 if (!old_rs ||
947 old_rs->clip_plane_enable != rs->clip_plane_enable ||
948 old_rs->pa_cl_clip_cntl != rs->pa_cl_clip_cntl)
949 si_mark_atom_dirty(sctx, &sctx->clip_regs);
950
951 sctx->ia_multi_vgt_param_key.u.line_stipple_enabled =
952 rs->line_stipple_enable;
953
954 if (!old_rs ||
955 old_rs->clip_plane_enable != rs->clip_plane_enable ||
956 old_rs->rasterizer_discard != rs->rasterizer_discard ||
957 old_rs->sprite_coord_enable != rs->sprite_coord_enable ||
958 old_rs->flatshade != rs->flatshade ||
959 old_rs->two_side != rs->two_side ||
960 old_rs->multisample_enable != rs->multisample_enable ||
961 old_rs->poly_stipple_enable != rs->poly_stipple_enable ||
962 old_rs->poly_smooth != rs->poly_smooth ||
963 old_rs->line_smooth != rs->line_smooth ||
964 old_rs->clamp_fragment_color != rs->clamp_fragment_color ||
965 old_rs->force_persample_interp != rs->force_persample_interp)
966 sctx->do_update_shaders = true;
967 }
968
969 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
970 {
971 struct si_context *sctx = (struct si_context *)ctx;
972 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
973
974 if (sctx->queued.named.rasterizer == state)
975 si_pm4_bind_state(sctx, poly_offset, NULL);
976
977 FREE(rs->pm4_poly_offset);
978 si_pm4_delete_state(sctx, rasterizer, rs);
979 }
980
981 /*
982 * infeered state between dsa and stencil ref
983 */
984 static void si_emit_stencil_ref(struct si_context *sctx, struct r600_atom *atom)
985 {
986 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
987 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
988 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
989
990 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
991 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
992 S_028430_STENCILMASK(dsa->valuemask[0]) |
993 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
994 S_028430_STENCILOPVAL(1));
995 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
996 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
997 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
998 S_028434_STENCILOPVAL_BF(1));
999 }
1000
1001 static void si_set_stencil_ref(struct pipe_context *ctx,
1002 const struct pipe_stencil_ref *state)
1003 {
1004 struct si_context *sctx = (struct si_context *)ctx;
1005
1006 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
1007 return;
1008
1009 sctx->stencil_ref.state = *state;
1010 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1011 }
1012
1013
1014 /*
1015 * DSA
1016 */
1017
1018 static uint32_t si_translate_stencil_op(int s_op)
1019 {
1020 switch (s_op) {
1021 case PIPE_STENCIL_OP_KEEP:
1022 return V_02842C_STENCIL_KEEP;
1023 case PIPE_STENCIL_OP_ZERO:
1024 return V_02842C_STENCIL_ZERO;
1025 case PIPE_STENCIL_OP_REPLACE:
1026 return V_02842C_STENCIL_REPLACE_TEST;
1027 case PIPE_STENCIL_OP_INCR:
1028 return V_02842C_STENCIL_ADD_CLAMP;
1029 case PIPE_STENCIL_OP_DECR:
1030 return V_02842C_STENCIL_SUB_CLAMP;
1031 case PIPE_STENCIL_OP_INCR_WRAP:
1032 return V_02842C_STENCIL_ADD_WRAP;
1033 case PIPE_STENCIL_OP_DECR_WRAP:
1034 return V_02842C_STENCIL_SUB_WRAP;
1035 case PIPE_STENCIL_OP_INVERT:
1036 return V_02842C_STENCIL_INVERT;
1037 default:
1038 R600_ERR("Unknown stencil op %d", s_op);
1039 assert(0);
1040 break;
1041 }
1042 return 0;
1043 }
1044
1045 static void *si_create_dsa_state(struct pipe_context *ctx,
1046 const struct pipe_depth_stencil_alpha_state *state)
1047 {
1048 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
1049 struct si_pm4_state *pm4 = &dsa->pm4;
1050 unsigned db_depth_control;
1051 uint32_t db_stencil_control = 0;
1052
1053 if (!dsa) {
1054 return NULL;
1055 }
1056
1057 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
1058 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
1059 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
1060 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
1061
1062 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
1063 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
1064 S_028800_ZFUNC(state->depth.func) |
1065 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
1066
1067 /* stencil */
1068 if (state->stencil[0].enabled) {
1069 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1070 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
1071 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
1072 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
1073 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
1074
1075 if (state->stencil[1].enabled) {
1076 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1077 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1078 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
1079 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
1080 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
1081 }
1082 }
1083
1084 /* alpha */
1085 if (state->alpha.enabled) {
1086 dsa->alpha_func = state->alpha.func;
1087
1088 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1089 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
1090 } else {
1091 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1092 }
1093
1094 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1095 if (state->stencil[0].enabled)
1096 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1097 if (state->depth.bounds_test) {
1098 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1099 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1100 }
1101
1102 return dsa;
1103 }
1104
1105 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1106 {
1107 struct si_context *sctx = (struct si_context *)ctx;
1108 struct si_state_dsa *old_dsa = sctx->queued.named.dsa;
1109 struct si_state_dsa *dsa = state;
1110
1111 if (!state)
1112 return;
1113
1114 si_pm4_bind_state(sctx, dsa, dsa);
1115
1116 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1117 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1118 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1119 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1120 }
1121
1122 if (!old_dsa || old_dsa->alpha_func != dsa->alpha_func)
1123 sctx->do_update_shaders = true;
1124 }
1125
1126 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1127 {
1128 struct si_context *sctx = (struct si_context *)ctx;
1129 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1130 }
1131
1132 static void *si_create_db_flush_dsa(struct si_context *sctx)
1133 {
1134 struct pipe_depth_stencil_alpha_state dsa = {};
1135
1136 return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
1137 }
1138
1139 /* DB RENDER STATE */
1140
1141 static void si_set_active_query_state(struct pipe_context *ctx, boolean enable)
1142 {
1143 struct si_context *sctx = (struct si_context*)ctx;
1144
1145 /* Pipeline stat & streamout queries. */
1146 if (enable) {
1147 sctx->b.flags &= ~R600_CONTEXT_STOP_PIPELINE_STATS;
1148 sctx->b.flags |= R600_CONTEXT_START_PIPELINE_STATS;
1149 } else {
1150 sctx->b.flags &= ~R600_CONTEXT_START_PIPELINE_STATS;
1151 sctx->b.flags |= R600_CONTEXT_STOP_PIPELINE_STATS;
1152 }
1153
1154 /* Occlusion queries. */
1155 if (sctx->occlusion_queries_disabled != !enable) {
1156 sctx->occlusion_queries_disabled = !enable;
1157 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1158 }
1159 }
1160
1161 static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
1162 {
1163 struct si_context *sctx = (struct si_context*)ctx;
1164
1165 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1166 }
1167
1168 static void si_save_qbo_state(struct pipe_context *ctx, struct r600_qbo_state *st)
1169 {
1170 struct si_context *sctx = (struct si_context*)ctx;
1171
1172 st->saved_compute = sctx->cs_shader_state.program;
1173
1174 si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1175 si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
1176 }
1177
1178 static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
1179 {
1180 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1181 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1182 unsigned db_shader_control;
1183
1184 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1185
1186 /* DB_RENDER_CONTROL */
1187 if (sctx->dbcb_depth_copy_enabled ||
1188 sctx->dbcb_stencil_copy_enabled) {
1189 radeon_emit(cs,
1190 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1191 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1192 S_028000_COPY_CENTROID(1) |
1193 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
1194 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1195 radeon_emit(cs,
1196 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1197 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace));
1198 } else {
1199 radeon_emit(cs,
1200 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1201 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear));
1202 }
1203
1204 /* DB_COUNT_CONTROL (occlusion queries) */
1205 if (sctx->b.num_occlusion_queries > 0 &&
1206 !sctx->occlusion_queries_disabled) {
1207 bool perfect = sctx->b.num_perfect_occlusion_queries > 0;
1208
1209 if (sctx->b.chip_class >= CIK) {
1210 radeon_emit(cs,
1211 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1212 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
1213 S_028004_ZPASS_ENABLE(1) |
1214 S_028004_SLICE_EVEN_ENABLE(1) |
1215 S_028004_SLICE_ODD_ENABLE(1));
1216 } else {
1217 radeon_emit(cs,
1218 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1219 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
1220 }
1221 } else {
1222 /* Disable occlusion queries. */
1223 if (sctx->b.chip_class >= CIK) {
1224 radeon_emit(cs, 0);
1225 } else {
1226 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
1227 }
1228 }
1229
1230 /* DB_RENDER_OVERRIDE2 */
1231 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
1232 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1233 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1234 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4));
1235
1236 db_shader_control = sctx->ps_db_shader_control;
1237
1238 /* Bug workaround for smoothing (overrasterization) on SI. */
1239 if (sctx->b.chip_class == SI && sctx->smoothing_enabled) {
1240 db_shader_control &= C_02880C_Z_ORDER;
1241 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1242 }
1243
1244 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1245 if (!rs || !rs->multisample_enable)
1246 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1247
1248 if (sctx->screen->b.has_rbplus &&
1249 !sctx->screen->b.rbplus_allowed)
1250 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1251
1252 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
1253 db_shader_control);
1254 }
1255
1256 /*
1257 * format translation
1258 */
1259 static uint32_t si_translate_colorformat(enum pipe_format format)
1260 {
1261 const struct util_format_description *desc = util_format_description(format);
1262
1263 #define HAS_SIZE(x,y,z,w) \
1264 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1265 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1266
1267 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1268 return V_028C70_COLOR_10_11_11;
1269
1270 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1271 return V_028C70_COLOR_INVALID;
1272
1273 /* hw cannot support mixed formats (except depth/stencil, since
1274 * stencil is not written to). */
1275 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1276 return V_028C70_COLOR_INVALID;
1277
1278 switch (desc->nr_channels) {
1279 case 1:
1280 switch (desc->channel[0].size) {
1281 case 8:
1282 return V_028C70_COLOR_8;
1283 case 16:
1284 return V_028C70_COLOR_16;
1285 case 32:
1286 return V_028C70_COLOR_32;
1287 }
1288 break;
1289 case 2:
1290 if (desc->channel[0].size == desc->channel[1].size) {
1291 switch (desc->channel[0].size) {
1292 case 8:
1293 return V_028C70_COLOR_8_8;
1294 case 16:
1295 return V_028C70_COLOR_16_16;
1296 case 32:
1297 return V_028C70_COLOR_32_32;
1298 }
1299 } else if (HAS_SIZE(8,24,0,0)) {
1300 return V_028C70_COLOR_24_8;
1301 } else if (HAS_SIZE(24,8,0,0)) {
1302 return V_028C70_COLOR_8_24;
1303 }
1304 break;
1305 case 3:
1306 if (HAS_SIZE(5,6,5,0)) {
1307 return V_028C70_COLOR_5_6_5;
1308 } else if (HAS_SIZE(32,8,24,0)) {
1309 return V_028C70_COLOR_X24_8_32_FLOAT;
1310 }
1311 break;
1312 case 4:
1313 if (desc->channel[0].size == desc->channel[1].size &&
1314 desc->channel[0].size == desc->channel[2].size &&
1315 desc->channel[0].size == desc->channel[3].size) {
1316 switch (desc->channel[0].size) {
1317 case 4:
1318 return V_028C70_COLOR_4_4_4_4;
1319 case 8:
1320 return V_028C70_COLOR_8_8_8_8;
1321 case 16:
1322 return V_028C70_COLOR_16_16_16_16;
1323 case 32:
1324 return V_028C70_COLOR_32_32_32_32;
1325 }
1326 } else if (HAS_SIZE(5,5,5,1)) {
1327 return V_028C70_COLOR_1_5_5_5;
1328 } else if (HAS_SIZE(10,10,10,2)) {
1329 return V_028C70_COLOR_2_10_10_10;
1330 }
1331 break;
1332 }
1333 return V_028C70_COLOR_INVALID;
1334 }
1335
1336 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1337 {
1338 if (SI_BIG_ENDIAN) {
1339 switch(colorformat) {
1340 /* 8-bit buffers. */
1341 case V_028C70_COLOR_8:
1342 return V_028C70_ENDIAN_NONE;
1343
1344 /* 16-bit buffers. */
1345 case V_028C70_COLOR_5_6_5:
1346 case V_028C70_COLOR_1_5_5_5:
1347 case V_028C70_COLOR_4_4_4_4:
1348 case V_028C70_COLOR_16:
1349 case V_028C70_COLOR_8_8:
1350 return V_028C70_ENDIAN_8IN16;
1351
1352 /* 32-bit buffers. */
1353 case V_028C70_COLOR_8_8_8_8:
1354 case V_028C70_COLOR_2_10_10_10:
1355 case V_028C70_COLOR_8_24:
1356 case V_028C70_COLOR_24_8:
1357 case V_028C70_COLOR_16_16:
1358 return V_028C70_ENDIAN_8IN32;
1359
1360 /* 64-bit buffers. */
1361 case V_028C70_COLOR_16_16_16_16:
1362 return V_028C70_ENDIAN_8IN16;
1363
1364 case V_028C70_COLOR_32_32:
1365 return V_028C70_ENDIAN_8IN32;
1366
1367 /* 128-bit buffers. */
1368 case V_028C70_COLOR_32_32_32_32:
1369 return V_028C70_ENDIAN_8IN32;
1370 default:
1371 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1372 }
1373 } else {
1374 return V_028C70_ENDIAN_NONE;
1375 }
1376 }
1377
1378 static uint32_t si_translate_dbformat(enum pipe_format format)
1379 {
1380 switch (format) {
1381 case PIPE_FORMAT_Z16_UNORM:
1382 return V_028040_Z_16;
1383 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1384 case PIPE_FORMAT_X8Z24_UNORM:
1385 case PIPE_FORMAT_Z24X8_UNORM:
1386 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1387 return V_028040_Z_24; /* deprecated on SI */
1388 case PIPE_FORMAT_Z32_FLOAT:
1389 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1390 return V_028040_Z_32_FLOAT;
1391 default:
1392 return V_028040_Z_INVALID;
1393 }
1394 }
1395
1396 /*
1397 * Texture translation
1398 */
1399
1400 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1401 enum pipe_format format,
1402 const struct util_format_description *desc,
1403 int first_non_void)
1404 {
1405 struct si_screen *sscreen = (struct si_screen*)screen;
1406 bool enable_compressed_formats = (sscreen->b.info.drm_major == 2 &&
1407 sscreen->b.info.drm_minor >= 31) ||
1408 sscreen->b.info.drm_major == 3;
1409 bool uniform = true;
1410 int i;
1411
1412 /* Colorspace (return non-RGB formats directly). */
1413 switch (desc->colorspace) {
1414 /* Depth stencil formats */
1415 case UTIL_FORMAT_COLORSPACE_ZS:
1416 switch (format) {
1417 case PIPE_FORMAT_Z16_UNORM:
1418 return V_008F14_IMG_DATA_FORMAT_16;
1419 case PIPE_FORMAT_X24S8_UINT:
1420 case PIPE_FORMAT_S8X24_UINT:
1421 /*
1422 * Implemented as an 8_8_8_8 data format to fix texture
1423 * gathers in stencil sampling. This affects at least
1424 * GL45-CTS.texture_cube_map_array.sampling on VI.
1425 */
1426 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1427 case PIPE_FORMAT_Z24X8_UNORM:
1428 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1429 return V_008F14_IMG_DATA_FORMAT_8_24;
1430 case PIPE_FORMAT_X8Z24_UNORM:
1431 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1432 return V_008F14_IMG_DATA_FORMAT_24_8;
1433 case PIPE_FORMAT_S8_UINT:
1434 return V_008F14_IMG_DATA_FORMAT_8;
1435 case PIPE_FORMAT_Z32_FLOAT:
1436 return V_008F14_IMG_DATA_FORMAT_32;
1437 case PIPE_FORMAT_X32_S8X24_UINT:
1438 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1439 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1440 default:
1441 goto out_unknown;
1442 }
1443
1444 case UTIL_FORMAT_COLORSPACE_YUV:
1445 goto out_unknown; /* TODO */
1446
1447 case UTIL_FORMAT_COLORSPACE_SRGB:
1448 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1449 goto out_unknown;
1450 break;
1451
1452 default:
1453 break;
1454 }
1455
1456 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1457 if (!enable_compressed_formats)
1458 goto out_unknown;
1459
1460 switch (format) {
1461 case PIPE_FORMAT_RGTC1_SNORM:
1462 case PIPE_FORMAT_LATC1_SNORM:
1463 case PIPE_FORMAT_RGTC1_UNORM:
1464 case PIPE_FORMAT_LATC1_UNORM:
1465 return V_008F14_IMG_DATA_FORMAT_BC4;
1466 case PIPE_FORMAT_RGTC2_SNORM:
1467 case PIPE_FORMAT_LATC2_SNORM:
1468 case PIPE_FORMAT_RGTC2_UNORM:
1469 case PIPE_FORMAT_LATC2_UNORM:
1470 return V_008F14_IMG_DATA_FORMAT_BC5;
1471 default:
1472 goto out_unknown;
1473 }
1474 }
1475
1476 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1477 (sscreen->b.family == CHIP_STONEY ||
1478 sscreen->b.chip_class >= GFX9)) {
1479 switch (format) {
1480 case PIPE_FORMAT_ETC1_RGB8:
1481 case PIPE_FORMAT_ETC2_RGB8:
1482 case PIPE_FORMAT_ETC2_SRGB8:
1483 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1484 case PIPE_FORMAT_ETC2_RGB8A1:
1485 case PIPE_FORMAT_ETC2_SRGB8A1:
1486 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1487 case PIPE_FORMAT_ETC2_RGBA8:
1488 case PIPE_FORMAT_ETC2_SRGBA8:
1489 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1490 case PIPE_FORMAT_ETC2_R11_UNORM:
1491 case PIPE_FORMAT_ETC2_R11_SNORM:
1492 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1493 case PIPE_FORMAT_ETC2_RG11_UNORM:
1494 case PIPE_FORMAT_ETC2_RG11_SNORM:
1495 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1496 default:
1497 goto out_unknown;
1498 }
1499 }
1500
1501 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1502 if (!enable_compressed_formats)
1503 goto out_unknown;
1504
1505 switch (format) {
1506 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1507 case PIPE_FORMAT_BPTC_SRGBA:
1508 return V_008F14_IMG_DATA_FORMAT_BC7;
1509 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1510 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1511 return V_008F14_IMG_DATA_FORMAT_BC6;
1512 default:
1513 goto out_unknown;
1514 }
1515 }
1516
1517 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1518 switch (format) {
1519 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1520 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1521 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1522 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1523 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1524 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1525 default:
1526 goto out_unknown;
1527 }
1528 }
1529
1530 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1531 if (!enable_compressed_formats)
1532 goto out_unknown;
1533
1534 if (!util_format_s3tc_enabled) {
1535 goto out_unknown;
1536 }
1537
1538 switch (format) {
1539 case PIPE_FORMAT_DXT1_RGB:
1540 case PIPE_FORMAT_DXT1_RGBA:
1541 case PIPE_FORMAT_DXT1_SRGB:
1542 case PIPE_FORMAT_DXT1_SRGBA:
1543 return V_008F14_IMG_DATA_FORMAT_BC1;
1544 case PIPE_FORMAT_DXT3_RGBA:
1545 case PIPE_FORMAT_DXT3_SRGBA:
1546 return V_008F14_IMG_DATA_FORMAT_BC2;
1547 case PIPE_FORMAT_DXT5_RGBA:
1548 case PIPE_FORMAT_DXT5_SRGBA:
1549 return V_008F14_IMG_DATA_FORMAT_BC3;
1550 default:
1551 goto out_unknown;
1552 }
1553 }
1554
1555 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1556 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1557 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1558 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1559 }
1560
1561 /* R8G8Bx_SNORM - TODO CxV8U8 */
1562
1563 /* hw cannot support mixed formats (except depth/stencil, since only
1564 * depth is read).*/
1565 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1566 goto out_unknown;
1567
1568 /* See whether the components are of the same size. */
1569 for (i = 1; i < desc->nr_channels; i++) {
1570 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1571 }
1572
1573 /* Non-uniform formats. */
1574 if (!uniform) {
1575 switch(desc->nr_channels) {
1576 case 3:
1577 if (desc->channel[0].size == 5 &&
1578 desc->channel[1].size == 6 &&
1579 desc->channel[2].size == 5) {
1580 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1581 }
1582 goto out_unknown;
1583 case 4:
1584 if (desc->channel[0].size == 5 &&
1585 desc->channel[1].size == 5 &&
1586 desc->channel[2].size == 5 &&
1587 desc->channel[3].size == 1) {
1588 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1589 }
1590 if (desc->channel[0].size == 10 &&
1591 desc->channel[1].size == 10 &&
1592 desc->channel[2].size == 10 &&
1593 desc->channel[3].size == 2) {
1594 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1595 }
1596 goto out_unknown;
1597 }
1598 goto out_unknown;
1599 }
1600
1601 if (first_non_void < 0 || first_non_void > 3)
1602 goto out_unknown;
1603
1604 /* uniform formats */
1605 switch (desc->channel[first_non_void].size) {
1606 case 4:
1607 switch (desc->nr_channels) {
1608 #if 0 /* Not supported for render targets */
1609 case 2:
1610 return V_008F14_IMG_DATA_FORMAT_4_4;
1611 #endif
1612 case 4:
1613 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1614 }
1615 break;
1616 case 8:
1617 switch (desc->nr_channels) {
1618 case 1:
1619 return V_008F14_IMG_DATA_FORMAT_8;
1620 case 2:
1621 return V_008F14_IMG_DATA_FORMAT_8_8;
1622 case 4:
1623 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1624 }
1625 break;
1626 case 16:
1627 switch (desc->nr_channels) {
1628 case 1:
1629 return V_008F14_IMG_DATA_FORMAT_16;
1630 case 2:
1631 return V_008F14_IMG_DATA_FORMAT_16_16;
1632 case 4:
1633 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1634 }
1635 break;
1636 case 32:
1637 switch (desc->nr_channels) {
1638 case 1:
1639 return V_008F14_IMG_DATA_FORMAT_32;
1640 case 2:
1641 return V_008F14_IMG_DATA_FORMAT_32_32;
1642 #if 0 /* Not supported for render targets */
1643 case 3:
1644 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1645 #endif
1646 case 4:
1647 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1648 }
1649 }
1650
1651 out_unknown:
1652 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1653 return ~0;
1654 }
1655
1656 static unsigned si_tex_wrap(unsigned wrap)
1657 {
1658 switch (wrap) {
1659 default:
1660 case PIPE_TEX_WRAP_REPEAT:
1661 return V_008F30_SQ_TEX_WRAP;
1662 case PIPE_TEX_WRAP_CLAMP:
1663 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1664 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1665 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1666 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1667 return V_008F30_SQ_TEX_CLAMP_BORDER;
1668 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1669 return V_008F30_SQ_TEX_MIRROR;
1670 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1671 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1672 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1673 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1674 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1675 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1676 }
1677 }
1678
1679 static unsigned si_tex_mipfilter(unsigned filter)
1680 {
1681 switch (filter) {
1682 case PIPE_TEX_MIPFILTER_NEAREST:
1683 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1684 case PIPE_TEX_MIPFILTER_LINEAR:
1685 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1686 default:
1687 case PIPE_TEX_MIPFILTER_NONE:
1688 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1689 }
1690 }
1691
1692 static unsigned si_tex_compare(unsigned compare)
1693 {
1694 switch (compare) {
1695 default:
1696 case PIPE_FUNC_NEVER:
1697 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1698 case PIPE_FUNC_LESS:
1699 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1700 case PIPE_FUNC_EQUAL:
1701 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1702 case PIPE_FUNC_LEQUAL:
1703 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1704 case PIPE_FUNC_GREATER:
1705 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1706 case PIPE_FUNC_NOTEQUAL:
1707 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1708 case PIPE_FUNC_GEQUAL:
1709 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1710 case PIPE_FUNC_ALWAYS:
1711 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1712 }
1713 }
1714
1715 static unsigned si_tex_dim(struct si_screen *sscreen, struct r600_texture *rtex,
1716 unsigned view_target, unsigned nr_samples)
1717 {
1718 unsigned res_target = rtex->resource.b.b.target;
1719
1720 if (view_target == PIPE_TEXTURE_CUBE ||
1721 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1722 res_target = view_target;
1723 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1724 else if (res_target == PIPE_TEXTURE_CUBE ||
1725 res_target == PIPE_TEXTURE_CUBE_ARRAY)
1726 res_target = PIPE_TEXTURE_2D_ARRAY;
1727
1728 /* GFX9 allocates 1D textures as 2D. */
1729 if ((res_target == PIPE_TEXTURE_1D ||
1730 res_target == PIPE_TEXTURE_1D_ARRAY) &&
1731 sscreen->b.chip_class >= GFX9 &&
1732 rtex->surface.u.gfx9.resource_type == RADEON_RESOURCE_2D) {
1733 if (res_target == PIPE_TEXTURE_1D)
1734 res_target = PIPE_TEXTURE_2D;
1735 else
1736 res_target = PIPE_TEXTURE_2D_ARRAY;
1737 }
1738
1739 switch (res_target) {
1740 default:
1741 case PIPE_TEXTURE_1D:
1742 return V_008F1C_SQ_RSRC_IMG_1D;
1743 case PIPE_TEXTURE_1D_ARRAY:
1744 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1745 case PIPE_TEXTURE_2D:
1746 case PIPE_TEXTURE_RECT:
1747 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1748 V_008F1C_SQ_RSRC_IMG_2D;
1749 case PIPE_TEXTURE_2D_ARRAY:
1750 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1751 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1752 case PIPE_TEXTURE_3D:
1753 return V_008F1C_SQ_RSRC_IMG_3D;
1754 case PIPE_TEXTURE_CUBE:
1755 case PIPE_TEXTURE_CUBE_ARRAY:
1756 return V_008F1C_SQ_RSRC_IMG_CUBE;
1757 }
1758 }
1759
1760 /*
1761 * Format support testing
1762 */
1763
1764 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1765 {
1766 return si_translate_texformat(screen, format, util_format_description(format),
1767 util_format_get_first_non_void_channel(format)) != ~0U;
1768 }
1769
1770 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1771 const struct util_format_description *desc,
1772 int first_non_void)
1773 {
1774 int i;
1775
1776 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1777 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1778
1779 assert(first_non_void >= 0);
1780
1781 if (desc->nr_channels == 4 &&
1782 desc->channel[0].size == 10 &&
1783 desc->channel[1].size == 10 &&
1784 desc->channel[2].size == 10 &&
1785 desc->channel[3].size == 2)
1786 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1787
1788 /* See whether the components are of the same size. */
1789 for (i = 0; i < desc->nr_channels; i++) {
1790 if (desc->channel[first_non_void].size != desc->channel[i].size)
1791 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1792 }
1793
1794 switch (desc->channel[first_non_void].size) {
1795 case 8:
1796 switch (desc->nr_channels) {
1797 case 1:
1798 case 3: /* 3 loads */
1799 return V_008F0C_BUF_DATA_FORMAT_8;
1800 case 2:
1801 return V_008F0C_BUF_DATA_FORMAT_8_8;
1802 case 4:
1803 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1804 }
1805 break;
1806 case 16:
1807 switch (desc->nr_channels) {
1808 case 1:
1809 case 3: /* 3 loads */
1810 return V_008F0C_BUF_DATA_FORMAT_16;
1811 case 2:
1812 return V_008F0C_BUF_DATA_FORMAT_16_16;
1813 case 4:
1814 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1815 }
1816 break;
1817 case 32:
1818 switch (desc->nr_channels) {
1819 case 1:
1820 return V_008F0C_BUF_DATA_FORMAT_32;
1821 case 2:
1822 return V_008F0C_BUF_DATA_FORMAT_32_32;
1823 case 3:
1824 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1825 case 4:
1826 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1827 }
1828 break;
1829 case 64:
1830 /* Legacy double formats. */
1831 switch (desc->nr_channels) {
1832 case 1: /* 1 load */
1833 return V_008F0C_BUF_DATA_FORMAT_32_32;
1834 case 2: /* 1 load */
1835 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1836 case 3: /* 3 loads */
1837 return V_008F0C_BUF_DATA_FORMAT_32_32;
1838 case 4: /* 2 loads */
1839 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1840 }
1841 break;
1842 }
1843
1844 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1845 }
1846
1847 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1848 const struct util_format_description *desc,
1849 int first_non_void)
1850 {
1851 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1852 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1853
1854 assert(first_non_void >= 0);
1855
1856 switch (desc->channel[first_non_void].type) {
1857 case UTIL_FORMAT_TYPE_SIGNED:
1858 case UTIL_FORMAT_TYPE_FIXED:
1859 if (desc->channel[first_non_void].size >= 32 ||
1860 desc->channel[first_non_void].pure_integer)
1861 return V_008F0C_BUF_NUM_FORMAT_SINT;
1862 else if (desc->channel[first_non_void].normalized)
1863 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1864 else
1865 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1866 break;
1867 case UTIL_FORMAT_TYPE_UNSIGNED:
1868 if (desc->channel[first_non_void].size >= 32 ||
1869 desc->channel[first_non_void].pure_integer)
1870 return V_008F0C_BUF_NUM_FORMAT_UINT;
1871 else if (desc->channel[first_non_void].normalized)
1872 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1873 else
1874 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1875 break;
1876 case UTIL_FORMAT_TYPE_FLOAT:
1877 default:
1878 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1879 }
1880 }
1881
1882 static unsigned si_is_vertex_format_supported(struct pipe_screen *screen,
1883 enum pipe_format format,
1884 unsigned usage)
1885 {
1886 const struct util_format_description *desc;
1887 int first_non_void;
1888 unsigned data_format;
1889
1890 assert((usage & ~(PIPE_BIND_SHADER_IMAGE |
1891 PIPE_BIND_SAMPLER_VIEW |
1892 PIPE_BIND_VERTEX_BUFFER)) == 0);
1893
1894 desc = util_format_description(format);
1895
1896 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
1897 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
1898 * for read-only access (with caveats surrounding bounds checks), but
1899 * obviously fails for write access which we have to implement for
1900 * shader images. Luckily, OpenGL doesn't expect this to be supported
1901 * anyway, and so the only impact is on PBO uploads / downloads, which
1902 * shouldn't be expected to be fast for GL_RGB anyway.
1903 */
1904 if (desc->block.bits == 3 * 8 ||
1905 desc->block.bits == 3 * 16) {
1906 if (usage & (PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW)) {
1907 usage &= ~(PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW);
1908 if (!usage)
1909 return 0;
1910 }
1911 }
1912
1913 first_non_void = util_format_get_first_non_void_channel(format);
1914 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1915 if (data_format == V_008F0C_BUF_DATA_FORMAT_INVALID)
1916 return 0;
1917
1918 return usage;
1919 }
1920
1921 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1922 {
1923 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1924 r600_translate_colorswap(format, false) != ~0U;
1925 }
1926
1927 static bool si_is_zs_format_supported(enum pipe_format format)
1928 {
1929 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1930 }
1931
1932 static boolean si_is_format_supported(struct pipe_screen *screen,
1933 enum pipe_format format,
1934 enum pipe_texture_target target,
1935 unsigned sample_count,
1936 unsigned usage)
1937 {
1938 unsigned retval = 0;
1939
1940 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1941 R600_ERR("r600: unsupported texture type %d\n", target);
1942 return false;
1943 }
1944
1945 if (!util_format_is_supported(format, usage))
1946 return false;
1947
1948 if (sample_count > 1) {
1949 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
1950 return false;
1951
1952 if (usage & PIPE_BIND_SHADER_IMAGE)
1953 return false;
1954
1955 switch (sample_count) {
1956 case 2:
1957 case 4:
1958 case 8:
1959 break;
1960 case 16:
1961 if (format == PIPE_FORMAT_NONE)
1962 return true;
1963 else
1964 return false;
1965 default:
1966 return false;
1967 }
1968 }
1969
1970 if (usage & (PIPE_BIND_SAMPLER_VIEW |
1971 PIPE_BIND_SHADER_IMAGE)) {
1972 if (target == PIPE_BUFFER) {
1973 retval |= si_is_vertex_format_supported(
1974 screen, format, usage & (PIPE_BIND_SAMPLER_VIEW |
1975 PIPE_BIND_SHADER_IMAGE));
1976 } else {
1977 if (si_is_sampler_format_supported(screen, format))
1978 retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
1979 PIPE_BIND_SHADER_IMAGE);
1980 }
1981 }
1982
1983 if ((usage & (PIPE_BIND_RENDER_TARGET |
1984 PIPE_BIND_DISPLAY_TARGET |
1985 PIPE_BIND_SCANOUT |
1986 PIPE_BIND_SHARED |
1987 PIPE_BIND_BLENDABLE)) &&
1988 si_is_colorbuffer_format_supported(format)) {
1989 retval |= usage &
1990 (PIPE_BIND_RENDER_TARGET |
1991 PIPE_BIND_DISPLAY_TARGET |
1992 PIPE_BIND_SCANOUT |
1993 PIPE_BIND_SHARED);
1994 if (!util_format_is_pure_integer(format) &&
1995 !util_format_is_depth_or_stencil(format))
1996 retval |= usage & PIPE_BIND_BLENDABLE;
1997 }
1998
1999 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
2000 si_is_zs_format_supported(format)) {
2001 retval |= PIPE_BIND_DEPTH_STENCIL;
2002 }
2003
2004 if (usage & PIPE_BIND_VERTEX_BUFFER) {
2005 retval |= si_is_vertex_format_supported(screen, format,
2006 PIPE_BIND_VERTEX_BUFFER);
2007 }
2008
2009 if ((usage & PIPE_BIND_LINEAR) &&
2010 !util_format_is_compressed(format) &&
2011 !(usage & PIPE_BIND_DEPTH_STENCIL))
2012 retval |= PIPE_BIND_LINEAR;
2013
2014 return retval == usage;
2015 }
2016
2017 /*
2018 * framebuffer handling
2019 */
2020
2021 static void si_choose_spi_color_formats(struct r600_surface *surf,
2022 unsigned format, unsigned swap,
2023 unsigned ntype, bool is_depth)
2024 {
2025 /* Alpha is needed for alpha-to-coverage.
2026 * Blending may be with or without alpha.
2027 */
2028 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
2029 unsigned alpha = 0; /* exports alpha, but may not support blending */
2030 unsigned blend = 0; /* supports blending, but may not export alpha */
2031 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
2032
2033 /* Choose the SPI color formats. These are required values for RB+.
2034 * Other chips have multiple choices, though they are not necessarily better.
2035 */
2036 switch (format) {
2037 case V_028C70_COLOR_5_6_5:
2038 case V_028C70_COLOR_1_5_5_5:
2039 case V_028C70_COLOR_5_5_5_1:
2040 case V_028C70_COLOR_4_4_4_4:
2041 case V_028C70_COLOR_10_11_11:
2042 case V_028C70_COLOR_11_11_10:
2043 case V_028C70_COLOR_8:
2044 case V_028C70_COLOR_8_8:
2045 case V_028C70_COLOR_8_8_8_8:
2046 case V_028C70_COLOR_10_10_10_2:
2047 case V_028C70_COLOR_2_10_10_10:
2048 if (ntype == V_028C70_NUMBER_UINT)
2049 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2050 else if (ntype == V_028C70_NUMBER_SINT)
2051 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2052 else
2053 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2054 break;
2055
2056 case V_028C70_COLOR_16:
2057 case V_028C70_COLOR_16_16:
2058 case V_028C70_COLOR_16_16_16_16:
2059 if (ntype == V_028C70_NUMBER_UNORM ||
2060 ntype == V_028C70_NUMBER_SNORM) {
2061 /* UNORM16 and SNORM16 don't support blending */
2062 if (ntype == V_028C70_NUMBER_UNORM)
2063 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
2064 else
2065 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
2066
2067 /* Use 32 bits per channel for blending. */
2068 if (format == V_028C70_COLOR_16) {
2069 if (swap == V_028C70_SWAP_STD) { /* R */
2070 blend = V_028714_SPI_SHADER_32_R;
2071 blend_alpha = V_028714_SPI_SHADER_32_AR;
2072 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2073 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2074 else
2075 assert(0);
2076 } else if (format == V_028C70_COLOR_16_16) {
2077 if (swap == V_028C70_SWAP_STD) { /* RG */
2078 blend = V_028714_SPI_SHADER_32_GR;
2079 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2080 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2081 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2082 else
2083 assert(0);
2084 } else /* 16_16_16_16 */
2085 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2086 } else if (ntype == V_028C70_NUMBER_UINT)
2087 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2088 else if (ntype == V_028C70_NUMBER_SINT)
2089 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2090 else if (ntype == V_028C70_NUMBER_FLOAT)
2091 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2092 else
2093 assert(0);
2094 break;
2095
2096 case V_028C70_COLOR_32:
2097 if (swap == V_028C70_SWAP_STD) { /* R */
2098 blend = normal = V_028714_SPI_SHADER_32_R;
2099 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
2100 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2101 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2102 else
2103 assert(0);
2104 break;
2105
2106 case V_028C70_COLOR_32_32:
2107 if (swap == V_028C70_SWAP_STD) { /* RG */
2108 blend = normal = V_028714_SPI_SHADER_32_GR;
2109 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2110 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2111 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2112 else
2113 assert(0);
2114 break;
2115
2116 case V_028C70_COLOR_32_32_32_32:
2117 case V_028C70_COLOR_8_24:
2118 case V_028C70_COLOR_24_8:
2119 case V_028C70_COLOR_X24_8_32_FLOAT:
2120 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2121 break;
2122
2123 default:
2124 assert(0);
2125 return;
2126 }
2127
2128 /* The DB->CB copy needs 32_ABGR. */
2129 if (is_depth)
2130 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2131
2132 surf->spi_shader_col_format = normal;
2133 surf->spi_shader_col_format_alpha = alpha;
2134 surf->spi_shader_col_format_blend = blend;
2135 surf->spi_shader_col_format_blend_alpha = blend_alpha;
2136 }
2137
2138 static void si_initialize_color_surface(struct si_context *sctx,
2139 struct r600_surface *surf)
2140 {
2141 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2142 unsigned color_info, color_attrib, color_view;
2143 unsigned format, swap, ntype, endian;
2144 const struct util_format_description *desc;
2145 int i;
2146 unsigned blend_clamp = 0, blend_bypass = 0;
2147
2148 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2149 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
2150
2151 desc = util_format_description(surf->base.format);
2152 for (i = 0; i < 4; i++) {
2153 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2154 break;
2155 }
2156 }
2157 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
2158 ntype = V_028C70_NUMBER_FLOAT;
2159 } else {
2160 ntype = V_028C70_NUMBER_UNORM;
2161 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2162 ntype = V_028C70_NUMBER_SRGB;
2163 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2164 if (desc->channel[i].pure_integer) {
2165 ntype = V_028C70_NUMBER_SINT;
2166 } else {
2167 assert(desc->channel[i].normalized);
2168 ntype = V_028C70_NUMBER_SNORM;
2169 }
2170 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2171 if (desc->channel[i].pure_integer) {
2172 ntype = V_028C70_NUMBER_UINT;
2173 } else {
2174 assert(desc->channel[i].normalized);
2175 ntype = V_028C70_NUMBER_UNORM;
2176 }
2177 }
2178 }
2179
2180 format = si_translate_colorformat(surf->base.format);
2181 if (format == V_028C70_COLOR_INVALID) {
2182 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2183 }
2184 assert(format != V_028C70_COLOR_INVALID);
2185 swap = r600_translate_colorswap(surf->base.format, false);
2186 endian = si_colorformat_endian_swap(format);
2187
2188 /* blend clamp should be set for all NORM/SRGB types */
2189 if (ntype == V_028C70_NUMBER_UNORM ||
2190 ntype == V_028C70_NUMBER_SNORM ||
2191 ntype == V_028C70_NUMBER_SRGB)
2192 blend_clamp = 1;
2193
2194 /* set blend bypass according to docs if SINT/UINT or
2195 8/24 COLOR variants */
2196 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2197 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2198 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2199 blend_clamp = 0;
2200 blend_bypass = 1;
2201 }
2202
2203 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) {
2204 if (format == V_028C70_COLOR_8 ||
2205 format == V_028C70_COLOR_8_8 ||
2206 format == V_028C70_COLOR_8_8_8_8)
2207 surf->color_is_int8 = true;
2208 else if (format == V_028C70_COLOR_10_10_10_2 ||
2209 format == V_028C70_COLOR_2_10_10_10)
2210 surf->color_is_int10 = true;
2211 }
2212
2213 color_info = S_028C70_FORMAT(format) |
2214 S_028C70_COMP_SWAP(swap) |
2215 S_028C70_BLEND_CLAMP(blend_clamp) |
2216 S_028C70_BLEND_BYPASS(blend_bypass) |
2217 S_028C70_SIMPLE_FLOAT(1) |
2218 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2219 ntype != V_028C70_NUMBER_SNORM &&
2220 ntype != V_028C70_NUMBER_SRGB &&
2221 format != V_028C70_COLOR_8_24 &&
2222 format != V_028C70_COLOR_24_8) |
2223 S_028C70_NUMBER_TYPE(ntype) |
2224 S_028C70_ENDIAN(endian);
2225
2226 /* Intensity is implemented as Red, so treat it that way. */
2227 color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2228 util_format_is_intensity(surf->base.format));
2229
2230 if (rtex->resource.b.b.nr_samples > 1) {
2231 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
2232
2233 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2234 S_028C74_NUM_FRAGMENTS(log_samples);
2235
2236 if (rtex->fmask.size) {
2237 color_info |= S_028C70_COMPRESSION(1);
2238 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
2239
2240 if (sctx->b.chip_class == SI) {
2241 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2242 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2243 }
2244 }
2245 }
2246
2247 surf->cb_color_view = color_view;
2248 surf->cb_color_info = color_info;
2249 surf->cb_color_attrib = color_attrib;
2250
2251 if (sctx->b.chip_class >= VI) {
2252 unsigned max_uncompressed_block_size = 2;
2253
2254 if (rtex->resource.b.b.nr_samples > 1) {
2255 if (rtex->surface.bpe == 1)
2256 max_uncompressed_block_size = 0;
2257 else if (rtex->surface.bpe == 2)
2258 max_uncompressed_block_size = 1;
2259 }
2260
2261 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2262 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2263 }
2264
2265 /* This must be set for fast clear to work without FMASK. */
2266 if (!rtex->fmask.size && sctx->b.chip_class == SI) {
2267 unsigned bankh = util_logbase2(rtex->surface.u.legacy.bankh);
2268 surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2269 }
2270
2271 if (sctx->b.chip_class >= GFX9) {
2272 unsigned mip0_depth = util_max_layer(&rtex->resource.b.b, 0);
2273
2274 surf->cb_color_view |= S_028C6C_MIP_LEVEL(surf->base.u.tex.level);
2275 surf->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
2276 S_028C74_RESOURCE_TYPE(rtex->surface.u.gfx9.resource_type);
2277 surf->cb_color_attrib2 = S_028C68_MIP0_WIDTH(surf->width0 - 1) |
2278 S_028C68_MIP0_HEIGHT(surf->height0 - 1) |
2279 S_028C68_MAX_MIP(rtex->resource.b.b.last_level);
2280 }
2281
2282 /* Determine pixel shader export format */
2283 si_choose_spi_color_formats(surf, format, swap, ntype, rtex->is_depth);
2284
2285 surf->color_initialized = true;
2286 }
2287
2288 static void si_init_depth_surface(struct si_context *sctx,
2289 struct r600_surface *surf)
2290 {
2291 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2292 unsigned level = surf->base.u.tex.level;
2293 unsigned format, stencil_format;
2294 uint32_t z_info, s_info;
2295
2296 format = si_translate_dbformat(rtex->db_render_format);
2297 stencil_format = rtex->surface.flags & RADEON_SURF_SBUFFER ?
2298 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
2299
2300 assert(format != V_028040_Z_INVALID);
2301 if (format == V_028040_Z_INVALID)
2302 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
2303
2304 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2305 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2306 surf->db_htile_data_base = 0;
2307 surf->db_htile_surface = 0;
2308
2309 if (sctx->b.chip_class >= GFX9) {
2310 assert(rtex->surface.u.gfx9.surf_offset == 0);
2311 surf->db_depth_base = rtex->resource.gpu_address >> 8;
2312 surf->db_stencil_base = (rtex->resource.gpu_address +
2313 rtex->surface.u.gfx9.stencil_offset) >> 8;
2314 z_info = S_028038_FORMAT(format) |
2315 S_028038_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples)) |
2316 S_028038_SW_MODE(rtex->surface.u.gfx9.surf.swizzle_mode) |
2317 S_028038_MAXMIP(rtex->resource.b.b.last_level);
2318 s_info = S_02803C_FORMAT(stencil_format) |
2319 S_02803C_SW_MODE(rtex->surface.u.gfx9.stencil.swizzle_mode);
2320 surf->db_z_info2 = S_028068_EPITCH(rtex->surface.u.gfx9.surf.epitch);
2321 surf->db_stencil_info2 = S_02806C_EPITCH(rtex->surface.u.gfx9.stencil.epitch);
2322 surf->db_depth_view |= S_028008_MIPID(level);
2323 surf->db_depth_size = S_02801C_X_MAX(rtex->resource.b.b.width0 - 1) |
2324 S_02801C_Y_MAX(rtex->resource.b.b.height0 - 1);
2325
2326 /* Only use HTILE for the first level. */
2327 if (rtex->htile_offset && !level) {
2328 z_info |= S_028038_TILE_SURFACE_ENABLE(1) |
2329 S_028038_ALLOW_EXPCLEAR(1);
2330
2331 if (rtex->tc_compatible_htile) {
2332 unsigned max_zplanes = 4;
2333
2334 if (rtex->db_render_format == PIPE_FORMAT_Z16_UNORM &&
2335 rtex->resource.b.b.nr_samples > 1)
2336 max_zplanes = 2;
2337
2338 z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1) |
2339 S_028038_ITERATE_FLUSH(1);
2340 s_info |= S_02803C_ITERATE_FLUSH(1);
2341 }
2342
2343 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
2344 /* Stencil buffer workaround ported from the SI-CI-VI code.
2345 * See that for explanation.
2346 */
2347 s_info |= S_02803C_ALLOW_EXPCLEAR(rtex->resource.b.b.nr_samples <= 1);
2348 } else {
2349 /* Use all HTILE for depth if there's no stencil. */
2350 s_info |= S_02803C_TILE_STENCIL_DISABLE(1);
2351 }
2352
2353 surf->db_htile_data_base = (rtex->resource.gpu_address +
2354 rtex->htile_offset) >> 8;
2355 surf->db_htile_surface = S_028ABC_FULL_CACHE(1) |
2356 S_028ABC_PIPE_ALIGNED(rtex->surface.u.gfx9.htile.pipe_aligned) |
2357 S_028ABC_RB_ALIGNED(rtex->surface.u.gfx9.htile.rb_aligned);
2358 }
2359 } else {
2360 /* SI-CI-VI */
2361 struct legacy_surf_level *levelinfo = &rtex->surface.u.legacy.level[level];
2362
2363 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2364
2365 surf->db_depth_base = (rtex->resource.gpu_address +
2366 rtex->surface.u.legacy.level[level].offset) >> 8;
2367 surf->db_stencil_base = (rtex->resource.gpu_address +
2368 rtex->surface.u.legacy.stencil_level[level].offset) >> 8;
2369
2370 z_info = S_028040_FORMAT(format) |
2371 S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
2372 s_info = S_028044_FORMAT(stencil_format);
2373 surf->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!rtex->tc_compatible_htile);
2374
2375 if (sctx->b.chip_class >= CIK) {
2376 struct radeon_info *info = &sctx->screen->b.info;
2377 unsigned index = rtex->surface.u.legacy.tiling_index[level];
2378 unsigned stencil_index = rtex->surface.u.legacy.stencil_tiling_index[level];
2379 unsigned macro_index = rtex->surface.u.legacy.macro_tile_index;
2380 unsigned tile_mode = info->si_tile_mode_array[index];
2381 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2382 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2383
2384 surf->db_depth_info |=
2385 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2386 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2387 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2388 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2389 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2390 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2391 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2392 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2393 } else {
2394 unsigned tile_mode_index = si_tile_mode_index(rtex, level, false);
2395 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2396 tile_mode_index = si_tile_mode_index(rtex, level, true);
2397 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2398 }
2399
2400 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2401 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2402 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2403 levelinfo->nblk_y) / 64 - 1);
2404
2405 /* Only use HTILE for the first level. */
2406 if (rtex->htile_offset && !level) {
2407 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2408 S_028040_ALLOW_EXPCLEAR(1);
2409
2410 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
2411 /* Workaround: For a not yet understood reason, the
2412 * combination of MSAA, fast stencil clear and stencil
2413 * decompress messes with subsequent stencil buffer
2414 * uses. Problem was reproduced on Verde, Bonaire,
2415 * Tonga, and Carrizo.
2416 *
2417 * Disabling EXPCLEAR works around the problem.
2418 *
2419 * Check piglit's arb_texture_multisample-stencil-clear
2420 * test if you want to try changing this.
2421 */
2422 if (rtex->resource.b.b.nr_samples <= 1)
2423 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2424 } else if (!rtex->tc_compatible_htile) {
2425 /* Use all of the htile_buffer for depth if there's no stencil.
2426 * This must not be set when TC-compatible HTILE is enabled
2427 * due to a hw bug.
2428 */
2429 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2430 }
2431
2432 surf->db_htile_data_base = (rtex->resource.gpu_address +
2433 rtex->htile_offset) >> 8;
2434 surf->db_htile_surface = S_028ABC_FULL_CACHE(1);
2435
2436 if (rtex->tc_compatible_htile) {
2437 surf->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
2438
2439 if (rtex->resource.b.b.nr_samples <= 1)
2440 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2441 else if (rtex->resource.b.b.nr_samples <= 4)
2442 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2443 else
2444 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2445 }
2446 }
2447 }
2448
2449 surf->db_z_info = z_info;
2450 surf->db_stencil_info = s_info;
2451
2452 surf->depth_initialized = true;
2453 }
2454
2455 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
2456 {
2457 for (int i = 0; i < state->nr_cbufs; ++i) {
2458 struct r600_surface *surf = NULL;
2459 struct r600_texture *rtex;
2460
2461 if (!state->cbufs[i])
2462 continue;
2463 surf = (struct r600_surface*)state->cbufs[i];
2464 rtex = (struct r600_texture*)surf->base.texture;
2465
2466 p_atomic_dec(&rtex->framebuffers_bound);
2467 }
2468 }
2469
2470 static void si_set_framebuffer_state(struct pipe_context *ctx,
2471 const struct pipe_framebuffer_state *state)
2472 {
2473 struct si_context *sctx = (struct si_context *)ctx;
2474 struct pipe_constant_buffer constbuf = {0};
2475 struct r600_surface *surf = NULL;
2476 struct r600_texture *rtex;
2477 bool old_any_dst_linear = sctx->framebuffer.any_dst_linear;
2478 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2479 bool unbound = false;
2480 int i;
2481
2482 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
2483 if (!sctx->framebuffer.state.cbufs[i])
2484 continue;
2485
2486 rtex = (struct r600_texture*)sctx->framebuffer.state.cbufs[i]->texture;
2487 if (rtex->dcc_gather_statistics)
2488 vi_separate_dcc_stop_query(ctx, rtex);
2489 }
2490
2491 /* Disable DCC if the formats are incompatible. */
2492 for (i = 0; i < state->nr_cbufs; i++) {
2493 if (!state->cbufs[i])
2494 continue;
2495
2496 surf = (struct r600_surface*)state->cbufs[i];
2497 rtex = (struct r600_texture*)surf->base.texture;
2498
2499 if (!surf->dcc_incompatible)
2500 continue;
2501
2502 /* Since the DCC decompression calls back into set_framebuffer-
2503 * _state, we need to unbind the framebuffer, so that
2504 * vi_separate_dcc_stop_query isn't called twice with the same
2505 * color buffer.
2506 */
2507 if (!unbound) {
2508 util_copy_framebuffer_state(&sctx->framebuffer.state, NULL);
2509 unbound = true;
2510 }
2511
2512 if (vi_dcc_enabled(rtex, surf->base.u.tex.level))
2513 if (!r600_texture_disable_dcc(&sctx->b, rtex))
2514 sctx->b.decompress_dcc(ctx, rtex);
2515
2516 surf->dcc_incompatible = false;
2517 }
2518
2519 /* Only flush TC when changing the framebuffer state, because
2520 * the only client not using TC that can change textures is
2521 * the framebuffer.
2522 *
2523 * Wait for compute shaders because of possible transitions:
2524 * - FB write -> shader read
2525 * - shader write -> FB read
2526 *
2527 * DB caches are flushed on demand (using si_decompress_textures).
2528 *
2529 * When MSAA is enabled, CB and TC caches are flushed on demand
2530 * (after FMASK decompression). Shader write -> FB read transitions
2531 * cannot happen for MSAA textures, because MSAA shader images are
2532 * not supported.
2533 *
2534 * Only flush and wait for CB if there is actually a bound color buffer.
2535 */
2536 if (sctx->framebuffer.nr_samples <= 1 &&
2537 sctx->framebuffer.state.nr_cbufs) {
2538 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
2539 SI_CONTEXT_INV_GLOBAL_L2 |
2540 SI_CONTEXT_FLUSH_AND_INV_CB;
2541 }
2542 sctx->b.flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
2543
2544 /* u_blitter doesn't invoke depth decompression when it does multiple
2545 * blits in a row, but the only case when it matters for DB is when
2546 * doing generate_mipmap. So here we flush DB manually between
2547 * individual generate_mipmap blits.
2548 * Note that lower mipmap levels aren't compressed.
2549 */
2550 if (sctx->generate_mipmap_for_depth) {
2551 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
2552 SI_CONTEXT_INV_GLOBAL_L2 |
2553 SI_CONTEXT_FLUSH_AND_INV_DB;
2554 }
2555
2556 /* Take the maximum of the old and new count. If the new count is lower,
2557 * dirtying is needed to disable the unbound colorbuffers.
2558 */
2559 sctx->framebuffer.dirty_cbufs |=
2560 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2561 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2562
2563 si_dec_framebuffer_counters(&sctx->framebuffer.state);
2564 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2565
2566 sctx->framebuffer.colorbuf_enabled_4bit = 0;
2567 sctx->framebuffer.spi_shader_col_format = 0;
2568 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2569 sctx->framebuffer.spi_shader_col_format_blend = 0;
2570 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2571 sctx->framebuffer.color_is_int8 = 0;
2572 sctx->framebuffer.color_is_int10 = 0;
2573
2574 sctx->framebuffer.compressed_cb_mask = 0;
2575 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2576 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2577 sctx->framebuffer.any_dst_linear = false;
2578
2579 for (i = 0; i < state->nr_cbufs; i++) {
2580 if (!state->cbufs[i])
2581 continue;
2582
2583 surf = (struct r600_surface*)state->cbufs[i];
2584 rtex = (struct r600_texture*)surf->base.texture;
2585
2586 if (!surf->color_initialized) {
2587 si_initialize_color_surface(sctx, surf);
2588 }
2589
2590 sctx->framebuffer.colorbuf_enabled_4bit |= 0xf << (i * 4);
2591 sctx->framebuffer.spi_shader_col_format |=
2592 surf->spi_shader_col_format << (i * 4);
2593 sctx->framebuffer.spi_shader_col_format_alpha |=
2594 surf->spi_shader_col_format_alpha << (i * 4);
2595 sctx->framebuffer.spi_shader_col_format_blend |=
2596 surf->spi_shader_col_format_blend << (i * 4);
2597 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2598 surf->spi_shader_col_format_blend_alpha << (i * 4);
2599
2600 if (surf->color_is_int8)
2601 sctx->framebuffer.color_is_int8 |= 1 << i;
2602 if (surf->color_is_int10)
2603 sctx->framebuffer.color_is_int10 |= 1 << i;
2604
2605 if (rtex->fmask.size) {
2606 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2607 }
2608
2609 if (rtex->surface.is_linear)
2610 sctx->framebuffer.any_dst_linear = true;
2611
2612 r600_context_add_resource_size(ctx, surf->base.texture);
2613
2614 p_atomic_inc(&rtex->framebuffers_bound);
2615
2616 if (rtex->dcc_gather_statistics) {
2617 /* Dirty tracking must be enabled for DCC usage analysis. */
2618 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2619 vi_separate_dcc_start_query(ctx, rtex);
2620 }
2621 }
2622
2623 if (state->zsbuf) {
2624 surf = (struct r600_surface*)state->zsbuf;
2625 rtex = (struct r600_texture*)surf->base.texture;
2626
2627 if (!surf->depth_initialized) {
2628 si_init_depth_surface(sctx, surf);
2629 }
2630 r600_context_add_resource_size(ctx, surf->base.texture);
2631 }
2632
2633 si_update_poly_offset_state(sctx);
2634 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2635 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
2636
2637 if (sctx->framebuffer.any_dst_linear != old_any_dst_linear)
2638 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2639
2640 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2641 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2642 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2643
2644 /* Set sample locations as fragment shader constants. */
2645 switch (sctx->framebuffer.nr_samples) {
2646 case 1:
2647 constbuf.user_buffer = sctx->b.sample_locations_1x;
2648 break;
2649 case 2:
2650 constbuf.user_buffer = sctx->b.sample_locations_2x;
2651 break;
2652 case 4:
2653 constbuf.user_buffer = sctx->b.sample_locations_4x;
2654 break;
2655 case 8:
2656 constbuf.user_buffer = sctx->b.sample_locations_8x;
2657 break;
2658 case 16:
2659 constbuf.user_buffer = sctx->b.sample_locations_16x;
2660 break;
2661 default:
2662 R600_ERR("Requested an invalid number of samples %i.\n",
2663 sctx->framebuffer.nr_samples);
2664 assert(0);
2665 }
2666 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2667 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
2668
2669 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
2670 }
2671
2672 sctx->do_update_shaders = true;
2673
2674 if (!sctx->decompression_enabled) {
2675 /* Prevent textures decompression when the framebuffer state
2676 * changes come from the decompression passes themselves.
2677 */
2678 sctx->need_check_render_feedback = true;
2679 sctx->framebuffer.do_update_surf_dirtiness = true;
2680 }
2681 }
2682
2683 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
2684 {
2685 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2686 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2687 unsigned i, nr_cbufs = state->nr_cbufs;
2688 struct r600_texture *tex = NULL;
2689 struct r600_surface *cb = NULL;
2690 unsigned cb_color_info = 0;
2691
2692 /* Colorbuffers. */
2693 for (i = 0; i < nr_cbufs; i++) {
2694 uint64_t cb_color_base, cb_color_fmask, cb_dcc_base;
2695 unsigned cb_color_attrib;
2696
2697 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2698 continue;
2699
2700 cb = (struct r600_surface*)state->cbufs[i];
2701 if (!cb) {
2702 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2703 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2704 continue;
2705 }
2706
2707 tex = (struct r600_texture *)cb->base.texture;
2708 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2709 &tex->resource, RADEON_USAGE_READWRITE,
2710 tex->resource.b.b.nr_samples > 1 ?
2711 RADEON_PRIO_COLOR_BUFFER_MSAA :
2712 RADEON_PRIO_COLOR_BUFFER);
2713
2714 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2715 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2716 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2717 RADEON_PRIO_CMASK);
2718 }
2719
2720 if (tex->dcc_separate_buffer)
2721 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2722 tex->dcc_separate_buffer,
2723 RADEON_USAGE_READWRITE,
2724 RADEON_PRIO_DCC);
2725
2726 /* Compute mutable surface parameters. */
2727 cb_color_base = tex->resource.gpu_address >> 8;
2728 cb_color_fmask = cb_color_base;
2729 cb_dcc_base = 0;
2730 cb_color_info = cb->cb_color_info | tex->cb_color_info;
2731 cb_color_attrib = cb->cb_color_attrib;
2732
2733 if (tex->fmask.size)
2734 cb_color_fmask = (tex->resource.gpu_address + tex->fmask.offset) >> 8;
2735
2736 /* Set up DCC. */
2737 if (vi_dcc_enabled(tex, cb->base.u.tex.level)) {
2738 bool is_msaa_resolve_dst = state->cbufs[0] &&
2739 state->cbufs[0]->texture->nr_samples > 1 &&
2740 state->cbufs[1] == &cb->base &&
2741 state->cbufs[1]->texture->nr_samples <= 1;
2742
2743 if (!is_msaa_resolve_dst)
2744 cb_color_info |= S_028C70_DCC_ENABLE(1);
2745
2746 cb_dcc_base = ((!tex->dcc_separate_buffer ? tex->resource.gpu_address : 0) +
2747 tex->dcc_offset) >> 8;
2748 }
2749
2750 if (sctx->b.chip_class >= GFX9) {
2751 struct gfx9_surf_meta_flags meta;
2752
2753 if (tex->dcc_offset)
2754 meta = tex->surface.u.gfx9.dcc;
2755 else
2756 meta = tex->surface.u.gfx9.cmask;
2757
2758 /* Set mutable surface parameters. */
2759 cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
2760 cb_color_attrib |= S_028C74_COLOR_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
2761 S_028C74_FMASK_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
2762 S_028C74_RB_ALIGNED(meta.rb_aligned) |
2763 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
2764
2765 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 15);
2766 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
2767 radeon_emit(cs, cb_color_base >> 32); /* CB_COLOR0_BASE_EXT */
2768 radeon_emit(cs, cb->cb_color_attrib2); /* CB_COLOR0_ATTRIB2 */
2769 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
2770 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
2771 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
2772 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
2773 radeon_emit(cs, tex->cmask.base_address_reg); /* CB_COLOR0_CMASK */
2774 radeon_emit(cs, tex->cmask.base_address_reg >> 32); /* CB_COLOR0_CMASK_BASE_EXT */
2775 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
2776 radeon_emit(cs, cb_color_fmask >> 32); /* CB_COLOR0_FMASK_BASE_EXT */
2777 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
2778 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
2779 radeon_emit(cs, cb_dcc_base); /* CB_COLOR0_DCC_BASE */
2780 radeon_emit(cs, cb_dcc_base >> 32); /* CB_COLOR0_DCC_BASE_EXT */
2781
2782 radeon_set_context_reg(cs, R_0287A0_CB_MRT0_EPITCH + i * 4,
2783 S_0287A0_EPITCH(tex->surface.u.gfx9.surf.epitch));
2784 } else {
2785 /* Compute mutable surface parameters (SI-CI-VI). */
2786 const struct legacy_surf_level *level_info =
2787 &tex->surface.u.legacy.level[cb->base.u.tex.level];
2788 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
2789 unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
2790
2791 cb_color_base += level_info->offset >> 8;
2792 if (cb_dcc_base)
2793 cb_dcc_base += level_info->dcc_offset >> 8;
2794
2795 pitch_tile_max = level_info->nblk_x / 8 - 1;
2796 slice_tile_max = level_info->nblk_x *
2797 level_info->nblk_y / 64 - 1;
2798 tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false);
2799
2800 cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
2801 cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
2802 cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
2803
2804 if (tex->fmask.size) {
2805 if (sctx->b.chip_class >= CIK)
2806 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->fmask.pitch_in_pixels / 8 - 1);
2807 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->fmask.tile_mode_index);
2808 cb_color_fmask_slice = S_028C88_TILE_MAX(tex->fmask.slice_tile_max);
2809 } else {
2810 /* This must be set for fast clear to work without FMASK. */
2811 if (sctx->b.chip_class >= CIK)
2812 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
2813 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
2814 cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
2815 }
2816
2817 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
2818 sctx->b.chip_class >= VI ? 14 : 13);
2819 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
2820 radeon_emit(cs, cb_color_pitch); /* CB_COLOR0_PITCH */
2821 radeon_emit(cs, cb_color_slice); /* CB_COLOR0_SLICE */
2822 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
2823 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
2824 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
2825 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
2826 radeon_emit(cs, tex->cmask.base_address_reg); /* CB_COLOR0_CMASK */
2827 radeon_emit(cs, tex->cmask.slice_tile_max); /* CB_COLOR0_CMASK_SLICE */
2828 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
2829 radeon_emit(cs, cb_color_fmask_slice); /* CB_COLOR0_FMASK_SLICE */
2830 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
2831 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
2832
2833 if (sctx->b.chip_class >= VI) /* R_028C94_CB_COLOR0_DCC_BASE */
2834 radeon_emit(cs, cb_dcc_base);
2835 }
2836 }
2837 for (; i < 8 ; i++)
2838 if (sctx->framebuffer.dirty_cbufs & (1 << i))
2839 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
2840
2841 /* ZS buffer. */
2842 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
2843 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
2844 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
2845
2846 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2847 &rtex->resource, RADEON_USAGE_READWRITE,
2848 zb->base.texture->nr_samples > 1 ?
2849 RADEON_PRIO_DEPTH_BUFFER_MSAA :
2850 RADEON_PRIO_DEPTH_BUFFER);
2851
2852 if (sctx->b.chip_class >= GFX9) {
2853 radeon_set_context_reg_seq(cs, R_028014_DB_HTILE_DATA_BASE, 3);
2854 radeon_emit(cs, zb->db_htile_data_base); /* DB_HTILE_DATA_BASE */
2855 radeon_emit(cs, zb->db_htile_data_base >> 32); /* DB_HTILE_DATA_BASE_HI */
2856 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
2857
2858 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 10);
2859 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
2860 S_028038_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
2861 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
2862 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
2863 radeon_emit(cs, zb->db_depth_base >> 32); /* DB_Z_READ_BASE_HI */
2864 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
2865 radeon_emit(cs, zb->db_stencil_base >> 32); /* DB_STENCIL_READ_BASE_HI */
2866 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
2867 radeon_emit(cs, zb->db_depth_base >> 32); /* DB_Z_WRITE_BASE_HI */
2868 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
2869 radeon_emit(cs, zb->db_stencil_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
2870
2871 radeon_set_context_reg_seq(cs, R_028068_DB_Z_INFO2, 2);
2872 radeon_emit(cs, zb->db_z_info2); /* DB_Z_INFO2 */
2873 radeon_emit(cs, zb->db_stencil_info2); /* DB_STENCIL_INFO2 */
2874 } else {
2875 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
2876
2877 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
2878 radeon_emit(cs, zb->db_depth_info); /* DB_DEPTH_INFO */
2879 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
2880 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
2881 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
2882 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
2883 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
2884 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
2885 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
2886 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
2887 radeon_emit(cs, zb->db_depth_slice); /* DB_DEPTH_SLICE */
2888 }
2889
2890 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
2891 radeon_emit(cs, rtex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
2892 radeon_emit(cs, fui(rtex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
2893
2894 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
2895 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
2896 } else if (sctx->framebuffer.dirty_zsbuf) {
2897 if (sctx->b.chip_class >= GFX9)
2898 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 2);
2899 else
2900 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
2901
2902 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
2903 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
2904 }
2905
2906 /* Framebuffer dimensions. */
2907 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2908 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2909 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
2910
2911 if (sctx->b.chip_class >= GFX9) {
2912 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2913 radeon_emit(cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
2914 }
2915
2916 sctx->framebuffer.dirty_cbufs = 0;
2917 sctx->framebuffer.dirty_zsbuf = false;
2918 }
2919
2920 static void si_emit_msaa_sample_locs(struct si_context *sctx,
2921 struct r600_atom *atom)
2922 {
2923 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2924 unsigned nr_samples = sctx->framebuffer.nr_samples;
2925 bool has_msaa_sample_loc_bug = sctx->screen->has_msaa_sample_loc_bug;
2926
2927 /* Smoothing (only possible with nr_samples == 1) uses the same
2928 * sample locations as the MSAA it simulates.
2929 */
2930 if (nr_samples <= 1 && sctx->smoothing_enabled)
2931 nr_samples = SI_NUM_SMOOTH_AA_SAMPLES;
2932
2933 /* On Polaris, the small primitive filter uses the sample locations
2934 * even when MSAA is off, so we need to make sure they're set to 0.
2935 */
2936 if (has_msaa_sample_loc_bug)
2937 nr_samples = MAX2(nr_samples, 1);
2938
2939 if (nr_samples >= 1 &&
2940 (nr_samples != sctx->msaa_sample_locs.nr_samples)) {
2941 sctx->msaa_sample_locs.nr_samples = nr_samples;
2942 cayman_emit_msaa_sample_locs(cs, nr_samples);
2943 }
2944
2945 if (sctx->b.family >= CHIP_POLARIS10) {
2946 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
2947 unsigned small_prim_filter_cntl =
2948 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
2949 /* line bug */
2950 S_028830_LINE_FILTER_DISABLE(sctx->b.family <= CHIP_POLARIS12);
2951
2952 /* The alternative of setting sample locations to 0 would
2953 * require a DB flush to avoid Z errors, see
2954 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
2955 */
2956 if (has_msaa_sample_loc_bug &&
2957 sctx->framebuffer.nr_samples > 1 &&
2958 rs && !rs->multisample_enable)
2959 small_prim_filter_cntl &= C_028830_SMALL_PRIM_FILTER_ENABLE;
2960
2961 radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
2962 small_prim_filter_cntl);
2963 }
2964 }
2965
2966 static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom)
2967 {
2968 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2969 unsigned num_tile_pipes = sctx->screen->b.info.num_tile_pipes;
2970 /* 33% faster rendering to linear color buffers */
2971 bool dst_is_linear = sctx->framebuffer.any_dst_linear;
2972 unsigned sc_mode_cntl_1 =
2973 S_028A4C_WALK_SIZE(dst_is_linear) |
2974 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear) |
2975 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
2976 /* always 1: */
2977 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
2978 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
2979 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
2980 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
2981 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
2982 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
2983
2984 cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples,
2985 sctx->ps_iter_samples,
2986 sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0,
2987 sc_mode_cntl_1);
2988
2989 /* GFX9: Flush DFSM when the AA mode changes. */
2990 if (sctx->b.chip_class >= GFX9) {
2991 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2992 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
2993 }
2994 }
2995
2996 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
2997 {
2998 struct si_context *sctx = (struct si_context *)ctx;
2999
3000 if (sctx->ps_iter_samples == min_samples)
3001 return;
3002
3003 sctx->ps_iter_samples = min_samples;
3004 sctx->do_update_shaders = true;
3005
3006 if (sctx->framebuffer.nr_samples > 1)
3007 si_mark_atom_dirty(sctx, &sctx->msaa_config);
3008 }
3009
3010 /*
3011 * Samplers
3012 */
3013
3014 /**
3015 * Build the sampler view descriptor for a buffer texture.
3016 * @param state 256-bit descriptor; only the high 128 bits are filled in
3017 */
3018 void
3019 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
3020 enum pipe_format format,
3021 unsigned offset, unsigned size,
3022 uint32_t *state)
3023 {
3024 const struct util_format_description *desc;
3025 int first_non_void;
3026 unsigned stride;
3027 unsigned num_records;
3028 unsigned num_format, data_format;
3029
3030 desc = util_format_description(format);
3031 first_non_void = util_format_get_first_non_void_channel(format);
3032 stride = desc->block.bits / 8;
3033 num_format = si_translate_buffer_numformat(&screen->b.b, desc, first_non_void);
3034 data_format = si_translate_buffer_dataformat(&screen->b.b, desc, first_non_void);
3035
3036 num_records = size / stride;
3037 num_records = MIN2(num_records, (buf->b.b.width0 - offset) / stride);
3038
3039 /* The NUM_RECORDS field has a different meaning depending on the chip,
3040 * instruction type, STRIDE, and SWIZZLE_ENABLE.
3041 *
3042 * SI-CIK:
3043 * - If STRIDE == 0, it's in byte units.
3044 * - If STRIDE != 0, it's in units of STRIDE, used with inst.IDXEN.
3045 *
3046 * VI:
3047 * - For SMEM and STRIDE == 0, it's in byte units.
3048 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3049 * - For VMEM and STRIDE == 0 or SWIZZLE_ENABLE == 0, it's in byte units.
3050 * - For VMEM and STRIDE != 0 and SWIZZLE_ENABLE == 1, it's in units of STRIDE.
3051 * NOTE: There is incompatibility between VMEM and SMEM opcodes due to SWIZZLE_-
3052 * ENABLE. The workaround is to set STRIDE = 0 if SWIZZLE_ENABLE == 0 when
3053 * using SMEM. This can be done in the shader by clearing STRIDE with s_and.
3054 * That way the same descriptor can be used by both SMEM and VMEM.
3055 *
3056 * GFX9:
3057 * - For SMEM and STRIDE == 0, it's in byte units.
3058 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3059 * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
3060 * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
3061 */
3062 if (screen->b.chip_class >= GFX9)
3063 /* When vindex == 0, LLVM sets IDXEN = 0, thus changing units
3064 * from STRIDE to bytes. This works around it by setting
3065 * NUM_RECORDS to at least the size of one element, so that
3066 * the first element is readable when IDXEN == 0.
3067 *
3068 * TODO: Fix this in LLVM, but do we need a new intrinsic where
3069 * IDXEN is enforced?
3070 */
3071 num_records = num_records ? MAX2(num_records, stride) : 0;
3072 else if (screen->b.chip_class == VI)
3073 num_records *= stride;
3074
3075 state[4] = 0;
3076 state[5] = S_008F04_STRIDE(stride);
3077 state[6] = num_records;
3078 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3079 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3080 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3081 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
3082 S_008F0C_NUM_FORMAT(num_format) |
3083 S_008F0C_DATA_FORMAT(data_format);
3084 }
3085
3086 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle[4])
3087 {
3088 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3089
3090 if (swizzle[3] == PIPE_SWIZZLE_X) {
3091 /* For the pre-defined border color values (white, opaque
3092 * black, transparent black), the only thing that matters is
3093 * that the alpha channel winds up in the correct place
3094 * (because the RGB channels are all the same) so either of
3095 * these enumerations will work.
3096 */
3097 if (swizzle[2] == PIPE_SWIZZLE_Y)
3098 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
3099 else
3100 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
3101 } else if (swizzle[0] == PIPE_SWIZZLE_X) {
3102 if (swizzle[1] == PIPE_SWIZZLE_Y)
3103 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3104 else
3105 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
3106 } else if (swizzle[1] == PIPE_SWIZZLE_X) {
3107 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
3108 } else if (swizzle[2] == PIPE_SWIZZLE_X) {
3109 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
3110 }
3111
3112 return bc_swizzle;
3113 }
3114
3115 /**
3116 * Build the sampler view descriptor for a texture.
3117 */
3118 void
3119 si_make_texture_descriptor(struct si_screen *screen,
3120 struct r600_texture *tex,
3121 bool sampler,
3122 enum pipe_texture_target target,
3123 enum pipe_format pipe_format,
3124 const unsigned char state_swizzle[4],
3125 unsigned first_level, unsigned last_level,
3126 unsigned first_layer, unsigned last_layer,
3127 unsigned width, unsigned height, unsigned depth,
3128 uint32_t *state,
3129 uint32_t *fmask_state)
3130 {
3131 struct pipe_resource *res = &tex->resource.b.b;
3132 const struct util_format_description *base_desc, *desc;
3133 unsigned char swizzle[4];
3134 int first_non_void;
3135 unsigned num_format, data_format, type;
3136 uint64_t va;
3137
3138 desc = util_format_description(pipe_format);
3139 base_desc = util_format_description(res->format);
3140
3141 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
3142 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
3143 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
3144 const unsigned char swizzle_wwww[4] = {3, 3, 3, 3};
3145
3146 switch (pipe_format) {
3147 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3148 case PIPE_FORMAT_X32_S8X24_UINT:
3149 case PIPE_FORMAT_X8Z24_UNORM:
3150 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3151 break;
3152 case PIPE_FORMAT_X24S8_UINT:
3153 /*
3154 * X24S8 is implemented as an 8_8_8_8 data format, to
3155 * fix texture gathers. This affects at least
3156 * GL45-CTS.texture_cube_map_array.sampling on VI.
3157 */
3158 util_format_compose_swizzles(swizzle_wwww, state_swizzle, swizzle);
3159 break;
3160 default:
3161 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
3162 }
3163 } else {
3164 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
3165 }
3166
3167 first_non_void = util_format_get_first_non_void_channel(pipe_format);
3168
3169 switch (pipe_format) {
3170 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3171 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3172 break;
3173 default:
3174 if (first_non_void < 0) {
3175 if (util_format_is_compressed(pipe_format)) {
3176 switch (pipe_format) {
3177 case PIPE_FORMAT_DXT1_SRGB:
3178 case PIPE_FORMAT_DXT1_SRGBA:
3179 case PIPE_FORMAT_DXT3_SRGBA:
3180 case PIPE_FORMAT_DXT5_SRGBA:
3181 case PIPE_FORMAT_BPTC_SRGBA:
3182 case PIPE_FORMAT_ETC2_SRGB8:
3183 case PIPE_FORMAT_ETC2_SRGB8A1:
3184 case PIPE_FORMAT_ETC2_SRGBA8:
3185 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3186 break;
3187 case PIPE_FORMAT_RGTC1_SNORM:
3188 case PIPE_FORMAT_LATC1_SNORM:
3189 case PIPE_FORMAT_RGTC2_SNORM:
3190 case PIPE_FORMAT_LATC2_SNORM:
3191 case PIPE_FORMAT_ETC2_R11_SNORM:
3192 case PIPE_FORMAT_ETC2_RG11_SNORM:
3193 /* implies float, so use SNORM/UNORM to determine
3194 whether data is signed or not */
3195 case PIPE_FORMAT_BPTC_RGB_FLOAT:
3196 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3197 break;
3198 default:
3199 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3200 break;
3201 }
3202 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
3203 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3204 } else {
3205 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3206 }
3207 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
3208 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3209 } else {
3210 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3211
3212 switch (desc->channel[first_non_void].type) {
3213 case UTIL_FORMAT_TYPE_FLOAT:
3214 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3215 break;
3216 case UTIL_FORMAT_TYPE_SIGNED:
3217 if (desc->channel[first_non_void].normalized)
3218 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3219 else if (desc->channel[first_non_void].pure_integer)
3220 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
3221 else
3222 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
3223 break;
3224 case UTIL_FORMAT_TYPE_UNSIGNED:
3225 if (desc->channel[first_non_void].normalized)
3226 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3227 else if (desc->channel[first_non_void].pure_integer)
3228 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3229 else
3230 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
3231 }
3232 }
3233 }
3234
3235 data_format = si_translate_texformat(&screen->b.b, pipe_format, desc, first_non_void);
3236 if (data_format == ~0) {
3237 data_format = 0;
3238 }
3239
3240 /* Enable clamping for UNORM depth formats promoted to Z32F. */
3241 if (screen->b.chip_class >= GFX9 &&
3242 util_format_has_depth(desc) &&
3243 num_format == V_008F14_IMG_NUM_FORMAT_FLOAT &&
3244 util_get_depth_format_type(base_desc) != UTIL_FORMAT_TYPE_FLOAT) {
3245 /* NUM_FORMAT=FLOAT and DATA_FORMAT=24_8 means "clamp to [0,1]". */
3246 data_format = V_008F14_IMG_DATA_FORMAT_24_8;
3247 }
3248
3249 /* S8 with Z32 HTILE needs a special format. */
3250 if (screen->b.chip_class >= GFX9 &&
3251 pipe_format == PIPE_FORMAT_S8_UINT &&
3252 tex->tc_compatible_htile)
3253 data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
3254
3255 if (!sampler &&
3256 (res->target == PIPE_TEXTURE_CUBE ||
3257 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
3258 (screen->b.chip_class <= VI &&
3259 res->target == PIPE_TEXTURE_3D))) {
3260 /* For the purpose of shader images, treat cube maps and 3D
3261 * textures as 2D arrays. For 3D textures, the address
3262 * calculations for mipmaps are different, so we rely on the
3263 * caller to effectively disable mipmaps.
3264 */
3265 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
3266
3267 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
3268 } else {
3269 type = si_tex_dim(screen, tex, target, res->nr_samples);
3270 }
3271
3272 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
3273 height = 1;
3274 depth = res->array_size;
3275 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
3276 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
3277 if (sampler || res->target != PIPE_TEXTURE_3D)
3278 depth = res->array_size;
3279 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
3280 depth = res->array_size / 6;
3281
3282 state[0] = 0;
3283 state[1] = (S_008F14_DATA_FORMAT_GFX6(data_format) |
3284 S_008F14_NUM_FORMAT_GFX6(num_format));
3285 state[2] = (S_008F18_WIDTH(width - 1) |
3286 S_008F18_HEIGHT(height - 1) |
3287 S_008F18_PERF_MOD(4));
3288 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
3289 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
3290 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
3291 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
3292 S_008F1C_BASE_LEVEL(res->nr_samples > 1 ?
3293 0 : first_level) |
3294 S_008F1C_LAST_LEVEL(res->nr_samples > 1 ?
3295 util_logbase2(res->nr_samples) :
3296 last_level) |
3297 S_008F1C_TYPE(type));
3298 state[4] = 0;
3299 state[5] = S_008F24_BASE_ARRAY(first_layer);
3300 state[6] = 0;
3301 state[7] = 0;
3302
3303 if (screen->b.chip_class >= GFX9) {
3304 unsigned bc_swizzle = gfx9_border_color_swizzle(desc->swizzle);
3305
3306 /* Depth is the the last accessible layer on Gfx9.
3307 * The hw doesn't need to know the total number of layers.
3308 */
3309 if (type == V_008F1C_SQ_RSRC_IMG_3D)
3310 state[4] |= S_008F20_DEPTH(depth - 1);
3311 else
3312 state[4] |= S_008F20_DEPTH(last_layer);
3313
3314 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
3315 state[5] |= S_008F24_MAX_MIP(res->nr_samples > 1 ?
3316 util_logbase2(res->nr_samples) :
3317 tex->resource.b.b.last_level);
3318 } else {
3319 state[3] |= S_008F1C_POW2_PAD(res->last_level > 0);
3320 state[4] |= S_008F20_DEPTH(depth - 1);
3321 state[5] |= S_008F24_LAST_ARRAY(last_layer);
3322 }
3323
3324 if (tex->dcc_offset) {
3325 unsigned swap = r600_translate_colorswap(pipe_format, false);
3326
3327 state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
3328 } else {
3329 /* The last dword is unused by hw. The shader uses it to clear
3330 * bits in the first dword of sampler state.
3331 */
3332 if (screen->b.chip_class <= CIK && res->nr_samples <= 1) {
3333 if (first_level == last_level)
3334 state[7] = C_008F30_MAX_ANISO_RATIO;
3335 else
3336 state[7] = 0xffffffff;
3337 }
3338 }
3339
3340 /* Initialize the sampler view for FMASK. */
3341 if (tex->fmask.size) {
3342 uint32_t data_format, num_format;
3343
3344 va = tex->resource.gpu_address + tex->fmask.offset;
3345
3346 if (screen->b.chip_class >= GFX9) {
3347 data_format = V_008F14_IMG_DATA_FORMAT_FMASK;
3348 switch (res->nr_samples) {
3349 case 2:
3350 num_format = V_008F14_IMG_FMASK_8_2_2;
3351 break;
3352 case 4:
3353 num_format = V_008F14_IMG_FMASK_8_4_4;
3354 break;
3355 case 8:
3356 num_format = V_008F14_IMG_FMASK_32_8_8;
3357 break;
3358 default:
3359 unreachable("invalid nr_samples");
3360 }
3361 } else {
3362 switch (res->nr_samples) {
3363 case 2:
3364 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
3365 break;
3366 case 4:
3367 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
3368 break;
3369 case 8:
3370 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
3371 break;
3372 default:
3373 unreachable("invalid nr_samples");
3374 }
3375 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3376 }
3377
3378 fmask_state[0] = va >> 8;
3379 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
3380 S_008F14_DATA_FORMAT_GFX6(data_format) |
3381 S_008F14_NUM_FORMAT_GFX6(num_format);
3382 fmask_state[2] = S_008F18_WIDTH(width - 1) |
3383 S_008F18_HEIGHT(height - 1);
3384 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
3385 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
3386 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
3387 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
3388 S_008F1C_TYPE(si_tex_dim(screen, tex, target, 0));
3389 fmask_state[4] = 0;
3390 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
3391 fmask_state[6] = 0;
3392 fmask_state[7] = 0;
3393
3394 if (screen->b.chip_class >= GFX9) {
3395 fmask_state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode);
3396 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
3397 S_008F20_PITCH_GFX9(tex->surface.u.gfx9.fmask.epitch);
3398 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned) |
3399 S_008F24_META_RB_ALIGNED(tex->surface.u.gfx9.cmask.rb_aligned);
3400 } else {
3401 fmask_state[3] |= S_008F1C_TILING_INDEX(tex->fmask.tile_mode_index);
3402 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
3403 S_008F20_PITCH_GFX6(tex->fmask.pitch_in_pixels - 1);
3404 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
3405 }
3406 }
3407 }
3408
3409 /**
3410 * Create a sampler view.
3411 *
3412 * @param ctx context
3413 * @param texture texture
3414 * @param state sampler view template
3415 * @param width0 width0 override (for compressed textures as int)
3416 * @param height0 height0 override (for compressed textures as int)
3417 * @param force_level set the base address to the level (for compressed textures)
3418 */
3419 struct pipe_sampler_view *
3420 si_create_sampler_view_custom(struct pipe_context *ctx,
3421 struct pipe_resource *texture,
3422 const struct pipe_sampler_view *state,
3423 unsigned width0, unsigned height0,
3424 unsigned force_level)
3425 {
3426 struct si_context *sctx = (struct si_context*)ctx;
3427 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
3428 struct r600_texture *tmp = (struct r600_texture*)texture;
3429 unsigned base_level, first_level, last_level;
3430 unsigned char state_swizzle[4];
3431 unsigned height, depth, width;
3432 unsigned last_layer = state->u.tex.last_layer;
3433 enum pipe_format pipe_format;
3434 const struct legacy_surf_level *surflevel;
3435
3436 if (!view)
3437 return NULL;
3438
3439 /* initialize base object */
3440 view->base = *state;
3441 view->base.texture = NULL;
3442 view->base.reference.count = 1;
3443 view->base.context = ctx;
3444
3445 assert(texture);
3446 pipe_resource_reference(&view->base.texture, texture);
3447
3448 if (state->format == PIPE_FORMAT_X24S8_UINT ||
3449 state->format == PIPE_FORMAT_S8X24_UINT ||
3450 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
3451 state->format == PIPE_FORMAT_S8_UINT)
3452 view->is_stencil_sampler = true;
3453
3454 /* Buffer resource. */
3455 if (texture->target == PIPE_BUFFER) {
3456 si_make_buffer_descriptor(sctx->screen,
3457 (struct r600_resource *)texture,
3458 state->format,
3459 state->u.buf.offset,
3460 state->u.buf.size,
3461 view->state);
3462 return &view->base;
3463 }
3464
3465 state_swizzle[0] = state->swizzle_r;
3466 state_swizzle[1] = state->swizzle_g;
3467 state_swizzle[2] = state->swizzle_b;
3468 state_swizzle[3] = state->swizzle_a;
3469
3470 base_level = 0;
3471 first_level = state->u.tex.first_level;
3472 last_level = state->u.tex.last_level;
3473 width = width0;
3474 height = height0;
3475 depth = texture->depth0;
3476
3477 if (sctx->b.chip_class <= VI && force_level) {
3478 assert(force_level == first_level &&
3479 force_level == last_level);
3480 base_level = force_level;
3481 first_level = 0;
3482 last_level = 0;
3483 width = u_minify(width, force_level);
3484 height = u_minify(height, force_level);
3485 depth = u_minify(depth, force_level);
3486 }
3487
3488 /* This is not needed if state trackers set last_layer correctly. */
3489 if (state->target == PIPE_TEXTURE_1D ||
3490 state->target == PIPE_TEXTURE_2D ||
3491 state->target == PIPE_TEXTURE_RECT ||
3492 state->target == PIPE_TEXTURE_CUBE)
3493 last_layer = state->u.tex.first_layer;
3494
3495 /* Texturing with separate depth and stencil. */
3496 pipe_format = state->format;
3497
3498 /* Depth/stencil texturing sometimes needs separate texture. */
3499 if (tmp->is_depth && !r600_can_sample_zs(tmp, view->is_stencil_sampler)) {
3500 if (!tmp->flushed_depth_texture &&
3501 !r600_init_flushed_depth_texture(ctx, texture, NULL)) {
3502 pipe_resource_reference(&view->base.texture, NULL);
3503 FREE(view);
3504 return NULL;
3505 }
3506
3507 assert(tmp->flushed_depth_texture);
3508
3509 /* Override format for the case where the flushed texture
3510 * contains only Z or only S.
3511 */
3512 if (tmp->flushed_depth_texture->resource.b.b.format != tmp->resource.b.b.format)
3513 pipe_format = tmp->flushed_depth_texture->resource.b.b.format;
3514
3515 tmp = tmp->flushed_depth_texture;
3516 }
3517
3518 surflevel = tmp->surface.u.legacy.level;
3519
3520 if (tmp->db_compatible) {
3521 if (!view->is_stencil_sampler)
3522 pipe_format = tmp->db_render_format;
3523
3524 switch (pipe_format) {
3525 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
3526 pipe_format = PIPE_FORMAT_Z32_FLOAT;
3527 break;
3528 case PIPE_FORMAT_X8Z24_UNORM:
3529 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3530 /* Z24 is always stored like this for DB
3531 * compatibility.
3532 */
3533 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
3534 break;
3535 case PIPE_FORMAT_X24S8_UINT:
3536 case PIPE_FORMAT_S8X24_UINT:
3537 case PIPE_FORMAT_X32_S8X24_UINT:
3538 pipe_format = PIPE_FORMAT_S8_UINT;
3539 surflevel = tmp->surface.u.legacy.stencil_level;
3540 break;
3541 default:;
3542 }
3543 }
3544
3545 view->dcc_incompatible =
3546 vi_dcc_formats_are_incompatible(texture,
3547 state->u.tex.first_level,
3548 state->format);
3549
3550 si_make_texture_descriptor(sctx->screen, tmp, true,
3551 state->target, pipe_format, state_swizzle,
3552 first_level, last_level,
3553 state->u.tex.first_layer, last_layer,
3554 width, height, depth,
3555 view->state, view->fmask_state);
3556
3557 view->base_level_info = &surflevel[base_level];
3558 view->base_level = base_level;
3559 view->block_width = util_format_get_blockwidth(pipe_format);
3560 return &view->base;
3561 }
3562
3563 static struct pipe_sampler_view *
3564 si_create_sampler_view(struct pipe_context *ctx,
3565 struct pipe_resource *texture,
3566 const struct pipe_sampler_view *state)
3567 {
3568 return si_create_sampler_view_custom(ctx, texture, state,
3569 texture ? texture->width0 : 0,
3570 texture ? texture->height0 : 0, 0);
3571 }
3572
3573 static void si_sampler_view_destroy(struct pipe_context *ctx,
3574 struct pipe_sampler_view *state)
3575 {
3576 struct si_sampler_view *view = (struct si_sampler_view *)state;
3577
3578 pipe_resource_reference(&state->texture, NULL);
3579 FREE(view);
3580 }
3581
3582 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
3583 {
3584 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
3585 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
3586 (linear_filter &&
3587 (wrap == PIPE_TEX_WRAP_CLAMP ||
3588 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
3589 }
3590
3591 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
3592 {
3593 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
3594 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
3595
3596 return (state->border_color.ui[0] || state->border_color.ui[1] ||
3597 state->border_color.ui[2] || state->border_color.ui[3]) &&
3598 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
3599 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
3600 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
3601 }
3602
3603 static void *si_create_sampler_state(struct pipe_context *ctx,
3604 const struct pipe_sampler_state *state)
3605 {
3606 struct si_context *sctx = (struct si_context *)ctx;
3607 struct r600_common_screen *rscreen = sctx->b.screen;
3608 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
3609 unsigned border_color_type, border_color_index = 0;
3610 unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
3611 : state->max_anisotropy;
3612 unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso);
3613
3614 if (!rstate) {
3615 return NULL;
3616 }
3617
3618 if (!sampler_state_needs_border_color(state))
3619 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3620 else if (state->border_color.f[0] == 0 &&
3621 state->border_color.f[1] == 0 &&
3622 state->border_color.f[2] == 0 &&
3623 state->border_color.f[3] == 0)
3624 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3625 else if (state->border_color.f[0] == 0 &&
3626 state->border_color.f[1] == 0 &&
3627 state->border_color.f[2] == 0 &&
3628 state->border_color.f[3] == 1)
3629 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3630 else if (state->border_color.f[0] == 1 &&
3631 state->border_color.f[1] == 1 &&
3632 state->border_color.f[2] == 1 &&
3633 state->border_color.f[3] == 1)
3634 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3635 else {
3636 int i;
3637
3638 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
3639
3640 /* Check if the border has been uploaded already. */
3641 for (i = 0; i < sctx->border_color_count; i++)
3642 if (memcmp(&sctx->border_color_table[i], &state->border_color,
3643 sizeof(state->border_color)) == 0)
3644 break;
3645
3646 if (i >= SI_MAX_BORDER_COLORS) {
3647 /* Getting 4096 unique border colors is very unlikely. */
3648 fprintf(stderr, "radeonsi: The border color table is full. "
3649 "Any new border colors will be just black. "
3650 "Please file a bug.\n");
3651 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3652 } else {
3653 if (i == sctx->border_color_count) {
3654 /* Upload a new border color. */
3655 memcpy(&sctx->border_color_table[i], &state->border_color,
3656 sizeof(state->border_color));
3657 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
3658 &state->border_color,
3659 sizeof(state->border_color));
3660 sctx->border_color_count++;
3661 }
3662
3663 border_color_index = i;
3664 }
3665 }
3666
3667 #ifdef DEBUG
3668 rstate->magic = SI_SAMPLER_STATE_MAGIC;
3669 #endif
3670 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
3671 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
3672 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
3673 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3674 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
3675 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
3676 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
3677 S_008F30_ANISO_BIAS(max_aniso_ratio) |
3678 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
3679 S_008F30_COMPAT_MODE(sctx->b.chip_class >= VI));
3680 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
3681 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)) |
3682 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
3683 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
3684 S_008F38_XY_MAG_FILTER(eg_tex_filter(state->mag_img_filter, max_aniso)) |
3685 S_008F38_XY_MIN_FILTER(eg_tex_filter(state->min_img_filter, max_aniso)) |
3686 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
3687 S_008F38_MIP_POINT_PRECLAMP(1) |
3688 S_008F38_DISABLE_LSB_CEIL(sctx->b.chip_class <= VI) |
3689 S_008F38_FILTER_PREC_FIX(1) |
3690 S_008F38_ANISO_OVERRIDE(sctx->b.chip_class >= VI));
3691 rstate->val[3] = S_008F3C_BORDER_COLOR_PTR(border_color_index) |
3692 S_008F3C_BORDER_COLOR_TYPE(border_color_type);
3693 return rstate;
3694 }
3695
3696 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
3697 {
3698 struct si_context *sctx = (struct si_context *)ctx;
3699
3700 if (sctx->sample_mask.sample_mask == (uint16_t)sample_mask)
3701 return;
3702
3703 sctx->sample_mask.sample_mask = sample_mask;
3704 si_mark_atom_dirty(sctx, &sctx->sample_mask.atom);
3705 }
3706
3707 static void si_emit_sample_mask(struct si_context *sctx, struct r600_atom *atom)
3708 {
3709 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
3710 unsigned mask = sctx->sample_mask.sample_mask;
3711
3712 /* Needed for line and polygon smoothing as well as for the Polaris
3713 * small primitive filter. We expect the state tracker to take care of
3714 * this for us.
3715 */
3716 assert(mask == 0xffff || sctx->framebuffer.nr_samples > 1 ||
3717 (mask & 1 && sctx->blitter->running));
3718
3719 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3720 radeon_emit(cs, mask | (mask << 16));
3721 radeon_emit(cs, mask | (mask << 16));
3722 }
3723
3724 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
3725 {
3726 #ifdef DEBUG
3727 struct si_sampler_state *s = state;
3728
3729 assert(s->magic == SI_SAMPLER_STATE_MAGIC);
3730 s->magic = 0;
3731 #endif
3732 free(state);
3733 }
3734
3735 /*
3736 * Vertex elements & buffers
3737 */
3738
3739 static void *si_create_vertex_elements(struct pipe_context *ctx,
3740 unsigned count,
3741 const struct pipe_vertex_element *elements)
3742 {
3743 struct si_screen *sscreen = (struct si_screen*)ctx->screen;
3744 struct si_vertex_elements *v = CALLOC_STRUCT(si_vertex_elements);
3745 bool used[SI_NUM_VERTEX_BUFFERS] = {};
3746 int i;
3747
3748 assert(count <= SI_MAX_ATTRIBS);
3749 if (!v)
3750 return NULL;
3751
3752 v->count = count;
3753 v->desc_list_byte_size = align(count * 16, SI_CPDMA_ALIGNMENT);
3754
3755 for (i = 0; i < count; ++i) {
3756 const struct util_format_description *desc;
3757 const struct util_format_channel_description *channel;
3758 unsigned data_format, num_format;
3759 int first_non_void;
3760 unsigned vbo_index = elements[i].vertex_buffer_index;
3761 unsigned char swizzle[4];
3762
3763 if (vbo_index >= SI_NUM_VERTEX_BUFFERS) {
3764 FREE(v);
3765 return NULL;
3766 }
3767
3768 if (elements[i].instance_divisor) {
3769 v->uses_instance_divisors = true;
3770 v->instance_divisors[i] = elements[i].instance_divisor;
3771
3772 if (v->instance_divisors[i] == 1)
3773 v->instance_divisor_is_one |= 1u << i;
3774 else
3775 v->instance_divisor_is_fetched |= 1u << i;
3776 }
3777
3778 if (!used[vbo_index]) {
3779 v->first_vb_use_mask |= 1 << i;
3780 used[vbo_index] = true;
3781 }
3782
3783 desc = util_format_description(elements[i].src_format);
3784 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
3785 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
3786 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
3787 channel = first_non_void >= 0 ? &desc->channel[first_non_void] : NULL;
3788 memcpy(swizzle, desc->swizzle, sizeof(swizzle));
3789
3790 v->format_size[i] = desc->block.bits / 8;
3791 v->src_offset[i] = elements[i].src_offset;
3792 v->vertex_buffer_index[i] = vbo_index;
3793
3794 /* The hardware always treats the 2-bit alpha channel as
3795 * unsigned, so a shader workaround is needed. The affected
3796 * chips are VI and older except Stoney (GFX8.1).
3797 */
3798 if (data_format == V_008F0C_BUF_DATA_FORMAT_2_10_10_10 &&
3799 sscreen->b.chip_class <= VI &&
3800 sscreen->b.family != CHIP_STONEY) {
3801 if (num_format == V_008F0C_BUF_NUM_FORMAT_SNORM) {
3802 v->fix_fetch[i] = SI_FIX_FETCH_A2_SNORM;
3803 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SSCALED) {
3804 v->fix_fetch[i] = SI_FIX_FETCH_A2_SSCALED;
3805 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SINT) {
3806 /* This isn't actually used in OpenGL. */
3807 v->fix_fetch[i] = SI_FIX_FETCH_A2_SINT;
3808 }
3809 } else if (channel && channel->type == UTIL_FORMAT_TYPE_FIXED) {
3810 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
3811 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_FIXED;
3812 else
3813 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_FIXED;
3814 } else if (channel && channel->size == 32 && !channel->pure_integer) {
3815 if (channel->type == UTIL_FORMAT_TYPE_SIGNED) {
3816 if (channel->normalized) {
3817 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
3818 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_SNORM;
3819 else
3820 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SNORM;
3821 } else {
3822 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SSCALED;
3823 }
3824 } else if (channel->type == UTIL_FORMAT_TYPE_UNSIGNED) {
3825 if (channel->normalized) {
3826 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
3827 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_UNORM;
3828 else
3829 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_UNORM;
3830 } else {
3831 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_USCALED;
3832 }
3833 }
3834 } else if (channel && channel->size == 64 &&
3835 channel->type == UTIL_FORMAT_TYPE_FLOAT) {
3836 switch (desc->nr_channels) {
3837 case 1:
3838 case 2:
3839 v->fix_fetch[i] = SI_FIX_FETCH_RG_64_FLOAT;
3840 swizzle[0] = PIPE_SWIZZLE_X;
3841 swizzle[1] = PIPE_SWIZZLE_Y;
3842 swizzle[2] = desc->nr_channels == 2 ? PIPE_SWIZZLE_Z : PIPE_SWIZZLE_0;
3843 swizzle[3] = desc->nr_channels == 2 ? PIPE_SWIZZLE_W : PIPE_SWIZZLE_0;
3844 break;
3845 case 3:
3846 v->fix_fetch[i] = SI_FIX_FETCH_RGB_64_FLOAT;
3847 swizzle[0] = PIPE_SWIZZLE_X; /* 3 loads */
3848 swizzle[1] = PIPE_SWIZZLE_Y;
3849 swizzle[2] = PIPE_SWIZZLE_0;
3850 swizzle[3] = PIPE_SWIZZLE_0;
3851 break;
3852 case 4:
3853 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_64_FLOAT;
3854 swizzle[0] = PIPE_SWIZZLE_X; /* 2 loads */
3855 swizzle[1] = PIPE_SWIZZLE_Y;
3856 swizzle[2] = PIPE_SWIZZLE_Z;
3857 swizzle[3] = PIPE_SWIZZLE_W;
3858 break;
3859 default:
3860 assert(0);
3861 }
3862 } else if (channel && desc->nr_channels == 3) {
3863 assert(desc->swizzle[0] == PIPE_SWIZZLE_X);
3864
3865 if (channel->size == 8) {
3866 if (channel->pure_integer)
3867 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8_INT;
3868 else
3869 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8;
3870 } else if (channel->size == 16) {
3871 if (channel->pure_integer)
3872 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16_INT;
3873 else
3874 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16;
3875 }
3876 }
3877
3878 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
3879 S_008F0C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
3880 S_008F0C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
3881 S_008F0C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
3882 S_008F0C_NUM_FORMAT(num_format) |
3883 S_008F0C_DATA_FORMAT(data_format);
3884 }
3885 return v;
3886 }
3887
3888 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
3889 {
3890 struct si_context *sctx = (struct si_context *)ctx;
3891 struct si_vertex_elements *old = sctx->vertex_elements;
3892 struct si_vertex_elements *v = (struct si_vertex_elements*)state;
3893
3894 sctx->vertex_elements = v;
3895 sctx->vertex_buffers_dirty = true;
3896
3897 if (v &&
3898 (!old ||
3899 old->count != v->count ||
3900 old->uses_instance_divisors != v->uses_instance_divisors ||
3901 v->uses_instance_divisors || /* we don't check which divisors changed */
3902 memcmp(old->fix_fetch, v->fix_fetch, sizeof(v->fix_fetch[0]) * v->count)))
3903 sctx->do_update_shaders = true;
3904
3905 if (v && v->instance_divisor_is_fetched) {
3906 struct pipe_constant_buffer cb;
3907
3908 cb.buffer = NULL;
3909 cb.user_buffer = v->instance_divisors;
3910 cb.buffer_offset = 0;
3911 cb.buffer_size = sizeof(uint32_t) * v->count;
3912 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS, &cb);
3913 }
3914 }
3915
3916 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
3917 {
3918 struct si_context *sctx = (struct si_context *)ctx;
3919
3920 if (sctx->vertex_elements == state)
3921 sctx->vertex_elements = NULL;
3922 FREE(state);
3923 }
3924
3925 static void si_set_vertex_buffers(struct pipe_context *ctx,
3926 unsigned start_slot, unsigned count,
3927 const struct pipe_vertex_buffer *buffers)
3928 {
3929 struct si_context *sctx = (struct si_context *)ctx;
3930 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
3931 int i;
3932
3933 assert(start_slot + count <= ARRAY_SIZE(sctx->vertex_buffer));
3934
3935 if (buffers) {
3936 for (i = 0; i < count; i++) {
3937 const struct pipe_vertex_buffer *src = buffers + i;
3938 struct pipe_vertex_buffer *dsti = dst + i;
3939 struct pipe_resource *buf = src->buffer.resource;
3940
3941 pipe_resource_reference(&dsti->buffer.resource, buf);
3942 dsti->buffer_offset = src->buffer_offset;
3943 dsti->stride = src->stride;
3944 r600_context_add_resource_size(ctx, buf);
3945 if (buf)
3946 r600_resource(buf)->bind_history |= PIPE_BIND_VERTEX_BUFFER;
3947 }
3948 } else {
3949 for (i = 0; i < count; i++) {
3950 pipe_resource_reference(&dst[i].buffer.resource, NULL);
3951 }
3952 }
3953 sctx->vertex_buffers_dirty = true;
3954 }
3955
3956 /*
3957 * Misc
3958 */
3959
3960 static void si_set_tess_state(struct pipe_context *ctx,
3961 const float default_outer_level[4],
3962 const float default_inner_level[2])
3963 {
3964 struct si_context *sctx = (struct si_context *)ctx;
3965 struct pipe_constant_buffer cb;
3966 float array[8];
3967
3968 memcpy(array, default_outer_level, sizeof(float) * 4);
3969 memcpy(array+4, default_inner_level, sizeof(float) * 2);
3970
3971 cb.buffer = NULL;
3972 cb.user_buffer = NULL;
3973 cb.buffer_size = sizeof(array);
3974
3975 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
3976 (void*)array, sizeof(array),
3977 &cb.buffer_offset);
3978
3979 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
3980 pipe_resource_reference(&cb.buffer, NULL);
3981 }
3982
3983 static void si_texture_barrier(struct pipe_context *ctx, unsigned flags)
3984 {
3985 struct si_context *sctx = (struct si_context *)ctx;
3986
3987 /* Multisample surfaces are flushed in si_decompress_textures. */
3988 if (sctx->framebuffer.nr_samples <= 1 &&
3989 sctx->framebuffer.state.nr_cbufs) {
3990 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
3991 SI_CONTEXT_INV_GLOBAL_L2 |
3992 SI_CONTEXT_FLUSH_AND_INV_CB;
3993 }
3994 sctx->framebuffer.do_update_surf_dirtiness = true;
3995 }
3996
3997 /* This only ensures coherency for shader image/buffer stores. */
3998 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
3999 {
4000 struct si_context *sctx = (struct si_context *)ctx;
4001
4002 /* Subsequent commands must wait for all shader invocations to
4003 * complete. */
4004 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
4005 SI_CONTEXT_CS_PARTIAL_FLUSH;
4006
4007 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
4008 sctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 |
4009 SI_CONTEXT_INV_VMEM_L1;
4010
4011 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
4012 PIPE_BARRIER_SHADER_BUFFER |
4013 PIPE_BARRIER_TEXTURE |
4014 PIPE_BARRIER_IMAGE |
4015 PIPE_BARRIER_STREAMOUT_BUFFER |
4016 PIPE_BARRIER_GLOBAL_BUFFER)) {
4017 /* As far as I can tell, L1 contents are written back to L2
4018 * automatically at end of shader, but the contents of other
4019 * L1 caches might still be stale. */
4020 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
4021 }
4022
4023 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
4024 /* Indices are read through TC L2 since VI.
4025 * L1 isn't used.
4026 */
4027 if (sctx->screen->b.chip_class <= CIK)
4028 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4029 }
4030
4031 /* MSAA color, any depth and any stencil are flushed in
4032 * si_decompress_textures when needed.
4033 */
4034 if (flags & PIPE_BARRIER_FRAMEBUFFER &&
4035 sctx->framebuffer.nr_samples <= 1 &&
4036 sctx->framebuffer.state.nr_cbufs) {
4037 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_CB |
4038 SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4039 }
4040
4041 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
4042 if (sctx->screen->b.chip_class <= VI &&
4043 flags & PIPE_BARRIER_INDIRECT_BUFFER)
4044 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4045 }
4046
4047 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
4048 {
4049 struct pipe_blend_state blend;
4050
4051 memset(&blend, 0, sizeof(blend));
4052 blend.independent_blend_enable = true;
4053 blend.rt[0].colormask = 0xf;
4054 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
4055 }
4056
4057 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
4058 bool include_draw_vbo)
4059 {
4060 si_need_cs_space((struct si_context*)ctx);
4061 }
4062
4063 static void si_init_config(struct si_context *sctx);
4064
4065 void si_init_state_functions(struct si_context *sctx)
4066 {
4067 si_init_external_atom(sctx, &sctx->b.render_cond_atom, &sctx->atoms.s.render_cond);
4068 si_init_external_atom(sctx, &sctx->b.streamout.begin_atom, &sctx->atoms.s.streamout_begin);
4069 si_init_external_atom(sctx, &sctx->b.streamout.enable_atom, &sctx->atoms.s.streamout_enable);
4070 si_init_external_atom(sctx, &sctx->b.scissors.atom, &sctx->atoms.s.scissors);
4071 si_init_external_atom(sctx, &sctx->b.viewports.atom, &sctx->atoms.s.viewports);
4072
4073 si_init_atom(sctx, &sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state);
4074 si_init_atom(sctx, &sctx->msaa_sample_locs.atom, &sctx->atoms.s.msaa_sample_locs, si_emit_msaa_sample_locs);
4075 si_init_atom(sctx, &sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state);
4076 si_init_atom(sctx, &sctx->msaa_config, &sctx->atoms.s.msaa_config, si_emit_msaa_config);
4077 si_init_atom(sctx, &sctx->sample_mask.atom, &sctx->atoms.s.sample_mask, si_emit_sample_mask);
4078 si_init_atom(sctx, &sctx->cb_render_state, &sctx->atoms.s.cb_render_state, si_emit_cb_render_state);
4079 si_init_atom(sctx, &sctx->blend_color.atom, &sctx->atoms.s.blend_color, si_emit_blend_color);
4080 si_init_atom(sctx, &sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs);
4081 si_init_atom(sctx, &sctx->clip_state.atom, &sctx->atoms.s.clip_state, si_emit_clip_state);
4082 si_init_atom(sctx, &sctx->stencil_ref.atom, &sctx->atoms.s.stencil_ref, si_emit_stencil_ref);
4083
4084 sctx->b.b.create_blend_state = si_create_blend_state;
4085 sctx->b.b.bind_blend_state = si_bind_blend_state;
4086 sctx->b.b.delete_blend_state = si_delete_blend_state;
4087 sctx->b.b.set_blend_color = si_set_blend_color;
4088
4089 sctx->b.b.create_rasterizer_state = si_create_rs_state;
4090 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
4091 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
4092
4093 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
4094 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
4095 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
4096
4097 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
4098 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
4099 sctx->custom_blend_fmask_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
4100 sctx->custom_blend_eliminate_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
4101 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
4102
4103 sctx->b.b.set_clip_state = si_set_clip_state;
4104 sctx->b.b.set_stencil_ref = si_set_stencil_ref;
4105
4106 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
4107 sctx->b.b.get_sample_position = cayman_get_sample_position;
4108
4109 sctx->b.b.create_sampler_state = si_create_sampler_state;
4110 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
4111
4112 sctx->b.b.create_sampler_view = si_create_sampler_view;
4113 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
4114
4115 sctx->b.b.set_sample_mask = si_set_sample_mask;
4116
4117 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
4118 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
4119 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
4120 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
4121
4122 sctx->b.b.texture_barrier = si_texture_barrier;
4123 sctx->b.b.memory_barrier = si_memory_barrier;
4124 sctx->b.b.set_min_samples = si_set_min_samples;
4125 sctx->b.b.set_tess_state = si_set_tess_state;
4126
4127 sctx->b.b.set_active_query_state = si_set_active_query_state;
4128 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
4129 sctx->b.save_qbo_state = si_save_qbo_state;
4130 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
4131
4132 sctx->b.b.draw_vbo = si_draw_vbo;
4133
4134 si_init_config(sctx);
4135 }
4136
4137 static uint32_t si_get_bo_metadata_word1(struct r600_common_screen *rscreen)
4138 {
4139 return (ATI_VENDOR_ID << 16) | rscreen->info.pci_id;
4140 }
4141
4142 static void si_query_opaque_metadata(struct r600_common_screen *rscreen,
4143 struct r600_texture *rtex,
4144 struct radeon_bo_metadata *md)
4145 {
4146 struct si_screen *sscreen = (struct si_screen*)rscreen;
4147 struct pipe_resource *res = &rtex->resource.b.b;
4148 static const unsigned char swizzle[] = {
4149 PIPE_SWIZZLE_X,
4150 PIPE_SWIZZLE_Y,
4151 PIPE_SWIZZLE_Z,
4152 PIPE_SWIZZLE_W
4153 };
4154 uint32_t desc[8], i;
4155 bool is_array = util_resource_is_array_texture(res);
4156
4157 /* DRM 2.x.x doesn't support this. */
4158 if (rscreen->info.drm_major != 3)
4159 return;
4160
4161 assert(rtex->dcc_separate_buffer == NULL);
4162 assert(rtex->fmask.size == 0);
4163
4164 /* Metadata image format format version 1:
4165 * [0] = 1 (metadata format identifier)
4166 * [1] = (VENDOR_ID << 16) | PCI_ID
4167 * [2:9] = image descriptor for the whole resource
4168 * [2] is always 0, because the base address is cleared
4169 * [9] is the DCC offset bits [39:8] from the beginning of
4170 * the buffer
4171 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
4172 */
4173
4174 md->metadata[0] = 1; /* metadata image format version 1 */
4175
4176 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
4177 md->metadata[1] = si_get_bo_metadata_word1(rscreen);
4178
4179 si_make_texture_descriptor(sscreen, rtex, true,
4180 res->target, res->format,
4181 swizzle, 0, res->last_level, 0,
4182 is_array ? res->array_size - 1 : 0,
4183 res->width0, res->height0, res->depth0,
4184 desc, NULL);
4185
4186 si_set_mutable_tex_desc_fields(sscreen, rtex, &rtex->surface.u.legacy.level[0],
4187 0, 0, rtex->surface.blk_w, false, desc);
4188
4189 /* Clear the base address and set the relative DCC offset. */
4190 desc[0] = 0;
4191 desc[1] &= C_008F14_BASE_ADDRESS_HI;
4192 desc[7] = rtex->dcc_offset >> 8;
4193
4194 /* Dwords [2:9] contain the image descriptor. */
4195 memcpy(&md->metadata[2], desc, sizeof(desc));
4196 md->size_metadata = 10 * 4;
4197
4198 /* Dwords [10:..] contain the mipmap level offsets. */
4199 if (rscreen->chip_class <= VI) {
4200 for (i = 0; i <= res->last_level; i++)
4201 md->metadata[10+i] = rtex->surface.u.legacy.level[i].offset >> 8;
4202
4203 md->size_metadata += (1 + res->last_level) * 4;
4204 }
4205 }
4206
4207 static void si_apply_opaque_metadata(struct r600_common_screen *rscreen,
4208 struct r600_texture *rtex,
4209 struct radeon_bo_metadata *md)
4210 {
4211 uint32_t *desc = &md->metadata[2];
4212
4213 if (rscreen->chip_class < VI)
4214 return;
4215
4216 /* Return if DCC is enabled. The texture should be set up with it
4217 * already.
4218 */
4219 if (md->size_metadata >= 11 * 4 &&
4220 md->metadata[0] != 0 &&
4221 md->metadata[1] == si_get_bo_metadata_word1(rscreen) &&
4222 G_008F28_COMPRESSION_EN(desc[6])) {
4223 assert(rtex->dcc_offset == ((uint64_t)desc[7] << 8));
4224 return;
4225 }
4226
4227 /* Disable DCC. These are always set by texture_from_handle and must
4228 * be cleared here.
4229 */
4230 rtex->dcc_offset = 0;
4231 }
4232
4233 void si_init_screen_state_functions(struct si_screen *sscreen)
4234 {
4235 sscreen->b.b.is_format_supported = si_is_format_supported;
4236 sscreen->b.query_opaque_metadata = si_query_opaque_metadata;
4237 sscreen->b.apply_opaque_metadata = si_apply_opaque_metadata;
4238 }
4239
4240 static void
4241 si_write_harvested_raster_configs(struct si_context *sctx,
4242 struct si_pm4_state *pm4,
4243 unsigned raster_config,
4244 unsigned raster_config_1)
4245 {
4246 unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1);
4247 unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1);
4248 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
4249 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
4250 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
4251 unsigned rb_per_se = num_rb / num_se;
4252 unsigned se_mask[4];
4253 unsigned se;
4254
4255 se_mask[0] = ((1 << rb_per_se) - 1);
4256 se_mask[1] = (se_mask[0] << rb_per_se);
4257 se_mask[2] = (se_mask[1] << rb_per_se);
4258 se_mask[3] = (se_mask[2] << rb_per_se);
4259
4260 se_mask[0] &= rb_mask;
4261 se_mask[1] &= rb_mask;
4262 se_mask[2] &= rb_mask;
4263 se_mask[3] &= rb_mask;
4264
4265 assert(num_se == 1 || num_se == 2 || num_se == 4);
4266 assert(sh_per_se == 1 || sh_per_se == 2);
4267 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
4268
4269 /* XXX: I can't figure out what the *_XSEL and *_YSEL
4270 * fields are for, so I'm leaving them as their default
4271 * values. */
4272
4273 for (se = 0; se < num_se; se++) {
4274 unsigned raster_config_se = raster_config;
4275 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
4276 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
4277 int idx = (se / 2) * 2;
4278
4279 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
4280 raster_config_se &= C_028350_SE_MAP;
4281
4282 if (!se_mask[idx]) {
4283 raster_config_se |=
4284 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
4285 } else {
4286 raster_config_se |=
4287 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
4288 }
4289 }
4290
4291 pkr0_mask &= rb_mask;
4292 pkr1_mask &= rb_mask;
4293 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
4294 raster_config_se &= C_028350_PKR_MAP;
4295
4296 if (!pkr0_mask) {
4297 raster_config_se |=
4298 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
4299 } else {
4300 raster_config_se |=
4301 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
4302 }
4303 }
4304
4305 if (rb_per_se >= 2) {
4306 unsigned rb0_mask = 1 << (se * rb_per_se);
4307 unsigned rb1_mask = rb0_mask << 1;
4308
4309 rb0_mask &= rb_mask;
4310 rb1_mask &= rb_mask;
4311 if (!rb0_mask || !rb1_mask) {
4312 raster_config_se &= C_028350_RB_MAP_PKR0;
4313
4314 if (!rb0_mask) {
4315 raster_config_se |=
4316 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
4317 } else {
4318 raster_config_se |=
4319 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
4320 }
4321 }
4322
4323 if (rb_per_se > 2) {
4324 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
4325 rb1_mask = rb0_mask << 1;
4326 rb0_mask &= rb_mask;
4327 rb1_mask &= rb_mask;
4328 if (!rb0_mask || !rb1_mask) {
4329 raster_config_se &= C_028350_RB_MAP_PKR1;
4330
4331 if (!rb0_mask) {
4332 raster_config_se |=
4333 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
4334 } else {
4335 raster_config_se |=
4336 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
4337 }
4338 }
4339 }
4340 }
4341
4342 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
4343 if (sctx->b.chip_class < CIK)
4344 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
4345 SE_INDEX(se) | SH_BROADCAST_WRITES |
4346 INSTANCE_BROADCAST_WRITES);
4347 else
4348 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
4349 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
4350 S_030800_INSTANCE_BROADCAST_WRITES(1));
4351 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
4352 }
4353
4354 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
4355 if (sctx->b.chip_class < CIK)
4356 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
4357 SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
4358 INSTANCE_BROADCAST_WRITES);
4359 else {
4360 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
4361 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
4362 S_030800_INSTANCE_BROADCAST_WRITES(1));
4363
4364 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
4365 (!se_mask[2] && !se_mask[3]))) {
4366 raster_config_1 &= C_028354_SE_PAIR_MAP;
4367
4368 if (!se_mask[0] && !se_mask[1]) {
4369 raster_config_1 |=
4370 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
4371 } else {
4372 raster_config_1 |=
4373 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
4374 }
4375 }
4376
4377 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
4378 }
4379 }
4380
4381 static void si_init_config(struct si_context *sctx)
4382 {
4383 struct si_screen *sscreen = sctx->screen;
4384 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
4385 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
4386 unsigned raster_config, raster_config_1;
4387 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
4388 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
4389
4390 if (!pm4)
4391 return;
4392
4393 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
4394 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
4395 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
4396 si_pm4_cmd_end(pm4, false);
4397
4398 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
4399 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
4400
4401 /* FIXME calculate these values somehow ??? */
4402 if (sctx->b.chip_class <= VI) {
4403 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
4404 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
4405 }
4406 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
4407
4408 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
4409 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
4410
4411 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
4412 si_pm4_set_reg(pm4, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
4413 if (sctx->b.chip_class >= GFX9)
4414 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0);
4415 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
4416 if (sctx->b.chip_class < CIK)
4417 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
4418 S_008A14_CLIP_VTX_REORDER_ENA(1));
4419
4420 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
4421 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
4422
4423 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
4424
4425 switch (sctx->screen->b.family) {
4426 case CHIP_TAHITI:
4427 case CHIP_PITCAIRN:
4428 raster_config = 0x2a00126a;
4429 raster_config_1 = 0x00000000;
4430 break;
4431 case CHIP_VERDE:
4432 raster_config = 0x0000124a;
4433 raster_config_1 = 0x00000000;
4434 break;
4435 case CHIP_OLAND:
4436 raster_config = 0x00000082;
4437 raster_config_1 = 0x00000000;
4438 break;
4439 case CHIP_HAINAN:
4440 raster_config = 0x00000000;
4441 raster_config_1 = 0x00000000;
4442 break;
4443 case CHIP_BONAIRE:
4444 raster_config = 0x16000012;
4445 raster_config_1 = 0x00000000;
4446 break;
4447 case CHIP_HAWAII:
4448 raster_config = 0x3a00161a;
4449 raster_config_1 = 0x0000002e;
4450 break;
4451 case CHIP_FIJI:
4452 if (sscreen->b.info.cik_macrotile_mode_array[0] == 0x000000e8) {
4453 /* old kernels with old tiling config */
4454 raster_config = 0x16000012;
4455 raster_config_1 = 0x0000002a;
4456 } else {
4457 raster_config = 0x3a00161a;
4458 raster_config_1 = 0x0000002e;
4459 }
4460 break;
4461 case CHIP_POLARIS10:
4462 raster_config = 0x16000012;
4463 raster_config_1 = 0x0000002a;
4464 break;
4465 case CHIP_POLARIS11:
4466 case CHIP_POLARIS12:
4467 raster_config = 0x16000012;
4468 raster_config_1 = 0x00000000;
4469 break;
4470 case CHIP_TONGA:
4471 raster_config = 0x16000012;
4472 raster_config_1 = 0x0000002a;
4473 break;
4474 case CHIP_ICELAND:
4475 if (num_rb == 1)
4476 raster_config = 0x00000000;
4477 else
4478 raster_config = 0x00000002;
4479 raster_config_1 = 0x00000000;
4480 break;
4481 case CHIP_CARRIZO:
4482 raster_config = 0x00000002;
4483 raster_config_1 = 0x00000000;
4484 break;
4485 case CHIP_KAVERI:
4486 /* KV should be 0x00000002, but that causes problems with radeon */
4487 raster_config = 0x00000000; /* 0x00000002 */
4488 raster_config_1 = 0x00000000;
4489 break;
4490 case CHIP_KABINI:
4491 case CHIP_MULLINS:
4492 case CHIP_STONEY:
4493 raster_config = 0x00000000;
4494 raster_config_1 = 0x00000000;
4495 break;
4496 default:
4497 if (sctx->b.chip_class <= VI) {
4498 fprintf(stderr,
4499 "radeonsi: Unknown GPU, using 0 for raster_config\n");
4500 raster_config = 0x00000000;
4501 raster_config_1 = 0x00000000;
4502 }
4503 break;
4504 }
4505
4506 if (sctx->b.chip_class <= VI) {
4507 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
4508 /* Always use the default config when all backends are enabled
4509 * (or when we failed to determine the enabled backends).
4510 */
4511 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
4512 raster_config);
4513 if (sctx->b.chip_class >= CIK)
4514 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
4515 raster_config_1);
4516 } else {
4517 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
4518 }
4519 }
4520
4521 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
4522 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
4523 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
4524 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
4525 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
4526 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
4527 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
4528
4529 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
4530 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
4531 S_028230_ER_TRI(0xA) |
4532 S_028230_ER_POINT(0xA) |
4533 S_028230_ER_RECT(0xA) |
4534 /* Required by DX10_DIAMOND_TEST_ENA: */
4535 S_028230_ER_LINE_LR(0x1A) |
4536 S_028230_ER_LINE_RL(0x26) |
4537 S_028230_ER_LINE_TB(0xA) |
4538 S_028230_ER_LINE_BT(0xA));
4539 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
4540 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
4541 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
4542 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
4543 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
4544 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
4545 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 0);
4546
4547 if (sctx->b.chip_class >= GFX9) {
4548 si_pm4_set_reg(pm4, R_030920_VGT_MAX_VTX_INDX, ~0);
4549 si_pm4_set_reg(pm4, R_030924_VGT_MIN_VTX_INDX, 0);
4550 si_pm4_set_reg(pm4, R_030928_VGT_INDX_OFFSET, 0);
4551 } else {
4552 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
4553 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
4554 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
4555 }
4556
4557 if (sctx->b.chip_class >= CIK) {
4558 if (sctx->b.chip_class >= GFX9) {
4559 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, S_00B41C_CU_EN(0xffff));
4560 } else {
4561 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff));
4562 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
4563 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xffff));
4564
4565 /* If this is 0, Bonaire can hang even if GS isn't being used.
4566 * Other chips are unaffected. These are suboptimal values,
4567 * but we don't use on-chip GS.
4568 */
4569 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
4570 S_028A44_ES_VERTS_PER_SUBGRP(64) |
4571 S_028A44_GS_PRIMS_PER_SUBGRP(4));
4572 }
4573 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
4574
4575 if (sscreen->b.info.num_good_compute_units /
4576 (sscreen->b.info.max_se * sscreen->b.info.max_sh_per_se) <= 4) {
4577 /* Too few available compute units per SH. Disallowing
4578 * VS to run on CU0 could hurt us more than late VS
4579 * allocation would help.
4580 *
4581 * LATE_ALLOC_VS = 2 is the highest safe number.
4582 */
4583 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
4584 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
4585 } else {
4586 /* Set LATE_ALLOC_VS == 31. It should be less than
4587 * the number of scratch waves. Limitations:
4588 * - VS can't execute on CU0.
4589 * - If HS writes outputs to LDS, LS can't execute on CU0.
4590 */
4591 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xfffe));
4592 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
4593 }
4594
4595 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
4596 }
4597
4598 if (sctx->b.chip_class >= VI) {
4599 unsigned vgt_tess_distribution;
4600
4601 si_pm4_set_reg(pm4, R_028424_CB_DCC_CONTROL,
4602 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
4603 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
4604 if (sctx->b.family < CHIP_POLARIS10)
4605 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
4606 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
4607
4608 vgt_tess_distribution =
4609 S_028B50_ACCUM_ISOLINE(32) |
4610 S_028B50_ACCUM_TRI(11) |
4611 S_028B50_ACCUM_QUAD(11) |
4612 S_028B50_DONUT_SPLIT(16);
4613
4614 /* Testing with Unigine Heaven extreme tesselation yielded best results
4615 * with TRAP_SPLIT = 3.
4616 */
4617 if (sctx->b.family == CHIP_FIJI ||
4618 sctx->b.family >= CHIP_POLARIS10)
4619 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
4620
4621 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution);
4622 } else {
4623 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
4624 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
4625 }
4626
4627 if (sctx->screen->b.has_rbplus)
4628 si_pm4_set_reg(pm4, R_028C40_PA_SC_SHADER_CONTROL, 0);
4629
4630 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
4631 if (sctx->b.chip_class >= CIK)
4632 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, border_color_va >> 40);
4633 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
4634 RADEON_PRIO_BORDER_COLORS);
4635
4636 if (sctx->b.chip_class >= GFX9) {
4637 unsigned num_se = sscreen->b.info.max_se;
4638 unsigned pc_lines = 0;
4639
4640 switch (sctx->b.family) {
4641 case CHIP_VEGA10:
4642 pc_lines = 4096;
4643 break;
4644 case CHIP_RAVEN:
4645 pc_lines = 1024;
4646 break;
4647 default:
4648 assert(0);
4649 }
4650
4651 si_pm4_set_reg(pm4, R_028060_DB_DFSM_CONTROL,
4652 S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF));
4653 si_pm4_set_reg(pm4, R_028064_DB_RENDER_FILTER, 0);
4654 /* TODO: We can use this to disable RBs for rendering to GART: */
4655 si_pm4_set_reg(pm4, R_02835C_PA_SC_TILE_STEERING_OVERRIDE, 0);
4656 si_pm4_set_reg(pm4, R_02883C_PA_SU_OVER_RASTERIZATION_CNTL, 0);
4657 /* TODO: Enable the binner: */
4658 si_pm4_set_reg(pm4, R_028C44_PA_SC_BINNER_CNTL_0,
4659 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
4660 S_028C44_DISABLE_START_OF_PRIM(1));
4661 si_pm4_set_reg(pm4, R_028C48_PA_SC_BINNER_CNTL_1,
4662 S_028C48_MAX_ALLOC_COUNT(MIN2(128, pc_lines / (4 * num_se))) |
4663 S_028C48_MAX_PRIM_PER_BATCH(1023));
4664 si_pm4_set_reg(pm4, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
4665 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
4666 si_pm4_set_reg(pm4, R_030968_VGT_INSTANCE_BASE_ID, 0);
4667 }
4668
4669 si_pm4_upload_indirect_buffer(sctx, pm4);
4670 sctx->init_config = pm4;
4671 }