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radeonsi: skip unnecessary si_update_shaders calls
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "si_shader.h"
29 #include "sid.h"
30 #include "radeon/r600_cs.h"
31
32 #include "util/u_dual_blend.h"
33 #include "util/u_format.h"
34 #include "util/u_format_s3tc.h"
35 #include "util/u_memory.h"
36 #include "util/u_pstipple.h"
37 #include "util/u_resource.h"
38
39 /* Initialize an external atom (owned by ../radeon). */
40 static void
41 si_init_external_atom(struct si_context *sctx, struct r600_atom *atom,
42 struct r600_atom **list_elem)
43 {
44 atom->id = list_elem - sctx->atoms.array + 1;
45 *list_elem = atom;
46 }
47
48 /* Initialize an atom owned by radeonsi. */
49 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
50 struct r600_atom **list_elem,
51 void (*emit_func)(struct si_context *ctx, struct r600_atom *state))
52 {
53 atom->emit = (void*)emit_func;
54 atom->id = list_elem - sctx->atoms.array + 1; /* index+1 in the atom array */
55 *list_elem = atom;
56 }
57
58 static unsigned si_map_swizzle(unsigned swizzle)
59 {
60 switch (swizzle) {
61 case PIPE_SWIZZLE_Y:
62 return V_008F0C_SQ_SEL_Y;
63 case PIPE_SWIZZLE_Z:
64 return V_008F0C_SQ_SEL_Z;
65 case PIPE_SWIZZLE_W:
66 return V_008F0C_SQ_SEL_W;
67 case PIPE_SWIZZLE_0:
68 return V_008F0C_SQ_SEL_0;
69 case PIPE_SWIZZLE_1:
70 return V_008F0C_SQ_SEL_1;
71 default: /* PIPE_SWIZZLE_X */
72 return V_008F0C_SQ_SEL_X;
73 }
74 }
75
76 static uint32_t S_FIXED(float value, uint32_t frac_bits)
77 {
78 return value * (1 << frac_bits);
79 }
80
81 /* 12.4 fixed-point */
82 static unsigned si_pack_float_12p4(float x)
83 {
84 return x <= 0 ? 0 :
85 x >= 4096 ? 0xffff : x * 16;
86 }
87
88 /*
89 * Inferred framebuffer and blender state.
90 *
91 * One of the reasons CB_TARGET_MASK must be derived from the framebuffer state
92 * is that:
93 * - The blend state mask is 0xf most of the time.
94 * - The COLOR1 format isn't INVALID because of possible dual-source blending,
95 * so COLOR1 is enabled pretty much all the time.
96 * So CB_TARGET_MASK is the only register that can disable COLOR1.
97 *
98 * Another reason is to avoid a hang with dual source blending.
99 */
100 static void si_emit_cb_render_state(struct si_context *sctx, struct r600_atom *atom)
101 {
102 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
103 struct si_state_blend *blend = sctx->queued.named.blend;
104 uint32_t cb_target_mask = 0, i;
105
106 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++)
107 if (sctx->framebuffer.state.cbufs[i])
108 cb_target_mask |= 0xf << (4*i);
109
110 if (blend)
111 cb_target_mask &= blend->cb_target_mask;
112
113 /* Avoid a hang that happens when dual source blending is enabled
114 * but there is not enough color outputs. This is undefined behavior,
115 * so disable color writes completely.
116 *
117 * Reproducible with Unigine Heaven 4.0 and drirc missing.
118 */
119 if (blend && blend->dual_src_blend &&
120 sctx->ps_shader.cso &&
121 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
122 cb_target_mask = 0;
123
124 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, cb_target_mask);
125
126 /* STONEY-specific register settings. */
127 if (sctx->b.family == CHIP_STONEY) {
128 unsigned spi_shader_col_format =
129 sctx->ps_shader.cso ?
130 sctx->ps_shader.current->key.ps.epilog.spi_shader_col_format : 0;
131 unsigned sx_ps_downconvert = 0;
132 unsigned sx_blend_opt_epsilon = 0;
133 unsigned sx_blend_opt_control = 0;
134
135 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
136 struct r600_surface *surf =
137 (struct r600_surface*)sctx->framebuffer.state.cbufs[i];
138 unsigned format, swap, spi_format, colormask;
139 bool has_alpha, has_rgb;
140
141 if (!surf)
142 continue;
143
144 format = G_028C70_FORMAT(surf->cb_color_info);
145 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
146 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
147 colormask = (cb_target_mask >> (i * 4)) & 0xf;
148
149 /* Set if RGB and A are present. */
150 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
151
152 if (format == V_028C70_COLOR_8 ||
153 format == V_028C70_COLOR_16 ||
154 format == V_028C70_COLOR_32)
155 has_rgb = !has_alpha;
156 else
157 has_rgb = true;
158
159 /* Check the colormask and export format. */
160 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
161 has_rgb = false;
162 if (!(colormask & PIPE_MASK_A))
163 has_alpha = false;
164
165 if (spi_format == V_028714_SPI_SHADER_ZERO) {
166 has_rgb = false;
167 has_alpha = false;
168 }
169
170 /* Disable value checking for disabled channels. */
171 if (!has_rgb)
172 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
173 if (!has_alpha)
174 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
175
176 /* Enable down-conversion for 32bpp and smaller formats. */
177 switch (format) {
178 case V_028C70_COLOR_8:
179 case V_028C70_COLOR_8_8:
180 case V_028C70_COLOR_8_8_8_8:
181 /* For 1 and 2-channel formats, use the superset thereof. */
182 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
183 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
184 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
185 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
186 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
187 }
188 break;
189
190 case V_028C70_COLOR_5_6_5:
191 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
192 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
193 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
194 }
195 break;
196
197 case V_028C70_COLOR_1_5_5_5:
198 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
199 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
200 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
201 }
202 break;
203
204 case V_028C70_COLOR_4_4_4_4:
205 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
206 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
207 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
208 }
209 break;
210
211 case V_028C70_COLOR_32:
212 if (swap == V_0280A0_SWAP_STD &&
213 spi_format == V_028714_SPI_SHADER_32_R)
214 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
215 else if (swap == V_0280A0_SWAP_ALT_REV &&
216 spi_format == V_028714_SPI_SHADER_32_AR)
217 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
218 break;
219
220 case V_028C70_COLOR_16:
221 case V_028C70_COLOR_16_16:
222 /* For 1-channel formats, use the superset thereof. */
223 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
224 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
225 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
226 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
227 if (swap == V_0280A0_SWAP_STD ||
228 swap == V_0280A0_SWAP_STD_REV)
229 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
230 else
231 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
232 }
233 break;
234
235 case V_028C70_COLOR_10_11_11:
236 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
237 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
238 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
239 }
240 break;
241
242 case V_028C70_COLOR_2_10_10_10:
243 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
244 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
245 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
246 }
247 break;
248 }
249 }
250
251 if (sctx->screen->b.debug_flags & DBG_NO_RB_PLUS) {
252 sx_ps_downconvert = 0;
253 sx_blend_opt_epsilon = 0;
254 sx_blend_opt_control = 0;
255 }
256
257 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
258 radeon_emit(cs, sx_ps_downconvert); /* R_028754_SX_PS_DOWNCONVERT */
259 radeon_emit(cs, sx_blend_opt_epsilon); /* R_028758_SX_BLEND_OPT_EPSILON */
260 radeon_emit(cs, sx_blend_opt_control); /* R_02875C_SX_BLEND_OPT_CONTROL */
261 }
262 }
263
264 /*
265 * Blender functions
266 */
267
268 static uint32_t si_translate_blend_function(int blend_func)
269 {
270 switch (blend_func) {
271 case PIPE_BLEND_ADD:
272 return V_028780_COMB_DST_PLUS_SRC;
273 case PIPE_BLEND_SUBTRACT:
274 return V_028780_COMB_SRC_MINUS_DST;
275 case PIPE_BLEND_REVERSE_SUBTRACT:
276 return V_028780_COMB_DST_MINUS_SRC;
277 case PIPE_BLEND_MIN:
278 return V_028780_COMB_MIN_DST_SRC;
279 case PIPE_BLEND_MAX:
280 return V_028780_COMB_MAX_DST_SRC;
281 default:
282 R600_ERR("Unknown blend function %d\n", blend_func);
283 assert(0);
284 break;
285 }
286 return 0;
287 }
288
289 static uint32_t si_translate_blend_factor(int blend_fact)
290 {
291 switch (blend_fact) {
292 case PIPE_BLENDFACTOR_ONE:
293 return V_028780_BLEND_ONE;
294 case PIPE_BLENDFACTOR_SRC_COLOR:
295 return V_028780_BLEND_SRC_COLOR;
296 case PIPE_BLENDFACTOR_SRC_ALPHA:
297 return V_028780_BLEND_SRC_ALPHA;
298 case PIPE_BLENDFACTOR_DST_ALPHA:
299 return V_028780_BLEND_DST_ALPHA;
300 case PIPE_BLENDFACTOR_DST_COLOR:
301 return V_028780_BLEND_DST_COLOR;
302 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
303 return V_028780_BLEND_SRC_ALPHA_SATURATE;
304 case PIPE_BLENDFACTOR_CONST_COLOR:
305 return V_028780_BLEND_CONSTANT_COLOR;
306 case PIPE_BLENDFACTOR_CONST_ALPHA:
307 return V_028780_BLEND_CONSTANT_ALPHA;
308 case PIPE_BLENDFACTOR_ZERO:
309 return V_028780_BLEND_ZERO;
310 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
311 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
312 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
313 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
314 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
315 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
316 case PIPE_BLENDFACTOR_INV_DST_COLOR:
317 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
318 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
319 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
320 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
321 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
322 case PIPE_BLENDFACTOR_SRC1_COLOR:
323 return V_028780_BLEND_SRC1_COLOR;
324 case PIPE_BLENDFACTOR_SRC1_ALPHA:
325 return V_028780_BLEND_SRC1_ALPHA;
326 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
327 return V_028780_BLEND_INV_SRC1_COLOR;
328 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
329 return V_028780_BLEND_INV_SRC1_ALPHA;
330 default:
331 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
332 assert(0);
333 break;
334 }
335 return 0;
336 }
337
338 static uint32_t si_translate_blend_opt_function(int blend_func)
339 {
340 switch (blend_func) {
341 case PIPE_BLEND_ADD:
342 return V_028760_OPT_COMB_ADD;
343 case PIPE_BLEND_SUBTRACT:
344 return V_028760_OPT_COMB_SUBTRACT;
345 case PIPE_BLEND_REVERSE_SUBTRACT:
346 return V_028760_OPT_COMB_REVSUBTRACT;
347 case PIPE_BLEND_MIN:
348 return V_028760_OPT_COMB_MIN;
349 case PIPE_BLEND_MAX:
350 return V_028760_OPT_COMB_MAX;
351 default:
352 return V_028760_OPT_COMB_BLEND_DISABLED;
353 }
354 }
355
356 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
357 {
358 switch (blend_fact) {
359 case PIPE_BLENDFACTOR_ZERO:
360 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
361 case PIPE_BLENDFACTOR_ONE:
362 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
363 case PIPE_BLENDFACTOR_SRC_COLOR:
364 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
365 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
366 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
367 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
368 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
369 case PIPE_BLENDFACTOR_SRC_ALPHA:
370 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
371 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
372 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
373 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
374 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
375 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
376 default:
377 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
378 }
379 }
380
381 /**
382 * Get rid of DST in the blend factors by commuting the operands:
383 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
384 */
385 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
386 unsigned *dst_factor, unsigned expected_dst,
387 unsigned replacement_src)
388 {
389 if (*src_factor == expected_dst &&
390 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
391 *src_factor = PIPE_BLENDFACTOR_ZERO;
392 *dst_factor = replacement_src;
393
394 /* Commuting the operands requires reversing subtractions. */
395 if (*func == PIPE_BLEND_SUBTRACT)
396 *func = PIPE_BLEND_REVERSE_SUBTRACT;
397 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
398 *func = PIPE_BLEND_SUBTRACT;
399 }
400 }
401
402 static bool si_blend_factor_uses_dst(unsigned factor)
403 {
404 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
405 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
406 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
407 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
408 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
409 }
410
411 static void *si_create_blend_state_mode(struct pipe_context *ctx,
412 const struct pipe_blend_state *state,
413 unsigned mode)
414 {
415 struct si_context *sctx = (struct si_context*)ctx;
416 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
417 struct si_pm4_state *pm4 = &blend->pm4;
418 uint32_t sx_mrt_blend_opt[8] = {0};
419 uint32_t color_control = 0;
420
421 if (!blend)
422 return NULL;
423
424 blend->alpha_to_coverage = state->alpha_to_coverage;
425 blend->alpha_to_one = state->alpha_to_one;
426 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
427
428 if (state->logicop_enable) {
429 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
430 } else {
431 color_control |= S_028808_ROP3(0xcc);
432 }
433
434 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
435 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
436 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
437 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
438 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
439 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
440
441 if (state->alpha_to_coverage)
442 blend->need_src_alpha_4bit |= 0xf;
443
444 blend->cb_target_mask = 0;
445 for (int i = 0; i < 8; i++) {
446 /* state->rt entries > 0 only written if independent blending */
447 const int j = state->independent_blend_enable ? i : 0;
448
449 unsigned eqRGB = state->rt[j].rgb_func;
450 unsigned srcRGB = state->rt[j].rgb_src_factor;
451 unsigned dstRGB = state->rt[j].rgb_dst_factor;
452 unsigned eqA = state->rt[j].alpha_func;
453 unsigned srcA = state->rt[j].alpha_src_factor;
454 unsigned dstA = state->rt[j].alpha_dst_factor;
455
456 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
457 unsigned blend_cntl = 0;
458
459 sx_mrt_blend_opt[i] =
460 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
461 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
462
463 if (!state->rt[j].colormask)
464 continue;
465
466 /* cb_render_state will disable unused ones */
467 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
468
469 if (!state->rt[j].blend_enable) {
470 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
471 continue;
472 }
473
474 /* Blending optimizations for Stoney.
475 * These transformations don't change the behavior.
476 *
477 * First, get rid of DST in the blend factors:
478 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
479 */
480 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
481 PIPE_BLENDFACTOR_DST_COLOR,
482 PIPE_BLENDFACTOR_SRC_COLOR);
483 si_blend_remove_dst(&eqA, &srcA, &dstA,
484 PIPE_BLENDFACTOR_DST_COLOR,
485 PIPE_BLENDFACTOR_SRC_COLOR);
486 si_blend_remove_dst(&eqA, &srcA, &dstA,
487 PIPE_BLENDFACTOR_DST_ALPHA,
488 PIPE_BLENDFACTOR_SRC_ALPHA);
489
490 /* Look up the ideal settings from tables. */
491 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
492 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
493 srcA_opt = si_translate_blend_opt_factor(srcA, true);
494 dstA_opt = si_translate_blend_opt_factor(dstA, true);
495
496 /* Handle interdependencies. */
497 if (si_blend_factor_uses_dst(srcRGB))
498 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
499 if (si_blend_factor_uses_dst(srcA))
500 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
501
502 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
503 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
504 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
505 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
506 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
507
508 /* Set the final value. */
509 sx_mrt_blend_opt[i] =
510 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
511 S_028760_COLOR_DST_OPT(dstRGB_opt) |
512 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
513 S_028760_ALPHA_SRC_OPT(srcA_opt) |
514 S_028760_ALPHA_DST_OPT(dstA_opt) |
515 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
516
517 /* Set blend state. */
518 blend_cntl |= S_028780_ENABLE(1);
519 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
520 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
521 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
522
523 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
524 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
525 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
526 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
527 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
528 }
529 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
530
531 blend->blend_enable_4bit |= 0xfu << (i * 4);
532
533 /* This is only important for formats without alpha. */
534 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
535 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
536 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
537 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
538 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
539 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
540 blend->need_src_alpha_4bit |= 0xfu << (i * 4);
541 }
542
543 if (blend->cb_target_mask) {
544 color_control |= S_028808_MODE(mode);
545 } else {
546 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
547 }
548
549 if (sctx->b.family == CHIP_STONEY) {
550 for (int i = 0; i < 8; i++)
551 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
552 sx_mrt_blend_opt[i]);
553
554 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
555 if (blend->dual_src_blend || state->logicop_enable ||
556 mode == V_028808_CB_RESOLVE)
557 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
558 }
559
560 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
561 return blend;
562 }
563
564 static void *si_create_blend_state(struct pipe_context *ctx,
565 const struct pipe_blend_state *state)
566 {
567 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
568 }
569
570 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
571 {
572 struct si_context *sctx = (struct si_context *)ctx;
573 si_pm4_bind_state(sctx, blend, (struct si_state_blend *)state);
574 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
575 sctx->do_update_shaders = true;
576 }
577
578 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
579 {
580 struct si_context *sctx = (struct si_context *)ctx;
581 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
582 }
583
584 static void si_set_blend_color(struct pipe_context *ctx,
585 const struct pipe_blend_color *state)
586 {
587 struct si_context *sctx = (struct si_context *)ctx;
588
589 if (memcmp(&sctx->blend_color.state, state, sizeof(*state)) == 0)
590 return;
591
592 sctx->blend_color.state = *state;
593 si_mark_atom_dirty(sctx, &sctx->blend_color.atom);
594 }
595
596 static void si_emit_blend_color(struct si_context *sctx, struct r600_atom *atom)
597 {
598 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
599
600 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
601 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
602 }
603
604 /*
605 * Clipping
606 */
607
608 static void si_set_clip_state(struct pipe_context *ctx,
609 const struct pipe_clip_state *state)
610 {
611 struct si_context *sctx = (struct si_context *)ctx;
612 struct pipe_constant_buffer cb;
613
614 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
615 return;
616
617 sctx->clip_state.state = *state;
618 si_mark_atom_dirty(sctx, &sctx->clip_state.atom);
619
620 cb.buffer = NULL;
621 cb.user_buffer = state->ucp;
622 cb.buffer_offset = 0;
623 cb.buffer_size = 4*4*8;
624 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
625 pipe_resource_reference(&cb.buffer, NULL);
626 }
627
628 static void si_emit_clip_state(struct si_context *sctx, struct r600_atom *atom)
629 {
630 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
631
632 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
633 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
634 }
635
636 #define SIX_BITS 0x3F
637
638 static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom)
639 {
640 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
641 struct tgsi_shader_info *info = si_get_vs_info(sctx);
642 unsigned window_space =
643 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
644 unsigned clipdist_mask =
645 info->writes_clipvertex ? SIX_BITS : info->clipdist_writemask;
646
647 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
648 S_02881C_USE_VTX_POINT_SIZE(info->writes_psize) |
649 S_02881C_USE_VTX_EDGE_FLAG(info->writes_edgeflag) |
650 S_02881C_USE_VTX_RENDER_TARGET_INDX(info->writes_layer) |
651 S_02881C_USE_VTX_VIEWPORT_INDX(info->writes_viewport_index) |
652 S_02881C_VS_OUT_CCDIST0_VEC_ENA((clipdist_mask & 0x0F) != 0) |
653 S_02881C_VS_OUT_CCDIST1_VEC_ENA((clipdist_mask & 0xF0) != 0) |
654 S_02881C_VS_OUT_MISC_VEC_ENA(info->writes_psize ||
655 info->writes_edgeflag ||
656 info->writes_layer ||
657 info->writes_viewport_index) |
658 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(1) |
659 (sctx->queued.named.rasterizer->clip_plane_enable &
660 clipdist_mask));
661 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
662 sctx->queued.named.rasterizer->pa_cl_clip_cntl |
663 (clipdist_mask ? 0 :
664 sctx->queued.named.rasterizer->clip_plane_enable & SIX_BITS) |
665 S_028810_CLIP_DISABLE(window_space));
666
667 /* reuse needs to be set off if we write oViewport */
668 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF,
669 S_028AB4_REUSE_OFF(info->writes_viewport_index));
670 }
671
672 /*
673 * inferred state between framebuffer and rasterizer
674 */
675 static void si_update_poly_offset_state(struct si_context *sctx)
676 {
677 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
678
679 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf)
680 return;
681
682 switch (sctx->framebuffer.state.zsbuf->texture->format) {
683 case PIPE_FORMAT_Z16_UNORM:
684 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
685 break;
686 default: /* 24-bit */
687 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
688 break;
689 case PIPE_FORMAT_Z32_FLOAT:
690 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
691 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
692 break;
693 }
694 }
695
696 /*
697 * Rasterizer
698 */
699
700 static uint32_t si_translate_fill(uint32_t func)
701 {
702 switch(func) {
703 case PIPE_POLYGON_MODE_FILL:
704 return V_028814_X_DRAW_TRIANGLES;
705 case PIPE_POLYGON_MODE_LINE:
706 return V_028814_X_DRAW_LINES;
707 case PIPE_POLYGON_MODE_POINT:
708 return V_028814_X_DRAW_POINTS;
709 default:
710 assert(0);
711 return V_028814_X_DRAW_POINTS;
712 }
713 }
714
715 static void *si_create_rs_state(struct pipe_context *ctx,
716 const struct pipe_rasterizer_state *state)
717 {
718 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
719 struct si_pm4_state *pm4 = &rs->pm4;
720 unsigned tmp, i;
721 float psize_min, psize_max;
722
723 if (!rs) {
724 return NULL;
725 }
726
727 rs->scissor_enable = state->scissor;
728 rs->two_side = state->light_twoside;
729 rs->multisample_enable = state->multisample;
730 rs->force_persample_interp = state->force_persample_interp;
731 rs->clip_plane_enable = state->clip_plane_enable;
732 rs->line_stipple_enable = state->line_stipple_enable;
733 rs->poly_stipple_enable = state->poly_stipple_enable;
734 rs->line_smooth = state->line_smooth;
735 rs->poly_smooth = state->poly_smooth;
736 rs->uses_poly_offset = state->offset_point || state->offset_line ||
737 state->offset_tri;
738 rs->clamp_fragment_color = state->clamp_fragment_color;
739 rs->flatshade = state->flatshade;
740 rs->sprite_coord_enable = state->sprite_coord_enable;
741 rs->rasterizer_discard = state->rasterizer_discard;
742 rs->pa_sc_line_stipple = state->line_stipple_enable ?
743 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
744 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
745 rs->pa_cl_clip_cntl =
746 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
747 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
748 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
749 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
750 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
751
752 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
753 S_0286D4_FLAT_SHADE_ENA(1) |
754 S_0286D4_PNT_SPRITE_ENA(1) |
755 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
756 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
757 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
758 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
759 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
760
761 /* point size 12.4 fixed point */
762 tmp = (unsigned)(state->point_size * 8.0);
763 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
764
765 if (state->point_size_per_vertex) {
766 psize_min = util_get_min_point_size(state);
767 psize_max = 8192;
768 } else {
769 /* Force the point size to be as if the vertex output was disabled. */
770 psize_min = state->point_size;
771 psize_max = state->point_size;
772 }
773 /* Divide by two, because 0.5 = 1 pixel. */
774 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
775 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
776 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
777
778 tmp = (unsigned)state->line_width * 8;
779 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
780 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
781 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
782 S_028A48_MSAA_ENABLE(state->multisample ||
783 state->poly_smooth ||
784 state->line_smooth) |
785 S_028A48_VPORT_SCISSOR_ENABLE(1));
786
787 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
788 S_028BE4_PIX_CENTER(state->half_pixel_center) |
789 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
790
791 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
792 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
793 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
794 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
795 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
796 S_028814_FACE(!state->front_ccw) |
797 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
798 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
799 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
800 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
801 state->fill_back != PIPE_POLYGON_MODE_FILL) |
802 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
803 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
804 si_pm4_set_reg(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0 +
805 SI_SGPR_VS_STATE_BITS * 4, state->clamp_vertex_color);
806
807 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
808 for (i = 0; i < 3; i++) {
809 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
810 float offset_units = state->offset_units;
811 float offset_scale = state->offset_scale * 16.0f;
812 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
813
814 if (!state->offset_units_unscaled) {
815 switch (i) {
816 case 0: /* 16-bit zbuffer */
817 offset_units *= 4.0f;
818 pa_su_poly_offset_db_fmt_cntl =
819 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
820 break;
821 case 1: /* 24-bit zbuffer */
822 offset_units *= 2.0f;
823 pa_su_poly_offset_db_fmt_cntl =
824 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
825 break;
826 case 2: /* 32-bit zbuffer */
827 offset_units *= 1.0f;
828 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
829 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
830 break;
831 }
832 }
833
834 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
835 fui(offset_scale));
836 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
837 fui(offset_units));
838 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
839 fui(offset_scale));
840 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
841 fui(offset_units));
842 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
843 pa_su_poly_offset_db_fmt_cntl);
844 }
845
846 return rs;
847 }
848
849 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
850 {
851 struct si_context *sctx = (struct si_context *)ctx;
852 struct si_state_rasterizer *old_rs =
853 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
854 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
855
856 if (!state)
857 return;
858
859 if (sctx->framebuffer.nr_samples > 1 &&
860 (!old_rs || old_rs->multisample_enable != rs->multisample_enable)) {
861 si_mark_atom_dirty(sctx, &sctx->db_render_state);
862
863 if (sctx->b.family >= CHIP_POLARIS10)
864 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
865 }
866
867 r600_set_scissor_enable(&sctx->b, rs->scissor_enable);
868
869 si_pm4_bind_state(sctx, rasterizer, rs);
870 si_update_poly_offset_state(sctx);
871
872 si_mark_atom_dirty(sctx, &sctx->clip_regs);
873 sctx->do_update_shaders = true;
874 }
875
876 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
877 {
878 struct si_context *sctx = (struct si_context *)ctx;
879
880 if (sctx->queued.named.rasterizer == state)
881 si_pm4_bind_state(sctx, poly_offset, NULL);
882 si_pm4_delete_state(sctx, rasterizer, (struct si_state_rasterizer *)state);
883 }
884
885 /*
886 * infeered state between dsa and stencil ref
887 */
888 static void si_emit_stencil_ref(struct si_context *sctx, struct r600_atom *atom)
889 {
890 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
891 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
892 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
893
894 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
895 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
896 S_028430_STENCILMASK(dsa->valuemask[0]) |
897 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
898 S_028430_STENCILOPVAL(1));
899 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
900 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
901 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
902 S_028434_STENCILOPVAL_BF(1));
903 }
904
905 static void si_set_stencil_ref(struct pipe_context *ctx,
906 const struct pipe_stencil_ref *state)
907 {
908 struct si_context *sctx = (struct si_context *)ctx;
909
910 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
911 return;
912
913 sctx->stencil_ref.state = *state;
914 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
915 }
916
917
918 /*
919 * DSA
920 */
921
922 static uint32_t si_translate_stencil_op(int s_op)
923 {
924 switch (s_op) {
925 case PIPE_STENCIL_OP_KEEP:
926 return V_02842C_STENCIL_KEEP;
927 case PIPE_STENCIL_OP_ZERO:
928 return V_02842C_STENCIL_ZERO;
929 case PIPE_STENCIL_OP_REPLACE:
930 return V_02842C_STENCIL_REPLACE_TEST;
931 case PIPE_STENCIL_OP_INCR:
932 return V_02842C_STENCIL_ADD_CLAMP;
933 case PIPE_STENCIL_OP_DECR:
934 return V_02842C_STENCIL_SUB_CLAMP;
935 case PIPE_STENCIL_OP_INCR_WRAP:
936 return V_02842C_STENCIL_ADD_WRAP;
937 case PIPE_STENCIL_OP_DECR_WRAP:
938 return V_02842C_STENCIL_SUB_WRAP;
939 case PIPE_STENCIL_OP_INVERT:
940 return V_02842C_STENCIL_INVERT;
941 default:
942 R600_ERR("Unknown stencil op %d", s_op);
943 assert(0);
944 break;
945 }
946 return 0;
947 }
948
949 static void *si_create_dsa_state(struct pipe_context *ctx,
950 const struct pipe_depth_stencil_alpha_state *state)
951 {
952 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
953 struct si_pm4_state *pm4 = &dsa->pm4;
954 unsigned db_depth_control;
955 uint32_t db_stencil_control = 0;
956
957 if (!dsa) {
958 return NULL;
959 }
960
961 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
962 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
963 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
964 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
965
966 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
967 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
968 S_028800_ZFUNC(state->depth.func) |
969 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
970
971 /* stencil */
972 if (state->stencil[0].enabled) {
973 db_depth_control |= S_028800_STENCIL_ENABLE(1);
974 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
975 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
976 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
977 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
978
979 if (state->stencil[1].enabled) {
980 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
981 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
982 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
983 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
984 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
985 }
986 }
987
988 /* alpha */
989 if (state->alpha.enabled) {
990 dsa->alpha_func = state->alpha.func;
991
992 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
993 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
994 } else {
995 dsa->alpha_func = PIPE_FUNC_ALWAYS;
996 }
997
998 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
999 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1000 if (state->depth.bounds_test) {
1001 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1002 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1003 }
1004
1005 return dsa;
1006 }
1007
1008 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1009 {
1010 struct si_context *sctx = (struct si_context *)ctx;
1011 struct si_state_dsa *dsa = state;
1012
1013 if (!state)
1014 return;
1015
1016 si_pm4_bind_state(sctx, dsa, dsa);
1017
1018 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1019 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1020 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1021 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1022 }
1023 sctx->do_update_shaders = true;
1024 }
1025
1026 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1027 {
1028 struct si_context *sctx = (struct si_context *)ctx;
1029 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1030 }
1031
1032 static void *si_create_db_flush_dsa(struct si_context *sctx)
1033 {
1034 struct pipe_depth_stencil_alpha_state dsa = {};
1035
1036 return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
1037 }
1038
1039 /* DB RENDER STATE */
1040
1041 static void si_set_active_query_state(struct pipe_context *ctx, boolean enable)
1042 {
1043 struct si_context *sctx = (struct si_context*)ctx;
1044
1045 /* Pipeline stat & streamout queries. */
1046 if (enable) {
1047 sctx->b.flags &= ~R600_CONTEXT_STOP_PIPELINE_STATS;
1048 sctx->b.flags |= R600_CONTEXT_START_PIPELINE_STATS;
1049 } else {
1050 sctx->b.flags &= ~R600_CONTEXT_START_PIPELINE_STATS;
1051 sctx->b.flags |= R600_CONTEXT_STOP_PIPELINE_STATS;
1052 }
1053
1054 /* Occlusion queries. */
1055 if (sctx->occlusion_queries_disabled != !enable) {
1056 sctx->occlusion_queries_disabled = !enable;
1057 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1058 }
1059 }
1060
1061 static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
1062 {
1063 struct si_context *sctx = (struct si_context*)ctx;
1064
1065 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1066 }
1067
1068 static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
1069 {
1070 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1071 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1072 unsigned db_shader_control;
1073
1074 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1075
1076 /* DB_RENDER_CONTROL */
1077 if (sctx->dbcb_depth_copy_enabled ||
1078 sctx->dbcb_stencil_copy_enabled) {
1079 radeon_emit(cs,
1080 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1081 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1082 S_028000_COPY_CENTROID(1) |
1083 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
1084 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1085 radeon_emit(cs,
1086 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1087 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace));
1088 } else {
1089 radeon_emit(cs,
1090 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1091 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear));
1092 }
1093
1094 /* DB_COUNT_CONTROL (occlusion queries) */
1095 if (sctx->b.num_occlusion_queries > 0 &&
1096 !sctx->occlusion_queries_disabled) {
1097 bool perfect = sctx->b.num_perfect_occlusion_queries > 0;
1098
1099 if (sctx->b.chip_class >= CIK) {
1100 radeon_emit(cs,
1101 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1102 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
1103 S_028004_ZPASS_ENABLE(1) |
1104 S_028004_SLICE_EVEN_ENABLE(1) |
1105 S_028004_SLICE_ODD_ENABLE(1));
1106 } else {
1107 radeon_emit(cs,
1108 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1109 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
1110 }
1111 } else {
1112 /* Disable occlusion queries. */
1113 if (sctx->b.chip_class >= CIK) {
1114 radeon_emit(cs, 0);
1115 } else {
1116 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
1117 }
1118 }
1119
1120 /* DB_RENDER_OVERRIDE2 */
1121 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
1122 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1123 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1124 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4));
1125
1126 db_shader_control = S_02880C_ALPHA_TO_MASK_DISABLE(sctx->framebuffer.cb0_is_integer) |
1127 sctx->ps_db_shader_control;
1128
1129 /* Bug workaround for smoothing (overrasterization) on SI. */
1130 if (sctx->b.chip_class == SI && sctx->smoothing_enabled) {
1131 db_shader_control &= C_02880C_Z_ORDER;
1132 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1133 }
1134
1135 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1136 if (sctx->framebuffer.nr_samples <= 1 || (rs && !rs->multisample_enable))
1137 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1138
1139 if (sctx->b.family == CHIP_STONEY &&
1140 sctx->screen->b.debug_flags & DBG_NO_RB_PLUS)
1141 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1142
1143 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
1144 db_shader_control);
1145 }
1146
1147 /*
1148 * format translation
1149 */
1150 static uint32_t si_translate_colorformat(enum pipe_format format)
1151 {
1152 const struct util_format_description *desc = util_format_description(format);
1153
1154 #define HAS_SIZE(x,y,z,w) \
1155 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1156 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1157
1158 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1159 return V_028C70_COLOR_10_11_11;
1160
1161 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1162 return V_028C70_COLOR_INVALID;
1163
1164 /* hw cannot support mixed formats (except depth/stencil, since
1165 * stencil is not written to). */
1166 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1167 return V_028C70_COLOR_INVALID;
1168
1169 switch (desc->nr_channels) {
1170 case 1:
1171 switch (desc->channel[0].size) {
1172 case 8:
1173 return V_028C70_COLOR_8;
1174 case 16:
1175 return V_028C70_COLOR_16;
1176 case 32:
1177 return V_028C70_COLOR_32;
1178 }
1179 break;
1180 case 2:
1181 if (desc->channel[0].size == desc->channel[1].size) {
1182 switch (desc->channel[0].size) {
1183 case 8:
1184 return V_028C70_COLOR_8_8;
1185 case 16:
1186 return V_028C70_COLOR_16_16;
1187 case 32:
1188 return V_028C70_COLOR_32_32;
1189 }
1190 } else if (HAS_SIZE(8,24,0,0)) {
1191 return V_028C70_COLOR_24_8;
1192 } else if (HAS_SIZE(24,8,0,0)) {
1193 return V_028C70_COLOR_8_24;
1194 }
1195 break;
1196 case 3:
1197 if (HAS_SIZE(5,6,5,0)) {
1198 return V_028C70_COLOR_5_6_5;
1199 } else if (HAS_SIZE(32,8,24,0)) {
1200 return V_028C70_COLOR_X24_8_32_FLOAT;
1201 }
1202 break;
1203 case 4:
1204 if (desc->channel[0].size == desc->channel[1].size &&
1205 desc->channel[0].size == desc->channel[2].size &&
1206 desc->channel[0].size == desc->channel[3].size) {
1207 switch (desc->channel[0].size) {
1208 case 4:
1209 return V_028C70_COLOR_4_4_4_4;
1210 case 8:
1211 return V_028C70_COLOR_8_8_8_8;
1212 case 16:
1213 return V_028C70_COLOR_16_16_16_16;
1214 case 32:
1215 return V_028C70_COLOR_32_32_32_32;
1216 }
1217 } else if (HAS_SIZE(5,5,5,1)) {
1218 return V_028C70_COLOR_1_5_5_5;
1219 } else if (HAS_SIZE(10,10,10,2)) {
1220 return V_028C70_COLOR_2_10_10_10;
1221 }
1222 break;
1223 }
1224 return V_028C70_COLOR_INVALID;
1225 }
1226
1227 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1228 {
1229 if (SI_BIG_ENDIAN) {
1230 switch(colorformat) {
1231 /* 8-bit buffers. */
1232 case V_028C70_COLOR_8:
1233 return V_028C70_ENDIAN_NONE;
1234
1235 /* 16-bit buffers. */
1236 case V_028C70_COLOR_5_6_5:
1237 case V_028C70_COLOR_1_5_5_5:
1238 case V_028C70_COLOR_4_4_4_4:
1239 case V_028C70_COLOR_16:
1240 case V_028C70_COLOR_8_8:
1241 return V_028C70_ENDIAN_8IN16;
1242
1243 /* 32-bit buffers. */
1244 case V_028C70_COLOR_8_8_8_8:
1245 case V_028C70_COLOR_2_10_10_10:
1246 case V_028C70_COLOR_8_24:
1247 case V_028C70_COLOR_24_8:
1248 case V_028C70_COLOR_16_16:
1249 return V_028C70_ENDIAN_8IN32;
1250
1251 /* 64-bit buffers. */
1252 case V_028C70_COLOR_16_16_16_16:
1253 return V_028C70_ENDIAN_8IN16;
1254
1255 case V_028C70_COLOR_32_32:
1256 return V_028C70_ENDIAN_8IN32;
1257
1258 /* 128-bit buffers. */
1259 case V_028C70_COLOR_32_32_32_32:
1260 return V_028C70_ENDIAN_8IN32;
1261 default:
1262 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1263 }
1264 } else {
1265 return V_028C70_ENDIAN_NONE;
1266 }
1267 }
1268
1269 static uint32_t si_translate_dbformat(enum pipe_format format)
1270 {
1271 switch (format) {
1272 case PIPE_FORMAT_Z16_UNORM:
1273 return V_028040_Z_16;
1274 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1275 case PIPE_FORMAT_X8Z24_UNORM:
1276 case PIPE_FORMAT_Z24X8_UNORM:
1277 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1278 return V_028040_Z_24; /* deprecated on SI */
1279 case PIPE_FORMAT_Z32_FLOAT:
1280 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1281 return V_028040_Z_32_FLOAT;
1282 default:
1283 return V_028040_Z_INVALID;
1284 }
1285 }
1286
1287 /*
1288 * Texture translation
1289 */
1290
1291 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1292 enum pipe_format format,
1293 const struct util_format_description *desc,
1294 int first_non_void)
1295 {
1296 struct si_screen *sscreen = (struct si_screen*)screen;
1297 bool enable_compressed_formats = (sscreen->b.info.drm_major == 2 &&
1298 sscreen->b.info.drm_minor >= 31) ||
1299 sscreen->b.info.drm_major == 3;
1300 bool uniform = true;
1301 int i;
1302
1303 /* Colorspace (return non-RGB formats directly). */
1304 switch (desc->colorspace) {
1305 /* Depth stencil formats */
1306 case UTIL_FORMAT_COLORSPACE_ZS:
1307 switch (format) {
1308 case PIPE_FORMAT_Z16_UNORM:
1309 return V_008F14_IMG_DATA_FORMAT_16;
1310 case PIPE_FORMAT_X24S8_UINT:
1311 case PIPE_FORMAT_Z24X8_UNORM:
1312 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1313 return V_008F14_IMG_DATA_FORMAT_8_24;
1314 case PIPE_FORMAT_X8Z24_UNORM:
1315 case PIPE_FORMAT_S8X24_UINT:
1316 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1317 return V_008F14_IMG_DATA_FORMAT_24_8;
1318 case PIPE_FORMAT_S8_UINT:
1319 return V_008F14_IMG_DATA_FORMAT_8;
1320 case PIPE_FORMAT_Z32_FLOAT:
1321 return V_008F14_IMG_DATA_FORMAT_32;
1322 case PIPE_FORMAT_X32_S8X24_UINT:
1323 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1324 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1325 default:
1326 goto out_unknown;
1327 }
1328
1329 case UTIL_FORMAT_COLORSPACE_YUV:
1330 goto out_unknown; /* TODO */
1331
1332 case UTIL_FORMAT_COLORSPACE_SRGB:
1333 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1334 goto out_unknown;
1335 break;
1336
1337 default:
1338 break;
1339 }
1340
1341 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1342 if (!enable_compressed_formats)
1343 goto out_unknown;
1344
1345 switch (format) {
1346 case PIPE_FORMAT_RGTC1_SNORM:
1347 case PIPE_FORMAT_LATC1_SNORM:
1348 case PIPE_FORMAT_RGTC1_UNORM:
1349 case PIPE_FORMAT_LATC1_UNORM:
1350 return V_008F14_IMG_DATA_FORMAT_BC4;
1351 case PIPE_FORMAT_RGTC2_SNORM:
1352 case PIPE_FORMAT_LATC2_SNORM:
1353 case PIPE_FORMAT_RGTC2_UNORM:
1354 case PIPE_FORMAT_LATC2_UNORM:
1355 return V_008F14_IMG_DATA_FORMAT_BC5;
1356 default:
1357 goto out_unknown;
1358 }
1359 }
1360
1361 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1362 sscreen->b.family == CHIP_STONEY) {
1363 switch (format) {
1364 case PIPE_FORMAT_ETC1_RGB8:
1365 case PIPE_FORMAT_ETC2_RGB8:
1366 case PIPE_FORMAT_ETC2_SRGB8:
1367 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1368 case PIPE_FORMAT_ETC2_RGB8A1:
1369 case PIPE_FORMAT_ETC2_SRGB8A1:
1370 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1371 case PIPE_FORMAT_ETC2_RGBA8:
1372 case PIPE_FORMAT_ETC2_SRGBA8:
1373 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1374 case PIPE_FORMAT_ETC2_R11_UNORM:
1375 case PIPE_FORMAT_ETC2_R11_SNORM:
1376 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1377 case PIPE_FORMAT_ETC2_RG11_UNORM:
1378 case PIPE_FORMAT_ETC2_RG11_SNORM:
1379 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1380 default:
1381 goto out_unknown;
1382 }
1383 }
1384
1385 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1386 if (!enable_compressed_formats)
1387 goto out_unknown;
1388
1389 switch (format) {
1390 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1391 case PIPE_FORMAT_BPTC_SRGBA:
1392 return V_008F14_IMG_DATA_FORMAT_BC7;
1393 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1394 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1395 return V_008F14_IMG_DATA_FORMAT_BC6;
1396 default:
1397 goto out_unknown;
1398 }
1399 }
1400
1401 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1402 switch (format) {
1403 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1404 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1405 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1406 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1407 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1408 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1409 default:
1410 goto out_unknown;
1411 }
1412 }
1413
1414 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1415 if (!enable_compressed_formats)
1416 goto out_unknown;
1417
1418 if (!util_format_s3tc_enabled) {
1419 goto out_unknown;
1420 }
1421
1422 switch (format) {
1423 case PIPE_FORMAT_DXT1_RGB:
1424 case PIPE_FORMAT_DXT1_RGBA:
1425 case PIPE_FORMAT_DXT1_SRGB:
1426 case PIPE_FORMAT_DXT1_SRGBA:
1427 return V_008F14_IMG_DATA_FORMAT_BC1;
1428 case PIPE_FORMAT_DXT3_RGBA:
1429 case PIPE_FORMAT_DXT3_SRGBA:
1430 return V_008F14_IMG_DATA_FORMAT_BC2;
1431 case PIPE_FORMAT_DXT5_RGBA:
1432 case PIPE_FORMAT_DXT5_SRGBA:
1433 return V_008F14_IMG_DATA_FORMAT_BC3;
1434 default:
1435 goto out_unknown;
1436 }
1437 }
1438
1439 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1440 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1441 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1442 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1443 }
1444
1445 /* R8G8Bx_SNORM - TODO CxV8U8 */
1446
1447 /* hw cannot support mixed formats (except depth/stencil, since only
1448 * depth is read).*/
1449 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1450 goto out_unknown;
1451
1452 /* See whether the components are of the same size. */
1453 for (i = 1; i < desc->nr_channels; i++) {
1454 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1455 }
1456
1457 /* Non-uniform formats. */
1458 if (!uniform) {
1459 switch(desc->nr_channels) {
1460 case 3:
1461 if (desc->channel[0].size == 5 &&
1462 desc->channel[1].size == 6 &&
1463 desc->channel[2].size == 5) {
1464 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1465 }
1466 goto out_unknown;
1467 case 4:
1468 if (desc->channel[0].size == 5 &&
1469 desc->channel[1].size == 5 &&
1470 desc->channel[2].size == 5 &&
1471 desc->channel[3].size == 1) {
1472 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1473 }
1474 if (desc->channel[0].size == 10 &&
1475 desc->channel[1].size == 10 &&
1476 desc->channel[2].size == 10 &&
1477 desc->channel[3].size == 2) {
1478 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1479 }
1480 goto out_unknown;
1481 }
1482 goto out_unknown;
1483 }
1484
1485 if (first_non_void < 0 || first_non_void > 3)
1486 goto out_unknown;
1487
1488 /* uniform formats */
1489 switch (desc->channel[first_non_void].size) {
1490 case 4:
1491 switch (desc->nr_channels) {
1492 #if 0 /* Not supported for render targets */
1493 case 2:
1494 return V_008F14_IMG_DATA_FORMAT_4_4;
1495 #endif
1496 case 4:
1497 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1498 }
1499 break;
1500 case 8:
1501 switch (desc->nr_channels) {
1502 case 1:
1503 return V_008F14_IMG_DATA_FORMAT_8;
1504 case 2:
1505 return V_008F14_IMG_DATA_FORMAT_8_8;
1506 case 4:
1507 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1508 }
1509 break;
1510 case 16:
1511 switch (desc->nr_channels) {
1512 case 1:
1513 return V_008F14_IMG_DATA_FORMAT_16;
1514 case 2:
1515 return V_008F14_IMG_DATA_FORMAT_16_16;
1516 case 4:
1517 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1518 }
1519 break;
1520 case 32:
1521 switch (desc->nr_channels) {
1522 case 1:
1523 return V_008F14_IMG_DATA_FORMAT_32;
1524 case 2:
1525 return V_008F14_IMG_DATA_FORMAT_32_32;
1526 #if 0 /* Not supported for render targets */
1527 case 3:
1528 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1529 #endif
1530 case 4:
1531 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1532 }
1533 }
1534
1535 out_unknown:
1536 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1537 return ~0;
1538 }
1539
1540 static unsigned si_tex_wrap(unsigned wrap)
1541 {
1542 switch (wrap) {
1543 default:
1544 case PIPE_TEX_WRAP_REPEAT:
1545 return V_008F30_SQ_TEX_WRAP;
1546 case PIPE_TEX_WRAP_CLAMP:
1547 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1548 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1549 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1550 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1551 return V_008F30_SQ_TEX_CLAMP_BORDER;
1552 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1553 return V_008F30_SQ_TEX_MIRROR;
1554 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1555 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1556 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1557 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1558 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1559 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1560 }
1561 }
1562
1563 static unsigned si_tex_mipfilter(unsigned filter)
1564 {
1565 switch (filter) {
1566 case PIPE_TEX_MIPFILTER_NEAREST:
1567 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1568 case PIPE_TEX_MIPFILTER_LINEAR:
1569 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1570 default:
1571 case PIPE_TEX_MIPFILTER_NONE:
1572 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1573 }
1574 }
1575
1576 static unsigned si_tex_compare(unsigned compare)
1577 {
1578 switch (compare) {
1579 default:
1580 case PIPE_FUNC_NEVER:
1581 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1582 case PIPE_FUNC_LESS:
1583 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1584 case PIPE_FUNC_EQUAL:
1585 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1586 case PIPE_FUNC_LEQUAL:
1587 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1588 case PIPE_FUNC_GREATER:
1589 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1590 case PIPE_FUNC_NOTEQUAL:
1591 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1592 case PIPE_FUNC_GEQUAL:
1593 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1594 case PIPE_FUNC_ALWAYS:
1595 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1596 }
1597 }
1598
1599 static unsigned si_tex_dim(unsigned res_target, unsigned view_target,
1600 unsigned nr_samples)
1601 {
1602 if (view_target == PIPE_TEXTURE_CUBE ||
1603 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1604 res_target = view_target;
1605
1606 switch (res_target) {
1607 default:
1608 case PIPE_TEXTURE_1D:
1609 return V_008F1C_SQ_RSRC_IMG_1D;
1610 case PIPE_TEXTURE_1D_ARRAY:
1611 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1612 case PIPE_TEXTURE_2D:
1613 case PIPE_TEXTURE_RECT:
1614 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1615 V_008F1C_SQ_RSRC_IMG_2D;
1616 case PIPE_TEXTURE_2D_ARRAY:
1617 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1618 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1619 case PIPE_TEXTURE_3D:
1620 return V_008F1C_SQ_RSRC_IMG_3D;
1621 case PIPE_TEXTURE_CUBE:
1622 case PIPE_TEXTURE_CUBE_ARRAY:
1623 return V_008F1C_SQ_RSRC_IMG_CUBE;
1624 }
1625 }
1626
1627 /*
1628 * Format support testing
1629 */
1630
1631 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1632 {
1633 return si_translate_texformat(screen, format, util_format_description(format),
1634 util_format_get_first_non_void_channel(format)) != ~0U;
1635 }
1636
1637 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1638 const struct util_format_description *desc,
1639 int first_non_void)
1640 {
1641 unsigned type;
1642 int i;
1643
1644 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1645 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1646
1647 assert(first_non_void >= 0);
1648 type = desc->channel[first_non_void].type;
1649
1650 if (type == UTIL_FORMAT_TYPE_FIXED)
1651 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1652
1653 if (desc->nr_channels == 4 &&
1654 desc->channel[0].size == 10 &&
1655 desc->channel[1].size == 10 &&
1656 desc->channel[2].size == 10 &&
1657 desc->channel[3].size == 2)
1658 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1659
1660 /* See whether the components are of the same size. */
1661 for (i = 0; i < desc->nr_channels; i++) {
1662 if (desc->channel[first_non_void].size != desc->channel[i].size)
1663 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1664 }
1665
1666 switch (desc->channel[first_non_void].size) {
1667 case 8:
1668 switch (desc->nr_channels) {
1669 case 1:
1670 return V_008F0C_BUF_DATA_FORMAT_8;
1671 case 2:
1672 return V_008F0C_BUF_DATA_FORMAT_8_8;
1673 case 3:
1674 case 4:
1675 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1676 }
1677 break;
1678 case 16:
1679 switch (desc->nr_channels) {
1680 case 1:
1681 return V_008F0C_BUF_DATA_FORMAT_16;
1682 case 2:
1683 return V_008F0C_BUF_DATA_FORMAT_16_16;
1684 case 3:
1685 case 4:
1686 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1687 }
1688 break;
1689 case 32:
1690 /* From the Southern Islands ISA documentation about MTBUF:
1691 * 'Memory reads of data in memory that is 32 or 64 bits do not
1692 * undergo any format conversion.'
1693 */
1694 if (type != UTIL_FORMAT_TYPE_FLOAT &&
1695 !desc->channel[first_non_void].pure_integer)
1696 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1697
1698 switch (desc->nr_channels) {
1699 case 1:
1700 return V_008F0C_BUF_DATA_FORMAT_32;
1701 case 2:
1702 return V_008F0C_BUF_DATA_FORMAT_32_32;
1703 case 3:
1704 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1705 case 4:
1706 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1707 }
1708 break;
1709 }
1710
1711 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1712 }
1713
1714 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1715 const struct util_format_description *desc,
1716 int first_non_void)
1717 {
1718 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1719 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1720
1721 assert(first_non_void >= 0);
1722
1723 switch (desc->channel[first_non_void].type) {
1724 case UTIL_FORMAT_TYPE_SIGNED:
1725 if (desc->channel[first_non_void].normalized)
1726 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1727 else if (desc->channel[first_non_void].pure_integer)
1728 return V_008F0C_BUF_NUM_FORMAT_SINT;
1729 else
1730 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1731 break;
1732 case UTIL_FORMAT_TYPE_UNSIGNED:
1733 if (desc->channel[first_non_void].normalized)
1734 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1735 else if (desc->channel[first_non_void].pure_integer)
1736 return V_008F0C_BUF_NUM_FORMAT_UINT;
1737 else
1738 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1739 break;
1740 case UTIL_FORMAT_TYPE_FLOAT:
1741 default:
1742 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1743 }
1744 }
1745
1746 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
1747 {
1748 const struct util_format_description *desc;
1749 int first_non_void;
1750 unsigned data_format;
1751
1752 desc = util_format_description(format);
1753 first_non_void = util_format_get_first_non_void_channel(format);
1754 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1755 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
1756 }
1757
1758 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1759 {
1760 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1761 r600_translate_colorswap(format, false) != ~0U;
1762 }
1763
1764 static bool si_is_zs_format_supported(enum pipe_format format)
1765 {
1766 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1767 }
1768
1769 static boolean si_is_format_supported(struct pipe_screen *screen,
1770 enum pipe_format format,
1771 enum pipe_texture_target target,
1772 unsigned sample_count,
1773 unsigned usage)
1774 {
1775 unsigned retval = 0;
1776
1777 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1778 R600_ERR("r600: unsupported texture type %d\n", target);
1779 return false;
1780 }
1781
1782 if (!util_format_is_supported(format, usage))
1783 return false;
1784
1785 if (sample_count > 1) {
1786 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
1787 return false;
1788
1789 if (usage & PIPE_BIND_SHADER_IMAGE)
1790 return false;
1791
1792 switch (sample_count) {
1793 case 2:
1794 case 4:
1795 case 8:
1796 break;
1797 case 16:
1798 if (format == PIPE_FORMAT_NONE)
1799 return true;
1800 else
1801 return false;
1802 default:
1803 return false;
1804 }
1805 }
1806
1807 if (usage & (PIPE_BIND_SAMPLER_VIEW |
1808 PIPE_BIND_SHADER_IMAGE)) {
1809 if (target == PIPE_BUFFER) {
1810 if (si_is_vertex_format_supported(screen, format))
1811 retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
1812 PIPE_BIND_SHADER_IMAGE);
1813 } else {
1814 if (si_is_sampler_format_supported(screen, format))
1815 retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
1816 PIPE_BIND_SHADER_IMAGE);
1817 }
1818 }
1819
1820 if ((usage & (PIPE_BIND_RENDER_TARGET |
1821 PIPE_BIND_DISPLAY_TARGET |
1822 PIPE_BIND_SCANOUT |
1823 PIPE_BIND_SHARED |
1824 PIPE_BIND_BLENDABLE)) &&
1825 si_is_colorbuffer_format_supported(format)) {
1826 retval |= usage &
1827 (PIPE_BIND_RENDER_TARGET |
1828 PIPE_BIND_DISPLAY_TARGET |
1829 PIPE_BIND_SCANOUT |
1830 PIPE_BIND_SHARED);
1831 if (!util_format_is_pure_integer(format) &&
1832 !util_format_is_depth_or_stencil(format))
1833 retval |= usage & PIPE_BIND_BLENDABLE;
1834 }
1835
1836 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1837 si_is_zs_format_supported(format)) {
1838 retval |= PIPE_BIND_DEPTH_STENCIL;
1839 }
1840
1841 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
1842 si_is_vertex_format_supported(screen, format)) {
1843 retval |= PIPE_BIND_VERTEX_BUFFER;
1844 }
1845
1846 if (usage & PIPE_BIND_TRANSFER_READ)
1847 retval |= PIPE_BIND_TRANSFER_READ;
1848 if (usage & PIPE_BIND_TRANSFER_WRITE)
1849 retval |= PIPE_BIND_TRANSFER_WRITE;
1850
1851 if ((usage & PIPE_BIND_LINEAR) &&
1852 !util_format_is_compressed(format) &&
1853 !(usage & PIPE_BIND_DEPTH_STENCIL))
1854 retval |= PIPE_BIND_LINEAR;
1855
1856 return retval == usage;
1857 }
1858
1859 /*
1860 * framebuffer handling
1861 */
1862
1863 static void si_choose_spi_color_formats(struct r600_surface *surf,
1864 unsigned format, unsigned swap,
1865 unsigned ntype, bool is_depth)
1866 {
1867 /* Alpha is needed for alpha-to-coverage.
1868 * Blending may be with or without alpha.
1869 */
1870 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
1871 unsigned alpha = 0; /* exports alpha, but may not support blending */
1872 unsigned blend = 0; /* supports blending, but may not export alpha */
1873 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
1874
1875 /* Choose the SPI color formats. These are required values for Stoney/RB+.
1876 * Other chips have multiple choices, though they are not necessarily better.
1877 */
1878 switch (format) {
1879 case V_028C70_COLOR_5_6_5:
1880 case V_028C70_COLOR_1_5_5_5:
1881 case V_028C70_COLOR_5_5_5_1:
1882 case V_028C70_COLOR_4_4_4_4:
1883 case V_028C70_COLOR_10_11_11:
1884 case V_028C70_COLOR_11_11_10:
1885 case V_028C70_COLOR_8:
1886 case V_028C70_COLOR_8_8:
1887 case V_028C70_COLOR_8_8_8_8:
1888 case V_028C70_COLOR_10_10_10_2:
1889 case V_028C70_COLOR_2_10_10_10:
1890 if (ntype == V_028C70_NUMBER_UINT)
1891 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
1892 else if (ntype == V_028C70_NUMBER_SINT)
1893 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
1894 else
1895 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
1896 break;
1897
1898 case V_028C70_COLOR_16:
1899 case V_028C70_COLOR_16_16:
1900 case V_028C70_COLOR_16_16_16_16:
1901 if (ntype == V_028C70_NUMBER_UNORM ||
1902 ntype == V_028C70_NUMBER_SNORM) {
1903 /* UNORM16 and SNORM16 don't support blending */
1904 if (ntype == V_028C70_NUMBER_UNORM)
1905 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
1906 else
1907 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
1908
1909 /* Use 32 bits per channel for blending. */
1910 if (format == V_028C70_COLOR_16) {
1911 if (swap == V_028C70_SWAP_STD) { /* R */
1912 blend = V_028714_SPI_SHADER_32_R;
1913 blend_alpha = V_028714_SPI_SHADER_32_AR;
1914 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
1915 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
1916 else
1917 assert(0);
1918 } else if (format == V_028C70_COLOR_16_16) {
1919 if (swap == V_028C70_SWAP_STD) { /* RG */
1920 blend = V_028714_SPI_SHADER_32_GR;
1921 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
1922 } else if (swap == V_028C70_SWAP_ALT) /* RA */
1923 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
1924 else
1925 assert(0);
1926 } else /* 16_16_16_16 */
1927 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
1928 } else if (ntype == V_028C70_NUMBER_UINT)
1929 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
1930 else if (ntype == V_028C70_NUMBER_SINT)
1931 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
1932 else if (ntype == V_028C70_NUMBER_FLOAT)
1933 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
1934 else
1935 assert(0);
1936 break;
1937
1938 case V_028C70_COLOR_32:
1939 if (swap == V_028C70_SWAP_STD) { /* R */
1940 blend = normal = V_028714_SPI_SHADER_32_R;
1941 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
1942 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
1943 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
1944 else
1945 assert(0);
1946 break;
1947
1948 case V_028C70_COLOR_32_32:
1949 if (swap == V_028C70_SWAP_STD) { /* RG */
1950 blend = normal = V_028714_SPI_SHADER_32_GR;
1951 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
1952 } else if (swap == V_028C70_SWAP_ALT) /* RA */
1953 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
1954 else
1955 assert(0);
1956 break;
1957
1958 case V_028C70_COLOR_32_32_32_32:
1959 case V_028C70_COLOR_8_24:
1960 case V_028C70_COLOR_24_8:
1961 case V_028C70_COLOR_X24_8_32_FLOAT:
1962 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
1963 break;
1964
1965 default:
1966 assert(0);
1967 return;
1968 }
1969
1970 /* The DB->CB copy needs 32_ABGR. */
1971 if (is_depth)
1972 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
1973
1974 surf->spi_shader_col_format = normal;
1975 surf->spi_shader_col_format_alpha = alpha;
1976 surf->spi_shader_col_format_blend = blend;
1977 surf->spi_shader_col_format_blend_alpha = blend_alpha;
1978 }
1979
1980 static void si_initialize_color_surface(struct si_context *sctx,
1981 struct r600_surface *surf)
1982 {
1983 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1984 unsigned color_info, color_attrib, color_view;
1985 unsigned format, swap, ntype, endian;
1986 const struct util_format_description *desc;
1987 int i;
1988 unsigned blend_clamp = 0, blend_bypass = 0;
1989
1990 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
1991 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
1992
1993 desc = util_format_description(surf->base.format);
1994 for (i = 0; i < 4; i++) {
1995 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1996 break;
1997 }
1998 }
1999 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
2000 ntype = V_028C70_NUMBER_FLOAT;
2001 } else {
2002 ntype = V_028C70_NUMBER_UNORM;
2003 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2004 ntype = V_028C70_NUMBER_SRGB;
2005 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2006 if (desc->channel[i].pure_integer) {
2007 ntype = V_028C70_NUMBER_SINT;
2008 } else {
2009 assert(desc->channel[i].normalized);
2010 ntype = V_028C70_NUMBER_SNORM;
2011 }
2012 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2013 if (desc->channel[i].pure_integer) {
2014 ntype = V_028C70_NUMBER_UINT;
2015 } else {
2016 assert(desc->channel[i].normalized);
2017 ntype = V_028C70_NUMBER_UNORM;
2018 }
2019 }
2020 }
2021
2022 format = si_translate_colorformat(surf->base.format);
2023 if (format == V_028C70_COLOR_INVALID) {
2024 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2025 }
2026 assert(format != V_028C70_COLOR_INVALID);
2027 swap = r600_translate_colorswap(surf->base.format, false);
2028 endian = si_colorformat_endian_swap(format);
2029
2030 /* blend clamp should be set for all NORM/SRGB types */
2031 if (ntype == V_028C70_NUMBER_UNORM ||
2032 ntype == V_028C70_NUMBER_SNORM ||
2033 ntype == V_028C70_NUMBER_SRGB)
2034 blend_clamp = 1;
2035
2036 /* set blend bypass according to docs if SINT/UINT or
2037 8/24 COLOR variants */
2038 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2039 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2040 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2041 blend_clamp = 0;
2042 blend_bypass = 1;
2043 }
2044
2045 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
2046 (format == V_028C70_COLOR_8 ||
2047 format == V_028C70_COLOR_8_8 ||
2048 format == V_028C70_COLOR_8_8_8_8))
2049 surf->color_is_int8 = true;
2050
2051 color_info = S_028C70_FORMAT(format) |
2052 S_028C70_COMP_SWAP(swap) |
2053 S_028C70_BLEND_CLAMP(blend_clamp) |
2054 S_028C70_BLEND_BYPASS(blend_bypass) |
2055 S_028C70_NUMBER_TYPE(ntype) |
2056 S_028C70_ENDIAN(endian);
2057
2058 /* Intensity is implemented as Red, so treat it that way. */
2059 color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2060 util_format_is_intensity(surf->base.format));
2061
2062 if (rtex->resource.b.b.nr_samples > 1) {
2063 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
2064
2065 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2066 S_028C74_NUM_FRAGMENTS(log_samples);
2067
2068 if (rtex->fmask.size) {
2069 color_info |= S_028C70_COMPRESSION(1);
2070 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
2071
2072 if (sctx->b.chip_class == SI) {
2073 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2074 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2075 }
2076 }
2077 }
2078
2079 surf->cb_color_view = color_view;
2080 surf->cb_color_info = color_info;
2081 surf->cb_color_attrib = color_attrib;
2082
2083 if (sctx->b.chip_class >= VI) {
2084 unsigned max_uncompressed_block_size = 2;
2085
2086 if (rtex->surface.nsamples > 1) {
2087 if (rtex->surface.bpe == 1)
2088 max_uncompressed_block_size = 0;
2089 else if (rtex->surface.bpe == 2)
2090 max_uncompressed_block_size = 1;
2091 }
2092
2093 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2094 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2095 }
2096
2097 /* This must be set for fast clear to work without FMASK. */
2098 if (!rtex->fmask.size && sctx->b.chip_class == SI) {
2099 unsigned bankh = util_logbase2(rtex->surface.bankh);
2100 surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2101 }
2102
2103 /* Determine pixel shader export format */
2104 si_choose_spi_color_formats(surf, format, swap, ntype, rtex->is_depth);
2105
2106 surf->color_initialized = true;
2107 }
2108
2109 static void si_init_depth_surface(struct si_context *sctx,
2110 struct r600_surface *surf)
2111 {
2112 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2113 unsigned level = surf->base.u.tex.level;
2114 struct radeon_surf_level *levelinfo = &rtex->surface.level[level];
2115 unsigned format;
2116 uint32_t z_info, s_info, db_depth_info;
2117 uint64_t z_offs, s_offs;
2118 uint32_t db_htile_data_base, db_htile_surface;
2119
2120 format = si_translate_dbformat(rtex->resource.b.b.format);
2121
2122 if (format == V_028040_Z_INVALID) {
2123 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
2124 }
2125 assert(format != V_028040_Z_INVALID);
2126
2127 s_offs = z_offs = rtex->resource.gpu_address;
2128 z_offs += rtex->surface.level[level].offset;
2129 s_offs += rtex->surface.stencil_level[level].offset;
2130
2131 db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
2132
2133 z_info = S_028040_FORMAT(format);
2134 if (rtex->resource.b.b.nr_samples > 1) {
2135 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
2136 }
2137
2138 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
2139 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
2140 else
2141 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
2142
2143 if (sctx->b.chip_class >= CIK) {
2144 struct radeon_info *info = &sctx->screen->b.info;
2145 unsigned index = rtex->surface.tiling_index[level];
2146 unsigned stencil_index = rtex->surface.stencil_tiling_index[level];
2147 unsigned macro_index = rtex->surface.macro_tile_index;
2148 unsigned tile_mode = info->si_tile_mode_array[index];
2149 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2150 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2151
2152 db_depth_info |=
2153 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2154 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2155 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2156 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2157 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2158 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2159 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2160 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2161 } else {
2162 unsigned tile_mode_index = si_tile_mode_index(rtex, level, false);
2163 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2164 tile_mode_index = si_tile_mode_index(rtex, level, true);
2165 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2166 }
2167
2168 /* HiZ aka depth buffer htile */
2169 /* use htile only for first level */
2170 if (rtex->htile_buffer && !level) {
2171 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2172 S_028040_ALLOW_EXPCLEAR(1);
2173
2174 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
2175 /* Workaround: For a not yet understood reason, the
2176 * combination of MSAA, fast stencil clear and stencil
2177 * decompress messes with subsequent stencil buffer
2178 * uses. Problem was reproduced on Verde, Bonaire,
2179 * Tonga, and Carrizo.
2180 *
2181 * Disabling EXPCLEAR works around the problem.
2182 *
2183 * Check piglit's arb_texture_multisample-stencil-clear
2184 * test if you want to try changing this.
2185 */
2186 if (rtex->resource.b.b.nr_samples <= 1)
2187 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2188 } else
2189 /* Use all of the htile_buffer for depth if there's no stencil. */
2190 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2191
2192 uint64_t va = rtex->htile_buffer->gpu_address;
2193 db_htile_data_base = va >> 8;
2194 db_htile_surface = S_028ABC_FULL_CACHE(1);
2195 } else {
2196 db_htile_data_base = 0;
2197 db_htile_surface = 0;
2198 }
2199
2200 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2201
2202 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2203 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2204 surf->db_htile_data_base = db_htile_data_base;
2205 surf->db_depth_info = db_depth_info;
2206 surf->db_z_info = z_info;
2207 surf->db_stencil_info = s_info;
2208 surf->db_depth_base = z_offs >> 8;
2209 surf->db_stencil_base = s_offs >> 8;
2210 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2211 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2212 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2213 levelinfo->nblk_y) / 64 - 1);
2214 surf->db_htile_surface = db_htile_surface;
2215
2216 surf->depth_initialized = true;
2217 }
2218
2219 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
2220 {
2221 for (int i = 0; i < state->nr_cbufs; ++i) {
2222 struct r600_surface *surf = NULL;
2223 struct r600_texture *rtex;
2224
2225 if (!state->cbufs[i])
2226 continue;
2227 surf = (struct r600_surface*)state->cbufs[i];
2228 rtex = (struct r600_texture*)surf->base.texture;
2229
2230 p_atomic_dec(&rtex->framebuffers_bound);
2231 }
2232 }
2233
2234 static void si_set_framebuffer_state(struct pipe_context *ctx,
2235 const struct pipe_framebuffer_state *state)
2236 {
2237 struct si_context *sctx = (struct si_context *)ctx;
2238 struct pipe_constant_buffer constbuf = {0};
2239 struct r600_surface *surf = NULL;
2240 struct r600_texture *rtex;
2241 bool old_cb0_is_integer = sctx->framebuffer.cb0_is_integer;
2242 bool old_any_dst_linear = sctx->framebuffer.any_dst_linear;
2243 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2244 int i;
2245
2246 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
2247 if (!sctx->framebuffer.state.cbufs[i])
2248 continue;
2249
2250 rtex = (struct r600_texture*)sctx->framebuffer.state.cbufs[i]->texture;
2251 if (rtex->dcc_gather_statistics)
2252 vi_separate_dcc_stop_query(ctx, rtex);
2253 }
2254
2255 /* Only flush TC when changing the framebuffer state, because
2256 * the only client not using TC that can change textures is
2257 * the framebuffer.
2258 *
2259 * Flush all CB and DB caches here because all buffers can be used
2260 * for write by both TC (with shader image stores) and CB/DB.
2261 */
2262 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
2263 SI_CONTEXT_INV_GLOBAL_L2 |
2264 SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER |
2265 SI_CONTEXT_CS_PARTIAL_FLUSH;
2266
2267 /* Take the maximum of the old and new count. If the new count is lower,
2268 * dirtying is needed to disable the unbound colorbuffers.
2269 */
2270 sctx->framebuffer.dirty_cbufs |=
2271 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2272 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2273
2274 si_dec_framebuffer_counters(&sctx->framebuffer.state);
2275 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2276
2277 sctx->framebuffer.spi_shader_col_format = 0;
2278 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2279 sctx->framebuffer.spi_shader_col_format_blend = 0;
2280 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2281 sctx->framebuffer.color_is_int8 = 0;
2282
2283 sctx->framebuffer.compressed_cb_mask = 0;
2284 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2285 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2286 sctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
2287 util_format_is_pure_integer(state->cbufs[0]->format);
2288 sctx->framebuffer.any_dst_linear = false;
2289
2290 if (sctx->framebuffer.cb0_is_integer != old_cb0_is_integer)
2291 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2292
2293 for (i = 0; i < state->nr_cbufs; i++) {
2294 if (!state->cbufs[i])
2295 continue;
2296
2297 surf = (struct r600_surface*)state->cbufs[i];
2298 rtex = (struct r600_texture*)surf->base.texture;
2299
2300 if (!surf->color_initialized) {
2301 si_initialize_color_surface(sctx, surf);
2302 }
2303
2304 sctx->framebuffer.spi_shader_col_format |=
2305 surf->spi_shader_col_format << (i * 4);
2306 sctx->framebuffer.spi_shader_col_format_alpha |=
2307 surf->spi_shader_col_format_alpha << (i * 4);
2308 sctx->framebuffer.spi_shader_col_format_blend |=
2309 surf->spi_shader_col_format_blend << (i * 4);
2310 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2311 surf->spi_shader_col_format_blend_alpha << (i * 4);
2312
2313 if (surf->color_is_int8)
2314 sctx->framebuffer.color_is_int8 |= 1 << i;
2315
2316 if (rtex->fmask.size && rtex->cmask.size) {
2317 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2318 }
2319
2320 if (surf->level_info->mode == RADEON_SURF_MODE_LINEAR_ALIGNED)
2321 sctx->framebuffer.any_dst_linear = true;
2322
2323 r600_context_add_resource_size(ctx, surf->base.texture);
2324
2325 p_atomic_inc(&rtex->framebuffers_bound);
2326
2327 if (rtex->dcc_gather_statistics) {
2328 /* Dirty tracking must be enabled for DCC usage analysis. */
2329 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2330 vi_separate_dcc_start_query(ctx, rtex);
2331 }
2332 }
2333 /* Set the second SPI format for possible dual-src blending. */
2334 if (i == 1 && surf) {
2335 sctx->framebuffer.spi_shader_col_format |=
2336 surf->spi_shader_col_format << (i * 4);
2337 sctx->framebuffer.spi_shader_col_format_alpha |=
2338 surf->spi_shader_col_format_alpha << (i * 4);
2339 sctx->framebuffer.spi_shader_col_format_blend |=
2340 surf->spi_shader_col_format_blend << (i * 4);
2341 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2342 surf->spi_shader_col_format_blend_alpha << (i * 4);
2343 }
2344
2345 if (state->zsbuf) {
2346 surf = (struct r600_surface*)state->zsbuf;
2347
2348 if (!surf->depth_initialized) {
2349 si_init_depth_surface(sctx, surf);
2350 }
2351 r600_context_add_resource_size(ctx, surf->base.texture);
2352 }
2353
2354 si_update_poly_offset_state(sctx);
2355 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2356 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
2357
2358 if (sctx->framebuffer.any_dst_linear != old_any_dst_linear)
2359 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2360
2361 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2362 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2363 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2364
2365 /* Set sample locations as fragment shader constants. */
2366 switch (sctx->framebuffer.nr_samples) {
2367 case 1:
2368 constbuf.user_buffer = sctx->b.sample_locations_1x;
2369 break;
2370 case 2:
2371 constbuf.user_buffer = sctx->b.sample_locations_2x;
2372 break;
2373 case 4:
2374 constbuf.user_buffer = sctx->b.sample_locations_4x;
2375 break;
2376 case 8:
2377 constbuf.user_buffer = sctx->b.sample_locations_8x;
2378 break;
2379 case 16:
2380 constbuf.user_buffer = sctx->b.sample_locations_16x;
2381 break;
2382 default:
2383 R600_ERR("Requested an invalid number of samples %i.\n",
2384 sctx->framebuffer.nr_samples);
2385 assert(0);
2386 }
2387 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2388 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
2389
2390 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
2391 }
2392
2393 sctx->need_check_render_feedback = true;
2394 sctx->do_update_shaders = true;
2395 }
2396
2397 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
2398 {
2399 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2400 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2401 unsigned i, nr_cbufs = state->nr_cbufs;
2402 struct r600_texture *tex = NULL;
2403 struct r600_surface *cb = NULL;
2404 unsigned cb_color_info = 0;
2405
2406 /* Colorbuffers. */
2407 for (i = 0; i < nr_cbufs; i++) {
2408 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
2409 unsigned cb_color_base, cb_color_fmask, cb_color_attrib;
2410 unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
2411
2412 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2413 continue;
2414
2415 cb = (struct r600_surface*)state->cbufs[i];
2416 if (!cb) {
2417 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2418 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2419 continue;
2420 }
2421
2422 tex = (struct r600_texture *)cb->base.texture;
2423 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2424 &tex->resource, RADEON_USAGE_READWRITE,
2425 tex->surface.nsamples > 1 ?
2426 RADEON_PRIO_COLOR_BUFFER_MSAA :
2427 RADEON_PRIO_COLOR_BUFFER);
2428
2429 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2430 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2431 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2432 RADEON_PRIO_CMASK);
2433 }
2434
2435 if (tex->dcc_separate_buffer)
2436 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2437 tex->dcc_separate_buffer,
2438 RADEON_USAGE_READWRITE,
2439 RADEON_PRIO_DCC);
2440
2441 /* Compute mutable surface parameters. */
2442 pitch_tile_max = cb->level_info->nblk_x / 8 - 1;
2443 slice_tile_max = cb->level_info->nblk_x *
2444 cb->level_info->nblk_y / 64 - 1;
2445 tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false);
2446
2447 cb_color_base = (tex->resource.gpu_address + cb->level_info->offset) >> 8;
2448 cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
2449 cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
2450 cb_color_attrib = cb->cb_color_attrib |
2451 S_028C74_TILE_MODE_INDEX(tile_mode_index);
2452
2453 if (tex->fmask.size) {
2454 if (sctx->b.chip_class >= CIK)
2455 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->fmask.pitch_in_pixels / 8 - 1);
2456 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->fmask.tile_mode_index);
2457 cb_color_fmask = (tex->resource.gpu_address + tex->fmask.offset) >> 8;
2458 cb_color_fmask_slice = S_028C88_TILE_MAX(tex->fmask.slice_tile_max);
2459 } else {
2460 /* This must be set for fast clear to work without FMASK. */
2461 if (sctx->b.chip_class >= CIK)
2462 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
2463 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
2464 cb_color_fmask = cb_color_base;
2465 cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
2466 }
2467
2468 cb_color_info = cb->cb_color_info | tex->cb_color_info;
2469
2470 if (tex->dcc_offset && cb->level_info->dcc_enabled) {
2471 bool is_msaa_resolve_dst = state->cbufs[0] &&
2472 state->cbufs[0]->texture->nr_samples > 1 &&
2473 state->cbufs[1] == &cb->base &&
2474 state->cbufs[1]->texture->nr_samples <= 1;
2475
2476 if (!is_msaa_resolve_dst)
2477 cb_color_info |= S_028C70_DCC_ENABLE(1);
2478 }
2479
2480 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
2481 sctx->b.chip_class >= VI ? 14 : 13);
2482 radeon_emit(cs, cb_color_base); /* R_028C60_CB_COLOR0_BASE */
2483 radeon_emit(cs, cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
2484 radeon_emit(cs, cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
2485 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
2486 radeon_emit(cs, cb_color_info); /* R_028C70_CB_COLOR0_INFO */
2487 radeon_emit(cs, cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
2488 radeon_emit(cs, cb->cb_dcc_control); /* R_028C78_CB_COLOR0_DCC_CONTROL */
2489 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
2490 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
2491 radeon_emit(cs, cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
2492 radeon_emit(cs, cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
2493 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
2494 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
2495
2496 if (sctx->b.chip_class >= VI) /* R_028C94_CB_COLOR0_DCC_BASE */
2497 radeon_emit(cs, ((!tex->dcc_separate_buffer ? tex->resource.gpu_address : 0) +
2498 tex->dcc_offset +
2499 tex->surface.level[cb->base.u.tex.level].dcc_offset) >> 8);
2500 }
2501 /* set CB_COLOR1_INFO for possible dual-src blending */
2502 if (i == 1 && state->cbufs[0] &&
2503 sctx->framebuffer.dirty_cbufs & (1 << 0)) {
2504 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
2505 cb_color_info);
2506 i++;
2507 }
2508 for (; i < 8 ; i++)
2509 if (sctx->framebuffer.dirty_cbufs & (1 << i))
2510 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
2511
2512 /* ZS buffer. */
2513 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
2514 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
2515 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
2516
2517 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2518 &rtex->resource, RADEON_USAGE_READWRITE,
2519 zb->base.texture->nr_samples > 1 ?
2520 RADEON_PRIO_DEPTH_BUFFER_MSAA :
2521 RADEON_PRIO_DEPTH_BUFFER);
2522
2523 if (zb->db_htile_data_base) {
2524 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2525 rtex->htile_buffer, RADEON_USAGE_READWRITE,
2526 RADEON_PRIO_HTILE);
2527 }
2528
2529 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
2530 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
2531
2532 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
2533 radeon_emit(cs, zb->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
2534 radeon_emit(cs, zb->db_z_info | /* R_028040_DB_Z_INFO */
2535 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
2536 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
2537 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
2538 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
2539 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
2540 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
2541 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
2542 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
2543
2544 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
2545 radeon_emit(cs, rtex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
2546 radeon_emit(cs, fui(rtex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
2547
2548 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
2549 } else if (sctx->framebuffer.dirty_zsbuf) {
2550 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
2551 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
2552 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
2553 }
2554
2555 /* Framebuffer dimensions. */
2556 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2557 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2558 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
2559
2560 sctx->framebuffer.dirty_cbufs = 0;
2561 sctx->framebuffer.dirty_zsbuf = false;
2562 }
2563
2564 static void si_emit_msaa_sample_locs(struct si_context *sctx,
2565 struct r600_atom *atom)
2566 {
2567 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2568 unsigned nr_samples = sctx->framebuffer.nr_samples;
2569
2570 /* Smoothing (only possible with nr_samples == 1) uses the same
2571 * sample locations as the MSAA it simulates.
2572 */
2573 if (nr_samples <= 1 && sctx->smoothing_enabled)
2574 nr_samples = SI_NUM_SMOOTH_AA_SAMPLES;
2575
2576 /* On Polaris, the small primitive filter uses the sample locations
2577 * even when MSAA is off, so we need to make sure they're set to 0.
2578 */
2579 if ((nr_samples > 1 || sctx->b.family >= CHIP_POLARIS10) &&
2580 (nr_samples != sctx->msaa_sample_locs.nr_samples)) {
2581 sctx->msaa_sample_locs.nr_samples = nr_samples;
2582 cayman_emit_msaa_sample_locs(cs, nr_samples);
2583 }
2584
2585 if (sctx->b.family >= CHIP_POLARIS10) {
2586 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
2587 unsigned small_prim_filter_cntl =
2588 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
2589 S_028830_LINE_FILTER_DISABLE(1); /* line bug */
2590
2591 /* The alternative of setting sample locations to 0 would
2592 * require a DB flush to avoid Z errors, see
2593 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
2594 */
2595 if (sctx->framebuffer.nr_samples > 1 && rs && !rs->multisample_enable)
2596 small_prim_filter_cntl &= C_028830_SMALL_PRIM_FILTER_ENABLE;
2597
2598 radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
2599 small_prim_filter_cntl);
2600 }
2601 }
2602
2603 static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom)
2604 {
2605 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2606 unsigned num_tile_pipes = sctx->screen->b.info.num_tile_pipes;
2607 /* 33% faster rendering to linear color buffers */
2608 bool dst_is_linear = sctx->framebuffer.any_dst_linear;
2609 unsigned sc_mode_cntl_1 =
2610 S_028A4C_WALK_SIZE(dst_is_linear) |
2611 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear) |
2612 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
2613 /* always 1: */
2614 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
2615 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
2616 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
2617 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
2618 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
2619 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
2620
2621 cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples,
2622 sctx->ps_iter_samples,
2623 sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0,
2624 sc_mode_cntl_1);
2625 }
2626
2627 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
2628 {
2629 struct si_context *sctx = (struct si_context *)ctx;
2630
2631 if (sctx->ps_iter_samples == min_samples)
2632 return;
2633
2634 sctx->ps_iter_samples = min_samples;
2635 sctx->do_update_shaders = true;
2636
2637 if (sctx->framebuffer.nr_samples > 1)
2638 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2639 }
2640
2641 /*
2642 * Samplers
2643 */
2644
2645 /**
2646 * Build the sampler view descriptor for a buffer texture.
2647 * @param state 256-bit descriptor; only the high 128 bits are filled in
2648 */
2649 void
2650 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
2651 enum pipe_format format,
2652 unsigned first_element, unsigned last_element,
2653 uint32_t *state)
2654 {
2655 const struct util_format_description *desc;
2656 int first_non_void;
2657 uint64_t va;
2658 unsigned stride;
2659 unsigned num_records;
2660 unsigned num_format, data_format;
2661
2662 desc = util_format_description(format);
2663 first_non_void = util_format_get_first_non_void_channel(format);
2664 stride = desc->block.bits / 8;
2665 va = buf->gpu_address + first_element * stride;
2666 num_format = si_translate_buffer_numformat(&screen->b.b, desc, first_non_void);
2667 data_format = si_translate_buffer_dataformat(&screen->b.b, desc, first_non_void);
2668
2669 num_records = last_element + 1 - first_element;
2670 num_records = MIN2(num_records, buf->b.b.width0 / stride);
2671
2672 if (screen->b.chip_class >= VI)
2673 num_records *= stride;
2674
2675 state[4] = va;
2676 state[5] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
2677 S_008F04_STRIDE(stride);
2678 state[6] = num_records;
2679 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2680 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2681 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2682 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2683 S_008F0C_NUM_FORMAT(num_format) |
2684 S_008F0C_DATA_FORMAT(data_format);
2685 }
2686
2687 /**
2688 * Build the sampler view descriptor for a texture.
2689 */
2690 void
2691 si_make_texture_descriptor(struct si_screen *screen,
2692 struct r600_texture *tex,
2693 bool sampler,
2694 enum pipe_texture_target target,
2695 enum pipe_format pipe_format,
2696 const unsigned char state_swizzle[4],
2697 unsigned first_level, unsigned last_level,
2698 unsigned first_layer, unsigned last_layer,
2699 unsigned width, unsigned height, unsigned depth,
2700 uint32_t *state,
2701 uint32_t *fmask_state)
2702 {
2703 struct pipe_resource *res = &tex->resource.b.b;
2704 const struct util_format_description *desc;
2705 unsigned char swizzle[4];
2706 int first_non_void;
2707 unsigned num_format, data_format, type;
2708 uint64_t va;
2709
2710 desc = util_format_description(pipe_format);
2711
2712 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2713 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2714 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2715
2716 switch (pipe_format) {
2717 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2718 case PIPE_FORMAT_X24S8_UINT:
2719 case PIPE_FORMAT_X32_S8X24_UINT:
2720 case PIPE_FORMAT_X8Z24_UNORM:
2721 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
2722 break;
2723 default:
2724 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
2725 }
2726 } else {
2727 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2728 }
2729
2730 first_non_void = util_format_get_first_non_void_channel(pipe_format);
2731
2732 switch (pipe_format) {
2733 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2734 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2735 break;
2736 default:
2737 if (first_non_void < 0) {
2738 if (util_format_is_compressed(pipe_format)) {
2739 switch (pipe_format) {
2740 case PIPE_FORMAT_DXT1_SRGB:
2741 case PIPE_FORMAT_DXT1_SRGBA:
2742 case PIPE_FORMAT_DXT3_SRGBA:
2743 case PIPE_FORMAT_DXT5_SRGBA:
2744 case PIPE_FORMAT_BPTC_SRGBA:
2745 case PIPE_FORMAT_ETC2_SRGB8:
2746 case PIPE_FORMAT_ETC2_SRGB8A1:
2747 case PIPE_FORMAT_ETC2_SRGBA8:
2748 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2749 break;
2750 case PIPE_FORMAT_RGTC1_SNORM:
2751 case PIPE_FORMAT_LATC1_SNORM:
2752 case PIPE_FORMAT_RGTC2_SNORM:
2753 case PIPE_FORMAT_LATC2_SNORM:
2754 case PIPE_FORMAT_ETC2_R11_SNORM:
2755 case PIPE_FORMAT_ETC2_RG11_SNORM:
2756 /* implies float, so use SNORM/UNORM to determine
2757 whether data is signed or not */
2758 case PIPE_FORMAT_BPTC_RGB_FLOAT:
2759 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2760 break;
2761 default:
2762 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2763 break;
2764 }
2765 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
2766 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2767 } else {
2768 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2769 }
2770 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
2771 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2772 } else {
2773 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2774
2775 switch (desc->channel[first_non_void].type) {
2776 case UTIL_FORMAT_TYPE_FLOAT:
2777 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2778 break;
2779 case UTIL_FORMAT_TYPE_SIGNED:
2780 if (desc->channel[first_non_void].normalized)
2781 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2782 else if (desc->channel[first_non_void].pure_integer)
2783 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
2784 else
2785 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
2786 break;
2787 case UTIL_FORMAT_TYPE_UNSIGNED:
2788 if (desc->channel[first_non_void].normalized)
2789 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2790 else if (desc->channel[first_non_void].pure_integer)
2791 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
2792 else
2793 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
2794 }
2795 }
2796 }
2797
2798 data_format = si_translate_texformat(&screen->b.b, pipe_format, desc, first_non_void);
2799 if (data_format == ~0) {
2800 data_format = 0;
2801 }
2802
2803 if (!sampler &&
2804 (res->target == PIPE_TEXTURE_CUBE ||
2805 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
2806 res->target == PIPE_TEXTURE_3D)) {
2807 /* For the purpose of shader images, treat cube maps and 3D
2808 * textures as 2D arrays. For 3D textures, the address
2809 * calculations for mipmaps are different, so we rely on the
2810 * caller to effectively disable mipmaps.
2811 */
2812 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
2813
2814 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
2815 } else {
2816 type = si_tex_dim(res->target, target, res->nr_samples);
2817 }
2818
2819 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
2820 height = 1;
2821 depth = res->array_size;
2822 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
2823 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
2824 if (sampler || res->target != PIPE_TEXTURE_3D)
2825 depth = res->array_size;
2826 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
2827 depth = res->array_size / 6;
2828
2829 state[0] = 0;
2830 state[1] = (S_008F14_DATA_FORMAT(data_format) |
2831 S_008F14_NUM_FORMAT(num_format));
2832 state[2] = (S_008F18_WIDTH(width - 1) |
2833 S_008F18_HEIGHT(height - 1));
2834 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2835 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2836 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2837 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2838 S_008F1C_BASE_LEVEL(res->nr_samples > 1 ?
2839 0 : first_level) |
2840 S_008F1C_LAST_LEVEL(res->nr_samples > 1 ?
2841 util_logbase2(res->nr_samples) :
2842 last_level) |
2843 S_008F1C_POW2_PAD(res->last_level > 0) |
2844 S_008F1C_TYPE(type));
2845 state[4] = S_008F20_DEPTH(depth - 1);
2846 state[5] = (S_008F24_BASE_ARRAY(first_layer) |
2847 S_008F24_LAST_ARRAY(last_layer));
2848 state[6] = 0;
2849 state[7] = 0;
2850
2851 if (tex->dcc_offset) {
2852 unsigned swap = r600_translate_colorswap(pipe_format, false);
2853
2854 state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
2855 } else {
2856 /* The last dword is unused by hw. The shader uses it to clear
2857 * bits in the first dword of sampler state.
2858 */
2859 if (screen->b.chip_class <= CIK && res->nr_samples <= 1) {
2860 if (first_level == last_level)
2861 state[7] = C_008F30_MAX_ANISO_RATIO;
2862 else
2863 state[7] = 0xffffffff;
2864 }
2865 }
2866
2867 /* Initialize the sampler view for FMASK. */
2868 if (tex->fmask.size) {
2869 uint32_t fmask_format;
2870
2871 va = tex->resource.gpu_address + tex->fmask.offset;
2872
2873 switch (res->nr_samples) {
2874 case 2:
2875 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
2876 break;
2877 case 4:
2878 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
2879 break;
2880 case 8:
2881 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
2882 break;
2883 default:
2884 assert(0);
2885 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
2886 }
2887
2888 fmask_state[0] = va >> 8;
2889 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
2890 S_008F14_DATA_FORMAT(fmask_format) |
2891 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT);
2892 fmask_state[2] = S_008F18_WIDTH(width - 1) |
2893 S_008F18_HEIGHT(height - 1);
2894 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
2895 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
2896 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
2897 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
2898 S_008F1C_TILING_INDEX(tex->fmask.tile_mode_index) |
2899 S_008F1C_TYPE(si_tex_dim(res->target, target, 0));
2900 fmask_state[4] = S_008F20_DEPTH(depth - 1) |
2901 S_008F20_PITCH(tex->fmask.pitch_in_pixels - 1);
2902 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer) |
2903 S_008F24_LAST_ARRAY(last_layer);
2904 fmask_state[6] = 0;
2905 fmask_state[7] = 0;
2906 }
2907 }
2908
2909 /**
2910 * Create a sampler view.
2911 *
2912 * @param ctx context
2913 * @param texture texture
2914 * @param state sampler view template
2915 * @param width0 width0 override (for compressed textures as int)
2916 * @param height0 height0 override (for compressed textures as int)
2917 * @param force_level set the base address to the level (for compressed textures)
2918 */
2919 struct pipe_sampler_view *
2920 si_create_sampler_view_custom(struct pipe_context *ctx,
2921 struct pipe_resource *texture,
2922 const struct pipe_sampler_view *state,
2923 unsigned width0, unsigned height0,
2924 unsigned force_level)
2925 {
2926 struct si_context *sctx = (struct si_context*)ctx;
2927 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
2928 struct r600_texture *tmp = (struct r600_texture*)texture;
2929 unsigned base_level, first_level, last_level;
2930 unsigned char state_swizzle[4];
2931 unsigned height, depth, width;
2932 unsigned last_layer = state->u.tex.last_layer;
2933 enum pipe_format pipe_format;
2934 const struct radeon_surf_level *surflevel;
2935
2936 if (!view)
2937 return NULL;
2938
2939 /* initialize base object */
2940 view->base = *state;
2941 view->base.texture = NULL;
2942 view->base.reference.count = 1;
2943 view->base.context = ctx;
2944
2945 /* NULL resource, obey swizzle (only ZERO and ONE make sense). */
2946 if (!texture) {
2947 view->state[3] = S_008F1C_DST_SEL_X(si_map_swizzle(state->swizzle_r)) |
2948 S_008F1C_DST_SEL_Y(si_map_swizzle(state->swizzle_g)) |
2949 S_008F1C_DST_SEL_Z(si_map_swizzle(state->swizzle_b)) |
2950 S_008F1C_DST_SEL_W(si_map_swizzle(state->swizzle_a)) |
2951 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D);
2952 return &view->base;
2953 }
2954
2955 pipe_resource_reference(&view->base.texture, texture);
2956
2957 if (state->format == PIPE_FORMAT_X24S8_UINT ||
2958 state->format == PIPE_FORMAT_S8X24_UINT ||
2959 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
2960 state->format == PIPE_FORMAT_S8_UINT)
2961 view->is_stencil_sampler = true;
2962
2963 /* Buffer resource. */
2964 if (texture->target == PIPE_BUFFER) {
2965 si_make_buffer_descriptor(sctx->screen,
2966 (struct r600_resource *)texture,
2967 state->format,
2968 state->u.buf.first_element,
2969 state->u.buf.last_element,
2970 view->state);
2971
2972 LIST_ADDTAIL(&view->list, &sctx->b.texture_buffers);
2973 return &view->base;
2974 }
2975
2976 state_swizzle[0] = state->swizzle_r;
2977 state_swizzle[1] = state->swizzle_g;
2978 state_swizzle[2] = state->swizzle_b;
2979 state_swizzle[3] = state->swizzle_a;
2980
2981 base_level = 0;
2982 first_level = state->u.tex.first_level;
2983 last_level = state->u.tex.last_level;
2984 width = width0;
2985 height = height0;
2986 depth = texture->depth0;
2987
2988 if (force_level) {
2989 assert(force_level == first_level &&
2990 force_level == last_level);
2991 base_level = force_level;
2992 first_level = 0;
2993 last_level = 0;
2994 width = u_minify(width, force_level);
2995 height = u_minify(height, force_level);
2996 depth = u_minify(depth, force_level);
2997 }
2998
2999 /* This is not needed if state trackers set last_layer correctly. */
3000 if (state->target == PIPE_TEXTURE_1D ||
3001 state->target == PIPE_TEXTURE_2D ||
3002 state->target == PIPE_TEXTURE_RECT ||
3003 state->target == PIPE_TEXTURE_CUBE)
3004 last_layer = state->u.tex.first_layer;
3005
3006 /* Texturing with separate depth and stencil. */
3007 pipe_format = state->format;
3008
3009 /* Depth/stencil texturing sometimes needs separate texture. */
3010 if (tmp->is_depth && !r600_can_sample_zs(tmp, view->is_stencil_sampler)) {
3011 if (!tmp->flushed_depth_texture &&
3012 !r600_init_flushed_depth_texture(ctx, texture, NULL)) {
3013 pipe_resource_reference(&view->base.texture, NULL);
3014 FREE(view);
3015 return NULL;
3016 }
3017
3018 assert(tmp->flushed_depth_texture);
3019
3020 /* Override format for the case where the flushed texture
3021 * contains only Z or only S.
3022 */
3023 if (tmp->flushed_depth_texture->resource.b.b.format != tmp->resource.b.b.format)
3024 pipe_format = tmp->flushed_depth_texture->resource.b.b.format;
3025
3026 tmp = tmp->flushed_depth_texture;
3027 }
3028
3029 surflevel = tmp->surface.level;
3030
3031 if (tmp->db_compatible) {
3032 switch (pipe_format) {
3033 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
3034 pipe_format = PIPE_FORMAT_Z32_FLOAT;
3035 break;
3036 case PIPE_FORMAT_X8Z24_UNORM:
3037 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3038 /* Z24 is always stored like this for DB
3039 * compatibility.
3040 */
3041 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
3042 break;
3043 case PIPE_FORMAT_X24S8_UINT:
3044 case PIPE_FORMAT_S8X24_UINT:
3045 case PIPE_FORMAT_X32_S8X24_UINT:
3046 pipe_format = PIPE_FORMAT_S8_UINT;
3047 surflevel = tmp->surface.stencil_level;
3048 break;
3049 default:;
3050 }
3051 }
3052
3053 si_make_texture_descriptor(sctx->screen, tmp, true,
3054 state->target, pipe_format, state_swizzle,
3055 first_level, last_level,
3056 state->u.tex.first_layer, last_layer,
3057 width, height, depth,
3058 view->state, view->fmask_state);
3059
3060 view->base_level_info = &surflevel[base_level];
3061 view->base_level = base_level;
3062 view->block_width = util_format_get_blockwidth(pipe_format);
3063 return &view->base;
3064 }
3065
3066 static struct pipe_sampler_view *
3067 si_create_sampler_view(struct pipe_context *ctx,
3068 struct pipe_resource *texture,
3069 const struct pipe_sampler_view *state)
3070 {
3071 return si_create_sampler_view_custom(ctx, texture, state,
3072 texture ? texture->width0 : 0,
3073 texture ? texture->height0 : 0, 0);
3074 }
3075
3076 static void si_sampler_view_destroy(struct pipe_context *ctx,
3077 struct pipe_sampler_view *state)
3078 {
3079 struct si_sampler_view *view = (struct si_sampler_view *)state;
3080
3081 if (state->texture && state->texture->target == PIPE_BUFFER)
3082 LIST_DELINIT(&view->list);
3083
3084 pipe_resource_reference(&state->texture, NULL);
3085 FREE(view);
3086 }
3087
3088 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
3089 {
3090 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
3091 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
3092 (linear_filter &&
3093 (wrap == PIPE_TEX_WRAP_CLAMP ||
3094 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
3095 }
3096
3097 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
3098 {
3099 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
3100 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
3101
3102 return (state->border_color.ui[0] || state->border_color.ui[1] ||
3103 state->border_color.ui[2] || state->border_color.ui[3]) &&
3104 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
3105 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
3106 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
3107 }
3108
3109 static void *si_create_sampler_state(struct pipe_context *ctx,
3110 const struct pipe_sampler_state *state)
3111 {
3112 struct si_context *sctx = (struct si_context *)ctx;
3113 struct r600_common_screen *rscreen = sctx->b.screen;
3114 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
3115 unsigned border_color_type, border_color_index = 0;
3116 unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
3117 : state->max_anisotropy;
3118 unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso);
3119
3120 if (!rstate) {
3121 return NULL;
3122 }
3123
3124 if (!sampler_state_needs_border_color(state))
3125 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3126 else if (state->border_color.f[0] == 0 &&
3127 state->border_color.f[1] == 0 &&
3128 state->border_color.f[2] == 0 &&
3129 state->border_color.f[3] == 0)
3130 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3131 else if (state->border_color.f[0] == 0 &&
3132 state->border_color.f[1] == 0 &&
3133 state->border_color.f[2] == 0 &&
3134 state->border_color.f[3] == 1)
3135 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3136 else if (state->border_color.f[0] == 1 &&
3137 state->border_color.f[1] == 1 &&
3138 state->border_color.f[2] == 1 &&
3139 state->border_color.f[3] == 1)
3140 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3141 else {
3142 int i;
3143
3144 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
3145
3146 /* Check if the border has been uploaded already. */
3147 for (i = 0; i < sctx->border_color_count; i++)
3148 if (memcmp(&sctx->border_color_table[i], &state->border_color,
3149 sizeof(state->border_color)) == 0)
3150 break;
3151
3152 if (i >= SI_MAX_BORDER_COLORS) {
3153 /* Getting 4096 unique border colors is very unlikely. */
3154 fprintf(stderr, "radeonsi: The border color table is full. "
3155 "Any new border colors will be just black. "
3156 "Please file a bug.\n");
3157 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3158 } else {
3159 if (i == sctx->border_color_count) {
3160 /* Upload a new border color. */
3161 memcpy(&sctx->border_color_table[i], &state->border_color,
3162 sizeof(state->border_color));
3163 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
3164 &state->border_color,
3165 sizeof(state->border_color));
3166 sctx->border_color_count++;
3167 }
3168
3169 border_color_index = i;
3170 }
3171 }
3172
3173 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
3174 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
3175 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
3176 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3177 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
3178 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
3179 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
3180 S_008F30_COMPAT_MODE(sctx->b.chip_class >= VI));
3181 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
3182 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
3183 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
3184 S_008F38_XY_MAG_FILTER(eg_tex_filter(state->mag_img_filter, max_aniso)) |
3185 S_008F38_XY_MIN_FILTER(eg_tex_filter(state->min_img_filter, max_aniso)) |
3186 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
3187 S_008F38_MIP_POINT_PRECLAMP(1) |
3188 S_008F38_DISABLE_LSB_CEIL(1) |
3189 S_008F38_FILTER_PREC_FIX(1) |
3190 S_008F38_ANISO_OVERRIDE(sctx->b.chip_class >= VI));
3191 rstate->val[3] = S_008F3C_BORDER_COLOR_PTR(border_color_index) |
3192 S_008F3C_BORDER_COLOR_TYPE(border_color_type);
3193 return rstate;
3194 }
3195
3196 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
3197 {
3198 struct si_context *sctx = (struct si_context *)ctx;
3199
3200 if (sctx->sample_mask.sample_mask == (uint16_t)sample_mask)
3201 return;
3202
3203 sctx->sample_mask.sample_mask = sample_mask;
3204 si_mark_atom_dirty(sctx, &sctx->sample_mask.atom);
3205 }
3206
3207 static void si_emit_sample_mask(struct si_context *sctx, struct r600_atom *atom)
3208 {
3209 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
3210 unsigned mask = sctx->sample_mask.sample_mask;
3211
3212 /* Needed for line and polygon smoothing as well as for the Polaris
3213 * small primitive filter. We expect the state tracker to take care of
3214 * this for us.
3215 */
3216 assert(mask == 0xffff || sctx->framebuffer.nr_samples > 1 ||
3217 (mask & 1 && sctx->blitter->running));
3218
3219 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3220 radeon_emit(cs, mask | (mask << 16));
3221 radeon_emit(cs, mask | (mask << 16));
3222 }
3223
3224 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
3225 {
3226 free(state);
3227 }
3228
3229 /*
3230 * Vertex elements & buffers
3231 */
3232
3233 static void *si_create_vertex_elements(struct pipe_context *ctx,
3234 unsigned count,
3235 const struct pipe_vertex_element *elements)
3236 {
3237 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
3238 int i;
3239
3240 assert(count <= SI_MAX_ATTRIBS);
3241 if (!v)
3242 return NULL;
3243
3244 v->count = count;
3245 for (i = 0; i < count; ++i) {
3246 const struct util_format_description *desc;
3247 unsigned data_format, num_format;
3248 int first_non_void;
3249
3250 desc = util_format_description(elements[i].src_format);
3251 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
3252 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
3253 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
3254
3255 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3256 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3257 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3258 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
3259 S_008F0C_NUM_FORMAT(num_format) |
3260 S_008F0C_DATA_FORMAT(data_format);
3261 v->format_size[i] = desc->block.bits / 8;
3262 }
3263 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
3264
3265 return v;
3266 }
3267
3268 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
3269 {
3270 struct si_context *sctx = (struct si_context *)ctx;
3271 struct si_vertex_element *v = (struct si_vertex_element*)state;
3272
3273 sctx->vertex_elements = v;
3274 sctx->vertex_buffers_dirty = true;
3275 sctx->do_update_shaders = true;
3276 }
3277
3278 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
3279 {
3280 struct si_context *sctx = (struct si_context *)ctx;
3281
3282 if (sctx->vertex_elements == state)
3283 sctx->vertex_elements = NULL;
3284 FREE(state);
3285 }
3286
3287 static void si_set_vertex_buffers(struct pipe_context *ctx,
3288 unsigned start_slot, unsigned count,
3289 const struct pipe_vertex_buffer *buffers)
3290 {
3291 struct si_context *sctx = (struct si_context *)ctx;
3292 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
3293 int i;
3294
3295 assert(start_slot + count <= ARRAY_SIZE(sctx->vertex_buffer));
3296
3297 if (buffers) {
3298 for (i = 0; i < count; i++) {
3299 const struct pipe_vertex_buffer *src = buffers + i;
3300 struct pipe_vertex_buffer *dsti = dst + i;
3301
3302 pipe_resource_reference(&dsti->buffer, src->buffer);
3303 dsti->buffer_offset = src->buffer_offset;
3304 dsti->stride = src->stride;
3305 r600_context_add_resource_size(ctx, src->buffer);
3306 }
3307 } else {
3308 for (i = 0; i < count; i++) {
3309 pipe_resource_reference(&dst[i].buffer, NULL);
3310 }
3311 }
3312 sctx->vertex_buffers_dirty = true;
3313 }
3314
3315 static void si_set_index_buffer(struct pipe_context *ctx,
3316 const struct pipe_index_buffer *ib)
3317 {
3318 struct si_context *sctx = (struct si_context *)ctx;
3319
3320 if (ib) {
3321 pipe_resource_reference(&sctx->index_buffer.buffer, ib->buffer);
3322 memcpy(&sctx->index_buffer, ib, sizeof(*ib));
3323 r600_context_add_resource_size(ctx, ib->buffer);
3324 } else {
3325 pipe_resource_reference(&sctx->index_buffer.buffer, NULL);
3326 }
3327 }
3328
3329 /*
3330 * Misc
3331 */
3332
3333 static void si_set_tess_state(struct pipe_context *ctx,
3334 const float default_outer_level[4],
3335 const float default_inner_level[2])
3336 {
3337 struct si_context *sctx = (struct si_context *)ctx;
3338 struct pipe_constant_buffer cb;
3339 float array[8];
3340
3341 memcpy(array, default_outer_level, sizeof(float) * 4);
3342 memcpy(array+4, default_inner_level, sizeof(float) * 2);
3343
3344 cb.buffer = NULL;
3345 cb.user_buffer = NULL;
3346 cb.buffer_size = sizeof(array);
3347
3348 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
3349 (void*)array, sizeof(array),
3350 &cb.buffer_offset);
3351
3352 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
3353 pipe_resource_reference(&cb.buffer, NULL);
3354 }
3355
3356 static void si_texture_barrier(struct pipe_context *ctx)
3357 {
3358 struct si_context *sctx = (struct si_context *)ctx;
3359
3360 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
3361 SI_CONTEXT_INV_GLOBAL_L2 |
3362 SI_CONTEXT_FLUSH_AND_INV_CB |
3363 SI_CONTEXT_CS_PARTIAL_FLUSH;
3364 }
3365
3366 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
3367 {
3368 struct si_context *sctx = (struct si_context *)ctx;
3369
3370 /* Subsequent commands must wait for all shader invocations to
3371 * complete. */
3372 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
3373 SI_CONTEXT_CS_PARTIAL_FLUSH;
3374
3375 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
3376 sctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 |
3377 SI_CONTEXT_INV_VMEM_L1;
3378
3379 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
3380 PIPE_BARRIER_SHADER_BUFFER |
3381 PIPE_BARRIER_TEXTURE |
3382 PIPE_BARRIER_IMAGE |
3383 PIPE_BARRIER_STREAMOUT_BUFFER |
3384 PIPE_BARRIER_GLOBAL_BUFFER)) {
3385 /* As far as I can tell, L1 contents are written back to L2
3386 * automatically at end of shader, but the contents of other
3387 * L1 caches might still be stale. */
3388 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
3389 }
3390
3391 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
3392 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
3393
3394 /* Indices are read through TC L2 since VI. */
3395 if (sctx->screen->b.chip_class <= CIK)
3396 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
3397 }
3398
3399 if (flags & PIPE_BARRIER_FRAMEBUFFER)
3400 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER;
3401
3402 if (flags & (PIPE_BARRIER_MAPPED_BUFFER |
3403 PIPE_BARRIER_FRAMEBUFFER |
3404 PIPE_BARRIER_INDIRECT_BUFFER)) {
3405 /* Not sure if INV_GLOBAL_L2 is the best thing here.
3406 *
3407 * We need to make sure that TC L1 & L2 are written back to
3408 * memory, because neither CPU accesses nor CB fetches consider
3409 * TC, but there's no need to invalidate any TC cache lines. */
3410 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
3411 }
3412 }
3413
3414 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
3415 {
3416 struct pipe_blend_state blend;
3417
3418 memset(&blend, 0, sizeof(blend));
3419 blend.independent_blend_enable = true;
3420 blend.rt[0].colormask = 0xf;
3421 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
3422 }
3423
3424 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
3425 bool include_draw_vbo)
3426 {
3427 si_need_cs_space((struct si_context*)ctx);
3428 }
3429
3430 static void si_init_config(struct si_context *sctx);
3431
3432 void si_init_state_functions(struct si_context *sctx)
3433 {
3434 si_init_external_atom(sctx, &sctx->b.render_cond_atom, &sctx->atoms.s.render_cond);
3435 si_init_external_atom(sctx, &sctx->b.streamout.begin_atom, &sctx->atoms.s.streamout_begin);
3436 si_init_external_atom(sctx, &sctx->b.streamout.enable_atom, &sctx->atoms.s.streamout_enable);
3437 si_init_external_atom(sctx, &sctx->b.scissors.atom, &sctx->atoms.s.scissors);
3438 si_init_external_atom(sctx, &sctx->b.viewports.atom, &sctx->atoms.s.viewports);
3439
3440 si_init_atom(sctx, &sctx->cache_flush, &sctx->atoms.s.cache_flush, si_emit_cache_flush);
3441 si_init_atom(sctx, &sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state);
3442 si_init_atom(sctx, &sctx->msaa_sample_locs.atom, &sctx->atoms.s.msaa_sample_locs, si_emit_msaa_sample_locs);
3443 si_init_atom(sctx, &sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state);
3444 si_init_atom(sctx, &sctx->msaa_config, &sctx->atoms.s.msaa_config, si_emit_msaa_config);
3445 si_init_atom(sctx, &sctx->sample_mask.atom, &sctx->atoms.s.sample_mask, si_emit_sample_mask);
3446 si_init_atom(sctx, &sctx->cb_render_state, &sctx->atoms.s.cb_render_state, si_emit_cb_render_state);
3447 si_init_atom(sctx, &sctx->blend_color.atom, &sctx->atoms.s.blend_color, si_emit_blend_color);
3448 si_init_atom(sctx, &sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs);
3449 si_init_atom(sctx, &sctx->clip_state.atom, &sctx->atoms.s.clip_state, si_emit_clip_state);
3450 si_init_atom(sctx, &sctx->stencil_ref.atom, &sctx->atoms.s.stencil_ref, si_emit_stencil_ref);
3451
3452 sctx->b.b.create_blend_state = si_create_blend_state;
3453 sctx->b.b.bind_blend_state = si_bind_blend_state;
3454 sctx->b.b.delete_blend_state = si_delete_blend_state;
3455 sctx->b.b.set_blend_color = si_set_blend_color;
3456
3457 sctx->b.b.create_rasterizer_state = si_create_rs_state;
3458 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
3459 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
3460
3461 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
3462 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
3463 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
3464
3465 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
3466 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
3467 sctx->custom_blend_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
3468 sctx->custom_blend_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
3469 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
3470
3471 sctx->b.b.set_clip_state = si_set_clip_state;
3472 sctx->b.b.set_stencil_ref = si_set_stencil_ref;
3473
3474 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
3475 sctx->b.b.get_sample_position = cayman_get_sample_position;
3476
3477 sctx->b.b.create_sampler_state = si_create_sampler_state;
3478 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
3479
3480 sctx->b.b.create_sampler_view = si_create_sampler_view;
3481 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
3482
3483 sctx->b.b.set_sample_mask = si_set_sample_mask;
3484
3485 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
3486 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
3487 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
3488 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
3489 sctx->b.b.set_index_buffer = si_set_index_buffer;
3490
3491 sctx->b.b.texture_barrier = si_texture_barrier;
3492 sctx->b.b.memory_barrier = si_memory_barrier;
3493 sctx->b.b.set_min_samples = si_set_min_samples;
3494 sctx->b.b.set_tess_state = si_set_tess_state;
3495
3496 sctx->b.b.set_active_query_state = si_set_active_query_state;
3497 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
3498 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
3499
3500 sctx->b.b.draw_vbo = si_draw_vbo;
3501
3502 si_init_config(sctx);
3503 }
3504
3505 static uint32_t si_get_bo_metadata_word1(struct r600_common_screen *rscreen)
3506 {
3507 return (ATI_VENDOR_ID << 16) | rscreen->info.pci_id;
3508 }
3509
3510 static void si_query_opaque_metadata(struct r600_common_screen *rscreen,
3511 struct r600_texture *rtex,
3512 struct radeon_bo_metadata *md)
3513 {
3514 struct si_screen *sscreen = (struct si_screen*)rscreen;
3515 struct pipe_resource *res = &rtex->resource.b.b;
3516 static const unsigned char swizzle[] = {
3517 PIPE_SWIZZLE_X,
3518 PIPE_SWIZZLE_Y,
3519 PIPE_SWIZZLE_Z,
3520 PIPE_SWIZZLE_W
3521 };
3522 uint32_t desc[8], i;
3523 bool is_array = util_resource_is_array_texture(res);
3524
3525 /* DRM 2.x.x doesn't support this. */
3526 if (rscreen->info.drm_major != 3)
3527 return;
3528
3529 assert(rtex->dcc_separate_buffer == NULL);
3530 assert(rtex->fmask.size == 0);
3531
3532 /* Metadata image format format version 1:
3533 * [0] = 1 (metadata format identifier)
3534 * [1] = (VENDOR_ID << 16) | PCI_ID
3535 * [2:9] = image descriptor for the whole resource
3536 * [2] is always 0, because the base address is cleared
3537 * [9] is the DCC offset bits [39:8] from the beginning of
3538 * the buffer
3539 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
3540 */
3541
3542 md->metadata[0] = 1; /* metadata image format version 1 */
3543
3544 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
3545 md->metadata[1] = si_get_bo_metadata_word1(rscreen);
3546
3547 si_make_texture_descriptor(sscreen, rtex, true,
3548 res->target, res->format,
3549 swizzle, 0, res->last_level, 0,
3550 is_array ? res->array_size - 1 : 0,
3551 res->width0, res->height0, res->depth0,
3552 desc, NULL);
3553
3554 si_set_mutable_tex_desc_fields(rtex, &rtex->surface.level[0], 0, 0,
3555 rtex->surface.blk_w, false, desc);
3556
3557 /* Clear the base address and set the relative DCC offset. */
3558 desc[0] = 0;
3559 desc[1] &= C_008F14_BASE_ADDRESS_HI;
3560 desc[7] = rtex->dcc_offset >> 8;
3561
3562 /* Dwords [2:9] contain the image descriptor. */
3563 memcpy(&md->metadata[2], desc, sizeof(desc));
3564
3565 /* Dwords [10:..] contain the mipmap level offsets. */
3566 for (i = 0; i <= res->last_level; i++)
3567 md->metadata[10+i] = rtex->surface.level[i].offset >> 8;
3568
3569 md->size_metadata = (11 + res->last_level) * 4;
3570 }
3571
3572 static void si_apply_opaque_metadata(struct r600_common_screen *rscreen,
3573 struct r600_texture *rtex,
3574 struct radeon_bo_metadata *md)
3575 {
3576 uint32_t *desc = &md->metadata[2];
3577
3578 if (rscreen->chip_class < VI)
3579 return;
3580
3581 /* Return if DCC is enabled. The texture should be set up with it
3582 * already.
3583 */
3584 if (md->size_metadata >= 11 * 4 &&
3585 md->metadata[0] != 0 &&
3586 md->metadata[1] == si_get_bo_metadata_word1(rscreen) &&
3587 G_008F28_COMPRESSION_EN(desc[6])) {
3588 assert(rtex->dcc_offset == ((uint64_t)desc[7] << 8));
3589 return;
3590 }
3591
3592 /* Disable DCC. These are always set by texture_from_handle and must
3593 * be cleared here.
3594 */
3595 rtex->dcc_offset = 0;
3596 }
3597
3598 void si_init_screen_state_functions(struct si_screen *sscreen)
3599 {
3600 sscreen->b.b.is_format_supported = si_is_format_supported;
3601 sscreen->b.query_opaque_metadata = si_query_opaque_metadata;
3602 sscreen->b.apply_opaque_metadata = si_apply_opaque_metadata;
3603 }
3604
3605 static void
3606 si_write_harvested_raster_configs(struct si_context *sctx,
3607 struct si_pm4_state *pm4,
3608 unsigned raster_config,
3609 unsigned raster_config_1)
3610 {
3611 unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1);
3612 unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1);
3613 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
3614 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
3615 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
3616 unsigned rb_per_se = num_rb / num_se;
3617 unsigned se_mask[4];
3618 unsigned se;
3619
3620 se_mask[0] = ((1 << rb_per_se) - 1);
3621 se_mask[1] = (se_mask[0] << rb_per_se);
3622 se_mask[2] = (se_mask[1] << rb_per_se);
3623 se_mask[3] = (se_mask[2] << rb_per_se);
3624
3625 se_mask[0] &= rb_mask;
3626 se_mask[1] &= rb_mask;
3627 se_mask[2] &= rb_mask;
3628 se_mask[3] &= rb_mask;
3629
3630 assert(num_se == 1 || num_se == 2 || num_se == 4);
3631 assert(sh_per_se == 1 || sh_per_se == 2);
3632 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
3633
3634 /* XXX: I can't figure out what the *_XSEL and *_YSEL
3635 * fields are for, so I'm leaving them as their default
3636 * values. */
3637
3638 for (se = 0; se < num_se; se++) {
3639 unsigned raster_config_se = raster_config;
3640 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
3641 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
3642 int idx = (se / 2) * 2;
3643
3644 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
3645 raster_config_se &= C_028350_SE_MAP;
3646
3647 if (!se_mask[idx]) {
3648 raster_config_se |=
3649 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
3650 } else {
3651 raster_config_se |=
3652 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
3653 }
3654 }
3655
3656 pkr0_mask &= rb_mask;
3657 pkr1_mask &= rb_mask;
3658 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
3659 raster_config_se &= C_028350_PKR_MAP;
3660
3661 if (!pkr0_mask) {
3662 raster_config_se |=
3663 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
3664 } else {
3665 raster_config_se |=
3666 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
3667 }
3668 }
3669
3670 if (rb_per_se >= 2) {
3671 unsigned rb0_mask = 1 << (se * rb_per_se);
3672 unsigned rb1_mask = rb0_mask << 1;
3673
3674 rb0_mask &= rb_mask;
3675 rb1_mask &= rb_mask;
3676 if (!rb0_mask || !rb1_mask) {
3677 raster_config_se &= C_028350_RB_MAP_PKR0;
3678
3679 if (!rb0_mask) {
3680 raster_config_se |=
3681 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
3682 } else {
3683 raster_config_se |=
3684 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
3685 }
3686 }
3687
3688 if (rb_per_se > 2) {
3689 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
3690 rb1_mask = rb0_mask << 1;
3691 rb0_mask &= rb_mask;
3692 rb1_mask &= rb_mask;
3693 if (!rb0_mask || !rb1_mask) {
3694 raster_config_se &= C_028350_RB_MAP_PKR1;
3695
3696 if (!rb0_mask) {
3697 raster_config_se |=
3698 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
3699 } else {
3700 raster_config_se |=
3701 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
3702 }
3703 }
3704 }
3705 }
3706
3707 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
3708 if (sctx->b.chip_class < CIK)
3709 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3710 SE_INDEX(se) | SH_BROADCAST_WRITES |
3711 INSTANCE_BROADCAST_WRITES);
3712 else
3713 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
3714 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
3715 S_030800_INSTANCE_BROADCAST_WRITES(1));
3716 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
3717 }
3718
3719 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
3720 if (sctx->b.chip_class < CIK)
3721 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3722 SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
3723 INSTANCE_BROADCAST_WRITES);
3724 else {
3725 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
3726 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
3727 S_030800_INSTANCE_BROADCAST_WRITES(1));
3728
3729 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
3730 (!se_mask[2] && !se_mask[3]))) {
3731 raster_config_1 &= C_028354_SE_PAIR_MAP;
3732
3733 if (!se_mask[0] && !se_mask[1]) {
3734 raster_config_1 |=
3735 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
3736 } else {
3737 raster_config_1 |=
3738 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
3739 }
3740 }
3741
3742 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
3743 }
3744 }
3745
3746 static void si_init_config(struct si_context *sctx)
3747 {
3748 struct si_screen *sscreen = sctx->screen;
3749 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
3750 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
3751 unsigned raster_config, raster_config_1;
3752 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
3753 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3754 int i;
3755
3756 if (!pm4)
3757 return;
3758
3759 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
3760 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
3761 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
3762 si_pm4_cmd_end(pm4, false);
3763
3764 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
3765 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
3766
3767 /* FIXME calculate these values somehow ??? */
3768 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
3769 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
3770 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
3771
3772 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
3773 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3774
3775 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
3776 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
3777 if (sctx->b.chip_class < CIK)
3778 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
3779 S_008A14_CLIP_VTX_REORDER_ENA(1));
3780
3781 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
3782 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
3783
3784 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
3785
3786 for (i = 0; i < 16; i++) {
3787 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0);
3788 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0));
3789 }
3790
3791 switch (sctx->screen->b.family) {
3792 case CHIP_TAHITI:
3793 case CHIP_PITCAIRN:
3794 raster_config = 0x2a00126a;
3795 raster_config_1 = 0x00000000;
3796 break;
3797 case CHIP_VERDE:
3798 raster_config = 0x0000124a;
3799 raster_config_1 = 0x00000000;
3800 break;
3801 case CHIP_OLAND:
3802 raster_config = 0x00000082;
3803 raster_config_1 = 0x00000000;
3804 break;
3805 case CHIP_HAINAN:
3806 raster_config = 0x00000000;
3807 raster_config_1 = 0x00000000;
3808 break;
3809 case CHIP_BONAIRE:
3810 raster_config = 0x16000012;
3811 raster_config_1 = 0x00000000;
3812 break;
3813 case CHIP_HAWAII:
3814 raster_config = 0x3a00161a;
3815 raster_config_1 = 0x0000002e;
3816 break;
3817 case CHIP_FIJI:
3818 if (sscreen->b.info.cik_macrotile_mode_array[0] == 0x000000e8) {
3819 /* old kernels with old tiling config */
3820 raster_config = 0x16000012;
3821 raster_config_1 = 0x0000002a;
3822 } else {
3823 raster_config = 0x3a00161a;
3824 raster_config_1 = 0x0000002e;
3825 }
3826 break;
3827 case CHIP_POLARIS10:
3828 raster_config = 0x16000012;
3829 raster_config_1 = 0x0000002a;
3830 break;
3831 case CHIP_POLARIS11:
3832 raster_config = 0x16000012;
3833 raster_config_1 = 0x00000000;
3834 break;
3835 case CHIP_TONGA:
3836 raster_config = 0x16000012;
3837 raster_config_1 = 0x0000002a;
3838 break;
3839 case CHIP_ICELAND:
3840 if (num_rb == 1)
3841 raster_config = 0x00000000;
3842 else
3843 raster_config = 0x00000002;
3844 raster_config_1 = 0x00000000;
3845 break;
3846 case CHIP_CARRIZO:
3847 raster_config = 0x00000002;
3848 raster_config_1 = 0x00000000;
3849 break;
3850 case CHIP_KAVERI:
3851 /* KV should be 0x00000002, but that causes problems with radeon */
3852 raster_config = 0x00000000; /* 0x00000002 */
3853 raster_config_1 = 0x00000000;
3854 break;
3855 case CHIP_KABINI:
3856 case CHIP_MULLINS:
3857 case CHIP_STONEY:
3858 raster_config = 0x00000000;
3859 raster_config_1 = 0x00000000;
3860 break;
3861 default:
3862 fprintf(stderr,
3863 "radeonsi: Unknown GPU, using 0 for raster_config\n");
3864 raster_config = 0x00000000;
3865 raster_config_1 = 0x00000000;
3866 break;
3867 }
3868
3869 /* Always use the default config when all backends are enabled
3870 * (or when we failed to determine the enabled backends).
3871 */
3872 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
3873 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
3874 raster_config);
3875 if (sctx->b.chip_class >= CIK)
3876 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
3877 raster_config_1);
3878 } else {
3879 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
3880 }
3881
3882 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
3883 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
3884 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
3885 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
3886 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
3887 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
3888 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
3889
3890 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
3891 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
3892 S_028230_ER_TRI(0xA) |
3893 S_028230_ER_POINT(0xA) |
3894 S_028230_ER_RECT(0xA) |
3895 /* Required by DX10_DIAMOND_TEST_ENA: */
3896 S_028230_ER_LINE_LR(0x1A) |
3897 S_028230_ER_LINE_RL(0x26) |
3898 S_028230_ER_LINE_TB(0xA) |
3899 S_028230_ER_LINE_BT(0xA));
3900 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
3901 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
3902 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
3903 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
3904 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
3905 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
3906 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE,
3907 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3908 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
3909
3910 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
3911 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
3912 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
3913
3914 if (sctx->b.chip_class >= CIK) {
3915 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff));
3916 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
3917 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xffff));
3918 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
3919
3920 if (sscreen->b.info.num_good_compute_units /
3921 (sscreen->b.info.max_se * sscreen->b.info.max_sh_per_se) <= 4) {
3922 /* Too few available compute units per SH. Disallowing
3923 * VS to run on CU0 could hurt us more than late VS
3924 * allocation would help.
3925 *
3926 * LATE_ALLOC_VS = 2 is the highest safe number.
3927 */
3928 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
3929 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
3930 } else {
3931 /* Set LATE_ALLOC_VS == 31. It should be less than
3932 * the number of scratch waves. Limitations:
3933 * - VS can't execute on CU0.
3934 * - If HS writes outputs to LDS, LS can't execute on CU0.
3935 */
3936 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xfffe));
3937 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
3938 }
3939
3940 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
3941 }
3942
3943 if (sctx->b.chip_class >= VI) {
3944 unsigned vgt_tess_distribution;
3945
3946 si_pm4_set_reg(pm4, R_028424_CB_DCC_CONTROL,
3947 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
3948 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
3949 if (sctx->b.family < CHIP_POLARIS10)
3950 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
3951 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
3952
3953 vgt_tess_distribution =
3954 S_028B50_ACCUM_ISOLINE(32) |
3955 S_028B50_ACCUM_TRI(11) |
3956 S_028B50_ACCUM_QUAD(11) |
3957 S_028B50_DONUT_SPLIT(16);
3958
3959 /* Testing with Unigine Heaven extreme tesselation yielded best results
3960 * with TRAP_SPLIT = 3.
3961 */
3962 if (sctx->b.family == CHIP_FIJI ||
3963 sctx->b.family >= CHIP_POLARIS10)
3964 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
3965
3966 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution);
3967 } else {
3968 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
3969 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
3970 }
3971
3972 if (sctx->b.family == CHIP_STONEY)
3973 si_pm4_set_reg(pm4, R_028C40_PA_SC_SHADER_CONTROL, 0);
3974
3975 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
3976 if (sctx->b.chip_class >= CIK)
3977 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, border_color_va >> 40);
3978 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
3979 RADEON_PRIO_BORDER_COLORS);
3980
3981 si_pm4_upload_indirect_buffer(sctx, pm4);
3982 sctx->init_config = pm4;
3983 }