2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Christian König <christian.koenig@amd.com>
28 #include "si_shader.h"
30 #include "../radeon/r600_cs.h"
32 #include "tgsi/tgsi_parse.h"
33 #include "tgsi/tgsi_scan.h"
34 #include "util/u_format.h"
35 #include "util/u_format_s3tc.h"
36 #include "util/u_framebuffer.h"
37 #include "util/u_helpers.h"
38 #include "util/u_memory.h"
40 static uint32_t cik_num_banks(struct si_screen
*sscreen
, unsigned bpe
, unsigned tile_split
)
42 if (sscreen
->b
.info
.cik_macrotile_mode_array_valid
) {
43 unsigned index
, tileb
;
46 tileb
= MIN2(tile_split
, tileb
);
48 for (index
= 0; tileb
> 64; index
++) {
54 return (sscreen
->b
.info
.cik_macrotile_mode_array
[index
] >> 6) & 0x3;
58 switch (sscreen
->b
.tiling_info
.num_banks
) {
60 return V_02803C_ADDR_SURF_2_BANK
;
62 return V_02803C_ADDR_SURF_4_BANK
;
65 return V_02803C_ADDR_SURF_8_BANK
;
67 return V_02803C_ADDR_SURF_16_BANK
;
71 static unsigned cik_tile_split(unsigned tile_split
)
75 tile_split
= V_028040_ADDR_SURF_TILE_SPLIT_64B
;
78 tile_split
= V_028040_ADDR_SURF_TILE_SPLIT_128B
;
81 tile_split
= V_028040_ADDR_SURF_TILE_SPLIT_256B
;
84 tile_split
= V_028040_ADDR_SURF_TILE_SPLIT_512B
;
88 tile_split
= V_028040_ADDR_SURF_TILE_SPLIT_1KB
;
91 tile_split
= V_028040_ADDR_SURF_TILE_SPLIT_2KB
;
94 tile_split
= V_028040_ADDR_SURF_TILE_SPLIT_4KB
;
100 static unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect
)
102 switch (macro_tile_aspect
) {
105 macro_tile_aspect
= V_02803C_ADDR_SURF_MACRO_ASPECT_1
;
108 macro_tile_aspect
= V_02803C_ADDR_SURF_MACRO_ASPECT_2
;
111 macro_tile_aspect
= V_02803C_ADDR_SURF_MACRO_ASPECT_4
;
114 macro_tile_aspect
= V_02803C_ADDR_SURF_MACRO_ASPECT_8
;
117 return macro_tile_aspect
;
120 static unsigned cik_bank_wh(unsigned bankwh
)
125 bankwh
= V_02803C_ADDR_SURF_BANK_WIDTH_1
;
128 bankwh
= V_02803C_ADDR_SURF_BANK_WIDTH_2
;
131 bankwh
= V_02803C_ADDR_SURF_BANK_WIDTH_4
;
134 bankwh
= V_02803C_ADDR_SURF_BANK_WIDTH_8
;
140 static unsigned cik_db_pipe_config(struct si_screen
*sscreen
, unsigned tile_mode
)
142 if (sscreen
->b
.info
.si_tile_mode_array_valid
) {
143 uint32_t gb_tile_mode
= sscreen
->b
.info
.si_tile_mode_array
[tile_mode
];
145 return G_009910_PIPE_CONFIG(gb_tile_mode
);
148 /* This is probably broken for a lot of chips, but it's only used
149 * if the kernel cannot return the tile mode array for CIK. */
150 switch (sscreen
->b
.info
.r600_num_tile_pipes
) {
152 return V_02803C_X_ADDR_SURF_P16_32X32_16X16
;
154 return V_02803C_X_ADDR_SURF_P8_32X32_16X16
;
157 if (sscreen
->b
.info
.r600_num_backends
== 4)
158 return V_02803C_X_ADDR_SURF_P4_16X16
;
160 return V_02803C_X_ADDR_SURF_P4_8X16
;
162 return V_02803C_ADDR_SURF_P2
;
166 static unsigned si_map_swizzle(unsigned swizzle
)
169 case UTIL_FORMAT_SWIZZLE_Y
:
170 return V_008F0C_SQ_SEL_Y
;
171 case UTIL_FORMAT_SWIZZLE_Z
:
172 return V_008F0C_SQ_SEL_Z
;
173 case UTIL_FORMAT_SWIZZLE_W
:
174 return V_008F0C_SQ_SEL_W
;
175 case UTIL_FORMAT_SWIZZLE_0
:
176 return V_008F0C_SQ_SEL_0
;
177 case UTIL_FORMAT_SWIZZLE_1
:
178 return V_008F0C_SQ_SEL_1
;
179 default: /* UTIL_FORMAT_SWIZZLE_X */
180 return V_008F0C_SQ_SEL_X
;
184 static uint32_t S_FIXED(float value
, uint32_t frac_bits
)
186 return value
* (1 << frac_bits
);
189 /* 12.4 fixed-point */
190 static unsigned si_pack_float_12p4(float x
)
193 x
>= 4096 ? 0xffff : x
* 16;
197 * inferred framebuffer and blender state
199 static void si_update_fb_blend_state(struct si_context
*sctx
)
201 struct si_pm4_state
*pm4
;
202 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
208 pm4
= si_pm4_alloc_state(sctx
);
212 mask
= (1ULL << ((unsigned)sctx
->framebuffer
.nr_cbufs
* 4)) - 1;
213 mask
&= blend
->cb_target_mask
;
214 si_pm4_set_reg(pm4
, R_028238_CB_TARGET_MASK
, mask
);
216 si_pm4_set_state(sctx
, fb_blend
, pm4
);
223 static uint32_t si_translate_blend_function(int blend_func
)
225 switch (blend_func
) {
227 return V_028780_COMB_DST_PLUS_SRC
;
228 case PIPE_BLEND_SUBTRACT
:
229 return V_028780_COMB_SRC_MINUS_DST
;
230 case PIPE_BLEND_REVERSE_SUBTRACT
:
231 return V_028780_COMB_DST_MINUS_SRC
;
233 return V_028780_COMB_MIN_DST_SRC
;
235 return V_028780_COMB_MAX_DST_SRC
;
237 R600_ERR("Unknown blend function %d\n", blend_func
);
244 static uint32_t si_translate_blend_factor(int blend_fact
)
246 switch (blend_fact
) {
247 case PIPE_BLENDFACTOR_ONE
:
248 return V_028780_BLEND_ONE
;
249 case PIPE_BLENDFACTOR_SRC_COLOR
:
250 return V_028780_BLEND_SRC_COLOR
;
251 case PIPE_BLENDFACTOR_SRC_ALPHA
:
252 return V_028780_BLEND_SRC_ALPHA
;
253 case PIPE_BLENDFACTOR_DST_ALPHA
:
254 return V_028780_BLEND_DST_ALPHA
;
255 case PIPE_BLENDFACTOR_DST_COLOR
:
256 return V_028780_BLEND_DST_COLOR
;
257 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
258 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
259 case PIPE_BLENDFACTOR_CONST_COLOR
:
260 return V_028780_BLEND_CONSTANT_COLOR
;
261 case PIPE_BLENDFACTOR_CONST_ALPHA
:
262 return V_028780_BLEND_CONSTANT_ALPHA
;
263 case PIPE_BLENDFACTOR_ZERO
:
264 return V_028780_BLEND_ZERO
;
265 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
266 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
267 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
268 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
269 case PIPE_BLENDFACTOR_INV_DST_ALPHA
:
270 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
271 case PIPE_BLENDFACTOR_INV_DST_COLOR
:
272 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
273 case PIPE_BLENDFACTOR_INV_CONST_COLOR
:
274 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR
;
275 case PIPE_BLENDFACTOR_INV_CONST_ALPHA
:
276 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA
;
277 case PIPE_BLENDFACTOR_SRC1_COLOR
:
278 return V_028780_BLEND_SRC1_COLOR
;
279 case PIPE_BLENDFACTOR_SRC1_ALPHA
:
280 return V_028780_BLEND_SRC1_ALPHA
;
281 case PIPE_BLENDFACTOR_INV_SRC1_COLOR
:
282 return V_028780_BLEND_INV_SRC1_COLOR
;
283 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA
:
284 return V_028780_BLEND_INV_SRC1_ALPHA
;
286 R600_ERR("Bad blend factor %d not supported!\n", blend_fact
);
293 static void *si_create_blend_state_mode(struct pipe_context
*ctx
,
294 const struct pipe_blend_state
*state
,
297 struct si_state_blend
*blend
= CALLOC_STRUCT(si_state_blend
);
298 struct si_pm4_state
*pm4
= &blend
->pm4
;
300 uint32_t color_control
= 0;
305 blend
->alpha_to_one
= state
->alpha_to_one
;
307 if (state
->logicop_enable
) {
308 color_control
|= S_028808_ROP3(state
->logicop_func
| (state
->logicop_func
<< 4));
310 color_control
|= S_028808_ROP3(0xcc);
313 si_pm4_set_reg(pm4
, R_028B70_DB_ALPHA_TO_MASK
,
314 S_028B70_ALPHA_TO_MASK_ENABLE(state
->alpha_to_coverage
) |
315 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
316 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
317 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
318 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
320 blend
->cb_target_mask
= 0;
321 for (int i
= 0; i
< 8; i
++) {
322 /* state->rt entries > 0 only written if independent blending */
323 const int j
= state
->independent_blend_enable
? i
: 0;
325 unsigned eqRGB
= state
->rt
[j
].rgb_func
;
326 unsigned srcRGB
= state
->rt
[j
].rgb_src_factor
;
327 unsigned dstRGB
= state
->rt
[j
].rgb_dst_factor
;
328 unsigned eqA
= state
->rt
[j
].alpha_func
;
329 unsigned srcA
= state
->rt
[j
].alpha_src_factor
;
330 unsigned dstA
= state
->rt
[j
].alpha_dst_factor
;
332 unsigned blend_cntl
= 0;
334 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
335 blend
->cb_target_mask
|= state
->rt
[j
].colormask
<< (4 * i
);
337 if (!state
->rt
[j
].blend_enable
) {
338 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
342 blend_cntl
|= S_028780_ENABLE(1);
343 blend_cntl
|= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB
));
344 blend_cntl
|= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB
));
345 blend_cntl
|= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB
));
347 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
348 blend_cntl
|= S_028780_SEPARATE_ALPHA_BLEND(1);
349 blend_cntl
|= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA
));
350 blend_cntl
|= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA
));
351 blend_cntl
|= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA
));
353 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
356 if (blend
->cb_target_mask
) {
357 color_control
|= S_028808_MODE(mode
);
359 color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
361 si_pm4_set_reg(pm4
, R_028808_CB_COLOR_CONTROL
, color_control
);
366 static void *si_create_blend_state(struct pipe_context
*ctx
,
367 const struct pipe_blend_state
*state
)
369 return si_create_blend_state_mode(ctx
, state
, V_028808_CB_NORMAL
);
372 static void si_bind_blend_state(struct pipe_context
*ctx
, void *state
)
374 struct si_context
*sctx
= (struct si_context
*)ctx
;
375 si_pm4_bind_state(sctx
, blend
, (struct si_state_blend
*)state
);
376 si_update_fb_blend_state(sctx
);
379 static void si_delete_blend_state(struct pipe_context
*ctx
, void *state
)
381 struct si_context
*sctx
= (struct si_context
*)ctx
;
382 si_pm4_delete_state(sctx
, blend
, (struct si_state_blend
*)state
);
385 static void si_set_blend_color(struct pipe_context
*ctx
,
386 const struct pipe_blend_color
*state
)
388 struct si_context
*sctx
= (struct si_context
*)ctx
;
389 struct si_pm4_state
*pm4
= si_pm4_alloc_state(sctx
);
394 si_pm4_set_reg(pm4
, R_028414_CB_BLEND_RED
, fui(state
->color
[0]));
395 si_pm4_set_reg(pm4
, R_028418_CB_BLEND_GREEN
, fui(state
->color
[1]));
396 si_pm4_set_reg(pm4
, R_02841C_CB_BLEND_BLUE
, fui(state
->color
[2]));
397 si_pm4_set_reg(pm4
, R_028420_CB_BLEND_ALPHA
, fui(state
->color
[3]));
399 si_pm4_set_state(sctx
, blend_color
, pm4
);
403 * Clipping, scissors and viewport
406 static void si_set_clip_state(struct pipe_context
*ctx
,
407 const struct pipe_clip_state
*state
)
409 struct si_context
*sctx
= (struct si_context
*)ctx
;
410 struct si_pm4_state
*pm4
= si_pm4_alloc_state(sctx
);
411 struct pipe_constant_buffer cb
;
416 for (int i
= 0; i
< 6; i
++) {
417 si_pm4_set_reg(pm4
, R_0285BC_PA_CL_UCP_0_X
+ i
* 16,
418 fui(state
->ucp
[i
][0]));
419 si_pm4_set_reg(pm4
, R_0285C0_PA_CL_UCP_0_Y
+ i
* 16,
420 fui(state
->ucp
[i
][1]));
421 si_pm4_set_reg(pm4
, R_0285C4_PA_CL_UCP_0_Z
+ i
* 16,
422 fui(state
->ucp
[i
][2]));
423 si_pm4_set_reg(pm4
, R_0285C8_PA_CL_UCP_0_W
+ i
* 16,
424 fui(state
->ucp
[i
][3]));
428 cb
.user_buffer
= state
->ucp
;
429 cb
.buffer_offset
= 0;
430 cb
.buffer_size
= 4*4*8;
431 ctx
->set_constant_buffer(ctx
, PIPE_SHADER_VERTEX
, NUM_PIPE_CONST_BUFFERS
, &cb
);
432 pipe_resource_reference(&cb
.buffer
, NULL
);
434 si_pm4_set_state(sctx
, clip
, pm4
);
437 static void si_set_scissor_states(struct pipe_context
*ctx
,
439 unsigned num_scissors
,
440 const struct pipe_scissor_state
*state
)
442 struct si_context
*sctx
= (struct si_context
*)ctx
;
443 struct si_pm4_state
*pm4
= si_pm4_alloc_state(sctx
);
448 si_pm4_set_reg(pm4
, R_028250_PA_SC_VPORT_SCISSOR_0_TL
,
449 S_028250_TL_X(state
->minx
) | S_028250_TL_Y(state
->miny
) |
450 S_028250_WINDOW_OFFSET_DISABLE(1));
451 si_pm4_set_reg(pm4
, R_028254_PA_SC_VPORT_SCISSOR_0_BR
,
452 S_028254_BR_X(state
->maxx
) | S_028254_BR_Y(state
->maxy
));
454 si_pm4_set_state(sctx
, scissor
, pm4
);
457 static void si_set_viewport_states(struct pipe_context
*ctx
,
459 unsigned num_viewports
,
460 const struct pipe_viewport_state
*state
)
462 struct si_context
*sctx
= (struct si_context
*)ctx
;
463 struct si_state_viewport
*viewport
= CALLOC_STRUCT(si_state_viewport
);
464 struct si_pm4_state
*pm4
= &viewport
->pm4
;
466 if (viewport
== NULL
)
469 viewport
->viewport
= *state
;
470 si_pm4_set_reg(pm4
, R_02843C_PA_CL_VPORT_XSCALE_0
, fui(state
->scale
[0]));
471 si_pm4_set_reg(pm4
, R_028440_PA_CL_VPORT_XOFFSET_0
, fui(state
->translate
[0]));
472 si_pm4_set_reg(pm4
, R_028444_PA_CL_VPORT_YSCALE_0
, fui(state
->scale
[1]));
473 si_pm4_set_reg(pm4
, R_028448_PA_CL_VPORT_YOFFSET_0
, fui(state
->translate
[1]));
474 si_pm4_set_reg(pm4
, R_02844C_PA_CL_VPORT_ZSCALE_0
, fui(state
->scale
[2]));
475 si_pm4_set_reg(pm4
, R_028450_PA_CL_VPORT_ZOFFSET_0
, fui(state
->translate
[2]));
477 si_pm4_set_state(sctx
, viewport
, viewport
);
481 * inferred state between framebuffer and rasterizer
483 static void si_update_fb_rs_state(struct si_context
*sctx
)
485 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
486 struct si_pm4_state
*pm4
;
487 unsigned offset_db_fmt_cntl
= 0, depth
;
490 if (!rs
|| !sctx
->framebuffer
.zsbuf
)
493 offset_units
= sctx
->queued
.named
.rasterizer
->offset_units
;
494 switch (sctx
->framebuffer
.zsbuf
->texture
->format
) {
495 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
496 case PIPE_FORMAT_X8Z24_UNORM
:
497 case PIPE_FORMAT_Z24X8_UNORM
:
498 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
500 offset_units
*= 2.0f
;
502 case PIPE_FORMAT_Z32_FLOAT
:
503 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
505 offset_units
*= 1.0f
;
506 offset_db_fmt_cntl
|= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
508 case PIPE_FORMAT_Z16_UNORM
:
510 offset_units
*= 4.0f
;
516 pm4
= si_pm4_alloc_state(sctx
);
521 /* FIXME some of those reg can be computed with cso */
522 offset_db_fmt_cntl
|= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth
);
523 si_pm4_set_reg(pm4
, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE
,
524 fui(sctx
->queued
.named
.rasterizer
->offset_scale
));
525 si_pm4_set_reg(pm4
, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET
, fui(offset_units
));
526 si_pm4_set_reg(pm4
, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE
,
527 fui(sctx
->queued
.named
.rasterizer
->offset_scale
));
528 si_pm4_set_reg(pm4
, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET
, fui(offset_units
));
529 si_pm4_set_reg(pm4
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
, offset_db_fmt_cntl
);
531 si_pm4_set_state(sctx
, fb_rs
, pm4
);
538 static uint32_t si_translate_fill(uint32_t func
)
541 case PIPE_POLYGON_MODE_FILL
:
542 return V_028814_X_DRAW_TRIANGLES
;
543 case PIPE_POLYGON_MODE_LINE
:
544 return V_028814_X_DRAW_LINES
;
545 case PIPE_POLYGON_MODE_POINT
:
546 return V_028814_X_DRAW_POINTS
;
549 return V_028814_X_DRAW_POINTS
;
553 static void *si_create_rs_state(struct pipe_context
*ctx
,
554 const struct pipe_rasterizer_state
*state
)
556 struct si_state_rasterizer
*rs
= CALLOC_STRUCT(si_state_rasterizer
);
557 struct si_pm4_state
*pm4
= &rs
->pm4
;
559 unsigned prov_vtx
= 1, polygon_dual_mode
;
560 float psize_min
, psize_max
;
566 rs
->two_side
= state
->light_twoside
;
567 rs
->multisample_enable
= state
->multisample
;
568 rs
->clip_plane_enable
= state
->clip_plane_enable
;
569 rs
->line_stipple_enable
= state
->line_stipple_enable
;
571 polygon_dual_mode
= (state
->fill_front
!= PIPE_POLYGON_MODE_FILL
||
572 state
->fill_back
!= PIPE_POLYGON_MODE_FILL
);
574 if (state
->flatshade_first
)
577 rs
->flatshade
= state
->flatshade
;
578 rs
->sprite_coord_enable
= state
->sprite_coord_enable
;
579 rs
->pa_sc_line_stipple
= state
->line_stipple_enable
?
580 S_028A0C_LINE_PATTERN(state
->line_stipple_pattern
) |
581 S_028A0C_REPEAT_COUNT(state
->line_stipple_factor
) : 0;
582 rs
->pa_su_sc_mode_cntl
=
583 S_028814_PROVOKING_VTX_LAST(prov_vtx
) |
584 S_028814_CULL_FRONT(state
->rasterizer_discard
|| (state
->cull_face
& PIPE_FACE_FRONT
) ? 1 : 0) |
585 S_028814_CULL_BACK(state
->rasterizer_discard
|| (state
->cull_face
& PIPE_FACE_BACK
) ? 1 : 0) |
586 S_028814_FACE(!state
->front_ccw
) |
587 S_028814_POLY_OFFSET_FRONT_ENABLE(state
->offset_tri
) |
588 S_028814_POLY_OFFSET_BACK_ENABLE(state
->offset_tri
) |
589 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_tri
) |
590 S_028814_POLY_MODE(polygon_dual_mode
) |
591 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state
->fill_front
)) |
592 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state
->fill_back
));
593 rs
->pa_cl_clip_cntl
=
594 S_028810_PS_UCP_MODE(3) |
595 S_028810_ZCLIP_NEAR_DISABLE(!state
->depth_clip
) |
596 S_028810_ZCLIP_FAR_DISABLE(!state
->depth_clip
) |
597 S_028810_DX_RASTERIZATION_KILL(state
->rasterizer_discard
) |
598 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
601 rs
->offset_units
= state
->offset_units
;
602 rs
->offset_scale
= state
->offset_scale
* 12.0f
;
604 tmp
= S_0286D4_FLAT_SHADE_ENA(1);
605 if (state
->sprite_coord_enable
) {
606 tmp
|= S_0286D4_PNT_SPRITE_ENA(1) |
607 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S
) |
608 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T
) |
609 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0
) |
610 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1
);
611 if (state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
) {
612 tmp
|= S_0286D4_PNT_SPRITE_TOP_1(1);
615 si_pm4_set_reg(pm4
, R_0286D4_SPI_INTERP_CONTROL_0
, tmp
);
617 /* point size 12.4 fixed point */
618 tmp
= (unsigned)(state
->point_size
* 8.0);
619 si_pm4_set_reg(pm4
, R_028A00_PA_SU_POINT_SIZE
, S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
));
621 if (state
->point_size_per_vertex
) {
622 psize_min
= util_get_min_point_size(state
);
625 /* Force the point size to be as if the vertex output was disabled. */
626 psize_min
= state
->point_size
;
627 psize_max
= state
->point_size
;
629 /* Divide by two, because 0.5 = 1 pixel. */
630 si_pm4_set_reg(pm4
, R_028A04_PA_SU_POINT_MINMAX
,
631 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min
/2)) |
632 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max
/2)));
634 tmp
= (unsigned)state
->line_width
* 8;
635 si_pm4_set_reg(pm4
, R_028A08_PA_SU_LINE_CNTL
, S_028A08_WIDTH(tmp
));
636 si_pm4_set_reg(pm4
, R_028A48_PA_SC_MODE_CNTL_0
,
637 S_028A48_LINE_STIPPLE_ENABLE(state
->line_stipple_enable
) |
638 S_028A48_MSAA_ENABLE(state
->multisample
) |
639 S_028A48_VPORT_SCISSOR_ENABLE(state
->scissor
));
641 si_pm4_set_reg(pm4
, R_028BE4_PA_SU_VTX_CNTL
,
642 S_028BE4_PIX_CENTER(state
->half_pixel_center
) |
643 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH
));
645 si_pm4_set_reg(pm4
, R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, fui(state
->offset_clamp
));
650 static void si_bind_rs_state(struct pipe_context
*ctx
, void *state
)
652 struct si_context
*sctx
= (struct si_context
*)ctx
;
653 struct si_state_rasterizer
*rs
= (struct si_state_rasterizer
*)state
;
659 sctx
->sprite_coord_enable
= rs
->sprite_coord_enable
;
660 sctx
->pa_sc_line_stipple
= rs
->pa_sc_line_stipple
;
661 sctx
->pa_su_sc_mode_cntl
= rs
->pa_su_sc_mode_cntl
;
663 si_pm4_bind_state(sctx
, rasterizer
, rs
);
664 si_update_fb_rs_state(sctx
);
667 static void si_delete_rs_state(struct pipe_context
*ctx
, void *state
)
669 struct si_context
*sctx
= (struct si_context
*)ctx
;
670 si_pm4_delete_state(sctx
, rasterizer
, (struct si_state_rasterizer
*)state
);
674 * infeered state between dsa and stencil ref
676 static void si_update_dsa_stencil_ref(struct si_context
*sctx
)
678 struct si_pm4_state
*pm4
= si_pm4_alloc_state(sctx
);
679 struct pipe_stencil_ref
*ref
= &sctx
->stencil_ref
;
680 struct si_state_dsa
*dsa
= sctx
->queued
.named
.dsa
;
685 si_pm4_set_reg(pm4
, R_028430_DB_STENCILREFMASK
,
686 S_028430_STENCILTESTVAL(ref
->ref_value
[0]) |
687 S_028430_STENCILMASK(dsa
->valuemask
[0]) |
688 S_028430_STENCILWRITEMASK(dsa
->writemask
[0]) |
689 S_028430_STENCILOPVAL(1));
690 si_pm4_set_reg(pm4
, R_028434_DB_STENCILREFMASK_BF
,
691 S_028434_STENCILTESTVAL_BF(ref
->ref_value
[1]) |
692 S_028434_STENCILMASK_BF(dsa
->valuemask
[1]) |
693 S_028434_STENCILWRITEMASK_BF(dsa
->writemask
[1]) |
694 S_028434_STENCILOPVAL_BF(1));
696 si_pm4_set_state(sctx
, dsa_stencil_ref
, pm4
);
699 static void si_set_pipe_stencil_ref(struct pipe_context
*ctx
,
700 const struct pipe_stencil_ref
*state
)
702 struct si_context
*sctx
= (struct si_context
*)ctx
;
703 sctx
->stencil_ref
= *state
;
704 si_update_dsa_stencil_ref(sctx
);
712 static uint32_t si_translate_stencil_op(int s_op
)
715 case PIPE_STENCIL_OP_KEEP
:
716 return V_02842C_STENCIL_KEEP
;
717 case PIPE_STENCIL_OP_ZERO
:
718 return V_02842C_STENCIL_ZERO
;
719 case PIPE_STENCIL_OP_REPLACE
:
720 return V_02842C_STENCIL_REPLACE_TEST
;
721 case PIPE_STENCIL_OP_INCR
:
722 return V_02842C_STENCIL_ADD_CLAMP
;
723 case PIPE_STENCIL_OP_DECR
:
724 return V_02842C_STENCIL_SUB_CLAMP
;
725 case PIPE_STENCIL_OP_INCR_WRAP
:
726 return V_02842C_STENCIL_ADD_WRAP
;
727 case PIPE_STENCIL_OP_DECR_WRAP
:
728 return V_02842C_STENCIL_SUB_WRAP
;
729 case PIPE_STENCIL_OP_INVERT
:
730 return V_02842C_STENCIL_INVERT
;
732 R600_ERR("Unknown stencil op %d", s_op
);
739 static void *si_create_dsa_state(struct pipe_context
*ctx
,
740 const struct pipe_depth_stencil_alpha_state
*state
)
742 struct si_state_dsa
*dsa
= CALLOC_STRUCT(si_state_dsa
);
743 struct si_pm4_state
*pm4
= &dsa
->pm4
;
744 unsigned db_depth_control
;
745 unsigned db_render_control
;
746 uint32_t db_stencil_control
= 0;
752 dsa
->valuemask
[0] = state
->stencil
[0].valuemask
;
753 dsa
->valuemask
[1] = state
->stencil
[1].valuemask
;
754 dsa
->writemask
[0] = state
->stencil
[0].writemask
;
755 dsa
->writemask
[1] = state
->stencil
[1].writemask
;
757 db_depth_control
= S_028800_Z_ENABLE(state
->depth
.enabled
) |
758 S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
759 S_028800_ZFUNC(state
->depth
.func
);
762 if (state
->stencil
[0].enabled
) {
763 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
764 db_depth_control
|= S_028800_STENCILFUNC(state
->stencil
[0].func
);
765 db_stencil_control
|= S_02842C_STENCILFAIL(si_translate_stencil_op(state
->stencil
[0].fail_op
));
766 db_stencil_control
|= S_02842C_STENCILZPASS(si_translate_stencil_op(state
->stencil
[0].zpass_op
));
767 db_stencil_control
|= S_02842C_STENCILZFAIL(si_translate_stencil_op(state
->stencil
[0].zfail_op
));
769 if (state
->stencil
[1].enabled
) {
770 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
771 db_depth_control
|= S_028800_STENCILFUNC_BF(state
->stencil
[1].func
);
772 db_stencil_control
|= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state
->stencil
[1].fail_op
));
773 db_stencil_control
|= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state
->stencil
[1].zpass_op
));
774 db_stencil_control
|= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state
->stencil
[1].zfail_op
));
779 if (state
->alpha
.enabled
) {
780 dsa
->alpha_func
= state
->alpha
.func
;
781 dsa
->alpha_ref
= state
->alpha
.ref_value
;
783 si_pm4_set_reg(pm4
, R_00B030_SPI_SHADER_USER_DATA_PS_0
+
784 SI_SGPR_ALPHA_REF
* 4, fui(dsa
->alpha_ref
));
786 dsa
->alpha_func
= PIPE_FUNC_ALWAYS
;
790 db_render_control
= 0;
791 si_pm4_set_reg(pm4
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
792 si_pm4_set_reg(pm4
, R_028000_DB_RENDER_CONTROL
, db_render_control
);
793 si_pm4_set_reg(pm4
, R_02842C_DB_STENCIL_CONTROL
, db_stencil_control
);
798 static void si_bind_dsa_state(struct pipe_context
*ctx
, void *state
)
800 struct si_context
*sctx
= (struct si_context
*)ctx
;
801 struct si_state_dsa
*dsa
= state
;
806 si_pm4_bind_state(sctx
, dsa
, dsa
);
807 si_update_dsa_stencil_ref(sctx
);
810 static void si_delete_dsa_state(struct pipe_context
*ctx
, void *state
)
812 struct si_context
*sctx
= (struct si_context
*)ctx
;
813 si_pm4_delete_state(sctx
, dsa
, (struct si_state_dsa
*)state
);
816 static void *si_create_db_flush_dsa(struct si_context
*sctx
, bool copy_depth
,
817 bool copy_stencil
, int sample
)
819 struct pipe_depth_stencil_alpha_state dsa
;
820 struct si_state_dsa
*state
;
822 memset(&dsa
, 0, sizeof(dsa
));
824 state
= sctx
->b
.b
.create_depth_stencil_alpha_state(&sctx
->b
.b
, &dsa
);
825 if (copy_depth
|| copy_stencil
) {
826 si_pm4_set_reg(&state
->pm4
, R_028000_DB_RENDER_CONTROL
,
827 S_028000_DEPTH_COPY(copy_depth
) |
828 S_028000_STENCIL_COPY(copy_stencil
) |
829 S_028000_COPY_CENTROID(1) |
830 S_028000_COPY_SAMPLE(sample
));
832 si_pm4_set_reg(&state
->pm4
, R_028000_DB_RENDER_CONTROL
,
833 S_028000_DEPTH_COMPRESS_DISABLE(1) |
834 S_028000_STENCIL_COMPRESS_DISABLE(1));
843 static uint32_t si_translate_colorformat(enum pipe_format format
)
845 const struct util_format_description
*desc
= util_format_description(format
);
847 #define HAS_SIZE(x,y,z,w) \
848 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
849 desc->channel[2].size == (z) && desc->channel[3].size == (w))
851 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
852 return V_028C70_COLOR_10_11_11
;
854 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
855 return V_028C70_COLOR_INVALID
;
857 switch (desc
->nr_channels
) {
859 switch (desc
->channel
[0].size
) {
861 return V_028C70_COLOR_8
;
863 return V_028C70_COLOR_16
;
865 return V_028C70_COLOR_32
;
869 if (desc
->channel
[0].size
== desc
->channel
[1].size
) {
870 switch (desc
->channel
[0].size
) {
872 return V_028C70_COLOR_8_8
;
874 return V_028C70_COLOR_16_16
;
876 return V_028C70_COLOR_32_32
;
878 } else if (HAS_SIZE(8,24,0,0)) {
879 return V_028C70_COLOR_24_8
;
880 } else if (HAS_SIZE(24,8,0,0)) {
881 return V_028C70_COLOR_8_24
;
885 if (HAS_SIZE(5,6,5,0)) {
886 return V_028C70_COLOR_5_6_5
;
887 } else if (HAS_SIZE(32,8,24,0)) {
888 return V_028C70_COLOR_X24_8_32_FLOAT
;
892 if (desc
->channel
[0].size
== desc
->channel
[1].size
&&
893 desc
->channel
[0].size
== desc
->channel
[2].size
&&
894 desc
->channel
[0].size
== desc
->channel
[3].size
) {
895 switch (desc
->channel
[0].size
) {
897 return V_028C70_COLOR_4_4_4_4
;
899 return V_028C70_COLOR_8_8_8_8
;
901 return V_028C70_COLOR_16_16_16_16
;
903 return V_028C70_COLOR_32_32_32_32
;
905 } else if (HAS_SIZE(5,5,5,1)) {
906 return V_028C70_COLOR_1_5_5_5
;
907 } else if (HAS_SIZE(10,10,10,2)) {
908 return V_028C70_COLOR_2_10_10_10
;
912 return V_028C70_COLOR_INVALID
;
915 static uint32_t si_translate_colorswap(enum pipe_format format
)
917 const struct util_format_description
*desc
= util_format_description(format
);
919 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == UTIL_FORMAT_SWIZZLE_##swz)
921 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
922 return V_028C70_SWAP_STD
;
924 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
927 switch (desc
->nr_channels
) {
929 if (HAS_SWIZZLE(0,X
))
930 return V_028C70_SWAP_STD
; /* X___ */
931 else if (HAS_SWIZZLE(3,X
))
932 return V_028C70_SWAP_ALT_REV
; /* ___X */
935 if ((HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,Y
)) ||
936 (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(1,NONE
)) ||
937 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,Y
)))
938 return V_028C70_SWAP_STD
; /* XY__ */
939 else if ((HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,X
)) ||
940 (HAS_SWIZZLE(0,Y
) && HAS_SWIZZLE(1,NONE
)) ||
941 (HAS_SWIZZLE(0,NONE
) && HAS_SWIZZLE(1,X
)))
942 return V_028C70_SWAP_STD_REV
; /* YX__ */
943 else if (HAS_SWIZZLE(0,X
) && HAS_SWIZZLE(3,Y
))
944 return V_028C70_SWAP_ALT
; /* X__Y */
947 if (HAS_SWIZZLE(0,X
))
948 return V_028C70_SWAP_STD
; /* XYZ */
949 else if (HAS_SWIZZLE(0,Z
))
950 return V_028C70_SWAP_STD_REV
; /* ZYX */
953 /* check the middle channels, the 1st and 4th channel can be NONE */
954 if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,Z
))
955 return V_028C70_SWAP_STD
; /* XYZW */
956 else if (HAS_SWIZZLE(1,Z
) && HAS_SWIZZLE(2,Y
))
957 return V_028C70_SWAP_STD_REV
; /* WZYX */
958 else if (HAS_SWIZZLE(1,Y
) && HAS_SWIZZLE(2,X
))
959 return V_028C70_SWAP_ALT
; /* ZYXW */
960 else if (HAS_SWIZZLE(1,X
) && HAS_SWIZZLE(2,Y
))
961 return V_028C70_SWAP_ALT_REV
; /* WXYZ */
967 static uint32_t si_colorformat_endian_swap(uint32_t colorformat
)
970 switch(colorformat
) {
972 case V_028C70_COLOR_8
:
973 return V_028C70_ENDIAN_NONE
;
975 /* 16-bit buffers. */
976 case V_028C70_COLOR_5_6_5
:
977 case V_028C70_COLOR_1_5_5_5
:
978 case V_028C70_COLOR_4_4_4_4
:
979 case V_028C70_COLOR_16
:
980 case V_028C70_COLOR_8_8
:
981 return V_028C70_ENDIAN_8IN16
;
983 /* 32-bit buffers. */
984 case V_028C70_COLOR_8_8_8_8
:
985 case V_028C70_COLOR_2_10_10_10
:
986 case V_028C70_COLOR_8_24
:
987 case V_028C70_COLOR_24_8
:
988 case V_028C70_COLOR_16_16
:
989 return V_028C70_ENDIAN_8IN32
;
991 /* 64-bit buffers. */
992 case V_028C70_COLOR_16_16_16_16
:
993 return V_028C70_ENDIAN_8IN16
;
995 case V_028C70_COLOR_32_32
:
996 return V_028C70_ENDIAN_8IN32
;
998 /* 128-bit buffers. */
999 case V_028C70_COLOR_32_32_32_32
:
1000 return V_028C70_ENDIAN_8IN32
;
1002 return V_028C70_ENDIAN_NONE
; /* Unsupported. */
1005 return V_028C70_ENDIAN_NONE
;
1009 /* Returns the size in bits of the widest component of a CB format */
1010 static unsigned si_colorformat_max_comp_size(uint32_t colorformat
)
1012 switch(colorformat
) {
1013 case V_028C70_COLOR_4_4_4_4
:
1016 case V_028C70_COLOR_1_5_5_5
:
1017 case V_028C70_COLOR_5_5_5_1
:
1020 case V_028C70_COLOR_5_6_5
:
1023 case V_028C70_COLOR_8
:
1024 case V_028C70_COLOR_8_8
:
1025 case V_028C70_COLOR_8_8_8_8
:
1028 case V_028C70_COLOR_10_10_10_2
:
1029 case V_028C70_COLOR_2_10_10_10
:
1032 case V_028C70_COLOR_10_11_11
:
1033 case V_028C70_COLOR_11_11_10
:
1036 case V_028C70_COLOR_16
:
1037 case V_028C70_COLOR_16_16
:
1038 case V_028C70_COLOR_16_16_16_16
:
1041 case V_028C70_COLOR_8_24
:
1042 case V_028C70_COLOR_24_8
:
1045 case V_028C70_COLOR_32
:
1046 case V_028C70_COLOR_32_32
:
1047 case V_028C70_COLOR_32_32_32_32
:
1048 case V_028C70_COLOR_X24_8_32_FLOAT
:
1052 assert(!"Unknown maximum component size");
1056 static uint32_t si_translate_dbformat(enum pipe_format format
)
1059 case PIPE_FORMAT_Z16_UNORM
:
1060 return V_028040_Z_16
;
1061 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1062 case PIPE_FORMAT_X8Z24_UNORM
:
1063 case PIPE_FORMAT_Z24X8_UNORM
:
1064 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1065 return V_028040_Z_24
; /* deprecated on SI */
1066 case PIPE_FORMAT_Z32_FLOAT
:
1067 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1068 return V_028040_Z_32_FLOAT
;
1070 return V_028040_Z_INVALID
;
1075 * Texture translation
1078 static uint32_t si_translate_texformat(struct pipe_screen
*screen
,
1079 enum pipe_format format
,
1080 const struct util_format_description
*desc
,
1083 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1084 bool enable_s3tc
= sscreen
->b
.info
.drm_minor
>= 31;
1085 boolean uniform
= TRUE
;
1088 /* Colorspace (return non-RGB formats directly). */
1089 switch (desc
->colorspace
) {
1090 /* Depth stencil formats */
1091 case UTIL_FORMAT_COLORSPACE_ZS
:
1093 case PIPE_FORMAT_Z16_UNORM
:
1094 return V_008F14_IMG_DATA_FORMAT_16
;
1095 case PIPE_FORMAT_X24S8_UINT
:
1096 case PIPE_FORMAT_Z24X8_UNORM
:
1097 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1098 return V_008F14_IMG_DATA_FORMAT_8_24
;
1099 case PIPE_FORMAT_X8Z24_UNORM
:
1100 case PIPE_FORMAT_S8X24_UINT
:
1101 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1102 return V_008F14_IMG_DATA_FORMAT_24_8
;
1103 case PIPE_FORMAT_S8_UINT
:
1104 return V_008F14_IMG_DATA_FORMAT_8
;
1105 case PIPE_FORMAT_Z32_FLOAT
:
1106 return V_008F14_IMG_DATA_FORMAT_32
;
1107 case PIPE_FORMAT_X32_S8X24_UINT
:
1108 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1109 return V_008F14_IMG_DATA_FORMAT_X24_8_32
;
1114 case UTIL_FORMAT_COLORSPACE_YUV
:
1115 goto out_unknown
; /* TODO */
1117 case UTIL_FORMAT_COLORSPACE_SRGB
:
1118 if (desc
->nr_channels
!= 4 && desc
->nr_channels
!= 1)
1126 if (desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
) {
1131 case PIPE_FORMAT_RGTC1_SNORM
:
1132 case PIPE_FORMAT_LATC1_SNORM
:
1133 case PIPE_FORMAT_RGTC1_UNORM
:
1134 case PIPE_FORMAT_LATC1_UNORM
:
1135 return V_008F14_IMG_DATA_FORMAT_BC4
;
1136 case PIPE_FORMAT_RGTC2_SNORM
:
1137 case PIPE_FORMAT_LATC2_SNORM
:
1138 case PIPE_FORMAT_RGTC2_UNORM
:
1139 case PIPE_FORMAT_LATC2_UNORM
:
1140 return V_008F14_IMG_DATA_FORMAT_BC5
;
1146 if (desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
1151 if (!util_format_s3tc_enabled
) {
1156 case PIPE_FORMAT_DXT1_RGB
:
1157 case PIPE_FORMAT_DXT1_RGBA
:
1158 case PIPE_FORMAT_DXT1_SRGB
:
1159 case PIPE_FORMAT_DXT1_SRGBA
:
1160 return V_008F14_IMG_DATA_FORMAT_BC1
;
1161 case PIPE_FORMAT_DXT3_RGBA
:
1162 case PIPE_FORMAT_DXT3_SRGBA
:
1163 return V_008F14_IMG_DATA_FORMAT_BC2
;
1164 case PIPE_FORMAT_DXT5_RGBA
:
1165 case PIPE_FORMAT_DXT5_SRGBA
:
1166 return V_008F14_IMG_DATA_FORMAT_BC3
;
1172 if (format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
1173 return V_008F14_IMG_DATA_FORMAT_5_9_9_9
;
1174 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
1175 return V_008F14_IMG_DATA_FORMAT_10_11_11
;
1178 /* R8G8Bx_SNORM - TODO CxV8U8 */
1180 /* See whether the components are of the same size. */
1181 for (i
= 1; i
< desc
->nr_channels
; i
++) {
1182 uniform
= uniform
&& desc
->channel
[0].size
== desc
->channel
[i
].size
;
1185 /* Non-uniform formats. */
1187 switch(desc
->nr_channels
) {
1189 if (desc
->channel
[0].size
== 5 &&
1190 desc
->channel
[1].size
== 6 &&
1191 desc
->channel
[2].size
== 5) {
1192 return V_008F14_IMG_DATA_FORMAT_5_6_5
;
1196 if (desc
->channel
[0].size
== 5 &&
1197 desc
->channel
[1].size
== 5 &&
1198 desc
->channel
[2].size
== 5 &&
1199 desc
->channel
[3].size
== 1) {
1200 return V_008F14_IMG_DATA_FORMAT_1_5_5_5
;
1202 if (desc
->channel
[0].size
== 10 &&
1203 desc
->channel
[1].size
== 10 &&
1204 desc
->channel
[2].size
== 10 &&
1205 desc
->channel
[3].size
== 2) {
1206 return V_008F14_IMG_DATA_FORMAT_2_10_10_10
;
1213 if (first_non_void
< 0 || first_non_void
> 3)
1216 /* uniform formats */
1217 switch (desc
->channel
[first_non_void
].size
) {
1219 switch (desc
->nr_channels
) {
1220 #if 0 /* Not supported for render targets */
1222 return V_008F14_IMG_DATA_FORMAT_4_4
;
1225 return V_008F14_IMG_DATA_FORMAT_4_4_4_4
;
1229 switch (desc
->nr_channels
) {
1231 return V_008F14_IMG_DATA_FORMAT_8
;
1233 return V_008F14_IMG_DATA_FORMAT_8_8
;
1235 return V_008F14_IMG_DATA_FORMAT_8_8_8_8
;
1239 switch (desc
->nr_channels
) {
1241 return V_008F14_IMG_DATA_FORMAT_16
;
1243 return V_008F14_IMG_DATA_FORMAT_16_16
;
1245 return V_008F14_IMG_DATA_FORMAT_16_16_16_16
;
1249 switch (desc
->nr_channels
) {
1251 return V_008F14_IMG_DATA_FORMAT_32
;
1253 return V_008F14_IMG_DATA_FORMAT_32_32
;
1254 #if 0 /* Not supported for render targets */
1256 return V_008F14_IMG_DATA_FORMAT_32_32_32
;
1259 return V_008F14_IMG_DATA_FORMAT_32_32_32_32
;
1264 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1268 static unsigned si_tex_wrap(unsigned wrap
)
1272 case PIPE_TEX_WRAP_REPEAT
:
1273 return V_008F30_SQ_TEX_WRAP
;
1274 case PIPE_TEX_WRAP_CLAMP
:
1275 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER
;
1276 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
1277 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL
;
1278 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
1279 return V_008F30_SQ_TEX_CLAMP_BORDER
;
1280 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
1281 return V_008F30_SQ_TEX_MIRROR
;
1282 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
1283 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
1284 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
1285 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
1286 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
1287 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER
;
1291 static unsigned si_tex_filter(unsigned filter
)
1295 case PIPE_TEX_FILTER_NEAREST
:
1296 return V_008F38_SQ_TEX_XY_FILTER_POINT
;
1297 case PIPE_TEX_FILTER_LINEAR
:
1298 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR
;
1302 static unsigned si_tex_mipfilter(unsigned filter
)
1305 case PIPE_TEX_MIPFILTER_NEAREST
:
1306 return V_008F38_SQ_TEX_Z_FILTER_POINT
;
1307 case PIPE_TEX_MIPFILTER_LINEAR
:
1308 return V_008F38_SQ_TEX_Z_FILTER_LINEAR
;
1310 case PIPE_TEX_MIPFILTER_NONE
:
1311 return V_008F38_SQ_TEX_Z_FILTER_NONE
;
1315 static unsigned si_tex_compare(unsigned compare
)
1319 case PIPE_FUNC_NEVER
:
1320 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
1321 case PIPE_FUNC_LESS
:
1322 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS
;
1323 case PIPE_FUNC_EQUAL
:
1324 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL
;
1325 case PIPE_FUNC_LEQUAL
:
1326 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
1327 case PIPE_FUNC_GREATER
:
1328 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER
;
1329 case PIPE_FUNC_NOTEQUAL
:
1330 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
1331 case PIPE_FUNC_GEQUAL
:
1332 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
1333 case PIPE_FUNC_ALWAYS
:
1334 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
1338 static unsigned si_tex_dim(unsigned dim
, unsigned nr_samples
)
1342 case PIPE_TEXTURE_1D
:
1343 return V_008F1C_SQ_RSRC_IMG_1D
;
1344 case PIPE_TEXTURE_1D_ARRAY
:
1345 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY
;
1346 case PIPE_TEXTURE_2D
:
1347 case PIPE_TEXTURE_RECT
:
1348 return nr_samples
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA
:
1349 V_008F1C_SQ_RSRC_IMG_2D
;
1350 case PIPE_TEXTURE_2D_ARRAY
:
1351 return nr_samples
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
:
1352 V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
1353 case PIPE_TEXTURE_3D
:
1354 return V_008F1C_SQ_RSRC_IMG_3D
;
1355 case PIPE_TEXTURE_CUBE
:
1356 return V_008F1C_SQ_RSRC_IMG_CUBE
;
1361 * Format support testing
1364 static bool si_is_sampler_format_supported(struct pipe_screen
*screen
, enum pipe_format format
)
1366 return si_translate_texformat(screen
, format
, util_format_description(format
),
1367 util_format_get_first_non_void_channel(format
)) != ~0U;
1370 static uint32_t si_translate_buffer_dataformat(struct pipe_screen
*screen
,
1371 const struct util_format_description
*desc
,
1374 unsigned type
= desc
->channel
[first_non_void
].type
;
1377 if (type
== UTIL_FORMAT_TYPE_FIXED
)
1378 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
1380 if (desc
->nr_channels
== 4 &&
1381 desc
->channel
[0].size
== 10 &&
1382 desc
->channel
[1].size
== 10 &&
1383 desc
->channel
[2].size
== 10 &&
1384 desc
->channel
[3].size
== 2)
1385 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10
;
1387 /* See whether the components are of the same size. */
1388 for (i
= 0; i
< desc
->nr_channels
; i
++) {
1389 if (desc
->channel
[first_non_void
].size
!= desc
->channel
[i
].size
)
1390 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
1393 switch (desc
->channel
[first_non_void
].size
) {
1395 switch (desc
->nr_channels
) {
1397 return V_008F0C_BUF_DATA_FORMAT_8
;
1399 return V_008F0C_BUF_DATA_FORMAT_8_8
;
1402 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8
;
1406 switch (desc
->nr_channels
) {
1408 return V_008F0C_BUF_DATA_FORMAT_16
;
1410 return V_008F0C_BUF_DATA_FORMAT_16_16
;
1413 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16
;
1417 /* From the Southern Islands ISA documentation about MTBUF:
1418 * 'Memory reads of data in memory that is 32 or 64 bits do not
1419 * undergo any format conversion.'
1421 if (type
!= UTIL_FORMAT_TYPE_FLOAT
&&
1422 !desc
->channel
[first_non_void
].pure_integer
)
1423 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
1425 switch (desc
->nr_channels
) {
1427 return V_008F0C_BUF_DATA_FORMAT_32
;
1429 return V_008F0C_BUF_DATA_FORMAT_32_32
;
1431 return V_008F0C_BUF_DATA_FORMAT_32_32_32
;
1433 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
1438 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
1441 static uint32_t si_translate_buffer_numformat(struct pipe_screen
*screen
,
1442 const struct util_format_description
*desc
,
1445 switch (desc
->channel
[first_non_void
].type
) {
1446 case UTIL_FORMAT_TYPE_SIGNED
:
1447 if (desc
->channel
[first_non_void
].normalized
)
1448 return V_008F0C_BUF_NUM_FORMAT_SNORM
;
1449 else if (desc
->channel
[first_non_void
].pure_integer
)
1450 return V_008F0C_BUF_NUM_FORMAT_SINT
;
1452 return V_008F0C_BUF_NUM_FORMAT_SSCALED
;
1454 case UTIL_FORMAT_TYPE_UNSIGNED
:
1455 if (desc
->channel
[first_non_void
].normalized
)
1456 return V_008F0C_BUF_NUM_FORMAT_UNORM
;
1457 else if (desc
->channel
[first_non_void
].pure_integer
)
1458 return V_008F0C_BUF_NUM_FORMAT_UINT
;
1460 return V_008F0C_BUF_NUM_FORMAT_USCALED
;
1462 case UTIL_FORMAT_TYPE_FLOAT
:
1464 return V_008F0C_BUF_NUM_FORMAT_FLOAT
;
1468 static bool si_is_vertex_format_supported(struct pipe_screen
*screen
, enum pipe_format format
)
1470 const struct util_format_description
*desc
;
1472 unsigned data_format
;
1474 desc
= util_format_description(format
);
1475 first_non_void
= util_format_get_first_non_void_channel(format
);
1476 data_format
= si_translate_buffer_dataformat(screen
, desc
, first_non_void
);
1477 return data_format
!= V_008F0C_BUF_DATA_FORMAT_INVALID
;
1480 static bool si_is_colorbuffer_format_supported(enum pipe_format format
)
1482 return si_translate_colorformat(format
) != V_028C70_COLOR_INVALID
&&
1483 si_translate_colorswap(format
) != ~0U;
1486 static bool si_is_zs_format_supported(enum pipe_format format
)
1488 return si_translate_dbformat(format
) != V_028040_Z_INVALID
;
1491 boolean
si_is_format_supported(struct pipe_screen
*screen
,
1492 enum pipe_format format
,
1493 enum pipe_texture_target target
,
1494 unsigned sample_count
,
1497 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1498 unsigned retval
= 0;
1500 if (target
>= PIPE_MAX_TEXTURE_TYPES
) {
1501 R600_ERR("r600: unsupported texture type %d\n", target
);
1505 if (!util_format_is_supported(format
, usage
))
1508 if (sample_count
> 1) {
1509 if (HAVE_LLVM
< 0x0304)
1512 /* 2D tiling on CIK is supported since DRM 2.35.0 */
1513 if (sscreen
->b
.chip_class
>= CIK
&& sscreen
->b
.info
.drm_minor
< 35)
1516 switch (sample_count
) {
1526 if (usage
& PIPE_BIND_SAMPLER_VIEW
) {
1527 if (target
== PIPE_BUFFER
) {
1528 if (si_is_vertex_format_supported(screen
, format
))
1529 retval
|= PIPE_BIND_SAMPLER_VIEW
;
1531 if (si_is_sampler_format_supported(screen
, format
))
1532 retval
|= PIPE_BIND_SAMPLER_VIEW
;
1536 if ((usage
& (PIPE_BIND_RENDER_TARGET
|
1537 PIPE_BIND_DISPLAY_TARGET
|
1539 PIPE_BIND_SHARED
)) &&
1540 si_is_colorbuffer_format_supported(format
)) {
1542 (PIPE_BIND_RENDER_TARGET
|
1543 PIPE_BIND_DISPLAY_TARGET
|
1548 if ((usage
& PIPE_BIND_DEPTH_STENCIL
) &&
1549 si_is_zs_format_supported(format
)) {
1550 retval
|= PIPE_BIND_DEPTH_STENCIL
;
1553 if ((usage
& PIPE_BIND_VERTEX_BUFFER
) &&
1554 si_is_vertex_format_supported(screen
, format
)) {
1555 retval
|= PIPE_BIND_VERTEX_BUFFER
;
1558 if (usage
& PIPE_BIND_TRANSFER_READ
)
1559 retval
|= PIPE_BIND_TRANSFER_READ
;
1560 if (usage
& PIPE_BIND_TRANSFER_WRITE
)
1561 retval
|= PIPE_BIND_TRANSFER_WRITE
;
1563 return retval
== usage
;
1566 static unsigned si_tile_mode_index(struct r600_texture
*rtex
, unsigned level
, bool stencil
)
1568 unsigned tile_mode_index
= 0;
1571 tile_mode_index
= rtex
->surface
.stencil_tiling_index
[level
];
1573 tile_mode_index
= rtex
->surface
.tiling_index
[level
];
1575 return tile_mode_index
;
1579 * framebuffer handling
1582 static void si_cb(struct si_context
*sctx
, struct si_pm4_state
*pm4
,
1583 const struct pipe_framebuffer_state
*state
, int cb
)
1585 struct r600_texture
*rtex
;
1586 struct si_surface
*surf
;
1587 unsigned level
= state
->cbufs
[cb
]->u
.tex
.level
;
1588 unsigned pitch
, slice
;
1589 unsigned color_info
, color_attrib
, color_pitch
, color_view
;
1590 unsigned tile_mode_index
;
1591 unsigned format
, swap
, ntype
, endian
;
1593 const struct util_format_description
*desc
;
1595 unsigned blend_clamp
= 0, blend_bypass
= 0;
1596 unsigned max_comp_size
;
1598 surf
= (struct si_surface
*)state
->cbufs
[cb
];
1599 rtex
= (struct r600_texture
*)state
->cbufs
[cb
]->texture
;
1601 offset
= rtex
->surface
.level
[level
].offset
;
1603 /* Layered rendering doesn't work with LINEAR_GENERAL.
1604 * (LINEAR_ALIGNED and others work) */
1605 if (rtex
->surface
.level
[level
].mode
== RADEON_SURF_MODE_LINEAR
) {
1606 assert(state
->cbufs
[cb
]->u
.tex
.first_layer
== state
->cbufs
[cb
]->u
.tex
.last_layer
);
1607 offset
+= rtex
->surface
.level
[level
].slice_size
*
1608 state
->cbufs
[cb
]->u
.tex
.first_layer
;
1611 color_view
= S_028C6C_SLICE_START(state
->cbufs
[cb
]->u
.tex
.first_layer
) |
1612 S_028C6C_SLICE_MAX(state
->cbufs
[cb
]->u
.tex
.last_layer
);
1615 pitch
= (rtex
->surface
.level
[level
].nblk_x
) / 8 - 1;
1616 slice
= (rtex
->surface
.level
[level
].nblk_x
* rtex
->surface
.level
[level
].nblk_y
) / 64;
1621 tile_mode_index
= si_tile_mode_index(rtex
, level
, false);
1623 desc
= util_format_description(surf
->base
.format
);
1624 for (i
= 0; i
< 4; i
++) {
1625 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
1629 if (i
== 4 || desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
) {
1630 ntype
= V_028C70_NUMBER_FLOAT
;
1632 ntype
= V_028C70_NUMBER_UNORM
;
1633 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
1634 ntype
= V_028C70_NUMBER_SRGB
;
1635 else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
1636 if (desc
->channel
[i
].pure_integer
) {
1637 ntype
= V_028C70_NUMBER_SINT
;
1639 assert(desc
->channel
[i
].normalized
);
1640 ntype
= V_028C70_NUMBER_SNORM
;
1642 } else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
1643 if (desc
->channel
[i
].pure_integer
) {
1644 ntype
= V_028C70_NUMBER_UINT
;
1646 assert(desc
->channel
[i
].normalized
);
1647 ntype
= V_028C70_NUMBER_UNORM
;
1652 format
= si_translate_colorformat(surf
->base
.format
);
1653 if (format
== V_028C70_COLOR_INVALID
) {
1654 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf
->base
.format
);
1656 assert(format
!= V_028C70_COLOR_INVALID
);
1657 swap
= si_translate_colorswap(surf
->base
.format
);
1658 if (rtex
->resource
.b
.b
.usage
== PIPE_USAGE_STAGING
) {
1659 endian
= V_028C70_ENDIAN_NONE
;
1661 endian
= si_colorformat_endian_swap(format
);
1664 /* blend clamp should be set for all NORM/SRGB types */
1665 if (ntype
== V_028C70_NUMBER_UNORM
||
1666 ntype
== V_028C70_NUMBER_SNORM
||
1667 ntype
== V_028C70_NUMBER_SRGB
)
1670 /* set blend bypass according to docs if SINT/UINT or
1671 8/24 COLOR variants */
1672 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
1673 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
1674 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
1679 color_info
= S_028C70_FORMAT(format
) |
1680 S_028C70_COMP_SWAP(swap
) |
1681 S_028C70_BLEND_CLAMP(blend_clamp
) |
1682 S_028C70_BLEND_BYPASS(blend_bypass
) |
1683 S_028C70_NUMBER_TYPE(ntype
) |
1684 S_028C70_ENDIAN(endian
);
1686 color_pitch
= S_028C64_TILE_MAX(pitch
);
1688 color_attrib
= S_028C74_TILE_MODE_INDEX(tile_mode_index
) |
1689 S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] == UTIL_FORMAT_SWIZZLE_1
);
1691 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
1692 unsigned log_samples
= util_logbase2(rtex
->resource
.b
.b
.nr_samples
);
1694 color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
1695 S_028C74_NUM_FRAGMENTS(log_samples
);
1697 if (rtex
->fmask
.size
) {
1698 color_info
|= S_028C70_COMPRESSION(1);
1699 unsigned fmask_bankh
= util_logbase2(rtex
->fmask
.bank_height
);
1701 color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(rtex
->fmask
.tile_mode_index
);
1703 if (sctx
->b
.chip_class
== SI
) {
1704 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
1705 color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh
);
1707 if (sctx
->b
.chip_class
>= CIK
) {
1708 color_pitch
|= S_028C64_FMASK_TILE_MAX(rtex
->fmask
.pitch
/ 8 - 1);
1713 if (rtex
->cmask
.size
) {
1714 color_info
|= S_028C70_FAST_CLEAR(1);
1717 offset
+= r600_resource_va(sctx
->b
.b
.screen
, state
->cbufs
[cb
]->texture
);
1720 si_pm4_add_bo(pm4
, &rtex
->resource
, RADEON_USAGE_READWRITE
);
1721 si_pm4_set_reg(pm4
, R_028C60_CB_COLOR0_BASE
+ cb
* 0x3C, offset
);
1722 si_pm4_set_reg(pm4
, R_028C64_CB_COLOR0_PITCH
+ cb
* 0x3C, color_pitch
);
1723 si_pm4_set_reg(pm4
, R_028C68_CB_COLOR0_SLICE
+ cb
* 0x3C, S_028C68_TILE_MAX(slice
));
1724 si_pm4_set_reg(pm4
, R_028C6C_CB_COLOR0_VIEW
+ cb
* 0x3C, color_view
);
1725 si_pm4_set_reg(pm4
, R_028C70_CB_COLOR0_INFO
+ cb
* 0x3C, color_info
);
1726 si_pm4_set_reg(pm4
, R_028C74_CB_COLOR0_ATTRIB
+ cb
* 0x3C, color_attrib
);
1728 if (rtex
->cmask
.size
) {
1729 si_pm4_set_reg(pm4
, R_028C7C_CB_COLOR0_CMASK
+ cb
* 0x3C,
1730 offset
+ (rtex
->cmask
.offset
>> 8));
1731 si_pm4_set_reg(pm4
, R_028C80_CB_COLOR0_CMASK_SLICE
+ cb
* 0x3C,
1732 S_028C80_TILE_MAX(rtex
->cmask
.slice_tile_max
));
1734 if (rtex
->fmask
.size
) {
1735 si_pm4_set_reg(pm4
, R_028C84_CB_COLOR0_FMASK
+ cb
* 0x3C,
1736 offset
+ (rtex
->fmask
.offset
>> 8));
1737 si_pm4_set_reg(pm4
, R_028C88_CB_COLOR0_FMASK_SLICE
+ cb
* 0x3C,
1738 S_028C88_TILE_MAX(rtex
->fmask
.slice_tile_max
));
1741 /* set CB_COLOR1_INFO for possible dual-src blending */
1742 if (state
->nr_cbufs
== 1) {
1744 si_pm4_set_reg(pm4
, R_028C70_CB_COLOR0_INFO
+ 1 * 0x3C, color_info
);
1747 /* Determine pixel shader export format */
1748 max_comp_size
= si_colorformat_max_comp_size(format
);
1749 if (ntype
== V_028C70_NUMBER_SRGB
||
1750 ((ntype
== V_028C70_NUMBER_UNORM
|| ntype
== V_028C70_NUMBER_SNORM
) &&
1751 max_comp_size
<= 10) ||
1752 (ntype
== V_028C70_NUMBER_FLOAT
&& max_comp_size
<= 16)) {
1753 sctx
->export_16bpc
|= 1 << cb
;
1754 /* set SPI_SHADER_COL_FORMAT for possible dual-src blending */
1755 if (state
->nr_cbufs
== 1)
1756 sctx
->export_16bpc
|= 1 << 1;
1760 static void si_db(struct si_context
*sctx
, struct si_pm4_state
*pm4
,
1761 const struct pipe_framebuffer_state
*state
)
1763 struct si_screen
*sscreen
= sctx
->screen
;
1764 struct r600_texture
*rtex
;
1765 struct si_surface
*surf
;
1766 unsigned level
, pitch
, slice
, format
, tile_mode_index
, array_mode
;
1767 unsigned macro_aspect
, tile_split
, stile_split
, bankh
, bankw
, nbanks
, pipe_config
;
1768 uint32_t z_info
, s_info
, db_depth_info
;
1769 uint64_t z_offs
, s_offs
;
1770 uint32_t db_htile_data_base
, db_htile_surface
;
1772 if (state
->zsbuf
== NULL
) {
1773 si_pm4_set_reg(pm4
, R_028040_DB_Z_INFO
, S_028040_FORMAT(V_028040_Z_INVALID
));
1774 si_pm4_set_reg(pm4
, R_028044_DB_STENCIL_INFO
, S_028044_FORMAT(V_028044_STENCIL_INVALID
));
1778 surf
= (struct si_surface
*)state
->zsbuf
;
1779 level
= surf
->base
.u
.tex
.level
;
1780 rtex
= (struct r600_texture
*)surf
->base
.texture
;
1782 format
= si_translate_dbformat(rtex
->resource
.b
.b
.format
);
1784 if (format
== V_028040_Z_INVALID
) {
1785 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex
->resource
.b
.b
.format
);
1787 assert(format
!= V_028040_Z_INVALID
);
1789 s_offs
= z_offs
= r600_resource_va(sctx
->b
.b
.screen
, surf
->base
.texture
);
1790 z_offs
+= rtex
->surface
.level
[level
].offset
;
1791 s_offs
+= rtex
->surface
.stencil_level
[level
].offset
;
1796 pitch
= (rtex
->surface
.level
[level
].nblk_x
/ 8) - 1;
1797 slice
= (rtex
->surface
.level
[level
].nblk_x
* rtex
->surface
.level
[level
].nblk_y
) / 64;
1802 db_depth_info
= S_02803C_ADDR5_SWIZZLE_MASK(1);
1804 z_info
= S_028040_FORMAT(format
);
1805 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
1806 z_info
|= S_028040_NUM_SAMPLES(util_logbase2(rtex
->resource
.b
.b
.nr_samples
));
1809 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
)
1810 s_info
= S_028044_FORMAT(V_028044_STENCIL_8
);
1812 s_info
= S_028044_FORMAT(V_028044_STENCIL_INVALID
);
1814 if (sctx
->b
.chip_class
>= CIK
) {
1815 switch (rtex
->surface
.level
[level
].mode
) {
1816 case RADEON_SURF_MODE_2D
:
1817 array_mode
= V_02803C_ARRAY_2D_TILED_THIN1
;
1819 case RADEON_SURF_MODE_1D
:
1820 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1821 case RADEON_SURF_MODE_LINEAR
:
1823 array_mode
= V_02803C_ARRAY_1D_TILED_THIN1
;
1826 tile_split
= rtex
->surface
.tile_split
;
1827 stile_split
= rtex
->surface
.stencil_tile_split
;
1828 macro_aspect
= rtex
->surface
.mtilea
;
1829 bankw
= rtex
->surface
.bankw
;
1830 bankh
= rtex
->surface
.bankh
;
1831 tile_split
= cik_tile_split(tile_split
);
1832 stile_split
= cik_tile_split(stile_split
);
1833 macro_aspect
= cik_macro_tile_aspect(macro_aspect
);
1834 bankw
= cik_bank_wh(bankw
);
1835 bankh
= cik_bank_wh(bankh
);
1836 nbanks
= cik_num_banks(sscreen
, rtex
->surface
.bpe
, rtex
->surface
.tile_split
);
1837 tile_mode_index
= si_tile_mode_index(rtex
, level
, false);
1838 pipe_config
= cik_db_pipe_config(sscreen
, tile_mode_index
);
1840 db_depth_info
|= S_02803C_ARRAY_MODE(array_mode
) |
1841 S_02803C_PIPE_CONFIG(pipe_config
) |
1842 S_02803C_BANK_WIDTH(bankw
) |
1843 S_02803C_BANK_HEIGHT(bankh
) |
1844 S_02803C_MACRO_TILE_ASPECT(macro_aspect
) |
1845 S_02803C_NUM_BANKS(nbanks
);
1846 z_info
|= S_028040_TILE_SPLIT(tile_split
);
1847 s_info
|= S_028044_TILE_SPLIT(stile_split
);
1849 tile_mode_index
= si_tile_mode_index(rtex
, level
, false);
1850 z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
1851 tile_mode_index
= si_tile_mode_index(rtex
, level
, true);
1852 s_info
|= S_028044_TILE_MODE_INDEX(tile_mode_index
);
1855 /* HiZ aka depth buffer htile */
1856 /* use htile only for first level */
1857 if (rtex
->htile_buffer
&& !level
) {
1858 const struct util_format_description
*fmt_desc
;
1860 z_info
|= S_028040_TILE_SURFACE_ENABLE(1);
1862 /* This is optimal for the clear value of 1.0 and using
1863 * the LESS and LEQUAL test functions. Set this to 0
1864 * for the opposite case. This can only be changed when
1866 z_info
|= S_028040_ZRANGE_PRECISION(1);
1868 fmt_desc
= util_format_description(rtex
->resource
.b
.b
.format
);
1869 if (!util_format_has_stencil(fmt_desc
)) {
1870 /* Use all of the htile_buffer for depth */
1871 s_info
|= S_028044_TILE_STENCIL_DISABLE(1);
1874 uint64_t va
= r600_resource_va(&sctx
->screen
->b
.b
, &rtex
->htile_buffer
->b
.b
);
1875 db_htile_data_base
= va
>> 8;
1876 db_htile_surface
= S_028ABC_FULL_CACHE(1);
1878 si_pm4_add_bo(pm4
, rtex
->htile_buffer
, RADEON_USAGE_READWRITE
);
1880 db_htile_data_base
= 0;
1881 db_htile_surface
= 0;
1884 si_pm4_set_reg(pm4
, R_028008_DB_DEPTH_VIEW
,
1885 S_028008_SLICE_START(state
->zsbuf
->u
.tex
.first_layer
) |
1886 S_028008_SLICE_MAX(state
->zsbuf
->u
.tex
.last_layer
));
1887 si_pm4_set_reg(pm4
, R_028014_DB_HTILE_DATA_BASE
, db_htile_data_base
);
1889 si_pm4_set_reg(pm4
, R_02803C_DB_DEPTH_INFO
, db_depth_info
);
1890 si_pm4_set_reg(pm4
, R_028040_DB_Z_INFO
, z_info
);
1891 si_pm4_set_reg(pm4
, R_028044_DB_STENCIL_INFO
, s_info
);
1893 si_pm4_add_bo(pm4
, &rtex
->resource
, RADEON_USAGE_READWRITE
);
1894 si_pm4_set_reg(pm4
, R_028048_DB_Z_READ_BASE
, z_offs
);
1895 si_pm4_set_reg(pm4
, R_02804C_DB_STENCIL_READ_BASE
, s_offs
);
1896 si_pm4_set_reg(pm4
, R_028050_DB_Z_WRITE_BASE
, z_offs
);
1897 si_pm4_set_reg(pm4
, R_028054_DB_STENCIL_WRITE_BASE
, s_offs
);
1899 si_pm4_set_reg(pm4
, R_028058_DB_DEPTH_SIZE
, S_028058_PITCH_TILE_MAX(pitch
));
1900 si_pm4_set_reg(pm4
, R_02805C_DB_DEPTH_SLICE
, S_02805C_SLICE_TILE_MAX(slice
));
1902 si_pm4_set_reg(pm4
, R_028ABC_DB_HTILE_SURFACE
, db_htile_surface
);
1905 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1906 (((s0x) & 0xf) | (((s0y) & 0xf) << 4) | \
1907 (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) | \
1908 (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) | \
1909 (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
1912 * There are two locations (-4, 4), (4, -4). */
1913 static uint32_t sample_locs_2x
[] = {
1914 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1915 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1916 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1917 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1919 static unsigned max_dist_2x
= 4;
1921 * There are 4 locations: (-2, -2), (2, 2), (-6, 6), (6, -6). */
1922 static uint32_t sample_locs_4x
[] = {
1923 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1924 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1925 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1926 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1928 static unsigned max_dist_4x
= 6;
1929 /* Cayman/SI 8xMSAA */
1930 static uint32_t cm_sample_locs_8x
[] = {
1931 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1932 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1933 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1934 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1935 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1936 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1937 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1938 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1940 static unsigned cm_max_dist_8x
= 8;
1941 /* Cayman/SI 16xMSAA */
1942 static uint32_t cm_sample_locs_16x
[] = {
1943 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1944 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1945 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1946 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1947 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1948 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1949 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1950 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1951 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1952 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1953 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1954 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1955 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1956 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1957 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1958 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1960 static unsigned cm_max_dist_16x
= 8;
1962 static void si_get_sample_position(struct pipe_context
*ctx
,
1963 unsigned sample_count
,
1964 unsigned sample_index
,
1971 switch (sample_count
) {
1974 out_value
[0] = out_value
[1] = 0.5;
1977 offset
= 4 * (sample_index
* 2);
1978 val
.idx
= (sample_locs_2x
[0] >> offset
) & 0xf;
1979 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
1980 val
.idx
= (sample_locs_2x
[0] >> (offset
+ 4)) & 0xf;
1981 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
1984 offset
= 4 * (sample_index
* 2);
1985 val
.idx
= (sample_locs_4x
[0] >> offset
) & 0xf;
1986 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
1987 val
.idx
= (sample_locs_4x
[0] >> (offset
+ 4)) & 0xf;
1988 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
1991 offset
= 4 * (sample_index
% 4 * 2);
1992 index
= (sample_index
/ 4) * 4;
1993 val
.idx
= (cm_sample_locs_8x
[index
] >> offset
) & 0xf;
1994 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
1995 val
.idx
= (cm_sample_locs_8x
[index
] >> (offset
+ 4)) & 0xf;
1996 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
1999 offset
= 4 * (sample_index
% 4 * 2);
2000 index
= (sample_index
/ 4) * 4;
2001 val
.idx
= (cm_sample_locs_16x
[index
] >> offset
) & 0xf;
2002 out_value
[0] = (float)(val
.idx
+ 8) / 16.0f
;
2003 val
.idx
= (cm_sample_locs_16x
[index
] >> (offset
+ 4)) & 0xf;
2004 out_value
[1] = (float)(val
.idx
+ 8) / 16.0f
;
2009 static void si_set_msaa_state(struct si_context
*sctx
, struct si_pm4_state
*pm4
, int nr_samples
)
2011 unsigned max_dist
= 0;
2013 switch (nr_samples
) {
2018 si_pm4_set_reg(pm4
, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, sample_locs_2x
[0]);
2019 si_pm4_set_reg(pm4
, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, sample_locs_2x
[1]);
2020 si_pm4_set_reg(pm4
, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, sample_locs_2x
[2]);
2021 si_pm4_set_reg(pm4
, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, sample_locs_2x
[3]);
2022 max_dist
= max_dist_2x
;
2025 si_pm4_set_reg(pm4
, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, sample_locs_4x
[0]);
2026 si_pm4_set_reg(pm4
, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, sample_locs_4x
[1]);
2027 si_pm4_set_reg(pm4
, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, sample_locs_4x
[2]);
2028 si_pm4_set_reg(pm4
, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, sample_locs_4x
[3]);
2029 max_dist
= max_dist_4x
;
2032 si_pm4_set_reg(pm4
, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, cm_sample_locs_8x
[0]);
2033 si_pm4_set_reg(pm4
, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1
, cm_sample_locs_8x
[4]);
2034 si_pm4_set_reg(pm4
, R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2
, 0);
2035 si_pm4_set_reg(pm4
, R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3
, 0);
2036 si_pm4_set_reg(pm4
, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, cm_sample_locs_8x
[1]);
2037 si_pm4_set_reg(pm4
, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1
, cm_sample_locs_8x
[5]);
2038 si_pm4_set_reg(pm4
, R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2
, 0);
2039 si_pm4_set_reg(pm4
, R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3
, 0);
2040 si_pm4_set_reg(pm4
, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, cm_sample_locs_8x
[2]);
2041 si_pm4_set_reg(pm4
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1
, cm_sample_locs_8x
[6]);
2042 si_pm4_set_reg(pm4
, R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2
, 0);
2043 si_pm4_set_reg(pm4
, R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3
, 0);
2044 si_pm4_set_reg(pm4
, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, cm_sample_locs_8x
[3]);
2045 si_pm4_set_reg(pm4
, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1
, cm_sample_locs_8x
[7]);
2046 max_dist
= cm_max_dist_8x
;
2049 si_pm4_set_reg(pm4
, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0
, cm_sample_locs_16x
[0]);
2050 si_pm4_set_reg(pm4
, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1
, cm_sample_locs_16x
[4]);
2051 si_pm4_set_reg(pm4
, R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2
, cm_sample_locs_16x
[8]);
2052 si_pm4_set_reg(pm4
, R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3
, cm_sample_locs_16x
[12]);
2053 si_pm4_set_reg(pm4
, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0
, cm_sample_locs_16x
[1]);
2054 si_pm4_set_reg(pm4
, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1
, cm_sample_locs_16x
[5]);
2055 si_pm4_set_reg(pm4
, R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2
, cm_sample_locs_16x
[9]);
2056 si_pm4_set_reg(pm4
, R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3
, cm_sample_locs_16x
[13]);
2057 si_pm4_set_reg(pm4
, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0
, cm_sample_locs_16x
[2]);
2058 si_pm4_set_reg(pm4
, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1
, cm_sample_locs_16x
[6]);
2059 si_pm4_set_reg(pm4
, R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2
, cm_sample_locs_16x
[10]);
2060 si_pm4_set_reg(pm4
, R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3
, cm_sample_locs_16x
[14]);
2061 si_pm4_set_reg(pm4
, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0
, cm_sample_locs_16x
[3]);
2062 si_pm4_set_reg(pm4
, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1
, cm_sample_locs_16x
[7]);
2063 si_pm4_set_reg(pm4
, R_028C30_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2
, cm_sample_locs_16x
[11]);
2064 si_pm4_set_reg(pm4
, R_028C34_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3
, cm_sample_locs_16x
[15]);
2065 max_dist
= cm_max_dist_16x
;
2069 if (nr_samples
> 1) {
2070 unsigned log_samples
= util_logbase2(nr_samples
);
2072 si_pm4_set_reg(pm4
, R_028BDC_PA_SC_LINE_CNTL
,
2073 S_028BDC_LAST_PIXEL(1) |
2074 S_028BDC_EXPAND_LINE_WIDTH(1));
2075 si_pm4_set_reg(pm4
, R_028BE0_PA_SC_AA_CONFIG
,
2076 S_028BE0_MSAA_NUM_SAMPLES(log_samples
) |
2077 S_028BE0_MAX_SAMPLE_DIST(max_dist
) |
2078 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples
));
2080 si_pm4_set_reg(pm4
, R_028804_DB_EQAA
,
2081 S_028804_MAX_ANCHOR_SAMPLES(log_samples
) |
2082 S_028804_PS_ITER_SAMPLES(log_samples
) |
2083 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples
) |
2084 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples
) |
2085 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
2086 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
2088 si_pm4_set_reg(pm4
, R_028BDC_PA_SC_LINE_CNTL
, S_028BDC_LAST_PIXEL(1));
2089 si_pm4_set_reg(pm4
, R_028BE0_PA_SC_AA_CONFIG
, 0);
2091 si_pm4_set_reg(pm4
, R_028804_DB_EQAA
,
2092 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
2093 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
2097 static void si_set_framebuffer_state(struct pipe_context
*ctx
,
2098 const struct pipe_framebuffer_state
*state
)
2100 struct si_context
*sctx
= (struct si_context
*)ctx
;
2101 struct si_pm4_state
*pm4
= si_pm4_alloc_state(sctx
);
2107 if (sctx
->framebuffer
.nr_cbufs
) {
2108 sctx
->b
.flags
|= R600_CONTEXT_FLUSH_AND_INV_CB
|
2109 R600_CONTEXT_FLUSH_AND_INV_CB_META
;
2111 if (sctx
->framebuffer
.zsbuf
) {
2112 sctx
->b
.flags
|= R600_CONTEXT_FLUSH_AND_INV_DB
|
2113 R600_CONTEXT_FLUSH_AND_INV_DB_META
;
2116 util_copy_framebuffer_state(&sctx
->framebuffer
, state
);
2119 sctx
->export_16bpc
= 0;
2120 sctx
->fb_compressed_cb_mask
= 0;
2121 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
2122 struct r600_texture
*rtex
;
2124 if (!state
->cbufs
[i
]) {
2125 si_pm4_set_reg(pm4
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
2126 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
2130 rtex
= (struct r600_texture
*)state
->cbufs
[i
]->texture
;
2132 si_cb(sctx
, pm4
, state
, i
);
2134 if (rtex
->fmask
.size
|| rtex
->cmask
.size
) {
2135 sctx
->fb_compressed_cb_mask
|= 1 << i
;
2138 for (; i
< 8; i
++) {
2139 si_pm4_set_reg(pm4
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
2140 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
2143 assert(!(sctx
->export_16bpc
& ~0xff));
2144 si_db(sctx
, pm4
, state
);
2146 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2147 si_pm4_set_reg(pm4
, R_028208_PA_SC_WINDOW_SCISSOR_BR
,
2148 S_028208_BR_X(state
->width
) | S_028208_BR_Y(state
->height
));
2150 nr_samples
= util_framebuffer_get_num_samples(state
);
2152 si_set_msaa_state(sctx
, pm4
, nr_samples
);
2153 sctx
->fb_log_samples
= util_logbase2(nr_samples
);
2154 sctx
->fb_cb0_is_integer
= state
->nr_cbufs
&& state
->cbufs
[0] &&
2155 util_format_is_pure_integer(state
->cbufs
[0]->format
);
2157 si_pm4_set_state(sctx
, framebuffer
, pm4
);
2158 si_update_fb_rs_state(sctx
);
2159 si_update_fb_blend_state(sctx
);
2166 /* Compute the key for the hw shader variant */
2167 static INLINE
void si_shader_selector_key(struct pipe_context
*ctx
,
2168 struct si_pipe_shader_selector
*sel
,
2169 union si_shader_key
*key
)
2171 struct si_context
*sctx
= (struct si_context
*)ctx
;
2172 memset(key
, 0, sizeof(*key
));
2174 if ((sel
->type
== PIPE_SHADER_VERTEX
|| sel
->type
== PIPE_SHADER_GEOMETRY
) &&
2175 sctx
->queued
.named
.rasterizer
) {
2176 if (sctx
->queued
.named
.rasterizer
->clip_plane_enable
& 0xf0)
2177 key
->vs
.ucps_enabled
|= 0x2;
2178 if (sctx
->queued
.named
.rasterizer
->clip_plane_enable
& 0xf)
2179 key
->vs
.ucps_enabled
|= 0x1;
2182 if (sel
->type
== PIPE_SHADER_VERTEX
) {
2184 if (!sctx
->vertex_elements
)
2187 for (i
= 0; i
< sctx
->vertex_elements
->count
; ++i
)
2188 key
->vs
.instance_divisors
[i
] = sctx
->vertex_elements
->elements
[i
].instance_divisor
;
2190 key
->vs
.as_es
= sctx
->gs_shader
!= NULL
;
2191 } else if (sel
->type
== PIPE_SHADER_FRAGMENT
) {
2192 if (sel
->fs_write_all
)
2193 key
->ps
.nr_cbufs
= sctx
->framebuffer
.nr_cbufs
;
2194 key
->ps
.export_16bpc
= sctx
->export_16bpc
;
2196 if (sctx
->queued
.named
.rasterizer
) {
2197 key
->ps
.color_two_side
= sctx
->queued
.named
.rasterizer
->two_side
;
2198 key
->ps
.flatshade
= sctx
->queued
.named
.rasterizer
->flatshade
;
2200 if (sctx
->queued
.named
.blend
) {
2201 key
->ps
.alpha_to_one
= sctx
->queued
.named
.blend
->alpha_to_one
&&
2202 sctx
->queued
.named
.rasterizer
->multisample_enable
&&
2203 !sctx
->fb_cb0_is_integer
;
2206 if (sctx
->queued
.named
.dsa
) {
2207 key
->ps
.alpha_func
= sctx
->queued
.named
.dsa
->alpha_func
;
2209 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
2210 if (sctx
->framebuffer
.nr_cbufs
&&
2211 sctx
->framebuffer
.cbufs
[0] &&
2212 util_format_is_pure_integer(sctx
->framebuffer
.cbufs
[0]->texture
->format
))
2213 key
->ps
.alpha_func
= PIPE_FUNC_ALWAYS
;
2215 key
->ps
.alpha_func
= PIPE_FUNC_ALWAYS
;
2220 /* Select the hw shader variant depending on the current state. */
2221 int si_shader_select(struct pipe_context
*ctx
,
2222 struct si_pipe_shader_selector
*sel
)
2224 union si_shader_key key
;
2225 struct si_pipe_shader
* shader
= NULL
;
2228 si_shader_selector_key(ctx
, sel
, &key
);
2230 /* Check if we don't need to change anything.
2231 * This path is also used for most shaders that don't need multiple
2232 * variants, it will cost just a computation of the key and this
2234 if (likely(sel
->current
&& memcmp(&sel
->current
->key
, &key
, sizeof(key
)) == 0)) {
2238 /* lookup if we have other variants in the list */
2239 if (sel
->num_shaders
> 1) {
2240 struct si_pipe_shader
*p
= sel
->current
, *c
= p
->next_variant
;
2242 while (c
&& memcmp(&c
->key
, &key
, sizeof(key
)) != 0) {
2244 c
= c
->next_variant
;
2248 p
->next_variant
= c
->next_variant
;
2254 shader
->next_variant
= sel
->current
;
2255 sel
->current
= shader
;
2257 shader
= CALLOC(1, sizeof(struct si_pipe_shader
));
2258 shader
->selector
= sel
;
2261 shader
->next_variant
= sel
->current
;
2262 sel
->current
= shader
;
2263 r
= si_pipe_shader_create(ctx
, shader
);
2265 R600_ERR("Failed to build shader variant (type=%u) %d\n",
2267 sel
->current
= NULL
;
2277 static void *si_create_shader_state(struct pipe_context
*ctx
,
2278 const struct pipe_shader_state
*state
,
2279 unsigned pipe_shader_type
)
2281 struct si_pipe_shader_selector
*sel
= CALLOC_STRUCT(si_pipe_shader_selector
);
2284 sel
->type
= pipe_shader_type
;
2285 sel
->tokens
= tgsi_dup_tokens(state
->tokens
);
2286 sel
->so
= state
->stream_output
;
2288 if (pipe_shader_type
== PIPE_SHADER_FRAGMENT
) {
2289 struct tgsi_shader_info info
;
2291 tgsi_scan_shader(state
->tokens
, &info
);
2292 sel
->fs_write_all
= info
.color0_writes_all_cbufs
;
2295 r
= si_shader_select(ctx
, sel
);
2304 static void *si_create_fs_state(struct pipe_context
*ctx
,
2305 const struct pipe_shader_state
*state
)
2307 return si_create_shader_state(ctx
, state
, PIPE_SHADER_FRAGMENT
);
2310 #if HAVE_LLVM >= 0x0305
2312 static void *si_create_gs_state(struct pipe_context
*ctx
,
2313 const struct pipe_shader_state
*state
)
2315 return si_create_shader_state(ctx
, state
, PIPE_SHADER_GEOMETRY
);
2320 static void *si_create_vs_state(struct pipe_context
*ctx
,
2321 const struct pipe_shader_state
*state
)
2323 return si_create_shader_state(ctx
, state
, PIPE_SHADER_VERTEX
);
2326 static void si_bind_vs_shader(struct pipe_context
*ctx
, void *state
)
2328 struct si_context
*sctx
= (struct si_context
*)ctx
;
2329 struct si_pipe_shader_selector
*sel
= state
;
2331 if (sctx
->vs_shader
== sel
)
2334 if (!sel
|| !sel
->current
)
2337 sctx
->vs_shader
= sel
;
2340 #if HAVE_LLVM >= 0x0305
2342 static void si_bind_gs_shader(struct pipe_context
*ctx
, void *state
)
2344 struct si_context
*sctx
= (struct si_context
*)ctx
;
2345 struct si_pipe_shader_selector
*sel
= state
;
2347 if (sctx
->gs_shader
== sel
)
2350 sctx
->gs_shader
= sel
;
2355 static void si_bind_ps_shader(struct pipe_context
*ctx
, void *state
)
2357 struct si_context
*sctx
= (struct si_context
*)ctx
;
2358 struct si_pipe_shader_selector
*sel
= state
;
2360 if (sctx
->ps_shader
== sel
)
2363 if (!sel
|| !sel
->current
)
2364 sel
= sctx
->dummy_pixel_shader
;
2366 sctx
->ps_shader
= sel
;
2369 static void si_delete_shader_selector(struct pipe_context
*ctx
,
2370 struct si_pipe_shader_selector
*sel
)
2372 struct si_context
*sctx
= (struct si_context
*)ctx
;
2373 struct si_pipe_shader
*p
= sel
->current
, *c
;
2376 c
= p
->next_variant
;
2377 si_pm4_delete_state(sctx
, vs
, p
->pm4
);
2378 si_pipe_shader_destroy(ctx
, p
);
2387 static void si_delete_vs_shader(struct pipe_context
*ctx
, void *state
)
2389 struct si_context
*sctx
= (struct si_context
*)ctx
;
2390 struct si_pipe_shader_selector
*sel
= (struct si_pipe_shader_selector
*)state
;
2392 if (sctx
->vs_shader
== sel
) {
2393 sctx
->vs_shader
= NULL
;
2396 si_delete_shader_selector(ctx
, sel
);
2399 #if HAVE_LLVM >= 0x0305
2401 static void si_delete_gs_shader(struct pipe_context
*ctx
, void *state
)
2403 struct si_context
*sctx
= (struct si_context
*)ctx
;
2404 struct si_pipe_shader_selector
*sel
= (struct si_pipe_shader_selector
*)state
;
2406 if (sctx
->gs_shader
== sel
) {
2407 sctx
->gs_shader
= NULL
;
2410 si_delete_shader_selector(ctx
, sel
);
2415 static void si_delete_ps_shader(struct pipe_context
*ctx
, void *state
)
2417 struct si_context
*sctx
= (struct si_context
*)ctx
;
2418 struct si_pipe_shader_selector
*sel
= (struct si_pipe_shader_selector
*)state
;
2420 if (sctx
->ps_shader
== sel
) {
2421 sctx
->ps_shader
= NULL
;
2424 si_delete_shader_selector(ctx
, sel
);
2431 static struct pipe_sampler_view
*si_create_sampler_view(struct pipe_context
*ctx
,
2432 struct pipe_resource
*texture
,
2433 const struct pipe_sampler_view
*state
)
2435 struct si_pipe_sampler_view
*view
= CALLOC_STRUCT(si_pipe_sampler_view
);
2436 struct r600_texture
*tmp
= (struct r600_texture
*)texture
;
2437 const struct util_format_description
*desc
;
2438 unsigned format
, num_format
;
2440 unsigned char state_swizzle
[4], swizzle
[4];
2441 unsigned height
, depth
, width
;
2442 enum pipe_format pipe_format
= state
->format
;
2443 struct radeon_surface_level
*surflevel
;
2450 /* initialize base object */
2451 view
->base
= *state
;
2452 view
->base
.texture
= NULL
;
2453 pipe_resource_reference(&view
->base
.texture
, texture
);
2454 view
->base
.reference
.count
= 1;
2455 view
->base
.context
= ctx
;
2456 view
->resource
= &tmp
->resource
;
2458 /* Buffer resource. */
2459 if (texture
->target
== PIPE_BUFFER
) {
2462 desc
= util_format_description(state
->format
);
2463 first_non_void
= util_format_get_first_non_void_channel(state
->format
);
2464 stride
= desc
->block
.bits
/ 8;
2465 va
= r600_resource_va(ctx
->screen
, texture
) + state
->u
.buf
.first_element
*stride
;
2466 format
= si_translate_buffer_dataformat(ctx
->screen
, desc
, first_non_void
);
2467 num_format
= si_translate_buffer_numformat(ctx
->screen
, desc
, first_non_void
);
2469 view
->state
[0] = va
;
2470 view
->state
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
2471 S_008F04_STRIDE(stride
);
2472 view
->state
[2] = state
->u
.buf
.last_element
+ 1 - state
->u
.buf
.first_element
;
2473 view
->state
[3] = S_008F0C_DST_SEL_X(si_map_swizzle(desc
->swizzle
[0])) |
2474 S_008F0C_DST_SEL_Y(si_map_swizzle(desc
->swizzle
[1])) |
2475 S_008F0C_DST_SEL_Z(si_map_swizzle(desc
->swizzle
[2])) |
2476 S_008F0C_DST_SEL_W(si_map_swizzle(desc
->swizzle
[3])) |
2477 S_008F0C_NUM_FORMAT(num_format
) |
2478 S_008F0C_DATA_FORMAT(format
);
2482 state_swizzle
[0] = state
->swizzle_r
;
2483 state_swizzle
[1] = state
->swizzle_g
;
2484 state_swizzle
[2] = state
->swizzle_b
;
2485 state_swizzle
[3] = state
->swizzle_a
;
2487 surflevel
= tmp
->surface
.level
;
2489 /* Texturing with separate depth and stencil. */
2490 if (tmp
->is_depth
&& !tmp
->is_flushing_texture
) {
2491 switch (pipe_format
) {
2492 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
2493 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
2495 case PIPE_FORMAT_X8Z24_UNORM
:
2496 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
2497 /* Z24 is always stored like this. */
2498 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
2500 case PIPE_FORMAT_X24S8_UINT
:
2501 case PIPE_FORMAT_S8X24_UINT
:
2502 case PIPE_FORMAT_X32_S8X24_UINT
:
2503 pipe_format
= PIPE_FORMAT_S8_UINT
;
2504 surflevel
= tmp
->surface
.stencil_level
;
2510 desc
= util_format_description(pipe_format
);
2512 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
) {
2513 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
2514 const unsigned char swizzle_yyyy
[4] = {1, 1, 1, 1};
2516 switch (pipe_format
) {
2517 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
2518 case PIPE_FORMAT_X24S8_UINT
:
2519 case PIPE_FORMAT_X32_S8X24_UINT
:
2520 case PIPE_FORMAT_X8Z24_UNORM
:
2521 util_format_compose_swizzles(swizzle_yyyy
, state_swizzle
, swizzle
);
2524 util_format_compose_swizzles(swizzle_xxxx
, state_swizzle
, swizzle
);
2527 util_format_compose_swizzles(desc
->swizzle
, state_swizzle
, swizzle
);
2530 first_non_void
= util_format_get_first_non_void_channel(pipe_format
);
2532 switch (pipe_format
) {
2533 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
2534 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
2537 if (first_non_void
< 0) {
2538 if (util_format_is_compressed(pipe_format
)) {
2539 switch (pipe_format
) {
2540 case PIPE_FORMAT_DXT1_SRGB
:
2541 case PIPE_FORMAT_DXT1_SRGBA
:
2542 case PIPE_FORMAT_DXT3_SRGBA
:
2543 case PIPE_FORMAT_DXT5_SRGBA
:
2544 num_format
= V_008F14_IMG_NUM_FORMAT_SRGB
;
2546 case PIPE_FORMAT_RGTC1_SNORM
:
2547 case PIPE_FORMAT_LATC1_SNORM
:
2548 case PIPE_FORMAT_RGTC2_SNORM
:
2549 case PIPE_FORMAT_LATC2_SNORM
:
2550 num_format
= V_008F14_IMG_NUM_FORMAT_SNORM
;
2553 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
2557 num_format
= V_008F14_IMG_NUM_FORMAT_FLOAT
;
2559 } else if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
) {
2560 num_format
= V_008F14_IMG_NUM_FORMAT_SRGB
;
2562 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
2564 switch (desc
->channel
[first_non_void
].type
) {
2565 case UTIL_FORMAT_TYPE_FLOAT
:
2566 num_format
= V_008F14_IMG_NUM_FORMAT_FLOAT
;
2568 case UTIL_FORMAT_TYPE_SIGNED
:
2569 if (desc
->channel
[first_non_void
].normalized
)
2570 num_format
= V_008F14_IMG_NUM_FORMAT_SNORM
;
2571 else if (desc
->channel
[first_non_void
].pure_integer
)
2572 num_format
= V_008F14_IMG_NUM_FORMAT_SINT
;
2574 num_format
= V_008F14_IMG_NUM_FORMAT_SSCALED
;
2576 case UTIL_FORMAT_TYPE_UNSIGNED
:
2577 if (desc
->channel
[first_non_void
].normalized
)
2578 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
2579 else if (desc
->channel
[first_non_void
].pure_integer
)
2580 num_format
= V_008F14_IMG_NUM_FORMAT_UINT
;
2582 num_format
= V_008F14_IMG_NUM_FORMAT_USCALED
;
2587 format
= si_translate_texformat(ctx
->screen
, pipe_format
, desc
, first_non_void
);
2592 /* not supported any more */
2593 //endian = si_colorformat_endian_swap(format);
2595 width
= surflevel
[0].npix_x
;
2596 height
= surflevel
[0].npix_y
;
2597 depth
= surflevel
[0].npix_z
;
2598 pitch
= surflevel
[0].nblk_x
* util_format_get_blockwidth(pipe_format
);
2600 if (texture
->target
== PIPE_TEXTURE_1D_ARRAY
) {
2602 depth
= texture
->array_size
;
2603 } else if (texture
->target
== PIPE_TEXTURE_2D_ARRAY
) {
2604 depth
= texture
->array_size
;
2607 va
= r600_resource_va(ctx
->screen
, texture
);
2608 va
+= surflevel
[0].offset
;
2609 va
+= tmp
->mipmap_shift
* surflevel
[texture
->last_level
].slice_size
;
2610 view
->state
[0] = va
>> 8;
2611 view
->state
[1] = (S_008F14_BASE_ADDRESS_HI(va
>> 40) |
2612 S_008F14_DATA_FORMAT(format
) |
2613 S_008F14_NUM_FORMAT(num_format
));
2614 view
->state
[2] = (S_008F18_WIDTH(width
- 1) |
2615 S_008F18_HEIGHT(height
- 1));
2616 view
->state
[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle
[0])) |
2617 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle
[1])) |
2618 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle
[2])) |
2619 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle
[3])) |
2620 S_008F1C_BASE_LEVEL(texture
->nr_samples
> 1 ?
2621 0 : state
->u
.tex
.first_level
- tmp
->mipmap_shift
) |
2622 S_008F1C_LAST_LEVEL(texture
->nr_samples
> 1 ?
2623 util_logbase2(texture
->nr_samples
) :
2624 state
->u
.tex
.last_level
- tmp
->mipmap_shift
) |
2625 S_008F1C_TILING_INDEX(si_tile_mode_index(tmp
, 0, false)) |
2626 S_008F1C_POW2_PAD(texture
->last_level
> 0) |
2627 S_008F1C_TYPE(si_tex_dim(texture
->target
, texture
->nr_samples
)));
2628 view
->state
[4] = (S_008F20_DEPTH(depth
- 1) | S_008F20_PITCH(pitch
- 1));
2629 view
->state
[5] = (S_008F24_BASE_ARRAY(state
->u
.tex
.first_layer
) |
2630 S_008F24_LAST_ARRAY(state
->u
.tex
.last_layer
));
2634 /* Initialize the sampler view for FMASK. */
2635 if (tmp
->fmask
.size
) {
2636 uint64_t va
= r600_resource_va(ctx
->screen
, texture
) + tmp
->fmask
.offset
;
2637 uint32_t fmask_format
;
2639 switch (texture
->nr_samples
) {
2641 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2
;
2644 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4
;
2647 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8
;
2651 fmask_format
= V_008F14_IMG_DATA_FORMAT_INVALID
;
2654 view
->fmask_state
[0] = va
>> 8;
2655 view
->fmask_state
[1] = S_008F14_BASE_ADDRESS_HI(va
>> 40) |
2656 S_008F14_DATA_FORMAT(fmask_format
) |
2657 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT
);
2658 view
->fmask_state
[2] = S_008F18_WIDTH(width
- 1) |
2659 S_008F18_HEIGHT(height
- 1);
2660 view
->fmask_state
[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X
) |
2661 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X
) |
2662 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X
) |
2663 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X
) |
2664 S_008F1C_TILING_INDEX(tmp
->fmask
.tile_mode_index
) |
2665 S_008F1C_TYPE(si_tex_dim(texture
->target
, 0));
2666 view
->fmask_state
[4] = S_008F20_DEPTH(depth
- 1) |
2667 S_008F20_PITCH(tmp
->fmask
.pitch
- 1);
2668 view
->fmask_state
[5] = S_008F24_BASE_ARRAY(state
->u
.tex
.first_layer
) |
2669 S_008F24_LAST_ARRAY(state
->u
.tex
.last_layer
);
2670 view
->fmask_state
[6] = 0;
2671 view
->fmask_state
[7] = 0;
2677 static void si_sampler_view_destroy(struct pipe_context
*ctx
,
2678 struct pipe_sampler_view
*state
)
2680 struct r600_pipe_sampler_view
*resource
= (struct r600_pipe_sampler_view
*)state
;
2682 pipe_resource_reference(&state
->texture
, NULL
);
2686 static bool wrap_mode_uses_border_color(unsigned wrap
, bool linear_filter
)
2688 return wrap
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
||
2689 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
||
2691 (wrap
== PIPE_TEX_WRAP_CLAMP
||
2692 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP
));
2695 static bool sampler_state_needs_border_color(const struct pipe_sampler_state
*state
)
2697 bool linear_filter
= state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
||
2698 state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
;
2700 return (state
->border_color
.ui
[0] || state
->border_color
.ui
[1] ||
2701 state
->border_color
.ui
[2] || state
->border_color
.ui
[3]) &&
2702 (wrap_mode_uses_border_color(state
->wrap_s
, linear_filter
) ||
2703 wrap_mode_uses_border_color(state
->wrap_t
, linear_filter
) ||
2704 wrap_mode_uses_border_color(state
->wrap_r
, linear_filter
));
2707 static void *si_create_sampler_state(struct pipe_context
*ctx
,
2708 const struct pipe_sampler_state
*state
)
2710 struct si_pipe_sampler_state
*rstate
= CALLOC_STRUCT(si_pipe_sampler_state
);
2711 unsigned aniso_flag_offset
= state
->max_anisotropy
> 1 ? 2 : 0;
2712 unsigned border_color_type
;
2714 if (rstate
== NULL
) {
2718 if (sampler_state_needs_border_color(state
))
2719 border_color_type
= V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER
;
2721 border_color_type
= V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
;
2723 rstate
->val
[0] = (S_008F30_CLAMP_X(si_tex_wrap(state
->wrap_s
)) |
2724 S_008F30_CLAMP_Y(si_tex_wrap(state
->wrap_t
)) |
2725 S_008F30_CLAMP_Z(si_tex_wrap(state
->wrap_r
)) |
2726 (state
->max_anisotropy
& 0x7) << 9 | /* XXX */
2727 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state
->compare_func
)) |
2728 S_008F30_FORCE_UNNORMALIZED(!state
->normalized_coords
) |
2729 aniso_flag_offset
<< 16 | /* XXX */
2730 S_008F30_DISABLE_CUBE_WRAP(!state
->seamless_cube_map
));
2731 rstate
->val
[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 8)) |
2732 S_008F34_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 8)));
2733 rstate
->val
[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 8)) |
2734 S_008F38_XY_MAG_FILTER(si_tex_filter(state
->mag_img_filter
)) |
2735 S_008F38_XY_MIN_FILTER(si_tex_filter(state
->min_img_filter
)) |
2736 S_008F38_MIP_FILTER(si_tex_mipfilter(state
->min_mip_filter
)));
2737 rstate
->val
[3] = S_008F3C_BORDER_COLOR_TYPE(border_color_type
);
2739 if (border_color_type
== V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER
) {
2740 memcpy(rstate
->border_color
, state
->border_color
.ui
,
2741 sizeof(rstate
->border_color
));
2747 /* XXX consider moving this function to si_descriptors.c for gcc to inline
2748 * the si_set_sampler_view calls. LTO might help too. */
2749 static void si_set_sampler_views(struct pipe_context
*ctx
,
2750 unsigned shader
, unsigned start
,
2752 struct pipe_sampler_view
**views
)
2754 struct si_context
*sctx
= (struct si_context
*)ctx
;
2755 struct si_textures_info
*samplers
= &sctx
->samplers
[shader
];
2756 struct si_pipe_sampler_view
**rviews
= (struct si_pipe_sampler_view
**)views
;
2759 if (shader
>= SI_NUM_SHADERS
)
2764 for (i
= 0; i
< count
; i
++) {
2766 samplers
->depth_texture_mask
&= ~(1 << i
);
2767 samplers
->compressed_colortex_mask
&= ~(1 << i
);
2768 si_set_sampler_view(sctx
, shader
, i
, NULL
, NULL
);
2769 si_set_sampler_view(sctx
, shader
, FMASK_TEX_OFFSET
+ i
,
2774 si_set_sampler_view(sctx
, shader
, i
, views
[i
], rviews
[i
]->state
);
2776 if (views
[i
]->texture
->target
!= PIPE_BUFFER
) {
2777 struct r600_texture
*rtex
=
2778 (struct r600_texture
*)views
[i
]->texture
;
2780 if (rtex
->is_depth
&& !rtex
->is_flushing_texture
) {
2781 samplers
->depth_texture_mask
|= 1 << i
;
2783 samplers
->depth_texture_mask
&= ~(1 << i
);
2785 if (rtex
->cmask
.size
|| rtex
->fmask
.size
) {
2786 samplers
->compressed_colortex_mask
|= 1 << i
;
2788 samplers
->compressed_colortex_mask
&= ~(1 << i
);
2791 if (rtex
->fmask
.size
) {
2792 si_set_sampler_view(sctx
, shader
, FMASK_TEX_OFFSET
+ i
,
2793 views
[i
], rviews
[i
]->fmask_state
);
2795 si_set_sampler_view(sctx
, shader
, FMASK_TEX_OFFSET
+ i
,
2800 for (; i
< samplers
->n_views
; i
++) {
2801 samplers
->depth_texture_mask
&= ~(1 << i
);
2802 samplers
->compressed_colortex_mask
&= ~(1 << i
);
2803 si_set_sampler_view(sctx
, shader
, i
, NULL
, NULL
);
2804 si_set_sampler_view(sctx
, shader
, FMASK_TEX_OFFSET
+ i
,
2808 samplers
->n_views
= count
;
2809 sctx
->b
.flags
|= R600_CONTEXT_INV_TEX_CACHE
;
2812 static void si_set_sampler_states(struct si_context
*sctx
,
2813 struct si_pm4_state
*pm4
,
2814 unsigned count
, void **states
,
2815 struct si_textures_info
*samplers
,
2816 unsigned user_data_reg
)
2818 struct si_pipe_sampler_state
**rstates
= (struct si_pipe_sampler_state
**)states
;
2819 uint32_t *border_color_table
= NULL
;
2825 sctx
->b
.flags
|= R600_CONTEXT_INV_TEX_CACHE
;
2827 si_pm4_sh_data_begin(pm4
);
2828 for (i
= 0; i
< count
; i
++) {
2830 G_008F3C_BORDER_COLOR_TYPE(rstates
[i
]->val
[3]) ==
2831 V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER
) {
2832 if (!sctx
->border_color_table
||
2833 ((sctx
->border_color_offset
+ count
- i
) &
2834 C_008F3C_BORDER_COLOR_PTR
)) {
2835 r600_resource_reference(&sctx
->border_color_table
, NULL
);
2836 sctx
->border_color_offset
= 0;
2838 sctx
->border_color_table
=
2839 si_resource_create_custom(&sctx
->screen
->b
.b
,
2844 if (!border_color_table
) {
2845 border_color_table
=
2846 sctx
->b
.ws
->buffer_map(sctx
->border_color_table
->cs_buf
,
2847 sctx
->b
.rings
.gfx
.cs
,
2848 PIPE_TRANSFER_WRITE
|
2849 PIPE_TRANSFER_UNSYNCHRONIZED
);
2852 for (j
= 0; j
< 4; j
++) {
2853 border_color_table
[4 * sctx
->border_color_offset
+ j
] =
2854 util_le32_to_cpu(rstates
[i
]->border_color
[j
]);
2857 rstates
[i
]->val
[3] &= C_008F3C_BORDER_COLOR_PTR
;
2858 rstates
[i
]->val
[3] |= S_008F3C_BORDER_COLOR_PTR(sctx
->border_color_offset
++);
2861 for (j
= 0; j
< Elements(rstates
[i
]->val
); ++j
) {
2862 si_pm4_sh_data_add(pm4
, rstates
[i
] ? rstates
[i
]->val
[j
] : 0);
2865 si_pm4_sh_data_end(pm4
, user_data_reg
, SI_SGPR_SAMPLER
);
2867 if (border_color_table
) {
2868 uint64_t va_offset
=
2869 r600_resource_va(&sctx
->screen
->b
.b
,
2870 (void*)sctx
->border_color_table
);
2872 si_pm4_set_reg(pm4
, R_028080_TA_BC_BASE_ADDR
, va_offset
>> 8);
2873 if (sctx
->b
.chip_class
>= CIK
)
2874 si_pm4_set_reg(pm4
, R_028084_TA_BC_BASE_ADDR_HI
, va_offset
>> 40);
2875 sctx
->b
.ws
->buffer_unmap(sctx
->border_color_table
->cs_buf
);
2876 si_pm4_add_bo(pm4
, sctx
->border_color_table
, RADEON_USAGE_READ
);
2879 memcpy(samplers
->samplers
, states
, sizeof(void*) * count
);
2882 samplers
->n_samplers
= count
;
2885 static void si_bind_vs_sampler_states(struct pipe_context
*ctx
, unsigned count
, void **states
)
2887 struct si_context
*sctx
= (struct si_context
*)ctx
;
2888 struct si_pm4_state
*pm4
= si_pm4_alloc_state(sctx
);
2890 si_set_sampler_states(sctx
, pm4
, count
, states
,
2891 &sctx
->samplers
[PIPE_SHADER_VERTEX
],
2892 R_00B130_SPI_SHADER_USER_DATA_VS_0
);
2893 #if HAVE_LLVM >= 0x0305
2894 si_set_sampler_states(sctx
, pm4
, count
, states
,
2895 &sctx
->samplers
[PIPE_SHADER_VERTEX
],
2896 R_00B330_SPI_SHADER_USER_DATA_ES_0
);
2898 si_pm4_set_state(sctx
, vs_sampler
, pm4
);
2901 static void si_bind_gs_sampler_states(struct pipe_context
*ctx
, unsigned count
, void **states
)
2903 struct si_context
*sctx
= (struct si_context
*)ctx
;
2904 struct si_pm4_state
*pm4
= si_pm4_alloc_state(sctx
);
2906 si_set_sampler_states(sctx
, pm4
, count
, states
,
2907 &sctx
->samplers
[PIPE_SHADER_GEOMETRY
],
2908 R_00B230_SPI_SHADER_USER_DATA_GS_0
);
2909 si_pm4_set_state(sctx
, gs_sampler
, pm4
);
2912 static void si_bind_ps_sampler_states(struct pipe_context
*ctx
, unsigned count
, void **states
)
2914 struct si_context
*sctx
= (struct si_context
*)ctx
;
2915 struct si_pm4_state
*pm4
= si_pm4_alloc_state(sctx
);
2917 si_set_sampler_states(sctx
, pm4
, count
, states
,
2918 &sctx
->samplers
[PIPE_SHADER_FRAGMENT
],
2919 R_00B030_SPI_SHADER_USER_DATA_PS_0
);
2920 si_pm4_set_state(sctx
, ps_sampler
, pm4
);
2924 static void si_bind_sampler_states(struct pipe_context
*ctx
, unsigned shader
,
2925 unsigned start
, unsigned count
,
2931 case PIPE_SHADER_VERTEX
:
2932 si_bind_vs_sampler_states(ctx
, count
, states
);
2934 case PIPE_SHADER_GEOMETRY
:
2935 si_bind_gs_sampler_states(ctx
, count
, states
);
2937 case PIPE_SHADER_FRAGMENT
:
2938 si_bind_ps_sampler_states(ctx
, count
, states
);
2947 static void si_set_sample_mask(struct pipe_context
*ctx
, unsigned sample_mask
)
2949 struct si_context
*sctx
= (struct si_context
*)ctx
;
2950 struct si_pm4_state
*pm4
= si_pm4_alloc_state(sctx
);
2951 uint16_t mask
= sample_mask
;
2956 si_pm4_set_reg(pm4
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, mask
| (mask
<< 16));
2957 si_pm4_set_reg(pm4
, R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1
, mask
| (mask
<< 16));
2959 si_pm4_set_state(sctx
, sample_mask
, pm4
);
2962 static void si_delete_sampler_state(struct pipe_context
*ctx
, void *state
)
2968 * Vertex elements & buffers
2971 static void *si_create_vertex_elements(struct pipe_context
*ctx
,
2973 const struct pipe_vertex_element
*elements
)
2975 struct si_vertex_element
*v
= CALLOC_STRUCT(si_vertex_element
);
2978 assert(count
< PIPE_MAX_ATTRIBS
);
2983 for (i
= 0; i
< count
; ++i
) {
2984 const struct util_format_description
*desc
;
2985 unsigned data_format
, num_format
;
2988 desc
= util_format_description(elements
[i
].src_format
);
2989 first_non_void
= util_format_get_first_non_void_channel(elements
[i
].src_format
);
2990 data_format
= si_translate_buffer_dataformat(ctx
->screen
, desc
, first_non_void
);
2991 num_format
= si_translate_buffer_numformat(ctx
->screen
, desc
, first_non_void
);
2993 v
->rsrc_word3
[i
] = S_008F0C_DST_SEL_X(si_map_swizzle(desc
->swizzle
[0])) |
2994 S_008F0C_DST_SEL_Y(si_map_swizzle(desc
->swizzle
[1])) |
2995 S_008F0C_DST_SEL_Z(si_map_swizzle(desc
->swizzle
[2])) |
2996 S_008F0C_DST_SEL_W(si_map_swizzle(desc
->swizzle
[3])) |
2997 S_008F0C_NUM_FORMAT(num_format
) |
2998 S_008F0C_DATA_FORMAT(data_format
);
3000 memcpy(v
->elements
, elements
, sizeof(struct pipe_vertex_element
) * count
);
3005 static void si_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
3007 struct si_context
*sctx
= (struct si_context
*)ctx
;
3008 struct si_vertex_element
*v
= (struct si_vertex_element
*)state
;
3010 sctx
->vertex_elements
= v
;
3013 static void si_delete_vertex_element(struct pipe_context
*ctx
, void *state
)
3015 struct si_context
*sctx
= (struct si_context
*)ctx
;
3017 if (sctx
->vertex_elements
== state
)
3018 sctx
->vertex_elements
= NULL
;
3022 static void si_set_vertex_buffers(struct pipe_context
*ctx
, unsigned start_slot
, unsigned count
,
3023 const struct pipe_vertex_buffer
*buffers
)
3025 struct si_context
*sctx
= (struct si_context
*)ctx
;
3027 util_set_vertex_buffers_count(sctx
->vertex_buffer
, &sctx
->nr_vertex_buffers
, buffers
, start_slot
, count
);
3030 static void si_set_index_buffer(struct pipe_context
*ctx
,
3031 const struct pipe_index_buffer
*ib
)
3033 struct si_context
*sctx
= (struct si_context
*)ctx
;
3036 pipe_resource_reference(&sctx
->index_buffer
.buffer
, ib
->buffer
);
3037 memcpy(&sctx
->index_buffer
, ib
, sizeof(*ib
));
3039 pipe_resource_reference(&sctx
->index_buffer
.buffer
, NULL
);
3046 static void si_set_polygon_stipple(struct pipe_context
*ctx
,
3047 const struct pipe_poly_stipple
*state
)
3051 static void si_texture_barrier(struct pipe_context
*ctx
)
3053 struct si_context
*sctx
= (struct si_context
*)ctx
;
3055 sctx
->b
.flags
|= R600_CONTEXT_INV_TEX_CACHE
|
3056 R600_CONTEXT_FLUSH_AND_INV_CB
;
3059 static void *si_create_blend_custom(struct si_context
*sctx
, unsigned mode
)
3061 struct pipe_blend_state blend
;
3063 memset(&blend
, 0, sizeof(blend
));
3064 blend
.independent_blend_enable
= true;
3065 blend
.rt
[0].colormask
= 0xf;
3066 return si_create_blend_state_mode(&sctx
->b
.b
, &blend
, mode
);
3069 static struct pipe_surface
*r600_create_surface(struct pipe_context
*pipe
,
3070 struct pipe_resource
*texture
,
3071 const struct pipe_surface
*surf_tmpl
)
3073 struct r600_texture
*rtex
= (struct r600_texture
*)texture
;
3074 struct si_surface
*surface
= CALLOC_STRUCT(si_surface
);
3075 unsigned level
= surf_tmpl
->u
.tex
.level
;
3077 if (surface
== NULL
)
3080 assert(surf_tmpl
->u
.tex
.first_layer
<= util_max_layer(texture
, surf_tmpl
->u
.tex
.level
));
3081 assert(surf_tmpl
->u
.tex
.last_layer
<= util_max_layer(texture
, surf_tmpl
->u
.tex
.level
));
3083 pipe_reference_init(&surface
->base
.reference
, 1);
3084 pipe_resource_reference(&surface
->base
.texture
, texture
);
3085 surface
->base
.context
= pipe
;
3086 surface
->base
.format
= surf_tmpl
->format
;
3087 surface
->base
.width
= rtex
->surface
.level
[level
].npix_x
;
3088 surface
->base
.height
= rtex
->surface
.level
[level
].npix_y
;
3089 surface
->base
.texture
= texture
;
3090 surface
->base
.u
.tex
.first_layer
= surf_tmpl
->u
.tex
.first_layer
;
3091 surface
->base
.u
.tex
.last_layer
= surf_tmpl
->u
.tex
.last_layer
;
3092 surface
->base
.u
.tex
.level
= level
;
3094 return &surface
->base
;
3097 static void r600_surface_destroy(struct pipe_context
*pipe
,
3098 struct pipe_surface
*surface
)
3100 pipe_resource_reference(&surface
->texture
, NULL
);
3104 static boolean
si_dma_copy(struct pipe_context
*ctx
,
3105 struct pipe_resource
*dst
,
3107 unsigned dst_x
, unsigned dst_y
, unsigned dst_z
,
3108 struct pipe_resource
*src
,
3110 const struct pipe_box
*src_box
)
3112 /* XXX implement this or share evergreen_dma_blit with r600g */
3116 static void si_set_occlusion_query_state(struct pipe_context
*ctx
, bool enable
)
3118 /* XXX Turn this into a proper state. Right now the queries are
3119 * enabled in draw_vbo, which snoops r600_common_context to see
3120 * if any occlusion queries are active. */
3123 static void si_need_gfx_cs_space(struct pipe_context
*ctx
, unsigned num_dw
,
3124 bool include_draw_vbo
)
3126 si_need_cs_space((struct si_context
*)ctx
, num_dw
, include_draw_vbo
);
3129 void si_init_state_functions(struct si_context
*sctx
)
3133 sctx
->b
.b
.create_blend_state
= si_create_blend_state
;
3134 sctx
->b
.b
.bind_blend_state
= si_bind_blend_state
;
3135 sctx
->b
.b
.delete_blend_state
= si_delete_blend_state
;
3136 sctx
->b
.b
.set_blend_color
= si_set_blend_color
;
3138 sctx
->b
.b
.create_rasterizer_state
= si_create_rs_state
;
3139 sctx
->b
.b
.bind_rasterizer_state
= si_bind_rs_state
;
3140 sctx
->b
.b
.delete_rasterizer_state
= si_delete_rs_state
;
3142 sctx
->b
.b
.create_depth_stencil_alpha_state
= si_create_dsa_state
;
3143 sctx
->b
.b
.bind_depth_stencil_alpha_state
= si_bind_dsa_state
;
3144 sctx
->b
.b
.delete_depth_stencil_alpha_state
= si_delete_dsa_state
;
3146 for (i
= 0; i
< 8; i
++) {
3147 sctx
->custom_dsa_flush_depth_stencil
[i
] = si_create_db_flush_dsa(sctx
, true, true, i
);
3148 sctx
->custom_dsa_flush_depth
[i
] = si_create_db_flush_dsa(sctx
, true, false, i
);
3149 sctx
->custom_dsa_flush_stencil
[i
] = si_create_db_flush_dsa(sctx
, false, true, i
);
3151 sctx
->custom_dsa_flush_inplace
= si_create_db_flush_dsa(sctx
, false, false, 0);
3152 sctx
->custom_blend_resolve
= si_create_blend_custom(sctx
, V_028808_CB_RESOLVE
);
3153 sctx
->custom_blend_decompress
= si_create_blend_custom(sctx
, V_028808_CB_FMASK_DECOMPRESS
);
3155 sctx
->b
.b
.set_clip_state
= si_set_clip_state
;
3156 sctx
->b
.b
.set_scissor_states
= si_set_scissor_states
;
3157 sctx
->b
.b
.set_viewport_states
= si_set_viewport_states
;
3158 sctx
->b
.b
.set_stencil_ref
= si_set_pipe_stencil_ref
;
3160 sctx
->b
.b
.set_framebuffer_state
= si_set_framebuffer_state
;
3161 sctx
->b
.b
.get_sample_position
= si_get_sample_position
;
3163 sctx
->b
.b
.create_vs_state
= si_create_vs_state
;
3164 sctx
->b
.b
.create_fs_state
= si_create_fs_state
;
3165 sctx
->b
.b
.bind_vs_state
= si_bind_vs_shader
;
3166 sctx
->b
.b
.bind_fs_state
= si_bind_ps_shader
;
3167 sctx
->b
.b
.delete_vs_state
= si_delete_vs_shader
;
3168 sctx
->b
.b
.delete_fs_state
= si_delete_ps_shader
;
3169 #if HAVE_LLVM >= 0x0305
3170 sctx
->b
.b
.create_gs_state
= si_create_gs_state
;
3171 sctx
->b
.b
.bind_gs_state
= si_bind_gs_shader
;
3172 sctx
->b
.b
.delete_gs_state
= si_delete_gs_shader
;
3175 sctx
->b
.b
.create_sampler_state
= si_create_sampler_state
;
3176 sctx
->b
.b
.bind_sampler_states
= si_bind_sampler_states
;
3177 sctx
->b
.b
.delete_sampler_state
= si_delete_sampler_state
;
3179 sctx
->b
.b
.create_sampler_view
= si_create_sampler_view
;
3180 sctx
->b
.b
.set_sampler_views
= si_set_sampler_views
;
3181 sctx
->b
.b
.sampler_view_destroy
= si_sampler_view_destroy
;
3183 sctx
->b
.b
.set_sample_mask
= si_set_sample_mask
;
3185 sctx
->b
.b
.create_vertex_elements_state
= si_create_vertex_elements
;
3186 sctx
->b
.b
.bind_vertex_elements_state
= si_bind_vertex_elements
;
3187 sctx
->b
.b
.delete_vertex_elements_state
= si_delete_vertex_element
;
3188 sctx
->b
.b
.set_vertex_buffers
= si_set_vertex_buffers
;
3189 sctx
->b
.b
.set_index_buffer
= si_set_index_buffer
;
3191 sctx
->b
.b
.texture_barrier
= si_texture_barrier
;
3192 sctx
->b
.b
.set_polygon_stipple
= si_set_polygon_stipple
;
3193 sctx
->b
.b
.create_surface
= r600_create_surface
;
3194 sctx
->b
.b
.surface_destroy
= r600_surface_destroy
;
3195 sctx
->b
.dma_copy
= si_dma_copy
;
3196 sctx
->b
.set_occlusion_query_state
= si_set_occlusion_query_state
;
3197 sctx
->b
.need_gfx_cs_space
= si_need_gfx_cs_space
;
3199 sctx
->b
.b
.draw_vbo
= si_draw_vbo
;
3202 void si_init_config(struct si_context
*sctx
)
3204 struct si_pm4_state
*pm4
= si_pm4_alloc_state(sctx
);
3209 si_cmd_context_control(pm4
);
3211 si_pm4_set_reg(pm4
, R_028A4C_PA_SC_MODE_CNTL_1
, 0x0);
3213 si_pm4_set_reg(pm4
, R_028A10_VGT_OUTPUT_PATH_CNTL
, 0x0);
3214 si_pm4_set_reg(pm4
, R_028A14_VGT_HOS_CNTL
, 0x0);
3215 si_pm4_set_reg(pm4
, R_028A18_VGT_HOS_MAX_TESS_LEVEL
, 0x0);
3216 si_pm4_set_reg(pm4
, R_028A1C_VGT_HOS_MIN_TESS_LEVEL
, 0x0);
3217 si_pm4_set_reg(pm4
, R_028A20_VGT_HOS_REUSE_DEPTH
, 0x0);
3218 si_pm4_set_reg(pm4
, R_028A24_VGT_GROUP_PRIM_TYPE
, 0x0);
3219 si_pm4_set_reg(pm4
, R_028A28_VGT_GROUP_FIRST_DECR
, 0x0);
3220 si_pm4_set_reg(pm4
, R_028A2C_VGT_GROUP_DECR
, 0x0);
3221 si_pm4_set_reg(pm4
, R_028A30_VGT_GROUP_VECT_0_CNTL
, 0x0);
3222 si_pm4_set_reg(pm4
, R_028A34_VGT_GROUP_VECT_1_CNTL
, 0x0);
3223 si_pm4_set_reg(pm4
, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL
, 0x0);
3224 si_pm4_set_reg(pm4
, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL
, 0x0);
3226 /* FIXME calculate these values somehow ??? */
3227 si_pm4_set_reg(pm4
, R_028A54_VGT_GS_PER_ES
, 0x80);
3228 si_pm4_set_reg(pm4
, R_028A58_VGT_ES_PER_GS
, 0x40);
3229 si_pm4_set_reg(pm4
, R_028A5C_VGT_GS_PER_VS
, 0x2);
3231 si_pm4_set_reg(pm4
, R_028A84_VGT_PRIMITIVEID_EN
, 0x0);
3232 si_pm4_set_reg(pm4
, R_028A8C_VGT_PRIMITIVEID_RESET
, 0x0);
3233 si_pm4_set_reg(pm4
, R_028AB8_VGT_VTX_CNT_EN
, 0);
3234 si_pm4_set_reg(pm4
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
3236 si_pm4_set_reg(pm4
, R_028B60_VGT_GS_VERT_ITEMSIZE_1
, 0);
3237 si_pm4_set_reg(pm4
, R_028B64_VGT_GS_VERT_ITEMSIZE_2
, 0);
3238 si_pm4_set_reg(pm4
, R_028B68_VGT_GS_VERT_ITEMSIZE_3
, 0);
3239 si_pm4_set_reg(pm4
, R_028B90_VGT_GS_INSTANCE_CNT
, 0);
3241 si_pm4_set_reg(pm4
, R_028B94_VGT_STRMOUT_CONFIG
, 0x0);
3242 si_pm4_set_reg(pm4
, R_028B98_VGT_STRMOUT_BUFFER_CONFIG
, 0x0);
3243 if (sctx
->b
.chip_class
== SI
) {
3244 si_pm4_set_reg(pm4
, R_028AA8_IA_MULTI_VGT_PARAM
,
3245 S_028AA8_SWITCH_ON_EOP(1) |
3246 S_028AA8_PARTIAL_VS_WAVE_ON(1) |
3247 S_028AA8_PRIMGROUP_SIZE(63));
3249 si_pm4_set_reg(pm4
, R_028AB4_VGT_REUSE_OFF
, 0x00000000);
3250 si_pm4_set_reg(pm4
, R_028AB8_VGT_VTX_CNT_EN
, 0x0);
3251 if (sctx
->b
.chip_class
< CIK
)
3252 si_pm4_set_reg(pm4
, R_008A14_PA_CL_ENHANCE
, S_008A14_NUM_CLIP_SEQ(3) |
3253 S_008A14_CLIP_VTX_REORDER_ENA(1));
3255 si_pm4_set_reg(pm4
, R_028BD4_PA_SC_CENTROID_PRIORITY_0
, 0x76543210);
3256 si_pm4_set_reg(pm4
, R_028BD8_PA_SC_CENTROID_PRIORITY_1
, 0xfedcba98);
3258 si_pm4_set_reg(pm4
, R_02882C_PA_SU_PRIM_FILTER_CNTL
, 0);
3260 if (sctx
->b
.chip_class
>= CIK
) {
3261 switch (sctx
->screen
->b
.family
) {
3263 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
, 0x16000012);
3264 si_pm4_set_reg(pm4
, R_028354_PA_SC_RASTER_CONFIG_1
, 0x00000000);
3267 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
, 0x3a00161a);
3268 si_pm4_set_reg(pm4
, R_028354_PA_SC_RASTER_CONFIG_1
, 0x0000002e);
3275 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
, 0x00000000);
3276 si_pm4_set_reg(pm4
, R_028354_PA_SC_RASTER_CONFIG_1
, 0x00000000);
3280 switch (sctx
->screen
->b
.family
) {
3283 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
, 0x2a00126a);
3286 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
, 0x0000124a);
3289 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
, 0x00000082);
3292 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
, 0x00000000);
3295 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
, 0x00000000);
3300 si_pm4_set_reg(pm4
, R_028204_PA_SC_WINDOW_SCISSOR_TL
, S_028204_WINDOW_OFFSET_DISABLE(1));
3301 si_pm4_set_reg(pm4
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, S_028240_WINDOW_OFFSET_DISABLE(1));
3302 si_pm4_set_reg(pm4
, R_028244_PA_SC_GENERIC_SCISSOR_BR
,
3303 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
3304 si_pm4_set_reg(pm4
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 0);
3305 si_pm4_set_reg(pm4
, R_028034_PA_SC_SCREEN_SCISSOR_BR
,
3306 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
3308 si_pm4_set_reg(pm4
, R_02820C_PA_SC_CLIPRECT_RULE
, 0xFFFF);
3309 si_pm4_set_reg(pm4
, R_028230_PA_SC_EDGERULE
, 0xAAAAAAAA);
3310 si_pm4_set_reg(pm4
, R_0282D0_PA_SC_VPORT_ZMIN_0
, 0x00000000);
3311 si_pm4_set_reg(pm4
, R_0282D4_PA_SC_VPORT_ZMAX_0
, 0x3F800000);
3312 si_pm4_set_reg(pm4
, R_028818_PA_CL_VTE_CNTL
, 0x0000043F);
3313 si_pm4_set_reg(pm4
, R_028820_PA_CL_NANINF_CNTL
, 0x00000000);
3314 si_pm4_set_reg(pm4
, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ
, 0x3F800000);
3315 si_pm4_set_reg(pm4
, R_028BEC_PA_CL_GB_VERT_DISC_ADJ
, 0x3F800000);
3316 si_pm4_set_reg(pm4
, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ
, 0x3F800000);
3317 si_pm4_set_reg(pm4
, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ
, 0x3F800000);
3318 si_pm4_set_reg(pm4
, R_028020_DB_DEPTH_BOUNDS_MIN
, 0x00000000);
3319 si_pm4_set_reg(pm4
, R_028024_DB_DEPTH_BOUNDS_MAX
, 0x00000000);
3320 si_pm4_set_reg(pm4
, R_028028_DB_STENCIL_CLEAR
, 0x00000000);
3321 si_pm4_set_reg(pm4
, R_02802C_DB_DEPTH_CLEAR
, 0x3F800000);
3322 si_pm4_set_reg(pm4
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 0x0);
3323 si_pm4_set_reg(pm4
, R_028AC4_DB_SRESULTS_COMPARE_STATE1
, 0x0);
3324 si_pm4_set_reg(pm4
, R_028AC8_DB_PRELOAD_CONTROL
, 0x0);
3325 si_pm4_set_reg(pm4
, R_02800C_DB_RENDER_OVERRIDE
,
3326 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE
) |
3327 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE
));
3328 si_pm4_set_reg(pm4
, R_028400_VGT_MAX_VTX_INDX
, ~0);
3329 si_pm4_set_reg(pm4
, R_028404_VGT_MIN_VTX_INDX
, 0);
3331 if (sctx
->b
.chip_class
>= CIK
) {
3332 si_pm4_set_reg(pm4
, R_00B118_SPI_SHADER_PGM_RSRC3_VS
, S_00B118_CU_EN(0xffff));
3333 si_pm4_set_reg(pm4
, R_00B11C_SPI_SHADER_LATE_ALLOC_VS
, S_00B11C_LIMIT(0));
3334 si_pm4_set_reg(pm4
, R_00B01C_SPI_SHADER_PGM_RSRC3_PS
, S_00B01C_CU_EN(0xffff));
3337 si_pm4_set_state(sctx
, init
, pm4
);