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radeonsi: Write htile state to hardware.
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "util/u_memory.h"
28 #include "util/u_framebuffer.h"
29 #include "util/u_blitter.h"
30 #include "util/u_helpers.h"
31 #include "util/u_math.h"
32 #include "util/u_pack_color.h"
33 #include "util/u_upload_mgr.h"
34 #include "util/u_format_s3tc.h"
35 #include "tgsi/tgsi_parse.h"
36 #include "radeonsi_pipe.h"
37 #include "radeonsi_shader.h"
38 #include "si_state.h"
39 #include "../radeon/r600_cs.h"
40 #include "sid.h"
41
42 static uint32_t cik_num_banks(uint32_t nbanks)
43 {
44 switch (nbanks) {
45 case 2:
46 return V_02803C_ADDR_SURF_2_BANK;
47 case 4:
48 return V_02803C_ADDR_SURF_4_BANK;
49 case 8:
50 default:
51 return V_02803C_ADDR_SURF_8_BANK;
52 case 16:
53 return V_02803C_ADDR_SURF_16_BANK;
54 }
55 }
56
57
58 static unsigned cik_tile_split(unsigned tile_split)
59 {
60 switch (tile_split) {
61 case 64:
62 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_64B;
63 break;
64 case 128:
65 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_128B;
66 break;
67 case 256:
68 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_256B;
69 break;
70 case 512:
71 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_512B;
72 break;
73 default:
74 case 1024:
75 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_1KB;
76 break;
77 case 2048:
78 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_2KB;
79 break;
80 case 4096:
81 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_4KB;
82 break;
83 }
84 return tile_split;
85 }
86
87 static unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect)
88 {
89 switch (macro_tile_aspect) {
90 default:
91 case 1:
92 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_1;
93 break;
94 case 2:
95 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_2;
96 break;
97 case 4:
98 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_4;
99 break;
100 case 8:
101 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_8;
102 break;
103 }
104 return macro_tile_aspect;
105 }
106
107 static unsigned cik_bank_wh(unsigned bankwh)
108 {
109 switch (bankwh) {
110 default:
111 case 1:
112 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_1;
113 break;
114 case 2:
115 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_2;
116 break;
117 case 4:
118 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_4;
119 break;
120 case 8:
121 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_8;
122 break;
123 }
124 return bankwh;
125 }
126
127 static unsigned cik_db_pipe_config(unsigned tile_pipes,
128 unsigned num_rbs)
129 {
130 unsigned pipe_config;
131
132 switch (tile_pipes) {
133 case 8:
134 pipe_config = V_02803C_X_ADDR_SURF_P8_32X32_16X16;
135 break;
136 case 4:
137 default:
138 if (num_rbs == 4)
139 pipe_config = V_02803C_X_ADDR_SURF_P4_16X16;
140 else
141 pipe_config = V_02803C_X_ADDR_SURF_P4_8X16;
142 break;
143 case 2:
144 pipe_config = V_02803C_ADDR_SURF_P2;
145 break;
146 }
147 return pipe_config;
148 }
149
150 /*
151 * inferred framebuffer and blender state
152 */
153 static void si_update_fb_blend_state(struct r600_context *rctx)
154 {
155 struct si_pm4_state *pm4;
156 struct si_state_blend *blend = rctx->queued.named.blend;
157 uint32_t mask;
158
159 if (blend == NULL)
160 return;
161
162 pm4 = si_pm4_alloc_state(rctx);
163 if (pm4 == NULL)
164 return;
165
166 mask = (1ULL << ((unsigned)rctx->framebuffer.nr_cbufs * 4)) - 1;
167 mask &= blend->cb_target_mask;
168 si_pm4_set_reg(pm4, R_028238_CB_TARGET_MASK, mask);
169
170 si_pm4_set_state(rctx, fb_blend, pm4);
171 }
172
173 /*
174 * Blender functions
175 */
176
177 static uint32_t si_translate_blend_function(int blend_func)
178 {
179 switch (blend_func) {
180 case PIPE_BLEND_ADD:
181 return V_028780_COMB_DST_PLUS_SRC;
182 case PIPE_BLEND_SUBTRACT:
183 return V_028780_COMB_SRC_MINUS_DST;
184 case PIPE_BLEND_REVERSE_SUBTRACT:
185 return V_028780_COMB_DST_MINUS_SRC;
186 case PIPE_BLEND_MIN:
187 return V_028780_COMB_MIN_DST_SRC;
188 case PIPE_BLEND_MAX:
189 return V_028780_COMB_MAX_DST_SRC;
190 default:
191 R600_ERR("Unknown blend function %d\n", blend_func);
192 assert(0);
193 break;
194 }
195 return 0;
196 }
197
198 static uint32_t si_translate_blend_factor(int blend_fact)
199 {
200 switch (blend_fact) {
201 case PIPE_BLENDFACTOR_ONE:
202 return V_028780_BLEND_ONE;
203 case PIPE_BLENDFACTOR_SRC_COLOR:
204 return V_028780_BLEND_SRC_COLOR;
205 case PIPE_BLENDFACTOR_SRC_ALPHA:
206 return V_028780_BLEND_SRC_ALPHA;
207 case PIPE_BLENDFACTOR_DST_ALPHA:
208 return V_028780_BLEND_DST_ALPHA;
209 case PIPE_BLENDFACTOR_DST_COLOR:
210 return V_028780_BLEND_DST_COLOR;
211 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
212 return V_028780_BLEND_SRC_ALPHA_SATURATE;
213 case PIPE_BLENDFACTOR_CONST_COLOR:
214 return V_028780_BLEND_CONSTANT_COLOR;
215 case PIPE_BLENDFACTOR_CONST_ALPHA:
216 return V_028780_BLEND_CONSTANT_ALPHA;
217 case PIPE_BLENDFACTOR_ZERO:
218 return V_028780_BLEND_ZERO;
219 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
220 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
221 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
222 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
223 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
224 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
225 case PIPE_BLENDFACTOR_INV_DST_COLOR:
226 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
227 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
228 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
229 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
230 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
231 case PIPE_BLENDFACTOR_SRC1_COLOR:
232 return V_028780_BLEND_SRC1_COLOR;
233 case PIPE_BLENDFACTOR_SRC1_ALPHA:
234 return V_028780_BLEND_SRC1_ALPHA;
235 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
236 return V_028780_BLEND_INV_SRC1_COLOR;
237 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
238 return V_028780_BLEND_INV_SRC1_ALPHA;
239 default:
240 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
241 assert(0);
242 break;
243 }
244 return 0;
245 }
246
247 static void *si_create_blend_state_mode(struct pipe_context *ctx,
248 const struct pipe_blend_state *state,
249 unsigned mode)
250 {
251 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
252 struct si_pm4_state *pm4 = &blend->pm4;
253
254 uint32_t color_control;
255
256 if (blend == NULL)
257 return NULL;
258
259 blend->alpha_to_one = state->alpha_to_one;
260
261 color_control = S_028808_MODE(mode);
262 if (state->logicop_enable) {
263 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
264 } else {
265 color_control |= S_028808_ROP3(0xcc);
266 }
267 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
268
269 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
270 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
271 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
272 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
273 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
274 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
275
276 blend->cb_target_mask = 0;
277 for (int i = 0; i < 8; i++) {
278 /* state->rt entries > 0 only written if independent blending */
279 const int j = state->independent_blend_enable ? i : 0;
280
281 unsigned eqRGB = state->rt[j].rgb_func;
282 unsigned srcRGB = state->rt[j].rgb_src_factor;
283 unsigned dstRGB = state->rt[j].rgb_dst_factor;
284 unsigned eqA = state->rt[j].alpha_func;
285 unsigned srcA = state->rt[j].alpha_src_factor;
286 unsigned dstA = state->rt[j].alpha_dst_factor;
287
288 unsigned blend_cntl = 0;
289
290 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
291 blend->cb_target_mask |= state->rt[j].colormask << (4 * i);
292
293 if (!state->rt[j].blend_enable) {
294 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
295 continue;
296 }
297
298 blend_cntl |= S_028780_ENABLE(1);
299 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
300 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
301 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
302
303 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
304 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
305 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
306 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
307 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
308 }
309 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
310 }
311
312 return blend;
313 }
314
315 static void *si_create_blend_state(struct pipe_context *ctx,
316 const struct pipe_blend_state *state)
317 {
318 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
319 }
320
321 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
322 {
323 struct r600_context *rctx = (struct r600_context *)ctx;
324 si_pm4_bind_state(rctx, blend, (struct si_state_blend *)state);
325 si_update_fb_blend_state(rctx);
326 }
327
328 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
329 {
330 struct r600_context *rctx = (struct r600_context *)ctx;
331 si_pm4_delete_state(rctx, blend, (struct si_state_blend *)state);
332 }
333
334 static void si_set_blend_color(struct pipe_context *ctx,
335 const struct pipe_blend_color *state)
336 {
337 struct r600_context *rctx = (struct r600_context *)ctx;
338 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
339
340 if (pm4 == NULL)
341 return;
342
343 si_pm4_set_reg(pm4, R_028414_CB_BLEND_RED, fui(state->color[0]));
344 si_pm4_set_reg(pm4, R_028418_CB_BLEND_GREEN, fui(state->color[1]));
345 si_pm4_set_reg(pm4, R_02841C_CB_BLEND_BLUE, fui(state->color[2]));
346 si_pm4_set_reg(pm4, R_028420_CB_BLEND_ALPHA, fui(state->color[3]));
347
348 si_pm4_set_state(rctx, blend_color, pm4);
349 }
350
351 /*
352 * Clipping, scissors and viewport
353 */
354
355 static void si_set_clip_state(struct pipe_context *ctx,
356 const struct pipe_clip_state *state)
357 {
358 struct r600_context *rctx = (struct r600_context *)ctx;
359 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
360 struct pipe_constant_buffer cb;
361
362 if (pm4 == NULL)
363 return;
364
365 for (int i = 0; i < 6; i++) {
366 si_pm4_set_reg(pm4, R_0285BC_PA_CL_UCP_0_X + i * 16,
367 fui(state->ucp[i][0]));
368 si_pm4_set_reg(pm4, R_0285C0_PA_CL_UCP_0_Y + i * 16,
369 fui(state->ucp[i][1]));
370 si_pm4_set_reg(pm4, R_0285C4_PA_CL_UCP_0_Z + i * 16,
371 fui(state->ucp[i][2]));
372 si_pm4_set_reg(pm4, R_0285C8_PA_CL_UCP_0_W + i * 16,
373 fui(state->ucp[i][3]));
374 }
375
376 cb.buffer = NULL;
377 cb.user_buffer = state->ucp;
378 cb.buffer_offset = 0;
379 cb.buffer_size = 4*4*8;
380 ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, NUM_PIPE_CONST_BUFFERS, &cb);
381 pipe_resource_reference(&cb.buffer, NULL);
382
383 si_pm4_set_state(rctx, clip, pm4);
384 }
385
386 static void si_set_scissor_states(struct pipe_context *ctx,
387 unsigned start_slot,
388 unsigned num_scissors,
389 const struct pipe_scissor_state *state)
390 {
391 struct r600_context *rctx = (struct r600_context *)ctx;
392 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
393 uint32_t tl, br;
394
395 if (pm4 == NULL)
396 return;
397
398 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny);
399 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
400 si_pm4_set_reg(pm4, R_028210_PA_SC_CLIPRECT_0_TL, tl);
401 si_pm4_set_reg(pm4, R_028214_PA_SC_CLIPRECT_0_BR, br);
402 si_pm4_set_reg(pm4, R_028218_PA_SC_CLIPRECT_1_TL, tl);
403 si_pm4_set_reg(pm4, R_02821C_PA_SC_CLIPRECT_1_BR, br);
404 si_pm4_set_reg(pm4, R_028220_PA_SC_CLIPRECT_2_TL, tl);
405 si_pm4_set_reg(pm4, R_028224_PA_SC_CLIPRECT_2_BR, br);
406 si_pm4_set_reg(pm4, R_028228_PA_SC_CLIPRECT_3_TL, tl);
407 si_pm4_set_reg(pm4, R_02822C_PA_SC_CLIPRECT_3_BR, br);
408
409 si_pm4_set_state(rctx, scissor, pm4);
410 }
411
412 static void si_set_viewport_states(struct pipe_context *ctx,
413 unsigned start_slot,
414 unsigned num_viewports,
415 const struct pipe_viewport_state *state)
416 {
417 struct r600_context *rctx = (struct r600_context *)ctx;
418 struct si_state_viewport *viewport = CALLOC_STRUCT(si_state_viewport);
419 struct si_pm4_state *pm4 = &viewport->pm4;
420
421 if (viewport == NULL)
422 return;
423
424 viewport->viewport = *state;
425 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000);
426 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000);
427 si_pm4_set_reg(pm4, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
428 si_pm4_set_reg(pm4, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
429 si_pm4_set_reg(pm4, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
430 si_pm4_set_reg(pm4, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
431 si_pm4_set_reg(pm4, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
432 si_pm4_set_reg(pm4, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
433 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
434
435 si_pm4_set_state(rctx, viewport, viewport);
436 }
437
438 /*
439 * inferred state between framebuffer and rasterizer
440 */
441 static void si_update_fb_rs_state(struct r600_context *rctx)
442 {
443 struct si_state_rasterizer *rs = rctx->queued.named.rasterizer;
444 struct si_pm4_state *pm4;
445 unsigned offset_db_fmt_cntl = 0, depth;
446 float offset_units;
447
448 if (!rs || !rctx->framebuffer.zsbuf)
449 return;
450
451 offset_units = rctx->queued.named.rasterizer->offset_units;
452 switch (rctx->framebuffer.zsbuf->texture->format) {
453 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
454 case PIPE_FORMAT_X8Z24_UNORM:
455 case PIPE_FORMAT_Z24X8_UNORM:
456 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
457 depth = -24;
458 offset_units *= 2.0f;
459 break;
460 case PIPE_FORMAT_Z32_FLOAT:
461 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
462 depth = -23;
463 offset_units *= 1.0f;
464 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
465 break;
466 case PIPE_FORMAT_Z16_UNORM:
467 depth = -16;
468 offset_units *= 4.0f;
469 break;
470 default:
471 return;
472 }
473
474 pm4 = si_pm4_alloc_state(rctx);
475
476 if (pm4 == NULL)
477 return;
478
479 /* FIXME some of those reg can be computed with cso */
480 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
481 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
482 fui(rctx->queued.named.rasterizer->offset_scale));
483 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units));
484 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
485 fui(rctx->queued.named.rasterizer->offset_scale));
486 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units));
487 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, offset_db_fmt_cntl);
488
489 si_pm4_set_state(rctx, fb_rs, pm4);
490 }
491
492 /*
493 * Rasterizer
494 */
495
496 static uint32_t si_translate_fill(uint32_t func)
497 {
498 switch(func) {
499 case PIPE_POLYGON_MODE_FILL:
500 return V_028814_X_DRAW_TRIANGLES;
501 case PIPE_POLYGON_MODE_LINE:
502 return V_028814_X_DRAW_LINES;
503 case PIPE_POLYGON_MODE_POINT:
504 return V_028814_X_DRAW_POINTS;
505 default:
506 assert(0);
507 return V_028814_X_DRAW_POINTS;
508 }
509 }
510
511 static void *si_create_rs_state(struct pipe_context *ctx,
512 const struct pipe_rasterizer_state *state)
513 {
514 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
515 struct si_pm4_state *pm4 = &rs->pm4;
516 unsigned tmp;
517 unsigned prov_vtx = 1, polygon_dual_mode;
518 unsigned clip_rule;
519 float psize_min, psize_max;
520
521 if (rs == NULL) {
522 return NULL;
523 }
524
525 rs->two_side = state->light_twoside;
526 rs->multisample_enable = state->multisample;
527 rs->clip_plane_enable = state->clip_plane_enable;
528 rs->line_stipple_enable = state->line_stipple_enable;
529
530 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
531 state->fill_back != PIPE_POLYGON_MODE_FILL);
532
533 if (state->flatshade_first)
534 prov_vtx = 0;
535
536 rs->flatshade = state->flatshade;
537 rs->sprite_coord_enable = state->sprite_coord_enable;
538 rs->pa_sc_line_stipple = state->line_stipple_enable ?
539 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
540 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
541 rs->pa_su_sc_mode_cntl =
542 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
543 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
544 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
545 S_028814_FACE(!state->front_ccw) |
546 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
547 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
548 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
549 S_028814_POLY_MODE(polygon_dual_mode) |
550 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
551 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back));
552 rs->pa_cl_clip_cntl =
553 S_028810_PS_UCP_MODE(3) |
554 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
555 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
556 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
557 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
558
559 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
560
561 /* offset */
562 rs->offset_units = state->offset_units;
563 rs->offset_scale = state->offset_scale * 12.0f;
564
565 tmp = S_0286D4_FLAT_SHADE_ENA(1);
566 if (state->sprite_coord_enable) {
567 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
568 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
569 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
570 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
571 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1);
572 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
573 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
574 }
575 }
576 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
577
578 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0x00000000);
579 /* point size 12.4 fixed point */
580 tmp = (unsigned)(state->point_size * 8.0);
581 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
582
583 if (state->point_size_per_vertex) {
584 psize_min = util_get_min_point_size(state);
585 psize_max = 8192;
586 } else {
587 /* Force the point size to be as if the vertex output was disabled. */
588 psize_min = state->point_size;
589 psize_max = state->point_size;
590 }
591 /* Divide by two, because 0.5 = 1 pixel. */
592 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
593 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
594 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
595
596 tmp = (unsigned)state->line_width * 8;
597 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
598 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
599 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
600 S_028A48_MSAA_ENABLE(state->multisample));
601
602 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
603 S_028BE4_PIX_CENTER(state->half_pixel_center) |
604 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
605 si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000);
606 si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000);
607 si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000);
608 si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000);
609
610 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
611 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule);
612
613 return rs;
614 }
615
616 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
617 {
618 struct r600_context *rctx = (struct r600_context *)ctx;
619 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
620
621 if (state == NULL)
622 return;
623
624 // TODO
625 rctx->sprite_coord_enable = rs->sprite_coord_enable;
626 rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
627 rctx->pa_su_sc_mode_cntl = rs->pa_su_sc_mode_cntl;
628
629 si_pm4_bind_state(rctx, rasterizer, rs);
630 si_update_fb_rs_state(rctx);
631 }
632
633 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
634 {
635 struct r600_context *rctx = (struct r600_context *)ctx;
636 si_pm4_delete_state(rctx, rasterizer, (struct si_state_rasterizer *)state);
637 }
638
639 /*
640 * infeered state between dsa and stencil ref
641 */
642 static void si_update_dsa_stencil_ref(struct r600_context *rctx)
643 {
644 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
645 struct pipe_stencil_ref *ref = &rctx->stencil_ref;
646 struct si_state_dsa *dsa = rctx->queued.named.dsa;
647
648 if (pm4 == NULL)
649 return;
650
651 si_pm4_set_reg(pm4, R_028430_DB_STENCILREFMASK,
652 S_028430_STENCILTESTVAL(ref->ref_value[0]) |
653 S_028430_STENCILMASK(dsa->valuemask[0]) |
654 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
655 S_028430_STENCILOPVAL(1));
656 si_pm4_set_reg(pm4, R_028434_DB_STENCILREFMASK_BF,
657 S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
658 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
659 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
660 S_028434_STENCILOPVAL_BF(1));
661
662 si_pm4_set_state(rctx, dsa_stencil_ref, pm4);
663 }
664
665 static void si_set_pipe_stencil_ref(struct pipe_context *ctx,
666 const struct pipe_stencil_ref *state)
667 {
668 struct r600_context *rctx = (struct r600_context *)ctx;
669 rctx->stencil_ref = *state;
670 si_update_dsa_stencil_ref(rctx);
671 }
672
673
674 /*
675 * DSA
676 */
677
678 static uint32_t si_translate_stencil_op(int s_op)
679 {
680 switch (s_op) {
681 case PIPE_STENCIL_OP_KEEP:
682 return V_02842C_STENCIL_KEEP;
683 case PIPE_STENCIL_OP_ZERO:
684 return V_02842C_STENCIL_ZERO;
685 case PIPE_STENCIL_OP_REPLACE:
686 return V_02842C_STENCIL_REPLACE_TEST;
687 case PIPE_STENCIL_OP_INCR:
688 return V_02842C_STENCIL_ADD_CLAMP;
689 case PIPE_STENCIL_OP_DECR:
690 return V_02842C_STENCIL_SUB_CLAMP;
691 case PIPE_STENCIL_OP_INCR_WRAP:
692 return V_02842C_STENCIL_ADD_WRAP;
693 case PIPE_STENCIL_OP_DECR_WRAP:
694 return V_02842C_STENCIL_SUB_WRAP;
695 case PIPE_STENCIL_OP_INVERT:
696 return V_02842C_STENCIL_INVERT;
697 default:
698 R600_ERR("Unknown stencil op %d", s_op);
699 assert(0);
700 break;
701 }
702 return 0;
703 }
704
705 static void *si_create_dsa_state(struct pipe_context *ctx,
706 const struct pipe_depth_stencil_alpha_state *state)
707 {
708 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
709 struct si_pm4_state *pm4 = &dsa->pm4;
710 unsigned db_depth_control;
711 unsigned db_render_control;
712 uint32_t db_stencil_control = 0;
713
714 if (dsa == NULL) {
715 return NULL;
716 }
717
718 dsa->valuemask[0] = state->stencil[0].valuemask;
719 dsa->valuemask[1] = state->stencil[1].valuemask;
720 dsa->writemask[0] = state->stencil[0].writemask;
721 dsa->writemask[1] = state->stencil[1].writemask;
722
723 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
724 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
725 S_028800_ZFUNC(state->depth.func);
726
727 /* stencil */
728 if (state->stencil[0].enabled) {
729 db_depth_control |= S_028800_STENCIL_ENABLE(1);
730 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
731 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
732 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
733 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
734
735 if (state->stencil[1].enabled) {
736 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
737 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
738 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
739 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
740 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
741 }
742 }
743
744 /* alpha */
745 if (state->alpha.enabled) {
746 dsa->alpha_func = state->alpha.func;
747 dsa->alpha_ref = state->alpha.ref_value;
748
749 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
750 SI_SGPR_ALPHA_REF * 4, fui(dsa->alpha_ref));
751 } else {
752 dsa->alpha_func = PIPE_FUNC_ALWAYS;
753 }
754
755 /* misc */
756 db_render_control = 0;
757 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, 0x00000000);
758 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, 0x00000000);
759 si_pm4_set_reg(pm4, R_028028_DB_STENCIL_CLEAR, 0x00000000);
760 si_pm4_set_reg(pm4, R_02802C_DB_DEPTH_CLEAR, 0x3F800000);
761 //si_pm4_set_reg(pm4, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control);
762 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
763 si_pm4_set_reg(pm4, R_028000_DB_RENDER_CONTROL, db_render_control);
764 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
765 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
766 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
767 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
768
769 return dsa;
770 }
771
772 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
773 {
774 struct r600_context *rctx = (struct r600_context *)ctx;
775 struct si_state_dsa *dsa = state;
776
777 if (state == NULL)
778 return;
779
780 si_pm4_bind_state(rctx, dsa, dsa);
781 si_update_dsa_stencil_ref(rctx);
782 }
783
784 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
785 {
786 struct r600_context *rctx = (struct r600_context *)ctx;
787 si_pm4_delete_state(rctx, dsa, (struct si_state_dsa *)state);
788 }
789
790 static void *si_create_db_flush_dsa(struct r600_context *rctx, bool copy_depth,
791 bool copy_stencil, int sample)
792 {
793 struct pipe_depth_stencil_alpha_state dsa;
794 struct si_state_dsa *state;
795
796 memset(&dsa, 0, sizeof(dsa));
797
798 state = rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa);
799 if (copy_depth || copy_stencil) {
800 si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL,
801 S_028000_DEPTH_COPY(copy_depth) |
802 S_028000_STENCIL_COPY(copy_stencil) |
803 S_028000_COPY_CENTROID(1) |
804 S_028000_COPY_SAMPLE(sample));
805 } else {
806 si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL,
807 S_028000_DEPTH_COMPRESS_DISABLE(1) |
808 S_028000_STENCIL_COMPRESS_DISABLE(1));
809 si_pm4_set_reg(&state->pm4, R_02800C_DB_RENDER_OVERRIDE,
810 S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
811 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
812 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE) |
813 S_02800C_DISABLE_TILE_RATE_TILES(1));
814 }
815
816 return state;
817 }
818
819 /*
820 * format translation
821 */
822 static uint32_t si_translate_colorformat(enum pipe_format format)
823 {
824 const struct util_format_description *desc = util_format_description(format);
825
826 #define HAS_SIZE(x,y,z,w) \
827 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
828 desc->channel[2].size == (z) && desc->channel[3].size == (w))
829
830 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
831 return V_028C70_COLOR_10_11_11;
832
833 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
834 return V_028C70_COLOR_INVALID;
835
836 switch (desc->nr_channels) {
837 case 1:
838 switch (desc->channel[0].size) {
839 case 8:
840 return V_028C70_COLOR_8;
841 case 16:
842 return V_028C70_COLOR_16;
843 case 32:
844 return V_028C70_COLOR_32;
845 }
846 break;
847 case 2:
848 if (desc->channel[0].size == desc->channel[1].size) {
849 switch (desc->channel[0].size) {
850 case 8:
851 return V_028C70_COLOR_8_8;
852 case 16:
853 return V_028C70_COLOR_16_16;
854 case 32:
855 return V_028C70_COLOR_32_32;
856 }
857 } else if (HAS_SIZE(8,24,0,0)) {
858 return V_028C70_COLOR_24_8;
859 } else if (HAS_SIZE(24,8,0,0)) {
860 return V_028C70_COLOR_8_24;
861 }
862 break;
863 case 3:
864 if (HAS_SIZE(5,6,5,0)) {
865 return V_028C70_COLOR_5_6_5;
866 } else if (HAS_SIZE(32,8,24,0)) {
867 return V_028C70_COLOR_X24_8_32_FLOAT;
868 }
869 break;
870 case 4:
871 if (desc->channel[0].size == desc->channel[1].size &&
872 desc->channel[0].size == desc->channel[2].size &&
873 desc->channel[0].size == desc->channel[3].size) {
874 switch (desc->channel[0].size) {
875 case 4:
876 return V_028C70_COLOR_4_4_4_4;
877 case 8:
878 return V_028C70_COLOR_8_8_8_8;
879 case 16:
880 return V_028C70_COLOR_16_16_16_16;
881 case 32:
882 return V_028C70_COLOR_32_32_32_32;
883 }
884 } else if (HAS_SIZE(5,5,5,1)) {
885 return V_028C70_COLOR_1_5_5_5;
886 } else if (HAS_SIZE(10,10,10,2)) {
887 return V_028C70_COLOR_2_10_10_10;
888 }
889 break;
890 }
891 return V_028C70_COLOR_INVALID;
892 }
893
894 static uint32_t si_translate_colorswap(enum pipe_format format)
895 {
896 const struct util_format_description *desc = util_format_description(format);
897
898 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == UTIL_FORMAT_SWIZZLE_##swz)
899
900 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
901 return V_028C70_SWAP_STD;
902
903 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
904 return ~0;
905
906 switch (desc->nr_channels) {
907 case 1:
908 if (HAS_SWIZZLE(0,X))
909 return V_028C70_SWAP_STD; /* X___ */
910 else if (HAS_SWIZZLE(3,X))
911 return V_028C70_SWAP_ALT_REV; /* ___X */
912 break;
913 case 2:
914 if ((HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,Y)) ||
915 (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,NONE)) ||
916 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,Y)))
917 return V_028C70_SWAP_STD; /* XY__ */
918 else if ((HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,X)) ||
919 (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,NONE)) ||
920 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,X)))
921 return V_028C70_SWAP_STD_REV; /* YX__ */
922 else if (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(3,Y))
923 return V_028C70_SWAP_ALT; /* X__Y */
924 break;
925 case 3:
926 if (HAS_SWIZZLE(0,X))
927 return V_028C70_SWAP_STD; /* XYZ */
928 else if (HAS_SWIZZLE(0,Z))
929 return V_028C70_SWAP_STD_REV; /* ZYX */
930 break;
931 case 4:
932 /* check the middle channels, the 1st and 4th channel can be NONE */
933 if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,Z))
934 return V_028C70_SWAP_STD; /* XYZW */
935 else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,Y))
936 return V_028C70_SWAP_STD_REV; /* WZYX */
937 else if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,X))
938 return V_028C70_SWAP_ALT; /* ZYXW */
939 else if (HAS_SWIZZLE(1,X) && HAS_SWIZZLE(2,Y))
940 return V_028C70_SWAP_ALT_REV; /* WXYZ */
941 break;
942 }
943 return ~0U;
944 }
945
946 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
947 {
948 if (R600_BIG_ENDIAN) {
949 switch(colorformat) {
950 /* 8-bit buffers. */
951 case V_028C70_COLOR_8:
952 return V_028C70_ENDIAN_NONE;
953
954 /* 16-bit buffers. */
955 case V_028C70_COLOR_5_6_5:
956 case V_028C70_COLOR_1_5_5_5:
957 case V_028C70_COLOR_4_4_4_4:
958 case V_028C70_COLOR_16:
959 case V_028C70_COLOR_8_8:
960 return V_028C70_ENDIAN_8IN16;
961
962 /* 32-bit buffers. */
963 case V_028C70_COLOR_8_8_8_8:
964 case V_028C70_COLOR_2_10_10_10:
965 case V_028C70_COLOR_8_24:
966 case V_028C70_COLOR_24_8:
967 case V_028C70_COLOR_16_16:
968 return V_028C70_ENDIAN_8IN32;
969
970 /* 64-bit buffers. */
971 case V_028C70_COLOR_16_16_16_16:
972 return V_028C70_ENDIAN_8IN16;
973
974 case V_028C70_COLOR_32_32:
975 return V_028C70_ENDIAN_8IN32;
976
977 /* 128-bit buffers. */
978 case V_028C70_COLOR_32_32_32_32:
979 return V_028C70_ENDIAN_8IN32;
980 default:
981 return V_028C70_ENDIAN_NONE; /* Unsupported. */
982 }
983 } else {
984 return V_028C70_ENDIAN_NONE;
985 }
986 }
987
988 /* Returns the size in bits of the widest component of a CB format */
989 static unsigned si_colorformat_max_comp_size(uint32_t colorformat)
990 {
991 switch(colorformat) {
992 case V_028C70_COLOR_4_4_4_4:
993 return 4;
994
995 case V_028C70_COLOR_1_5_5_5:
996 case V_028C70_COLOR_5_5_5_1:
997 return 5;
998
999 case V_028C70_COLOR_5_6_5:
1000 return 6;
1001
1002 case V_028C70_COLOR_8:
1003 case V_028C70_COLOR_8_8:
1004 case V_028C70_COLOR_8_8_8_8:
1005 return 8;
1006
1007 case V_028C70_COLOR_10_10_10_2:
1008 case V_028C70_COLOR_2_10_10_10:
1009 return 10;
1010
1011 case V_028C70_COLOR_10_11_11:
1012 case V_028C70_COLOR_11_11_10:
1013 return 11;
1014
1015 case V_028C70_COLOR_16:
1016 case V_028C70_COLOR_16_16:
1017 case V_028C70_COLOR_16_16_16_16:
1018 return 16;
1019
1020 case V_028C70_COLOR_8_24:
1021 case V_028C70_COLOR_24_8:
1022 return 24;
1023
1024 case V_028C70_COLOR_32:
1025 case V_028C70_COLOR_32_32:
1026 case V_028C70_COLOR_32_32_32_32:
1027 case V_028C70_COLOR_X24_8_32_FLOAT:
1028 return 32;
1029 }
1030
1031 assert(!"Unknown maximum component size");
1032 return 0;
1033 }
1034
1035 static uint32_t si_translate_dbformat(enum pipe_format format)
1036 {
1037 switch (format) {
1038 case PIPE_FORMAT_Z16_UNORM:
1039 return V_028040_Z_16;
1040 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1041 case PIPE_FORMAT_X8Z24_UNORM:
1042 case PIPE_FORMAT_Z24X8_UNORM:
1043 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1044 return V_028040_Z_24; /* deprecated on SI */
1045 case PIPE_FORMAT_Z32_FLOAT:
1046 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1047 return V_028040_Z_32_FLOAT;
1048 default:
1049 return V_028040_Z_INVALID;
1050 }
1051 }
1052
1053 /*
1054 * Texture translation
1055 */
1056
1057 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1058 enum pipe_format format,
1059 const struct util_format_description *desc,
1060 int first_non_void)
1061 {
1062 struct r600_screen *rscreen = (struct r600_screen*)screen;
1063 bool enable_s3tc = rscreen->b.info.drm_minor >= 31;
1064 boolean uniform = TRUE;
1065 int i;
1066
1067 /* Colorspace (return non-RGB formats directly). */
1068 switch (desc->colorspace) {
1069 /* Depth stencil formats */
1070 case UTIL_FORMAT_COLORSPACE_ZS:
1071 switch (format) {
1072 case PIPE_FORMAT_Z16_UNORM:
1073 return V_008F14_IMG_DATA_FORMAT_16;
1074 case PIPE_FORMAT_X24S8_UINT:
1075 case PIPE_FORMAT_Z24X8_UNORM:
1076 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1077 return V_008F14_IMG_DATA_FORMAT_8_24;
1078 case PIPE_FORMAT_X8Z24_UNORM:
1079 case PIPE_FORMAT_S8X24_UINT:
1080 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1081 return V_008F14_IMG_DATA_FORMAT_24_8;
1082 case PIPE_FORMAT_S8_UINT:
1083 return V_008F14_IMG_DATA_FORMAT_8;
1084 case PIPE_FORMAT_Z32_FLOAT:
1085 return V_008F14_IMG_DATA_FORMAT_32;
1086 case PIPE_FORMAT_X32_S8X24_UINT:
1087 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1088 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1089 default:
1090 goto out_unknown;
1091 }
1092
1093 case UTIL_FORMAT_COLORSPACE_YUV:
1094 goto out_unknown; /* TODO */
1095
1096 case UTIL_FORMAT_COLORSPACE_SRGB:
1097 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1098 goto out_unknown;
1099 break;
1100
1101 default:
1102 break;
1103 }
1104
1105 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1106 if (!enable_s3tc)
1107 goto out_unknown;
1108
1109 switch (format) {
1110 case PIPE_FORMAT_RGTC1_SNORM:
1111 case PIPE_FORMAT_LATC1_SNORM:
1112 case PIPE_FORMAT_RGTC1_UNORM:
1113 case PIPE_FORMAT_LATC1_UNORM:
1114 return V_008F14_IMG_DATA_FORMAT_BC4;
1115 case PIPE_FORMAT_RGTC2_SNORM:
1116 case PIPE_FORMAT_LATC2_SNORM:
1117 case PIPE_FORMAT_RGTC2_UNORM:
1118 case PIPE_FORMAT_LATC2_UNORM:
1119 return V_008F14_IMG_DATA_FORMAT_BC5;
1120 default:
1121 goto out_unknown;
1122 }
1123 }
1124
1125 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1126
1127 if (!enable_s3tc)
1128 goto out_unknown;
1129
1130 if (!util_format_s3tc_enabled) {
1131 goto out_unknown;
1132 }
1133
1134 switch (format) {
1135 case PIPE_FORMAT_DXT1_RGB:
1136 case PIPE_FORMAT_DXT1_RGBA:
1137 case PIPE_FORMAT_DXT1_SRGB:
1138 case PIPE_FORMAT_DXT1_SRGBA:
1139 return V_008F14_IMG_DATA_FORMAT_BC1;
1140 case PIPE_FORMAT_DXT3_RGBA:
1141 case PIPE_FORMAT_DXT3_SRGBA:
1142 return V_008F14_IMG_DATA_FORMAT_BC2;
1143 case PIPE_FORMAT_DXT5_RGBA:
1144 case PIPE_FORMAT_DXT5_SRGBA:
1145 return V_008F14_IMG_DATA_FORMAT_BC3;
1146 default:
1147 goto out_unknown;
1148 }
1149 }
1150
1151 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1152 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1153 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1154 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1155 }
1156
1157 /* R8G8Bx_SNORM - TODO CxV8U8 */
1158
1159 /* See whether the components are of the same size. */
1160 for (i = 1; i < desc->nr_channels; i++) {
1161 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1162 }
1163
1164 /* Non-uniform formats. */
1165 if (!uniform) {
1166 switch(desc->nr_channels) {
1167 case 3:
1168 if (desc->channel[0].size == 5 &&
1169 desc->channel[1].size == 6 &&
1170 desc->channel[2].size == 5) {
1171 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1172 }
1173 goto out_unknown;
1174 case 4:
1175 if (desc->channel[0].size == 5 &&
1176 desc->channel[1].size == 5 &&
1177 desc->channel[2].size == 5 &&
1178 desc->channel[3].size == 1) {
1179 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1180 }
1181 if (desc->channel[0].size == 10 &&
1182 desc->channel[1].size == 10 &&
1183 desc->channel[2].size == 10 &&
1184 desc->channel[3].size == 2) {
1185 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1186 }
1187 goto out_unknown;
1188 }
1189 goto out_unknown;
1190 }
1191
1192 if (first_non_void < 0 || first_non_void > 3)
1193 goto out_unknown;
1194
1195 /* uniform formats */
1196 switch (desc->channel[first_non_void].size) {
1197 case 4:
1198 switch (desc->nr_channels) {
1199 #if 0 /* Not supported for render targets */
1200 case 2:
1201 return V_008F14_IMG_DATA_FORMAT_4_4;
1202 #endif
1203 case 4:
1204 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1205 }
1206 break;
1207 case 8:
1208 switch (desc->nr_channels) {
1209 case 1:
1210 return V_008F14_IMG_DATA_FORMAT_8;
1211 case 2:
1212 return V_008F14_IMG_DATA_FORMAT_8_8;
1213 case 4:
1214 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1215 }
1216 break;
1217 case 16:
1218 switch (desc->nr_channels) {
1219 case 1:
1220 return V_008F14_IMG_DATA_FORMAT_16;
1221 case 2:
1222 return V_008F14_IMG_DATA_FORMAT_16_16;
1223 case 4:
1224 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1225 }
1226 break;
1227 case 32:
1228 switch (desc->nr_channels) {
1229 case 1:
1230 return V_008F14_IMG_DATA_FORMAT_32;
1231 case 2:
1232 return V_008F14_IMG_DATA_FORMAT_32_32;
1233 #if 0 /* Not supported for render targets */
1234 case 3:
1235 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1236 #endif
1237 case 4:
1238 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1239 }
1240 }
1241
1242 out_unknown:
1243 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1244 return ~0;
1245 }
1246
1247 static unsigned si_tex_wrap(unsigned wrap)
1248 {
1249 switch (wrap) {
1250 default:
1251 case PIPE_TEX_WRAP_REPEAT:
1252 return V_008F30_SQ_TEX_WRAP;
1253 case PIPE_TEX_WRAP_CLAMP:
1254 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1255 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1256 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1257 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1258 return V_008F30_SQ_TEX_CLAMP_BORDER;
1259 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1260 return V_008F30_SQ_TEX_MIRROR;
1261 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1262 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1263 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1264 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1265 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1266 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1267 }
1268 }
1269
1270 static unsigned si_tex_filter(unsigned filter)
1271 {
1272 switch (filter) {
1273 default:
1274 case PIPE_TEX_FILTER_NEAREST:
1275 return V_008F38_SQ_TEX_XY_FILTER_POINT;
1276 case PIPE_TEX_FILTER_LINEAR:
1277 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
1278 }
1279 }
1280
1281 static unsigned si_tex_mipfilter(unsigned filter)
1282 {
1283 switch (filter) {
1284 case PIPE_TEX_MIPFILTER_NEAREST:
1285 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1286 case PIPE_TEX_MIPFILTER_LINEAR:
1287 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1288 default:
1289 case PIPE_TEX_MIPFILTER_NONE:
1290 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1291 }
1292 }
1293
1294 static unsigned si_tex_compare(unsigned compare)
1295 {
1296 switch (compare) {
1297 default:
1298 case PIPE_FUNC_NEVER:
1299 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1300 case PIPE_FUNC_LESS:
1301 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1302 case PIPE_FUNC_EQUAL:
1303 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1304 case PIPE_FUNC_LEQUAL:
1305 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1306 case PIPE_FUNC_GREATER:
1307 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1308 case PIPE_FUNC_NOTEQUAL:
1309 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1310 case PIPE_FUNC_GEQUAL:
1311 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1312 case PIPE_FUNC_ALWAYS:
1313 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1314 }
1315 }
1316
1317 static unsigned si_tex_dim(unsigned dim, unsigned nr_samples)
1318 {
1319 switch (dim) {
1320 default:
1321 case PIPE_TEXTURE_1D:
1322 return V_008F1C_SQ_RSRC_IMG_1D;
1323 case PIPE_TEXTURE_1D_ARRAY:
1324 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1325 case PIPE_TEXTURE_2D:
1326 case PIPE_TEXTURE_RECT:
1327 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1328 V_008F1C_SQ_RSRC_IMG_2D;
1329 case PIPE_TEXTURE_2D_ARRAY:
1330 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1331 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1332 case PIPE_TEXTURE_3D:
1333 return V_008F1C_SQ_RSRC_IMG_3D;
1334 case PIPE_TEXTURE_CUBE:
1335 return V_008F1C_SQ_RSRC_IMG_CUBE;
1336 }
1337 }
1338
1339 /*
1340 * Format support testing
1341 */
1342
1343 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1344 {
1345 return si_translate_texformat(screen, format, util_format_description(format),
1346 util_format_get_first_non_void_channel(format)) != ~0U;
1347 }
1348
1349 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1350 const struct util_format_description *desc,
1351 int first_non_void)
1352 {
1353 unsigned type = desc->channel[first_non_void].type;
1354 int i;
1355
1356 if (type == UTIL_FORMAT_TYPE_FIXED)
1357 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1358
1359 if (desc->nr_channels == 4 &&
1360 desc->channel[0].size == 10 &&
1361 desc->channel[1].size == 10 &&
1362 desc->channel[2].size == 10 &&
1363 desc->channel[3].size == 2)
1364 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1365
1366 /* See whether the components are of the same size. */
1367 for (i = 0; i < desc->nr_channels; i++) {
1368 if (desc->channel[first_non_void].size != desc->channel[i].size)
1369 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1370 }
1371
1372 switch (desc->channel[first_non_void].size) {
1373 case 8:
1374 switch (desc->nr_channels) {
1375 case 1:
1376 return V_008F0C_BUF_DATA_FORMAT_8;
1377 case 2:
1378 return V_008F0C_BUF_DATA_FORMAT_8_8;
1379 case 3:
1380 case 4:
1381 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1382 }
1383 break;
1384 case 16:
1385 switch (desc->nr_channels) {
1386 case 1:
1387 return V_008F0C_BUF_DATA_FORMAT_16;
1388 case 2:
1389 return V_008F0C_BUF_DATA_FORMAT_16_16;
1390 case 3:
1391 case 4:
1392 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1393 }
1394 break;
1395 case 32:
1396 /* From the Southern Islands ISA documentation about MTBUF:
1397 * 'Memory reads of data in memory that is 32 or 64 bits do not
1398 * undergo any format conversion.'
1399 */
1400 if (type != UTIL_FORMAT_TYPE_FLOAT &&
1401 !desc->channel[first_non_void].pure_integer)
1402 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1403
1404 switch (desc->nr_channels) {
1405 case 1:
1406 return V_008F0C_BUF_DATA_FORMAT_32;
1407 case 2:
1408 return V_008F0C_BUF_DATA_FORMAT_32_32;
1409 case 3:
1410 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1411 case 4:
1412 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1413 }
1414 break;
1415 }
1416
1417 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1418 }
1419
1420 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1421 const struct util_format_description *desc,
1422 int first_non_void)
1423 {
1424 switch (desc->channel[first_non_void].type) {
1425 case UTIL_FORMAT_TYPE_SIGNED:
1426 if (desc->channel[first_non_void].normalized)
1427 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1428 else if (desc->channel[first_non_void].pure_integer)
1429 return V_008F0C_BUF_NUM_FORMAT_SINT;
1430 else
1431 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1432 break;
1433 case UTIL_FORMAT_TYPE_UNSIGNED:
1434 if (desc->channel[first_non_void].normalized)
1435 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1436 else if (desc->channel[first_non_void].pure_integer)
1437 return V_008F0C_BUF_NUM_FORMAT_UINT;
1438 else
1439 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1440 break;
1441 case UTIL_FORMAT_TYPE_FLOAT:
1442 default:
1443 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1444 }
1445 }
1446
1447 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
1448 {
1449 const struct util_format_description *desc;
1450 int first_non_void;
1451 unsigned data_format;
1452
1453 desc = util_format_description(format);
1454 first_non_void = util_format_get_first_non_void_channel(format);
1455 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1456 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
1457 }
1458
1459 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1460 {
1461 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1462 si_translate_colorswap(format) != ~0U;
1463 }
1464
1465 static bool si_is_zs_format_supported(enum pipe_format format)
1466 {
1467 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1468 }
1469
1470 boolean si_is_format_supported(struct pipe_screen *screen,
1471 enum pipe_format format,
1472 enum pipe_texture_target target,
1473 unsigned sample_count,
1474 unsigned usage)
1475 {
1476 struct r600_screen *rscreen = (struct r600_screen *)screen;
1477 unsigned retval = 0;
1478
1479 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1480 R600_ERR("r600: unsupported texture type %d\n", target);
1481 return FALSE;
1482 }
1483
1484 if (!util_format_is_supported(format, usage))
1485 return FALSE;
1486
1487 if (sample_count > 1) {
1488 if (HAVE_LLVM < 0x0304)
1489 return FALSE;
1490
1491 /* 2D tiling on CIK is supported since DRM 2.35.0 */
1492 if (rscreen->b.chip_class >= CIK && rscreen->b.info.drm_minor < 35)
1493 return FALSE;
1494
1495 switch (sample_count) {
1496 case 2:
1497 case 4:
1498 case 8:
1499 break;
1500 default:
1501 return FALSE;
1502 }
1503 }
1504
1505 if (usage & PIPE_BIND_SAMPLER_VIEW) {
1506 if (target == PIPE_BUFFER) {
1507 if (si_is_vertex_format_supported(screen, format))
1508 retval |= PIPE_BIND_SAMPLER_VIEW;
1509 } else {
1510 if (si_is_sampler_format_supported(screen, format))
1511 retval |= PIPE_BIND_SAMPLER_VIEW;
1512 }
1513 }
1514
1515 if ((usage & (PIPE_BIND_RENDER_TARGET |
1516 PIPE_BIND_DISPLAY_TARGET |
1517 PIPE_BIND_SCANOUT |
1518 PIPE_BIND_SHARED)) &&
1519 si_is_colorbuffer_format_supported(format)) {
1520 retval |= usage &
1521 (PIPE_BIND_RENDER_TARGET |
1522 PIPE_BIND_DISPLAY_TARGET |
1523 PIPE_BIND_SCANOUT |
1524 PIPE_BIND_SHARED);
1525 }
1526
1527 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1528 si_is_zs_format_supported(format)) {
1529 retval |= PIPE_BIND_DEPTH_STENCIL;
1530 }
1531
1532 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
1533 si_is_vertex_format_supported(screen, format)) {
1534 retval |= PIPE_BIND_VERTEX_BUFFER;
1535 }
1536
1537 if (usage & PIPE_BIND_TRANSFER_READ)
1538 retval |= PIPE_BIND_TRANSFER_READ;
1539 if (usage & PIPE_BIND_TRANSFER_WRITE)
1540 retval |= PIPE_BIND_TRANSFER_WRITE;
1541
1542 return retval == usage;
1543 }
1544
1545 static unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
1546 {
1547 unsigned tile_mode_index = 0;
1548
1549 if (stencil) {
1550 tile_mode_index = rtex->surface.stencil_tiling_index[level];
1551 } else {
1552 tile_mode_index = rtex->surface.tiling_index[level];
1553 }
1554 return tile_mode_index;
1555 }
1556
1557 /*
1558 * framebuffer handling
1559 */
1560
1561 static void si_cb(struct r600_context *rctx, struct si_pm4_state *pm4,
1562 const struct pipe_framebuffer_state *state, int cb)
1563 {
1564 struct r600_texture *rtex;
1565 struct r600_surface *surf;
1566 unsigned level = state->cbufs[cb]->u.tex.level;
1567 unsigned pitch, slice;
1568 unsigned color_info, color_attrib, color_pitch, color_view;
1569 unsigned tile_mode_index;
1570 unsigned format, swap, ntype, endian;
1571 uint64_t offset;
1572 const struct util_format_description *desc;
1573 int i;
1574 unsigned blend_clamp = 0, blend_bypass = 0;
1575 unsigned max_comp_size;
1576
1577 surf = (struct r600_surface *)state->cbufs[cb];
1578 rtex = (struct r600_texture*)state->cbufs[cb]->texture;
1579
1580 offset = rtex->surface.level[level].offset;
1581
1582 /* Layered rendering doesn't work with LINEAR_GENERAL.
1583 * (LINEAR_ALIGNED and others work) */
1584 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) {
1585 assert(state->cbufs[cb]->u.tex.first_layer == state->cbufs[cb]->u.tex.last_layer);
1586 offset += rtex->surface.level[level].slice_size *
1587 state->cbufs[cb]->u.tex.first_layer;
1588 color_view = 0;
1589 } else {
1590 color_view = S_028C6C_SLICE_START(state->cbufs[cb]->u.tex.first_layer) |
1591 S_028C6C_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer);
1592 }
1593
1594 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1595 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1596 if (slice) {
1597 slice = slice - 1;
1598 }
1599
1600 tile_mode_index = si_tile_mode_index(rtex, level, false);
1601
1602 desc = util_format_description(surf->base.format);
1603 for (i = 0; i < 4; i++) {
1604 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1605 break;
1606 }
1607 }
1608 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1609 ntype = V_028C70_NUMBER_FLOAT;
1610 } else {
1611 ntype = V_028C70_NUMBER_UNORM;
1612 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1613 ntype = V_028C70_NUMBER_SRGB;
1614 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1615 if (desc->channel[i].pure_integer) {
1616 ntype = V_028C70_NUMBER_SINT;
1617 } else {
1618 assert(desc->channel[i].normalized);
1619 ntype = V_028C70_NUMBER_SNORM;
1620 }
1621 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1622 if (desc->channel[i].pure_integer) {
1623 ntype = V_028C70_NUMBER_UINT;
1624 } else {
1625 assert(desc->channel[i].normalized);
1626 ntype = V_028C70_NUMBER_UNORM;
1627 }
1628 }
1629 }
1630
1631 format = si_translate_colorformat(surf->base.format);
1632 if (format == V_028C70_COLOR_INVALID) {
1633 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
1634 }
1635 assert(format != V_028C70_COLOR_INVALID);
1636 swap = si_translate_colorswap(surf->base.format);
1637 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1638 endian = V_028C70_ENDIAN_NONE;
1639 } else {
1640 endian = si_colorformat_endian_swap(format);
1641 }
1642
1643 /* blend clamp should be set for all NORM/SRGB types */
1644 if (ntype == V_028C70_NUMBER_UNORM ||
1645 ntype == V_028C70_NUMBER_SNORM ||
1646 ntype == V_028C70_NUMBER_SRGB)
1647 blend_clamp = 1;
1648
1649 /* set blend bypass according to docs if SINT/UINT or
1650 8/24 COLOR variants */
1651 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1652 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1653 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1654 blend_clamp = 0;
1655 blend_bypass = 1;
1656 }
1657
1658 color_info = S_028C70_FORMAT(format) |
1659 S_028C70_COMP_SWAP(swap) |
1660 S_028C70_BLEND_CLAMP(blend_clamp) |
1661 S_028C70_BLEND_BYPASS(blend_bypass) |
1662 S_028C70_NUMBER_TYPE(ntype) |
1663 S_028C70_ENDIAN(endian);
1664
1665 color_pitch = S_028C64_TILE_MAX(pitch);
1666
1667 color_attrib = S_028C74_TILE_MODE_INDEX(tile_mode_index) |
1668 S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == UTIL_FORMAT_SWIZZLE_1);
1669
1670 if (rtex->resource.b.b.nr_samples > 1) {
1671 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1672
1673 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1674 S_028C74_NUM_FRAGMENTS(log_samples);
1675
1676 if (rtex->fmask.size) {
1677 color_info |= S_028C70_COMPRESSION(1);
1678 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
1679
1680 color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(rtex->fmask.tile_mode_index);
1681
1682 if (rctx->b.chip_class == SI) {
1683 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
1684 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1685 }
1686 if (rctx->b.chip_class >= CIK) {
1687 color_pitch |= S_028C64_FMASK_TILE_MAX(rtex->fmask.pitch / 8 - 1);
1688 }
1689 }
1690 }
1691
1692 if (rtex->cmask.size) {
1693 color_info |= S_028C70_FAST_CLEAR(1);
1694 }
1695
1696 offset += r600_resource_va(rctx->b.b.screen, state->cbufs[cb]->texture);
1697 offset >>= 8;
1698
1699 si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE);
1700 si_pm4_set_reg(pm4, R_028C60_CB_COLOR0_BASE + cb * 0x3C, offset);
1701 si_pm4_set_reg(pm4, R_028C64_CB_COLOR0_PITCH + cb * 0x3C, color_pitch);
1702 si_pm4_set_reg(pm4, R_028C68_CB_COLOR0_SLICE + cb * 0x3C, S_028C68_TILE_MAX(slice));
1703 si_pm4_set_reg(pm4, R_028C6C_CB_COLOR0_VIEW + cb * 0x3C, color_view);
1704 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + cb * 0x3C, color_info);
1705 si_pm4_set_reg(pm4, R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C, color_attrib);
1706
1707 if (rtex->cmask.size) {
1708 si_pm4_set_reg(pm4, R_028C7C_CB_COLOR0_CMASK + cb * 0x3C,
1709 offset + (rtex->cmask.offset >> 8));
1710 si_pm4_set_reg(pm4, R_028C80_CB_COLOR0_CMASK_SLICE + cb * 0x3C,
1711 S_028C80_TILE_MAX(rtex->cmask.slice_tile_max));
1712 }
1713 if (rtex->fmask.size) {
1714 si_pm4_set_reg(pm4, R_028C84_CB_COLOR0_FMASK + cb * 0x3C,
1715 offset + (rtex->fmask.offset >> 8));
1716 si_pm4_set_reg(pm4, R_028C88_CB_COLOR0_FMASK_SLICE + cb * 0x3C,
1717 S_028C88_TILE_MAX(rtex->fmask.slice_tile_max));
1718 }
1719
1720 /* set CB_COLOR1_INFO for possible dual-src blending */
1721 if (state->nr_cbufs == 1) {
1722 assert(cb == 0);
1723 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + 1 * 0x3C, color_info);
1724 }
1725
1726 /* Determine pixel shader export format */
1727 max_comp_size = si_colorformat_max_comp_size(format);
1728 if (ntype == V_028C70_NUMBER_SRGB ||
1729 ((ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM) &&
1730 max_comp_size <= 10) ||
1731 (ntype == V_028C70_NUMBER_FLOAT && max_comp_size <= 16)) {
1732 rctx->export_16bpc |= 1 << cb;
1733 /* set SPI_SHADER_COL_FORMAT for possible dual-src blending */
1734 if (state->nr_cbufs == 1)
1735 rctx->export_16bpc |= 1 << 1;
1736 }
1737 }
1738
1739 /* Update register(s) containing depth buffer and draw state. */
1740 void si_update_db_draw_state(struct r600_context *rctx, struct r600_surface *zsbuf)
1741 {
1742 struct si_pm4_state *pm4;
1743 uint32_t db_render_override;
1744 boolean hiz_enable = false;
1745
1746 pm4 = si_pm4_alloc_state(rctx);
1747 if (pm4 == NULL) {
1748 return;
1749 }
1750
1751 /* db */
1752
1753 /* TODO HiS aka stencil buffer htile goes here */
1754 db_render_override = S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
1755 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
1756
1757 /* HiZ aka depth buffer htile */
1758 if (zsbuf && zsbuf->base.texture) {
1759 struct r600_texture *rtex = (struct r600_texture*)zsbuf->base.texture;
1760 uint level = zsbuf->base.u.tex.level;
1761 /* use htile only for first level */
1762 hiz_enable = rtex->htile_buffer && !level;
1763 }
1764 if (hiz_enable) {
1765 db_render_override |= S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_OFF);
1766 } else {
1767 db_render_override |= S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE);
1768 }
1769
1770 /* draw */
1771
1772 if (rctx->num_cs_dw_nontimer_queries_suspend) {
1773 db_render_override |= S_02800C_NOOP_CULL_DISABLE(1);
1774 }
1775
1776 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
1777 si_pm4_set_state(rctx, db_draw, pm4);
1778 }
1779
1780 static void si_db(struct r600_context *rctx, struct si_pm4_state *pm4,
1781 const struct pipe_framebuffer_state *state)
1782 {
1783 struct r600_screen *rscreen = rctx->screen;
1784 struct r600_texture *rtex;
1785 struct r600_surface *surf;
1786 unsigned level, pitch, slice, format, tile_mode_index, array_mode;
1787 unsigned macro_aspect, tile_split, stile_split, bankh, bankw, nbanks, pipe_config;
1788 uint32_t z_info, s_info, db_depth_info;
1789 uint64_t z_offs, s_offs;
1790 uint32_t db_htile_data_base, db_htile_surface;
1791
1792 if (state->zsbuf == NULL) {
1793 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, S_028040_FORMAT(V_028040_Z_INVALID));
1794 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, S_028044_FORMAT(V_028044_STENCIL_INVALID));
1795 return;
1796 }
1797
1798 surf = (struct r600_surface *)state->zsbuf;
1799 level = surf->base.u.tex.level;
1800 rtex = (struct r600_texture*)surf->base.texture;
1801
1802 format = si_translate_dbformat(rtex->resource.b.b.format);
1803
1804 if (format == V_028040_Z_INVALID) {
1805 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
1806 }
1807 assert(format != V_028040_Z_INVALID);
1808
1809 s_offs = z_offs = r600_resource_va(rctx->b.b.screen, surf->base.texture);
1810 z_offs += rtex->surface.level[level].offset;
1811 s_offs += rtex->surface.stencil_level[level].offset;
1812
1813 z_offs >>= 8;
1814 s_offs >>= 8;
1815
1816 pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
1817 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1818 if (slice) {
1819 slice = slice - 1;
1820 }
1821
1822 db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
1823
1824 z_info = S_028040_FORMAT(format);
1825 if (rtex->resource.b.b.nr_samples > 1) {
1826 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
1827 }
1828
1829 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
1830 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
1831 else
1832 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
1833
1834 if (rctx->b.chip_class >= CIK) {
1835 switch (rtex->surface.level[level].mode) {
1836 case RADEON_SURF_MODE_2D:
1837 array_mode = V_02803C_ARRAY_2D_TILED_THIN1;
1838 break;
1839 case RADEON_SURF_MODE_1D:
1840 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1841 case RADEON_SURF_MODE_LINEAR:
1842 default:
1843 array_mode = V_02803C_ARRAY_1D_TILED_THIN1;
1844 break;
1845 }
1846 tile_split = rtex->surface.tile_split;
1847 stile_split = rtex->surface.stencil_tile_split;
1848 macro_aspect = rtex->surface.mtilea;
1849 bankw = rtex->surface.bankw;
1850 bankh = rtex->surface.bankh;
1851 tile_split = cik_tile_split(tile_split);
1852 stile_split = cik_tile_split(stile_split);
1853 macro_aspect = cik_macro_tile_aspect(macro_aspect);
1854 bankw = cik_bank_wh(bankw);
1855 bankh = cik_bank_wh(bankh);
1856 nbanks = cik_num_banks(rscreen->b.tiling_info.num_banks);
1857 pipe_config = cik_db_pipe_config(rscreen->b.info.r600_num_tile_pipes,
1858 rscreen->b.info.r600_num_backends);
1859
1860 db_depth_info |= S_02803C_ARRAY_MODE(array_mode) |
1861 S_02803C_PIPE_CONFIG(pipe_config) |
1862 S_02803C_BANK_WIDTH(bankw) |
1863 S_02803C_BANK_HEIGHT(bankh) |
1864 S_02803C_MACRO_TILE_ASPECT(macro_aspect) |
1865 S_02803C_NUM_BANKS(nbanks);
1866 z_info |= S_028040_TILE_SPLIT(tile_split);
1867 s_info |= S_028044_TILE_SPLIT(stile_split);
1868 } else {
1869 tile_mode_index = si_tile_mode_index(rtex, level, false);
1870 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
1871 tile_mode_index = si_tile_mode_index(rtex, level, true);
1872 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
1873 }
1874
1875 /* HiZ aka depth buffer htile */
1876 /* use htile only for first level */
1877 if (rtex->htile_buffer && !level) {
1878 z_info |= S_028040_TILE_SURFACE_ENABLE(1);
1879 /* Force off means no force, DB_SHADER_CONTROL decides */
1880 uint64_t va = r600_resource_va(&rctx->screen->b.b, &rtex->htile_buffer->b.b);
1881 db_htile_data_base = va >> 8;
1882 db_htile_surface = S_028ABC_FULL_CACHE(1);
1883 } else {
1884 db_htile_data_base = 0;
1885 db_htile_surface = 0;
1886 }
1887
1888 si_pm4_set_reg(pm4, R_028008_DB_DEPTH_VIEW,
1889 S_028008_SLICE_START(state->zsbuf->u.tex.first_layer) |
1890 S_028008_SLICE_MAX(state->zsbuf->u.tex.last_layer));
1891 si_pm4_set_reg(pm4, R_028014_DB_HTILE_DATA_BASE, db_htile_data_base);
1892
1893 si_pm4_set_reg(pm4, R_02803C_DB_DEPTH_INFO, db_depth_info);
1894 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, z_info);
1895 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, s_info);
1896
1897 si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE);
1898 si_pm4_set_reg(pm4, R_028048_DB_Z_READ_BASE, z_offs);
1899 si_pm4_set_reg(pm4, R_02804C_DB_STENCIL_READ_BASE, s_offs);
1900 si_pm4_set_reg(pm4, R_028050_DB_Z_WRITE_BASE, z_offs);
1901 si_pm4_set_reg(pm4, R_028054_DB_STENCIL_WRITE_BASE, s_offs);
1902
1903 si_pm4_set_reg(pm4, R_028058_DB_DEPTH_SIZE, S_028058_PITCH_TILE_MAX(pitch));
1904 si_pm4_set_reg(pm4, R_02805C_DB_DEPTH_SLICE, S_02805C_SLICE_TILE_MAX(slice));
1905
1906 si_pm4_set_reg(pm4, R_028ABC_DB_HTILE_SURFACE, db_htile_surface);
1907 }
1908
1909 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1910 (((s0x) & 0xf) | (((s0y) & 0xf) << 4) | \
1911 (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) | \
1912 (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) | \
1913 (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
1914
1915 /* 2xMSAA
1916 * There are two locations (-4, 4), (4, -4). */
1917 static uint32_t sample_locs_2x[] = {
1918 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1919 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1920 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1921 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1922 };
1923 static unsigned max_dist_2x = 4;
1924 /* 4xMSAA
1925 * There are 4 locations: (-2, -2), (2, 2), (-6, 6), (6, -6). */
1926 static uint32_t sample_locs_4x[] = {
1927 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1928 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1929 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1930 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1931 };
1932 static unsigned max_dist_4x = 6;
1933 /* Cayman/SI 8xMSAA */
1934 static uint32_t cm_sample_locs_8x[] = {
1935 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1936 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1937 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1938 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1939 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1940 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1941 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1942 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1943 };
1944 static unsigned cm_max_dist_8x = 8;
1945 /* Cayman/SI 16xMSAA */
1946 static uint32_t cm_sample_locs_16x[] = {
1947 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1948 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1949 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1950 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1951 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1952 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1953 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1954 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1955 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1956 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1957 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1958 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1959 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1960 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1961 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1962 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1963 };
1964 static unsigned cm_max_dist_16x = 8;
1965
1966 static void si_get_sample_position(struct pipe_context *ctx,
1967 unsigned sample_count,
1968 unsigned sample_index,
1969 float *out_value)
1970 {
1971 int offset, index;
1972 struct {
1973 int idx:4;
1974 } val;
1975 switch (sample_count) {
1976 case 1:
1977 default:
1978 out_value[0] = out_value[1] = 0.5;
1979 break;
1980 case 2:
1981 offset = 4 * (sample_index * 2);
1982 val.idx = (sample_locs_2x[0] >> offset) & 0xf;
1983 out_value[0] = (float)(val.idx + 8) / 16.0f;
1984 val.idx = (sample_locs_2x[0] >> (offset + 4)) & 0xf;
1985 out_value[1] = (float)(val.idx + 8) / 16.0f;
1986 break;
1987 case 4:
1988 offset = 4 * (sample_index * 2);
1989 val.idx = (sample_locs_4x[0] >> offset) & 0xf;
1990 out_value[0] = (float)(val.idx + 8) / 16.0f;
1991 val.idx = (sample_locs_4x[0] >> (offset + 4)) & 0xf;
1992 out_value[1] = (float)(val.idx + 8) / 16.0f;
1993 break;
1994 case 8:
1995 offset = 4 * (sample_index % 4 * 2);
1996 index = (sample_index / 4) * 4;
1997 val.idx = (cm_sample_locs_8x[index] >> offset) & 0xf;
1998 out_value[0] = (float)(val.idx + 8) / 16.0f;
1999 val.idx = (cm_sample_locs_8x[index] >> (offset + 4)) & 0xf;
2000 out_value[1] = (float)(val.idx + 8) / 16.0f;
2001 break;
2002 case 16:
2003 offset = 4 * (sample_index % 4 * 2);
2004 index = (sample_index / 4) * 4;
2005 val.idx = (cm_sample_locs_16x[index] >> offset) & 0xf;
2006 out_value[0] = (float)(val.idx + 8) / 16.0f;
2007 val.idx = (cm_sample_locs_16x[index] >> (offset + 4)) & 0xf;
2008 out_value[1] = (float)(val.idx + 8) / 16.0f;
2009 break;
2010 }
2011 }
2012
2013 static void si_set_msaa_state(struct r600_context *rctx, struct si_pm4_state *pm4, int nr_samples)
2014 {
2015 unsigned max_dist = 0;
2016
2017 switch (nr_samples) {
2018 default:
2019 nr_samples = 0;
2020 break;
2021 case 2:
2022 si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_2x[0]);
2023 si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_2x[1]);
2024 si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_2x[2]);
2025 si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_2x[3]);
2026 max_dist = max_dist_2x;
2027 break;
2028 case 4:
2029 si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_4x[0]);
2030 si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_4x[1]);
2031 si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_4x[2]);
2032 si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_4x[3]);
2033 max_dist = max_dist_4x;
2034 break;
2035 case 8:
2036 si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, cm_sample_locs_8x[0]);
2037 si_pm4_set_reg(pm4, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, cm_sample_locs_8x[4]);
2038 si_pm4_set_reg(pm4, R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2, 0);
2039 si_pm4_set_reg(pm4, R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3, 0);
2040 si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, cm_sample_locs_8x[1]);
2041 si_pm4_set_reg(pm4, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, cm_sample_locs_8x[5]);
2042 si_pm4_set_reg(pm4, R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2, 0);
2043 si_pm4_set_reg(pm4, R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3, 0);
2044 si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, cm_sample_locs_8x[2]);
2045 si_pm4_set_reg(pm4, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, cm_sample_locs_8x[6]);
2046 si_pm4_set_reg(pm4, R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2, 0);
2047 si_pm4_set_reg(pm4, R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3, 0);
2048 si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, cm_sample_locs_8x[3]);
2049 si_pm4_set_reg(pm4, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, cm_sample_locs_8x[7]);
2050 max_dist = cm_max_dist_8x;
2051 break;
2052 case 16:
2053 si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, cm_sample_locs_16x[0]);
2054 si_pm4_set_reg(pm4, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, cm_sample_locs_16x[4]);
2055 si_pm4_set_reg(pm4, R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2, cm_sample_locs_16x[8]);
2056 si_pm4_set_reg(pm4, R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3, cm_sample_locs_16x[12]);
2057 si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, cm_sample_locs_16x[1]);
2058 si_pm4_set_reg(pm4, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, cm_sample_locs_16x[5]);
2059 si_pm4_set_reg(pm4, R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2, cm_sample_locs_16x[9]);
2060 si_pm4_set_reg(pm4, R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3, cm_sample_locs_16x[13]);
2061 si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, cm_sample_locs_16x[2]);
2062 si_pm4_set_reg(pm4, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, cm_sample_locs_16x[6]);
2063 si_pm4_set_reg(pm4, R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2, cm_sample_locs_16x[10]);
2064 si_pm4_set_reg(pm4, R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3, cm_sample_locs_16x[14]);
2065 si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, cm_sample_locs_16x[3]);
2066 si_pm4_set_reg(pm4, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, cm_sample_locs_16x[7]);
2067 si_pm4_set_reg(pm4, R_028C30_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2, cm_sample_locs_16x[11]);
2068 si_pm4_set_reg(pm4, R_028C34_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3, cm_sample_locs_16x[15]);
2069 max_dist = cm_max_dist_16x;
2070 break;
2071 }
2072
2073 if (nr_samples > 1) {
2074 unsigned log_samples = util_logbase2(nr_samples);
2075
2076 si_pm4_set_reg(pm4, R_028BDC_PA_SC_LINE_CNTL,
2077 S_028BDC_LAST_PIXEL(1) |
2078 S_028BDC_EXPAND_LINE_WIDTH(1));
2079 si_pm4_set_reg(pm4, R_028BE0_PA_SC_AA_CONFIG,
2080 S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
2081 S_028BE0_MAX_SAMPLE_DIST(max_dist) |
2082 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples));
2083
2084 si_pm4_set_reg(pm4, R_028804_DB_EQAA,
2085 S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
2086 S_028804_PS_ITER_SAMPLES(log_samples) |
2087 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
2088 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples) |
2089 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
2090 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
2091 } else {
2092 si_pm4_set_reg(pm4, R_028BDC_PA_SC_LINE_CNTL, S_028BDC_LAST_PIXEL(1));
2093 si_pm4_set_reg(pm4, R_028BE0_PA_SC_AA_CONFIG, 0);
2094
2095 si_pm4_set_reg(pm4, R_028804_DB_EQAA,
2096 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
2097 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
2098 }
2099 }
2100
2101 static void si_set_framebuffer_state(struct pipe_context *ctx,
2102 const struct pipe_framebuffer_state *state)
2103 {
2104 struct r600_context *rctx = (struct r600_context *)ctx;
2105 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
2106 uint32_t tl, br;
2107 int tl_x, tl_y, br_x, br_y, nr_samples, i;
2108
2109 if (pm4 == NULL)
2110 return;
2111
2112 if (rctx->framebuffer.nr_cbufs) {
2113 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB |
2114 R600_CONTEXT_FLUSH_AND_INV_CB_META;
2115 }
2116 if (rctx->framebuffer.zsbuf) {
2117 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB;
2118 }
2119
2120 util_copy_framebuffer_state(&rctx->framebuffer, state);
2121
2122 /* build states */
2123 rctx->export_16bpc = 0;
2124 rctx->fb_compressed_cb_mask = 0;
2125 for (i = 0; i < state->nr_cbufs; i++) {
2126 struct r600_texture *rtex =
2127 (struct r600_texture*)state->cbufs[i]->texture;
2128
2129 si_cb(rctx, pm4, state, i);
2130
2131 if (rtex->fmask.size || rtex->cmask.size) {
2132 rctx->fb_compressed_cb_mask |= 1 << i;
2133 }
2134 }
2135 for (; i < 8; i++) {
2136 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2137 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2138 }
2139
2140 assert(!(rctx->export_16bpc & ~0xff));
2141 si_db(rctx, pm4, state);
2142
2143 tl_x = 0;
2144 tl_y = 0;
2145 br_x = state->width;
2146 br_y = state->height;
2147
2148 tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
2149 br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
2150
2151 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, tl);
2152 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR, br);
2153 si_pm4_set_reg(pm4, R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl);
2154 si_pm4_set_reg(pm4, R_028254_PA_SC_VPORT_SCISSOR_0_BR, br);
2155 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, tl);
2156 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR, br);
2157 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, tl);
2158 si_pm4_set_reg(pm4, R_028208_PA_SC_WINDOW_SCISSOR_BR, br);
2159 si_pm4_set_reg(pm4, R_028200_PA_SC_WINDOW_OFFSET, 0x00000000);
2160 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2161
2162 if (state->nr_cbufs)
2163 nr_samples = state->cbufs[0]->texture->nr_samples;
2164 else if (state->zsbuf)
2165 nr_samples = state->zsbuf->texture->nr_samples;
2166 else
2167 nr_samples = 0;
2168
2169 si_set_msaa_state(rctx, pm4, nr_samples);
2170 rctx->fb_log_samples = util_logbase2(nr_samples);
2171 rctx->fb_cb0_is_integer = state->nr_cbufs &&
2172 util_format_is_pure_integer(state->cbufs[0]->format);
2173
2174 si_pm4_set_state(rctx, framebuffer, pm4);
2175 si_update_fb_rs_state(rctx);
2176 si_update_fb_blend_state(rctx);
2177 si_update_db_draw_state(rctx, (struct r600_surface *)state->zsbuf);
2178 }
2179
2180 /*
2181 * shaders
2182 */
2183
2184 /* Compute the key for the hw shader variant */
2185 static INLINE void si_shader_selector_key(struct pipe_context *ctx,
2186 struct si_pipe_shader_selector *sel,
2187 union si_shader_key *key)
2188 {
2189 struct r600_context *rctx = (struct r600_context *)ctx;
2190 memset(key, 0, sizeof(*key));
2191
2192 if (sel->type == PIPE_SHADER_VERTEX) {
2193 unsigned i;
2194 if (!rctx->vertex_elements)
2195 return;
2196
2197 for (i = 0; i < rctx->vertex_elements->count; ++i)
2198 key->vs.instance_divisors[i] = rctx->vertex_elements->elements[i].instance_divisor;
2199
2200 if (rctx->queued.named.rasterizer->clip_plane_enable & 0xf0)
2201 key->vs.ucps_enabled |= 0x2;
2202 if (rctx->queued.named.rasterizer->clip_plane_enable & 0xf)
2203 key->vs.ucps_enabled |= 0x1;
2204 } else if (sel->type == PIPE_SHADER_FRAGMENT) {
2205 if (sel->fs_write_all)
2206 key->ps.nr_cbufs = rctx->framebuffer.nr_cbufs;
2207 key->ps.export_16bpc = rctx->export_16bpc;
2208
2209 if (rctx->queued.named.rasterizer) {
2210 key->ps.color_two_side = rctx->queued.named.rasterizer->two_side;
2211 key->ps.flatshade = rctx->queued.named.rasterizer->flatshade;
2212
2213 if (rctx->queued.named.blend) {
2214 key->ps.alpha_to_one = rctx->queued.named.blend->alpha_to_one &&
2215 rctx->queued.named.rasterizer->multisample_enable &&
2216 !rctx->fb_cb0_is_integer;
2217 }
2218 }
2219 if (rctx->queued.named.dsa) {
2220 key->ps.alpha_func = rctx->queued.named.dsa->alpha_func;
2221
2222 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
2223 if (rctx->framebuffer.nr_cbufs &&
2224 rctx->framebuffer.cbufs[0] &&
2225 util_format_is_pure_integer(rctx->framebuffer.cbufs[0]->texture->format))
2226 key->ps.alpha_func = PIPE_FUNC_ALWAYS;
2227 } else {
2228 key->ps.alpha_func = PIPE_FUNC_ALWAYS;
2229 }
2230 }
2231 }
2232
2233 /* Select the hw shader variant depending on the current state.
2234 * (*dirty) is set to 1 if current variant was changed */
2235 int si_shader_select(struct pipe_context *ctx,
2236 struct si_pipe_shader_selector *sel,
2237 unsigned *dirty)
2238 {
2239 union si_shader_key key;
2240 struct si_pipe_shader * shader = NULL;
2241 int r;
2242
2243 si_shader_selector_key(ctx, sel, &key);
2244
2245 /* Check if we don't need to change anything.
2246 * This path is also used for most shaders that don't need multiple
2247 * variants, it will cost just a computation of the key and this
2248 * test. */
2249 if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
2250 return 0;
2251 }
2252
2253 /* lookup if we have other variants in the list */
2254 if (sel->num_shaders > 1) {
2255 struct si_pipe_shader *p = sel->current, *c = p->next_variant;
2256
2257 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
2258 p = c;
2259 c = c->next_variant;
2260 }
2261
2262 if (c) {
2263 p->next_variant = c->next_variant;
2264 shader = c;
2265 }
2266 }
2267
2268 if (unlikely(!shader)) {
2269 shader = CALLOC(1, sizeof(struct si_pipe_shader));
2270 shader->selector = sel;
2271 shader->key = key;
2272
2273 r = si_pipe_shader_create(ctx, shader);
2274 if (unlikely(r)) {
2275 R600_ERR("Failed to build shader variant (type=%u) %d\n",
2276 sel->type, r);
2277 sel->current = NULL;
2278 FREE(shader);
2279 return r;
2280 }
2281
2282 /* We don't know the value of fs_write_all property until we built
2283 * at least one variant, so we may need to recompute the key (include
2284 * rctx->framebuffer.nr_cbufs) after building first variant. */
2285 if (sel->type == PIPE_SHADER_FRAGMENT &&
2286 sel->num_shaders == 0 &&
2287 shader->shader.fs_write_all) {
2288 sel->fs_write_all = 1;
2289 si_shader_selector_key(ctx, sel, &shader->key);
2290 }
2291
2292 sel->num_shaders++;
2293 }
2294
2295 if (dirty)
2296 *dirty = 1;
2297
2298 shader->next_variant = sel->current;
2299 sel->current = shader;
2300
2301 return 0;
2302 }
2303
2304 static void *si_create_shader_state(struct pipe_context *ctx,
2305 const struct pipe_shader_state *state,
2306 unsigned pipe_shader_type)
2307 {
2308 struct si_pipe_shader_selector *sel = CALLOC_STRUCT(si_pipe_shader_selector);
2309 int r;
2310
2311 sel->type = pipe_shader_type;
2312 sel->tokens = tgsi_dup_tokens(state->tokens);
2313 sel->so = state->stream_output;
2314
2315 r = si_shader_select(ctx, sel, NULL);
2316 if (r) {
2317 free(sel);
2318 return NULL;
2319 }
2320
2321 return sel;
2322 }
2323
2324 static void *si_create_fs_state(struct pipe_context *ctx,
2325 const struct pipe_shader_state *state)
2326 {
2327 return si_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
2328 }
2329
2330 static void *si_create_vs_state(struct pipe_context *ctx,
2331 const struct pipe_shader_state *state)
2332 {
2333 return si_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
2334 }
2335
2336 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
2337 {
2338 struct r600_context *rctx = (struct r600_context *)ctx;
2339 struct si_pipe_shader_selector *sel = state;
2340
2341 if (rctx->vs_shader == sel)
2342 return;
2343
2344 rctx->vs_shader = sel;
2345
2346 if (sel && sel->current) {
2347 si_pm4_bind_state(rctx, vs, sel->current->pm4);
2348 rctx->b.streamout.stride_in_dw = sel->so.stride;
2349 } else {
2350 si_pm4_bind_state(rctx, vs, rctx->dummy_pixel_shader->pm4);
2351 }
2352
2353 rctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE;
2354 }
2355
2356 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
2357 {
2358 struct r600_context *rctx = (struct r600_context *)ctx;
2359 struct si_pipe_shader_selector *sel = state;
2360
2361 if (rctx->ps_shader == sel)
2362 return;
2363
2364 rctx->ps_shader = sel;
2365
2366 if (sel && sel->current)
2367 si_pm4_bind_state(rctx, ps, sel->current->pm4);
2368 else
2369 si_pm4_bind_state(rctx, ps, rctx->dummy_pixel_shader->pm4);
2370
2371 rctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE;
2372 }
2373
2374 static void si_delete_shader_selector(struct pipe_context *ctx,
2375 struct si_pipe_shader_selector *sel)
2376 {
2377 struct r600_context *rctx = (struct r600_context *)ctx;
2378 struct si_pipe_shader *p = sel->current, *c;
2379
2380 while (p) {
2381 c = p->next_variant;
2382 si_pm4_delete_state(rctx, vs, p->pm4);
2383 si_pipe_shader_destroy(ctx, p);
2384 free(p);
2385 p = c;
2386 }
2387
2388 free(sel->tokens);
2389 free(sel);
2390 }
2391
2392 static void si_delete_vs_shader(struct pipe_context *ctx, void *state)
2393 {
2394 struct r600_context *rctx = (struct r600_context *)ctx;
2395 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state;
2396
2397 if (rctx->vs_shader == sel) {
2398 rctx->vs_shader = NULL;
2399 }
2400
2401 si_delete_shader_selector(ctx, sel);
2402 }
2403
2404 static void si_delete_ps_shader(struct pipe_context *ctx, void *state)
2405 {
2406 struct r600_context *rctx = (struct r600_context *)ctx;
2407 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state;
2408
2409 if (rctx->ps_shader == sel) {
2410 rctx->ps_shader = NULL;
2411 }
2412
2413 si_delete_shader_selector(ctx, sel);
2414 }
2415
2416 /*
2417 * Samplers
2418 */
2419
2420 static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx,
2421 struct pipe_resource *texture,
2422 const struct pipe_sampler_view *state)
2423 {
2424 struct si_pipe_sampler_view *view = CALLOC_STRUCT(si_pipe_sampler_view);
2425 struct r600_texture *tmp = (struct r600_texture*)texture;
2426 const struct util_format_description *desc;
2427 unsigned format, num_format;
2428 uint32_t pitch = 0;
2429 unsigned char state_swizzle[4], swizzle[4];
2430 unsigned height, depth, width;
2431 enum pipe_format pipe_format = state->format;
2432 struct radeon_surface_level *surflevel;
2433 int first_non_void;
2434 uint64_t va;
2435
2436 if (view == NULL)
2437 return NULL;
2438
2439 /* initialize base object */
2440 view->base = *state;
2441 view->base.texture = NULL;
2442 pipe_resource_reference(&view->base.texture, texture);
2443 view->base.reference.count = 1;
2444 view->base.context = ctx;
2445 view->resource = &tmp->resource;
2446
2447 /* Buffer resource. */
2448 if (texture->target == PIPE_BUFFER) {
2449 unsigned stride;
2450
2451 desc = util_format_description(state->format);
2452 first_non_void = util_format_get_first_non_void_channel(state->format);
2453 stride = desc->block.bits / 8;
2454 va = r600_resource_va(ctx->screen, texture) + state->u.buf.first_element*stride;
2455 format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
2456 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
2457
2458 view->state[0] = va;
2459 view->state[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
2460 S_008F04_STRIDE(stride);
2461 view->state[2] = state->u.buf.last_element + 1 - state->u.buf.first_element;
2462 view->state[3] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2463 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2464 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2465 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2466 S_008F0C_NUM_FORMAT(num_format) |
2467 S_008F0C_DATA_FORMAT(format);
2468 return &view->base;
2469 }
2470
2471 state_swizzle[0] = state->swizzle_r;
2472 state_swizzle[1] = state->swizzle_g;
2473 state_swizzle[2] = state->swizzle_b;
2474 state_swizzle[3] = state->swizzle_a;
2475
2476 surflevel = tmp->surface.level;
2477
2478 /* Texturing with separate depth and stencil. */
2479 if (tmp->is_depth && !tmp->is_flushing_texture) {
2480 switch (pipe_format) {
2481 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2482 pipe_format = PIPE_FORMAT_Z32_FLOAT;
2483 break;
2484 case PIPE_FORMAT_X8Z24_UNORM:
2485 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2486 /* Z24 is always stored like this. */
2487 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
2488 break;
2489 case PIPE_FORMAT_X24S8_UINT:
2490 case PIPE_FORMAT_S8X24_UINT:
2491 case PIPE_FORMAT_X32_S8X24_UINT:
2492 pipe_format = PIPE_FORMAT_S8_UINT;
2493 surflevel = tmp->surface.stencil_level;
2494 break;
2495 default:;
2496 }
2497 }
2498
2499 desc = util_format_description(pipe_format);
2500
2501 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2502 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2503 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2504
2505 switch (pipe_format) {
2506 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2507 case PIPE_FORMAT_X24S8_UINT:
2508 case PIPE_FORMAT_X32_S8X24_UINT:
2509 case PIPE_FORMAT_X8Z24_UNORM:
2510 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
2511 break;
2512 default:
2513 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
2514 }
2515 } else {
2516 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2517 }
2518
2519 first_non_void = util_format_get_first_non_void_channel(pipe_format);
2520
2521 switch (pipe_format) {
2522 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2523 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2524 break;
2525 default:
2526 if (first_non_void < 0) {
2527 if (util_format_is_compressed(pipe_format)) {
2528 switch (pipe_format) {
2529 case PIPE_FORMAT_DXT1_SRGB:
2530 case PIPE_FORMAT_DXT1_SRGBA:
2531 case PIPE_FORMAT_DXT3_SRGBA:
2532 case PIPE_FORMAT_DXT5_SRGBA:
2533 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2534 break;
2535 case PIPE_FORMAT_RGTC1_SNORM:
2536 case PIPE_FORMAT_LATC1_SNORM:
2537 case PIPE_FORMAT_RGTC2_SNORM:
2538 case PIPE_FORMAT_LATC2_SNORM:
2539 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2540 break;
2541 default:
2542 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2543 break;
2544 }
2545 } else {
2546 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2547 }
2548 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
2549 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2550 } else {
2551 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2552
2553 switch (desc->channel[first_non_void].type) {
2554 case UTIL_FORMAT_TYPE_FLOAT:
2555 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2556 break;
2557 case UTIL_FORMAT_TYPE_SIGNED:
2558 if (desc->channel[first_non_void].normalized)
2559 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2560 else if (desc->channel[first_non_void].pure_integer)
2561 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
2562 else
2563 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
2564 break;
2565 case UTIL_FORMAT_TYPE_UNSIGNED:
2566 if (desc->channel[first_non_void].normalized)
2567 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2568 else if (desc->channel[first_non_void].pure_integer)
2569 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
2570 else
2571 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
2572 }
2573 }
2574 }
2575
2576 format = si_translate_texformat(ctx->screen, pipe_format, desc, first_non_void);
2577 if (format == ~0) {
2578 format = 0;
2579 }
2580
2581 /* not supported any more */
2582 //endian = si_colorformat_endian_swap(format);
2583
2584 width = surflevel[0].npix_x;
2585 height = surflevel[0].npix_y;
2586 depth = surflevel[0].npix_z;
2587 pitch = surflevel[0].nblk_x * util_format_get_blockwidth(pipe_format);
2588
2589 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
2590 height = 1;
2591 depth = texture->array_size;
2592 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
2593 depth = texture->array_size;
2594 }
2595
2596 va = r600_resource_va(ctx->screen, texture);
2597 va += surflevel[0].offset;
2598 va += tmp->mipmap_shift * surflevel[texture->last_level].slice_size;
2599 view->state[0] = va >> 8;
2600 view->state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) |
2601 S_008F14_DATA_FORMAT(format) |
2602 S_008F14_NUM_FORMAT(num_format));
2603 view->state[2] = (S_008F18_WIDTH(width - 1) |
2604 S_008F18_HEIGHT(height - 1));
2605 view->state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2606 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2607 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2608 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2609 S_008F1C_BASE_LEVEL(texture->nr_samples > 1 ?
2610 0 : state->u.tex.first_level - tmp->mipmap_shift) |
2611 S_008F1C_LAST_LEVEL(texture->nr_samples > 1 ?
2612 util_logbase2(texture->nr_samples) :
2613 state->u.tex.last_level - tmp->mipmap_shift) |
2614 S_008F1C_TILING_INDEX(si_tile_mode_index(tmp, 0, false)) |
2615 S_008F1C_POW2_PAD(texture->last_level > 0) |
2616 S_008F1C_TYPE(si_tex_dim(texture->target, texture->nr_samples)));
2617 view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
2618 view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2619 S_008F24_LAST_ARRAY(state->u.tex.last_layer));
2620 view->state[6] = 0;
2621 view->state[7] = 0;
2622
2623 /* Initialize the sampler view for FMASK. */
2624 if (tmp->fmask.size) {
2625 uint64_t va = r600_resource_va(ctx->screen, texture) + tmp->fmask.offset;
2626 uint32_t fmask_format;
2627
2628 switch (texture->nr_samples) {
2629 case 2:
2630 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
2631 break;
2632 case 4:
2633 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
2634 break;
2635 case 8:
2636 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
2637 break;
2638 default:
2639 assert(0);
2640 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
2641 }
2642
2643 view->fmask_state[0] = va >> 8;
2644 view->fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
2645 S_008F14_DATA_FORMAT(fmask_format) |
2646 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT);
2647 view->fmask_state[2] = S_008F18_WIDTH(width - 1) |
2648 S_008F18_HEIGHT(height - 1);
2649 view->fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
2650 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
2651 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
2652 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
2653 S_008F1C_TILING_INDEX(tmp->fmask.tile_mode_index) |
2654 S_008F1C_TYPE(si_tex_dim(texture->target, 0));
2655 view->fmask_state[4] = S_008F20_DEPTH(depth - 1) |
2656 S_008F20_PITCH(tmp->fmask.pitch - 1);
2657 view->fmask_state[5] = S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2658 S_008F24_LAST_ARRAY(state->u.tex.last_layer);
2659 view->fmask_state[6] = 0;
2660 view->fmask_state[7] = 0;
2661 }
2662
2663 return &view->base;
2664 }
2665
2666 static void si_sampler_view_destroy(struct pipe_context *ctx,
2667 struct pipe_sampler_view *state)
2668 {
2669 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
2670
2671 pipe_resource_reference(&state->texture, NULL);
2672 FREE(resource);
2673 }
2674
2675 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
2676 {
2677 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
2678 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
2679 (linear_filter &&
2680 (wrap == PIPE_TEX_WRAP_CLAMP ||
2681 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
2682 }
2683
2684 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
2685 {
2686 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
2687 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
2688
2689 return (state->border_color.ui[0] || state->border_color.ui[1] ||
2690 state->border_color.ui[2] || state->border_color.ui[3]) &&
2691 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
2692 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
2693 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
2694 }
2695
2696 static void *si_create_sampler_state(struct pipe_context *ctx,
2697 const struct pipe_sampler_state *state)
2698 {
2699 struct si_pipe_sampler_state *rstate = CALLOC_STRUCT(si_pipe_sampler_state);
2700 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
2701 unsigned border_color_type;
2702
2703 if (rstate == NULL) {
2704 return NULL;
2705 }
2706
2707 if (sampler_state_needs_border_color(state))
2708 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
2709 else
2710 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
2711
2712 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
2713 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
2714 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
2715 (state->max_anisotropy & 0x7) << 9 | /* XXX */
2716 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
2717 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
2718 aniso_flag_offset << 16 | /* XXX */
2719 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map));
2720 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
2721 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
2722 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
2723 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter)) |
2724 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter)) |
2725 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)));
2726 rstate->val[3] = S_008F3C_BORDER_COLOR_TYPE(border_color_type);
2727
2728 if (border_color_type == V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2729 memcpy(rstate->border_color, state->border_color.ui,
2730 sizeof(rstate->border_color));
2731 }
2732
2733 return rstate;
2734 }
2735
2736 /* XXX consider moving this function to si_descriptors.c for gcc to inline
2737 * the si_set_sampler_view calls. LTO might help too. */
2738 static void si_set_sampler_views(struct pipe_context *ctx,
2739 unsigned shader, unsigned start,
2740 unsigned count,
2741 struct pipe_sampler_view **views)
2742 {
2743 struct r600_context *rctx = (struct r600_context *)ctx;
2744 struct r600_textures_info *samplers = &rctx->samplers[shader];
2745 struct si_pipe_sampler_view **rviews = (struct si_pipe_sampler_view **)views;
2746 int i;
2747
2748 if (shader != PIPE_SHADER_VERTEX && shader != PIPE_SHADER_FRAGMENT)
2749 return;
2750
2751 assert(start == 0);
2752
2753 for (i = 0; i < count; i++) {
2754 if (!views[i]) {
2755 samplers->depth_texture_mask &= ~(1 << i);
2756 samplers->compressed_colortex_mask &= ~(1 << i);
2757 si_set_sampler_view(rctx, shader, i, NULL, NULL);
2758 si_set_sampler_view(rctx, shader, FMASK_TEX_OFFSET + i,
2759 NULL, NULL);
2760 continue;
2761 }
2762
2763 si_set_sampler_view(rctx, shader, i, views[i], rviews[i]->state);
2764
2765 if (views[i]->texture->target != PIPE_BUFFER) {
2766 struct r600_texture *rtex =
2767 (struct r600_texture*)views[i]->texture;
2768
2769 if (rtex->is_depth && !rtex->is_flushing_texture) {
2770 samplers->depth_texture_mask |= 1 << i;
2771 } else {
2772 samplers->depth_texture_mask &= ~(1 << i);
2773 }
2774 if (rtex->cmask.size || rtex->fmask.size) {
2775 samplers->compressed_colortex_mask |= 1 << i;
2776 } else {
2777 samplers->compressed_colortex_mask &= ~(1 << i);
2778 }
2779
2780 if (rtex->fmask.size) {
2781 si_set_sampler_view(rctx, shader, FMASK_TEX_OFFSET + i,
2782 views[i], rviews[i]->fmask_state);
2783 } else {
2784 si_set_sampler_view(rctx, shader, FMASK_TEX_OFFSET + i,
2785 NULL, NULL);
2786 }
2787 }
2788 }
2789 for (; i < samplers->n_views; i++) {
2790 samplers->depth_texture_mask &= ~(1 << i);
2791 samplers->compressed_colortex_mask &= ~(1 << i);
2792 si_set_sampler_view(rctx, shader, i, NULL, NULL);
2793 si_set_sampler_view(rctx, shader, FMASK_TEX_OFFSET + i,
2794 NULL, NULL);
2795 }
2796
2797 samplers->n_views = count;
2798 rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE;
2799 }
2800
2801 static struct si_pm4_state *si_set_sampler_states(struct r600_context *rctx, unsigned count,
2802 void **states,
2803 struct r600_textures_info *samplers,
2804 unsigned user_data_reg)
2805 {
2806 struct si_pipe_sampler_state **rstates = (struct si_pipe_sampler_state **)states;
2807 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
2808 uint32_t *border_color_table = NULL;
2809 int i, j;
2810
2811 if (!count)
2812 goto out;
2813
2814 rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE;
2815
2816 si_pm4_sh_data_begin(pm4);
2817 for (i = 0; i < count; i++) {
2818 if (rstates[i] &&
2819 G_008F3C_BORDER_COLOR_TYPE(rstates[i]->val[3]) ==
2820 V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2821 if (!rctx->border_color_table ||
2822 ((rctx->border_color_offset + count - i) &
2823 C_008F3C_BORDER_COLOR_PTR)) {
2824 r600_resource_reference(&rctx->border_color_table, NULL);
2825 rctx->border_color_offset = 0;
2826
2827 rctx->border_color_table =
2828 r600_resource_create_custom(&rctx->screen->b.b,
2829 PIPE_USAGE_STAGING,
2830 4096 * 4 * 4);
2831 }
2832
2833 if (!border_color_table) {
2834 border_color_table =
2835 rctx->b.ws->buffer_map(rctx->border_color_table->cs_buf,
2836 rctx->b.rings.gfx.cs,
2837 PIPE_TRANSFER_WRITE |
2838 PIPE_TRANSFER_UNSYNCHRONIZED);
2839 }
2840
2841 for (j = 0; j < 4; j++) {
2842 border_color_table[4 * rctx->border_color_offset + j] =
2843 util_le32_to_cpu(rstates[i]->border_color[j]);
2844 }
2845
2846 rstates[i]->val[3] &= C_008F3C_BORDER_COLOR_PTR;
2847 rstates[i]->val[3] |= S_008F3C_BORDER_COLOR_PTR(rctx->border_color_offset++);
2848 }
2849
2850 for (j = 0; j < Elements(rstates[i]->val); ++j) {
2851 si_pm4_sh_data_add(pm4, rstates[i] ? rstates[i]->val[j] : 0);
2852 }
2853 }
2854 si_pm4_sh_data_end(pm4, user_data_reg, SI_SGPR_SAMPLER);
2855
2856 if (border_color_table) {
2857 uint64_t va_offset =
2858 r600_resource_va(&rctx->screen->b.b,
2859 (void*)rctx->border_color_table);
2860
2861 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, va_offset >> 8);
2862 if (rctx->b.chip_class >= CIK)
2863 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, va_offset >> 40);
2864 rctx->b.ws->buffer_unmap(rctx->border_color_table->cs_buf);
2865 si_pm4_add_bo(pm4, rctx->border_color_table, RADEON_USAGE_READ);
2866 }
2867
2868 memcpy(samplers->samplers, states, sizeof(void*) * count);
2869
2870 out:
2871 samplers->n_samplers = count;
2872 return pm4;
2873 }
2874
2875 static void si_bind_vs_sampler_states(struct pipe_context *ctx, unsigned count, void **states)
2876 {
2877 struct r600_context *rctx = (struct r600_context *)ctx;
2878 struct si_pm4_state *pm4;
2879
2880 pm4 = si_set_sampler_states(rctx, count, states, &rctx->samplers[PIPE_SHADER_VERTEX],
2881 R_00B130_SPI_SHADER_USER_DATA_VS_0);
2882 si_pm4_set_state(rctx, vs_sampler, pm4);
2883 }
2884
2885 static void si_bind_ps_sampler_states(struct pipe_context *ctx, unsigned count, void **states)
2886 {
2887 struct r600_context *rctx = (struct r600_context *)ctx;
2888 struct si_pm4_state *pm4;
2889
2890 pm4 = si_set_sampler_states(rctx, count, states, &rctx->samplers[PIPE_SHADER_FRAGMENT],
2891 R_00B030_SPI_SHADER_USER_DATA_PS_0);
2892 si_pm4_set_state(rctx, ps_sampler, pm4);
2893 }
2894
2895
2896 static void si_bind_sampler_states(struct pipe_context *ctx, unsigned shader,
2897 unsigned start, unsigned count,
2898 void **states)
2899 {
2900 assert(start == 0);
2901
2902 switch (shader) {
2903 case PIPE_SHADER_VERTEX:
2904 si_bind_vs_sampler_states(ctx, count, states);
2905 break;
2906 case PIPE_SHADER_FRAGMENT:
2907 si_bind_ps_sampler_states(ctx, count, states);
2908 break;
2909 default:
2910 ;
2911 }
2912 }
2913
2914
2915
2916 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
2917 {
2918 struct r600_context *rctx = (struct r600_context *)ctx;
2919 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
2920 uint16_t mask = sample_mask;
2921
2922 if (pm4 == NULL)
2923 return;
2924
2925 si_pm4_set_reg(pm4, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, mask | (mask << 16));
2926 si_pm4_set_reg(pm4, R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, mask | (mask << 16));
2927
2928 si_pm4_set_state(rctx, sample_mask, pm4);
2929 }
2930
2931 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
2932 {
2933 free(state);
2934 }
2935
2936 /*
2937 * Vertex elements & buffers
2938 */
2939
2940 static void *si_create_vertex_elements(struct pipe_context *ctx,
2941 unsigned count,
2942 const struct pipe_vertex_element *elements)
2943 {
2944 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
2945 int i;
2946
2947 assert(count < PIPE_MAX_ATTRIBS);
2948 if (!v)
2949 return NULL;
2950
2951 v->count = count;
2952 for (i = 0; i < count; ++i) {
2953 const struct util_format_description *desc;
2954 unsigned data_format, num_format;
2955 int first_non_void;
2956
2957 desc = util_format_description(elements[i].src_format);
2958 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
2959 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
2960 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
2961
2962 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2963 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2964 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2965 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2966 S_008F0C_NUM_FORMAT(num_format) |
2967 S_008F0C_DATA_FORMAT(data_format);
2968 }
2969 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
2970
2971 return v;
2972 }
2973
2974 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
2975 {
2976 struct r600_context *rctx = (struct r600_context *)ctx;
2977 struct si_vertex_element *v = (struct si_vertex_element*)state;
2978
2979 rctx->vertex_elements = v;
2980 }
2981
2982 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
2983 {
2984 struct r600_context *rctx = (struct r600_context *)ctx;
2985
2986 if (rctx->vertex_elements == state)
2987 rctx->vertex_elements = NULL;
2988 FREE(state);
2989 }
2990
2991 static void si_set_vertex_buffers(struct pipe_context *ctx, unsigned start_slot, unsigned count,
2992 const struct pipe_vertex_buffer *buffers)
2993 {
2994 struct r600_context *rctx = (struct r600_context *)ctx;
2995
2996 util_set_vertex_buffers_count(rctx->vertex_buffer, &rctx->nr_vertex_buffers, buffers, start_slot, count);
2997 }
2998
2999 static void si_set_index_buffer(struct pipe_context *ctx,
3000 const struct pipe_index_buffer *ib)
3001 {
3002 struct r600_context *rctx = (struct r600_context *)ctx;
3003
3004 if (ib) {
3005 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
3006 memcpy(&rctx->index_buffer, ib, sizeof(*ib));
3007 } else {
3008 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
3009 }
3010 }
3011
3012 /*
3013 * Misc
3014 */
3015 static void si_set_polygon_stipple(struct pipe_context *ctx,
3016 const struct pipe_poly_stipple *state)
3017 {
3018 }
3019
3020 static void si_texture_barrier(struct pipe_context *ctx)
3021 {
3022 struct r600_context *rctx = (struct r600_context *)ctx;
3023
3024 rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE |
3025 R600_CONTEXT_FLUSH_AND_INV_CB;
3026 }
3027
3028 static void *si_create_blend_custom(struct r600_context *rctx, unsigned mode)
3029 {
3030 struct pipe_blend_state blend;
3031
3032 memset(&blend, 0, sizeof(blend));
3033 blend.independent_blend_enable = true;
3034 blend.rt[0].colormask = 0xf;
3035 return si_create_blend_state_mode(&rctx->b.b, &blend, mode);
3036 }
3037
3038 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
3039 struct pipe_resource *texture,
3040 const struct pipe_surface *surf_tmpl)
3041 {
3042 struct r600_texture *rtex = (struct r600_texture*)texture;
3043 struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
3044 unsigned level = surf_tmpl->u.tex.level;
3045
3046 if (surface == NULL)
3047 return NULL;
3048
3049 assert(surf_tmpl->u.tex.first_layer <= util_max_layer(texture, surf_tmpl->u.tex.level));
3050 assert(surf_tmpl->u.tex.last_layer <= util_max_layer(texture, surf_tmpl->u.tex.level));
3051
3052 pipe_reference_init(&surface->base.reference, 1);
3053 pipe_resource_reference(&surface->base.texture, texture);
3054 surface->base.context = pipe;
3055 surface->base.format = surf_tmpl->format;
3056 surface->base.width = rtex->surface.level[level].npix_x;
3057 surface->base.height = rtex->surface.level[level].npix_y;
3058 surface->base.texture = texture;
3059 surface->base.u.tex.first_layer = surf_tmpl->u.tex.first_layer;
3060 surface->base.u.tex.last_layer = surf_tmpl->u.tex.last_layer;
3061 surface->base.u.tex.level = level;
3062
3063 return &surface->base;
3064 }
3065
3066 static void r600_surface_destroy(struct pipe_context *pipe,
3067 struct pipe_surface *surface)
3068 {
3069 pipe_resource_reference(&surface->texture, NULL);
3070 FREE(surface);
3071 }
3072
3073 static boolean si_dma_copy(struct pipe_context *ctx,
3074 struct pipe_resource *dst,
3075 unsigned dst_level,
3076 unsigned dst_x, unsigned dst_y, unsigned dst_z,
3077 struct pipe_resource *src,
3078 unsigned src_level,
3079 const struct pipe_box *src_box)
3080 {
3081 /* XXX implement this or share evergreen_dma_blit with r600g */
3082 return FALSE;
3083 }
3084
3085 void si_init_state_functions(struct r600_context *rctx)
3086 {
3087 int i;
3088
3089 rctx->b.b.create_blend_state = si_create_blend_state;
3090 rctx->b.b.bind_blend_state = si_bind_blend_state;
3091 rctx->b.b.delete_blend_state = si_delete_blend_state;
3092 rctx->b.b.set_blend_color = si_set_blend_color;
3093
3094 rctx->b.b.create_rasterizer_state = si_create_rs_state;
3095 rctx->b.b.bind_rasterizer_state = si_bind_rs_state;
3096 rctx->b.b.delete_rasterizer_state = si_delete_rs_state;
3097
3098 rctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
3099 rctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
3100 rctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
3101
3102 for (i = 0; i < 8; i++) {
3103 rctx->custom_dsa_flush_depth_stencil[i] = si_create_db_flush_dsa(rctx, true, true, i);
3104 rctx->custom_dsa_flush_depth[i] = si_create_db_flush_dsa(rctx, true, false, i);
3105 rctx->custom_dsa_flush_stencil[i] = si_create_db_flush_dsa(rctx, false, true, i);
3106 }
3107 rctx->custom_dsa_flush_inplace = si_create_db_flush_dsa(rctx, false, false, 0);
3108 rctx->custom_blend_resolve = si_create_blend_custom(rctx, V_028808_CB_RESOLVE);
3109 rctx->custom_blend_decompress = si_create_blend_custom(rctx, V_028808_CB_FMASK_DECOMPRESS);
3110
3111 rctx->b.b.set_clip_state = si_set_clip_state;
3112 rctx->b.b.set_scissor_states = si_set_scissor_states;
3113 rctx->b.b.set_viewport_states = si_set_viewport_states;
3114 rctx->b.b.set_stencil_ref = si_set_pipe_stencil_ref;
3115
3116 rctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
3117 rctx->b.b.get_sample_position = si_get_sample_position;
3118
3119 rctx->b.b.create_vs_state = si_create_vs_state;
3120 rctx->b.b.create_fs_state = si_create_fs_state;
3121 rctx->b.b.bind_vs_state = si_bind_vs_shader;
3122 rctx->b.b.bind_fs_state = si_bind_ps_shader;
3123 rctx->b.b.delete_vs_state = si_delete_vs_shader;
3124 rctx->b.b.delete_fs_state = si_delete_ps_shader;
3125
3126 rctx->b.b.create_sampler_state = si_create_sampler_state;
3127 rctx->b.b.bind_sampler_states = si_bind_sampler_states;
3128 rctx->b.b.delete_sampler_state = si_delete_sampler_state;
3129
3130 rctx->b.b.create_sampler_view = si_create_sampler_view;
3131 rctx->b.b.set_sampler_views = si_set_sampler_views;
3132 rctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
3133
3134 rctx->b.b.set_sample_mask = si_set_sample_mask;
3135
3136 rctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
3137 rctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
3138 rctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
3139 rctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
3140 rctx->b.b.set_index_buffer = si_set_index_buffer;
3141
3142 rctx->b.b.texture_barrier = si_texture_barrier;
3143 rctx->b.b.set_polygon_stipple = si_set_polygon_stipple;
3144 rctx->b.b.create_surface = r600_create_surface;
3145 rctx->b.b.surface_destroy = r600_surface_destroy;
3146 rctx->b.dma_copy = si_dma_copy;
3147
3148 rctx->b.b.draw_vbo = si_draw_vbo;
3149 }
3150
3151 void si_init_config(struct r600_context *rctx)
3152 {
3153 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
3154
3155 if (pm4 == NULL)
3156 return;
3157
3158 si_cmd_context_control(pm4);
3159
3160 si_pm4_set_reg(pm4, R_028A4C_PA_SC_MODE_CNTL_1, 0x0);
3161
3162 si_pm4_set_reg(pm4, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0);
3163 si_pm4_set_reg(pm4, R_028A14_VGT_HOS_CNTL, 0x0);
3164 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0);
3165 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0);
3166 si_pm4_set_reg(pm4, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0);
3167 si_pm4_set_reg(pm4, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0);
3168 si_pm4_set_reg(pm4, R_028A28_VGT_GROUP_FIRST_DECR, 0x0);
3169 si_pm4_set_reg(pm4, R_028A2C_VGT_GROUP_DECR, 0x0);
3170 si_pm4_set_reg(pm4, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0);
3171 si_pm4_set_reg(pm4, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0);
3172 si_pm4_set_reg(pm4, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0);
3173 si_pm4_set_reg(pm4, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0);
3174 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, 0x0);
3175 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0x0);
3176 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
3177 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3178 si_pm4_set_reg(pm4, R_028B94_VGT_STRMOUT_CONFIG, 0x0);
3179 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
3180 if (rctx->b.chip_class == SI) {
3181 si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM,
3182 S_028AA8_SWITCH_ON_EOP(1) |
3183 S_028AA8_PARTIAL_VS_WAVE_ON(1) |
3184 S_028AA8_PRIMGROUP_SIZE(63));
3185 }
3186 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0x00000000);
3187 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
3188 if (rctx->b.chip_class < CIK)
3189 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
3190 S_008A14_CLIP_VTX_REORDER_ENA(1));
3191
3192 si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, 0);
3193 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
3194 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
3195
3196 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
3197
3198 if (rctx->b.chip_class >= CIK) {
3199 switch (rctx->screen->b.family) {
3200 case CHIP_BONAIRE:
3201 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x16000012);
3202 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000);
3203 break;
3204 case CHIP_HAWAII:
3205 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x3a00161a);
3206 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x0000002e);
3207 break;
3208 case CHIP_KAVERI:
3209 /* XXX todo */
3210 case CHIP_KABINI:
3211 /* XXX todo */
3212 default:
3213 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
3214 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000);
3215 break;
3216 }
3217 } else {
3218 switch (rctx->screen->b.family) {
3219 case CHIP_TAHITI:
3220 case CHIP_PITCAIRN:
3221 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x2a00126a);
3222 break;
3223 case CHIP_VERDE:
3224 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x0000124a);
3225 break;
3226 case CHIP_OLAND:
3227 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000082);
3228 break;
3229 case CHIP_HAINAN:
3230 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
3231 break;
3232 default:
3233 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
3234 break;
3235 }
3236 }
3237
3238 si_pm4_set_state(rctx, init, pm4);
3239 }