2 * Copyright 2012 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "si_build_pm4.h"
29 #include "util/u_dual_blend.h"
30 #include "util/u_format.h"
31 #include "util/u_format_s3tc.h"
32 #include "util/u_memory.h"
33 #include "util/u_resource.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/fast_idiv_by_const.h"
38 unsigned img_format
:9;
40 /* Various formats are only supported with workarounds for vertex fetch,
41 * and some 32_32_32 formats are supported natively, but only for buffers
42 * (possibly with some image support, actually, but no filtering). */
46 #include "gfx10_format_table.h"
48 static unsigned si_map_swizzle(unsigned swizzle
)
52 return V_008F0C_SQ_SEL_Y
;
54 return V_008F0C_SQ_SEL_Z
;
56 return V_008F0C_SQ_SEL_W
;
58 return V_008F0C_SQ_SEL_0
;
60 return V_008F0C_SQ_SEL_1
;
61 default: /* PIPE_SWIZZLE_X */
62 return V_008F0C_SQ_SEL_X
;
66 /* 12.4 fixed-point */
67 static unsigned si_pack_float_12p4(float x
)
70 x
>= 4096 ? 0xffff : x
* 16;
74 * Inferred framebuffer and blender state.
76 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
77 * if there is not enough PS outputs.
79 static void si_emit_cb_render_state(struct si_context
*sctx
)
81 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
82 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
83 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
84 * but you never know. */
85 uint32_t cb_target_mask
= sctx
->framebuffer
.colorbuf_enabled_4bit
&
86 blend
->cb_target_mask
;
89 /* Avoid a hang that happens when dual source blending is enabled
90 * but there is not enough color outputs. This is undefined behavior,
91 * so disable color writes completely.
93 * Reproducible with Unigine Heaven 4.0 and drirc missing.
95 if (blend
->dual_src_blend
&&
96 sctx
->ps_shader
.cso
&&
97 (sctx
->ps_shader
.cso
->info
.colors_written
& 0x3) != 0x3)
100 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
101 * I think we don't have to do anything between IBs.
103 if (sctx
->screen
->dpbb_allowed
&&
104 sctx
->last_cb_target_mask
!= cb_target_mask
) {
105 sctx
->last_cb_target_mask
= cb_target_mask
;
107 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
108 radeon_emit(cs
, EVENT_TYPE(V_028A90_BREAK_BATCH
) | EVENT_INDEX(0));
111 unsigned initial_cdw
= cs
->current
.cdw
;
112 radeon_opt_set_context_reg(sctx
, R_028238_CB_TARGET_MASK
,
113 SI_TRACKED_CB_TARGET_MASK
, cb_target_mask
);
115 if (sctx
->chip_class
>= GFX8
) {
116 /* DCC MSAA workaround.
117 * Alternatively, we can set CB_COLORi_DCC_CONTROL.OVERWRITE_-
118 * COMBINER_DISABLE, but that would be more complicated.
120 bool oc_disable
= blend
->dcc_msaa_corruption_4bit
& cb_target_mask
&&
121 sctx
->framebuffer
.nr_samples
>= 2;
122 unsigned watermark
= sctx
->framebuffer
.dcc_overwrite_combiner_watermark
;
124 radeon_opt_set_context_reg(
125 sctx
, R_028424_CB_DCC_CONTROL
,
126 SI_TRACKED_CB_DCC_CONTROL
,
127 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(sctx
->chip_class
<= GFX9
) |
128 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark
) |
129 S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable
) |
130 S_028424_DISABLE_CONSTANT_ENCODE_REG(sctx
->screen
->info
.has_dcc_constant_encode
));
133 /* RB+ register settings. */
134 if (sctx
->screen
->info
.rbplus_allowed
) {
135 unsigned spi_shader_col_format
=
136 sctx
->ps_shader
.cso
?
137 sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.spi_shader_col_format
: 0;
138 unsigned sx_ps_downconvert
= 0;
139 unsigned sx_blend_opt_epsilon
= 0;
140 unsigned sx_blend_opt_control
= 0;
142 for (i
= 0; i
< sctx
->framebuffer
.state
.nr_cbufs
; i
++) {
143 struct si_surface
*surf
=
144 (struct si_surface
*)sctx
->framebuffer
.state
.cbufs
[i
];
145 unsigned format
, swap
, spi_format
, colormask
;
146 bool has_alpha
, has_rgb
;
149 /* If the color buffer is not set, the driver sets 32_R
150 * as the SPI color format, because the hw doesn't allow
151 * holes between color outputs, so also set this to
154 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_R
<< (i
* 4);
158 format
= G_028C70_FORMAT(surf
->cb_color_info
);
159 swap
= G_028C70_COMP_SWAP(surf
->cb_color_info
);
160 spi_format
= (spi_shader_col_format
>> (i
* 4)) & 0xf;
161 colormask
= (cb_target_mask
>> (i
* 4)) & 0xf;
163 /* Set if RGB and A are present. */
164 has_alpha
= !G_028C74_FORCE_DST_ALPHA_1(surf
->cb_color_attrib
);
166 if (format
== V_028C70_COLOR_8
||
167 format
== V_028C70_COLOR_16
||
168 format
== V_028C70_COLOR_32
)
169 has_rgb
= !has_alpha
;
173 /* Check the colormask and export format. */
174 if (!(colormask
& (PIPE_MASK_RGBA
& ~PIPE_MASK_A
)))
176 if (!(colormask
& PIPE_MASK_A
))
179 if (spi_format
== V_028714_SPI_SHADER_ZERO
) {
184 /* Disable value checking for disabled channels. */
186 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
188 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
190 /* Enable down-conversion for 32bpp and smaller formats. */
192 case V_028C70_COLOR_8
:
193 case V_028C70_COLOR_8_8
:
194 case V_028C70_COLOR_8_8_8_8
:
195 /* For 1 and 2-channel formats, use the superset thereof. */
196 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
||
197 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
198 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
199 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_8_8_8_8
<< (i
* 4);
200 sx_blend_opt_epsilon
|= V_028758_8BIT_FORMAT
<< (i
* 4);
204 case V_028C70_COLOR_5_6_5
:
205 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
206 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_5_6_5
<< (i
* 4);
207 sx_blend_opt_epsilon
|= V_028758_6BIT_FORMAT
<< (i
* 4);
211 case V_028C70_COLOR_1_5_5_5
:
212 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
213 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_1_5_5_5
<< (i
* 4);
214 sx_blend_opt_epsilon
|= V_028758_5BIT_FORMAT
<< (i
* 4);
218 case V_028C70_COLOR_4_4_4_4
:
219 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
220 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_4_4_4_4
<< (i
* 4);
221 sx_blend_opt_epsilon
|= V_028758_4BIT_FORMAT
<< (i
* 4);
225 case V_028C70_COLOR_32
:
226 if (swap
== V_028C70_SWAP_STD
&&
227 spi_format
== V_028714_SPI_SHADER_32_R
)
228 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_R
<< (i
* 4);
229 else if (swap
== V_028C70_SWAP_ALT_REV
&&
230 spi_format
== V_028714_SPI_SHADER_32_AR
)
231 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_A
<< (i
* 4);
234 case V_028C70_COLOR_16
:
235 case V_028C70_COLOR_16_16
:
236 /* For 1-channel formats, use the superset thereof. */
237 if (spi_format
== V_028714_SPI_SHADER_UNORM16_ABGR
||
238 spi_format
== V_028714_SPI_SHADER_SNORM16_ABGR
||
239 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
240 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
241 if (swap
== V_028C70_SWAP_STD
||
242 swap
== V_028C70_SWAP_STD_REV
)
243 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_GR
<< (i
* 4);
245 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_AR
<< (i
* 4);
249 case V_028C70_COLOR_10_11_11
:
250 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
)
251 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_10_11_11
<< (i
* 4);
254 case V_028C70_COLOR_2_10_10_10
:
255 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
256 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_2_10_10_10
<< (i
* 4);
257 sx_blend_opt_epsilon
|= V_028758_10BIT_FORMAT
<< (i
* 4);
263 /* If there are no color outputs, the first color export is
264 * always enabled as 32_R, so also set this to enable RB+.
266 if (!sx_ps_downconvert
)
267 sx_ps_downconvert
= V_028754_SX_RT_EXPORT_32_R
;
269 /* SX_PS_DOWNCONVERT, SX_BLEND_OPT_EPSILON, SX_BLEND_OPT_CONTROL */
270 radeon_opt_set_context_reg3(sctx
, R_028754_SX_PS_DOWNCONVERT
,
271 SI_TRACKED_SX_PS_DOWNCONVERT
,
272 sx_ps_downconvert
, sx_blend_opt_epsilon
,
273 sx_blend_opt_control
);
275 if (initial_cdw
!= cs
->current
.cdw
)
276 sctx
->context_roll
= true;
283 static uint32_t si_translate_blend_function(int blend_func
)
285 switch (blend_func
) {
287 return V_028780_COMB_DST_PLUS_SRC
;
288 case PIPE_BLEND_SUBTRACT
:
289 return V_028780_COMB_SRC_MINUS_DST
;
290 case PIPE_BLEND_REVERSE_SUBTRACT
:
291 return V_028780_COMB_DST_MINUS_SRC
;
293 return V_028780_COMB_MIN_DST_SRC
;
295 return V_028780_COMB_MAX_DST_SRC
;
297 PRINT_ERR("Unknown blend function %d\n", blend_func
);
304 static uint32_t si_translate_blend_factor(int blend_fact
)
306 switch (blend_fact
) {
307 case PIPE_BLENDFACTOR_ONE
:
308 return V_028780_BLEND_ONE
;
309 case PIPE_BLENDFACTOR_SRC_COLOR
:
310 return V_028780_BLEND_SRC_COLOR
;
311 case PIPE_BLENDFACTOR_SRC_ALPHA
:
312 return V_028780_BLEND_SRC_ALPHA
;
313 case PIPE_BLENDFACTOR_DST_ALPHA
:
314 return V_028780_BLEND_DST_ALPHA
;
315 case PIPE_BLENDFACTOR_DST_COLOR
:
316 return V_028780_BLEND_DST_COLOR
;
317 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
318 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
319 case PIPE_BLENDFACTOR_CONST_COLOR
:
320 return V_028780_BLEND_CONSTANT_COLOR
;
321 case PIPE_BLENDFACTOR_CONST_ALPHA
:
322 return V_028780_BLEND_CONSTANT_ALPHA
;
323 case PIPE_BLENDFACTOR_ZERO
:
324 return V_028780_BLEND_ZERO
;
325 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
326 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
327 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
328 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
329 case PIPE_BLENDFACTOR_INV_DST_ALPHA
:
330 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
331 case PIPE_BLENDFACTOR_INV_DST_COLOR
:
332 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
333 case PIPE_BLENDFACTOR_INV_CONST_COLOR
:
334 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR
;
335 case PIPE_BLENDFACTOR_INV_CONST_ALPHA
:
336 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA
;
337 case PIPE_BLENDFACTOR_SRC1_COLOR
:
338 return V_028780_BLEND_SRC1_COLOR
;
339 case PIPE_BLENDFACTOR_SRC1_ALPHA
:
340 return V_028780_BLEND_SRC1_ALPHA
;
341 case PIPE_BLENDFACTOR_INV_SRC1_COLOR
:
342 return V_028780_BLEND_INV_SRC1_COLOR
;
343 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA
:
344 return V_028780_BLEND_INV_SRC1_ALPHA
;
346 PRINT_ERR("Bad blend factor %d not supported!\n", blend_fact
);
353 static uint32_t si_translate_blend_opt_function(int blend_func
)
355 switch (blend_func
) {
357 return V_028760_OPT_COMB_ADD
;
358 case PIPE_BLEND_SUBTRACT
:
359 return V_028760_OPT_COMB_SUBTRACT
;
360 case PIPE_BLEND_REVERSE_SUBTRACT
:
361 return V_028760_OPT_COMB_REVSUBTRACT
;
363 return V_028760_OPT_COMB_MIN
;
365 return V_028760_OPT_COMB_MAX
;
367 return V_028760_OPT_COMB_BLEND_DISABLED
;
371 static uint32_t si_translate_blend_opt_factor(int blend_fact
, bool is_alpha
)
373 switch (blend_fact
) {
374 case PIPE_BLENDFACTOR_ZERO
:
375 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL
;
376 case PIPE_BLENDFACTOR_ONE
:
377 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
;
378 case PIPE_BLENDFACTOR_SRC_COLOR
:
379 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
380 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0
;
381 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
382 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
383 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1
;
384 case PIPE_BLENDFACTOR_SRC_ALPHA
:
385 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
;
386 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
387 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
;
388 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
389 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
390 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
392 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
396 static void si_blend_check_commutativity(struct si_screen
*sscreen
,
397 struct si_state_blend
*blend
,
398 enum pipe_blend_func func
,
399 enum pipe_blendfactor src
,
400 enum pipe_blendfactor dst
,
403 /* Src factor is allowed when it does not depend on Dst */
404 static const uint32_t src_allowed
=
405 (1u << PIPE_BLENDFACTOR_ONE
) |
406 (1u << PIPE_BLENDFACTOR_SRC_COLOR
) |
407 (1u << PIPE_BLENDFACTOR_SRC_ALPHA
) |
408 (1u << PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
) |
409 (1u << PIPE_BLENDFACTOR_CONST_COLOR
) |
410 (1u << PIPE_BLENDFACTOR_CONST_ALPHA
) |
411 (1u << PIPE_BLENDFACTOR_SRC1_COLOR
) |
412 (1u << PIPE_BLENDFACTOR_SRC1_ALPHA
) |
413 (1u << PIPE_BLENDFACTOR_ZERO
) |
414 (1u << PIPE_BLENDFACTOR_INV_SRC_COLOR
) |
415 (1u << PIPE_BLENDFACTOR_INV_SRC_ALPHA
) |
416 (1u << PIPE_BLENDFACTOR_INV_CONST_COLOR
) |
417 (1u << PIPE_BLENDFACTOR_INV_CONST_ALPHA
) |
418 (1u << PIPE_BLENDFACTOR_INV_SRC1_COLOR
) |
419 (1u << PIPE_BLENDFACTOR_INV_SRC1_ALPHA
);
421 if (dst
== PIPE_BLENDFACTOR_ONE
&&
422 (src_allowed
& (1u << src
))) {
423 /* Addition is commutative, but floating point addition isn't
424 * associative: subtle changes can be introduced via different
427 * Out-of-order is also non-deterministic, which means that
428 * this breaks OpenGL invariance requirements. So only enable
429 * out-of-order additive blending if explicitly allowed by a
432 if (func
== PIPE_BLEND_MAX
|| func
== PIPE_BLEND_MIN
||
433 (func
== PIPE_BLEND_ADD
&& sscreen
->commutative_blend_add
))
434 blend
->commutative_4bit
|= chanmask
;
439 * Get rid of DST in the blend factors by commuting the operands:
440 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
442 static void si_blend_remove_dst(unsigned *func
, unsigned *src_factor
,
443 unsigned *dst_factor
, unsigned expected_dst
,
444 unsigned replacement_src
)
446 if (*src_factor
== expected_dst
&&
447 *dst_factor
== PIPE_BLENDFACTOR_ZERO
) {
448 *src_factor
= PIPE_BLENDFACTOR_ZERO
;
449 *dst_factor
= replacement_src
;
451 /* Commuting the operands requires reversing subtractions. */
452 if (*func
== PIPE_BLEND_SUBTRACT
)
453 *func
= PIPE_BLEND_REVERSE_SUBTRACT
;
454 else if (*func
== PIPE_BLEND_REVERSE_SUBTRACT
)
455 *func
= PIPE_BLEND_SUBTRACT
;
459 static bool si_blend_factor_uses_dst(unsigned factor
)
461 return factor
== PIPE_BLENDFACTOR_DST_COLOR
||
462 factor
== PIPE_BLENDFACTOR_DST_ALPHA
||
463 factor
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
464 factor
== PIPE_BLENDFACTOR_INV_DST_ALPHA
||
465 factor
== PIPE_BLENDFACTOR_INV_DST_COLOR
;
468 static void *si_create_blend_state_mode(struct pipe_context
*ctx
,
469 const struct pipe_blend_state
*state
,
472 struct si_context
*sctx
= (struct si_context
*)ctx
;
473 struct si_state_blend
*blend
= CALLOC_STRUCT(si_state_blend
);
474 struct si_pm4_state
*pm4
= &blend
->pm4
;
475 uint32_t sx_mrt_blend_opt
[8] = {0};
476 uint32_t color_control
= 0;
477 bool logicop_enable
= state
->logicop_enable
&&
478 state
->logicop_func
!= PIPE_LOGICOP_COPY
;
483 blend
->alpha_to_coverage
= state
->alpha_to_coverage
;
484 blend
->alpha_to_one
= state
->alpha_to_one
;
485 blend
->dual_src_blend
= util_blend_state_is_dual(state
, 0);
486 blend
->logicop_enable
= logicop_enable
;
488 if (logicop_enable
) {
489 color_control
|= S_028808_ROP3(state
->logicop_func
| (state
->logicop_func
<< 4));
491 color_control
|= S_028808_ROP3(0xcc);
494 si_pm4_set_reg(pm4
, R_028B70_DB_ALPHA_TO_MASK
,
495 S_028B70_ALPHA_TO_MASK_ENABLE(state
->alpha_to_coverage
) |
496 S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
497 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
498 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
499 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
500 S_028B70_OFFSET_ROUND(1));
502 if (state
->alpha_to_coverage
)
503 blend
->need_src_alpha_4bit
|= 0xf;
505 blend
->cb_target_mask
= 0;
506 blend
->cb_target_enabled_4bit
= 0;
508 for (int i
= 0; i
< 8; i
++) {
509 /* state->rt entries > 0 only written if independent blending */
510 const int j
= state
->independent_blend_enable
? i
: 0;
512 unsigned eqRGB
= state
->rt
[j
].rgb_func
;
513 unsigned srcRGB
= state
->rt
[j
].rgb_src_factor
;
514 unsigned dstRGB
= state
->rt
[j
].rgb_dst_factor
;
515 unsigned eqA
= state
->rt
[j
].alpha_func
;
516 unsigned srcA
= state
->rt
[j
].alpha_src_factor
;
517 unsigned dstA
= state
->rt
[j
].alpha_dst_factor
;
519 unsigned srcRGB_opt
, dstRGB_opt
, srcA_opt
, dstA_opt
;
520 unsigned blend_cntl
= 0;
522 sx_mrt_blend_opt
[i
] =
523 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) |
524 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
526 /* Only set dual source blending for MRT0 to avoid a hang. */
527 if (i
>= 1 && blend
->dual_src_blend
) {
528 /* Vulkan does this for dual source blending. */
530 blend_cntl
|= S_028780_ENABLE(1);
532 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
536 /* Only addition and subtraction equations are supported with
537 * dual source blending.
539 if (blend
->dual_src_blend
&&
540 (eqRGB
== PIPE_BLEND_MIN
|| eqRGB
== PIPE_BLEND_MAX
||
541 eqA
== PIPE_BLEND_MIN
|| eqA
== PIPE_BLEND_MAX
)) {
542 assert(!"Unsupported equation for dual source blending");
543 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
547 /* cb_render_state will disable unused ones */
548 blend
->cb_target_mask
|= (unsigned)state
->rt
[j
].colormask
<< (4 * i
);
549 if (state
->rt
[j
].colormask
)
550 blend
->cb_target_enabled_4bit
|= 0xf << (4 * i
);
552 if (!state
->rt
[j
].colormask
|| !state
->rt
[j
].blend_enable
) {
553 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
557 si_blend_check_commutativity(sctx
->screen
, blend
,
558 eqRGB
, srcRGB
, dstRGB
, 0x7 << (4 * i
));
559 si_blend_check_commutativity(sctx
->screen
, blend
,
560 eqA
, srcA
, dstA
, 0x8 << (4 * i
));
562 /* Blending optimizations for RB+.
563 * These transformations don't change the behavior.
565 * First, get rid of DST in the blend factors:
566 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
568 si_blend_remove_dst(&eqRGB
, &srcRGB
, &dstRGB
,
569 PIPE_BLENDFACTOR_DST_COLOR
,
570 PIPE_BLENDFACTOR_SRC_COLOR
);
571 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
572 PIPE_BLENDFACTOR_DST_COLOR
,
573 PIPE_BLENDFACTOR_SRC_COLOR
);
574 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
575 PIPE_BLENDFACTOR_DST_ALPHA
,
576 PIPE_BLENDFACTOR_SRC_ALPHA
);
578 /* Look up the ideal settings from tables. */
579 srcRGB_opt
= si_translate_blend_opt_factor(srcRGB
, false);
580 dstRGB_opt
= si_translate_blend_opt_factor(dstRGB
, false);
581 srcA_opt
= si_translate_blend_opt_factor(srcA
, true);
582 dstA_opt
= si_translate_blend_opt_factor(dstA
, true);
584 /* Handle interdependencies. */
585 if (si_blend_factor_uses_dst(srcRGB
))
586 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
587 if (si_blend_factor_uses_dst(srcA
))
588 dstA_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
590 if (srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
&&
591 (dstRGB
== PIPE_BLENDFACTOR_ZERO
||
592 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
593 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
))
594 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
596 /* Set the final value. */
597 sx_mrt_blend_opt
[i
] =
598 S_028760_COLOR_SRC_OPT(srcRGB_opt
) |
599 S_028760_COLOR_DST_OPT(dstRGB_opt
) |
600 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB
)) |
601 S_028760_ALPHA_SRC_OPT(srcA_opt
) |
602 S_028760_ALPHA_DST_OPT(dstA_opt
) |
603 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA
));
605 /* Set blend state. */
606 blend_cntl
|= S_028780_ENABLE(1);
607 blend_cntl
|= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB
));
608 blend_cntl
|= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB
));
609 blend_cntl
|= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB
));
611 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
612 blend_cntl
|= S_028780_SEPARATE_ALPHA_BLEND(1);
613 blend_cntl
|= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA
));
614 blend_cntl
|= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA
));
615 blend_cntl
|= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA
));
617 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
619 blend
->blend_enable_4bit
|= 0xfu
<< (i
* 4);
621 if (sctx
->family
<= CHIP_NAVI14
)
622 blend
->dcc_msaa_corruption_4bit
|= 0xfu
<< (i
* 4);
624 /* This is only important for formats without alpha. */
625 if (srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
626 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
627 srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
628 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
629 srcRGB
== PIPE_BLENDFACTOR_INV_SRC_ALPHA
||
630 dstRGB
== PIPE_BLENDFACTOR_INV_SRC_ALPHA
)
631 blend
->need_src_alpha_4bit
|= 0xfu
<< (i
* 4);
634 if (sctx
->family
<= CHIP_NAVI14
&& logicop_enable
)
635 blend
->dcc_msaa_corruption_4bit
|= blend
->cb_target_enabled_4bit
;
637 if (blend
->cb_target_mask
) {
638 color_control
|= S_028808_MODE(mode
);
640 color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
643 if (sctx
->screen
->info
.rbplus_allowed
) {
644 /* Disable RB+ blend optimizations for dual source blending.
647 if (blend
->dual_src_blend
) {
648 for (int i
= 0; i
< 8; i
++) {
649 sx_mrt_blend_opt
[i
] =
650 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE
) |
651 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE
);
655 for (int i
= 0; i
< 8; i
++)
656 si_pm4_set_reg(pm4
, R_028760_SX_MRT0_BLEND_OPT
+ i
* 4,
657 sx_mrt_blend_opt
[i
]);
659 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
660 if (blend
->dual_src_blend
|| logicop_enable
||
661 mode
== V_028808_CB_RESOLVE
)
662 color_control
|= S_028808_DISABLE_DUAL_QUAD(1);
665 si_pm4_set_reg(pm4
, R_028808_CB_COLOR_CONTROL
, color_control
);
669 static void *si_create_blend_state(struct pipe_context
*ctx
,
670 const struct pipe_blend_state
*state
)
672 return si_create_blend_state_mode(ctx
, state
, V_028808_CB_NORMAL
);
675 static void si_bind_blend_state(struct pipe_context
*ctx
, void *state
)
677 struct si_context
*sctx
= (struct si_context
*)ctx
;
678 struct si_state_blend
*old_blend
= sctx
->queued
.named
.blend
;
679 struct si_state_blend
*blend
= (struct si_state_blend
*)state
;
682 blend
= (struct si_state_blend
*)sctx
->noop_blend
;
684 si_pm4_bind_state(sctx
, blend
, blend
);
686 if (old_blend
->cb_target_mask
!= blend
->cb_target_mask
||
687 old_blend
->dual_src_blend
!= blend
->dual_src_blend
||
688 (old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
&&
689 sctx
->framebuffer
.nr_samples
>= 2 &&
690 sctx
->screen
->dcc_msaa_allowed
))
691 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
693 if (old_blend
->cb_target_mask
!= blend
->cb_target_mask
||
694 old_blend
->alpha_to_coverage
!= blend
->alpha_to_coverage
||
695 old_blend
->alpha_to_one
!= blend
->alpha_to_one
||
696 old_blend
->dual_src_blend
!= blend
->dual_src_blend
||
697 old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
||
698 old_blend
->need_src_alpha_4bit
!= blend
->need_src_alpha_4bit
)
699 sctx
->do_update_shaders
= true;
701 if (sctx
->screen
->dpbb_allowed
&&
702 (old_blend
->alpha_to_coverage
!= blend
->alpha_to_coverage
||
703 old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
||
704 old_blend
->cb_target_enabled_4bit
!= blend
->cb_target_enabled_4bit
))
705 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
707 if (sctx
->screen
->has_out_of_order_rast
&&
708 ((old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
||
709 old_blend
->cb_target_enabled_4bit
!= blend
->cb_target_enabled_4bit
||
710 old_blend
->commutative_4bit
!= blend
->commutative_4bit
||
711 old_blend
->logicop_enable
!= blend
->logicop_enable
)))
712 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
715 static void si_delete_blend_state(struct pipe_context
*ctx
, void *state
)
717 struct si_context
*sctx
= (struct si_context
*)ctx
;
718 si_pm4_delete_state(sctx
, blend
, (struct si_state_blend
*)state
);
721 static void si_set_blend_color(struct pipe_context
*ctx
,
722 const struct pipe_blend_color
*state
)
724 struct si_context
*sctx
= (struct si_context
*)ctx
;
725 static const struct pipe_blend_color zeros
;
727 sctx
->blend_color
.state
= *state
;
728 sctx
->blend_color
.any_nonzeros
= memcmp(state
, &zeros
, sizeof(*state
)) != 0;
729 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.blend_color
);
732 static void si_emit_blend_color(struct si_context
*sctx
)
734 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
736 radeon_set_context_reg_seq(cs
, R_028414_CB_BLEND_RED
, 4);
737 radeon_emit_array(cs
, (uint32_t*)sctx
->blend_color
.state
.color
, 4);
744 static void si_set_clip_state(struct pipe_context
*ctx
,
745 const struct pipe_clip_state
*state
)
747 struct si_context
*sctx
= (struct si_context
*)ctx
;
748 struct pipe_constant_buffer cb
;
749 static const struct pipe_clip_state zeros
;
751 if (memcmp(&sctx
->clip_state
.state
, state
, sizeof(*state
)) == 0)
754 sctx
->clip_state
.state
= *state
;
755 sctx
->clip_state
.any_nonzeros
= memcmp(state
, &zeros
, sizeof(*state
)) != 0;
756 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_state
);
759 cb
.user_buffer
= state
->ucp
;
760 cb
.buffer_offset
= 0;
761 cb
.buffer_size
= 4*4*8;
762 si_set_rw_buffer(sctx
, SI_VS_CONST_CLIP_PLANES
, &cb
);
763 pipe_resource_reference(&cb
.buffer
, NULL
);
766 static void si_emit_clip_state(struct si_context
*sctx
)
768 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
770 radeon_set_context_reg_seq(cs
, R_0285BC_PA_CL_UCP_0_X
, 6*4);
771 radeon_emit_array(cs
, (uint32_t*)sctx
->clip_state
.state
.ucp
, 6*4);
774 static void si_emit_clip_regs(struct si_context
*sctx
)
776 struct si_shader
*vs
= si_get_vs_state(sctx
);
777 struct si_shader_selector
*vs_sel
= vs
->selector
;
778 struct tgsi_shader_info
*info
= &vs_sel
->info
;
779 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
780 unsigned window_space
=
781 info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
782 unsigned clipdist_mask
= vs_sel
->clipdist_mask
;
783 unsigned ucp_mask
= clipdist_mask
? 0 : rs
->clip_plane_enable
& SIX_BITS
;
784 unsigned culldist_mask
= vs_sel
->culldist_mask
;
787 if (vs
->key
.opt
.clip_disable
) {
788 assert(!info
->culldist_writemask
);
792 total_mask
= clipdist_mask
| culldist_mask
;
794 /* Clip distances on points have no effect, so need to be implemented
795 * as cull distances. This applies for the clipvertex case as well.
797 * Setting this for primitives other than points should have no adverse
800 clipdist_mask
&= rs
->clip_plane_enable
;
801 culldist_mask
|= clipdist_mask
;
803 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
804 radeon_opt_set_context_reg(sctx
, R_02881C_PA_CL_VS_OUT_CNTL
,
805 SI_TRACKED_PA_CL_VS_OUT_CNTL
,
806 vs_sel
->pa_cl_vs_out_cntl
|
807 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0F) != 0) |
808 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xF0) != 0) |
809 clipdist_mask
| (culldist_mask
<< 8));
810 radeon_opt_set_context_reg(sctx
, R_028810_PA_CL_CLIP_CNTL
,
811 SI_TRACKED_PA_CL_CLIP_CNTL
,
812 rs
->pa_cl_clip_cntl
|
814 S_028810_CLIP_DISABLE(window_space
));
816 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
817 sctx
->context_roll
= true;
821 * inferred state between framebuffer and rasterizer
823 static void si_update_poly_offset_state(struct si_context
*sctx
)
825 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
827 if (!rs
->uses_poly_offset
|| !sctx
->framebuffer
.state
.zsbuf
) {
828 si_pm4_bind_state(sctx
, poly_offset
, NULL
);
832 /* Use the user format, not db_render_format, so that the polygon
833 * offset behaves as expected by applications.
835 switch (sctx
->framebuffer
.state
.zsbuf
->texture
->format
) {
836 case PIPE_FORMAT_Z16_UNORM
:
837 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[0]);
839 default: /* 24-bit */
840 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[1]);
842 case PIPE_FORMAT_Z32_FLOAT
:
843 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
844 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[2]);
853 static uint32_t si_translate_fill(uint32_t func
)
856 case PIPE_POLYGON_MODE_FILL
:
857 return V_028814_X_DRAW_TRIANGLES
;
858 case PIPE_POLYGON_MODE_LINE
:
859 return V_028814_X_DRAW_LINES
;
860 case PIPE_POLYGON_MODE_POINT
:
861 return V_028814_X_DRAW_POINTS
;
864 return V_028814_X_DRAW_POINTS
;
868 static void *si_create_rs_state(struct pipe_context
*ctx
,
869 const struct pipe_rasterizer_state
*state
)
871 struct si_screen
*sscreen
= ((struct si_context
*)ctx
)->screen
;
872 struct si_state_rasterizer
*rs
= CALLOC_STRUCT(si_state_rasterizer
);
873 struct si_pm4_state
*pm4
= &rs
->pm4
;
875 float psize_min
, psize_max
;
881 if (!state
->front_ccw
) {
882 rs
->cull_front
= !!(state
->cull_face
& PIPE_FACE_FRONT
);
883 rs
->cull_back
= !!(state
->cull_face
& PIPE_FACE_BACK
);
885 rs
->cull_back
= !!(state
->cull_face
& PIPE_FACE_FRONT
);
886 rs
->cull_front
= !!(state
->cull_face
& PIPE_FACE_BACK
);
888 rs
->depth_clamp_any
= !state
->depth_clip_near
|| !state
->depth_clip_far
;
889 rs
->provoking_vertex_first
= state
->flatshade_first
;
890 rs
->scissor_enable
= state
->scissor
;
891 rs
->clip_halfz
= state
->clip_halfz
;
892 rs
->two_side
= state
->light_twoside
;
893 rs
->multisample_enable
= state
->multisample
;
894 rs
->force_persample_interp
= state
->force_persample_interp
;
895 rs
->clip_plane_enable
= state
->clip_plane_enable
;
896 rs
->half_pixel_center
= state
->half_pixel_center
;
897 rs
->line_stipple_enable
= state
->line_stipple_enable
;
898 rs
->poly_stipple_enable
= state
->poly_stipple_enable
;
899 rs
->line_smooth
= state
->line_smooth
;
900 rs
->line_width
= state
->line_width
;
901 rs
->poly_smooth
= state
->poly_smooth
;
902 rs
->uses_poly_offset
= state
->offset_point
|| state
->offset_line
||
904 rs
->clamp_fragment_color
= state
->clamp_fragment_color
;
905 rs
->clamp_vertex_color
= state
->clamp_vertex_color
;
906 rs
->flatshade
= state
->flatshade
;
907 rs
->flatshade_first
= state
->flatshade_first
;
908 rs
->sprite_coord_enable
= state
->sprite_coord_enable
;
909 rs
->rasterizer_discard
= state
->rasterizer_discard
;
910 rs
->pa_sc_line_stipple
= state
->line_stipple_enable
?
911 S_028A0C_LINE_PATTERN(state
->line_stipple_pattern
) |
912 S_028A0C_REPEAT_COUNT(state
->line_stipple_factor
) : 0;
913 rs
->pa_cl_clip_cntl
=
914 S_028810_DX_CLIP_SPACE_DEF(state
->clip_halfz
) |
915 S_028810_ZCLIP_NEAR_DISABLE(!state
->depth_clip_near
) |
916 S_028810_ZCLIP_FAR_DISABLE(!state
->depth_clip_far
) |
917 S_028810_DX_RASTERIZATION_KILL(state
->rasterizer_discard
) |
918 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
920 si_pm4_set_reg(pm4
, R_0286D4_SPI_INTERP_CONTROL_0
,
921 S_0286D4_FLAT_SHADE_ENA(1) |
922 S_0286D4_PNT_SPRITE_ENA(state
->point_quad_rasterization
) |
923 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S
) |
924 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T
) |
925 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0
) |
926 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1
) |
927 S_0286D4_PNT_SPRITE_TOP_1(state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
));
929 /* point size 12.4 fixed point */
930 tmp
= (unsigned)(state
->point_size
* 8.0);
931 si_pm4_set_reg(pm4
, R_028A00_PA_SU_POINT_SIZE
, S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
));
933 if (state
->point_size_per_vertex
) {
934 psize_min
= util_get_min_point_size(state
);
935 psize_max
= SI_MAX_POINT_SIZE
;
937 /* Force the point size to be as if the vertex output was disabled. */
938 psize_min
= state
->point_size
;
939 psize_max
= state
->point_size
;
941 rs
->max_point_size
= psize_max
;
943 /* Divide by two, because 0.5 = 1 pixel. */
944 si_pm4_set_reg(pm4
, R_028A04_PA_SU_POINT_MINMAX
,
945 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min
/2)) |
946 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max
/2)));
948 si_pm4_set_reg(pm4
, R_028A08_PA_SU_LINE_CNTL
,
949 S_028A08_WIDTH(si_pack_float_12p4(state
->line_width
/2)));
950 si_pm4_set_reg(pm4
, R_028A48_PA_SC_MODE_CNTL_0
,
951 S_028A48_LINE_STIPPLE_ENABLE(state
->line_stipple_enable
) |
952 S_028A48_MSAA_ENABLE(state
->multisample
||
953 state
->poly_smooth
||
954 state
->line_smooth
) |
955 S_028A48_VPORT_SCISSOR_ENABLE(1) |
956 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen
->info
.chip_class
>= GFX9
));
958 si_pm4_set_reg(pm4
, R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, fui(state
->offset_clamp
));
959 si_pm4_set_reg(pm4
, R_028814_PA_SU_SC_MODE_CNTL
,
960 S_028814_PROVOKING_VTX_LAST(!state
->flatshade_first
) |
961 S_028814_CULL_FRONT((state
->cull_face
& PIPE_FACE_FRONT
) ? 1 : 0) |
962 S_028814_CULL_BACK((state
->cull_face
& PIPE_FACE_BACK
) ? 1 : 0) |
963 S_028814_FACE(!state
->front_ccw
) |
964 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state
, state
->fill_front
)) |
965 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state
, state
->fill_back
)) |
966 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_point
|| state
->offset_line
) |
967 S_028814_POLY_MODE(state
->fill_front
!= PIPE_POLYGON_MODE_FILL
||
968 state
->fill_back
!= PIPE_POLYGON_MODE_FILL
) |
969 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state
->fill_front
)) |
970 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state
->fill_back
)));
972 if (!rs
->uses_poly_offset
)
975 rs
->pm4_poly_offset
= CALLOC(3, sizeof(struct si_pm4_state
));
976 if (!rs
->pm4_poly_offset
) {
981 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
982 for (i
= 0; i
< 3; i
++) {
983 struct si_pm4_state
*pm4
= &rs
->pm4_poly_offset
[i
];
984 float offset_units
= state
->offset_units
;
985 float offset_scale
= state
->offset_scale
* 16.0f
;
986 uint32_t pa_su_poly_offset_db_fmt_cntl
= 0;
988 if (!state
->offset_units_unscaled
) {
990 case 0: /* 16-bit zbuffer */
991 offset_units
*= 4.0f
;
992 pa_su_poly_offset_db_fmt_cntl
=
993 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
995 case 1: /* 24-bit zbuffer */
996 offset_units
*= 2.0f
;
997 pa_su_poly_offset_db_fmt_cntl
=
998 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
1000 case 2: /* 32-bit zbuffer */
1001 offset_units
*= 1.0f
;
1002 pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
1003 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1008 si_pm4_set_reg(pm4
, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE
,
1010 si_pm4_set_reg(pm4
, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET
,
1012 si_pm4_set_reg(pm4
, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE
,
1014 si_pm4_set_reg(pm4
, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET
,
1016 si_pm4_set_reg(pm4
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
1017 pa_su_poly_offset_db_fmt_cntl
);
1023 static void si_bind_rs_state(struct pipe_context
*ctx
, void *state
)
1025 struct si_context
*sctx
= (struct si_context
*)ctx
;
1026 struct si_state_rasterizer
*old_rs
=
1027 (struct si_state_rasterizer
*)sctx
->queued
.named
.rasterizer
;
1028 struct si_state_rasterizer
*rs
= (struct si_state_rasterizer
*)state
;
1031 rs
= (struct si_state_rasterizer
*)sctx
->discard_rasterizer_state
;
1033 if (old_rs
->multisample_enable
!= rs
->multisample_enable
) {
1034 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
1036 /* Update the small primitive filter workaround if necessary. */
1037 if (sctx
->screen
->info
.has_msaa_sample_loc_bug
&&
1038 sctx
->framebuffer
.nr_samples
> 1)
1039 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_sample_locs
);
1042 sctx
->current_vs_state
&= C_VS_STATE_CLAMP_VERTEX_COLOR
;
1043 sctx
->current_vs_state
|= S_VS_STATE_CLAMP_VERTEX_COLOR(rs
->clamp_vertex_color
);
1045 si_pm4_bind_state(sctx
, rasterizer
, rs
);
1046 si_update_poly_offset_state(sctx
);
1048 if (old_rs
->scissor_enable
!= rs
->scissor_enable
)
1049 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.scissors
);
1051 if (old_rs
->line_width
!= rs
->line_width
||
1052 old_rs
->max_point_size
!= rs
->max_point_size
||
1053 old_rs
->half_pixel_center
!= rs
->half_pixel_center
)
1054 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.guardband
);
1056 if (old_rs
->clip_halfz
!= rs
->clip_halfz
)
1057 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.viewports
);
1059 if (old_rs
->clip_plane_enable
!= rs
->clip_plane_enable
||
1060 old_rs
->pa_cl_clip_cntl
!= rs
->pa_cl_clip_cntl
)
1061 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_regs
);
1063 sctx
->ia_multi_vgt_param_key
.u
.line_stipple_enabled
=
1064 rs
->line_stipple_enable
;
1066 if (old_rs
->clip_plane_enable
!= rs
->clip_plane_enable
||
1067 old_rs
->rasterizer_discard
!= rs
->rasterizer_discard
||
1068 old_rs
->sprite_coord_enable
!= rs
->sprite_coord_enable
||
1069 old_rs
->flatshade
!= rs
->flatshade
||
1070 old_rs
->two_side
!= rs
->two_side
||
1071 old_rs
->multisample_enable
!= rs
->multisample_enable
||
1072 old_rs
->poly_stipple_enable
!= rs
->poly_stipple_enable
||
1073 old_rs
->poly_smooth
!= rs
->poly_smooth
||
1074 old_rs
->line_smooth
!= rs
->line_smooth
||
1075 old_rs
->clamp_fragment_color
!= rs
->clamp_fragment_color
||
1076 old_rs
->force_persample_interp
!= rs
->force_persample_interp
)
1077 sctx
->do_update_shaders
= true;
1080 static void si_delete_rs_state(struct pipe_context
*ctx
, void *state
)
1082 struct si_context
*sctx
= (struct si_context
*)ctx
;
1083 struct si_state_rasterizer
*rs
= (struct si_state_rasterizer
*)state
;
1085 if (sctx
->queued
.named
.rasterizer
== state
)
1086 si_pm4_bind_state(sctx
, poly_offset
, NULL
);
1088 FREE(rs
->pm4_poly_offset
);
1089 si_pm4_delete_state(sctx
, rasterizer
, rs
);
1093 * infeered state between dsa and stencil ref
1095 static void si_emit_stencil_ref(struct si_context
*sctx
)
1097 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
1098 struct pipe_stencil_ref
*ref
= &sctx
->stencil_ref
.state
;
1099 struct si_dsa_stencil_ref_part
*dsa
= &sctx
->stencil_ref
.dsa_part
;
1101 radeon_set_context_reg_seq(cs
, R_028430_DB_STENCILREFMASK
, 2);
1102 radeon_emit(cs
, S_028430_STENCILTESTVAL(ref
->ref_value
[0]) |
1103 S_028430_STENCILMASK(dsa
->valuemask
[0]) |
1104 S_028430_STENCILWRITEMASK(dsa
->writemask
[0]) |
1105 S_028430_STENCILOPVAL(1));
1106 radeon_emit(cs
, S_028434_STENCILTESTVAL_BF(ref
->ref_value
[1]) |
1107 S_028434_STENCILMASK_BF(dsa
->valuemask
[1]) |
1108 S_028434_STENCILWRITEMASK_BF(dsa
->writemask
[1]) |
1109 S_028434_STENCILOPVAL_BF(1));
1112 static void si_set_stencil_ref(struct pipe_context
*ctx
,
1113 const struct pipe_stencil_ref
*state
)
1115 struct si_context
*sctx
= (struct si_context
*)ctx
;
1117 if (memcmp(&sctx
->stencil_ref
.state
, state
, sizeof(*state
)) == 0)
1120 sctx
->stencil_ref
.state
= *state
;
1121 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.stencil_ref
);
1129 static uint32_t si_translate_stencil_op(int s_op
)
1132 case PIPE_STENCIL_OP_KEEP
:
1133 return V_02842C_STENCIL_KEEP
;
1134 case PIPE_STENCIL_OP_ZERO
:
1135 return V_02842C_STENCIL_ZERO
;
1136 case PIPE_STENCIL_OP_REPLACE
:
1137 return V_02842C_STENCIL_REPLACE_TEST
;
1138 case PIPE_STENCIL_OP_INCR
:
1139 return V_02842C_STENCIL_ADD_CLAMP
;
1140 case PIPE_STENCIL_OP_DECR
:
1141 return V_02842C_STENCIL_SUB_CLAMP
;
1142 case PIPE_STENCIL_OP_INCR_WRAP
:
1143 return V_02842C_STENCIL_ADD_WRAP
;
1144 case PIPE_STENCIL_OP_DECR_WRAP
:
1145 return V_02842C_STENCIL_SUB_WRAP
;
1146 case PIPE_STENCIL_OP_INVERT
:
1147 return V_02842C_STENCIL_INVERT
;
1149 PRINT_ERR("Unknown stencil op %d", s_op
);
1156 static bool si_dsa_writes_stencil(const struct pipe_stencil_state
*s
)
1158 return s
->enabled
&& s
->writemask
&&
1159 (s
->fail_op
!= PIPE_STENCIL_OP_KEEP
||
1160 s
->zfail_op
!= PIPE_STENCIL_OP_KEEP
||
1161 s
->zpass_op
!= PIPE_STENCIL_OP_KEEP
);
1164 static bool si_order_invariant_stencil_op(enum pipe_stencil_op op
)
1166 /* REPLACE is normally order invariant, except when the stencil
1167 * reference value is written by the fragment shader. Tracking this
1168 * interaction does not seem worth the effort, so be conservative. */
1169 return op
!= PIPE_STENCIL_OP_INCR
&&
1170 op
!= PIPE_STENCIL_OP_DECR
&&
1171 op
!= PIPE_STENCIL_OP_REPLACE
;
1174 /* Compute whether, assuming Z writes are disabled, this stencil state is order
1175 * invariant in the sense that the set of passing fragments as well as the
1176 * final stencil buffer result does not depend on the order of fragments. */
1177 static bool si_order_invariant_stencil_state(const struct pipe_stencil_state
*state
)
1179 return !state
->enabled
|| !state
->writemask
||
1180 /* The following assumes that Z writes are disabled. */
1181 (state
->func
== PIPE_FUNC_ALWAYS
&&
1182 si_order_invariant_stencil_op(state
->zpass_op
) &&
1183 si_order_invariant_stencil_op(state
->zfail_op
)) ||
1184 (state
->func
== PIPE_FUNC_NEVER
&&
1185 si_order_invariant_stencil_op(state
->fail_op
));
1188 static void *si_create_dsa_state(struct pipe_context
*ctx
,
1189 const struct pipe_depth_stencil_alpha_state
*state
)
1191 struct si_context
*sctx
= (struct si_context
*)ctx
;
1192 struct si_state_dsa
*dsa
= CALLOC_STRUCT(si_state_dsa
);
1193 struct si_pm4_state
*pm4
= &dsa
->pm4
;
1194 unsigned db_depth_control
;
1195 uint32_t db_stencil_control
= 0;
1201 dsa
->stencil_ref
.valuemask
[0] = state
->stencil
[0].valuemask
;
1202 dsa
->stencil_ref
.valuemask
[1] = state
->stencil
[1].valuemask
;
1203 dsa
->stencil_ref
.writemask
[0] = state
->stencil
[0].writemask
;
1204 dsa
->stencil_ref
.writemask
[1] = state
->stencil
[1].writemask
;
1206 db_depth_control
= S_028800_Z_ENABLE(state
->depth
.enabled
) |
1207 S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
1208 S_028800_ZFUNC(state
->depth
.func
) |
1209 S_028800_DEPTH_BOUNDS_ENABLE(state
->depth
.bounds_test
);
1212 if (state
->stencil
[0].enabled
) {
1213 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
1214 db_depth_control
|= S_028800_STENCILFUNC(state
->stencil
[0].func
);
1215 db_stencil_control
|= S_02842C_STENCILFAIL(si_translate_stencil_op(state
->stencil
[0].fail_op
));
1216 db_stencil_control
|= S_02842C_STENCILZPASS(si_translate_stencil_op(state
->stencil
[0].zpass_op
));
1217 db_stencil_control
|= S_02842C_STENCILZFAIL(si_translate_stencil_op(state
->stencil
[0].zfail_op
));
1219 if (state
->stencil
[1].enabled
) {
1220 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
1221 db_depth_control
|= S_028800_STENCILFUNC_BF(state
->stencil
[1].func
);
1222 db_stencil_control
|= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state
->stencil
[1].fail_op
));
1223 db_stencil_control
|= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state
->stencil
[1].zpass_op
));
1224 db_stencil_control
|= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state
->stencil
[1].zfail_op
));
1229 if (state
->alpha
.enabled
) {
1230 dsa
->alpha_func
= state
->alpha
.func
;
1232 si_pm4_set_reg(pm4
, R_00B030_SPI_SHADER_USER_DATA_PS_0
+
1233 SI_SGPR_ALPHA_REF
* 4, fui(state
->alpha
.ref_value
));
1235 dsa
->alpha_func
= PIPE_FUNC_ALWAYS
;
1238 si_pm4_set_reg(pm4
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
1239 if (state
->stencil
[0].enabled
)
1240 si_pm4_set_reg(pm4
, R_02842C_DB_STENCIL_CONTROL
, db_stencil_control
);
1241 if (state
->depth
.bounds_test
) {
1242 si_pm4_set_reg(pm4
, R_028020_DB_DEPTH_BOUNDS_MIN
, fui(state
->depth
.bounds_min
));
1243 si_pm4_set_reg(pm4
, R_028024_DB_DEPTH_BOUNDS_MAX
, fui(state
->depth
.bounds_max
));
1246 dsa
->depth_enabled
= state
->depth
.enabled
;
1247 dsa
->depth_write_enabled
= state
->depth
.enabled
&&
1248 state
->depth
.writemask
;
1249 dsa
->stencil_enabled
= state
->stencil
[0].enabled
;
1250 dsa
->stencil_write_enabled
= state
->stencil
[0].enabled
&&
1251 (si_dsa_writes_stencil(&state
->stencil
[0]) ||
1252 si_dsa_writes_stencil(&state
->stencil
[1]));
1253 dsa
->db_can_write
= dsa
->depth_write_enabled
||
1254 dsa
->stencil_write_enabled
;
1256 bool zfunc_is_ordered
=
1257 state
->depth
.func
== PIPE_FUNC_NEVER
||
1258 state
->depth
.func
== PIPE_FUNC_LESS
||
1259 state
->depth
.func
== PIPE_FUNC_LEQUAL
||
1260 state
->depth
.func
== PIPE_FUNC_GREATER
||
1261 state
->depth
.func
== PIPE_FUNC_GEQUAL
;
1263 bool nozwrite_and_order_invariant_stencil
=
1264 !dsa
->db_can_write
||
1265 (!dsa
->depth_write_enabled
&&
1266 si_order_invariant_stencil_state(&state
->stencil
[0]) &&
1267 si_order_invariant_stencil_state(&state
->stencil
[1]));
1269 dsa
->order_invariance
[1].zs
=
1270 nozwrite_and_order_invariant_stencil
||
1271 (!dsa
->stencil_write_enabled
&& zfunc_is_ordered
);
1272 dsa
->order_invariance
[0].zs
= !dsa
->depth_write_enabled
|| zfunc_is_ordered
;
1274 dsa
->order_invariance
[1].pass_set
=
1275 nozwrite_and_order_invariant_stencil
||
1276 (!dsa
->stencil_write_enabled
&&
1277 (state
->depth
.func
== PIPE_FUNC_ALWAYS
||
1278 state
->depth
.func
== PIPE_FUNC_NEVER
));
1279 dsa
->order_invariance
[0].pass_set
=
1280 !dsa
->depth_write_enabled
||
1281 (state
->depth
.func
== PIPE_FUNC_ALWAYS
||
1282 state
->depth
.func
== PIPE_FUNC_NEVER
);
1284 dsa
->order_invariance
[1].pass_last
=
1285 sctx
->screen
->assume_no_z_fights
&&
1286 !dsa
->stencil_write_enabled
&&
1287 dsa
->depth_write_enabled
&& zfunc_is_ordered
;
1288 dsa
->order_invariance
[0].pass_last
=
1289 sctx
->screen
->assume_no_z_fights
&&
1290 dsa
->depth_write_enabled
&& zfunc_is_ordered
;
1295 static void si_bind_dsa_state(struct pipe_context
*ctx
, void *state
)
1297 struct si_context
*sctx
= (struct si_context
*)ctx
;
1298 struct si_state_dsa
*old_dsa
= sctx
->queued
.named
.dsa
;
1299 struct si_state_dsa
*dsa
= state
;
1302 dsa
= (struct si_state_dsa
*)sctx
->noop_dsa
;
1304 si_pm4_bind_state(sctx
, dsa
, dsa
);
1306 if (memcmp(&dsa
->stencil_ref
, &sctx
->stencil_ref
.dsa_part
,
1307 sizeof(struct si_dsa_stencil_ref_part
)) != 0) {
1308 sctx
->stencil_ref
.dsa_part
= dsa
->stencil_ref
;
1309 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.stencil_ref
);
1312 if (old_dsa
->alpha_func
!= dsa
->alpha_func
)
1313 sctx
->do_update_shaders
= true;
1315 if (sctx
->screen
->dpbb_allowed
&&
1316 ((old_dsa
->depth_enabled
!= dsa
->depth_enabled
||
1317 old_dsa
->stencil_enabled
!= dsa
->stencil_enabled
||
1318 old_dsa
->db_can_write
!= dsa
->db_can_write
)))
1319 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
1321 if (sctx
->screen
->has_out_of_order_rast
&&
1322 (memcmp(old_dsa
->order_invariance
, dsa
->order_invariance
,
1323 sizeof(old_dsa
->order_invariance
))))
1324 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
1327 static void si_delete_dsa_state(struct pipe_context
*ctx
, void *state
)
1329 struct si_context
*sctx
= (struct si_context
*)ctx
;
1330 si_pm4_delete_state(sctx
, dsa
, (struct si_state_dsa
*)state
);
1333 static void *si_create_db_flush_dsa(struct si_context
*sctx
)
1335 struct pipe_depth_stencil_alpha_state dsa
= {};
1337 return sctx
->b
.create_depth_stencil_alpha_state(&sctx
->b
, &dsa
);
1340 /* DB RENDER STATE */
1342 static void si_set_active_query_state(struct pipe_context
*ctx
, bool enable
)
1344 struct si_context
*sctx
= (struct si_context
*)ctx
;
1346 /* Pipeline stat & streamout queries. */
1348 sctx
->flags
&= ~SI_CONTEXT_STOP_PIPELINE_STATS
;
1349 sctx
->flags
|= SI_CONTEXT_START_PIPELINE_STATS
;
1351 sctx
->flags
&= ~SI_CONTEXT_START_PIPELINE_STATS
;
1352 sctx
->flags
|= SI_CONTEXT_STOP_PIPELINE_STATS
;
1355 /* Occlusion queries. */
1356 if (sctx
->occlusion_queries_disabled
!= !enable
) {
1357 sctx
->occlusion_queries_disabled
= !enable
;
1358 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
1362 void si_set_occlusion_query_state(struct si_context
*sctx
,
1363 bool old_perfect_enable
)
1365 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
1367 bool perfect_enable
= sctx
->num_perfect_occlusion_queries
!= 0;
1369 if (perfect_enable
!= old_perfect_enable
)
1370 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
1373 void si_save_qbo_state(struct si_context
*sctx
, struct si_qbo_state
*st
)
1375 st
->saved_compute
= sctx
->cs_shader_state
.program
;
1377 si_get_pipe_constant_buffer(sctx
, PIPE_SHADER_COMPUTE
, 0, &st
->saved_const0
);
1378 si_get_shader_buffers(sctx
, PIPE_SHADER_COMPUTE
, 0, 3, st
->saved_ssbo
);
1380 st
->saved_ssbo_writable_mask
= 0;
1382 for (unsigned i
= 0; i
< 3; i
++) {
1383 if (sctx
->const_and_shader_buffers
[PIPE_SHADER_COMPUTE
].writable_mask
&
1384 (1u << si_get_shaderbuf_slot(i
)))
1385 st
->saved_ssbo_writable_mask
|= 1 << i
;
1389 void si_restore_qbo_state(struct si_context
*sctx
, struct si_qbo_state
*st
)
1391 sctx
->b
.bind_compute_state(&sctx
->b
, st
->saved_compute
);
1393 sctx
->b
.set_constant_buffer(&sctx
->b
, PIPE_SHADER_COMPUTE
, 0, &st
->saved_const0
);
1394 pipe_resource_reference(&st
->saved_const0
.buffer
, NULL
);
1396 sctx
->b
.set_shader_buffers(&sctx
->b
, PIPE_SHADER_COMPUTE
, 0, 3, st
->saved_ssbo
,
1397 st
->saved_ssbo_writable_mask
);
1398 for (unsigned i
= 0; i
< 3; ++i
)
1399 pipe_resource_reference(&st
->saved_ssbo
[i
].buffer
, NULL
);
1402 static void si_emit_db_render_state(struct si_context
*sctx
)
1404 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
1405 unsigned db_shader_control
, db_render_control
, db_count_control
;
1406 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1408 /* DB_RENDER_CONTROL */
1409 if (sctx
->dbcb_depth_copy_enabled
||
1410 sctx
->dbcb_stencil_copy_enabled
) {
1412 S_028000_DEPTH_COPY(sctx
->dbcb_depth_copy_enabled
) |
1413 S_028000_STENCIL_COPY(sctx
->dbcb_stencil_copy_enabled
) |
1414 S_028000_COPY_CENTROID(1) |
1415 S_028000_COPY_SAMPLE(sctx
->dbcb_copy_sample
);
1416 } else if (sctx
->db_flush_depth_inplace
|| sctx
->db_flush_stencil_inplace
) {
1418 S_028000_DEPTH_COMPRESS_DISABLE(sctx
->db_flush_depth_inplace
) |
1419 S_028000_STENCIL_COMPRESS_DISABLE(sctx
->db_flush_stencil_inplace
);
1422 S_028000_DEPTH_CLEAR_ENABLE(sctx
->db_depth_clear
) |
1423 S_028000_STENCIL_CLEAR_ENABLE(sctx
->db_stencil_clear
);
1426 /* DB_COUNT_CONTROL (occlusion queries) */
1427 if (sctx
->num_occlusion_queries
> 0 &&
1428 !sctx
->occlusion_queries_disabled
) {
1429 bool perfect
= sctx
->num_perfect_occlusion_queries
> 0;
1430 bool gfx10_perfect
= sctx
->chip_class
>= GFX10
&& perfect
;
1432 if (sctx
->chip_class
>= GFX7
) {
1433 unsigned log_sample_rate
= sctx
->framebuffer
.log_samples
;
1435 /* Stoney doesn't increment occlusion query counters
1436 * if the sample rate is 16x. Use 8x sample rate instead.
1438 if (sctx
->family
== CHIP_STONEY
)
1439 log_sample_rate
= MIN2(log_sample_rate
, 3);
1442 S_028004_PERFECT_ZPASS_COUNTS(perfect
) |
1443 S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(gfx10_perfect
) |
1444 S_028004_SAMPLE_RATE(log_sample_rate
) |
1445 S_028004_ZPASS_ENABLE(1) |
1446 S_028004_SLICE_EVEN_ENABLE(1) |
1447 S_028004_SLICE_ODD_ENABLE(1);
1450 S_028004_PERFECT_ZPASS_COUNTS(perfect
) |
1451 S_028004_SAMPLE_RATE(sctx
->framebuffer
.log_samples
);
1454 /* Disable occlusion queries. */
1455 if (sctx
->chip_class
>= GFX7
) {
1456 db_count_control
= 0;
1458 db_count_control
= S_028004_ZPASS_INCREMENT_DISABLE(1);
1462 radeon_opt_set_context_reg2(sctx
, R_028000_DB_RENDER_CONTROL
,
1463 SI_TRACKED_DB_RENDER_CONTROL
, db_render_control
,
1466 /* DB_RENDER_OVERRIDE2 */
1467 radeon_opt_set_context_reg(sctx
, R_028010_DB_RENDER_OVERRIDE2
,
1468 SI_TRACKED_DB_RENDER_OVERRIDE2
,
1469 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx
->db_depth_disable_expclear
) |
1470 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx
->db_stencil_disable_expclear
) |
1471 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx
->framebuffer
.nr_samples
>= 4));
1473 db_shader_control
= sctx
->ps_db_shader_control
;
1475 /* Bug workaround for smoothing (overrasterization) on GFX6. */
1476 if (sctx
->chip_class
== GFX6
&& sctx
->smoothing_enabled
) {
1477 db_shader_control
&= C_02880C_Z_ORDER
;
1478 db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
);
1481 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1482 if (!rs
->multisample_enable
)
1483 db_shader_control
&= C_02880C_MASK_EXPORT_ENABLE
;
1485 if (sctx
->screen
->info
.has_rbplus
&&
1486 !sctx
->screen
->info
.rbplus_allowed
)
1487 db_shader_control
|= S_02880C_DUAL_QUAD_DISABLE(1);
1489 radeon_opt_set_context_reg(sctx
, R_02880C_DB_SHADER_CONTROL
,
1490 SI_TRACKED_DB_SHADER_CONTROL
, db_shader_control
);
1492 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
1493 sctx
->context_roll
= true;
1497 * format translation
1499 static uint32_t si_translate_colorformat(enum pipe_format format
)
1501 const struct util_format_description
*desc
= util_format_description(format
);
1503 return V_028C70_COLOR_INVALID
;
1505 #define HAS_SIZE(x,y,z,w) \
1506 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1507 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1509 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
1510 return V_028C70_COLOR_10_11_11
;
1512 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
1513 return V_028C70_COLOR_INVALID
;
1515 /* hw cannot support mixed formats (except depth/stencil, since
1516 * stencil is not written to). */
1517 if (desc
->is_mixed
&& desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
)
1518 return V_028C70_COLOR_INVALID
;
1520 switch (desc
->nr_channels
) {
1522 switch (desc
->channel
[0].size
) {
1524 return V_028C70_COLOR_8
;
1526 return V_028C70_COLOR_16
;
1528 return V_028C70_COLOR_32
;
1532 if (desc
->channel
[0].size
== desc
->channel
[1].size
) {
1533 switch (desc
->channel
[0].size
) {
1535 return V_028C70_COLOR_8_8
;
1537 return V_028C70_COLOR_16_16
;
1539 return V_028C70_COLOR_32_32
;
1541 } else if (HAS_SIZE(8,24,0,0)) {
1542 return V_028C70_COLOR_24_8
;
1543 } else if (HAS_SIZE(24,8,0,0)) {
1544 return V_028C70_COLOR_8_24
;
1548 if (HAS_SIZE(5,6,5,0)) {
1549 return V_028C70_COLOR_5_6_5
;
1550 } else if (HAS_SIZE(32,8,24,0)) {
1551 return V_028C70_COLOR_X24_8_32_FLOAT
;
1555 if (desc
->channel
[0].size
== desc
->channel
[1].size
&&
1556 desc
->channel
[0].size
== desc
->channel
[2].size
&&
1557 desc
->channel
[0].size
== desc
->channel
[3].size
) {
1558 switch (desc
->channel
[0].size
) {
1560 return V_028C70_COLOR_4_4_4_4
;
1562 return V_028C70_COLOR_8_8_8_8
;
1564 return V_028C70_COLOR_16_16_16_16
;
1566 return V_028C70_COLOR_32_32_32_32
;
1568 } else if (HAS_SIZE(5,5,5,1)) {
1569 return V_028C70_COLOR_1_5_5_5
;
1570 } else if (HAS_SIZE(1,5,5,5)) {
1571 return V_028C70_COLOR_5_5_5_1
;
1572 } else if (HAS_SIZE(10,10,10,2)) {
1573 return V_028C70_COLOR_2_10_10_10
;
1577 return V_028C70_COLOR_INVALID
;
1580 static uint32_t si_colorformat_endian_swap(uint32_t colorformat
)
1582 if (SI_BIG_ENDIAN
) {
1583 switch(colorformat
) {
1584 /* 8-bit buffers. */
1585 case V_028C70_COLOR_8
:
1586 return V_028C70_ENDIAN_NONE
;
1588 /* 16-bit buffers. */
1589 case V_028C70_COLOR_5_6_5
:
1590 case V_028C70_COLOR_1_5_5_5
:
1591 case V_028C70_COLOR_4_4_4_4
:
1592 case V_028C70_COLOR_16
:
1593 case V_028C70_COLOR_8_8
:
1594 return V_028C70_ENDIAN_8IN16
;
1596 /* 32-bit buffers. */
1597 case V_028C70_COLOR_8_8_8_8
:
1598 case V_028C70_COLOR_2_10_10_10
:
1599 case V_028C70_COLOR_8_24
:
1600 case V_028C70_COLOR_24_8
:
1601 case V_028C70_COLOR_16_16
:
1602 return V_028C70_ENDIAN_8IN32
;
1604 /* 64-bit buffers. */
1605 case V_028C70_COLOR_16_16_16_16
:
1606 return V_028C70_ENDIAN_8IN16
;
1608 case V_028C70_COLOR_32_32
:
1609 return V_028C70_ENDIAN_8IN32
;
1611 /* 128-bit buffers. */
1612 case V_028C70_COLOR_32_32_32_32
:
1613 return V_028C70_ENDIAN_8IN32
;
1615 return V_028C70_ENDIAN_NONE
; /* Unsupported. */
1618 return V_028C70_ENDIAN_NONE
;
1622 static uint32_t si_translate_dbformat(enum pipe_format format
)
1625 case PIPE_FORMAT_Z16_UNORM
:
1626 return V_028040_Z_16
;
1627 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1628 case PIPE_FORMAT_X8Z24_UNORM
:
1629 case PIPE_FORMAT_Z24X8_UNORM
:
1630 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1631 return V_028040_Z_24
; /* deprecated on AMD GCN */
1632 case PIPE_FORMAT_Z32_FLOAT
:
1633 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1634 return V_028040_Z_32_FLOAT
;
1636 return V_028040_Z_INVALID
;
1641 * Texture translation
1644 static uint32_t si_translate_texformat(struct pipe_screen
*screen
,
1645 enum pipe_format format
,
1646 const struct util_format_description
*desc
,
1649 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1650 bool uniform
= true;
1653 assert(sscreen
->info
.chip_class
<= GFX9
);
1655 /* Colorspace (return non-RGB formats directly). */
1656 switch (desc
->colorspace
) {
1657 /* Depth stencil formats */
1658 case UTIL_FORMAT_COLORSPACE_ZS
:
1660 case PIPE_FORMAT_Z16_UNORM
:
1661 return V_008F14_IMG_DATA_FORMAT_16
;
1662 case PIPE_FORMAT_X24S8_UINT
:
1663 case PIPE_FORMAT_S8X24_UINT
:
1665 * Implemented as an 8_8_8_8 data format to fix texture
1666 * gathers in stencil sampling. This affects at least
1667 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
1669 if (sscreen
->info
.chip_class
<= GFX8
)
1670 return V_008F14_IMG_DATA_FORMAT_8_8_8_8
;
1672 if (format
== PIPE_FORMAT_X24S8_UINT
)
1673 return V_008F14_IMG_DATA_FORMAT_8_24
;
1675 return V_008F14_IMG_DATA_FORMAT_24_8
;
1676 case PIPE_FORMAT_Z24X8_UNORM
:
1677 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1678 return V_008F14_IMG_DATA_FORMAT_8_24
;
1679 case PIPE_FORMAT_X8Z24_UNORM
:
1680 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1681 return V_008F14_IMG_DATA_FORMAT_24_8
;
1682 case PIPE_FORMAT_S8_UINT
:
1683 return V_008F14_IMG_DATA_FORMAT_8
;
1684 case PIPE_FORMAT_Z32_FLOAT
:
1685 return V_008F14_IMG_DATA_FORMAT_32
;
1686 case PIPE_FORMAT_X32_S8X24_UINT
:
1687 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1688 return V_008F14_IMG_DATA_FORMAT_X24_8_32
;
1693 case UTIL_FORMAT_COLORSPACE_YUV
:
1694 goto out_unknown
; /* TODO */
1696 case UTIL_FORMAT_COLORSPACE_SRGB
:
1697 if (desc
->nr_channels
!= 4 && desc
->nr_channels
!= 1)
1705 if (desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
) {
1706 if (!sscreen
->info
.has_format_bc1_through_bc7
)
1710 case PIPE_FORMAT_RGTC1_SNORM
:
1711 case PIPE_FORMAT_LATC1_SNORM
:
1712 case PIPE_FORMAT_RGTC1_UNORM
:
1713 case PIPE_FORMAT_LATC1_UNORM
:
1714 return V_008F14_IMG_DATA_FORMAT_BC4
;
1715 case PIPE_FORMAT_RGTC2_SNORM
:
1716 case PIPE_FORMAT_LATC2_SNORM
:
1717 case PIPE_FORMAT_RGTC2_UNORM
:
1718 case PIPE_FORMAT_LATC2_UNORM
:
1719 return V_008F14_IMG_DATA_FORMAT_BC5
;
1725 if (desc
->layout
== UTIL_FORMAT_LAYOUT_ETC
&&
1726 (sscreen
->info
.family
== CHIP_STONEY
||
1727 sscreen
->info
.family
== CHIP_VEGA10
||
1728 sscreen
->info
.family
== CHIP_RAVEN
)) {
1730 case PIPE_FORMAT_ETC1_RGB8
:
1731 case PIPE_FORMAT_ETC2_RGB8
:
1732 case PIPE_FORMAT_ETC2_SRGB8
:
1733 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB
;
1734 case PIPE_FORMAT_ETC2_RGB8A1
:
1735 case PIPE_FORMAT_ETC2_SRGB8A1
:
1736 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1
;
1737 case PIPE_FORMAT_ETC2_RGBA8
:
1738 case PIPE_FORMAT_ETC2_SRGBA8
:
1739 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA
;
1740 case PIPE_FORMAT_ETC2_R11_UNORM
:
1741 case PIPE_FORMAT_ETC2_R11_SNORM
:
1742 return V_008F14_IMG_DATA_FORMAT_ETC2_R
;
1743 case PIPE_FORMAT_ETC2_RG11_UNORM
:
1744 case PIPE_FORMAT_ETC2_RG11_SNORM
:
1745 return V_008F14_IMG_DATA_FORMAT_ETC2_RG
;
1751 if (desc
->layout
== UTIL_FORMAT_LAYOUT_BPTC
) {
1752 if (!sscreen
->info
.has_format_bc1_through_bc7
)
1756 case PIPE_FORMAT_BPTC_RGBA_UNORM
:
1757 case PIPE_FORMAT_BPTC_SRGBA
:
1758 return V_008F14_IMG_DATA_FORMAT_BC7
;
1759 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
1760 case PIPE_FORMAT_BPTC_RGB_UFLOAT
:
1761 return V_008F14_IMG_DATA_FORMAT_BC6
;
1767 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
1769 case PIPE_FORMAT_R8G8_B8G8_UNORM
:
1770 case PIPE_FORMAT_G8R8_B8R8_UNORM
:
1771 return V_008F14_IMG_DATA_FORMAT_GB_GR
;
1772 case PIPE_FORMAT_G8R8_G8B8_UNORM
:
1773 case PIPE_FORMAT_R8G8_R8B8_UNORM
:
1774 return V_008F14_IMG_DATA_FORMAT_BG_RG
;
1780 if (desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
1781 if (!sscreen
->info
.has_format_bc1_through_bc7
)
1785 case PIPE_FORMAT_DXT1_RGB
:
1786 case PIPE_FORMAT_DXT1_RGBA
:
1787 case PIPE_FORMAT_DXT1_SRGB
:
1788 case PIPE_FORMAT_DXT1_SRGBA
:
1789 return V_008F14_IMG_DATA_FORMAT_BC1
;
1790 case PIPE_FORMAT_DXT3_RGBA
:
1791 case PIPE_FORMAT_DXT3_SRGBA
:
1792 return V_008F14_IMG_DATA_FORMAT_BC2
;
1793 case PIPE_FORMAT_DXT5_RGBA
:
1794 case PIPE_FORMAT_DXT5_SRGBA
:
1795 return V_008F14_IMG_DATA_FORMAT_BC3
;
1801 if (format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
1802 return V_008F14_IMG_DATA_FORMAT_5_9_9_9
;
1803 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
1804 return V_008F14_IMG_DATA_FORMAT_10_11_11
;
1807 /* R8G8Bx_SNORM - TODO CxV8U8 */
1809 /* hw cannot support mixed formats (except depth/stencil, since only
1811 if (desc
->is_mixed
&& desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
)
1814 /* See whether the components are of the same size. */
1815 for (i
= 1; i
< desc
->nr_channels
; i
++) {
1816 uniform
= uniform
&& desc
->channel
[0].size
== desc
->channel
[i
].size
;
1819 /* Non-uniform formats. */
1821 switch(desc
->nr_channels
) {
1823 if (desc
->channel
[0].size
== 5 &&
1824 desc
->channel
[1].size
== 6 &&
1825 desc
->channel
[2].size
== 5) {
1826 return V_008F14_IMG_DATA_FORMAT_5_6_5
;
1830 if (desc
->channel
[0].size
== 5 &&
1831 desc
->channel
[1].size
== 5 &&
1832 desc
->channel
[2].size
== 5 &&
1833 desc
->channel
[3].size
== 1) {
1834 return V_008F14_IMG_DATA_FORMAT_1_5_5_5
;
1836 if (desc
->channel
[0].size
== 1 &&
1837 desc
->channel
[1].size
== 5 &&
1838 desc
->channel
[2].size
== 5 &&
1839 desc
->channel
[3].size
== 5) {
1840 return V_008F14_IMG_DATA_FORMAT_5_5_5_1
;
1842 if (desc
->channel
[0].size
== 10 &&
1843 desc
->channel
[1].size
== 10 &&
1844 desc
->channel
[2].size
== 10 &&
1845 desc
->channel
[3].size
== 2) {
1846 return V_008F14_IMG_DATA_FORMAT_2_10_10_10
;
1853 if (first_non_void
< 0 || first_non_void
> 3)
1856 /* uniform formats */
1857 switch (desc
->channel
[first_non_void
].size
) {
1859 switch (desc
->nr_channels
) {
1860 #if 0 /* Not supported for render targets */
1862 return V_008F14_IMG_DATA_FORMAT_4_4
;
1865 return V_008F14_IMG_DATA_FORMAT_4_4_4_4
;
1869 switch (desc
->nr_channels
) {
1871 return V_008F14_IMG_DATA_FORMAT_8
;
1873 return V_008F14_IMG_DATA_FORMAT_8_8
;
1875 return V_008F14_IMG_DATA_FORMAT_8_8_8_8
;
1879 switch (desc
->nr_channels
) {
1881 return V_008F14_IMG_DATA_FORMAT_16
;
1883 return V_008F14_IMG_DATA_FORMAT_16_16
;
1885 return V_008F14_IMG_DATA_FORMAT_16_16_16_16
;
1889 switch (desc
->nr_channels
) {
1891 return V_008F14_IMG_DATA_FORMAT_32
;
1893 return V_008F14_IMG_DATA_FORMAT_32_32
;
1894 #if 0 /* Not supported for render targets */
1896 return V_008F14_IMG_DATA_FORMAT_32_32_32
;
1899 return V_008F14_IMG_DATA_FORMAT_32_32_32_32
;
1907 static unsigned si_tex_wrap(unsigned wrap
)
1911 case PIPE_TEX_WRAP_REPEAT
:
1912 return V_008F30_SQ_TEX_WRAP
;
1913 case PIPE_TEX_WRAP_CLAMP
:
1914 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER
;
1915 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
1916 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL
;
1917 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
1918 return V_008F30_SQ_TEX_CLAMP_BORDER
;
1919 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
1920 return V_008F30_SQ_TEX_MIRROR
;
1921 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
1922 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
1923 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
1924 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
1925 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
1926 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER
;
1930 static unsigned si_tex_mipfilter(unsigned filter
)
1933 case PIPE_TEX_MIPFILTER_NEAREST
:
1934 return V_008F38_SQ_TEX_Z_FILTER_POINT
;
1935 case PIPE_TEX_MIPFILTER_LINEAR
:
1936 return V_008F38_SQ_TEX_Z_FILTER_LINEAR
;
1938 case PIPE_TEX_MIPFILTER_NONE
:
1939 return V_008F38_SQ_TEX_Z_FILTER_NONE
;
1943 static unsigned si_tex_compare(unsigned compare
)
1947 case PIPE_FUNC_NEVER
:
1948 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
1949 case PIPE_FUNC_LESS
:
1950 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS
;
1951 case PIPE_FUNC_EQUAL
:
1952 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL
;
1953 case PIPE_FUNC_LEQUAL
:
1954 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
1955 case PIPE_FUNC_GREATER
:
1956 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER
;
1957 case PIPE_FUNC_NOTEQUAL
:
1958 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
1959 case PIPE_FUNC_GEQUAL
:
1960 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
1961 case PIPE_FUNC_ALWAYS
:
1962 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
1966 static unsigned si_tex_dim(struct si_screen
*sscreen
, struct si_texture
*tex
,
1967 unsigned view_target
, unsigned nr_samples
)
1969 unsigned res_target
= tex
->buffer
.b
.b
.target
;
1971 if (view_target
== PIPE_TEXTURE_CUBE
||
1972 view_target
== PIPE_TEXTURE_CUBE_ARRAY
)
1973 res_target
= view_target
;
1974 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1975 else if (res_target
== PIPE_TEXTURE_CUBE
||
1976 res_target
== PIPE_TEXTURE_CUBE_ARRAY
)
1977 res_target
= PIPE_TEXTURE_2D_ARRAY
;
1979 /* GFX9 allocates 1D textures as 2D. */
1980 if ((res_target
== PIPE_TEXTURE_1D
||
1981 res_target
== PIPE_TEXTURE_1D_ARRAY
) &&
1982 sscreen
->info
.chip_class
== GFX9
&&
1983 tex
->surface
.u
.gfx9
.resource_type
== RADEON_RESOURCE_2D
) {
1984 if (res_target
== PIPE_TEXTURE_1D
)
1985 res_target
= PIPE_TEXTURE_2D
;
1987 res_target
= PIPE_TEXTURE_2D_ARRAY
;
1990 switch (res_target
) {
1992 case PIPE_TEXTURE_1D
:
1993 return V_008F1C_SQ_RSRC_IMG_1D
;
1994 case PIPE_TEXTURE_1D_ARRAY
:
1995 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY
;
1996 case PIPE_TEXTURE_2D
:
1997 case PIPE_TEXTURE_RECT
:
1998 return nr_samples
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA
:
1999 V_008F1C_SQ_RSRC_IMG_2D
;
2000 case PIPE_TEXTURE_2D_ARRAY
:
2001 return nr_samples
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
:
2002 V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
2003 case PIPE_TEXTURE_3D
:
2004 return V_008F1C_SQ_RSRC_IMG_3D
;
2005 case PIPE_TEXTURE_CUBE
:
2006 case PIPE_TEXTURE_CUBE_ARRAY
:
2007 return V_008F1C_SQ_RSRC_IMG_CUBE
;
2012 * Format support testing
2015 static bool si_is_sampler_format_supported(struct pipe_screen
*screen
, enum pipe_format format
)
2017 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2019 if (sscreen
->info
.chip_class
>= GFX10
) {
2020 const struct gfx10_format
*fmt
= &gfx10_format_table
[format
];
2021 if (!fmt
->img_format
|| fmt
->buffers_only
)
2026 const struct util_format_description
*desc
= util_format_description(format
);
2030 return si_translate_texformat(screen
, format
, desc
,
2031 util_format_get_first_non_void_channel(format
)) != ~0U;
2034 static uint32_t si_translate_buffer_dataformat(struct pipe_screen
*screen
,
2035 const struct util_format_description
*desc
,
2040 assert(((struct si_screen
*)screen
)->info
.chip_class
<= GFX9
);
2042 if (desc
->format
== PIPE_FORMAT_R11G11B10_FLOAT
)
2043 return V_008F0C_BUF_DATA_FORMAT_10_11_11
;
2045 assert(first_non_void
>= 0);
2047 if (desc
->nr_channels
== 4 &&
2048 desc
->channel
[0].size
== 10 &&
2049 desc
->channel
[1].size
== 10 &&
2050 desc
->channel
[2].size
== 10 &&
2051 desc
->channel
[3].size
== 2)
2052 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10
;
2054 /* See whether the components are of the same size. */
2055 for (i
= 0; i
< desc
->nr_channels
; i
++) {
2056 if (desc
->channel
[first_non_void
].size
!= desc
->channel
[i
].size
)
2057 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
2060 switch (desc
->channel
[first_non_void
].size
) {
2062 switch (desc
->nr_channels
) {
2064 case 3: /* 3 loads */
2065 return V_008F0C_BUF_DATA_FORMAT_8
;
2067 return V_008F0C_BUF_DATA_FORMAT_8_8
;
2069 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8
;
2073 switch (desc
->nr_channels
) {
2075 case 3: /* 3 loads */
2076 return V_008F0C_BUF_DATA_FORMAT_16
;
2078 return V_008F0C_BUF_DATA_FORMAT_16_16
;
2080 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16
;
2084 switch (desc
->nr_channels
) {
2086 return V_008F0C_BUF_DATA_FORMAT_32
;
2088 return V_008F0C_BUF_DATA_FORMAT_32_32
;
2090 return V_008F0C_BUF_DATA_FORMAT_32_32_32
;
2092 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
2096 /* Legacy double formats. */
2097 switch (desc
->nr_channels
) {
2098 case 1: /* 1 load */
2099 return V_008F0C_BUF_DATA_FORMAT_32_32
;
2100 case 2: /* 1 load */
2101 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
2102 case 3: /* 3 loads */
2103 return V_008F0C_BUF_DATA_FORMAT_32_32
;
2104 case 4: /* 2 loads */
2105 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
2110 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
2113 static uint32_t si_translate_buffer_numformat(struct pipe_screen
*screen
,
2114 const struct util_format_description
*desc
,
2117 assert(((struct si_screen
*)screen
)->info
.chip_class
<= GFX9
);
2119 if (desc
->format
== PIPE_FORMAT_R11G11B10_FLOAT
)
2120 return V_008F0C_BUF_NUM_FORMAT_FLOAT
;
2122 assert(first_non_void
>= 0);
2124 switch (desc
->channel
[first_non_void
].type
) {
2125 case UTIL_FORMAT_TYPE_SIGNED
:
2126 case UTIL_FORMAT_TYPE_FIXED
:
2127 if (desc
->channel
[first_non_void
].size
>= 32 ||
2128 desc
->channel
[first_non_void
].pure_integer
)
2129 return V_008F0C_BUF_NUM_FORMAT_SINT
;
2130 else if (desc
->channel
[first_non_void
].normalized
)
2131 return V_008F0C_BUF_NUM_FORMAT_SNORM
;
2133 return V_008F0C_BUF_NUM_FORMAT_SSCALED
;
2135 case UTIL_FORMAT_TYPE_UNSIGNED
:
2136 if (desc
->channel
[first_non_void
].size
>= 32 ||
2137 desc
->channel
[first_non_void
].pure_integer
)
2138 return V_008F0C_BUF_NUM_FORMAT_UINT
;
2139 else if (desc
->channel
[first_non_void
].normalized
)
2140 return V_008F0C_BUF_NUM_FORMAT_UNORM
;
2142 return V_008F0C_BUF_NUM_FORMAT_USCALED
;
2144 case UTIL_FORMAT_TYPE_FLOAT
:
2146 return V_008F0C_BUF_NUM_FORMAT_FLOAT
;
2150 static unsigned si_is_vertex_format_supported(struct pipe_screen
*screen
,
2151 enum pipe_format format
,
2154 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2155 const struct util_format_description
*desc
;
2157 unsigned data_format
;
2159 assert((usage
& ~(PIPE_BIND_SHADER_IMAGE
|
2160 PIPE_BIND_SAMPLER_VIEW
|
2161 PIPE_BIND_VERTEX_BUFFER
)) == 0);
2163 desc
= util_format_description(format
);
2167 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
2168 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
2169 * for read-only access (with caveats surrounding bounds checks), but
2170 * obviously fails for write access which we have to implement for
2171 * shader images. Luckily, OpenGL doesn't expect this to be supported
2172 * anyway, and so the only impact is on PBO uploads / downloads, which
2173 * shouldn't be expected to be fast for GL_RGB anyway.
2175 if (desc
->block
.bits
== 3 * 8 ||
2176 desc
->block
.bits
== 3 * 16) {
2177 if (usage
& (PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SAMPLER_VIEW
)) {
2178 usage
&= ~(PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SAMPLER_VIEW
);
2184 if (sscreen
->info
.chip_class
>= GFX10
) {
2185 const struct gfx10_format
*fmt
= &gfx10_format_table
[format
];
2186 if (!fmt
->img_format
|| fmt
->img_format
>= 128)
2191 first_non_void
= util_format_get_first_non_void_channel(format
);
2192 data_format
= si_translate_buffer_dataformat(screen
, desc
, first_non_void
);
2193 if (data_format
== V_008F0C_BUF_DATA_FORMAT_INVALID
)
2199 static bool si_is_colorbuffer_format_supported(enum pipe_format format
)
2201 return si_translate_colorformat(format
) != V_028C70_COLOR_INVALID
&&
2202 si_translate_colorswap(format
, false) != ~0U;
2205 static bool si_is_zs_format_supported(enum pipe_format format
)
2207 return si_translate_dbformat(format
) != V_028040_Z_INVALID
;
2210 static bool si_is_format_supported(struct pipe_screen
*screen
,
2211 enum pipe_format format
,
2212 enum pipe_texture_target target
,
2213 unsigned sample_count
,
2214 unsigned storage_sample_count
,
2217 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2218 unsigned retval
= 0;
2220 if (target
>= PIPE_MAX_TEXTURE_TYPES
) {
2221 PRINT_ERR("radeonsi: unsupported texture type %d\n", target
);
2225 if (MAX2(1, sample_count
) < MAX2(1, storage_sample_count
))
2228 if (sample_count
> 1) {
2229 if (!screen
->get_param(screen
, PIPE_CAP_TEXTURE_MULTISAMPLE
))
2232 if (usage
& PIPE_BIND_SHADER_IMAGE
)
2235 /* Only power-of-two sample counts are supported. */
2236 if (!util_is_power_of_two_or_zero(sample_count
) ||
2237 !util_is_power_of_two_or_zero(storage_sample_count
))
2240 /* MSAA support without framebuffer attachments. */
2241 if (format
== PIPE_FORMAT_NONE
&& sample_count
<= 16)
2244 if (!sscreen
->info
.has_eqaa_surface_allocator
||
2245 util_format_is_depth_or_stencil(format
)) {
2246 /* Color without EQAA or depth/stencil. */
2247 if (sample_count
> 8 ||
2248 sample_count
!= storage_sample_count
)
2251 /* Color with EQAA. */
2252 if (sample_count
> 16 ||
2253 storage_sample_count
> 8)
2258 if (usage
& (PIPE_BIND_SAMPLER_VIEW
|
2259 PIPE_BIND_SHADER_IMAGE
)) {
2260 if (target
== PIPE_BUFFER
) {
2261 retval
|= si_is_vertex_format_supported(
2262 screen
, format
, usage
& (PIPE_BIND_SAMPLER_VIEW
|
2263 PIPE_BIND_SHADER_IMAGE
));
2265 if (si_is_sampler_format_supported(screen
, format
))
2266 retval
|= usage
& (PIPE_BIND_SAMPLER_VIEW
|
2267 PIPE_BIND_SHADER_IMAGE
);
2271 if ((usage
& (PIPE_BIND_RENDER_TARGET
|
2272 PIPE_BIND_DISPLAY_TARGET
|
2275 PIPE_BIND_BLENDABLE
)) &&
2276 si_is_colorbuffer_format_supported(format
)) {
2278 (PIPE_BIND_RENDER_TARGET
|
2279 PIPE_BIND_DISPLAY_TARGET
|
2282 if (!util_format_is_pure_integer(format
) &&
2283 !util_format_is_depth_or_stencil(format
))
2284 retval
|= usage
& PIPE_BIND_BLENDABLE
;
2287 if ((usage
& PIPE_BIND_DEPTH_STENCIL
) &&
2288 si_is_zs_format_supported(format
)) {
2289 retval
|= PIPE_BIND_DEPTH_STENCIL
;
2292 if (usage
& PIPE_BIND_VERTEX_BUFFER
) {
2293 retval
|= si_is_vertex_format_supported(screen
, format
,
2294 PIPE_BIND_VERTEX_BUFFER
);
2297 if ((usage
& PIPE_BIND_LINEAR
) &&
2298 !util_format_is_compressed(format
) &&
2299 !(usage
& PIPE_BIND_DEPTH_STENCIL
))
2300 retval
|= PIPE_BIND_LINEAR
;
2302 return retval
== usage
;
2306 * framebuffer handling
2309 static void si_choose_spi_color_formats(struct si_surface
*surf
,
2310 unsigned format
, unsigned swap
,
2311 unsigned ntype
, bool is_depth
)
2313 /* Alpha is needed for alpha-to-coverage.
2314 * Blending may be with or without alpha.
2316 unsigned normal
= 0; /* most optimal, may not support blending or export alpha */
2317 unsigned alpha
= 0; /* exports alpha, but may not support blending */
2318 unsigned blend
= 0; /* supports blending, but may not export alpha */
2319 unsigned blend_alpha
= 0; /* least optimal, supports blending and exports alpha */
2321 /* Choose the SPI color formats. These are required values for RB+.
2322 * Other chips have multiple choices, though they are not necessarily better.
2325 case V_028C70_COLOR_5_6_5
:
2326 case V_028C70_COLOR_1_5_5_5
:
2327 case V_028C70_COLOR_5_5_5_1
:
2328 case V_028C70_COLOR_4_4_4_4
:
2329 case V_028C70_COLOR_10_11_11
:
2330 case V_028C70_COLOR_11_11_10
:
2331 case V_028C70_COLOR_8
:
2332 case V_028C70_COLOR_8_8
:
2333 case V_028C70_COLOR_8_8_8_8
:
2334 case V_028C70_COLOR_10_10_10_2
:
2335 case V_028C70_COLOR_2_10_10_10
:
2336 if (ntype
== V_028C70_NUMBER_UINT
)
2337 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
2338 else if (ntype
== V_028C70_NUMBER_SINT
)
2339 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
2341 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
2344 case V_028C70_COLOR_16
:
2345 case V_028C70_COLOR_16_16
:
2346 case V_028C70_COLOR_16_16_16_16
:
2347 if (ntype
== V_028C70_NUMBER_UNORM
||
2348 ntype
== V_028C70_NUMBER_SNORM
) {
2349 /* UNORM16 and SNORM16 don't support blending */
2350 if (ntype
== V_028C70_NUMBER_UNORM
)
2351 normal
= alpha
= V_028714_SPI_SHADER_UNORM16_ABGR
;
2353 normal
= alpha
= V_028714_SPI_SHADER_SNORM16_ABGR
;
2355 /* Use 32 bits per channel for blending. */
2356 if (format
== V_028C70_COLOR_16
) {
2357 if (swap
== V_028C70_SWAP_STD
) { /* R */
2358 blend
= V_028714_SPI_SHADER_32_R
;
2359 blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2360 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
2361 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2364 } else if (format
== V_028C70_COLOR_16_16
) {
2365 if (swap
== V_028C70_SWAP_STD
) { /* RG */
2366 blend
= V_028714_SPI_SHADER_32_GR
;
2367 blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2368 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
2369 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2372 } else /* 16_16_16_16 */
2373 blend
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2374 } else if (ntype
== V_028C70_NUMBER_UINT
)
2375 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
2376 else if (ntype
== V_028C70_NUMBER_SINT
)
2377 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
2378 else if (ntype
== V_028C70_NUMBER_FLOAT
)
2379 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
2384 case V_028C70_COLOR_32
:
2385 if (swap
== V_028C70_SWAP_STD
) { /* R */
2386 blend
= normal
= V_028714_SPI_SHADER_32_R
;
2387 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2388 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
2389 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
2394 case V_028C70_COLOR_32_32
:
2395 if (swap
== V_028C70_SWAP_STD
) { /* RG */
2396 blend
= normal
= V_028714_SPI_SHADER_32_GR
;
2397 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2398 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
2399 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
2404 case V_028C70_COLOR_32_32_32_32
:
2405 case V_028C70_COLOR_8_24
:
2406 case V_028C70_COLOR_24_8
:
2407 case V_028C70_COLOR_X24_8_32_FLOAT
:
2408 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
2416 /* The DB->CB copy needs 32_ABGR. */
2418 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
2420 surf
->spi_shader_col_format
= normal
;
2421 surf
->spi_shader_col_format_alpha
= alpha
;
2422 surf
->spi_shader_col_format_blend
= blend
;
2423 surf
->spi_shader_col_format_blend_alpha
= blend_alpha
;
2426 static void si_initialize_color_surface(struct si_context
*sctx
,
2427 struct si_surface
*surf
)
2429 struct si_texture
*tex
= (struct si_texture
*)surf
->base
.texture
;
2430 unsigned color_info
, color_attrib
;
2431 unsigned format
, swap
, ntype
, endian
;
2432 const struct util_format_description
*desc
;
2434 unsigned blend_clamp
= 0, blend_bypass
= 0;
2436 desc
= util_format_description(surf
->base
.format
);
2437 for (firstchan
= 0; firstchan
< 4; firstchan
++) {
2438 if (desc
->channel
[firstchan
].type
!= UTIL_FORMAT_TYPE_VOID
) {
2442 if (firstchan
== 4 || desc
->channel
[firstchan
].type
== UTIL_FORMAT_TYPE_FLOAT
) {
2443 ntype
= V_028C70_NUMBER_FLOAT
;
2445 ntype
= V_028C70_NUMBER_UNORM
;
2446 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
2447 ntype
= V_028C70_NUMBER_SRGB
;
2448 else if (desc
->channel
[firstchan
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2449 if (desc
->channel
[firstchan
].pure_integer
) {
2450 ntype
= V_028C70_NUMBER_SINT
;
2452 assert(desc
->channel
[firstchan
].normalized
);
2453 ntype
= V_028C70_NUMBER_SNORM
;
2455 } else if (desc
->channel
[firstchan
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
2456 if (desc
->channel
[firstchan
].pure_integer
) {
2457 ntype
= V_028C70_NUMBER_UINT
;
2459 assert(desc
->channel
[firstchan
].normalized
);
2460 ntype
= V_028C70_NUMBER_UNORM
;
2465 format
= si_translate_colorformat(surf
->base
.format
);
2466 if (format
== V_028C70_COLOR_INVALID
) {
2467 PRINT_ERR("Invalid CB format: %d, disabling CB.\n", surf
->base
.format
);
2469 assert(format
!= V_028C70_COLOR_INVALID
);
2470 swap
= si_translate_colorswap(surf
->base
.format
, false);
2471 endian
= si_colorformat_endian_swap(format
);
2473 /* blend clamp should be set for all NORM/SRGB types */
2474 if (ntype
== V_028C70_NUMBER_UNORM
||
2475 ntype
== V_028C70_NUMBER_SNORM
||
2476 ntype
== V_028C70_NUMBER_SRGB
)
2479 /* set blend bypass according to docs if SINT/UINT or
2480 8/24 COLOR variants */
2481 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
2482 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
2483 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
2488 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
) {
2489 if (format
== V_028C70_COLOR_8
||
2490 format
== V_028C70_COLOR_8_8
||
2491 format
== V_028C70_COLOR_8_8_8_8
)
2492 surf
->color_is_int8
= true;
2493 else if (format
== V_028C70_COLOR_10_10_10_2
||
2494 format
== V_028C70_COLOR_2_10_10_10
)
2495 surf
->color_is_int10
= true;
2498 color_info
= S_028C70_FORMAT(format
) |
2499 S_028C70_COMP_SWAP(swap
) |
2500 S_028C70_BLEND_CLAMP(blend_clamp
) |
2501 S_028C70_BLEND_BYPASS(blend_bypass
) |
2502 S_028C70_SIMPLE_FLOAT(1) |
2503 S_028C70_ROUND_MODE(ntype
!= V_028C70_NUMBER_UNORM
&&
2504 ntype
!= V_028C70_NUMBER_SNORM
&&
2505 ntype
!= V_028C70_NUMBER_SRGB
&&
2506 format
!= V_028C70_COLOR_8_24
&&
2507 format
!= V_028C70_COLOR_24_8
) |
2508 S_028C70_NUMBER_TYPE(ntype
) |
2509 S_028C70_ENDIAN(endian
);
2511 /* Intensity is implemented as Red, so treat it that way. */
2512 color_attrib
= S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] == PIPE_SWIZZLE_1
||
2513 util_format_is_intensity(surf
->base
.format
));
2515 if (tex
->buffer
.b
.b
.nr_samples
> 1) {
2516 unsigned log_samples
= util_logbase2(tex
->buffer
.b
.b
.nr_samples
);
2517 unsigned log_fragments
= util_logbase2(tex
->buffer
.b
.b
.nr_storage_samples
);
2519 color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
2520 S_028C74_NUM_FRAGMENTS(log_fragments
);
2522 if (tex
->fmask_offset
) {
2523 color_info
|= S_028C70_COMPRESSION(1);
2524 unsigned fmask_bankh
= util_logbase2(tex
->surface
.u
.legacy
.fmask
.bankh
);
2526 if (sctx
->chip_class
== GFX6
) {
2527 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on GFX6 too */
2528 color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh
);
2533 if (sctx
->chip_class
>= GFX10
) {
2534 unsigned min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_32B
;
2536 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2537 64 for APU because all of our APUs to date use DIMMs which have
2538 a request granularity size of 64B while all other chips have a
2540 if (!sctx
->screen
->info
.has_dedicated_vram
)
2541 min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_64B
;
2543 surf
->cb_dcc_control
=
2544 S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_256B
) |
2545 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_128B
) |
2546 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size
) |
2547 S_028C78_INDEPENDENT_64B_BLOCKS(0) |
2548 S_028C78_INDEPENDENT_128B_BLOCKS(1);
2549 } else if (sctx
->chip_class
>= GFX8
) {
2550 unsigned max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_256B
;
2551 unsigned min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_32B
;
2553 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2554 64 for APU because all of our APUs to date use DIMMs which have
2555 a request granularity size of 64B while all other chips have a
2557 if (!sctx
->screen
->info
.has_dedicated_vram
)
2558 min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_64B
;
2560 if (tex
->buffer
.b
.b
.nr_storage_samples
> 1) {
2561 if (tex
->surface
.bpe
== 1)
2562 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_64B
;
2563 else if (tex
->surface
.bpe
== 2)
2564 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_128B
;
2567 surf
->cb_dcc_control
= S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size
) |
2568 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size
) |
2569 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2572 /* This must be set for fast clear to work without FMASK. */
2573 if (!tex
->surface
.fmask_size
&& sctx
->chip_class
== GFX6
) {
2574 unsigned bankh
= util_logbase2(tex
->surface
.u
.legacy
.bankh
);
2575 color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(bankh
);
2578 /* GFX10 field has the same base shift as the GFX6 field */
2579 unsigned color_view
= S_028C6C_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
2580 S_028C6C_SLICE_MAX_GFX10(surf
->base
.u
.tex
.last_layer
);
2581 unsigned mip0_depth
= util_max_layer(&tex
->buffer
.b
.b
, 0);
2583 if (sctx
->chip_class
>= GFX10
) {
2584 color_view
|= S_028C6C_MIP_LEVEL_GFX10(surf
->base
.u
.tex
.level
);
2586 surf
->cb_color_attrib3
= S_028EE0_MIP0_DEPTH(mip0_depth
) |
2587 S_028EE0_RESOURCE_TYPE(tex
->surface
.u
.gfx9
.resource_type
) |
2588 S_028EE0_RESOURCE_LEVEL(1);
2589 } else if (sctx
->chip_class
== GFX9
) {
2590 color_view
|= S_028C6C_MIP_LEVEL_GFX9(surf
->base
.u
.tex
.level
);
2591 color_attrib
|= S_028C74_MIP0_DEPTH(mip0_depth
) |
2592 S_028C74_RESOURCE_TYPE(tex
->surface
.u
.gfx9
.resource_type
);
2595 if (sctx
->chip_class
>= GFX9
) {
2596 surf
->cb_color_attrib2
= S_028C68_MIP0_WIDTH(surf
->width0
- 1) |
2597 S_028C68_MIP0_HEIGHT(surf
->height0
- 1) |
2598 S_028C68_MAX_MIP(tex
->buffer
.b
.b
.last_level
);
2601 surf
->cb_color_view
= color_view
;
2602 surf
->cb_color_info
= color_info
;
2603 surf
->cb_color_attrib
= color_attrib
;
2605 /* Determine pixel shader export format */
2606 si_choose_spi_color_formats(surf
, format
, swap
, ntype
, tex
->is_depth
);
2608 surf
->color_initialized
= true;
2611 static void si_init_depth_surface(struct si_context
*sctx
,
2612 struct si_surface
*surf
)
2614 struct si_texture
*tex
= (struct si_texture
*)surf
->base
.texture
;
2615 unsigned level
= surf
->base
.u
.tex
.level
;
2616 unsigned format
, stencil_format
;
2617 uint32_t z_info
, s_info
;
2619 format
= si_translate_dbformat(tex
->db_render_format
);
2620 stencil_format
= tex
->surface
.has_stencil
?
2621 V_028044_STENCIL_8
: V_028044_STENCIL_INVALID
;
2623 assert(format
!= V_028040_Z_INVALID
);
2624 if (format
== V_028040_Z_INVALID
)
2625 PRINT_ERR("Invalid DB format: %d, disabling DB.\n", tex
->buffer
.b
.b
.format
);
2627 surf
->db_depth_view
= S_028008_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
2628 S_028008_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
2629 surf
->db_htile_data_base
= 0;
2630 surf
->db_htile_surface
= 0;
2632 if (sctx
->chip_class
>= GFX10
) {
2633 surf
->db_depth_view
|= S_028008_SLICE_START_HI(surf
->base
.u
.tex
.first_layer
>> 11) |
2634 S_028008_SLICE_MAX_HI(surf
->base
.u
.tex
.last_layer
>> 11);
2637 if (sctx
->chip_class
>= GFX9
) {
2638 assert(tex
->surface
.u
.gfx9
.surf_offset
== 0);
2639 surf
->db_depth_base
= tex
->buffer
.gpu_address
>> 8;
2640 surf
->db_stencil_base
= (tex
->buffer
.gpu_address
+
2641 tex
->surface
.u
.gfx9
.stencil_offset
) >> 8;
2642 z_info
= S_028038_FORMAT(format
) |
2643 S_028038_NUM_SAMPLES(util_logbase2(tex
->buffer
.b
.b
.nr_samples
)) |
2644 S_028038_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
2645 S_028038_MAXMIP(tex
->buffer
.b
.b
.last_level
);
2646 s_info
= S_02803C_FORMAT(stencil_format
) |
2647 S_02803C_SW_MODE(tex
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
2649 if (sctx
->chip_class
== GFX9
) {
2650 surf
->db_z_info2
= S_028068_EPITCH(tex
->surface
.u
.gfx9
.surf
.epitch
);
2651 surf
->db_stencil_info2
= S_02806C_EPITCH(tex
->surface
.u
.gfx9
.stencil
.epitch
);
2653 surf
->db_depth_view
|= S_028008_MIPID(level
);
2654 surf
->db_depth_size
= S_02801C_X_MAX(tex
->buffer
.b
.b
.width0
- 1) |
2655 S_02801C_Y_MAX(tex
->buffer
.b
.b
.height0
- 1);
2657 if (si_htile_enabled(tex
, level
, PIPE_MASK_ZS
)) {
2658 z_info
|= S_028038_TILE_SURFACE_ENABLE(1) |
2659 S_028038_ALLOW_EXPCLEAR(1);
2661 if (tex
->tc_compatible_htile
) {
2662 unsigned max_zplanes
= 4;
2664 if (tex
->db_render_format
== PIPE_FORMAT_Z16_UNORM
&&
2665 tex
->buffer
.b
.b
.nr_samples
> 1)
2668 z_info
|= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes
+ 1);
2670 if (sctx
->chip_class
>= GFX10
) {
2671 z_info
|= S_028040_ITERATE_FLUSH(1);
2672 s_info
|= S_028044_ITERATE_FLUSH(!tex
->htile_stencil_disabled
);
2674 z_info
|= S_028038_ITERATE_FLUSH(1);
2675 s_info
|= S_02803C_ITERATE_FLUSH(1);
2679 if (tex
->surface
.has_stencil
&& !tex
->htile_stencil_disabled
) {
2680 /* Stencil buffer workaround ported from the GFX6-GFX8 code.
2681 * See that for explanation.
2683 s_info
|= S_02803C_ALLOW_EXPCLEAR(tex
->buffer
.b
.b
.nr_samples
<= 1);
2685 /* Use all HTILE for depth if there's no stencil. */
2686 s_info
|= S_02803C_TILE_STENCIL_DISABLE(1);
2689 surf
->db_htile_data_base
= (tex
->buffer
.gpu_address
+
2690 tex
->htile_offset
) >> 8;
2691 surf
->db_htile_surface
= S_028ABC_FULL_CACHE(1) |
2692 S_028ABC_PIPE_ALIGNED(tex
->surface
.u
.gfx9
.htile
.pipe_aligned
);
2693 if (sctx
->chip_class
== GFX9
) {
2694 surf
->db_htile_surface
|=
2695 S_028ABC_RB_ALIGNED(tex
->surface
.u
.gfx9
.htile
.rb_aligned
);
2700 struct legacy_surf_level
*levelinfo
= &tex
->surface
.u
.legacy
.level
[level
];
2702 assert(levelinfo
->nblk_x
% 8 == 0 && levelinfo
->nblk_y
% 8 == 0);
2704 surf
->db_depth_base
= (tex
->buffer
.gpu_address
+
2705 tex
->surface
.u
.legacy
.level
[level
].offset
) >> 8;
2706 surf
->db_stencil_base
= (tex
->buffer
.gpu_address
+
2707 tex
->surface
.u
.legacy
.stencil_level
[level
].offset
) >> 8;
2709 z_info
= S_028040_FORMAT(format
) |
2710 S_028040_NUM_SAMPLES(util_logbase2(tex
->buffer
.b
.b
.nr_samples
));
2711 s_info
= S_028044_FORMAT(stencil_format
);
2712 surf
->db_depth_info
= S_02803C_ADDR5_SWIZZLE_MASK(!tex
->tc_compatible_htile
);
2714 if (sctx
->chip_class
>= GFX7
) {
2715 struct radeon_info
*info
= &sctx
->screen
->info
;
2716 unsigned index
= tex
->surface
.u
.legacy
.tiling_index
[level
];
2717 unsigned stencil_index
= tex
->surface
.u
.legacy
.stencil_tiling_index
[level
];
2718 unsigned macro_index
= tex
->surface
.u
.legacy
.macro_tile_index
;
2719 unsigned tile_mode
= info
->si_tile_mode_array
[index
];
2720 unsigned stencil_tile_mode
= info
->si_tile_mode_array
[stencil_index
];
2721 unsigned macro_mode
= info
->cik_macrotile_mode_array
[macro_index
];
2723 surf
->db_depth_info
|=
2724 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode
)) |
2725 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode
)) |
2726 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode
)) |
2727 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode
)) |
2728 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode
)) |
2729 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode
));
2730 z_info
|= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode
));
2731 s_info
|= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode
));
2733 unsigned tile_mode_index
= si_tile_mode_index(tex
, level
, false);
2734 z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
2735 tile_mode_index
= si_tile_mode_index(tex
, level
, true);
2736 s_info
|= S_028044_TILE_MODE_INDEX(tile_mode_index
);
2739 surf
->db_depth_size
= S_028058_PITCH_TILE_MAX((levelinfo
->nblk_x
/ 8) - 1) |
2740 S_028058_HEIGHT_TILE_MAX((levelinfo
->nblk_y
/ 8) - 1);
2741 surf
->db_depth_slice
= S_02805C_SLICE_TILE_MAX((levelinfo
->nblk_x
*
2742 levelinfo
->nblk_y
) / 64 - 1);
2744 if (si_htile_enabled(tex
, level
, PIPE_MASK_ZS
)) {
2745 z_info
|= S_028040_TILE_SURFACE_ENABLE(1) |
2746 S_028040_ALLOW_EXPCLEAR(1);
2748 if (tex
->surface
.has_stencil
) {
2749 /* Workaround: For a not yet understood reason, the
2750 * combination of MSAA, fast stencil clear and stencil
2751 * decompress messes with subsequent stencil buffer
2752 * uses. Problem was reproduced on Verde, Bonaire,
2753 * Tonga, and Carrizo.
2755 * Disabling EXPCLEAR works around the problem.
2757 * Check piglit's arb_texture_multisample-stencil-clear
2758 * test if you want to try changing this.
2760 if (tex
->buffer
.b
.b
.nr_samples
<= 1)
2761 s_info
|= S_028044_ALLOW_EXPCLEAR(1);
2762 } else if (!tex
->tc_compatible_htile
) {
2763 /* Use all of the htile_buffer for depth if there's no stencil.
2764 * This must not be set when TC-compatible HTILE is enabled
2767 s_info
|= S_028044_TILE_STENCIL_DISABLE(1);
2770 surf
->db_htile_data_base
= (tex
->buffer
.gpu_address
+
2771 tex
->htile_offset
) >> 8;
2772 surf
->db_htile_surface
= S_028ABC_FULL_CACHE(1);
2774 if (tex
->tc_compatible_htile
) {
2775 surf
->db_htile_surface
|= S_028ABC_TC_COMPATIBLE(1);
2777 /* 0 = full compression. N = only compress up to N-1 Z planes. */
2778 if (tex
->buffer
.b
.b
.nr_samples
<= 1)
2779 z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2780 else if (tex
->buffer
.b
.b
.nr_samples
<= 4)
2781 z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2783 z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2788 surf
->db_z_info
= z_info
;
2789 surf
->db_stencil_info
= s_info
;
2791 surf
->depth_initialized
= true;
2794 void si_update_fb_dirtiness_after_rendering(struct si_context
*sctx
)
2796 if (sctx
->decompression_enabled
)
2799 if (sctx
->framebuffer
.state
.zsbuf
) {
2800 struct pipe_surface
*surf
= sctx
->framebuffer
.state
.zsbuf
;
2801 struct si_texture
*tex
= (struct si_texture
*)surf
->texture
;
2803 tex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2805 if (tex
->surface
.has_stencil
)
2806 tex
->stencil_dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2809 unsigned compressed_cb_mask
= sctx
->framebuffer
.compressed_cb_mask
;
2810 while (compressed_cb_mask
) {
2811 unsigned i
= u_bit_scan(&compressed_cb_mask
);
2812 struct pipe_surface
*surf
= sctx
->framebuffer
.state
.cbufs
[i
];
2813 struct si_texture
*tex
= (struct si_texture
*)surf
->texture
;
2815 if (tex
->fmask_offset
)
2816 tex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2817 if (tex
->dcc_gather_statistics
)
2818 tex
->separate_dcc_dirty
= true;
2822 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state
*state
)
2824 for (int i
= 0; i
< state
->nr_cbufs
; ++i
) {
2825 struct si_surface
*surf
= NULL
;
2826 struct si_texture
*tex
;
2828 if (!state
->cbufs
[i
])
2830 surf
= (struct si_surface
*)state
->cbufs
[i
];
2831 tex
= (struct si_texture
*)surf
->base
.texture
;
2833 p_atomic_dec(&tex
->framebuffers_bound
);
2837 static void si_set_framebuffer_state(struct pipe_context
*ctx
,
2838 const struct pipe_framebuffer_state
*state
)
2840 struct si_context
*sctx
= (struct si_context
*)ctx
;
2841 struct si_surface
*surf
= NULL
;
2842 struct si_texture
*tex
;
2843 bool old_any_dst_linear
= sctx
->framebuffer
.any_dst_linear
;
2844 unsigned old_nr_samples
= sctx
->framebuffer
.nr_samples
;
2845 unsigned old_colorbuf_enabled_4bit
= sctx
->framebuffer
.colorbuf_enabled_4bit
;
2846 bool old_has_zsbuf
= !!sctx
->framebuffer
.state
.zsbuf
;
2847 bool old_has_stencil
=
2849 ((struct si_texture
*)sctx
->framebuffer
.state
.zsbuf
->texture
)->surface
.has_stencil
;
2850 bool unbound
= false;
2853 /* Reject zero-sized framebuffers due to a hw bug on GFX6 that occurs
2854 * when PA_SU_HARDWARE_SCREEN_OFFSET != 0 and any_scissor.BR_X/Y <= 0.
2855 * We could implement the full workaround here, but it's a useless case.
2857 if ((!state
->width
|| !state
->height
) && (state
->nr_cbufs
|| state
->zsbuf
)) {
2858 unreachable("the framebuffer shouldn't have zero area");
2862 si_update_fb_dirtiness_after_rendering(sctx
);
2864 for (i
= 0; i
< sctx
->framebuffer
.state
.nr_cbufs
; i
++) {
2865 if (!sctx
->framebuffer
.state
.cbufs
[i
])
2868 tex
= (struct si_texture
*)sctx
->framebuffer
.state
.cbufs
[i
]->texture
;
2869 if (tex
->dcc_gather_statistics
)
2870 vi_separate_dcc_stop_query(sctx
, tex
);
2873 /* Disable DCC if the formats are incompatible. */
2874 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
2875 if (!state
->cbufs
[i
])
2878 surf
= (struct si_surface
*)state
->cbufs
[i
];
2879 tex
= (struct si_texture
*)surf
->base
.texture
;
2881 if (!surf
->dcc_incompatible
)
2884 /* Since the DCC decompression calls back into set_framebuffer-
2885 * _state, we need to unbind the framebuffer, so that
2886 * vi_separate_dcc_stop_query isn't called twice with the same
2890 util_copy_framebuffer_state(&sctx
->framebuffer
.state
, NULL
);
2894 if (vi_dcc_enabled(tex
, surf
->base
.u
.tex
.level
))
2895 if (!si_texture_disable_dcc(sctx
, tex
))
2896 si_decompress_dcc(sctx
, tex
);
2898 surf
->dcc_incompatible
= false;
2901 /* Only flush TC when changing the framebuffer state, because
2902 * the only client not using TC that can change textures is
2905 * Wait for compute shaders because of possible transitions:
2906 * - FB write -> shader read
2907 * - shader write -> FB read
2909 * DB caches are flushed on demand (using si_decompress_textures).
2911 * When MSAA is enabled, CB and TC caches are flushed on demand
2912 * (after FMASK decompression). Shader write -> FB read transitions
2913 * cannot happen for MSAA textures, because MSAA shader images are
2916 * Only flush and wait for CB if there is actually a bound color buffer.
2918 if (sctx
->framebuffer
.uncompressed_cb_mask
) {
2919 si_make_CB_shader_coherent(sctx
, sctx
->framebuffer
.nr_samples
,
2920 sctx
->framebuffer
.CB_has_shader_readable_metadata
,
2921 sctx
->framebuffer
.all_DCC_pipe_aligned
);
2924 sctx
->flags
|= SI_CONTEXT_CS_PARTIAL_FLUSH
;
2926 /* u_blitter doesn't invoke depth decompression when it does multiple
2927 * blits in a row, but the only case when it matters for DB is when
2928 * doing generate_mipmap. So here we flush DB manually between
2929 * individual generate_mipmap blits.
2930 * Note that lower mipmap levels aren't compressed.
2932 if (sctx
->generate_mipmap_for_depth
) {
2933 si_make_DB_shader_coherent(sctx
, 1, false,
2934 sctx
->framebuffer
.DB_has_shader_readable_metadata
);
2935 } else if (sctx
->chip_class
== GFX9
) {
2936 /* It appears that DB metadata "leaks" in a sequence of:
2938 * - DCC decompress for shader image writes (with DB disabled)
2939 * - render with DEPTH_BEFORE_SHADER=1
2940 * Flushing DB metadata works around the problem.
2942 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_DB_META
;
2945 /* Take the maximum of the old and new count. If the new count is lower,
2946 * dirtying is needed to disable the unbound colorbuffers.
2948 sctx
->framebuffer
.dirty_cbufs
|=
2949 (1 << MAX2(sctx
->framebuffer
.state
.nr_cbufs
, state
->nr_cbufs
)) - 1;
2950 sctx
->framebuffer
.dirty_zsbuf
|= sctx
->framebuffer
.state
.zsbuf
!= state
->zsbuf
;
2952 si_dec_framebuffer_counters(&sctx
->framebuffer
.state
);
2953 util_copy_framebuffer_state(&sctx
->framebuffer
.state
, state
);
2955 sctx
->framebuffer
.colorbuf_enabled_4bit
= 0;
2956 sctx
->framebuffer
.spi_shader_col_format
= 0;
2957 sctx
->framebuffer
.spi_shader_col_format_alpha
= 0;
2958 sctx
->framebuffer
.spi_shader_col_format_blend
= 0;
2959 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
= 0;
2960 sctx
->framebuffer
.color_is_int8
= 0;
2961 sctx
->framebuffer
.color_is_int10
= 0;
2963 sctx
->framebuffer
.compressed_cb_mask
= 0;
2964 sctx
->framebuffer
.uncompressed_cb_mask
= 0;
2965 sctx
->framebuffer
.nr_samples
= util_framebuffer_get_num_samples(state
);
2966 sctx
->framebuffer
.nr_color_samples
= sctx
->framebuffer
.nr_samples
;
2967 sctx
->framebuffer
.log_samples
= util_logbase2(sctx
->framebuffer
.nr_samples
);
2968 sctx
->framebuffer
.any_dst_linear
= false;
2969 sctx
->framebuffer
.CB_has_shader_readable_metadata
= false;
2970 sctx
->framebuffer
.DB_has_shader_readable_metadata
= false;
2971 sctx
->framebuffer
.all_DCC_pipe_aligned
= true;
2972 sctx
->framebuffer
.min_bytes_per_pixel
= 0;
2974 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
2975 if (!state
->cbufs
[i
])
2978 surf
= (struct si_surface
*)state
->cbufs
[i
];
2979 tex
= (struct si_texture
*)surf
->base
.texture
;
2981 if (!surf
->color_initialized
) {
2982 si_initialize_color_surface(sctx
, surf
);
2985 sctx
->framebuffer
.colorbuf_enabled_4bit
|= 0xf << (i
* 4);
2986 sctx
->framebuffer
.spi_shader_col_format
|=
2987 surf
->spi_shader_col_format
<< (i
* 4);
2988 sctx
->framebuffer
.spi_shader_col_format_alpha
|=
2989 surf
->spi_shader_col_format_alpha
<< (i
* 4);
2990 sctx
->framebuffer
.spi_shader_col_format_blend
|=
2991 surf
->spi_shader_col_format_blend
<< (i
* 4);
2992 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
|=
2993 surf
->spi_shader_col_format_blend_alpha
<< (i
* 4);
2995 if (surf
->color_is_int8
)
2996 sctx
->framebuffer
.color_is_int8
|= 1 << i
;
2997 if (surf
->color_is_int10
)
2998 sctx
->framebuffer
.color_is_int10
|= 1 << i
;
3000 if (tex
->fmask_offset
)
3001 sctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
3003 sctx
->framebuffer
.uncompressed_cb_mask
|= 1 << i
;
3005 /* Don't update nr_color_samples for non-AA buffers.
3006 * (e.g. destination of MSAA resolve)
3008 if (tex
->buffer
.b
.b
.nr_samples
>= 2 &&
3009 tex
->buffer
.b
.b
.nr_storage_samples
< tex
->buffer
.b
.b
.nr_samples
) {
3010 sctx
->framebuffer
.nr_color_samples
=
3011 MIN2(sctx
->framebuffer
.nr_color_samples
,
3012 tex
->buffer
.b
.b
.nr_storage_samples
);
3013 sctx
->framebuffer
.nr_color_samples
=
3014 MAX2(1, sctx
->framebuffer
.nr_color_samples
);
3017 if (tex
->surface
.is_linear
)
3018 sctx
->framebuffer
.any_dst_linear
= true;
3020 if (vi_dcc_enabled(tex
, surf
->base
.u
.tex
.level
)) {
3021 sctx
->framebuffer
.CB_has_shader_readable_metadata
= true;
3023 if (sctx
->chip_class
>= GFX9
&&
3024 !tex
->surface
.u
.gfx9
.dcc
.pipe_aligned
)
3025 sctx
->framebuffer
.all_DCC_pipe_aligned
= false;
3028 si_context_add_resource_size(sctx
, surf
->base
.texture
);
3030 p_atomic_inc(&tex
->framebuffers_bound
);
3032 if (tex
->dcc_gather_statistics
) {
3033 /* Dirty tracking must be enabled for DCC usage analysis. */
3034 sctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
3035 vi_separate_dcc_start_query(sctx
, tex
);
3038 /* Update the minimum but don't keep 0. */
3039 if (!sctx
->framebuffer
.min_bytes_per_pixel
||
3040 tex
->surface
.bpe
< sctx
->framebuffer
.min_bytes_per_pixel
)
3041 sctx
->framebuffer
.min_bytes_per_pixel
= tex
->surface
.bpe
;
3044 /* For optimal DCC performance. */
3045 if (sctx
->chip_class
>= GFX10
)
3046 sctx
->framebuffer
.dcc_overwrite_combiner_watermark
= 6;
3048 sctx
->framebuffer
.dcc_overwrite_combiner_watermark
= 4;
3050 struct si_texture
*zstex
= NULL
;
3053 surf
= (struct si_surface
*)state
->zsbuf
;
3054 zstex
= (struct si_texture
*)surf
->base
.texture
;
3056 if (!surf
->depth_initialized
) {
3057 si_init_depth_surface(sctx
, surf
);
3060 if (vi_tc_compat_htile_enabled(zstex
, surf
->base
.u
.tex
.level
,
3062 sctx
->framebuffer
.DB_has_shader_readable_metadata
= true;
3064 si_context_add_resource_size(sctx
, surf
->base
.texture
);
3066 /* Update the minimum but don't keep 0. */
3067 if (!sctx
->framebuffer
.min_bytes_per_pixel
||
3068 zstex
->surface
.bpe
< sctx
->framebuffer
.min_bytes_per_pixel
)
3069 sctx
->framebuffer
.min_bytes_per_pixel
= zstex
->surface
.bpe
;
3072 si_update_ps_colorbuf0_slot(sctx
);
3073 si_update_poly_offset_state(sctx
);
3074 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
3075 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.framebuffer
);
3077 if (sctx
->screen
->dpbb_allowed
)
3078 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
3080 if (sctx
->framebuffer
.any_dst_linear
!= old_any_dst_linear
)
3081 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
3083 if (sctx
->screen
->has_out_of_order_rast
&&
3084 (sctx
->framebuffer
.colorbuf_enabled_4bit
!= old_colorbuf_enabled_4bit
||
3085 !!sctx
->framebuffer
.state
.zsbuf
!= old_has_zsbuf
||
3086 (zstex
&& zstex
->surface
.has_stencil
!= old_has_stencil
)))
3087 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
3089 if (sctx
->framebuffer
.nr_samples
!= old_nr_samples
) {
3090 struct pipe_constant_buffer constbuf
= {0};
3092 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
3093 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
3095 constbuf
.buffer
= sctx
->sample_pos_buffer
;
3097 /* Set sample locations as fragment shader constants. */
3098 switch (sctx
->framebuffer
.nr_samples
) {
3100 constbuf
.buffer_offset
= 0;
3103 constbuf
.buffer_offset
= (ubyte
*)sctx
->sample_positions
.x2
-
3104 (ubyte
*)sctx
->sample_positions
.x1
;
3107 constbuf
.buffer_offset
= (ubyte
*)sctx
->sample_positions
.x4
-
3108 (ubyte
*)sctx
->sample_positions
.x1
;
3111 constbuf
.buffer_offset
= (ubyte
*)sctx
->sample_positions
.x8
-
3112 (ubyte
*)sctx
->sample_positions
.x1
;
3115 constbuf
.buffer_offset
= (ubyte
*)sctx
->sample_positions
.x16
-
3116 (ubyte
*)sctx
->sample_positions
.x1
;
3119 PRINT_ERR("Requested an invalid number of samples %i.\n",
3120 sctx
->framebuffer
.nr_samples
);
3123 constbuf
.buffer_size
= sctx
->framebuffer
.nr_samples
* 2 * 4;
3124 si_set_rw_buffer(sctx
, SI_PS_CONST_SAMPLE_POSITIONS
, &constbuf
);
3126 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_sample_locs
);
3129 sctx
->do_update_shaders
= true;
3131 if (!sctx
->decompression_enabled
) {
3132 /* Prevent textures decompression when the framebuffer state
3133 * changes come from the decompression passes themselves.
3135 sctx
->need_check_render_feedback
= true;
3139 static void si_emit_framebuffer_state(struct si_context
*sctx
)
3141 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
3142 struct pipe_framebuffer_state
*state
= &sctx
->framebuffer
.state
;
3143 unsigned i
, nr_cbufs
= state
->nr_cbufs
;
3144 struct si_texture
*tex
= NULL
;
3145 struct si_surface
*cb
= NULL
;
3146 unsigned cb_color_info
= 0;
3149 for (i
= 0; i
< nr_cbufs
; i
++) {
3150 uint64_t cb_color_base
, cb_color_fmask
, cb_color_cmask
, cb_dcc_base
;
3151 unsigned cb_color_attrib
;
3153 if (!(sctx
->framebuffer
.dirty_cbufs
& (1 << i
)))
3156 cb
= (struct si_surface
*)state
->cbufs
[i
];
3158 radeon_set_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
3159 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
3163 tex
= (struct si_texture
*)cb
->base
.texture
;
3164 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
3165 &tex
->buffer
, RADEON_USAGE_READWRITE
,
3166 tex
->buffer
.b
.b
.nr_samples
> 1 ?
3167 RADEON_PRIO_COLOR_BUFFER_MSAA
:
3168 RADEON_PRIO_COLOR_BUFFER
);
3170 if (tex
->cmask_buffer
&& tex
->cmask_buffer
!= &tex
->buffer
) {
3171 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
3172 tex
->cmask_buffer
, RADEON_USAGE_READWRITE
,
3173 RADEON_PRIO_SEPARATE_META
);
3176 if (tex
->dcc_separate_buffer
)
3177 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
3178 tex
->dcc_separate_buffer
,
3179 RADEON_USAGE_READWRITE
,
3180 RADEON_PRIO_SEPARATE_META
);
3182 /* Compute mutable surface parameters. */
3183 cb_color_base
= tex
->buffer
.gpu_address
>> 8;
3185 cb_color_cmask
= tex
->cmask_base_address_reg
;
3187 cb_color_info
= cb
->cb_color_info
| tex
->cb_color_info
;
3188 cb_color_attrib
= cb
->cb_color_attrib
;
3190 if (cb
->base
.u
.tex
.level
> 0)
3191 cb_color_info
&= C_028C70_FAST_CLEAR
;
3193 if (tex
->fmask_offset
) {
3194 cb_color_fmask
= (tex
->buffer
.gpu_address
+ tex
->fmask_offset
) >> 8;
3195 cb_color_fmask
|= tex
->surface
.fmask_tile_swizzle
;
3199 if (vi_dcc_enabled(tex
, cb
->base
.u
.tex
.level
)) {
3200 bool is_msaa_resolve_dst
= state
->cbufs
[0] &&
3201 state
->cbufs
[0]->texture
->nr_samples
> 1 &&
3202 state
->cbufs
[1] == &cb
->base
&&
3203 state
->cbufs
[1]->texture
->nr_samples
<= 1;
3205 if (!is_msaa_resolve_dst
)
3206 cb_color_info
|= S_028C70_DCC_ENABLE(1);
3208 cb_dcc_base
= ((!tex
->dcc_separate_buffer
? tex
->buffer
.gpu_address
: 0) +
3209 tex
->dcc_offset
) >> 8;
3211 unsigned dcc_tile_swizzle
= tex
->surface
.tile_swizzle
;
3212 dcc_tile_swizzle
&= (tex
->surface
.dcc_alignment
- 1) >> 8;
3213 cb_dcc_base
|= dcc_tile_swizzle
;
3216 if (sctx
->chip_class
>= GFX10
) {
3217 unsigned cb_color_attrib3
;
3219 /* Set mutable surface parameters. */
3220 cb_color_base
+= tex
->surface
.u
.gfx9
.surf_offset
>> 8;
3221 cb_color_base
|= tex
->surface
.tile_swizzle
;
3222 if (!tex
->fmask_offset
)
3223 cb_color_fmask
= cb_color_base
;
3224 if (cb
->base
.u
.tex
.level
> 0)
3225 cb_color_cmask
= cb_color_base
;
3227 cb_color_attrib3
= cb
->cb_color_attrib3
|
3228 S_028EE0_COLOR_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
3229 S_028EE0_FMASK_SW_MODE(tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
) |
3230 S_028EE0_CMASK_PIPE_ALIGNED(tex
->surface
.u
.gfx9
.cmask
.pipe_aligned
) |
3231 S_028EE0_DCC_PIPE_ALIGNED(tex
->surface
.u
.gfx9
.dcc
.pipe_aligned
);
3233 radeon_set_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C, 14);
3234 radeon_emit(cs
, cb_color_base
); /* CB_COLOR0_BASE */
3235 radeon_emit(cs
, 0); /* hole */
3236 radeon_emit(cs
, 0); /* hole */
3237 radeon_emit(cs
, cb
->cb_color_view
); /* CB_COLOR0_VIEW */
3238 radeon_emit(cs
, cb_color_info
); /* CB_COLOR0_INFO */
3239 radeon_emit(cs
, cb_color_attrib
); /* CB_COLOR0_ATTRIB */
3240 radeon_emit(cs
, cb
->cb_dcc_control
); /* CB_COLOR0_DCC_CONTROL */
3241 radeon_emit(cs
, cb_color_cmask
); /* CB_COLOR0_CMASK */
3242 radeon_emit(cs
, 0); /* hole */
3243 radeon_emit(cs
, cb_color_fmask
); /* CB_COLOR0_FMASK */
3244 radeon_emit(cs
, 0); /* hole */
3245 radeon_emit(cs
, tex
->color_clear_value
[0]); /* CB_COLOR0_CLEAR_WORD0 */
3246 radeon_emit(cs
, tex
->color_clear_value
[1]); /* CB_COLOR0_CLEAR_WORD1 */
3247 radeon_emit(cs
, cb_dcc_base
); /* CB_COLOR0_DCC_BASE */
3249 radeon_set_context_reg(cs
, R_028E40_CB_COLOR0_BASE_EXT
+ i
* 4,
3250 cb_color_base
>> 32);
3251 radeon_set_context_reg(cs
, R_028E60_CB_COLOR0_CMASK_BASE_EXT
+ i
* 4,
3252 cb_color_cmask
>> 32);
3253 radeon_set_context_reg(cs
, R_028E80_CB_COLOR0_FMASK_BASE_EXT
+ i
* 4,
3254 cb_color_fmask
>> 32);
3255 radeon_set_context_reg(cs
, R_028EA0_CB_COLOR0_DCC_BASE_EXT
+ i
* 4,
3257 radeon_set_context_reg(cs
, R_028EC0_CB_COLOR0_ATTRIB2
+ i
* 4,
3258 cb
->cb_color_attrib2
);
3259 radeon_set_context_reg(cs
, R_028EE0_CB_COLOR0_ATTRIB3
+ i
* 4,
3261 } else if (sctx
->chip_class
== GFX9
) {
3262 struct gfx9_surf_meta_flags meta
;
3264 if (tex
->dcc_offset
)
3265 meta
= tex
->surface
.u
.gfx9
.dcc
;
3267 meta
= tex
->surface
.u
.gfx9
.cmask
;
3269 /* Set mutable surface parameters. */
3270 cb_color_base
+= tex
->surface
.u
.gfx9
.surf_offset
>> 8;
3271 cb_color_base
|= tex
->surface
.tile_swizzle
;
3272 if (!tex
->fmask_offset
)
3273 cb_color_fmask
= cb_color_base
;
3274 if (cb
->base
.u
.tex
.level
> 0)
3275 cb_color_cmask
= cb_color_base
;
3276 cb_color_attrib
|= S_028C74_COLOR_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
3277 S_028C74_FMASK_SW_MODE(tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
) |
3278 S_028C74_RB_ALIGNED(meta
.rb_aligned
) |
3279 S_028C74_PIPE_ALIGNED(meta
.pipe_aligned
);
3281 radeon_set_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C, 15);
3282 radeon_emit(cs
, cb_color_base
); /* CB_COLOR0_BASE */
3283 radeon_emit(cs
, S_028C64_BASE_256B(cb_color_base
>> 32)); /* CB_COLOR0_BASE_EXT */
3284 radeon_emit(cs
, cb
->cb_color_attrib2
); /* CB_COLOR0_ATTRIB2 */
3285 radeon_emit(cs
, cb
->cb_color_view
); /* CB_COLOR0_VIEW */
3286 radeon_emit(cs
, cb_color_info
); /* CB_COLOR0_INFO */
3287 radeon_emit(cs
, cb_color_attrib
); /* CB_COLOR0_ATTRIB */
3288 radeon_emit(cs
, cb
->cb_dcc_control
); /* CB_COLOR0_DCC_CONTROL */
3289 radeon_emit(cs
, cb_color_cmask
); /* CB_COLOR0_CMASK */
3290 radeon_emit(cs
, S_028C80_BASE_256B(cb_color_cmask
>> 32)); /* CB_COLOR0_CMASK_BASE_EXT */
3291 radeon_emit(cs
, cb_color_fmask
); /* CB_COLOR0_FMASK */
3292 radeon_emit(cs
, S_028C88_BASE_256B(cb_color_fmask
>> 32)); /* CB_COLOR0_FMASK_BASE_EXT */
3293 radeon_emit(cs
, tex
->color_clear_value
[0]); /* CB_COLOR0_CLEAR_WORD0 */
3294 radeon_emit(cs
, tex
->color_clear_value
[1]); /* CB_COLOR0_CLEAR_WORD1 */
3295 radeon_emit(cs
, cb_dcc_base
); /* CB_COLOR0_DCC_BASE */
3296 radeon_emit(cs
, S_028C98_BASE_256B(cb_dcc_base
>> 32)); /* CB_COLOR0_DCC_BASE_EXT */
3298 radeon_set_context_reg(cs
, R_0287A0_CB_MRT0_EPITCH
+ i
* 4,
3299 S_0287A0_EPITCH(tex
->surface
.u
.gfx9
.surf
.epitch
));
3301 /* Compute mutable surface parameters (GFX6-GFX8). */
3302 const struct legacy_surf_level
*level_info
=
3303 &tex
->surface
.u
.legacy
.level
[cb
->base
.u
.tex
.level
];
3304 unsigned pitch_tile_max
, slice_tile_max
, tile_mode_index
;
3305 unsigned cb_color_pitch
, cb_color_slice
, cb_color_fmask_slice
;
3307 cb_color_base
+= level_info
->offset
>> 8;
3308 /* Only macrotiled modes can set tile swizzle. */
3309 if (level_info
->mode
== RADEON_SURF_MODE_2D
)
3310 cb_color_base
|= tex
->surface
.tile_swizzle
;
3312 if (!tex
->fmask_offset
)
3313 cb_color_fmask
= cb_color_base
;
3314 if (cb
->base
.u
.tex
.level
> 0)
3315 cb_color_cmask
= cb_color_base
;
3317 cb_dcc_base
+= level_info
->dcc_offset
>> 8;
3319 pitch_tile_max
= level_info
->nblk_x
/ 8 - 1;
3320 slice_tile_max
= level_info
->nblk_x
*
3321 level_info
->nblk_y
/ 64 - 1;
3322 tile_mode_index
= si_tile_mode_index(tex
, cb
->base
.u
.tex
.level
, false);
3324 cb_color_attrib
|= S_028C74_TILE_MODE_INDEX(tile_mode_index
);
3325 cb_color_pitch
= S_028C64_TILE_MAX(pitch_tile_max
);
3326 cb_color_slice
= S_028C68_TILE_MAX(slice_tile_max
);
3328 if (tex
->fmask_offset
) {
3329 if (sctx
->chip_class
>= GFX7
)
3330 cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(tex
->surface
.u
.legacy
.fmask
.pitch_in_pixels
/ 8 - 1);
3331 cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tex
->surface
.u
.legacy
.fmask
.tiling_index
);
3332 cb_color_fmask_slice
= S_028C88_TILE_MAX(tex
->surface
.u
.legacy
.fmask
.slice_tile_max
);
3334 /* This must be set for fast clear to work without FMASK. */
3335 if (sctx
->chip_class
>= GFX7
)
3336 cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(pitch_tile_max
);
3337 cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index
);
3338 cb_color_fmask_slice
= S_028C88_TILE_MAX(slice_tile_max
);
3341 radeon_set_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C,
3342 sctx
->chip_class
>= GFX8
? 14 : 13);
3343 radeon_emit(cs
, cb_color_base
); /* CB_COLOR0_BASE */
3344 radeon_emit(cs
, cb_color_pitch
); /* CB_COLOR0_PITCH */
3345 radeon_emit(cs
, cb_color_slice
); /* CB_COLOR0_SLICE */
3346 radeon_emit(cs
, cb
->cb_color_view
); /* CB_COLOR0_VIEW */
3347 radeon_emit(cs
, cb_color_info
); /* CB_COLOR0_INFO */
3348 radeon_emit(cs
, cb_color_attrib
); /* CB_COLOR0_ATTRIB */
3349 radeon_emit(cs
, cb
->cb_dcc_control
); /* CB_COLOR0_DCC_CONTROL */
3350 radeon_emit(cs
, cb_color_cmask
); /* CB_COLOR0_CMASK */
3351 radeon_emit(cs
, tex
->surface
.u
.legacy
.cmask_slice_tile_max
); /* CB_COLOR0_CMASK_SLICE */
3352 radeon_emit(cs
, cb_color_fmask
); /* CB_COLOR0_FMASK */
3353 radeon_emit(cs
, cb_color_fmask_slice
); /* CB_COLOR0_FMASK_SLICE */
3354 radeon_emit(cs
, tex
->color_clear_value
[0]); /* CB_COLOR0_CLEAR_WORD0 */
3355 radeon_emit(cs
, tex
->color_clear_value
[1]); /* CB_COLOR0_CLEAR_WORD1 */
3357 if (sctx
->chip_class
>= GFX8
) /* R_028C94_CB_COLOR0_DCC_BASE */
3358 radeon_emit(cs
, cb_dcc_base
);
3362 if (sctx
->framebuffer
.dirty_cbufs
& (1 << i
))
3363 radeon_set_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C, 0);
3366 if (state
->zsbuf
&& sctx
->framebuffer
.dirty_zsbuf
) {
3367 struct si_surface
*zb
= (struct si_surface
*)state
->zsbuf
;
3368 struct si_texture
*tex
= (struct si_texture
*)zb
->base
.texture
;
3370 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
3371 &tex
->buffer
, RADEON_USAGE_READWRITE
,
3372 zb
->base
.texture
->nr_samples
> 1 ?
3373 RADEON_PRIO_DEPTH_BUFFER_MSAA
:
3374 RADEON_PRIO_DEPTH_BUFFER
);
3376 if (sctx
->chip_class
>= GFX10
) {
3377 radeon_set_context_reg(cs
, R_028014_DB_HTILE_DATA_BASE
, zb
->db_htile_data_base
);
3378 radeon_set_context_reg(cs
, R_02801C_DB_DEPTH_SIZE_XY
, zb
->db_depth_size
);
3380 radeon_set_context_reg_seq(cs
, R_02803C_DB_DEPTH_INFO
, 7);
3381 radeon_emit(cs
, S_02803C_RESOURCE_LEVEL(1)); /* DB_DEPTH_INFO */
3382 radeon_emit(cs
, zb
->db_z_info
| /* DB_Z_INFO */
3383 S_028038_ZRANGE_PRECISION(tex
->depth_clear_value
!= 0));
3384 radeon_emit(cs
, zb
->db_stencil_info
); /* DB_STENCIL_INFO */
3385 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_READ_BASE */
3386 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_READ_BASE */
3387 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_WRITE_BASE */
3388 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_WRITE_BASE */
3390 radeon_set_context_reg_seq(cs
, R_028068_DB_Z_READ_BASE_HI
, 5);
3391 radeon_emit(cs
, zb
->db_depth_base
>> 32); /* DB_Z_READ_BASE_HI */
3392 radeon_emit(cs
, zb
->db_stencil_base
>> 32); /* DB_STENCIL_READ_BASE_HI */
3393 radeon_emit(cs
, zb
->db_depth_base
>> 32); /* DB_Z_WRITE_BASE_HI */
3394 radeon_emit(cs
, zb
->db_stencil_base
>> 32); /* DB_STENCIL_WRITE_BASE_HI */
3395 radeon_emit(cs
, zb
->db_htile_data_base
>> 32); /* DB_HTILE_DATA_BASE_HI */
3396 } else if (sctx
->chip_class
== GFX9
) {
3397 radeon_set_context_reg_seq(cs
, R_028014_DB_HTILE_DATA_BASE
, 3);
3398 radeon_emit(cs
, zb
->db_htile_data_base
); /* DB_HTILE_DATA_BASE */
3399 radeon_emit(cs
, S_028018_BASE_HI(zb
->db_htile_data_base
>> 32)); /* DB_HTILE_DATA_BASE_HI */
3400 radeon_emit(cs
, zb
->db_depth_size
); /* DB_DEPTH_SIZE */
3402 radeon_set_context_reg_seq(cs
, R_028038_DB_Z_INFO
, 10);
3403 radeon_emit(cs
, zb
->db_z_info
| /* DB_Z_INFO */
3404 S_028038_ZRANGE_PRECISION(tex
->depth_clear_value
!= 0));
3405 radeon_emit(cs
, zb
->db_stencil_info
); /* DB_STENCIL_INFO */
3406 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_READ_BASE */
3407 radeon_emit(cs
, S_028044_BASE_HI(zb
->db_depth_base
>> 32)); /* DB_Z_READ_BASE_HI */
3408 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_READ_BASE */
3409 radeon_emit(cs
, S_02804C_BASE_HI(zb
->db_stencil_base
>> 32)); /* DB_STENCIL_READ_BASE_HI */
3410 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_WRITE_BASE */
3411 radeon_emit(cs
, S_028054_BASE_HI(zb
->db_depth_base
>> 32)); /* DB_Z_WRITE_BASE_HI */
3412 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_WRITE_BASE */
3413 radeon_emit(cs
, S_02805C_BASE_HI(zb
->db_stencil_base
>> 32)); /* DB_STENCIL_WRITE_BASE_HI */
3415 radeon_set_context_reg_seq(cs
, R_028068_DB_Z_INFO2
, 2);
3416 radeon_emit(cs
, zb
->db_z_info2
); /* DB_Z_INFO2 */
3417 radeon_emit(cs
, zb
->db_stencil_info2
); /* DB_STENCIL_INFO2 */
3419 radeon_set_context_reg(cs
, R_028014_DB_HTILE_DATA_BASE
, zb
->db_htile_data_base
);
3421 radeon_set_context_reg_seq(cs
, R_02803C_DB_DEPTH_INFO
, 9);
3422 radeon_emit(cs
, zb
->db_depth_info
); /* DB_DEPTH_INFO */
3423 radeon_emit(cs
, zb
->db_z_info
| /* DB_Z_INFO */
3424 S_028040_ZRANGE_PRECISION(tex
->depth_clear_value
!= 0));
3425 radeon_emit(cs
, zb
->db_stencil_info
); /* DB_STENCIL_INFO */
3426 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_READ_BASE */
3427 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_READ_BASE */
3428 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_WRITE_BASE */
3429 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_WRITE_BASE */
3430 radeon_emit(cs
, zb
->db_depth_size
); /* DB_DEPTH_SIZE */
3431 radeon_emit(cs
, zb
->db_depth_slice
); /* DB_DEPTH_SLICE */
3434 radeon_set_context_reg_seq(cs
, R_028028_DB_STENCIL_CLEAR
, 2);
3435 radeon_emit(cs
, tex
->stencil_clear_value
); /* R_028028_DB_STENCIL_CLEAR */
3436 radeon_emit(cs
, fui(tex
->depth_clear_value
)); /* R_02802C_DB_DEPTH_CLEAR */
3438 radeon_set_context_reg(cs
, R_028008_DB_DEPTH_VIEW
, zb
->db_depth_view
);
3439 radeon_set_context_reg(cs
, R_028ABC_DB_HTILE_SURFACE
, zb
->db_htile_surface
);
3440 } else if (sctx
->framebuffer
.dirty_zsbuf
) {
3441 if (sctx
->chip_class
== GFX9
)
3442 radeon_set_context_reg_seq(cs
, R_028038_DB_Z_INFO
, 2);
3444 radeon_set_context_reg_seq(cs
, R_028040_DB_Z_INFO
, 2);
3446 radeon_emit(cs
, S_028040_FORMAT(V_028040_Z_INVALID
)); /* DB_Z_INFO */
3447 radeon_emit(cs
, S_028044_FORMAT(V_028044_STENCIL_INVALID
)); /* DB_STENCIL_INFO */
3450 /* Framebuffer dimensions. */
3451 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
3452 radeon_set_context_reg(cs
, R_028208_PA_SC_WINDOW_SCISSOR_BR
,
3453 S_028208_BR_X(state
->width
) | S_028208_BR_Y(state
->height
));
3455 if (sctx
->screen
->dfsm_allowed
) {
3456 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3457 radeon_emit(cs
, EVENT_TYPE(V_028A90_BREAK_BATCH
) | EVENT_INDEX(0));
3460 sctx
->framebuffer
.dirty_cbufs
= 0;
3461 sctx
->framebuffer
.dirty_zsbuf
= false;
3464 static void si_emit_msaa_sample_locs(struct si_context
*sctx
)
3466 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
3467 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
3468 unsigned nr_samples
= sctx
->framebuffer
.nr_samples
;
3469 bool has_msaa_sample_loc_bug
= sctx
->screen
->info
.has_msaa_sample_loc_bug
;
3471 /* Smoothing (only possible with nr_samples == 1) uses the same
3472 * sample locations as the MSAA it simulates.
3474 if (nr_samples
<= 1 && sctx
->smoothing_enabled
)
3475 nr_samples
= SI_NUM_SMOOTH_AA_SAMPLES
;
3477 /* On Polaris, the small primitive filter uses the sample locations
3478 * even when MSAA is off, so we need to make sure they're set to 0.
3480 * GFX10 uses sample locations unconditionally, so they always need
3483 if ((nr_samples
>= 2 || has_msaa_sample_loc_bug
||
3484 sctx
->chip_class
>= GFX10
) &&
3485 nr_samples
!= sctx
->sample_locs_num_samples
) {
3486 sctx
->sample_locs_num_samples
= nr_samples
;
3487 si_emit_sample_locations(cs
, nr_samples
);
3490 if (sctx
->family
>= CHIP_POLARIS10
) {
3491 unsigned small_prim_filter_cntl
=
3492 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
3494 S_028830_LINE_FILTER_DISABLE(sctx
->family
<= CHIP_POLARIS12
);
3496 /* The alternative of setting sample locations to 0 would
3497 * require a DB flush to avoid Z errors, see
3498 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
3500 if (has_msaa_sample_loc_bug
&&
3501 sctx
->framebuffer
.nr_samples
> 1 &&
3502 !rs
->multisample_enable
)
3503 small_prim_filter_cntl
&= C_028830_SMALL_PRIM_FILTER_ENABLE
;
3505 radeon_opt_set_context_reg(sctx
,
3506 R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL
,
3507 SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL
,
3508 small_prim_filter_cntl
);
3511 /* The exclusion bits can be set to improve rasterization efficiency
3512 * if no sample lies on the pixel boundary (-8 sample offset).
3514 bool exclusion
= sctx
->chip_class
>= GFX7
&&
3515 (!rs
->multisample_enable
|| nr_samples
!= 16);
3516 radeon_opt_set_context_reg(sctx
, R_02882C_PA_SU_PRIM_FILTER_CNTL
,
3517 SI_TRACKED_PA_SU_PRIM_FILTER_CNTL
,
3518 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion
) |
3519 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion
));
3522 static bool si_out_of_order_rasterization(struct si_context
*sctx
)
3524 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
3525 struct si_state_dsa
*dsa
= sctx
->queued
.named
.dsa
;
3527 if (!sctx
->screen
->has_out_of_order_rast
)
3530 unsigned colormask
= sctx
->framebuffer
.colorbuf_enabled_4bit
;
3532 colormask
&= blend
->cb_target_enabled_4bit
;
3534 /* Conservative: No logic op. */
3535 if (colormask
&& blend
->logicop_enable
)
3538 struct si_dsa_order_invariance dsa_order_invariant
= {
3539 .zs
= true, .pass_set
= true, .pass_last
= false
3542 if (sctx
->framebuffer
.state
.zsbuf
) {
3543 struct si_texture
*zstex
=
3544 (struct si_texture
*)sctx
->framebuffer
.state
.zsbuf
->texture
;
3545 bool has_stencil
= zstex
->surface
.has_stencil
;
3546 dsa_order_invariant
= dsa
->order_invariance
[has_stencil
];
3547 if (!dsa_order_invariant
.zs
)
3550 /* The set of PS invocations is always order invariant,
3551 * except when early Z/S tests are requested. */
3552 if (sctx
->ps_shader
.cso
&&
3553 sctx
->ps_shader
.cso
->info
.writes_memory
&&
3554 sctx
->ps_shader
.cso
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
] &&
3555 !dsa_order_invariant
.pass_set
)
3558 if (sctx
->num_perfect_occlusion_queries
!= 0 &&
3559 !dsa_order_invariant
.pass_set
)
3566 unsigned blendmask
= colormask
& blend
->blend_enable_4bit
;
3569 /* Only commutative blending. */
3570 if (blendmask
& ~blend
->commutative_4bit
)
3573 if (!dsa_order_invariant
.pass_set
)
3577 if (colormask
& ~blendmask
) {
3578 if (!dsa_order_invariant
.pass_last
)
3585 static void si_emit_msaa_config(struct si_context
*sctx
)
3587 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
3588 unsigned num_tile_pipes
= sctx
->screen
->info
.num_tile_pipes
;
3589 /* 33% faster rendering to linear color buffers */
3590 bool dst_is_linear
= sctx
->framebuffer
.any_dst_linear
;
3591 bool out_of_order_rast
= si_out_of_order_rasterization(sctx
);
3592 unsigned sc_mode_cntl_1
=
3593 S_028A4C_WALK_SIZE(dst_is_linear
) |
3594 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear
) |
3595 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes
== 2 ? 2 : 3) |
3596 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast
) |
3597 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
3599 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
3600 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
3601 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
3602 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
3603 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
3604 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
3605 unsigned db_eqaa
= S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3606 S_028804_INCOHERENT_EQAA_READS(1) |
3607 S_028804_INTERPOLATE_COMP_Z(1) |
3608 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
3609 unsigned coverage_samples
, color_samples
, z_samples
;
3610 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
3612 /* S: Coverage samples (up to 16x):
3613 * - Scan conversion samples (PA_SC_AA_CONFIG.MSAA_NUM_SAMPLES)
3614 * - CB FMASK samples (CB_COLORi_ATTRIB.NUM_SAMPLES)
3616 * Z: Z/S samples (up to 8x, must be <= coverage samples and >= color samples):
3617 * - Value seen by DB (DB_Z_INFO.NUM_SAMPLES)
3618 * - Value seen by CB, must be correct even if Z/S is unbound (DB_EQAA.MAX_ANCHOR_SAMPLES)
3619 * # Missing samples are derived from Z planes if Z is compressed (up to 16x quality), or
3620 * # from the closest defined sample if Z is uncompressed (same quality as the number of
3623 * F: Color samples (up to 8x, must be <= coverage samples):
3624 * - CB color samples (CB_COLORi_ATTRIB.NUM_FRAGMENTS)
3625 * - PS iter samples (DB_EQAA.PS_ITER_SAMPLES)
3627 * Can be anything between coverage and color samples:
3628 * - SampleMaskIn samples (PA_SC_AA_CONFIG.MSAA_EXPOSED_SAMPLES)
3629 * - SampleMaskOut samples (DB_EQAA.MASK_EXPORT_NUM_SAMPLES)
3630 * - Alpha-to-coverage samples (DB_EQAA.ALPHA_TO_MASK_NUM_SAMPLES)
3631 * - Occlusion query samples (DB_COUNT_CONTROL.SAMPLE_RATE)
3632 * # All are currently set the same as coverage samples.
3634 * If color samples < coverage samples, FMASK has a higher bpp to store an "unknown"
3635 * flag for undefined color samples. A shader-based resolve must handle unknowns
3636 * or mask them out with AND. Unknowns can also be guessed from neighbors via
3637 * an edge-detect shader-based resolve, which is required to make "color samples = 1"
3638 * useful. The CB resolve always drops unknowns.
3640 * Sensible AA configurations:
3641 * EQAA 16s 8z 8f - might look the same as 16x MSAA if Z is compressed
3642 * EQAA 16s 8z 4f - might look the same as 16x MSAA if Z is compressed
3643 * EQAA 16s 4z 4f - might look the same as 16x MSAA if Z is compressed
3644 * EQAA 8s 8z 8f = 8x MSAA
3645 * EQAA 8s 8z 4f - might look the same as 8x MSAA
3646 * EQAA 8s 8z 2f - might look the same as 8x MSAA with low-density geometry
3647 * EQAA 8s 4z 4f - might look the same as 8x MSAA if Z is compressed
3648 * EQAA 8s 4z 2f - might look the same as 8x MSAA with low-density geometry if Z is compressed
3649 * EQAA 4s 4z 4f = 4x MSAA
3650 * EQAA 4s 4z 2f - might look the same as 4x MSAA with low-density geometry
3651 * EQAA 2s 2z 2f = 2x MSAA
3653 if (sctx
->framebuffer
.nr_samples
> 1 && rs
->multisample_enable
) {
3654 coverage_samples
= sctx
->framebuffer
.nr_samples
;
3655 color_samples
= sctx
->framebuffer
.nr_color_samples
;
3657 if (sctx
->framebuffer
.state
.zsbuf
) {
3658 z_samples
= sctx
->framebuffer
.state
.zsbuf
->texture
->nr_samples
;
3659 z_samples
= MAX2(1, z_samples
);
3661 z_samples
= coverage_samples
;
3663 } else if (sctx
->smoothing_enabled
) {
3664 coverage_samples
= color_samples
= z_samples
= SI_NUM_SMOOTH_AA_SAMPLES
;
3666 coverage_samples
= color_samples
= z_samples
= 1;
3669 /* Required by OpenGL line rasterization.
3671 * TODO: We should also enable perpendicular endcaps for AA lines,
3672 * but that requires implementing line stippling in the pixel
3673 * shader. SC can only do line stippling with axis-aligned
3676 unsigned sc_line_cntl
= S_028BDC_DX10_DIAMOND_TEST_ENA(1);
3677 unsigned sc_aa_config
= 0;
3679 if (coverage_samples
> 1) {
3680 /* distance from the pixel center, indexed by log2(nr_samples) */
3681 static unsigned max_dist
[] = {
3688 unsigned log_samples
= util_logbase2(coverage_samples
);
3689 unsigned log_z_samples
= util_logbase2(z_samples
);
3690 unsigned ps_iter_samples
= si_get_ps_iter_samples(sctx
);
3691 unsigned log_ps_iter_samples
= util_logbase2(ps_iter_samples
);
3693 sc_line_cntl
|= S_028BDC_EXPAND_LINE_WIDTH(1);
3694 sc_aa_config
= S_028BE0_MSAA_NUM_SAMPLES(log_samples
) |
3695 S_028BE0_MAX_SAMPLE_DIST(max_dist
[log_samples
]) |
3696 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples
);
3698 if (sctx
->framebuffer
.nr_samples
> 1) {
3699 db_eqaa
|= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples
) |
3700 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples
) |
3701 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples
) |
3702 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples
);
3703 sc_mode_cntl_1
|= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples
> 1);
3704 } else if (sctx
->smoothing_enabled
) {
3705 db_eqaa
|= S_028804_OVERRASTERIZATION_AMOUNT(log_samples
);
3709 unsigned initial_cdw
= cs
->current
.cdw
;
3711 /* R_028BDC_PA_SC_LINE_CNTL, R_028BE0_PA_SC_AA_CONFIG */
3712 radeon_opt_set_context_reg2(sctx
, R_028BDC_PA_SC_LINE_CNTL
,
3713 SI_TRACKED_PA_SC_LINE_CNTL
, sc_line_cntl
,
3715 /* R_028804_DB_EQAA */
3716 radeon_opt_set_context_reg(sctx
, R_028804_DB_EQAA
, SI_TRACKED_DB_EQAA
,
3718 /* R_028A4C_PA_SC_MODE_CNTL_1 */
3719 radeon_opt_set_context_reg(sctx
, R_028A4C_PA_SC_MODE_CNTL_1
,
3720 SI_TRACKED_PA_SC_MODE_CNTL_1
, sc_mode_cntl_1
);
3722 if (initial_cdw
!= cs
->current
.cdw
) {
3723 sctx
->context_roll
= true;
3725 /* GFX9: Flush DFSM when the AA mode changes. */
3726 if (sctx
->screen
->dfsm_allowed
) {
3727 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3728 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
3733 void si_update_ps_iter_samples(struct si_context
*sctx
)
3735 if (sctx
->framebuffer
.nr_samples
> 1)
3736 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
3737 if (sctx
->screen
->dpbb_allowed
)
3738 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
3741 static void si_set_min_samples(struct pipe_context
*ctx
, unsigned min_samples
)
3743 struct si_context
*sctx
= (struct si_context
*)ctx
;
3745 /* The hardware can only do sample shading with 2^n samples. */
3746 min_samples
= util_next_power_of_two(min_samples
);
3748 if (sctx
->ps_iter_samples
== min_samples
)
3751 sctx
->ps_iter_samples
= min_samples
;
3752 sctx
->do_update_shaders
= true;
3754 si_update_ps_iter_samples(sctx
);
3762 * Build the sampler view descriptor for a buffer texture.
3763 * @param state 256-bit descriptor; only the high 128 bits are filled in
3766 si_make_buffer_descriptor(struct si_screen
*screen
, struct si_resource
*buf
,
3767 enum pipe_format format
,
3768 unsigned offset
, unsigned size
,
3771 const struct util_format_description
*desc
;
3773 unsigned num_records
;
3775 desc
= util_format_description(format
);
3776 stride
= desc
->block
.bits
/ 8;
3778 num_records
= size
/ stride
;
3779 num_records
= MIN2(num_records
, (buf
->b
.b
.width0
- offset
) / stride
);
3781 /* The NUM_RECORDS field has a different meaning depending on the chip,
3782 * instruction type, STRIDE, and SWIZZLE_ENABLE.
3785 * - If STRIDE == 0, it's in byte units.
3786 * - If STRIDE != 0, it's in units of STRIDE, used with inst.IDXEN.
3789 * - For SMEM and STRIDE == 0, it's in byte units.
3790 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3791 * - For VMEM and STRIDE == 0 or SWIZZLE_ENABLE == 0, it's in byte units.
3792 * - For VMEM and STRIDE != 0 and SWIZZLE_ENABLE == 1, it's in units of STRIDE.
3793 * NOTE: There is incompatibility between VMEM and SMEM opcodes due to SWIZZLE_-
3794 * ENABLE. The workaround is to set STRIDE = 0 if SWIZZLE_ENABLE == 0 when
3795 * using SMEM. This can be done in the shader by clearing STRIDE with s_and.
3796 * That way the same descriptor can be used by both SMEM and VMEM.
3799 * - For SMEM and STRIDE == 0, it's in byte units.
3800 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3801 * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
3802 * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
3804 if (screen
->info
.chip_class
== GFX8
)
3805 num_records
*= stride
;
3808 state
[5] = S_008F04_STRIDE(stride
);
3809 state
[6] = num_records
;
3810 state
[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc
->swizzle
[0])) |
3811 S_008F0C_DST_SEL_Y(si_map_swizzle(desc
->swizzle
[1])) |
3812 S_008F0C_DST_SEL_Z(si_map_swizzle(desc
->swizzle
[2])) |
3813 S_008F0C_DST_SEL_W(si_map_swizzle(desc
->swizzle
[3]));
3815 if (screen
->info
.chip_class
>= GFX10
) {
3816 const struct gfx10_format
*fmt
= &gfx10_format_table
[format
];
3818 /* OOB_SELECT chooses the out-of-bounds check:
3819 * - 0: (index >= NUM_RECORDS) || (offset >= STRIDE)
3820 * - 1: index >= NUM_RECORDS
3821 * - 2: NUM_RECORDS == 0
3822 * - 3: if SWIZZLE_ENABLE == 0: offset >= NUM_RECORDS
3823 * else: swizzle_address >= NUM_RECORDS
3825 state
[7] |= S_008F0C_FORMAT(fmt
->img_format
) |
3826 S_008F0C_OOB_SELECT(0) |
3827 S_008F0C_RESOURCE_LEVEL(1);
3830 unsigned num_format
, data_format
;
3832 first_non_void
= util_format_get_first_non_void_channel(format
);
3833 num_format
= si_translate_buffer_numformat(&screen
->b
, desc
, first_non_void
);
3834 data_format
= si_translate_buffer_dataformat(&screen
->b
, desc
, first_non_void
);
3836 state
[7] |= S_008F0C_NUM_FORMAT(num_format
) |
3837 S_008F0C_DATA_FORMAT(data_format
);
3841 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle
[4])
3843 unsigned bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
3845 if (swizzle
[3] == PIPE_SWIZZLE_X
) {
3846 /* For the pre-defined border color values (white, opaque
3847 * black, transparent black), the only thing that matters is
3848 * that the alpha channel winds up in the correct place
3849 * (because the RGB channels are all the same) so either of
3850 * these enumerations will work.
3852 if (swizzle
[2] == PIPE_SWIZZLE_Y
)
3853 bc_swizzle
= V_008F20_BC_SWIZZLE_WZYX
;
3855 bc_swizzle
= V_008F20_BC_SWIZZLE_WXYZ
;
3856 } else if (swizzle
[0] == PIPE_SWIZZLE_X
) {
3857 if (swizzle
[1] == PIPE_SWIZZLE_Y
)
3858 bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
3860 bc_swizzle
= V_008F20_BC_SWIZZLE_XWYZ
;
3861 } else if (swizzle
[1] == PIPE_SWIZZLE_X
) {
3862 bc_swizzle
= V_008F20_BC_SWIZZLE_YXWZ
;
3863 } else if (swizzle
[2] == PIPE_SWIZZLE_X
) {
3864 bc_swizzle
= V_008F20_BC_SWIZZLE_ZYXW
;
3871 * Build the sampler view descriptor for a texture.
3874 gfx10_make_texture_descriptor(struct si_screen
*screen
,
3875 struct si_texture
*tex
,
3877 enum pipe_texture_target target
,
3878 enum pipe_format pipe_format
,
3879 const unsigned char state_swizzle
[4],
3880 unsigned first_level
, unsigned last_level
,
3881 unsigned first_layer
, unsigned last_layer
,
3882 unsigned width
, unsigned height
, unsigned depth
,
3884 uint32_t *fmask_state
)
3886 struct pipe_resource
*res
= &tex
->buffer
.b
.b
;
3887 const struct util_format_description
*desc
;
3888 unsigned img_format
;
3889 unsigned char swizzle
[4];
3893 desc
= util_format_description(pipe_format
);
3894 img_format
= gfx10_format_table
[pipe_format
].img_format
;
3896 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
) {
3897 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
3898 const unsigned char swizzle_yyyy
[4] = {1, 1, 1, 1};
3899 const unsigned char swizzle_wwww
[4] = {3, 3, 3, 3};
3900 bool is_stencil
= false;
3902 switch (pipe_format
) {
3903 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
3904 case PIPE_FORMAT_X32_S8X24_UINT
:
3905 case PIPE_FORMAT_X8Z24_UNORM
:
3906 util_format_compose_swizzles(swizzle_yyyy
, state_swizzle
, swizzle
);
3909 case PIPE_FORMAT_X24S8_UINT
:
3911 * X24S8 is implemented as an 8_8_8_8 data format, to
3912 * fix texture gathers. This affects at least
3913 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
3915 util_format_compose_swizzles(swizzle_wwww
, state_swizzle
, swizzle
);
3919 util_format_compose_swizzles(swizzle_xxxx
, state_swizzle
, swizzle
);
3920 is_stencil
= pipe_format
== PIPE_FORMAT_S8_UINT
;
3923 if (tex
->upgraded_depth
&& !is_stencil
) {
3924 assert(img_format
== V_008F0C_IMG_FORMAT_32_FLOAT
);
3925 img_format
= V_008F0C_IMG_FORMAT_32_FLOAT_CLAMP
;
3928 util_format_compose_swizzles(desc
->swizzle
, state_swizzle
, swizzle
);
3932 (res
->target
== PIPE_TEXTURE_CUBE
||
3933 res
->target
== PIPE_TEXTURE_CUBE_ARRAY
)) {
3934 /* For the purpose of shader images, treat cube maps as 2D
3937 type
= V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
3939 type
= si_tex_dim(screen
, tex
, target
, res
->nr_samples
);
3942 if (type
== V_008F1C_SQ_RSRC_IMG_1D_ARRAY
) {
3944 depth
= res
->array_size
;
3945 } else if (type
== V_008F1C_SQ_RSRC_IMG_2D_ARRAY
||
3946 type
== V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
) {
3947 if (sampler
|| res
->target
!= PIPE_TEXTURE_3D
)
3948 depth
= res
->array_size
;
3949 } else if (type
== V_008F1C_SQ_RSRC_IMG_CUBE
)
3950 depth
= res
->array_size
/ 6;
3953 state
[1] = S_00A004_FORMAT(img_format
) |
3954 S_00A004_WIDTH_LO(width
- 1);
3955 state
[2] = S_00A008_WIDTH_HI((width
- 1) >> 2) |
3956 S_00A008_HEIGHT(height
- 1) |
3957 S_00A008_RESOURCE_LEVEL(1);
3958 state
[3] = S_00A00C_DST_SEL_X(si_map_swizzle(swizzle
[0])) |
3959 S_00A00C_DST_SEL_Y(si_map_swizzle(swizzle
[1])) |
3960 S_00A00C_DST_SEL_Z(si_map_swizzle(swizzle
[2])) |
3961 S_00A00C_DST_SEL_W(si_map_swizzle(swizzle
[3])) |
3962 S_00A00C_BASE_LEVEL(res
->nr_samples
> 1 ?
3964 S_00A00C_LAST_LEVEL(res
->nr_samples
> 1 ?
3965 util_logbase2(res
->nr_samples
) :
3967 S_00A00C_BC_SWIZZLE(gfx9_border_color_swizzle(desc
->swizzle
)) |
3968 S_00A00C_TYPE(type
);
3969 /* Depth is the the last accessible layer on gfx9+. The hw doesn't need
3970 * to know the total number of layers.
3972 state
[4] = S_00A010_DEPTH((type
== V_008F1C_SQ_RSRC_IMG_3D
&& sampler
)
3973 ? depth
- 1 : last_layer
) |
3974 S_00A010_BASE_ARRAY(first_layer
);
3975 state
[5] = S_00A014_ARRAY_PITCH(!!(type
== V_008F1C_SQ_RSRC_IMG_3D
&& !sampler
)) |
3976 S_00A014_MAX_MIP(res
->nr_samples
> 1 ?
3977 util_logbase2(res
->nr_samples
) :
3978 tex
->buffer
.b
.b
.last_level
) |
3979 S_00A014_PERF_MOD(4);
3983 if (tex
->dcc_offset
) {
3984 state
[6] |= S_00A018_MAX_UNCOMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_256B
) |
3985 S_00A018_MAX_COMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_128B
) |
3986 S_00A018_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(screen
, pipe_format
));
3989 /* Initialize the sampler view for FMASK. */
3990 if (tex
->fmask_offset
) {
3993 va
= tex
->buffer
.gpu_address
+ tex
->fmask_offset
;
3995 #define FMASK(s,f) (((unsigned)(MAX2(1, s)) * 16) + (MAX2(1, f)))
3996 switch (FMASK(res
->nr_samples
, res
->nr_storage_samples
)) {
3998 format
= V_008F0C_IMG_FORMAT_FMASK8_S2_F1
;
4001 format
= V_008F0C_IMG_FORMAT_FMASK8_S2_F2
;
4004 format
= V_008F0C_IMG_FORMAT_FMASK8_S4_F1
;
4007 format
= V_008F0C_IMG_FORMAT_FMASK8_S4_F2
;
4010 format
= V_008F0C_IMG_FORMAT_FMASK8_S4_F4
;
4013 format
= V_008F0C_IMG_FORMAT_FMASK8_S8_F1
;
4016 format
= V_008F0C_IMG_FORMAT_FMASK16_S8_F2
;
4019 format
= V_008F0C_IMG_FORMAT_FMASK32_S8_F4
;
4022 format
= V_008F0C_IMG_FORMAT_FMASK32_S8_F8
;
4025 format
= V_008F0C_IMG_FORMAT_FMASK16_S16_F1
;
4028 format
= V_008F0C_IMG_FORMAT_FMASK32_S16_F2
;
4031 format
= V_008F0C_IMG_FORMAT_FMASK64_S16_F4
;
4034 format
= V_008F0C_IMG_FORMAT_FMASK64_S16_F8
;
4037 unreachable("invalid nr_samples");
4040 fmask_state
[0] = (va
>> 8) | tex
->surface
.fmask_tile_swizzle
;
4041 fmask_state
[1] = S_00A004_BASE_ADDRESS_HI(va
>> 40) |
4042 S_00A004_FORMAT(format
) |
4043 S_00A004_WIDTH_LO(width
- 1);
4044 fmask_state
[2] = S_00A008_WIDTH_HI((width
- 1) >> 2) |
4045 S_00A008_HEIGHT(height
- 1) |
4046 S_00A008_RESOURCE_LEVEL(1);
4047 fmask_state
[3] = S_00A00C_DST_SEL_X(V_008F1C_SQ_SEL_X
) |
4048 S_00A00C_DST_SEL_Y(V_008F1C_SQ_SEL_X
) |
4049 S_00A00C_DST_SEL_Z(V_008F1C_SQ_SEL_X
) |
4050 S_00A00C_DST_SEL_W(V_008F1C_SQ_SEL_X
) |
4051 S_00A00C_SW_MODE(tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
) |
4052 S_00A00C_TYPE(si_tex_dim(screen
, tex
, target
, 0));
4053 fmask_state
[4] = S_00A010_DEPTH(last_layer
) |
4054 S_00A010_BASE_ARRAY(first_layer
);
4056 fmask_state
[6] = S_00A018_META_PIPE_ALIGNED(tex
->surface
.u
.gfx9
.cmask
.pipe_aligned
);
4062 * Build the sampler view descriptor for a texture (SI-GFX9).
4065 si_make_texture_descriptor(struct si_screen
*screen
,
4066 struct si_texture
*tex
,
4068 enum pipe_texture_target target
,
4069 enum pipe_format pipe_format
,
4070 const unsigned char state_swizzle
[4],
4071 unsigned first_level
, unsigned last_level
,
4072 unsigned first_layer
, unsigned last_layer
,
4073 unsigned width
, unsigned height
, unsigned depth
,
4075 uint32_t *fmask_state
)
4077 struct pipe_resource
*res
= &tex
->buffer
.b
.b
;
4078 const struct util_format_description
*desc
;
4079 unsigned char swizzle
[4];
4081 unsigned num_format
, data_format
, type
, num_samples
;
4084 desc
= util_format_description(pipe_format
);
4086 num_samples
= desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
?
4087 MAX2(1, res
->nr_samples
) :
4088 MAX2(1, res
->nr_storage_samples
);
4090 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
) {
4091 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
4092 const unsigned char swizzle_yyyy
[4] = {1, 1, 1, 1};
4093 const unsigned char swizzle_wwww
[4] = {3, 3, 3, 3};
4095 switch (pipe_format
) {
4096 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
4097 case PIPE_FORMAT_X32_S8X24_UINT
:
4098 case PIPE_FORMAT_X8Z24_UNORM
:
4099 util_format_compose_swizzles(swizzle_yyyy
, state_swizzle
, swizzle
);
4101 case PIPE_FORMAT_X24S8_UINT
:
4103 * X24S8 is implemented as an 8_8_8_8 data format, to
4104 * fix texture gathers. This affects at least
4105 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
4107 if (screen
->info
.chip_class
<= GFX8
)
4108 util_format_compose_swizzles(swizzle_wwww
, state_swizzle
, swizzle
);
4110 util_format_compose_swizzles(swizzle_yyyy
, state_swizzle
, swizzle
);
4113 util_format_compose_swizzles(swizzle_xxxx
, state_swizzle
, swizzle
);
4116 util_format_compose_swizzles(desc
->swizzle
, state_swizzle
, swizzle
);
4119 first_non_void
= util_format_get_first_non_void_channel(pipe_format
);
4121 switch (pipe_format
) {
4122 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
4123 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
4126 if (first_non_void
< 0) {
4127 if (util_format_is_compressed(pipe_format
)) {
4128 switch (pipe_format
) {
4129 case PIPE_FORMAT_DXT1_SRGB
:
4130 case PIPE_FORMAT_DXT1_SRGBA
:
4131 case PIPE_FORMAT_DXT3_SRGBA
:
4132 case PIPE_FORMAT_DXT5_SRGBA
:
4133 case PIPE_FORMAT_BPTC_SRGBA
:
4134 case PIPE_FORMAT_ETC2_SRGB8
:
4135 case PIPE_FORMAT_ETC2_SRGB8A1
:
4136 case PIPE_FORMAT_ETC2_SRGBA8
:
4137 num_format
= V_008F14_IMG_NUM_FORMAT_SRGB
;
4139 case PIPE_FORMAT_RGTC1_SNORM
:
4140 case PIPE_FORMAT_LATC1_SNORM
:
4141 case PIPE_FORMAT_RGTC2_SNORM
:
4142 case PIPE_FORMAT_LATC2_SNORM
:
4143 case PIPE_FORMAT_ETC2_R11_SNORM
:
4144 case PIPE_FORMAT_ETC2_RG11_SNORM
:
4145 /* implies float, so use SNORM/UNORM to determine
4146 whether data is signed or not */
4147 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
4148 num_format
= V_008F14_IMG_NUM_FORMAT_SNORM
;
4151 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
4154 } else if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
4155 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
4157 num_format
= V_008F14_IMG_NUM_FORMAT_FLOAT
;
4159 } else if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
) {
4160 num_format
= V_008F14_IMG_NUM_FORMAT_SRGB
;
4162 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
4164 switch (desc
->channel
[first_non_void
].type
) {
4165 case UTIL_FORMAT_TYPE_FLOAT
:
4166 num_format
= V_008F14_IMG_NUM_FORMAT_FLOAT
;
4168 case UTIL_FORMAT_TYPE_SIGNED
:
4169 if (desc
->channel
[first_non_void
].normalized
)
4170 num_format
= V_008F14_IMG_NUM_FORMAT_SNORM
;
4171 else if (desc
->channel
[first_non_void
].pure_integer
)
4172 num_format
= V_008F14_IMG_NUM_FORMAT_SINT
;
4174 num_format
= V_008F14_IMG_NUM_FORMAT_SSCALED
;
4176 case UTIL_FORMAT_TYPE_UNSIGNED
:
4177 if (desc
->channel
[first_non_void
].normalized
)
4178 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
4179 else if (desc
->channel
[first_non_void
].pure_integer
)
4180 num_format
= V_008F14_IMG_NUM_FORMAT_UINT
;
4182 num_format
= V_008F14_IMG_NUM_FORMAT_USCALED
;
4187 data_format
= si_translate_texformat(&screen
->b
, pipe_format
, desc
, first_non_void
);
4188 if (data_format
== ~0) {
4192 /* S8 with Z32 HTILE needs a special format. */
4193 if (screen
->info
.chip_class
== GFX9
&&
4194 pipe_format
== PIPE_FORMAT_S8_UINT
&&
4195 tex
->tc_compatible_htile
)
4196 data_format
= V_008F14_IMG_DATA_FORMAT_S8_32
;
4199 (res
->target
== PIPE_TEXTURE_CUBE
||
4200 res
->target
== PIPE_TEXTURE_CUBE_ARRAY
||
4201 (screen
->info
.chip_class
<= GFX8
&&
4202 res
->target
== PIPE_TEXTURE_3D
))) {
4203 /* For the purpose of shader images, treat cube maps and 3D
4204 * textures as 2D arrays. For 3D textures, the address
4205 * calculations for mipmaps are different, so we rely on the
4206 * caller to effectively disable mipmaps.
4208 type
= V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
4210 assert(res
->target
!= PIPE_TEXTURE_3D
|| (first_level
== 0 && last_level
== 0));
4212 type
= si_tex_dim(screen
, tex
, target
, num_samples
);
4215 if (type
== V_008F1C_SQ_RSRC_IMG_1D_ARRAY
) {
4217 depth
= res
->array_size
;
4218 } else if (type
== V_008F1C_SQ_RSRC_IMG_2D_ARRAY
||
4219 type
== V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
) {
4220 if (sampler
|| res
->target
!= PIPE_TEXTURE_3D
)
4221 depth
= res
->array_size
;
4222 } else if (type
== V_008F1C_SQ_RSRC_IMG_CUBE
)
4223 depth
= res
->array_size
/ 6;
4226 state
[1] = (S_008F14_DATA_FORMAT(data_format
) |
4227 S_008F14_NUM_FORMAT(num_format
));
4228 state
[2] = (S_008F18_WIDTH(width
- 1) |
4229 S_008F18_HEIGHT(height
- 1) |
4230 S_008F18_PERF_MOD(4));
4231 state
[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle
[0])) |
4232 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle
[1])) |
4233 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle
[2])) |
4234 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle
[3])) |
4235 S_008F1C_BASE_LEVEL(num_samples
> 1 ? 0 : first_level
) |
4236 S_008F1C_LAST_LEVEL(num_samples
> 1 ?
4237 util_logbase2(num_samples
) :
4239 S_008F1C_TYPE(type
));
4241 state
[5] = S_008F24_BASE_ARRAY(first_layer
);
4245 if (screen
->info
.chip_class
== GFX9
) {
4246 unsigned bc_swizzle
= gfx9_border_color_swizzle(desc
->swizzle
);
4248 /* Depth is the the last accessible layer on Gfx9.
4249 * The hw doesn't need to know the total number of layers.
4251 if (type
== V_008F1C_SQ_RSRC_IMG_3D
)
4252 state
[4] |= S_008F20_DEPTH(depth
- 1);
4254 state
[4] |= S_008F20_DEPTH(last_layer
);
4256 state
[4] |= S_008F20_BC_SWIZZLE(bc_swizzle
);
4257 state
[5] |= S_008F24_MAX_MIP(num_samples
> 1 ?
4258 util_logbase2(num_samples
) :
4259 tex
->buffer
.b
.b
.last_level
);
4261 state
[3] |= S_008F1C_POW2_PAD(res
->last_level
> 0);
4262 state
[4] |= S_008F20_DEPTH(depth
- 1);
4263 state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
4266 if (tex
->dcc_offset
) {
4267 state
[6] = S_008F28_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(screen
, pipe_format
));
4269 /* The last dword is unused by hw. The shader uses it to clear
4270 * bits in the first dword of sampler state.
4272 if (screen
->info
.chip_class
<= GFX7
&& res
->nr_samples
<= 1) {
4273 if (first_level
== last_level
)
4274 state
[7] = C_008F30_MAX_ANISO_RATIO
;
4276 state
[7] = 0xffffffff;
4280 /* Initialize the sampler view for FMASK. */
4281 if (tex
->fmask_offset
) {
4282 uint32_t data_format
, num_format
;
4284 va
= tex
->buffer
.gpu_address
+ tex
->fmask_offset
;
4286 #define FMASK(s,f) (((unsigned)(MAX2(1, s)) * 16) + (MAX2(1, f)))
4287 if (screen
->info
.chip_class
== GFX9
) {
4288 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK
;
4289 switch (FMASK(res
->nr_samples
, res
->nr_storage_samples
)) {
4291 num_format
= V_008F14_IMG_FMASK_8_2_1
;
4294 num_format
= V_008F14_IMG_FMASK_8_2_2
;
4297 num_format
= V_008F14_IMG_FMASK_8_4_1
;
4300 num_format
= V_008F14_IMG_FMASK_8_4_2
;
4303 num_format
= V_008F14_IMG_FMASK_8_4_4
;
4306 num_format
= V_008F14_IMG_FMASK_8_8_1
;
4309 num_format
= V_008F14_IMG_FMASK_16_8_2
;
4312 num_format
= V_008F14_IMG_FMASK_32_8_4
;
4315 num_format
= V_008F14_IMG_FMASK_32_8_8
;
4318 num_format
= V_008F14_IMG_FMASK_16_16_1
;
4321 num_format
= V_008F14_IMG_FMASK_32_16_2
;
4324 num_format
= V_008F14_IMG_FMASK_64_16_4
;
4327 num_format
= V_008F14_IMG_FMASK_64_16_8
;
4330 unreachable("invalid nr_samples");
4333 switch (FMASK(res
->nr_samples
, res
->nr_storage_samples
)) {
4335 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F1
;
4338 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2
;
4341 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F1
;
4344 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F2
;
4347 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4
;
4350 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S8_F1
;
4353 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK16_S8_F2
;
4356 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F4
;
4359 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8
;
4362 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK16_S16_F1
;
4365 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S16_F2
;
4368 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F4
;
4371 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F8
;
4374 unreachable("invalid nr_samples");
4376 num_format
= V_008F14_IMG_NUM_FORMAT_UINT
;
4380 fmask_state
[0] = (va
>> 8) | tex
->surface
.fmask_tile_swizzle
;
4381 fmask_state
[1] = S_008F14_BASE_ADDRESS_HI(va
>> 40) |
4382 S_008F14_DATA_FORMAT(data_format
) |
4383 S_008F14_NUM_FORMAT(num_format
);
4384 fmask_state
[2] = S_008F18_WIDTH(width
- 1) |
4385 S_008F18_HEIGHT(height
- 1);
4386 fmask_state
[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X
) |
4387 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X
) |
4388 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X
) |
4389 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X
) |
4390 S_008F1C_TYPE(si_tex_dim(screen
, tex
, target
, 0));
4392 fmask_state
[5] = S_008F24_BASE_ARRAY(first_layer
);
4396 if (screen
->info
.chip_class
== GFX9
) {
4397 fmask_state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
);
4398 fmask_state
[4] |= S_008F20_DEPTH(last_layer
) |
4399 S_008F20_PITCH(tex
->surface
.u
.gfx9
.fmask
.epitch
);
4400 fmask_state
[5] |= S_008F24_META_PIPE_ALIGNED(tex
->surface
.u
.gfx9
.cmask
.pipe_aligned
) |
4401 S_008F24_META_RB_ALIGNED(tex
->surface
.u
.gfx9
.cmask
.rb_aligned
);
4403 fmask_state
[3] |= S_008F1C_TILING_INDEX(tex
->surface
.u
.legacy
.fmask
.tiling_index
);
4404 fmask_state
[4] |= S_008F20_DEPTH(depth
- 1) |
4405 S_008F20_PITCH(tex
->surface
.u
.legacy
.fmask
.pitch_in_pixels
- 1);
4406 fmask_state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
4412 * Create a sampler view.
4414 * @param ctx context
4415 * @param texture texture
4416 * @param state sampler view template
4417 * @param width0 width0 override (for compressed textures as int)
4418 * @param height0 height0 override (for compressed textures as int)
4419 * @param force_level set the base address to the level (for compressed textures)
4421 struct pipe_sampler_view
*
4422 si_create_sampler_view_custom(struct pipe_context
*ctx
,
4423 struct pipe_resource
*texture
,
4424 const struct pipe_sampler_view
*state
,
4425 unsigned width0
, unsigned height0
,
4426 unsigned force_level
)
4428 struct si_context
*sctx
= (struct si_context
*)ctx
;
4429 struct si_sampler_view
*view
= CALLOC_STRUCT(si_sampler_view
);
4430 struct si_texture
*tex
= (struct si_texture
*)texture
;
4431 unsigned base_level
, first_level
, last_level
;
4432 unsigned char state_swizzle
[4];
4433 unsigned height
, depth
, width
;
4434 unsigned last_layer
= state
->u
.tex
.last_layer
;
4435 enum pipe_format pipe_format
;
4436 const struct legacy_surf_level
*surflevel
;
4441 /* initialize base object */
4442 view
->base
= *state
;
4443 view
->base
.texture
= NULL
;
4444 view
->base
.reference
.count
= 1;
4445 view
->base
.context
= ctx
;
4448 pipe_resource_reference(&view
->base
.texture
, texture
);
4450 if (state
->format
== PIPE_FORMAT_X24S8_UINT
||
4451 state
->format
== PIPE_FORMAT_S8X24_UINT
||
4452 state
->format
== PIPE_FORMAT_X32_S8X24_UINT
||
4453 state
->format
== PIPE_FORMAT_S8_UINT
)
4454 view
->is_stencil_sampler
= true;
4456 /* Buffer resource. */
4457 if (texture
->target
== PIPE_BUFFER
) {
4458 si_make_buffer_descriptor(sctx
->screen
,
4459 si_resource(texture
),
4461 state
->u
.buf
.offset
,
4467 state_swizzle
[0] = state
->swizzle_r
;
4468 state_swizzle
[1] = state
->swizzle_g
;
4469 state_swizzle
[2] = state
->swizzle_b
;
4470 state_swizzle
[3] = state
->swizzle_a
;
4473 first_level
= state
->u
.tex
.first_level
;
4474 last_level
= state
->u
.tex
.last_level
;
4477 depth
= texture
->depth0
;
4479 if (sctx
->chip_class
<= GFX8
&& force_level
) {
4480 assert(force_level
== first_level
&&
4481 force_level
== last_level
);
4482 base_level
= force_level
;
4485 width
= u_minify(width
, force_level
);
4486 height
= u_minify(height
, force_level
);
4487 depth
= u_minify(depth
, force_level
);
4490 /* This is not needed if state trackers set last_layer correctly. */
4491 if (state
->target
== PIPE_TEXTURE_1D
||
4492 state
->target
== PIPE_TEXTURE_2D
||
4493 state
->target
== PIPE_TEXTURE_RECT
||
4494 state
->target
== PIPE_TEXTURE_CUBE
)
4495 last_layer
= state
->u
.tex
.first_layer
;
4497 /* Texturing with separate depth and stencil. */
4498 pipe_format
= state
->format
;
4500 /* Depth/stencil texturing sometimes needs separate texture. */
4501 if (tex
->is_depth
&& !si_can_sample_zs(tex
, view
->is_stencil_sampler
)) {
4502 if (!tex
->flushed_depth_texture
&&
4503 !si_init_flushed_depth_texture(ctx
, texture
)) {
4504 pipe_resource_reference(&view
->base
.texture
, NULL
);
4509 assert(tex
->flushed_depth_texture
);
4511 /* Override format for the case where the flushed texture
4512 * contains only Z or only S.
4514 if (tex
->flushed_depth_texture
->buffer
.b
.b
.format
!= tex
->buffer
.b
.b
.format
)
4515 pipe_format
= tex
->flushed_depth_texture
->buffer
.b
.b
.format
;
4517 tex
= tex
->flushed_depth_texture
;
4520 surflevel
= tex
->surface
.u
.legacy
.level
;
4522 if (tex
->db_compatible
) {
4523 if (!view
->is_stencil_sampler
)
4524 pipe_format
= tex
->db_render_format
;
4526 switch (pipe_format
) {
4527 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
4528 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
4530 case PIPE_FORMAT_X8Z24_UNORM
:
4531 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
4532 /* Z24 is always stored like this for DB
4535 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
4537 case PIPE_FORMAT_X24S8_UINT
:
4538 case PIPE_FORMAT_S8X24_UINT
:
4539 case PIPE_FORMAT_X32_S8X24_UINT
:
4540 pipe_format
= PIPE_FORMAT_S8_UINT
;
4541 surflevel
= tex
->surface
.u
.legacy
.stencil_level
;
4547 view
->dcc_incompatible
=
4548 vi_dcc_formats_are_incompatible(texture
,
4549 state
->u
.tex
.first_level
,
4552 sctx
->screen
->make_texture_descriptor(sctx
->screen
, tex
, true,
4553 state
->target
, pipe_format
, state_swizzle
,
4554 first_level
, last_level
,
4555 state
->u
.tex
.first_layer
, last_layer
,
4556 width
, height
, depth
,
4557 view
->state
, view
->fmask_state
);
4559 const struct util_format_description
*desc
= util_format_description(pipe_format
);
4560 view
->is_integer
= false;
4562 for (unsigned i
= 0; i
< desc
->nr_channels
; ++i
) {
4563 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_VOID
)
4566 /* Whether the number format is {U,S}{SCALED,INT} */
4568 (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
||
4569 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) &&
4570 (desc
->channel
[i
].pure_integer
|| !desc
->channel
[i
].normalized
);
4574 view
->base_level_info
= &surflevel
[base_level
];
4575 view
->base_level
= base_level
;
4576 view
->block_width
= util_format_get_blockwidth(pipe_format
);
4580 static struct pipe_sampler_view
*
4581 si_create_sampler_view(struct pipe_context
*ctx
,
4582 struct pipe_resource
*texture
,
4583 const struct pipe_sampler_view
*state
)
4585 return si_create_sampler_view_custom(ctx
, texture
, state
,
4586 texture
? texture
->width0
: 0,
4587 texture
? texture
->height0
: 0, 0);
4590 static void si_sampler_view_destroy(struct pipe_context
*ctx
,
4591 struct pipe_sampler_view
*state
)
4593 struct si_sampler_view
*view
= (struct si_sampler_view
*)state
;
4595 pipe_resource_reference(&state
->texture
, NULL
);
4599 static bool wrap_mode_uses_border_color(unsigned wrap
, bool linear_filter
)
4601 return wrap
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
||
4602 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
||
4604 (wrap
== PIPE_TEX_WRAP_CLAMP
||
4605 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP
));
4608 static uint32_t si_translate_border_color(struct si_context
*sctx
,
4609 const struct pipe_sampler_state
*state
,
4610 const union pipe_color_union
*color
,
4613 bool linear_filter
= state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
||
4614 state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
;
4616 if (!wrap_mode_uses_border_color(state
->wrap_s
, linear_filter
) &&
4617 !wrap_mode_uses_border_color(state
->wrap_t
, linear_filter
) &&
4618 !wrap_mode_uses_border_color(state
->wrap_r
, linear_filter
))
4619 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
);
4621 #define simple_border_types(elt) \
4623 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4624 color->elt[2] == 0 && color->elt[3] == 0) \
4625 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK); \
4626 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4627 color->elt[2] == 0 && color->elt[3] == 1) \
4628 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK); \
4629 if (color->elt[0] == 1 && color->elt[1] == 1 && \
4630 color->elt[2] == 1 && color->elt[3] == 1) \
4631 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE); \
4635 simple_border_types(ui
);
4637 simple_border_types(f
);
4639 #undef simple_border_types
4643 /* Check if the border has been uploaded already. */
4644 for (i
= 0; i
< sctx
->border_color_count
; i
++)
4645 if (memcmp(&sctx
->border_color_table
[i
], color
,
4646 sizeof(*color
)) == 0)
4649 if (i
>= SI_MAX_BORDER_COLORS
) {
4650 /* Getting 4096 unique border colors is very unlikely. */
4651 fprintf(stderr
, "radeonsi: The border color table is full. "
4652 "Any new border colors will be just black. "
4653 "Please file a bug.\n");
4654 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
);
4657 if (i
== sctx
->border_color_count
) {
4658 /* Upload a new border color. */
4659 memcpy(&sctx
->border_color_table
[i
], color
,
4661 util_memcpy_cpu_to_le32(&sctx
->border_color_map
[i
],
4662 color
, sizeof(*color
));
4663 sctx
->border_color_count
++;
4666 return S_008F3C_BORDER_COLOR_PTR(i
) |
4667 S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER
);
4670 static inline int S_FIXED(float value
, unsigned frac_bits
)
4672 return value
* (1 << frac_bits
);
4675 static inline unsigned si_tex_filter(unsigned filter
, unsigned max_aniso
)
4677 if (filter
== PIPE_TEX_FILTER_LINEAR
)
4678 return max_aniso
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
4679 : V_008F38_SQ_TEX_XY_FILTER_BILINEAR
;
4681 return max_aniso
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
4682 : V_008F38_SQ_TEX_XY_FILTER_POINT
;
4685 static inline unsigned si_tex_aniso_filter(unsigned filter
)
4698 static void *si_create_sampler_state(struct pipe_context
*ctx
,
4699 const struct pipe_sampler_state
*state
)
4701 struct si_context
*sctx
= (struct si_context
*)ctx
;
4702 struct si_screen
*sscreen
= sctx
->screen
;
4703 struct si_sampler_state
*rstate
= CALLOC_STRUCT(si_sampler_state
);
4704 unsigned max_aniso
= sscreen
->force_aniso
>= 0 ? sscreen
->force_aniso
4705 : state
->max_anisotropy
;
4706 unsigned max_aniso_ratio
= si_tex_aniso_filter(max_aniso
);
4707 union pipe_color_union clamped_border_color
;
4714 rstate
->magic
= SI_SAMPLER_STATE_MAGIC
;
4716 rstate
->val
[0] = (S_008F30_CLAMP_X(si_tex_wrap(state
->wrap_s
)) |
4717 S_008F30_CLAMP_Y(si_tex_wrap(state
->wrap_t
)) |
4718 S_008F30_CLAMP_Z(si_tex_wrap(state
->wrap_r
)) |
4719 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio
) |
4720 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state
->compare_func
)) |
4721 S_008F30_FORCE_UNNORMALIZED(!state
->normalized_coords
) |
4722 S_008F30_ANISO_THRESHOLD(max_aniso_ratio
>> 1) |
4723 S_008F30_ANISO_BIAS(max_aniso_ratio
) |
4724 S_008F30_DISABLE_CUBE_WRAP(!state
->seamless_cube_map
) |
4725 S_008F30_COMPAT_MODE(sctx
->chip_class
== GFX8
|| sctx
->chip_class
== GFX9
));
4726 rstate
->val
[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 8)) |
4727 S_008F34_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 8)) |
4728 S_008F34_PERF_MIP(max_aniso_ratio
? max_aniso_ratio
+ 6 : 0));
4729 rstate
->val
[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 8)) |
4730 S_008F38_XY_MAG_FILTER(si_tex_filter(state
->mag_img_filter
, max_aniso
)) |
4731 S_008F38_XY_MIN_FILTER(si_tex_filter(state
->min_img_filter
, max_aniso
)) |
4732 S_008F38_MIP_FILTER(si_tex_mipfilter(state
->min_mip_filter
)) |
4733 S_008F38_MIP_POINT_PRECLAMP(0));
4734 rstate
->val
[3] = si_translate_border_color(sctx
, state
, &state
->border_color
, false);
4736 if (sscreen
->info
.chip_class
>= GFX10
) {
4737 rstate
->val
[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
4739 rstate
->val
[2] |= S_008F38_DISABLE_LSB_CEIL(sctx
->chip_class
<= GFX8
) |
4740 S_008F38_FILTER_PREC_FIX(1) |
4741 S_008F38_ANISO_OVERRIDE_GFX6(sctx
->chip_class
>= GFX8
);
4744 /* Create sampler resource for integer textures. */
4745 memcpy(rstate
->integer_val
, rstate
->val
, sizeof(rstate
->val
));
4746 rstate
->integer_val
[3] = si_translate_border_color(sctx
, state
, &state
->border_color
, true);
4748 /* Create sampler resource for upgraded depth textures. */
4749 memcpy(rstate
->upgraded_depth_val
, rstate
->val
, sizeof(rstate
->val
));
4751 for (unsigned i
= 0; i
< 4; ++i
) {
4752 /* Use channel 0 on purpose, so that we can use OPAQUE_WHITE
4753 * when the border color is 1.0. */
4754 clamped_border_color
.f
[i
] = CLAMP(state
->border_color
.f
[0], 0, 1);
4757 if (memcmp(&state
->border_color
, &clamped_border_color
, sizeof(clamped_border_color
)) == 0) {
4758 if (sscreen
->info
.chip_class
<= GFX9
)
4759 rstate
->upgraded_depth_val
[3] |= S_008F3C_UPGRADED_DEPTH(1);
4761 rstate
->upgraded_depth_val
[3] =
4762 si_translate_border_color(sctx
, state
, &clamped_border_color
, false);
4768 static void si_set_sample_mask(struct pipe_context
*ctx
, unsigned sample_mask
)
4770 struct si_context
*sctx
= (struct si_context
*)ctx
;
4772 if (sctx
->sample_mask
== (uint16_t)sample_mask
)
4775 sctx
->sample_mask
= sample_mask
;
4776 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.sample_mask
);
4779 static void si_emit_sample_mask(struct si_context
*sctx
)
4781 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
4782 unsigned mask
= sctx
->sample_mask
;
4784 /* Needed for line and polygon smoothing as well as for the Polaris
4785 * small primitive filter. We expect the state tracker to take care of
4788 assert(mask
== 0xffff || sctx
->framebuffer
.nr_samples
> 1 ||
4789 (mask
& 1 && sctx
->blitter
->running
));
4791 radeon_set_context_reg_seq(cs
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
4792 radeon_emit(cs
, mask
| (mask
<< 16));
4793 radeon_emit(cs
, mask
| (mask
<< 16));
4796 static void si_delete_sampler_state(struct pipe_context
*ctx
, void *state
)
4799 struct si_sampler_state
*s
= state
;
4801 assert(s
->magic
== SI_SAMPLER_STATE_MAGIC
);
4808 * Vertex elements & buffers
4811 struct si_fast_udiv_info32
4812 si_compute_fast_udiv_info32(uint32_t D
, unsigned num_bits
)
4814 struct util_fast_udiv_info info
=
4815 util_compute_fast_udiv_info(D
, num_bits
, 32);
4817 struct si_fast_udiv_info32 result
= {
4826 static void *si_create_vertex_elements(struct pipe_context
*ctx
,
4828 const struct pipe_vertex_element
*elements
)
4830 struct si_screen
*sscreen
= (struct si_screen
*)ctx
->screen
;
4831 struct si_vertex_elements
*v
= CALLOC_STRUCT(si_vertex_elements
);
4832 bool used
[SI_NUM_VERTEX_BUFFERS
] = {};
4833 struct si_fast_udiv_info32 divisor_factors
[SI_MAX_ATTRIBS
] = {};
4834 STATIC_ASSERT(sizeof(struct si_fast_udiv_info32
) == 16);
4835 STATIC_ASSERT(sizeof(divisor_factors
[0].multiplier
) == 4);
4836 STATIC_ASSERT(sizeof(divisor_factors
[0].pre_shift
) == 4);
4837 STATIC_ASSERT(sizeof(divisor_factors
[0].post_shift
) == 4);
4838 STATIC_ASSERT(sizeof(divisor_factors
[0].increment
) == 4);
4841 assert(count
<= SI_MAX_ATTRIBS
);
4846 v
->desc_list_byte_size
= align(count
* 16, SI_CPDMA_ALIGNMENT
);
4848 for (i
= 0; i
< count
; ++i
) {
4849 const struct util_format_description
*desc
;
4850 const struct util_format_channel_description
*channel
;
4852 unsigned vbo_index
= elements
[i
].vertex_buffer_index
;
4854 if (vbo_index
>= SI_NUM_VERTEX_BUFFERS
) {
4859 unsigned instance_divisor
= elements
[i
].instance_divisor
;
4860 if (instance_divisor
) {
4861 v
->uses_instance_divisors
= true;
4863 if (instance_divisor
== 1) {
4864 v
->instance_divisor_is_one
|= 1u << i
;
4866 v
->instance_divisor_is_fetched
|= 1u << i
;
4867 divisor_factors
[i
] =
4868 si_compute_fast_udiv_info32(instance_divisor
, 32);
4872 if (!used
[vbo_index
]) {
4873 v
->first_vb_use_mask
|= 1 << i
;
4874 used
[vbo_index
] = true;
4877 desc
= util_format_description(elements
[i
].src_format
);
4878 first_non_void
= util_format_get_first_non_void_channel(elements
[i
].src_format
);
4879 channel
= first_non_void
>= 0 ? &desc
->channel
[first_non_void
] : NULL
;
4881 v
->format_size
[i
] = desc
->block
.bits
/ 8;
4882 v
->src_offset
[i
] = elements
[i
].src_offset
;
4883 v
->vertex_buffer_index
[i
] = vbo_index
;
4885 bool always_fix
= false;
4886 union si_vs_fix_fetch fix_fetch
;
4887 unsigned log_hw_load_size
; /* the load element size as seen by the hardware */
4890 log_hw_load_size
= MIN2(2, util_logbase2(desc
->block
.bits
) - 3);
4893 switch (channel
->type
) {
4894 case UTIL_FORMAT_TYPE_FLOAT
: fix_fetch
.u
.format
= AC_FETCH_FORMAT_FLOAT
; break;
4895 case UTIL_FORMAT_TYPE_FIXED
: fix_fetch
.u
.format
= AC_FETCH_FORMAT_FIXED
; break;
4896 case UTIL_FORMAT_TYPE_SIGNED
: {
4897 if (channel
->pure_integer
)
4898 fix_fetch
.u
.format
= AC_FETCH_FORMAT_SINT
;
4899 else if (channel
->normalized
)
4900 fix_fetch
.u
.format
= AC_FETCH_FORMAT_SNORM
;
4902 fix_fetch
.u
.format
= AC_FETCH_FORMAT_SSCALED
;
4905 case UTIL_FORMAT_TYPE_UNSIGNED
: {
4906 if (channel
->pure_integer
)
4907 fix_fetch
.u
.format
= AC_FETCH_FORMAT_UINT
;
4908 else if (channel
->normalized
)
4909 fix_fetch
.u
.format
= AC_FETCH_FORMAT_UNORM
;
4911 fix_fetch
.u
.format
= AC_FETCH_FORMAT_USCALED
;
4914 default: unreachable("bad format type");
4917 switch (elements
[i
].src_format
) {
4918 case PIPE_FORMAT_R11G11B10_FLOAT
: fix_fetch
.u
.format
= AC_FETCH_FORMAT_FLOAT
; break;
4919 default: unreachable("bad other format");
4923 if (desc
->channel
[0].size
== 10) {
4924 fix_fetch
.u
.log_size
= 3; /* special encoding for 2_10_10_10 */
4925 log_hw_load_size
= 2;
4927 /* The hardware always treats the 2-bit alpha channel as
4928 * unsigned, so a shader workaround is needed. The affected
4929 * chips are GFX8 and older except Stoney (GFX8.1).
4931 always_fix
= sscreen
->info
.chip_class
<= GFX8
&&
4932 sscreen
->info
.family
!= CHIP_STONEY
&&
4933 channel
->type
== UTIL_FORMAT_TYPE_SIGNED
;
4934 } else if (elements
[i
].src_format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
4935 fix_fetch
.u
.log_size
= 3; /* special encoding */
4936 fix_fetch
.u
.format
= AC_FETCH_FORMAT_FIXED
;
4937 log_hw_load_size
= 2;
4939 fix_fetch
.u
.log_size
= util_logbase2(channel
->size
) - 3;
4940 fix_fetch
.u
.num_channels_m1
= desc
->nr_channels
- 1;
4943 * - doubles (multiple loads + truncate to float)
4944 * - 32-bit requiring a conversion
4947 (fix_fetch
.u
.log_size
== 3) ||
4948 (fix_fetch
.u
.log_size
== 2 &&
4949 fix_fetch
.u
.format
!= AC_FETCH_FORMAT_FLOAT
&&
4950 fix_fetch
.u
.format
!= AC_FETCH_FORMAT_UINT
&&
4951 fix_fetch
.u
.format
!= AC_FETCH_FORMAT_SINT
);
4953 /* Also fixup 8_8_8 and 16_16_16. */
4954 if (desc
->nr_channels
== 3 && fix_fetch
.u
.log_size
<= 1) {
4956 log_hw_load_size
= fix_fetch
.u
.log_size
;
4960 if (desc
->swizzle
[0] != PIPE_SWIZZLE_X
) {
4961 assert(desc
->swizzle
[0] == PIPE_SWIZZLE_Z
&&
4962 (desc
->swizzle
[2] == PIPE_SWIZZLE_X
|| desc
->swizzle
[2] == PIPE_SWIZZLE_0
));
4963 fix_fetch
.u
.reverse
= 1;
4966 /* Force the workaround for unaligned access here already if the
4967 * offset relative to the vertex buffer base is unaligned.
4969 * There is a theoretical case in which this is too conservative:
4970 * if the vertex buffer's offset is also unaligned in just the
4971 * right way, we end up with an aligned address after all.
4972 * However, this case should be extremely rare in practice (it
4973 * won't happen in well-behaved applications), and taking it
4974 * into account would complicate the fast path (where everything
4975 * is nicely aligned).
4977 bool check_alignment
=
4978 log_hw_load_size
>= 1 &&
4979 (sscreen
->info
.chip_class
== GFX6
|| sscreen
->info
.chip_class
== GFX10
);
4980 bool opencode
= sscreen
->options
.vs_fetch_always_opencode
;
4982 if (check_alignment
&&
4983 (elements
[i
].src_offset
& ((1 << log_hw_load_size
) - 1)) != 0)
4986 if (always_fix
|| check_alignment
|| opencode
)
4987 v
->fix_fetch
[i
] = fix_fetch
.bits
;
4990 v
->fix_fetch_opencode
|= 1 << i
;
4991 if (opencode
|| always_fix
)
4992 v
->fix_fetch_always
|= 1 << i
;
4994 if (check_alignment
&& !opencode
) {
4995 assert(log_hw_load_size
== 1 || log_hw_load_size
== 2);
4997 v
->fix_fetch_unaligned
|= 1 << i
;
4998 v
->hw_load_is_dword
|= (log_hw_load_size
- 1) << i
;
4999 v
->vb_alignment_check_mask
|= 1 << vbo_index
;
5002 v
->rsrc_word3
[i
] = S_008F0C_DST_SEL_X(si_map_swizzle(desc
->swizzle
[0])) |
5003 S_008F0C_DST_SEL_Y(si_map_swizzle(desc
->swizzle
[1])) |
5004 S_008F0C_DST_SEL_Z(si_map_swizzle(desc
->swizzle
[2])) |
5005 S_008F0C_DST_SEL_W(si_map_swizzle(desc
->swizzle
[3]));
5007 if (sscreen
->info
.chip_class
>= GFX10
) {
5008 const struct gfx10_format
*fmt
=
5009 &gfx10_format_table
[elements
[i
].src_format
];
5010 assert(fmt
->img_format
!= 0 && fmt
->img_format
< 128);
5011 v
->rsrc_word3
[i
] |= S_008F0C_FORMAT(fmt
->img_format
) |
5012 S_008F0C_RESOURCE_LEVEL(1);
5014 unsigned data_format
, num_format
;
5015 data_format
= si_translate_buffer_dataformat(ctx
->screen
, desc
, first_non_void
);
5016 num_format
= si_translate_buffer_numformat(ctx
->screen
, desc
, first_non_void
);
5017 v
->rsrc_word3
[i
] |= S_008F0C_NUM_FORMAT(num_format
) |
5018 S_008F0C_DATA_FORMAT(data_format
);
5022 if (v
->instance_divisor_is_fetched
) {
5023 unsigned num_divisors
= util_last_bit(v
->instance_divisor_is_fetched
);
5025 v
->instance_divisor_factor_buffer
=
5026 (struct si_resource
*)
5027 pipe_buffer_create(&sscreen
->b
, 0, PIPE_USAGE_DEFAULT
,
5028 num_divisors
* sizeof(divisor_factors
[0]));
5029 if (!v
->instance_divisor_factor_buffer
) {
5033 void *map
= sscreen
->ws
->buffer_map(v
->instance_divisor_factor_buffer
->buf
,
5034 NULL
, PIPE_TRANSFER_WRITE
);
5035 memcpy(map
, divisor_factors
, num_divisors
* sizeof(divisor_factors
[0]));
5040 static void si_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
5042 struct si_context
*sctx
= (struct si_context
*)ctx
;
5043 struct si_vertex_elements
*old
= sctx
->vertex_elements
;
5044 struct si_vertex_elements
*v
= (struct si_vertex_elements
*)state
;
5046 sctx
->vertex_elements
= v
;
5047 sctx
->vertex_buffers_dirty
= true;
5051 old
->count
!= v
->count
||
5052 old
->uses_instance_divisors
!= v
->uses_instance_divisors
||
5053 /* we don't check which divisors changed */
5054 v
->uses_instance_divisors
||
5055 (old
->vb_alignment_check_mask
^ v
->vb_alignment_check_mask
) & sctx
->vertex_buffer_unaligned
||
5056 ((v
->vb_alignment_check_mask
& sctx
->vertex_buffer_unaligned
) &&
5057 memcmp(old
->vertex_buffer_index
, v
->vertex_buffer_index
,
5058 sizeof(v
->vertex_buffer_index
[0]) * v
->count
)) ||
5059 /* fix_fetch_{always,opencode,unaligned} and hw_load_is_dword are
5060 * functions of fix_fetch and the src_offset alignment.
5061 * If they change and fix_fetch doesn't, it must be due to different
5062 * src_offset alignment, which is reflected in fix_fetch_opencode. */
5063 old
->fix_fetch_opencode
!= v
->fix_fetch_opencode
||
5064 memcmp(old
->fix_fetch
, v
->fix_fetch
, sizeof(v
->fix_fetch
[0]) * v
->count
)))
5065 sctx
->do_update_shaders
= true;
5067 if (v
&& v
->instance_divisor_is_fetched
) {
5068 struct pipe_constant_buffer cb
;
5070 cb
.buffer
= &v
->instance_divisor_factor_buffer
->b
.b
;
5071 cb
.user_buffer
= NULL
;
5072 cb
.buffer_offset
= 0;
5073 cb
.buffer_size
= 0xffffffff;
5074 si_set_rw_buffer(sctx
, SI_VS_CONST_INSTANCE_DIVISORS
, &cb
);
5078 static void si_delete_vertex_element(struct pipe_context
*ctx
, void *state
)
5080 struct si_context
*sctx
= (struct si_context
*)ctx
;
5081 struct si_vertex_elements
*v
= (struct si_vertex_elements
*)state
;
5083 if (sctx
->vertex_elements
== state
)
5084 sctx
->vertex_elements
= NULL
;
5085 si_resource_reference(&v
->instance_divisor_factor_buffer
, NULL
);
5089 static void si_set_vertex_buffers(struct pipe_context
*ctx
,
5090 unsigned start_slot
, unsigned count
,
5091 const struct pipe_vertex_buffer
*buffers
)
5093 struct si_context
*sctx
= (struct si_context
*)ctx
;
5094 struct pipe_vertex_buffer
*dst
= sctx
->vertex_buffer
+ start_slot
;
5095 uint32_t orig_unaligned
= sctx
->vertex_buffer_unaligned
;
5096 uint32_t unaligned
= orig_unaligned
;
5099 assert(start_slot
+ count
<= ARRAY_SIZE(sctx
->vertex_buffer
));
5102 for (i
= 0; i
< count
; i
++) {
5103 const struct pipe_vertex_buffer
*src
= buffers
+ i
;
5104 struct pipe_vertex_buffer
*dsti
= dst
+ i
;
5105 struct pipe_resource
*buf
= src
->buffer
.resource
;
5107 pipe_resource_reference(&dsti
->buffer
.resource
, buf
);
5108 dsti
->buffer_offset
= src
->buffer_offset
;
5109 dsti
->stride
= src
->stride
;
5110 if (dsti
->buffer_offset
& 3 || dsti
->stride
& 3)
5111 unaligned
|= 1 << (start_slot
+ i
);
5113 unaligned
&= ~(1 << (start_slot
+ i
));
5115 si_context_add_resource_size(sctx
, buf
);
5117 si_resource(buf
)->bind_history
|= PIPE_BIND_VERTEX_BUFFER
;
5120 for (i
= 0; i
< count
; i
++) {
5121 pipe_resource_reference(&dst
[i
].buffer
.resource
, NULL
);
5123 unaligned
&= ~u_bit_consecutive(start_slot
, count
);
5125 sctx
->vertex_buffers_dirty
= true;
5126 sctx
->vertex_buffer_unaligned
= unaligned
;
5128 /* Check whether alignment may have changed in a way that requires
5129 * shader changes. This check is conservative: a vertex buffer can only
5130 * trigger a shader change if the misalignment amount changes (e.g.
5131 * from byte-aligned to short-aligned), but we only keep track of
5132 * whether buffers are at least dword-aligned, since that should always
5133 * be the case in well-behaved applications anyway.
5135 if (sctx
->vertex_elements
&&
5136 (sctx
->vertex_elements
->vb_alignment_check_mask
&
5137 (unaligned
| orig_unaligned
) & u_bit_consecutive(start_slot
, count
)))
5138 sctx
->do_update_shaders
= true;
5145 static void si_set_tess_state(struct pipe_context
*ctx
,
5146 const float default_outer_level
[4],
5147 const float default_inner_level
[2])
5149 struct si_context
*sctx
= (struct si_context
*)ctx
;
5150 struct pipe_constant_buffer cb
;
5153 memcpy(array
, default_outer_level
, sizeof(float) * 4);
5154 memcpy(array
+4, default_inner_level
, sizeof(float) * 2);
5157 cb
.user_buffer
= NULL
;
5158 cb
.buffer_size
= sizeof(array
);
5160 si_upload_const_buffer(sctx
, (struct si_resource
**)&cb
.buffer
,
5161 (void*)array
, sizeof(array
),
5164 si_set_rw_buffer(sctx
, SI_HS_CONST_DEFAULT_TESS_LEVELS
, &cb
);
5165 pipe_resource_reference(&cb
.buffer
, NULL
);
5168 static void si_texture_barrier(struct pipe_context
*ctx
, unsigned flags
)
5170 struct si_context
*sctx
= (struct si_context
*)ctx
;
5172 si_update_fb_dirtiness_after_rendering(sctx
);
5174 /* Multisample surfaces are flushed in si_decompress_textures. */
5175 if (sctx
->framebuffer
.uncompressed_cb_mask
) {
5176 si_make_CB_shader_coherent(sctx
, sctx
->framebuffer
.nr_samples
,
5177 sctx
->framebuffer
.CB_has_shader_readable_metadata
,
5178 sctx
->framebuffer
.all_DCC_pipe_aligned
);
5182 /* This only ensures coherency for shader image/buffer stores. */
5183 static void si_memory_barrier(struct pipe_context
*ctx
, unsigned flags
)
5185 struct si_context
*sctx
= (struct si_context
*)ctx
;
5187 if (!(flags
& ~PIPE_BARRIER_UPDATE
))
5190 /* Subsequent commands must wait for all shader invocations to
5192 sctx
->flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
|
5193 SI_CONTEXT_CS_PARTIAL_FLUSH
;
5195 if (flags
& PIPE_BARRIER_CONSTANT_BUFFER
)
5196 sctx
->flags
|= SI_CONTEXT_INV_SCACHE
|
5197 SI_CONTEXT_INV_VCACHE
;
5199 if (flags
& (PIPE_BARRIER_VERTEX_BUFFER
|
5200 PIPE_BARRIER_SHADER_BUFFER
|
5201 PIPE_BARRIER_TEXTURE
|
5202 PIPE_BARRIER_IMAGE
|
5203 PIPE_BARRIER_STREAMOUT_BUFFER
|
5204 PIPE_BARRIER_GLOBAL_BUFFER
)) {
5205 /* As far as I can tell, L1 contents are written back to L2
5206 * automatically at end of shader, but the contents of other
5207 * L1 caches might still be stale. */
5208 sctx
->flags
|= SI_CONTEXT_INV_VCACHE
;
5211 if (flags
& PIPE_BARRIER_INDEX_BUFFER
) {
5212 /* Indices are read through TC L2 since GFX8.
5215 if (sctx
->screen
->info
.chip_class
<= GFX7
)
5216 sctx
->flags
|= SI_CONTEXT_WB_L2
;
5219 /* MSAA color, any depth and any stencil are flushed in
5220 * si_decompress_textures when needed.
5222 if (flags
& PIPE_BARRIER_FRAMEBUFFER
&&
5223 sctx
->framebuffer
.uncompressed_cb_mask
) {
5224 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_CB
;
5226 if (sctx
->chip_class
<= GFX8
)
5227 sctx
->flags
|= SI_CONTEXT_WB_L2
;
5230 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
5231 if (sctx
->screen
->info
.chip_class
<= GFX8
&&
5232 flags
& PIPE_BARRIER_INDIRECT_BUFFER
)
5233 sctx
->flags
|= SI_CONTEXT_WB_L2
;
5236 static void *si_create_blend_custom(struct si_context
*sctx
, unsigned mode
)
5238 struct pipe_blend_state blend
;
5240 memset(&blend
, 0, sizeof(blend
));
5241 blend
.independent_blend_enable
= true;
5242 blend
.rt
[0].colormask
= 0xf;
5243 return si_create_blend_state_mode(&sctx
->b
, &blend
, mode
);
5246 static void si_init_config(struct si_context
*sctx
);
5248 void si_init_state_compute_functions(struct si_context
*sctx
)
5250 sctx
->b
.create_sampler_state
= si_create_sampler_state
;
5251 sctx
->b
.delete_sampler_state
= si_delete_sampler_state
;
5252 sctx
->b
.create_sampler_view
= si_create_sampler_view
;
5253 sctx
->b
.sampler_view_destroy
= si_sampler_view_destroy
;
5254 sctx
->b
.memory_barrier
= si_memory_barrier
;
5257 void si_init_state_functions(struct si_context
*sctx
)
5259 sctx
->atoms
.s
.framebuffer
.emit
= si_emit_framebuffer_state
;
5260 sctx
->atoms
.s
.msaa_sample_locs
.emit
= si_emit_msaa_sample_locs
;
5261 sctx
->atoms
.s
.db_render_state
.emit
= si_emit_db_render_state
;
5262 sctx
->atoms
.s
.dpbb_state
.emit
= si_emit_dpbb_state
;
5263 sctx
->atoms
.s
.msaa_config
.emit
= si_emit_msaa_config
;
5264 sctx
->atoms
.s
.sample_mask
.emit
= si_emit_sample_mask
;
5265 sctx
->atoms
.s
.cb_render_state
.emit
= si_emit_cb_render_state
;
5266 sctx
->atoms
.s
.blend_color
.emit
= si_emit_blend_color
;
5267 sctx
->atoms
.s
.clip_regs
.emit
= si_emit_clip_regs
;
5268 sctx
->atoms
.s
.clip_state
.emit
= si_emit_clip_state
;
5269 sctx
->atoms
.s
.stencil_ref
.emit
= si_emit_stencil_ref
;
5271 sctx
->b
.create_blend_state
= si_create_blend_state
;
5272 sctx
->b
.bind_blend_state
= si_bind_blend_state
;
5273 sctx
->b
.delete_blend_state
= si_delete_blend_state
;
5274 sctx
->b
.set_blend_color
= si_set_blend_color
;
5276 sctx
->b
.create_rasterizer_state
= si_create_rs_state
;
5277 sctx
->b
.bind_rasterizer_state
= si_bind_rs_state
;
5278 sctx
->b
.delete_rasterizer_state
= si_delete_rs_state
;
5280 sctx
->b
.create_depth_stencil_alpha_state
= si_create_dsa_state
;
5281 sctx
->b
.bind_depth_stencil_alpha_state
= si_bind_dsa_state
;
5282 sctx
->b
.delete_depth_stencil_alpha_state
= si_delete_dsa_state
;
5284 sctx
->custom_dsa_flush
= si_create_db_flush_dsa(sctx
);
5285 sctx
->custom_blend_resolve
= si_create_blend_custom(sctx
, V_028808_CB_RESOLVE
);
5286 sctx
->custom_blend_fmask_decompress
= si_create_blend_custom(sctx
, V_028808_CB_FMASK_DECOMPRESS
);
5287 sctx
->custom_blend_eliminate_fastclear
= si_create_blend_custom(sctx
, V_028808_CB_ELIMINATE_FAST_CLEAR
);
5288 sctx
->custom_blend_dcc_decompress
= si_create_blend_custom(sctx
, V_028808_CB_DCC_DECOMPRESS
);
5290 sctx
->b
.set_clip_state
= si_set_clip_state
;
5291 sctx
->b
.set_stencil_ref
= si_set_stencil_ref
;
5293 sctx
->b
.set_framebuffer_state
= si_set_framebuffer_state
;
5295 sctx
->b
.set_sample_mask
= si_set_sample_mask
;
5297 sctx
->b
.create_vertex_elements_state
= si_create_vertex_elements
;
5298 sctx
->b
.bind_vertex_elements_state
= si_bind_vertex_elements
;
5299 sctx
->b
.delete_vertex_elements_state
= si_delete_vertex_element
;
5300 sctx
->b
.set_vertex_buffers
= si_set_vertex_buffers
;
5302 sctx
->b
.texture_barrier
= si_texture_barrier
;
5303 sctx
->b
.set_min_samples
= si_set_min_samples
;
5304 sctx
->b
.set_tess_state
= si_set_tess_state
;
5306 sctx
->b
.set_active_query_state
= si_set_active_query_state
;
5308 si_init_config(sctx
);
5311 void si_init_screen_state_functions(struct si_screen
*sscreen
)
5313 sscreen
->b
.is_format_supported
= si_is_format_supported
;
5315 if (sscreen
->info
.chip_class
>= GFX10
) {
5316 sscreen
->make_texture_descriptor
= gfx10_make_texture_descriptor
;
5318 sscreen
->make_texture_descriptor
= si_make_texture_descriptor
;
5322 static void si_set_grbm_gfx_index(struct si_context
*sctx
,
5323 struct si_pm4_state
*pm4
, unsigned value
)
5325 unsigned reg
= sctx
->chip_class
>= GFX7
? R_030800_GRBM_GFX_INDEX
:
5326 R_00802C_GRBM_GFX_INDEX
;
5327 si_pm4_set_reg(pm4
, reg
, value
);
5330 static void si_set_grbm_gfx_index_se(struct si_context
*sctx
,
5331 struct si_pm4_state
*pm4
, unsigned se
)
5333 assert(se
== ~0 || se
< sctx
->screen
->info
.max_se
);
5334 si_set_grbm_gfx_index(sctx
, pm4
,
5335 (se
== ~0 ? S_030800_SE_BROADCAST_WRITES(1) :
5336 S_030800_SE_INDEX(se
)) |
5337 S_030800_SH_BROADCAST_WRITES(1) |
5338 S_030800_INSTANCE_BROADCAST_WRITES(1));
5342 si_write_harvested_raster_configs(struct si_context
*sctx
,
5343 struct si_pm4_state
*pm4
,
5344 unsigned raster_config
,
5345 unsigned raster_config_1
)
5347 unsigned num_se
= MAX2(sctx
->screen
->info
.max_se
, 1);
5348 unsigned raster_config_se
[4];
5351 ac_get_harvested_configs(&sctx
->screen
->info
,
5356 for (se
= 0; se
< num_se
; se
++) {
5357 si_set_grbm_gfx_index_se(sctx
, pm4
, se
);
5358 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
, raster_config_se
[se
]);
5360 si_set_grbm_gfx_index(sctx
, pm4
, ~0);
5362 if (sctx
->chip_class
>= GFX7
) {
5363 si_pm4_set_reg(pm4
, R_028354_PA_SC_RASTER_CONFIG_1
, raster_config_1
);
5367 static void si_set_raster_config(struct si_context
*sctx
, struct si_pm4_state
*pm4
)
5369 struct si_screen
*sscreen
= sctx
->screen
;
5370 unsigned num_rb
= MIN2(sscreen
->info
.num_render_backends
, 16);
5371 unsigned rb_mask
= sscreen
->info
.enabled_rb_mask
;
5372 unsigned raster_config
= sscreen
->pa_sc_raster_config
;
5373 unsigned raster_config_1
= sscreen
->pa_sc_raster_config_1
;
5375 if (!rb_mask
|| util_bitcount(rb_mask
) >= num_rb
) {
5376 /* Always use the default config when all backends are enabled
5377 * (or when we failed to determine the enabled backends).
5379 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
,
5381 if (sctx
->chip_class
>= GFX7
)
5382 si_pm4_set_reg(pm4
, R_028354_PA_SC_RASTER_CONFIG_1
,
5385 si_write_harvested_raster_configs(sctx
, pm4
, raster_config
, raster_config_1
);
5389 static void si_init_config(struct si_context
*sctx
)
5391 struct si_screen
*sscreen
= sctx
->screen
;
5392 uint64_t border_color_va
= sctx
->border_color_buffer
->gpu_address
;
5393 bool has_clear_state
= sscreen
->info
.has_clear_state
;
5394 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
5399 /* Since amdgpu version 3.6.0, CONTEXT_CONTROL is emitted by the kernel */
5400 if (!sscreen
->info
.is_amdgpu
|| sscreen
->info
.drm_minor
< 6) {
5401 si_pm4_cmd_begin(pm4
, PKT3_CONTEXT_CONTROL
);
5402 si_pm4_cmd_add(pm4
, CONTEXT_CONTROL_LOAD_ENABLE(1));
5403 si_pm4_cmd_add(pm4
, CONTEXT_CONTROL_SHADOW_ENABLE(1));
5404 si_pm4_cmd_end(pm4
, false);
5407 if (has_clear_state
) {
5408 si_pm4_cmd_begin(pm4
, PKT3_CLEAR_STATE
);
5409 si_pm4_cmd_add(pm4
, 0);
5410 si_pm4_cmd_end(pm4
, false);
5413 if (sctx
->chip_class
<= GFX8
)
5414 si_set_raster_config(sctx
, pm4
);
5416 si_pm4_set_reg(pm4
, R_028A18_VGT_HOS_MAX_TESS_LEVEL
, fui(64));
5417 if (!has_clear_state
)
5418 si_pm4_set_reg(pm4
, R_028A1C_VGT_HOS_MIN_TESS_LEVEL
, fui(0));
5420 /* FIXME calculate these values somehow ??? */
5421 if (sctx
->chip_class
<= GFX8
) {
5422 si_pm4_set_reg(pm4
, R_028A54_VGT_GS_PER_ES
, SI_GS_PER_ES
);
5423 si_pm4_set_reg(pm4
, R_028A58_VGT_ES_PER_GS
, 0x40);
5426 if (!has_clear_state
) {
5427 si_pm4_set_reg(pm4
, R_028A5C_VGT_GS_PER_VS
, 0x2);
5428 si_pm4_set_reg(pm4
, R_028A8C_VGT_PRIMITIVEID_RESET
, 0x0);
5429 si_pm4_set_reg(pm4
, R_028B98_VGT_STRMOUT_BUFFER_CONFIG
, 0x0);
5432 si_pm4_set_reg(pm4
, R_028AA0_VGT_INSTANCE_STEP_RATE_0
, 1);
5433 if (!has_clear_state
)
5434 si_pm4_set_reg(pm4
, R_028AB8_VGT_VTX_CNT_EN
, 0x0);
5435 if (sctx
->chip_class
< GFX7
)
5436 si_pm4_set_reg(pm4
, R_008A14_PA_CL_ENHANCE
, S_008A14_NUM_CLIP_SEQ(3) |
5437 S_008A14_CLIP_VTX_REORDER_ENA(1));
5439 /* CLEAR_STATE doesn't clear these correctly on certain generations.
5440 * I don't know why. Deduced by trial and error.
5442 if (sctx
->chip_class
<= GFX7
|| !has_clear_state
) {
5443 si_pm4_set_reg(pm4
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
5444 si_pm4_set_reg(pm4
, R_028204_PA_SC_WINDOW_SCISSOR_TL
, S_028204_WINDOW_OFFSET_DISABLE(1));
5445 si_pm4_set_reg(pm4
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, S_028240_WINDOW_OFFSET_DISABLE(1));
5446 si_pm4_set_reg(pm4
, R_028244_PA_SC_GENERIC_SCISSOR_BR
,
5447 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
5448 si_pm4_set_reg(pm4
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 0);
5449 si_pm4_set_reg(pm4
, R_028034_PA_SC_SCREEN_SCISSOR_BR
,
5450 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
5453 if (!has_clear_state
) {
5454 si_pm4_set_reg(pm4
, R_028230_PA_SC_EDGERULE
,
5455 S_028230_ER_TRI(0xA) |
5456 S_028230_ER_POINT(0xA) |
5457 S_028230_ER_RECT(0xA) |
5458 /* Required by DX10_DIAMOND_TEST_ENA: */
5459 S_028230_ER_LINE_LR(0x1A) |
5460 S_028230_ER_LINE_RL(0x26) |
5461 S_028230_ER_LINE_TB(0xA) |
5462 S_028230_ER_LINE_BT(0xA));
5463 si_pm4_set_reg(pm4
, R_028820_PA_CL_NANINF_CNTL
, 0);
5464 si_pm4_set_reg(pm4
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 0x0);
5465 si_pm4_set_reg(pm4
, R_028AC4_DB_SRESULTS_COMPARE_STATE1
, 0x0);
5466 si_pm4_set_reg(pm4
, R_028AC8_DB_PRELOAD_CONTROL
, 0x0);
5467 si_pm4_set_reg(pm4
, R_02800C_DB_RENDER_OVERRIDE
, 0);
5470 if (sctx
->chip_class
>= GFX10
) {
5471 si_pm4_set_reg(pm4
, R_028A98_VGT_DRAW_PAYLOAD_CNTL
, 0);
5472 si_pm4_set_reg(pm4
, R_030964_GE_MAX_VTX_INDX
, ~0);
5473 si_pm4_set_reg(pm4
, R_030924_GE_MIN_VTX_INDX
, 0);
5474 si_pm4_set_reg(pm4
, R_030928_GE_INDX_OFFSET
, 0);
5475 si_pm4_set_reg(pm4
, R_03097C_GE_STEREO_CNTL
, 0);
5476 si_pm4_set_reg(pm4
, R_030988_GE_USER_VGPR_EN
, 0);
5477 } else if (sctx
->chip_class
== GFX9
) {
5478 si_pm4_set_reg(pm4
, R_030920_VGT_MAX_VTX_INDX
, ~0);
5479 si_pm4_set_reg(pm4
, R_030924_VGT_MIN_VTX_INDX
, 0);
5480 si_pm4_set_reg(pm4
, R_030928_VGT_INDX_OFFSET
, 0);
5482 /* These registers, when written, also overwrite the CLEAR_STATE
5483 * context, so we can't rely on CLEAR_STATE setting them.
5484 * It would be an issue if there was another UMD changing them.
5486 si_pm4_set_reg(pm4
, R_028400_VGT_MAX_VTX_INDX
, ~0);
5487 si_pm4_set_reg(pm4
, R_028404_VGT_MIN_VTX_INDX
, 0);
5488 si_pm4_set_reg(pm4
, R_028408_VGT_INDX_OFFSET
, 0);
5491 if (sctx
->chip_class
>= GFX7
) {
5492 if (sctx
->chip_class
>= GFX10
) {
5493 /* Logical CUs 16 - 31 */
5494 si_pm4_set_reg(pm4
, R_00B404_SPI_SHADER_PGM_RSRC4_HS
,
5495 S_00B404_CU_EN(0xffff));
5496 si_pm4_set_reg(pm4
, R_00B104_SPI_SHADER_PGM_RSRC4_VS
,
5497 S_00B104_CU_EN(0xffff));
5498 si_pm4_set_reg(pm4
, R_00B004_SPI_SHADER_PGM_RSRC4_PS
,
5499 S_00B004_CU_EN(0xffff));
5502 if (sctx
->chip_class
>= GFX9
) {
5503 si_pm4_set_reg(pm4
, R_00B41C_SPI_SHADER_PGM_RSRC3_HS
,
5504 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
5506 si_pm4_set_reg(pm4
, R_00B51C_SPI_SHADER_PGM_RSRC3_LS
,
5507 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
5508 si_pm4_set_reg(pm4
, R_00B41C_SPI_SHADER_PGM_RSRC3_HS
,
5509 S_00B41C_WAVE_LIMIT(0x3F));
5510 si_pm4_set_reg(pm4
, R_00B31C_SPI_SHADER_PGM_RSRC3_ES
,
5511 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
5513 /* If this is 0, Bonaire can hang even if GS isn't being used.
5514 * Other chips are unaffected. These are suboptimal values,
5515 * but we don't use on-chip GS.
5517 si_pm4_set_reg(pm4
, R_028A44_VGT_GS_ONCHIP_CNTL
,
5518 S_028A44_ES_VERTS_PER_SUBGRP(64) |
5519 S_028A44_GS_PRIMS_PER_SUBGRP(4));
5522 /* Compute LATE_ALLOC_VS.LIMIT. */
5523 unsigned num_cu_per_sh
= sscreen
->info
.num_good_cu_per_sh
;
5524 unsigned late_alloc_limit
; /* The limit is per SH. */
5526 if (sctx
->family
== CHIP_KABINI
) {
5527 late_alloc_limit
= 0; /* Potential hang on Kabini. */
5528 } else if (num_cu_per_sh
<= 4) {
5529 /* Too few available compute units per SH. Disallowing
5530 * VS to run on one CU could hurt us more than late VS
5531 * allocation would help.
5533 * 2 is the highest safe number that allows us to keep
5536 late_alloc_limit
= 2;
5538 /* This is a good initial value, allowing 1 late_alloc
5539 * wave per SIMD on num_cu - 2.
5541 late_alloc_limit
= (num_cu_per_sh
- 2) * 4;
5544 unsigned late_alloc_limit_gs
= late_alloc_limit
;
5545 unsigned cu_mask_vs
= 0xffff;
5546 unsigned cu_mask_gs
= 0xffff;
5548 if (late_alloc_limit
> 2) {
5549 if (sctx
->chip_class
>= GFX10
) {
5550 /* CU2 & CU3 disabled because of the dual CU design */
5551 cu_mask_vs
= 0xfff3;
5552 cu_mask_gs
= 0xfff3; /* NGG only */
5554 cu_mask_vs
= 0xfffe; /* 1 CU disabled */
5558 /* Don't use late alloc for NGG on Navi14 due to a hw bug.
5559 * If NGG is never used, enable all CUs.
5561 if (!sscreen
->use_ngg
|| sctx
->family
== CHIP_NAVI14
) {
5562 late_alloc_limit_gs
= 0;
5563 cu_mask_gs
= 0xffff;
5566 /* VS can't execute on one CU if the limit is > 2. */
5567 si_pm4_set_reg(pm4
, R_00B118_SPI_SHADER_PGM_RSRC3_VS
,
5568 S_00B118_CU_EN(cu_mask_vs
) |
5569 S_00B118_WAVE_LIMIT(0x3F));
5570 si_pm4_set_reg(pm4
, R_00B11C_SPI_SHADER_LATE_ALLOC_VS
,
5571 S_00B11C_LIMIT(late_alloc_limit
));
5573 si_pm4_set_reg(pm4
, R_00B21C_SPI_SHADER_PGM_RSRC3_GS
,
5574 S_00B21C_CU_EN(cu_mask_gs
) | S_00B21C_WAVE_LIMIT(0x3F));
5576 if (sctx
->chip_class
>= GFX10
) {
5577 si_pm4_set_reg(pm4
, R_00B204_SPI_SHADER_PGM_RSRC4_GS
,
5578 S_00B204_CU_EN(0xffff) |
5579 S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(late_alloc_limit_gs
));
5582 si_pm4_set_reg(pm4
, R_00B01C_SPI_SHADER_PGM_RSRC3_PS
,
5583 S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
5586 if (sctx
->chip_class
>= GFX10
) {
5587 /* Break up a pixel wave if it contains deallocs for more than
5588 * half the parameter cache.
5590 * To avoid a deadlock where pixel waves aren't launched
5591 * because they're waiting for more pixels while the frontend
5592 * is stuck waiting for PC space, the maximum allowed value is
5593 * the size of the PC minus the largest possible allocation for
5594 * a single primitive shader subgroup.
5596 si_pm4_set_reg(pm4
, R_028C50_PA_SC_NGG_MODE_CNTL
,
5597 S_028C50_MAX_DEALLOCS_IN_WAVE(512));
5598 si_pm4_set_reg(pm4
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
, 14);
5600 if (!has_clear_state
) {
5601 si_pm4_set_reg(pm4
, R_02835C_PA_SC_TILE_STEERING_OVERRIDE
,
5602 sscreen
->info
.pa_sc_tile_steering_override
);
5605 si_pm4_set_reg(pm4
, R_02807C_DB_RMI_L2_CACHE_CONTROL
,
5606 S_02807C_Z_WR_POLICY(V_02807C_CACHE_STREAM_WR
) |
5607 S_02807C_S_WR_POLICY(V_02807C_CACHE_STREAM_WR
) |
5608 S_02807C_HTILE_WR_POLICY(V_02807C_CACHE_STREAM_WR
) |
5609 S_02807C_ZPCPSD_WR_POLICY(V_02807C_CACHE_STREAM_WR
) |
5610 S_02807C_Z_RD_POLICY(V_02807C_CACHE_NOA_RD
) |
5611 S_02807C_S_RD_POLICY(V_02807C_CACHE_NOA_RD
) |
5612 S_02807C_HTILE_RD_POLICY(V_02807C_CACHE_NOA_RD
));
5614 si_pm4_set_reg(pm4
, R_028410_CB_RMI_GL2_CACHE_CONTROL
,
5615 S_028410_CMASK_WR_POLICY(V_028410_CACHE_STREAM_WR
) |
5616 S_028410_FMASK_WR_POLICY(V_028410_CACHE_STREAM_WR
) |
5617 S_028410_DCC_WR_POLICY(V_028410_CACHE_STREAM_WR
) |
5618 S_028410_COLOR_WR_POLICY(V_028410_CACHE_STREAM_WR
) |
5619 S_028410_CMASK_RD_POLICY(V_028410_CACHE_NOA_RD
) |
5620 S_028410_FMASK_RD_POLICY(V_028410_CACHE_NOA_RD
) |
5621 S_028410_DCC_RD_POLICY(V_028410_CACHE_NOA_RD
) |
5622 S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA_RD
));
5623 si_pm4_set_reg(pm4
, R_028428_CB_COVERAGE_OUT_CONTROL
, 0);
5625 si_pm4_set_reg(pm4
, R_00B0C0_SPI_SHADER_REQ_CTRL_PS
,
5626 S_00B0C0_SOFT_GROUPING_EN(1) |
5627 S_00B0C0_NUMBER_OF_REQUESTS_PER_CU(4 - 1));
5628 si_pm4_set_reg(pm4
, R_00B1C0_SPI_SHADER_REQ_CTRL_VS
, 0);
5630 if (sctx
->family
== CHIP_NAVI10
||
5631 sctx
->family
== CHIP_NAVI12
||
5632 sctx
->family
== CHIP_NAVI14
) {
5633 /* SQ_NON_EVENT must be emitted before GE_PC_ALLOC is written. */
5634 si_pm4_cmd_begin(pm4
, PKT3_EVENT_WRITE
);
5635 si_pm4_cmd_add(pm4
, EVENT_TYPE(V_028A90_SQ_NON_EVENT
) | EVENT_INDEX(0));
5636 si_pm4_cmd_end(pm4
, false);
5638 /* TODO: For culling, replace 128 with 256. */
5639 si_pm4_set_reg(pm4
, R_030980_GE_PC_ALLOC
,
5640 S_030980_OVERSUB_EN(1) |
5641 S_030980_NUM_PC_LINES(128 * sscreen
->info
.max_se
- 1));
5644 if (sctx
->chip_class
>= GFX8
) {
5645 unsigned vgt_tess_distribution
;
5647 vgt_tess_distribution
=
5648 S_028B50_ACCUM_ISOLINE(32) |
5649 S_028B50_ACCUM_TRI(11) |
5650 S_028B50_ACCUM_QUAD(11) |
5651 S_028B50_DONUT_SPLIT(16);
5653 /* Testing with Unigine Heaven extreme tesselation yielded best results
5654 * with TRAP_SPLIT = 3.
5656 if (sctx
->family
== CHIP_FIJI
||
5657 sctx
->family
>= CHIP_POLARIS10
)
5658 vgt_tess_distribution
|= S_028B50_TRAP_SPLIT(3);
5660 si_pm4_set_reg(pm4
, R_028B50_VGT_TESS_DISTRIBUTION
, vgt_tess_distribution
);
5661 } else if (!has_clear_state
) {
5662 si_pm4_set_reg(pm4
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
, 14);
5663 si_pm4_set_reg(pm4
, R_028C5C_VGT_OUT_DEALLOC_CNTL
, 16);
5666 si_pm4_set_reg(pm4
, R_028080_TA_BC_BASE_ADDR
, border_color_va
>> 8);
5667 if (sctx
->chip_class
>= GFX7
) {
5668 si_pm4_set_reg(pm4
, R_028084_TA_BC_BASE_ADDR_HI
,
5669 S_028084_ADDRESS(border_color_va
>> 40));
5671 si_pm4_add_bo(pm4
, sctx
->border_color_buffer
, RADEON_USAGE_READ
,
5672 RADEON_PRIO_BORDER_COLORS
);
5674 if (sctx
->chip_class
>= GFX9
) {
5675 unsigned num_se
= sscreen
->info
.max_se
;
5676 unsigned pc_lines
= 0;
5677 unsigned max_alloc_count
= 0;
5679 switch (sctx
->family
) {
5699 if (sctx
->chip_class
>= GFX10
) {
5700 max_alloc_count
= pc_lines
/ 3;
5702 max_alloc_count
= MIN2(128, pc_lines
/ (4 * num_se
));
5705 si_pm4_set_reg(pm4
, R_028C48_PA_SC_BINNER_CNTL_1
,
5706 S_028C48_MAX_ALLOC_COUNT(max_alloc_count
- 1) |
5707 S_028C48_MAX_PRIM_PER_BATCH(1023));
5708 si_pm4_set_reg(pm4
, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
,
5709 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
5710 si_pm4_set_reg(pm4
, R_030968_VGT_INSTANCE_BASE_ID
, 0);
5713 si_pm4_upload_indirect_buffer(sctx
, pm4
);
5714 sctx
->init_config
= pm4
;