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radeonsi: add the htile buffer to the CS ioctl buffer list
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "util/u_memory.h"
28 #include "util/u_framebuffer.h"
29 #include "util/u_blitter.h"
30 #include "util/u_helpers.h"
31 #include "util/u_math.h"
32 #include "util/u_pack_color.h"
33 #include "util/u_upload_mgr.h"
34 #include "util/u_format_s3tc.h"
35 #include "tgsi/tgsi_parse.h"
36 #include "tgsi/tgsi_scan.h"
37 #include "radeonsi_pipe.h"
38 #include "radeonsi_shader.h"
39 #include "si_state.h"
40 #include "../radeon/r600_cs.h"
41 #include "sid.h"
42
43 static uint32_t cik_num_banks(uint32_t nbanks)
44 {
45 switch (nbanks) {
46 case 2:
47 return V_02803C_ADDR_SURF_2_BANK;
48 case 4:
49 return V_02803C_ADDR_SURF_4_BANK;
50 case 8:
51 default:
52 return V_02803C_ADDR_SURF_8_BANK;
53 case 16:
54 return V_02803C_ADDR_SURF_16_BANK;
55 }
56 }
57
58
59 static unsigned cik_tile_split(unsigned tile_split)
60 {
61 switch (tile_split) {
62 case 64:
63 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_64B;
64 break;
65 case 128:
66 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_128B;
67 break;
68 case 256:
69 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_256B;
70 break;
71 case 512:
72 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_512B;
73 break;
74 default:
75 case 1024:
76 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_1KB;
77 break;
78 case 2048:
79 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_2KB;
80 break;
81 case 4096:
82 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_4KB;
83 break;
84 }
85 return tile_split;
86 }
87
88 static unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect)
89 {
90 switch (macro_tile_aspect) {
91 default:
92 case 1:
93 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_1;
94 break;
95 case 2:
96 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_2;
97 break;
98 case 4:
99 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_4;
100 break;
101 case 8:
102 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_8;
103 break;
104 }
105 return macro_tile_aspect;
106 }
107
108 static unsigned cik_bank_wh(unsigned bankwh)
109 {
110 switch (bankwh) {
111 default:
112 case 1:
113 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_1;
114 break;
115 case 2:
116 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_2;
117 break;
118 case 4:
119 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_4;
120 break;
121 case 8:
122 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_8;
123 break;
124 }
125 return bankwh;
126 }
127
128 static unsigned cik_db_pipe_config(unsigned tile_pipes,
129 unsigned num_rbs)
130 {
131 unsigned pipe_config;
132
133 switch (tile_pipes) {
134 case 8:
135 pipe_config = V_02803C_X_ADDR_SURF_P8_32X32_16X16;
136 break;
137 case 4:
138 default:
139 if (num_rbs == 4)
140 pipe_config = V_02803C_X_ADDR_SURF_P4_16X16;
141 else
142 pipe_config = V_02803C_X_ADDR_SURF_P4_8X16;
143 break;
144 case 2:
145 pipe_config = V_02803C_ADDR_SURF_P2;
146 break;
147 }
148 return pipe_config;
149 }
150
151 /*
152 * inferred framebuffer and blender state
153 */
154 static void si_update_fb_blend_state(struct r600_context *rctx)
155 {
156 struct si_pm4_state *pm4;
157 struct si_state_blend *blend = rctx->queued.named.blend;
158 uint32_t mask;
159
160 if (blend == NULL)
161 return;
162
163 pm4 = si_pm4_alloc_state(rctx);
164 if (pm4 == NULL)
165 return;
166
167 mask = (1ULL << ((unsigned)rctx->framebuffer.nr_cbufs * 4)) - 1;
168 mask &= blend->cb_target_mask;
169 si_pm4_set_reg(pm4, R_028238_CB_TARGET_MASK, mask);
170
171 si_pm4_set_state(rctx, fb_blend, pm4);
172 }
173
174 /*
175 * Blender functions
176 */
177
178 static uint32_t si_translate_blend_function(int blend_func)
179 {
180 switch (blend_func) {
181 case PIPE_BLEND_ADD:
182 return V_028780_COMB_DST_PLUS_SRC;
183 case PIPE_BLEND_SUBTRACT:
184 return V_028780_COMB_SRC_MINUS_DST;
185 case PIPE_BLEND_REVERSE_SUBTRACT:
186 return V_028780_COMB_DST_MINUS_SRC;
187 case PIPE_BLEND_MIN:
188 return V_028780_COMB_MIN_DST_SRC;
189 case PIPE_BLEND_MAX:
190 return V_028780_COMB_MAX_DST_SRC;
191 default:
192 R600_ERR("Unknown blend function %d\n", blend_func);
193 assert(0);
194 break;
195 }
196 return 0;
197 }
198
199 static uint32_t si_translate_blend_factor(int blend_fact)
200 {
201 switch (blend_fact) {
202 case PIPE_BLENDFACTOR_ONE:
203 return V_028780_BLEND_ONE;
204 case PIPE_BLENDFACTOR_SRC_COLOR:
205 return V_028780_BLEND_SRC_COLOR;
206 case PIPE_BLENDFACTOR_SRC_ALPHA:
207 return V_028780_BLEND_SRC_ALPHA;
208 case PIPE_BLENDFACTOR_DST_ALPHA:
209 return V_028780_BLEND_DST_ALPHA;
210 case PIPE_BLENDFACTOR_DST_COLOR:
211 return V_028780_BLEND_DST_COLOR;
212 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
213 return V_028780_BLEND_SRC_ALPHA_SATURATE;
214 case PIPE_BLENDFACTOR_CONST_COLOR:
215 return V_028780_BLEND_CONSTANT_COLOR;
216 case PIPE_BLENDFACTOR_CONST_ALPHA:
217 return V_028780_BLEND_CONSTANT_ALPHA;
218 case PIPE_BLENDFACTOR_ZERO:
219 return V_028780_BLEND_ZERO;
220 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
221 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
222 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
223 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
224 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
225 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
226 case PIPE_BLENDFACTOR_INV_DST_COLOR:
227 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
228 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
229 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
230 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
231 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
232 case PIPE_BLENDFACTOR_SRC1_COLOR:
233 return V_028780_BLEND_SRC1_COLOR;
234 case PIPE_BLENDFACTOR_SRC1_ALPHA:
235 return V_028780_BLEND_SRC1_ALPHA;
236 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
237 return V_028780_BLEND_INV_SRC1_COLOR;
238 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
239 return V_028780_BLEND_INV_SRC1_ALPHA;
240 default:
241 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
242 assert(0);
243 break;
244 }
245 return 0;
246 }
247
248 static void *si_create_blend_state_mode(struct pipe_context *ctx,
249 const struct pipe_blend_state *state,
250 unsigned mode)
251 {
252 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
253 struct si_pm4_state *pm4 = &blend->pm4;
254
255 uint32_t color_control;
256
257 if (blend == NULL)
258 return NULL;
259
260 blend->alpha_to_one = state->alpha_to_one;
261
262 color_control = S_028808_MODE(mode);
263 if (state->logicop_enable) {
264 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
265 } else {
266 color_control |= S_028808_ROP3(0xcc);
267 }
268 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
269
270 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
271 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
272 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
273 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
274 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
275 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
276
277 blend->cb_target_mask = 0;
278 for (int i = 0; i < 8; i++) {
279 /* state->rt entries > 0 only written if independent blending */
280 const int j = state->independent_blend_enable ? i : 0;
281
282 unsigned eqRGB = state->rt[j].rgb_func;
283 unsigned srcRGB = state->rt[j].rgb_src_factor;
284 unsigned dstRGB = state->rt[j].rgb_dst_factor;
285 unsigned eqA = state->rt[j].alpha_func;
286 unsigned srcA = state->rt[j].alpha_src_factor;
287 unsigned dstA = state->rt[j].alpha_dst_factor;
288
289 unsigned blend_cntl = 0;
290
291 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
292 blend->cb_target_mask |= state->rt[j].colormask << (4 * i);
293
294 if (!state->rt[j].blend_enable) {
295 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
296 continue;
297 }
298
299 blend_cntl |= S_028780_ENABLE(1);
300 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
301 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
302 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
303
304 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
305 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
306 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
307 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
308 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
309 }
310 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
311 }
312
313 return blend;
314 }
315
316 static void *si_create_blend_state(struct pipe_context *ctx,
317 const struct pipe_blend_state *state)
318 {
319 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
320 }
321
322 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
323 {
324 struct r600_context *rctx = (struct r600_context *)ctx;
325 si_pm4_bind_state(rctx, blend, (struct si_state_blend *)state);
326 si_update_fb_blend_state(rctx);
327 }
328
329 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
330 {
331 struct r600_context *rctx = (struct r600_context *)ctx;
332 si_pm4_delete_state(rctx, blend, (struct si_state_blend *)state);
333 }
334
335 static void si_set_blend_color(struct pipe_context *ctx,
336 const struct pipe_blend_color *state)
337 {
338 struct r600_context *rctx = (struct r600_context *)ctx;
339 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
340
341 if (pm4 == NULL)
342 return;
343
344 si_pm4_set_reg(pm4, R_028414_CB_BLEND_RED, fui(state->color[0]));
345 si_pm4_set_reg(pm4, R_028418_CB_BLEND_GREEN, fui(state->color[1]));
346 si_pm4_set_reg(pm4, R_02841C_CB_BLEND_BLUE, fui(state->color[2]));
347 si_pm4_set_reg(pm4, R_028420_CB_BLEND_ALPHA, fui(state->color[3]));
348
349 si_pm4_set_state(rctx, blend_color, pm4);
350 }
351
352 /*
353 * Clipping, scissors and viewport
354 */
355
356 static void si_set_clip_state(struct pipe_context *ctx,
357 const struct pipe_clip_state *state)
358 {
359 struct r600_context *rctx = (struct r600_context *)ctx;
360 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
361 struct pipe_constant_buffer cb;
362
363 if (pm4 == NULL)
364 return;
365
366 for (int i = 0; i < 6; i++) {
367 si_pm4_set_reg(pm4, R_0285BC_PA_CL_UCP_0_X + i * 16,
368 fui(state->ucp[i][0]));
369 si_pm4_set_reg(pm4, R_0285C0_PA_CL_UCP_0_Y + i * 16,
370 fui(state->ucp[i][1]));
371 si_pm4_set_reg(pm4, R_0285C4_PA_CL_UCP_0_Z + i * 16,
372 fui(state->ucp[i][2]));
373 si_pm4_set_reg(pm4, R_0285C8_PA_CL_UCP_0_W + i * 16,
374 fui(state->ucp[i][3]));
375 }
376
377 cb.buffer = NULL;
378 cb.user_buffer = state->ucp;
379 cb.buffer_offset = 0;
380 cb.buffer_size = 4*4*8;
381 ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, NUM_PIPE_CONST_BUFFERS, &cb);
382 pipe_resource_reference(&cb.buffer, NULL);
383
384 si_pm4_set_state(rctx, clip, pm4);
385 }
386
387 static void si_set_scissor_states(struct pipe_context *ctx,
388 unsigned start_slot,
389 unsigned num_scissors,
390 const struct pipe_scissor_state *state)
391 {
392 struct r600_context *rctx = (struct r600_context *)ctx;
393 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
394 uint32_t tl, br;
395
396 if (pm4 == NULL)
397 return;
398
399 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny);
400 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
401 si_pm4_set_reg(pm4, R_028210_PA_SC_CLIPRECT_0_TL, tl);
402 si_pm4_set_reg(pm4, R_028214_PA_SC_CLIPRECT_0_BR, br);
403 si_pm4_set_reg(pm4, R_028218_PA_SC_CLIPRECT_1_TL, tl);
404 si_pm4_set_reg(pm4, R_02821C_PA_SC_CLIPRECT_1_BR, br);
405 si_pm4_set_reg(pm4, R_028220_PA_SC_CLIPRECT_2_TL, tl);
406 si_pm4_set_reg(pm4, R_028224_PA_SC_CLIPRECT_2_BR, br);
407 si_pm4_set_reg(pm4, R_028228_PA_SC_CLIPRECT_3_TL, tl);
408 si_pm4_set_reg(pm4, R_02822C_PA_SC_CLIPRECT_3_BR, br);
409
410 si_pm4_set_state(rctx, scissor, pm4);
411 }
412
413 static void si_set_viewport_states(struct pipe_context *ctx,
414 unsigned start_slot,
415 unsigned num_viewports,
416 const struct pipe_viewport_state *state)
417 {
418 struct r600_context *rctx = (struct r600_context *)ctx;
419 struct si_state_viewport *viewport = CALLOC_STRUCT(si_state_viewport);
420 struct si_pm4_state *pm4 = &viewport->pm4;
421
422 if (viewport == NULL)
423 return;
424
425 viewport->viewport = *state;
426 si_pm4_set_reg(pm4, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
427 si_pm4_set_reg(pm4, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
428 si_pm4_set_reg(pm4, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
429 si_pm4_set_reg(pm4, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
430 si_pm4_set_reg(pm4, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
431 si_pm4_set_reg(pm4, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
432
433 si_pm4_set_state(rctx, viewport, viewport);
434 }
435
436 /*
437 * inferred state between framebuffer and rasterizer
438 */
439 static void si_update_fb_rs_state(struct r600_context *rctx)
440 {
441 struct si_state_rasterizer *rs = rctx->queued.named.rasterizer;
442 struct si_pm4_state *pm4;
443 unsigned offset_db_fmt_cntl = 0, depth;
444 float offset_units;
445
446 if (!rs || !rctx->framebuffer.zsbuf)
447 return;
448
449 offset_units = rctx->queued.named.rasterizer->offset_units;
450 switch (rctx->framebuffer.zsbuf->texture->format) {
451 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
452 case PIPE_FORMAT_X8Z24_UNORM:
453 case PIPE_FORMAT_Z24X8_UNORM:
454 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
455 depth = -24;
456 offset_units *= 2.0f;
457 break;
458 case PIPE_FORMAT_Z32_FLOAT:
459 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
460 depth = -23;
461 offset_units *= 1.0f;
462 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
463 break;
464 case PIPE_FORMAT_Z16_UNORM:
465 depth = -16;
466 offset_units *= 4.0f;
467 break;
468 default:
469 return;
470 }
471
472 pm4 = si_pm4_alloc_state(rctx);
473
474 if (pm4 == NULL)
475 return;
476
477 /* FIXME some of those reg can be computed with cso */
478 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
479 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
480 fui(rctx->queued.named.rasterizer->offset_scale));
481 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units));
482 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
483 fui(rctx->queued.named.rasterizer->offset_scale));
484 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units));
485 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, offset_db_fmt_cntl);
486
487 si_pm4_set_state(rctx, fb_rs, pm4);
488 }
489
490 /*
491 * Rasterizer
492 */
493
494 static uint32_t si_translate_fill(uint32_t func)
495 {
496 switch(func) {
497 case PIPE_POLYGON_MODE_FILL:
498 return V_028814_X_DRAW_TRIANGLES;
499 case PIPE_POLYGON_MODE_LINE:
500 return V_028814_X_DRAW_LINES;
501 case PIPE_POLYGON_MODE_POINT:
502 return V_028814_X_DRAW_POINTS;
503 default:
504 assert(0);
505 return V_028814_X_DRAW_POINTS;
506 }
507 }
508
509 static void *si_create_rs_state(struct pipe_context *ctx,
510 const struct pipe_rasterizer_state *state)
511 {
512 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
513 struct si_pm4_state *pm4 = &rs->pm4;
514 unsigned tmp;
515 unsigned prov_vtx = 1, polygon_dual_mode;
516 unsigned clip_rule;
517 float psize_min, psize_max;
518
519 if (rs == NULL) {
520 return NULL;
521 }
522
523 rs->two_side = state->light_twoside;
524 rs->multisample_enable = state->multisample;
525 rs->clip_plane_enable = state->clip_plane_enable;
526 rs->line_stipple_enable = state->line_stipple_enable;
527
528 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
529 state->fill_back != PIPE_POLYGON_MODE_FILL);
530
531 if (state->flatshade_first)
532 prov_vtx = 0;
533
534 rs->flatshade = state->flatshade;
535 rs->sprite_coord_enable = state->sprite_coord_enable;
536 rs->pa_sc_line_stipple = state->line_stipple_enable ?
537 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
538 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
539 rs->pa_su_sc_mode_cntl =
540 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
541 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
542 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
543 S_028814_FACE(!state->front_ccw) |
544 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
545 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
546 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
547 S_028814_POLY_MODE(polygon_dual_mode) |
548 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
549 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back));
550 rs->pa_cl_clip_cntl =
551 S_028810_PS_UCP_MODE(3) |
552 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
553 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
554 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
555 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
556
557 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
558
559 /* offset */
560 rs->offset_units = state->offset_units;
561 rs->offset_scale = state->offset_scale * 12.0f;
562
563 tmp = S_0286D4_FLAT_SHADE_ENA(1);
564 if (state->sprite_coord_enable) {
565 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
566 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
567 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
568 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
569 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1);
570 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
571 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
572 }
573 }
574 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
575
576 /* point size 12.4 fixed point */
577 tmp = (unsigned)(state->point_size * 8.0);
578 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
579
580 if (state->point_size_per_vertex) {
581 psize_min = util_get_min_point_size(state);
582 psize_max = 8192;
583 } else {
584 /* Force the point size to be as if the vertex output was disabled. */
585 psize_min = state->point_size;
586 psize_max = state->point_size;
587 }
588 /* Divide by two, because 0.5 = 1 pixel. */
589 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
590 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
591 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
592
593 tmp = (unsigned)state->line_width * 8;
594 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
595 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
596 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
597 S_028A48_MSAA_ENABLE(state->multisample));
598
599 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
600 S_028BE4_PIX_CENTER(state->half_pixel_center) |
601 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
602
603 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
604 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule);
605
606 return rs;
607 }
608
609 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
610 {
611 struct r600_context *rctx = (struct r600_context *)ctx;
612 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
613
614 if (state == NULL)
615 return;
616
617 // TODO
618 rctx->sprite_coord_enable = rs->sprite_coord_enable;
619 rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
620 rctx->pa_su_sc_mode_cntl = rs->pa_su_sc_mode_cntl;
621
622 si_pm4_bind_state(rctx, rasterizer, rs);
623 si_update_fb_rs_state(rctx);
624 }
625
626 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
627 {
628 struct r600_context *rctx = (struct r600_context *)ctx;
629 si_pm4_delete_state(rctx, rasterizer, (struct si_state_rasterizer *)state);
630 }
631
632 /*
633 * infeered state between dsa and stencil ref
634 */
635 static void si_update_dsa_stencil_ref(struct r600_context *rctx)
636 {
637 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
638 struct pipe_stencil_ref *ref = &rctx->stencil_ref;
639 struct si_state_dsa *dsa = rctx->queued.named.dsa;
640
641 if (pm4 == NULL)
642 return;
643
644 si_pm4_set_reg(pm4, R_028430_DB_STENCILREFMASK,
645 S_028430_STENCILTESTVAL(ref->ref_value[0]) |
646 S_028430_STENCILMASK(dsa->valuemask[0]) |
647 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
648 S_028430_STENCILOPVAL(1));
649 si_pm4_set_reg(pm4, R_028434_DB_STENCILREFMASK_BF,
650 S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
651 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
652 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
653 S_028434_STENCILOPVAL_BF(1));
654
655 si_pm4_set_state(rctx, dsa_stencil_ref, pm4);
656 }
657
658 static void si_set_pipe_stencil_ref(struct pipe_context *ctx,
659 const struct pipe_stencil_ref *state)
660 {
661 struct r600_context *rctx = (struct r600_context *)ctx;
662 rctx->stencil_ref = *state;
663 si_update_dsa_stencil_ref(rctx);
664 }
665
666
667 /*
668 * DSA
669 */
670
671 static uint32_t si_translate_stencil_op(int s_op)
672 {
673 switch (s_op) {
674 case PIPE_STENCIL_OP_KEEP:
675 return V_02842C_STENCIL_KEEP;
676 case PIPE_STENCIL_OP_ZERO:
677 return V_02842C_STENCIL_ZERO;
678 case PIPE_STENCIL_OP_REPLACE:
679 return V_02842C_STENCIL_REPLACE_TEST;
680 case PIPE_STENCIL_OP_INCR:
681 return V_02842C_STENCIL_ADD_CLAMP;
682 case PIPE_STENCIL_OP_DECR:
683 return V_02842C_STENCIL_SUB_CLAMP;
684 case PIPE_STENCIL_OP_INCR_WRAP:
685 return V_02842C_STENCIL_ADD_WRAP;
686 case PIPE_STENCIL_OP_DECR_WRAP:
687 return V_02842C_STENCIL_SUB_WRAP;
688 case PIPE_STENCIL_OP_INVERT:
689 return V_02842C_STENCIL_INVERT;
690 default:
691 R600_ERR("Unknown stencil op %d", s_op);
692 assert(0);
693 break;
694 }
695 return 0;
696 }
697
698 static void *si_create_dsa_state(struct pipe_context *ctx,
699 const struct pipe_depth_stencil_alpha_state *state)
700 {
701 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
702 struct si_pm4_state *pm4 = &dsa->pm4;
703 unsigned db_depth_control;
704 unsigned db_render_control;
705 uint32_t db_stencil_control = 0;
706
707 if (dsa == NULL) {
708 return NULL;
709 }
710
711 dsa->valuemask[0] = state->stencil[0].valuemask;
712 dsa->valuemask[1] = state->stencil[1].valuemask;
713 dsa->writemask[0] = state->stencil[0].writemask;
714 dsa->writemask[1] = state->stencil[1].writemask;
715
716 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
717 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
718 S_028800_ZFUNC(state->depth.func);
719
720 /* stencil */
721 if (state->stencil[0].enabled) {
722 db_depth_control |= S_028800_STENCIL_ENABLE(1);
723 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
724 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
725 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
726 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
727
728 if (state->stencil[1].enabled) {
729 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
730 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
731 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
732 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
733 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
734 }
735 }
736
737 /* alpha */
738 if (state->alpha.enabled) {
739 dsa->alpha_func = state->alpha.func;
740 dsa->alpha_ref = state->alpha.ref_value;
741
742 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
743 SI_SGPR_ALPHA_REF * 4, fui(dsa->alpha_ref));
744 } else {
745 dsa->alpha_func = PIPE_FUNC_ALWAYS;
746 }
747
748 /* misc */
749 db_render_control = 0;
750 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
751 si_pm4_set_reg(pm4, R_028000_DB_RENDER_CONTROL, db_render_control);
752 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
753
754 return dsa;
755 }
756
757 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
758 {
759 struct r600_context *rctx = (struct r600_context *)ctx;
760 struct si_state_dsa *dsa = state;
761
762 if (state == NULL)
763 return;
764
765 si_pm4_bind_state(rctx, dsa, dsa);
766 si_update_dsa_stencil_ref(rctx);
767 }
768
769 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
770 {
771 struct r600_context *rctx = (struct r600_context *)ctx;
772 si_pm4_delete_state(rctx, dsa, (struct si_state_dsa *)state);
773 }
774
775 static void *si_create_db_flush_dsa(struct r600_context *rctx, bool copy_depth,
776 bool copy_stencil, int sample)
777 {
778 struct pipe_depth_stencil_alpha_state dsa;
779 struct si_state_dsa *state;
780
781 memset(&dsa, 0, sizeof(dsa));
782
783 state = rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa);
784 if (copy_depth || copy_stencil) {
785 si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL,
786 S_028000_DEPTH_COPY(copy_depth) |
787 S_028000_STENCIL_COPY(copy_stencil) |
788 S_028000_COPY_CENTROID(1) |
789 S_028000_COPY_SAMPLE(sample));
790 } else {
791 si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL,
792 S_028000_DEPTH_COMPRESS_DISABLE(1) |
793 S_028000_STENCIL_COMPRESS_DISABLE(1));
794 }
795
796 return state;
797 }
798
799 /*
800 * format translation
801 */
802 static uint32_t si_translate_colorformat(enum pipe_format format)
803 {
804 const struct util_format_description *desc = util_format_description(format);
805
806 #define HAS_SIZE(x,y,z,w) \
807 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
808 desc->channel[2].size == (z) && desc->channel[3].size == (w))
809
810 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
811 return V_028C70_COLOR_10_11_11;
812
813 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
814 return V_028C70_COLOR_INVALID;
815
816 switch (desc->nr_channels) {
817 case 1:
818 switch (desc->channel[0].size) {
819 case 8:
820 return V_028C70_COLOR_8;
821 case 16:
822 return V_028C70_COLOR_16;
823 case 32:
824 return V_028C70_COLOR_32;
825 }
826 break;
827 case 2:
828 if (desc->channel[0].size == desc->channel[1].size) {
829 switch (desc->channel[0].size) {
830 case 8:
831 return V_028C70_COLOR_8_8;
832 case 16:
833 return V_028C70_COLOR_16_16;
834 case 32:
835 return V_028C70_COLOR_32_32;
836 }
837 } else if (HAS_SIZE(8,24,0,0)) {
838 return V_028C70_COLOR_24_8;
839 } else if (HAS_SIZE(24,8,0,0)) {
840 return V_028C70_COLOR_8_24;
841 }
842 break;
843 case 3:
844 if (HAS_SIZE(5,6,5,0)) {
845 return V_028C70_COLOR_5_6_5;
846 } else if (HAS_SIZE(32,8,24,0)) {
847 return V_028C70_COLOR_X24_8_32_FLOAT;
848 }
849 break;
850 case 4:
851 if (desc->channel[0].size == desc->channel[1].size &&
852 desc->channel[0].size == desc->channel[2].size &&
853 desc->channel[0].size == desc->channel[3].size) {
854 switch (desc->channel[0].size) {
855 case 4:
856 return V_028C70_COLOR_4_4_4_4;
857 case 8:
858 return V_028C70_COLOR_8_8_8_8;
859 case 16:
860 return V_028C70_COLOR_16_16_16_16;
861 case 32:
862 return V_028C70_COLOR_32_32_32_32;
863 }
864 } else if (HAS_SIZE(5,5,5,1)) {
865 return V_028C70_COLOR_1_5_5_5;
866 } else if (HAS_SIZE(10,10,10,2)) {
867 return V_028C70_COLOR_2_10_10_10;
868 }
869 break;
870 }
871 return V_028C70_COLOR_INVALID;
872 }
873
874 static uint32_t si_translate_colorswap(enum pipe_format format)
875 {
876 const struct util_format_description *desc = util_format_description(format);
877
878 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == UTIL_FORMAT_SWIZZLE_##swz)
879
880 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
881 return V_028C70_SWAP_STD;
882
883 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
884 return ~0;
885
886 switch (desc->nr_channels) {
887 case 1:
888 if (HAS_SWIZZLE(0,X))
889 return V_028C70_SWAP_STD; /* X___ */
890 else if (HAS_SWIZZLE(3,X))
891 return V_028C70_SWAP_ALT_REV; /* ___X */
892 break;
893 case 2:
894 if ((HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,Y)) ||
895 (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,NONE)) ||
896 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,Y)))
897 return V_028C70_SWAP_STD; /* XY__ */
898 else if ((HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,X)) ||
899 (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,NONE)) ||
900 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,X)))
901 return V_028C70_SWAP_STD_REV; /* YX__ */
902 else if (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(3,Y))
903 return V_028C70_SWAP_ALT; /* X__Y */
904 break;
905 case 3:
906 if (HAS_SWIZZLE(0,X))
907 return V_028C70_SWAP_STD; /* XYZ */
908 else if (HAS_SWIZZLE(0,Z))
909 return V_028C70_SWAP_STD_REV; /* ZYX */
910 break;
911 case 4:
912 /* check the middle channels, the 1st and 4th channel can be NONE */
913 if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,Z))
914 return V_028C70_SWAP_STD; /* XYZW */
915 else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,Y))
916 return V_028C70_SWAP_STD_REV; /* WZYX */
917 else if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,X))
918 return V_028C70_SWAP_ALT; /* ZYXW */
919 else if (HAS_SWIZZLE(1,X) && HAS_SWIZZLE(2,Y))
920 return V_028C70_SWAP_ALT_REV; /* WXYZ */
921 break;
922 }
923 return ~0U;
924 }
925
926 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
927 {
928 if (R600_BIG_ENDIAN) {
929 switch(colorformat) {
930 /* 8-bit buffers. */
931 case V_028C70_COLOR_8:
932 return V_028C70_ENDIAN_NONE;
933
934 /* 16-bit buffers. */
935 case V_028C70_COLOR_5_6_5:
936 case V_028C70_COLOR_1_5_5_5:
937 case V_028C70_COLOR_4_4_4_4:
938 case V_028C70_COLOR_16:
939 case V_028C70_COLOR_8_8:
940 return V_028C70_ENDIAN_8IN16;
941
942 /* 32-bit buffers. */
943 case V_028C70_COLOR_8_8_8_8:
944 case V_028C70_COLOR_2_10_10_10:
945 case V_028C70_COLOR_8_24:
946 case V_028C70_COLOR_24_8:
947 case V_028C70_COLOR_16_16:
948 return V_028C70_ENDIAN_8IN32;
949
950 /* 64-bit buffers. */
951 case V_028C70_COLOR_16_16_16_16:
952 return V_028C70_ENDIAN_8IN16;
953
954 case V_028C70_COLOR_32_32:
955 return V_028C70_ENDIAN_8IN32;
956
957 /* 128-bit buffers. */
958 case V_028C70_COLOR_32_32_32_32:
959 return V_028C70_ENDIAN_8IN32;
960 default:
961 return V_028C70_ENDIAN_NONE; /* Unsupported. */
962 }
963 } else {
964 return V_028C70_ENDIAN_NONE;
965 }
966 }
967
968 /* Returns the size in bits of the widest component of a CB format */
969 static unsigned si_colorformat_max_comp_size(uint32_t colorformat)
970 {
971 switch(colorformat) {
972 case V_028C70_COLOR_4_4_4_4:
973 return 4;
974
975 case V_028C70_COLOR_1_5_5_5:
976 case V_028C70_COLOR_5_5_5_1:
977 return 5;
978
979 case V_028C70_COLOR_5_6_5:
980 return 6;
981
982 case V_028C70_COLOR_8:
983 case V_028C70_COLOR_8_8:
984 case V_028C70_COLOR_8_8_8_8:
985 return 8;
986
987 case V_028C70_COLOR_10_10_10_2:
988 case V_028C70_COLOR_2_10_10_10:
989 return 10;
990
991 case V_028C70_COLOR_10_11_11:
992 case V_028C70_COLOR_11_11_10:
993 return 11;
994
995 case V_028C70_COLOR_16:
996 case V_028C70_COLOR_16_16:
997 case V_028C70_COLOR_16_16_16_16:
998 return 16;
999
1000 case V_028C70_COLOR_8_24:
1001 case V_028C70_COLOR_24_8:
1002 return 24;
1003
1004 case V_028C70_COLOR_32:
1005 case V_028C70_COLOR_32_32:
1006 case V_028C70_COLOR_32_32_32_32:
1007 case V_028C70_COLOR_X24_8_32_FLOAT:
1008 return 32;
1009 }
1010
1011 assert(!"Unknown maximum component size");
1012 return 0;
1013 }
1014
1015 static uint32_t si_translate_dbformat(enum pipe_format format)
1016 {
1017 switch (format) {
1018 case PIPE_FORMAT_Z16_UNORM:
1019 return V_028040_Z_16;
1020 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1021 case PIPE_FORMAT_X8Z24_UNORM:
1022 case PIPE_FORMAT_Z24X8_UNORM:
1023 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1024 return V_028040_Z_24; /* deprecated on SI */
1025 case PIPE_FORMAT_Z32_FLOAT:
1026 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1027 return V_028040_Z_32_FLOAT;
1028 default:
1029 return V_028040_Z_INVALID;
1030 }
1031 }
1032
1033 /*
1034 * Texture translation
1035 */
1036
1037 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1038 enum pipe_format format,
1039 const struct util_format_description *desc,
1040 int first_non_void)
1041 {
1042 struct r600_screen *rscreen = (struct r600_screen*)screen;
1043 bool enable_s3tc = rscreen->b.info.drm_minor >= 31;
1044 boolean uniform = TRUE;
1045 int i;
1046
1047 /* Colorspace (return non-RGB formats directly). */
1048 switch (desc->colorspace) {
1049 /* Depth stencil formats */
1050 case UTIL_FORMAT_COLORSPACE_ZS:
1051 switch (format) {
1052 case PIPE_FORMAT_Z16_UNORM:
1053 return V_008F14_IMG_DATA_FORMAT_16;
1054 case PIPE_FORMAT_X24S8_UINT:
1055 case PIPE_FORMAT_Z24X8_UNORM:
1056 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1057 return V_008F14_IMG_DATA_FORMAT_8_24;
1058 case PIPE_FORMAT_X8Z24_UNORM:
1059 case PIPE_FORMAT_S8X24_UINT:
1060 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1061 return V_008F14_IMG_DATA_FORMAT_24_8;
1062 case PIPE_FORMAT_S8_UINT:
1063 return V_008F14_IMG_DATA_FORMAT_8;
1064 case PIPE_FORMAT_Z32_FLOAT:
1065 return V_008F14_IMG_DATA_FORMAT_32;
1066 case PIPE_FORMAT_X32_S8X24_UINT:
1067 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1068 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1069 default:
1070 goto out_unknown;
1071 }
1072
1073 case UTIL_FORMAT_COLORSPACE_YUV:
1074 goto out_unknown; /* TODO */
1075
1076 case UTIL_FORMAT_COLORSPACE_SRGB:
1077 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1078 goto out_unknown;
1079 break;
1080
1081 default:
1082 break;
1083 }
1084
1085 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1086 if (!enable_s3tc)
1087 goto out_unknown;
1088
1089 switch (format) {
1090 case PIPE_FORMAT_RGTC1_SNORM:
1091 case PIPE_FORMAT_LATC1_SNORM:
1092 case PIPE_FORMAT_RGTC1_UNORM:
1093 case PIPE_FORMAT_LATC1_UNORM:
1094 return V_008F14_IMG_DATA_FORMAT_BC4;
1095 case PIPE_FORMAT_RGTC2_SNORM:
1096 case PIPE_FORMAT_LATC2_SNORM:
1097 case PIPE_FORMAT_RGTC2_UNORM:
1098 case PIPE_FORMAT_LATC2_UNORM:
1099 return V_008F14_IMG_DATA_FORMAT_BC5;
1100 default:
1101 goto out_unknown;
1102 }
1103 }
1104
1105 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1106
1107 if (!enable_s3tc)
1108 goto out_unknown;
1109
1110 if (!util_format_s3tc_enabled) {
1111 goto out_unknown;
1112 }
1113
1114 switch (format) {
1115 case PIPE_FORMAT_DXT1_RGB:
1116 case PIPE_FORMAT_DXT1_RGBA:
1117 case PIPE_FORMAT_DXT1_SRGB:
1118 case PIPE_FORMAT_DXT1_SRGBA:
1119 return V_008F14_IMG_DATA_FORMAT_BC1;
1120 case PIPE_FORMAT_DXT3_RGBA:
1121 case PIPE_FORMAT_DXT3_SRGBA:
1122 return V_008F14_IMG_DATA_FORMAT_BC2;
1123 case PIPE_FORMAT_DXT5_RGBA:
1124 case PIPE_FORMAT_DXT5_SRGBA:
1125 return V_008F14_IMG_DATA_FORMAT_BC3;
1126 default:
1127 goto out_unknown;
1128 }
1129 }
1130
1131 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1132 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1133 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1134 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1135 }
1136
1137 /* R8G8Bx_SNORM - TODO CxV8U8 */
1138
1139 /* See whether the components are of the same size. */
1140 for (i = 1; i < desc->nr_channels; i++) {
1141 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1142 }
1143
1144 /* Non-uniform formats. */
1145 if (!uniform) {
1146 switch(desc->nr_channels) {
1147 case 3:
1148 if (desc->channel[0].size == 5 &&
1149 desc->channel[1].size == 6 &&
1150 desc->channel[2].size == 5) {
1151 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1152 }
1153 goto out_unknown;
1154 case 4:
1155 if (desc->channel[0].size == 5 &&
1156 desc->channel[1].size == 5 &&
1157 desc->channel[2].size == 5 &&
1158 desc->channel[3].size == 1) {
1159 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1160 }
1161 if (desc->channel[0].size == 10 &&
1162 desc->channel[1].size == 10 &&
1163 desc->channel[2].size == 10 &&
1164 desc->channel[3].size == 2) {
1165 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1166 }
1167 goto out_unknown;
1168 }
1169 goto out_unknown;
1170 }
1171
1172 if (first_non_void < 0 || first_non_void > 3)
1173 goto out_unknown;
1174
1175 /* uniform formats */
1176 switch (desc->channel[first_non_void].size) {
1177 case 4:
1178 switch (desc->nr_channels) {
1179 #if 0 /* Not supported for render targets */
1180 case 2:
1181 return V_008F14_IMG_DATA_FORMAT_4_4;
1182 #endif
1183 case 4:
1184 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1185 }
1186 break;
1187 case 8:
1188 switch (desc->nr_channels) {
1189 case 1:
1190 return V_008F14_IMG_DATA_FORMAT_8;
1191 case 2:
1192 return V_008F14_IMG_DATA_FORMAT_8_8;
1193 case 4:
1194 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1195 }
1196 break;
1197 case 16:
1198 switch (desc->nr_channels) {
1199 case 1:
1200 return V_008F14_IMG_DATA_FORMAT_16;
1201 case 2:
1202 return V_008F14_IMG_DATA_FORMAT_16_16;
1203 case 4:
1204 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1205 }
1206 break;
1207 case 32:
1208 switch (desc->nr_channels) {
1209 case 1:
1210 return V_008F14_IMG_DATA_FORMAT_32;
1211 case 2:
1212 return V_008F14_IMG_DATA_FORMAT_32_32;
1213 #if 0 /* Not supported for render targets */
1214 case 3:
1215 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1216 #endif
1217 case 4:
1218 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1219 }
1220 }
1221
1222 out_unknown:
1223 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1224 return ~0;
1225 }
1226
1227 static unsigned si_tex_wrap(unsigned wrap)
1228 {
1229 switch (wrap) {
1230 default:
1231 case PIPE_TEX_WRAP_REPEAT:
1232 return V_008F30_SQ_TEX_WRAP;
1233 case PIPE_TEX_WRAP_CLAMP:
1234 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1235 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1236 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1237 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1238 return V_008F30_SQ_TEX_CLAMP_BORDER;
1239 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1240 return V_008F30_SQ_TEX_MIRROR;
1241 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1242 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1243 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1244 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1245 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1246 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1247 }
1248 }
1249
1250 static unsigned si_tex_filter(unsigned filter)
1251 {
1252 switch (filter) {
1253 default:
1254 case PIPE_TEX_FILTER_NEAREST:
1255 return V_008F38_SQ_TEX_XY_FILTER_POINT;
1256 case PIPE_TEX_FILTER_LINEAR:
1257 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
1258 }
1259 }
1260
1261 static unsigned si_tex_mipfilter(unsigned filter)
1262 {
1263 switch (filter) {
1264 case PIPE_TEX_MIPFILTER_NEAREST:
1265 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1266 case PIPE_TEX_MIPFILTER_LINEAR:
1267 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1268 default:
1269 case PIPE_TEX_MIPFILTER_NONE:
1270 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1271 }
1272 }
1273
1274 static unsigned si_tex_compare(unsigned compare)
1275 {
1276 switch (compare) {
1277 default:
1278 case PIPE_FUNC_NEVER:
1279 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1280 case PIPE_FUNC_LESS:
1281 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1282 case PIPE_FUNC_EQUAL:
1283 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1284 case PIPE_FUNC_LEQUAL:
1285 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1286 case PIPE_FUNC_GREATER:
1287 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1288 case PIPE_FUNC_NOTEQUAL:
1289 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1290 case PIPE_FUNC_GEQUAL:
1291 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1292 case PIPE_FUNC_ALWAYS:
1293 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1294 }
1295 }
1296
1297 static unsigned si_tex_dim(unsigned dim, unsigned nr_samples)
1298 {
1299 switch (dim) {
1300 default:
1301 case PIPE_TEXTURE_1D:
1302 return V_008F1C_SQ_RSRC_IMG_1D;
1303 case PIPE_TEXTURE_1D_ARRAY:
1304 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1305 case PIPE_TEXTURE_2D:
1306 case PIPE_TEXTURE_RECT:
1307 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1308 V_008F1C_SQ_RSRC_IMG_2D;
1309 case PIPE_TEXTURE_2D_ARRAY:
1310 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1311 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1312 case PIPE_TEXTURE_3D:
1313 return V_008F1C_SQ_RSRC_IMG_3D;
1314 case PIPE_TEXTURE_CUBE:
1315 return V_008F1C_SQ_RSRC_IMG_CUBE;
1316 }
1317 }
1318
1319 /*
1320 * Format support testing
1321 */
1322
1323 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1324 {
1325 return si_translate_texformat(screen, format, util_format_description(format),
1326 util_format_get_first_non_void_channel(format)) != ~0U;
1327 }
1328
1329 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1330 const struct util_format_description *desc,
1331 int first_non_void)
1332 {
1333 unsigned type = desc->channel[first_non_void].type;
1334 int i;
1335
1336 if (type == UTIL_FORMAT_TYPE_FIXED)
1337 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1338
1339 if (desc->nr_channels == 4 &&
1340 desc->channel[0].size == 10 &&
1341 desc->channel[1].size == 10 &&
1342 desc->channel[2].size == 10 &&
1343 desc->channel[3].size == 2)
1344 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1345
1346 /* See whether the components are of the same size. */
1347 for (i = 0; i < desc->nr_channels; i++) {
1348 if (desc->channel[first_non_void].size != desc->channel[i].size)
1349 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1350 }
1351
1352 switch (desc->channel[first_non_void].size) {
1353 case 8:
1354 switch (desc->nr_channels) {
1355 case 1:
1356 return V_008F0C_BUF_DATA_FORMAT_8;
1357 case 2:
1358 return V_008F0C_BUF_DATA_FORMAT_8_8;
1359 case 3:
1360 case 4:
1361 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1362 }
1363 break;
1364 case 16:
1365 switch (desc->nr_channels) {
1366 case 1:
1367 return V_008F0C_BUF_DATA_FORMAT_16;
1368 case 2:
1369 return V_008F0C_BUF_DATA_FORMAT_16_16;
1370 case 3:
1371 case 4:
1372 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1373 }
1374 break;
1375 case 32:
1376 /* From the Southern Islands ISA documentation about MTBUF:
1377 * 'Memory reads of data in memory that is 32 or 64 bits do not
1378 * undergo any format conversion.'
1379 */
1380 if (type != UTIL_FORMAT_TYPE_FLOAT &&
1381 !desc->channel[first_non_void].pure_integer)
1382 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1383
1384 switch (desc->nr_channels) {
1385 case 1:
1386 return V_008F0C_BUF_DATA_FORMAT_32;
1387 case 2:
1388 return V_008F0C_BUF_DATA_FORMAT_32_32;
1389 case 3:
1390 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1391 case 4:
1392 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1393 }
1394 break;
1395 }
1396
1397 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1398 }
1399
1400 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1401 const struct util_format_description *desc,
1402 int first_non_void)
1403 {
1404 switch (desc->channel[first_non_void].type) {
1405 case UTIL_FORMAT_TYPE_SIGNED:
1406 if (desc->channel[first_non_void].normalized)
1407 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1408 else if (desc->channel[first_non_void].pure_integer)
1409 return V_008F0C_BUF_NUM_FORMAT_SINT;
1410 else
1411 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1412 break;
1413 case UTIL_FORMAT_TYPE_UNSIGNED:
1414 if (desc->channel[first_non_void].normalized)
1415 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1416 else if (desc->channel[first_non_void].pure_integer)
1417 return V_008F0C_BUF_NUM_FORMAT_UINT;
1418 else
1419 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1420 break;
1421 case UTIL_FORMAT_TYPE_FLOAT:
1422 default:
1423 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1424 }
1425 }
1426
1427 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
1428 {
1429 const struct util_format_description *desc;
1430 int first_non_void;
1431 unsigned data_format;
1432
1433 desc = util_format_description(format);
1434 first_non_void = util_format_get_first_non_void_channel(format);
1435 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1436 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
1437 }
1438
1439 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1440 {
1441 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1442 si_translate_colorswap(format) != ~0U;
1443 }
1444
1445 static bool si_is_zs_format_supported(enum pipe_format format)
1446 {
1447 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1448 }
1449
1450 boolean si_is_format_supported(struct pipe_screen *screen,
1451 enum pipe_format format,
1452 enum pipe_texture_target target,
1453 unsigned sample_count,
1454 unsigned usage)
1455 {
1456 struct r600_screen *rscreen = (struct r600_screen *)screen;
1457 unsigned retval = 0;
1458
1459 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1460 R600_ERR("r600: unsupported texture type %d\n", target);
1461 return FALSE;
1462 }
1463
1464 if (!util_format_is_supported(format, usage))
1465 return FALSE;
1466
1467 if (sample_count > 1) {
1468 if (HAVE_LLVM < 0x0304)
1469 return FALSE;
1470
1471 /* 2D tiling on CIK is supported since DRM 2.35.0 */
1472 if (rscreen->b.chip_class >= CIK && rscreen->b.info.drm_minor < 35)
1473 return FALSE;
1474
1475 switch (sample_count) {
1476 case 2:
1477 case 4:
1478 case 8:
1479 break;
1480 default:
1481 return FALSE;
1482 }
1483 }
1484
1485 if (usage & PIPE_BIND_SAMPLER_VIEW) {
1486 if (target == PIPE_BUFFER) {
1487 if (si_is_vertex_format_supported(screen, format))
1488 retval |= PIPE_BIND_SAMPLER_VIEW;
1489 } else {
1490 if (si_is_sampler_format_supported(screen, format))
1491 retval |= PIPE_BIND_SAMPLER_VIEW;
1492 }
1493 }
1494
1495 if ((usage & (PIPE_BIND_RENDER_TARGET |
1496 PIPE_BIND_DISPLAY_TARGET |
1497 PIPE_BIND_SCANOUT |
1498 PIPE_BIND_SHARED)) &&
1499 si_is_colorbuffer_format_supported(format)) {
1500 retval |= usage &
1501 (PIPE_BIND_RENDER_TARGET |
1502 PIPE_BIND_DISPLAY_TARGET |
1503 PIPE_BIND_SCANOUT |
1504 PIPE_BIND_SHARED);
1505 }
1506
1507 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1508 si_is_zs_format_supported(format)) {
1509 retval |= PIPE_BIND_DEPTH_STENCIL;
1510 }
1511
1512 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
1513 si_is_vertex_format_supported(screen, format)) {
1514 retval |= PIPE_BIND_VERTEX_BUFFER;
1515 }
1516
1517 if (usage & PIPE_BIND_TRANSFER_READ)
1518 retval |= PIPE_BIND_TRANSFER_READ;
1519 if (usage & PIPE_BIND_TRANSFER_WRITE)
1520 retval |= PIPE_BIND_TRANSFER_WRITE;
1521
1522 return retval == usage;
1523 }
1524
1525 static unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
1526 {
1527 unsigned tile_mode_index = 0;
1528
1529 if (stencil) {
1530 tile_mode_index = rtex->surface.stencil_tiling_index[level];
1531 } else {
1532 tile_mode_index = rtex->surface.tiling_index[level];
1533 }
1534 return tile_mode_index;
1535 }
1536
1537 /*
1538 * framebuffer handling
1539 */
1540
1541 static void si_cb(struct r600_context *rctx, struct si_pm4_state *pm4,
1542 const struct pipe_framebuffer_state *state, int cb)
1543 {
1544 struct r600_texture *rtex;
1545 struct r600_surface *surf;
1546 unsigned level = state->cbufs[cb]->u.tex.level;
1547 unsigned pitch, slice;
1548 unsigned color_info, color_attrib, color_pitch, color_view;
1549 unsigned tile_mode_index;
1550 unsigned format, swap, ntype, endian;
1551 uint64_t offset;
1552 const struct util_format_description *desc;
1553 int i;
1554 unsigned blend_clamp = 0, blend_bypass = 0;
1555 unsigned max_comp_size;
1556
1557 surf = (struct r600_surface *)state->cbufs[cb];
1558 rtex = (struct r600_texture*)state->cbufs[cb]->texture;
1559
1560 offset = rtex->surface.level[level].offset;
1561
1562 /* Layered rendering doesn't work with LINEAR_GENERAL.
1563 * (LINEAR_ALIGNED and others work) */
1564 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) {
1565 assert(state->cbufs[cb]->u.tex.first_layer == state->cbufs[cb]->u.tex.last_layer);
1566 offset += rtex->surface.level[level].slice_size *
1567 state->cbufs[cb]->u.tex.first_layer;
1568 color_view = 0;
1569 } else {
1570 color_view = S_028C6C_SLICE_START(state->cbufs[cb]->u.tex.first_layer) |
1571 S_028C6C_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer);
1572 }
1573
1574 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1575 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1576 if (slice) {
1577 slice = slice - 1;
1578 }
1579
1580 tile_mode_index = si_tile_mode_index(rtex, level, false);
1581
1582 desc = util_format_description(surf->base.format);
1583 for (i = 0; i < 4; i++) {
1584 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1585 break;
1586 }
1587 }
1588 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1589 ntype = V_028C70_NUMBER_FLOAT;
1590 } else {
1591 ntype = V_028C70_NUMBER_UNORM;
1592 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1593 ntype = V_028C70_NUMBER_SRGB;
1594 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1595 if (desc->channel[i].pure_integer) {
1596 ntype = V_028C70_NUMBER_SINT;
1597 } else {
1598 assert(desc->channel[i].normalized);
1599 ntype = V_028C70_NUMBER_SNORM;
1600 }
1601 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1602 if (desc->channel[i].pure_integer) {
1603 ntype = V_028C70_NUMBER_UINT;
1604 } else {
1605 assert(desc->channel[i].normalized);
1606 ntype = V_028C70_NUMBER_UNORM;
1607 }
1608 }
1609 }
1610
1611 format = si_translate_colorformat(surf->base.format);
1612 if (format == V_028C70_COLOR_INVALID) {
1613 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
1614 }
1615 assert(format != V_028C70_COLOR_INVALID);
1616 swap = si_translate_colorswap(surf->base.format);
1617 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1618 endian = V_028C70_ENDIAN_NONE;
1619 } else {
1620 endian = si_colorformat_endian_swap(format);
1621 }
1622
1623 /* blend clamp should be set for all NORM/SRGB types */
1624 if (ntype == V_028C70_NUMBER_UNORM ||
1625 ntype == V_028C70_NUMBER_SNORM ||
1626 ntype == V_028C70_NUMBER_SRGB)
1627 blend_clamp = 1;
1628
1629 /* set blend bypass according to docs if SINT/UINT or
1630 8/24 COLOR variants */
1631 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1632 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1633 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1634 blend_clamp = 0;
1635 blend_bypass = 1;
1636 }
1637
1638 color_info = S_028C70_FORMAT(format) |
1639 S_028C70_COMP_SWAP(swap) |
1640 S_028C70_BLEND_CLAMP(blend_clamp) |
1641 S_028C70_BLEND_BYPASS(blend_bypass) |
1642 S_028C70_NUMBER_TYPE(ntype) |
1643 S_028C70_ENDIAN(endian);
1644
1645 color_pitch = S_028C64_TILE_MAX(pitch);
1646
1647 color_attrib = S_028C74_TILE_MODE_INDEX(tile_mode_index) |
1648 S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == UTIL_FORMAT_SWIZZLE_1);
1649
1650 if (rtex->resource.b.b.nr_samples > 1) {
1651 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1652
1653 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1654 S_028C74_NUM_FRAGMENTS(log_samples);
1655
1656 if (rtex->fmask.size) {
1657 color_info |= S_028C70_COMPRESSION(1);
1658 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
1659
1660 color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(rtex->fmask.tile_mode_index);
1661
1662 if (rctx->b.chip_class == SI) {
1663 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
1664 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1665 }
1666 if (rctx->b.chip_class >= CIK) {
1667 color_pitch |= S_028C64_FMASK_TILE_MAX(rtex->fmask.pitch / 8 - 1);
1668 }
1669 }
1670 }
1671
1672 if (rtex->cmask.size) {
1673 color_info |= S_028C70_FAST_CLEAR(1);
1674 }
1675
1676 offset += r600_resource_va(rctx->b.b.screen, state->cbufs[cb]->texture);
1677 offset >>= 8;
1678
1679 si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE);
1680 si_pm4_set_reg(pm4, R_028C60_CB_COLOR0_BASE + cb * 0x3C, offset);
1681 si_pm4_set_reg(pm4, R_028C64_CB_COLOR0_PITCH + cb * 0x3C, color_pitch);
1682 si_pm4_set_reg(pm4, R_028C68_CB_COLOR0_SLICE + cb * 0x3C, S_028C68_TILE_MAX(slice));
1683 si_pm4_set_reg(pm4, R_028C6C_CB_COLOR0_VIEW + cb * 0x3C, color_view);
1684 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + cb * 0x3C, color_info);
1685 si_pm4_set_reg(pm4, R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C, color_attrib);
1686
1687 if (rtex->cmask.size) {
1688 si_pm4_set_reg(pm4, R_028C7C_CB_COLOR0_CMASK + cb * 0x3C,
1689 offset + (rtex->cmask.offset >> 8));
1690 si_pm4_set_reg(pm4, R_028C80_CB_COLOR0_CMASK_SLICE + cb * 0x3C,
1691 S_028C80_TILE_MAX(rtex->cmask.slice_tile_max));
1692 }
1693 if (rtex->fmask.size) {
1694 si_pm4_set_reg(pm4, R_028C84_CB_COLOR0_FMASK + cb * 0x3C,
1695 offset + (rtex->fmask.offset >> 8));
1696 si_pm4_set_reg(pm4, R_028C88_CB_COLOR0_FMASK_SLICE + cb * 0x3C,
1697 S_028C88_TILE_MAX(rtex->fmask.slice_tile_max));
1698 }
1699
1700 /* set CB_COLOR1_INFO for possible dual-src blending */
1701 if (state->nr_cbufs == 1) {
1702 assert(cb == 0);
1703 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + 1 * 0x3C, color_info);
1704 }
1705
1706 /* Determine pixel shader export format */
1707 max_comp_size = si_colorformat_max_comp_size(format);
1708 if (ntype == V_028C70_NUMBER_SRGB ||
1709 ((ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM) &&
1710 max_comp_size <= 10) ||
1711 (ntype == V_028C70_NUMBER_FLOAT && max_comp_size <= 16)) {
1712 rctx->export_16bpc |= 1 << cb;
1713 /* set SPI_SHADER_COL_FORMAT for possible dual-src blending */
1714 if (state->nr_cbufs == 1)
1715 rctx->export_16bpc |= 1 << 1;
1716 }
1717 }
1718
1719 static void si_db(struct r600_context *rctx, struct si_pm4_state *pm4,
1720 const struct pipe_framebuffer_state *state)
1721 {
1722 struct r600_screen *rscreen = rctx->screen;
1723 struct r600_texture *rtex;
1724 struct r600_surface *surf;
1725 unsigned level, pitch, slice, format, tile_mode_index, array_mode;
1726 unsigned macro_aspect, tile_split, stile_split, bankh, bankw, nbanks, pipe_config;
1727 uint32_t z_info, s_info, db_depth_info;
1728 uint64_t z_offs, s_offs;
1729 uint32_t db_htile_data_base, db_htile_surface;
1730
1731 if (state->zsbuf == NULL) {
1732 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, S_028040_FORMAT(V_028040_Z_INVALID));
1733 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, S_028044_FORMAT(V_028044_STENCIL_INVALID));
1734 return;
1735 }
1736
1737 surf = (struct r600_surface *)state->zsbuf;
1738 level = surf->base.u.tex.level;
1739 rtex = (struct r600_texture*)surf->base.texture;
1740
1741 format = si_translate_dbformat(rtex->resource.b.b.format);
1742
1743 if (format == V_028040_Z_INVALID) {
1744 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
1745 }
1746 assert(format != V_028040_Z_INVALID);
1747
1748 s_offs = z_offs = r600_resource_va(rctx->b.b.screen, surf->base.texture);
1749 z_offs += rtex->surface.level[level].offset;
1750 s_offs += rtex->surface.stencil_level[level].offset;
1751
1752 z_offs >>= 8;
1753 s_offs >>= 8;
1754
1755 pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
1756 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1757 if (slice) {
1758 slice = slice - 1;
1759 }
1760
1761 db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
1762
1763 z_info = S_028040_FORMAT(format);
1764 if (rtex->resource.b.b.nr_samples > 1) {
1765 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
1766 }
1767
1768 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
1769 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
1770 else
1771 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
1772
1773 if (rctx->b.chip_class >= CIK) {
1774 switch (rtex->surface.level[level].mode) {
1775 case RADEON_SURF_MODE_2D:
1776 array_mode = V_02803C_ARRAY_2D_TILED_THIN1;
1777 break;
1778 case RADEON_SURF_MODE_1D:
1779 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1780 case RADEON_SURF_MODE_LINEAR:
1781 default:
1782 array_mode = V_02803C_ARRAY_1D_TILED_THIN1;
1783 break;
1784 }
1785 tile_split = rtex->surface.tile_split;
1786 stile_split = rtex->surface.stencil_tile_split;
1787 macro_aspect = rtex->surface.mtilea;
1788 bankw = rtex->surface.bankw;
1789 bankh = rtex->surface.bankh;
1790 tile_split = cik_tile_split(tile_split);
1791 stile_split = cik_tile_split(stile_split);
1792 macro_aspect = cik_macro_tile_aspect(macro_aspect);
1793 bankw = cik_bank_wh(bankw);
1794 bankh = cik_bank_wh(bankh);
1795 nbanks = cik_num_banks(rscreen->b.tiling_info.num_banks);
1796 pipe_config = cik_db_pipe_config(rscreen->b.info.r600_num_tile_pipes,
1797 rscreen->b.info.r600_num_backends);
1798
1799 db_depth_info |= S_02803C_ARRAY_MODE(array_mode) |
1800 S_02803C_PIPE_CONFIG(pipe_config) |
1801 S_02803C_BANK_WIDTH(bankw) |
1802 S_02803C_BANK_HEIGHT(bankh) |
1803 S_02803C_MACRO_TILE_ASPECT(macro_aspect) |
1804 S_02803C_NUM_BANKS(nbanks);
1805 z_info |= S_028040_TILE_SPLIT(tile_split);
1806 s_info |= S_028044_TILE_SPLIT(stile_split);
1807 } else {
1808 tile_mode_index = si_tile_mode_index(rtex, level, false);
1809 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
1810 tile_mode_index = si_tile_mode_index(rtex, level, true);
1811 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
1812 }
1813
1814 /* HiZ aka depth buffer htile */
1815 /* use htile only for first level */
1816 if (rtex->htile_buffer && !level) {
1817 z_info |= S_028040_TILE_SURFACE_ENABLE(1);
1818
1819 /* This is optimal for the clear value of 1.0 and using
1820 * the LESS and LEQUAL test functions. Set this to 0
1821 * for the opposite case. This can only be changed when
1822 * clearing. */
1823 z_info |= S_028040_ZRANGE_PRECISION(1);
1824
1825 uint64_t va = r600_resource_va(&rctx->screen->b.b, &rtex->htile_buffer->b.b);
1826 db_htile_data_base = va >> 8;
1827 db_htile_surface = S_028ABC_FULL_CACHE(1);
1828
1829 si_pm4_add_bo(pm4, rtex->htile_buffer, RADEON_USAGE_READWRITE);
1830 } else {
1831 db_htile_data_base = 0;
1832 db_htile_surface = 0;
1833 }
1834
1835 si_pm4_set_reg(pm4, R_028008_DB_DEPTH_VIEW,
1836 S_028008_SLICE_START(state->zsbuf->u.tex.first_layer) |
1837 S_028008_SLICE_MAX(state->zsbuf->u.tex.last_layer));
1838 si_pm4_set_reg(pm4, R_028014_DB_HTILE_DATA_BASE, db_htile_data_base);
1839
1840 si_pm4_set_reg(pm4, R_02803C_DB_DEPTH_INFO, db_depth_info);
1841 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, z_info);
1842 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, s_info);
1843
1844 si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE);
1845 si_pm4_set_reg(pm4, R_028048_DB_Z_READ_BASE, z_offs);
1846 si_pm4_set_reg(pm4, R_02804C_DB_STENCIL_READ_BASE, s_offs);
1847 si_pm4_set_reg(pm4, R_028050_DB_Z_WRITE_BASE, z_offs);
1848 si_pm4_set_reg(pm4, R_028054_DB_STENCIL_WRITE_BASE, s_offs);
1849
1850 si_pm4_set_reg(pm4, R_028058_DB_DEPTH_SIZE, S_028058_PITCH_TILE_MAX(pitch));
1851 si_pm4_set_reg(pm4, R_02805C_DB_DEPTH_SLICE, S_02805C_SLICE_TILE_MAX(slice));
1852
1853 si_pm4_set_reg(pm4, R_028ABC_DB_HTILE_SURFACE, db_htile_surface);
1854 }
1855
1856 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1857 (((s0x) & 0xf) | (((s0y) & 0xf) << 4) | \
1858 (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) | \
1859 (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) | \
1860 (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
1861
1862 /* 2xMSAA
1863 * There are two locations (-4, 4), (4, -4). */
1864 static uint32_t sample_locs_2x[] = {
1865 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1866 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1867 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1868 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1869 };
1870 static unsigned max_dist_2x = 4;
1871 /* 4xMSAA
1872 * There are 4 locations: (-2, -2), (2, 2), (-6, 6), (6, -6). */
1873 static uint32_t sample_locs_4x[] = {
1874 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1875 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1876 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1877 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1878 };
1879 static unsigned max_dist_4x = 6;
1880 /* Cayman/SI 8xMSAA */
1881 static uint32_t cm_sample_locs_8x[] = {
1882 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1883 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1884 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1885 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1886 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1887 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1888 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1889 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1890 };
1891 static unsigned cm_max_dist_8x = 8;
1892 /* Cayman/SI 16xMSAA */
1893 static uint32_t cm_sample_locs_16x[] = {
1894 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1895 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1896 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1897 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1898 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1899 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1900 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1901 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1902 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1903 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1904 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1905 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1906 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1907 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1908 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1909 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1910 };
1911 static unsigned cm_max_dist_16x = 8;
1912
1913 static void si_get_sample_position(struct pipe_context *ctx,
1914 unsigned sample_count,
1915 unsigned sample_index,
1916 float *out_value)
1917 {
1918 int offset, index;
1919 struct {
1920 int idx:4;
1921 } val;
1922 switch (sample_count) {
1923 case 1:
1924 default:
1925 out_value[0] = out_value[1] = 0.5;
1926 break;
1927 case 2:
1928 offset = 4 * (sample_index * 2);
1929 val.idx = (sample_locs_2x[0] >> offset) & 0xf;
1930 out_value[0] = (float)(val.idx + 8) / 16.0f;
1931 val.idx = (sample_locs_2x[0] >> (offset + 4)) & 0xf;
1932 out_value[1] = (float)(val.idx + 8) / 16.0f;
1933 break;
1934 case 4:
1935 offset = 4 * (sample_index * 2);
1936 val.idx = (sample_locs_4x[0] >> offset) & 0xf;
1937 out_value[0] = (float)(val.idx + 8) / 16.0f;
1938 val.idx = (sample_locs_4x[0] >> (offset + 4)) & 0xf;
1939 out_value[1] = (float)(val.idx + 8) / 16.0f;
1940 break;
1941 case 8:
1942 offset = 4 * (sample_index % 4 * 2);
1943 index = (sample_index / 4) * 4;
1944 val.idx = (cm_sample_locs_8x[index] >> offset) & 0xf;
1945 out_value[0] = (float)(val.idx + 8) / 16.0f;
1946 val.idx = (cm_sample_locs_8x[index] >> (offset + 4)) & 0xf;
1947 out_value[1] = (float)(val.idx + 8) / 16.0f;
1948 break;
1949 case 16:
1950 offset = 4 * (sample_index % 4 * 2);
1951 index = (sample_index / 4) * 4;
1952 val.idx = (cm_sample_locs_16x[index] >> offset) & 0xf;
1953 out_value[0] = (float)(val.idx + 8) / 16.0f;
1954 val.idx = (cm_sample_locs_16x[index] >> (offset + 4)) & 0xf;
1955 out_value[1] = (float)(val.idx + 8) / 16.0f;
1956 break;
1957 }
1958 }
1959
1960 static void si_set_msaa_state(struct r600_context *rctx, struct si_pm4_state *pm4, int nr_samples)
1961 {
1962 unsigned max_dist = 0;
1963
1964 switch (nr_samples) {
1965 default:
1966 nr_samples = 0;
1967 break;
1968 case 2:
1969 si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_2x[0]);
1970 si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_2x[1]);
1971 si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_2x[2]);
1972 si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_2x[3]);
1973 max_dist = max_dist_2x;
1974 break;
1975 case 4:
1976 si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_4x[0]);
1977 si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_4x[1]);
1978 si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_4x[2]);
1979 si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_4x[3]);
1980 max_dist = max_dist_4x;
1981 break;
1982 case 8:
1983 si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, cm_sample_locs_8x[0]);
1984 si_pm4_set_reg(pm4, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, cm_sample_locs_8x[4]);
1985 si_pm4_set_reg(pm4, R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2, 0);
1986 si_pm4_set_reg(pm4, R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3, 0);
1987 si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, cm_sample_locs_8x[1]);
1988 si_pm4_set_reg(pm4, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, cm_sample_locs_8x[5]);
1989 si_pm4_set_reg(pm4, R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2, 0);
1990 si_pm4_set_reg(pm4, R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3, 0);
1991 si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, cm_sample_locs_8x[2]);
1992 si_pm4_set_reg(pm4, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, cm_sample_locs_8x[6]);
1993 si_pm4_set_reg(pm4, R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2, 0);
1994 si_pm4_set_reg(pm4, R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3, 0);
1995 si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, cm_sample_locs_8x[3]);
1996 si_pm4_set_reg(pm4, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, cm_sample_locs_8x[7]);
1997 max_dist = cm_max_dist_8x;
1998 break;
1999 case 16:
2000 si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, cm_sample_locs_16x[0]);
2001 si_pm4_set_reg(pm4, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, cm_sample_locs_16x[4]);
2002 si_pm4_set_reg(pm4, R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2, cm_sample_locs_16x[8]);
2003 si_pm4_set_reg(pm4, R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3, cm_sample_locs_16x[12]);
2004 si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, cm_sample_locs_16x[1]);
2005 si_pm4_set_reg(pm4, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, cm_sample_locs_16x[5]);
2006 si_pm4_set_reg(pm4, R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2, cm_sample_locs_16x[9]);
2007 si_pm4_set_reg(pm4, R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3, cm_sample_locs_16x[13]);
2008 si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, cm_sample_locs_16x[2]);
2009 si_pm4_set_reg(pm4, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, cm_sample_locs_16x[6]);
2010 si_pm4_set_reg(pm4, R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2, cm_sample_locs_16x[10]);
2011 si_pm4_set_reg(pm4, R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3, cm_sample_locs_16x[14]);
2012 si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, cm_sample_locs_16x[3]);
2013 si_pm4_set_reg(pm4, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, cm_sample_locs_16x[7]);
2014 si_pm4_set_reg(pm4, R_028C30_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2, cm_sample_locs_16x[11]);
2015 si_pm4_set_reg(pm4, R_028C34_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3, cm_sample_locs_16x[15]);
2016 max_dist = cm_max_dist_16x;
2017 break;
2018 }
2019
2020 if (nr_samples > 1) {
2021 unsigned log_samples = util_logbase2(nr_samples);
2022
2023 si_pm4_set_reg(pm4, R_028BDC_PA_SC_LINE_CNTL,
2024 S_028BDC_LAST_PIXEL(1) |
2025 S_028BDC_EXPAND_LINE_WIDTH(1));
2026 si_pm4_set_reg(pm4, R_028BE0_PA_SC_AA_CONFIG,
2027 S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
2028 S_028BE0_MAX_SAMPLE_DIST(max_dist) |
2029 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples));
2030
2031 si_pm4_set_reg(pm4, R_028804_DB_EQAA,
2032 S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
2033 S_028804_PS_ITER_SAMPLES(log_samples) |
2034 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
2035 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples) |
2036 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
2037 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
2038 } else {
2039 si_pm4_set_reg(pm4, R_028BDC_PA_SC_LINE_CNTL, S_028BDC_LAST_PIXEL(1));
2040 si_pm4_set_reg(pm4, R_028BE0_PA_SC_AA_CONFIG, 0);
2041
2042 si_pm4_set_reg(pm4, R_028804_DB_EQAA,
2043 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
2044 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
2045 }
2046 }
2047
2048 static void si_set_framebuffer_state(struct pipe_context *ctx,
2049 const struct pipe_framebuffer_state *state)
2050 {
2051 struct r600_context *rctx = (struct r600_context *)ctx;
2052 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
2053 uint32_t tl, br;
2054 int tl_x, tl_y, br_x, br_y, nr_samples, i;
2055
2056 if (pm4 == NULL)
2057 return;
2058
2059 if (rctx->framebuffer.nr_cbufs) {
2060 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB |
2061 R600_CONTEXT_FLUSH_AND_INV_CB_META;
2062 }
2063 if (rctx->framebuffer.zsbuf) {
2064 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB |
2065 R600_CONTEXT_FLUSH_AND_INV_DB_META;
2066 }
2067
2068 util_copy_framebuffer_state(&rctx->framebuffer, state);
2069
2070 /* build states */
2071 rctx->export_16bpc = 0;
2072 rctx->fb_compressed_cb_mask = 0;
2073 for (i = 0; i < state->nr_cbufs; i++) {
2074 struct r600_texture *rtex =
2075 (struct r600_texture*)state->cbufs[i]->texture;
2076
2077 si_cb(rctx, pm4, state, i);
2078
2079 if (rtex->fmask.size || rtex->cmask.size) {
2080 rctx->fb_compressed_cb_mask |= 1 << i;
2081 }
2082 }
2083 for (; i < 8; i++) {
2084 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2085 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2086 }
2087
2088 assert(!(rctx->export_16bpc & ~0xff));
2089 si_db(rctx, pm4, state);
2090
2091 tl_x = 0;
2092 tl_y = 0;
2093 br_x = state->width;
2094 br_y = state->height;
2095
2096 tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
2097 br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
2098
2099 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, tl);
2100 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR, br);
2101 si_pm4_set_reg(pm4, R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl);
2102 si_pm4_set_reg(pm4, R_028254_PA_SC_VPORT_SCISSOR_0_BR, br);
2103 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, tl);
2104 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR, br);
2105 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, tl);
2106 si_pm4_set_reg(pm4, R_028208_PA_SC_WINDOW_SCISSOR_BR, br);
2107
2108 if (state->nr_cbufs)
2109 nr_samples = state->cbufs[0]->texture->nr_samples;
2110 else if (state->zsbuf)
2111 nr_samples = state->zsbuf->texture->nr_samples;
2112 else
2113 nr_samples = 0;
2114
2115 si_set_msaa_state(rctx, pm4, nr_samples);
2116 rctx->fb_log_samples = util_logbase2(nr_samples);
2117 rctx->fb_cb0_is_integer = state->nr_cbufs &&
2118 util_format_is_pure_integer(state->cbufs[0]->format);
2119
2120 si_pm4_set_state(rctx, framebuffer, pm4);
2121 si_update_fb_rs_state(rctx);
2122 si_update_fb_blend_state(rctx);
2123 }
2124
2125 /*
2126 * shaders
2127 */
2128
2129 /* Compute the key for the hw shader variant */
2130 static INLINE void si_shader_selector_key(struct pipe_context *ctx,
2131 struct si_pipe_shader_selector *sel,
2132 union si_shader_key *key)
2133 {
2134 struct r600_context *rctx = (struct r600_context *)ctx;
2135 memset(key, 0, sizeof(*key));
2136
2137 if (sel->type == PIPE_SHADER_VERTEX) {
2138 unsigned i;
2139 if (!rctx->vertex_elements)
2140 return;
2141
2142 for (i = 0; i < rctx->vertex_elements->count; ++i)
2143 key->vs.instance_divisors[i] = rctx->vertex_elements->elements[i].instance_divisor;
2144
2145 if (rctx->queued.named.rasterizer->clip_plane_enable & 0xf0)
2146 key->vs.ucps_enabled |= 0x2;
2147 if (rctx->queued.named.rasterizer->clip_plane_enable & 0xf)
2148 key->vs.ucps_enabled |= 0x1;
2149 } else if (sel->type == PIPE_SHADER_FRAGMENT) {
2150 if (sel->fs_write_all)
2151 key->ps.nr_cbufs = rctx->framebuffer.nr_cbufs;
2152 key->ps.export_16bpc = rctx->export_16bpc;
2153
2154 if (rctx->queued.named.rasterizer) {
2155 key->ps.color_two_side = rctx->queued.named.rasterizer->two_side;
2156 key->ps.flatshade = rctx->queued.named.rasterizer->flatshade;
2157
2158 if (rctx->queued.named.blend) {
2159 key->ps.alpha_to_one = rctx->queued.named.blend->alpha_to_one &&
2160 rctx->queued.named.rasterizer->multisample_enable &&
2161 !rctx->fb_cb0_is_integer;
2162 }
2163 }
2164 if (rctx->queued.named.dsa) {
2165 key->ps.alpha_func = rctx->queued.named.dsa->alpha_func;
2166
2167 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
2168 if (rctx->framebuffer.nr_cbufs &&
2169 rctx->framebuffer.cbufs[0] &&
2170 util_format_is_pure_integer(rctx->framebuffer.cbufs[0]->texture->format))
2171 key->ps.alpha_func = PIPE_FUNC_ALWAYS;
2172 } else {
2173 key->ps.alpha_func = PIPE_FUNC_ALWAYS;
2174 }
2175 }
2176 }
2177
2178 /* Select the hw shader variant depending on the current state.
2179 * (*dirty) is set to 1 if current variant was changed */
2180 int si_shader_select(struct pipe_context *ctx,
2181 struct si_pipe_shader_selector *sel,
2182 unsigned *dirty)
2183 {
2184 union si_shader_key key;
2185 struct si_pipe_shader * shader = NULL;
2186 int r;
2187
2188 si_shader_selector_key(ctx, sel, &key);
2189
2190 /* Check if we don't need to change anything.
2191 * This path is also used for most shaders that don't need multiple
2192 * variants, it will cost just a computation of the key and this
2193 * test. */
2194 if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
2195 return 0;
2196 }
2197
2198 /* lookup if we have other variants in the list */
2199 if (sel->num_shaders > 1) {
2200 struct si_pipe_shader *p = sel->current, *c = p->next_variant;
2201
2202 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
2203 p = c;
2204 c = c->next_variant;
2205 }
2206
2207 if (c) {
2208 p->next_variant = c->next_variant;
2209 shader = c;
2210 }
2211 }
2212
2213 if (unlikely(!shader)) {
2214 shader = CALLOC(1, sizeof(struct si_pipe_shader));
2215 shader->selector = sel;
2216 shader->key = key;
2217
2218 r = si_pipe_shader_create(ctx, shader);
2219 if (unlikely(r)) {
2220 R600_ERR("Failed to build shader variant (type=%u) %d\n",
2221 sel->type, r);
2222 sel->current = NULL;
2223 FREE(shader);
2224 return r;
2225 }
2226 sel->num_shaders++;
2227 }
2228
2229 if (dirty)
2230 *dirty = 1;
2231
2232 shader->next_variant = sel->current;
2233 sel->current = shader;
2234
2235 return 0;
2236 }
2237
2238 static void *si_create_shader_state(struct pipe_context *ctx,
2239 const struct pipe_shader_state *state,
2240 unsigned pipe_shader_type)
2241 {
2242 struct si_pipe_shader_selector *sel = CALLOC_STRUCT(si_pipe_shader_selector);
2243 int r;
2244 struct tgsi_shader_info info;
2245
2246 tgsi_scan_shader(state->tokens, &info);
2247
2248 sel->type = pipe_shader_type;
2249 sel->tokens = tgsi_dup_tokens(state->tokens);
2250 sel->so = state->stream_output;
2251 sel->fs_write_all = info.color0_writes_all_cbufs;
2252
2253 r = si_shader_select(ctx, sel, NULL);
2254 if (r) {
2255 free(sel);
2256 return NULL;
2257 }
2258
2259 return sel;
2260 }
2261
2262 static void *si_create_fs_state(struct pipe_context *ctx,
2263 const struct pipe_shader_state *state)
2264 {
2265 return si_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
2266 }
2267
2268 static void *si_create_vs_state(struct pipe_context *ctx,
2269 const struct pipe_shader_state *state)
2270 {
2271 return si_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
2272 }
2273
2274 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
2275 {
2276 struct r600_context *rctx = (struct r600_context *)ctx;
2277 struct si_pipe_shader_selector *sel = state;
2278
2279 if (rctx->vs_shader == sel)
2280 return;
2281
2282 if (!sel || !sel->current)
2283 return;
2284
2285 rctx->vs_shader = sel;
2286 si_pm4_bind_state(rctx, vs, sel->current->pm4);
2287 rctx->b.streamout.stride_in_dw = sel->so.stride;
2288 rctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE;
2289 }
2290
2291 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
2292 {
2293 struct r600_context *rctx = (struct r600_context *)ctx;
2294 struct si_pipe_shader_selector *sel = state;
2295
2296 if (rctx->ps_shader == sel)
2297 return;
2298
2299 if (!sel || !sel->current)
2300 sel = rctx->dummy_pixel_shader;
2301
2302 rctx->ps_shader = sel;
2303 si_pm4_bind_state(rctx, ps, sel->current->pm4);
2304 rctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE;
2305 }
2306
2307 static void si_delete_shader_selector(struct pipe_context *ctx,
2308 struct si_pipe_shader_selector *sel)
2309 {
2310 struct r600_context *rctx = (struct r600_context *)ctx;
2311 struct si_pipe_shader *p = sel->current, *c;
2312
2313 while (p) {
2314 c = p->next_variant;
2315 si_pm4_delete_state(rctx, vs, p->pm4);
2316 si_pipe_shader_destroy(ctx, p);
2317 free(p);
2318 p = c;
2319 }
2320
2321 free(sel->tokens);
2322 free(sel);
2323 }
2324
2325 static void si_delete_vs_shader(struct pipe_context *ctx, void *state)
2326 {
2327 struct r600_context *rctx = (struct r600_context *)ctx;
2328 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state;
2329
2330 if (rctx->vs_shader == sel) {
2331 rctx->vs_shader = NULL;
2332 }
2333
2334 si_delete_shader_selector(ctx, sel);
2335 }
2336
2337 static void si_delete_ps_shader(struct pipe_context *ctx, void *state)
2338 {
2339 struct r600_context *rctx = (struct r600_context *)ctx;
2340 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state;
2341
2342 if (rctx->ps_shader == sel) {
2343 rctx->ps_shader = NULL;
2344 }
2345
2346 si_delete_shader_selector(ctx, sel);
2347 }
2348
2349 /*
2350 * Samplers
2351 */
2352
2353 static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx,
2354 struct pipe_resource *texture,
2355 const struct pipe_sampler_view *state)
2356 {
2357 struct si_pipe_sampler_view *view = CALLOC_STRUCT(si_pipe_sampler_view);
2358 struct r600_texture *tmp = (struct r600_texture*)texture;
2359 const struct util_format_description *desc;
2360 unsigned format, num_format;
2361 uint32_t pitch = 0;
2362 unsigned char state_swizzle[4], swizzle[4];
2363 unsigned height, depth, width;
2364 enum pipe_format pipe_format = state->format;
2365 struct radeon_surface_level *surflevel;
2366 int first_non_void;
2367 uint64_t va;
2368
2369 if (view == NULL)
2370 return NULL;
2371
2372 /* initialize base object */
2373 view->base = *state;
2374 view->base.texture = NULL;
2375 pipe_resource_reference(&view->base.texture, texture);
2376 view->base.reference.count = 1;
2377 view->base.context = ctx;
2378 view->resource = &tmp->resource;
2379
2380 /* Buffer resource. */
2381 if (texture->target == PIPE_BUFFER) {
2382 unsigned stride;
2383
2384 desc = util_format_description(state->format);
2385 first_non_void = util_format_get_first_non_void_channel(state->format);
2386 stride = desc->block.bits / 8;
2387 va = r600_resource_va(ctx->screen, texture) + state->u.buf.first_element*stride;
2388 format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
2389 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
2390
2391 view->state[0] = va;
2392 view->state[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
2393 S_008F04_STRIDE(stride);
2394 view->state[2] = state->u.buf.last_element + 1 - state->u.buf.first_element;
2395 view->state[3] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2396 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2397 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2398 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2399 S_008F0C_NUM_FORMAT(num_format) |
2400 S_008F0C_DATA_FORMAT(format);
2401 return &view->base;
2402 }
2403
2404 state_swizzle[0] = state->swizzle_r;
2405 state_swizzle[1] = state->swizzle_g;
2406 state_swizzle[2] = state->swizzle_b;
2407 state_swizzle[3] = state->swizzle_a;
2408
2409 surflevel = tmp->surface.level;
2410
2411 /* Texturing with separate depth and stencil. */
2412 if (tmp->is_depth && !tmp->is_flushing_texture) {
2413 switch (pipe_format) {
2414 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2415 pipe_format = PIPE_FORMAT_Z32_FLOAT;
2416 break;
2417 case PIPE_FORMAT_X8Z24_UNORM:
2418 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2419 /* Z24 is always stored like this. */
2420 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
2421 break;
2422 case PIPE_FORMAT_X24S8_UINT:
2423 case PIPE_FORMAT_S8X24_UINT:
2424 case PIPE_FORMAT_X32_S8X24_UINT:
2425 pipe_format = PIPE_FORMAT_S8_UINT;
2426 surflevel = tmp->surface.stencil_level;
2427 break;
2428 default:;
2429 }
2430 }
2431
2432 desc = util_format_description(pipe_format);
2433
2434 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2435 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2436 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2437
2438 switch (pipe_format) {
2439 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2440 case PIPE_FORMAT_X24S8_UINT:
2441 case PIPE_FORMAT_X32_S8X24_UINT:
2442 case PIPE_FORMAT_X8Z24_UNORM:
2443 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
2444 break;
2445 default:
2446 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
2447 }
2448 } else {
2449 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2450 }
2451
2452 first_non_void = util_format_get_first_non_void_channel(pipe_format);
2453
2454 switch (pipe_format) {
2455 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2456 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2457 break;
2458 default:
2459 if (first_non_void < 0) {
2460 if (util_format_is_compressed(pipe_format)) {
2461 switch (pipe_format) {
2462 case PIPE_FORMAT_DXT1_SRGB:
2463 case PIPE_FORMAT_DXT1_SRGBA:
2464 case PIPE_FORMAT_DXT3_SRGBA:
2465 case PIPE_FORMAT_DXT5_SRGBA:
2466 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2467 break;
2468 case PIPE_FORMAT_RGTC1_SNORM:
2469 case PIPE_FORMAT_LATC1_SNORM:
2470 case PIPE_FORMAT_RGTC2_SNORM:
2471 case PIPE_FORMAT_LATC2_SNORM:
2472 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2473 break;
2474 default:
2475 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2476 break;
2477 }
2478 } else {
2479 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2480 }
2481 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
2482 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2483 } else {
2484 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2485
2486 switch (desc->channel[first_non_void].type) {
2487 case UTIL_FORMAT_TYPE_FLOAT:
2488 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2489 break;
2490 case UTIL_FORMAT_TYPE_SIGNED:
2491 if (desc->channel[first_non_void].normalized)
2492 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2493 else if (desc->channel[first_non_void].pure_integer)
2494 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
2495 else
2496 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
2497 break;
2498 case UTIL_FORMAT_TYPE_UNSIGNED:
2499 if (desc->channel[first_non_void].normalized)
2500 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2501 else if (desc->channel[first_non_void].pure_integer)
2502 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
2503 else
2504 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
2505 }
2506 }
2507 }
2508
2509 format = si_translate_texformat(ctx->screen, pipe_format, desc, first_non_void);
2510 if (format == ~0) {
2511 format = 0;
2512 }
2513
2514 /* not supported any more */
2515 //endian = si_colorformat_endian_swap(format);
2516
2517 width = surflevel[0].npix_x;
2518 height = surflevel[0].npix_y;
2519 depth = surflevel[0].npix_z;
2520 pitch = surflevel[0].nblk_x * util_format_get_blockwidth(pipe_format);
2521
2522 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
2523 height = 1;
2524 depth = texture->array_size;
2525 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
2526 depth = texture->array_size;
2527 }
2528
2529 va = r600_resource_va(ctx->screen, texture);
2530 va += surflevel[0].offset;
2531 va += tmp->mipmap_shift * surflevel[texture->last_level].slice_size;
2532 view->state[0] = va >> 8;
2533 view->state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) |
2534 S_008F14_DATA_FORMAT(format) |
2535 S_008F14_NUM_FORMAT(num_format));
2536 view->state[2] = (S_008F18_WIDTH(width - 1) |
2537 S_008F18_HEIGHT(height - 1));
2538 view->state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2539 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2540 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2541 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2542 S_008F1C_BASE_LEVEL(texture->nr_samples > 1 ?
2543 0 : state->u.tex.first_level - tmp->mipmap_shift) |
2544 S_008F1C_LAST_LEVEL(texture->nr_samples > 1 ?
2545 util_logbase2(texture->nr_samples) :
2546 state->u.tex.last_level - tmp->mipmap_shift) |
2547 S_008F1C_TILING_INDEX(si_tile_mode_index(tmp, 0, false)) |
2548 S_008F1C_POW2_PAD(texture->last_level > 0) |
2549 S_008F1C_TYPE(si_tex_dim(texture->target, texture->nr_samples)));
2550 view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
2551 view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2552 S_008F24_LAST_ARRAY(state->u.tex.last_layer));
2553 view->state[6] = 0;
2554 view->state[7] = 0;
2555
2556 /* Initialize the sampler view for FMASK. */
2557 if (tmp->fmask.size) {
2558 uint64_t va = r600_resource_va(ctx->screen, texture) + tmp->fmask.offset;
2559 uint32_t fmask_format;
2560
2561 switch (texture->nr_samples) {
2562 case 2:
2563 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
2564 break;
2565 case 4:
2566 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
2567 break;
2568 case 8:
2569 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
2570 break;
2571 default:
2572 assert(0);
2573 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
2574 }
2575
2576 view->fmask_state[0] = va >> 8;
2577 view->fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
2578 S_008F14_DATA_FORMAT(fmask_format) |
2579 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT);
2580 view->fmask_state[2] = S_008F18_WIDTH(width - 1) |
2581 S_008F18_HEIGHT(height - 1);
2582 view->fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
2583 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
2584 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
2585 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
2586 S_008F1C_TILING_INDEX(tmp->fmask.tile_mode_index) |
2587 S_008F1C_TYPE(si_tex_dim(texture->target, 0));
2588 view->fmask_state[4] = S_008F20_DEPTH(depth - 1) |
2589 S_008F20_PITCH(tmp->fmask.pitch - 1);
2590 view->fmask_state[5] = S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2591 S_008F24_LAST_ARRAY(state->u.tex.last_layer);
2592 view->fmask_state[6] = 0;
2593 view->fmask_state[7] = 0;
2594 }
2595
2596 return &view->base;
2597 }
2598
2599 static void si_sampler_view_destroy(struct pipe_context *ctx,
2600 struct pipe_sampler_view *state)
2601 {
2602 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
2603
2604 pipe_resource_reference(&state->texture, NULL);
2605 FREE(resource);
2606 }
2607
2608 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
2609 {
2610 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
2611 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
2612 (linear_filter &&
2613 (wrap == PIPE_TEX_WRAP_CLAMP ||
2614 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
2615 }
2616
2617 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
2618 {
2619 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
2620 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
2621
2622 return (state->border_color.ui[0] || state->border_color.ui[1] ||
2623 state->border_color.ui[2] || state->border_color.ui[3]) &&
2624 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
2625 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
2626 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
2627 }
2628
2629 static void *si_create_sampler_state(struct pipe_context *ctx,
2630 const struct pipe_sampler_state *state)
2631 {
2632 struct si_pipe_sampler_state *rstate = CALLOC_STRUCT(si_pipe_sampler_state);
2633 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
2634 unsigned border_color_type;
2635
2636 if (rstate == NULL) {
2637 return NULL;
2638 }
2639
2640 if (sampler_state_needs_border_color(state))
2641 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
2642 else
2643 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
2644
2645 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
2646 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
2647 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
2648 (state->max_anisotropy & 0x7) << 9 | /* XXX */
2649 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
2650 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
2651 aniso_flag_offset << 16 | /* XXX */
2652 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map));
2653 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
2654 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
2655 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
2656 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter)) |
2657 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter)) |
2658 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)));
2659 rstate->val[3] = S_008F3C_BORDER_COLOR_TYPE(border_color_type);
2660
2661 if (border_color_type == V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2662 memcpy(rstate->border_color, state->border_color.ui,
2663 sizeof(rstate->border_color));
2664 }
2665
2666 return rstate;
2667 }
2668
2669 /* XXX consider moving this function to si_descriptors.c for gcc to inline
2670 * the si_set_sampler_view calls. LTO might help too. */
2671 static void si_set_sampler_views(struct pipe_context *ctx,
2672 unsigned shader, unsigned start,
2673 unsigned count,
2674 struct pipe_sampler_view **views)
2675 {
2676 struct r600_context *rctx = (struct r600_context *)ctx;
2677 struct r600_textures_info *samplers = &rctx->samplers[shader];
2678 struct si_pipe_sampler_view **rviews = (struct si_pipe_sampler_view **)views;
2679 int i;
2680
2681 if (shader != PIPE_SHADER_VERTEX && shader != PIPE_SHADER_FRAGMENT)
2682 return;
2683
2684 assert(start == 0);
2685
2686 for (i = 0; i < count; i++) {
2687 if (!views[i]) {
2688 samplers->depth_texture_mask &= ~(1 << i);
2689 samplers->compressed_colortex_mask &= ~(1 << i);
2690 si_set_sampler_view(rctx, shader, i, NULL, NULL);
2691 si_set_sampler_view(rctx, shader, FMASK_TEX_OFFSET + i,
2692 NULL, NULL);
2693 continue;
2694 }
2695
2696 si_set_sampler_view(rctx, shader, i, views[i], rviews[i]->state);
2697
2698 if (views[i]->texture->target != PIPE_BUFFER) {
2699 struct r600_texture *rtex =
2700 (struct r600_texture*)views[i]->texture;
2701
2702 if (rtex->is_depth && !rtex->is_flushing_texture) {
2703 samplers->depth_texture_mask |= 1 << i;
2704 } else {
2705 samplers->depth_texture_mask &= ~(1 << i);
2706 }
2707 if (rtex->cmask.size || rtex->fmask.size) {
2708 samplers->compressed_colortex_mask |= 1 << i;
2709 } else {
2710 samplers->compressed_colortex_mask &= ~(1 << i);
2711 }
2712
2713 if (rtex->fmask.size) {
2714 si_set_sampler_view(rctx, shader, FMASK_TEX_OFFSET + i,
2715 views[i], rviews[i]->fmask_state);
2716 } else {
2717 si_set_sampler_view(rctx, shader, FMASK_TEX_OFFSET + i,
2718 NULL, NULL);
2719 }
2720 }
2721 }
2722 for (; i < samplers->n_views; i++) {
2723 samplers->depth_texture_mask &= ~(1 << i);
2724 samplers->compressed_colortex_mask &= ~(1 << i);
2725 si_set_sampler_view(rctx, shader, i, NULL, NULL);
2726 si_set_sampler_view(rctx, shader, FMASK_TEX_OFFSET + i,
2727 NULL, NULL);
2728 }
2729
2730 samplers->n_views = count;
2731 rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE;
2732 }
2733
2734 static struct si_pm4_state *si_set_sampler_states(struct r600_context *rctx, unsigned count,
2735 void **states,
2736 struct r600_textures_info *samplers,
2737 unsigned user_data_reg)
2738 {
2739 struct si_pipe_sampler_state **rstates = (struct si_pipe_sampler_state **)states;
2740 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
2741 uint32_t *border_color_table = NULL;
2742 int i, j;
2743
2744 if (!count)
2745 goto out;
2746
2747 rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE;
2748
2749 si_pm4_sh_data_begin(pm4);
2750 for (i = 0; i < count; i++) {
2751 if (rstates[i] &&
2752 G_008F3C_BORDER_COLOR_TYPE(rstates[i]->val[3]) ==
2753 V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2754 if (!rctx->border_color_table ||
2755 ((rctx->border_color_offset + count - i) &
2756 C_008F3C_BORDER_COLOR_PTR)) {
2757 r600_resource_reference(&rctx->border_color_table, NULL);
2758 rctx->border_color_offset = 0;
2759
2760 rctx->border_color_table =
2761 r600_resource_create_custom(&rctx->screen->b.b,
2762 PIPE_USAGE_STAGING,
2763 4096 * 4 * 4);
2764 }
2765
2766 if (!border_color_table) {
2767 border_color_table =
2768 rctx->b.ws->buffer_map(rctx->border_color_table->cs_buf,
2769 rctx->b.rings.gfx.cs,
2770 PIPE_TRANSFER_WRITE |
2771 PIPE_TRANSFER_UNSYNCHRONIZED);
2772 }
2773
2774 for (j = 0; j < 4; j++) {
2775 border_color_table[4 * rctx->border_color_offset + j] =
2776 util_le32_to_cpu(rstates[i]->border_color[j]);
2777 }
2778
2779 rstates[i]->val[3] &= C_008F3C_BORDER_COLOR_PTR;
2780 rstates[i]->val[3] |= S_008F3C_BORDER_COLOR_PTR(rctx->border_color_offset++);
2781 }
2782
2783 for (j = 0; j < Elements(rstates[i]->val); ++j) {
2784 si_pm4_sh_data_add(pm4, rstates[i] ? rstates[i]->val[j] : 0);
2785 }
2786 }
2787 si_pm4_sh_data_end(pm4, user_data_reg, SI_SGPR_SAMPLER);
2788
2789 if (border_color_table) {
2790 uint64_t va_offset =
2791 r600_resource_va(&rctx->screen->b.b,
2792 (void*)rctx->border_color_table);
2793
2794 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, va_offset >> 8);
2795 if (rctx->b.chip_class >= CIK)
2796 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, va_offset >> 40);
2797 rctx->b.ws->buffer_unmap(rctx->border_color_table->cs_buf);
2798 si_pm4_add_bo(pm4, rctx->border_color_table, RADEON_USAGE_READ);
2799 }
2800
2801 memcpy(samplers->samplers, states, sizeof(void*) * count);
2802
2803 out:
2804 samplers->n_samplers = count;
2805 return pm4;
2806 }
2807
2808 static void si_bind_vs_sampler_states(struct pipe_context *ctx, unsigned count, void **states)
2809 {
2810 struct r600_context *rctx = (struct r600_context *)ctx;
2811 struct si_pm4_state *pm4;
2812
2813 pm4 = si_set_sampler_states(rctx, count, states, &rctx->samplers[PIPE_SHADER_VERTEX],
2814 R_00B130_SPI_SHADER_USER_DATA_VS_0);
2815 si_pm4_set_state(rctx, vs_sampler, pm4);
2816 }
2817
2818 static void si_bind_ps_sampler_states(struct pipe_context *ctx, unsigned count, void **states)
2819 {
2820 struct r600_context *rctx = (struct r600_context *)ctx;
2821 struct si_pm4_state *pm4;
2822
2823 pm4 = si_set_sampler_states(rctx, count, states, &rctx->samplers[PIPE_SHADER_FRAGMENT],
2824 R_00B030_SPI_SHADER_USER_DATA_PS_0);
2825 si_pm4_set_state(rctx, ps_sampler, pm4);
2826 }
2827
2828
2829 static void si_bind_sampler_states(struct pipe_context *ctx, unsigned shader,
2830 unsigned start, unsigned count,
2831 void **states)
2832 {
2833 assert(start == 0);
2834
2835 switch (shader) {
2836 case PIPE_SHADER_VERTEX:
2837 si_bind_vs_sampler_states(ctx, count, states);
2838 break;
2839 case PIPE_SHADER_FRAGMENT:
2840 si_bind_ps_sampler_states(ctx, count, states);
2841 break;
2842 default:
2843 ;
2844 }
2845 }
2846
2847
2848
2849 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
2850 {
2851 struct r600_context *rctx = (struct r600_context *)ctx;
2852 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
2853 uint16_t mask = sample_mask;
2854
2855 if (pm4 == NULL)
2856 return;
2857
2858 si_pm4_set_reg(pm4, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, mask | (mask << 16));
2859 si_pm4_set_reg(pm4, R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, mask | (mask << 16));
2860
2861 si_pm4_set_state(rctx, sample_mask, pm4);
2862 }
2863
2864 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
2865 {
2866 free(state);
2867 }
2868
2869 /*
2870 * Vertex elements & buffers
2871 */
2872
2873 static void *si_create_vertex_elements(struct pipe_context *ctx,
2874 unsigned count,
2875 const struct pipe_vertex_element *elements)
2876 {
2877 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
2878 int i;
2879
2880 assert(count < PIPE_MAX_ATTRIBS);
2881 if (!v)
2882 return NULL;
2883
2884 v->count = count;
2885 for (i = 0; i < count; ++i) {
2886 const struct util_format_description *desc;
2887 unsigned data_format, num_format;
2888 int first_non_void;
2889
2890 desc = util_format_description(elements[i].src_format);
2891 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
2892 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
2893 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
2894
2895 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2896 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2897 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2898 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2899 S_008F0C_NUM_FORMAT(num_format) |
2900 S_008F0C_DATA_FORMAT(data_format);
2901 }
2902 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
2903
2904 return v;
2905 }
2906
2907 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
2908 {
2909 struct r600_context *rctx = (struct r600_context *)ctx;
2910 struct si_vertex_element *v = (struct si_vertex_element*)state;
2911
2912 rctx->vertex_elements = v;
2913 }
2914
2915 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
2916 {
2917 struct r600_context *rctx = (struct r600_context *)ctx;
2918
2919 if (rctx->vertex_elements == state)
2920 rctx->vertex_elements = NULL;
2921 FREE(state);
2922 }
2923
2924 static void si_set_vertex_buffers(struct pipe_context *ctx, unsigned start_slot, unsigned count,
2925 const struct pipe_vertex_buffer *buffers)
2926 {
2927 struct r600_context *rctx = (struct r600_context *)ctx;
2928
2929 util_set_vertex_buffers_count(rctx->vertex_buffer, &rctx->nr_vertex_buffers, buffers, start_slot, count);
2930 }
2931
2932 static void si_set_index_buffer(struct pipe_context *ctx,
2933 const struct pipe_index_buffer *ib)
2934 {
2935 struct r600_context *rctx = (struct r600_context *)ctx;
2936
2937 if (ib) {
2938 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
2939 memcpy(&rctx->index_buffer, ib, sizeof(*ib));
2940 } else {
2941 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
2942 }
2943 }
2944
2945 /*
2946 * Misc
2947 */
2948 static void si_set_polygon_stipple(struct pipe_context *ctx,
2949 const struct pipe_poly_stipple *state)
2950 {
2951 }
2952
2953 static void si_texture_barrier(struct pipe_context *ctx)
2954 {
2955 struct r600_context *rctx = (struct r600_context *)ctx;
2956
2957 rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE |
2958 R600_CONTEXT_FLUSH_AND_INV_CB;
2959 }
2960
2961 static void *si_create_blend_custom(struct r600_context *rctx, unsigned mode)
2962 {
2963 struct pipe_blend_state blend;
2964
2965 memset(&blend, 0, sizeof(blend));
2966 blend.independent_blend_enable = true;
2967 blend.rt[0].colormask = 0xf;
2968 return si_create_blend_state_mode(&rctx->b.b, &blend, mode);
2969 }
2970
2971 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
2972 struct pipe_resource *texture,
2973 const struct pipe_surface *surf_tmpl)
2974 {
2975 struct r600_texture *rtex = (struct r600_texture*)texture;
2976 struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
2977 unsigned level = surf_tmpl->u.tex.level;
2978
2979 if (surface == NULL)
2980 return NULL;
2981
2982 assert(surf_tmpl->u.tex.first_layer <= util_max_layer(texture, surf_tmpl->u.tex.level));
2983 assert(surf_tmpl->u.tex.last_layer <= util_max_layer(texture, surf_tmpl->u.tex.level));
2984
2985 pipe_reference_init(&surface->base.reference, 1);
2986 pipe_resource_reference(&surface->base.texture, texture);
2987 surface->base.context = pipe;
2988 surface->base.format = surf_tmpl->format;
2989 surface->base.width = rtex->surface.level[level].npix_x;
2990 surface->base.height = rtex->surface.level[level].npix_y;
2991 surface->base.texture = texture;
2992 surface->base.u.tex.first_layer = surf_tmpl->u.tex.first_layer;
2993 surface->base.u.tex.last_layer = surf_tmpl->u.tex.last_layer;
2994 surface->base.u.tex.level = level;
2995
2996 return &surface->base;
2997 }
2998
2999 static void r600_surface_destroy(struct pipe_context *pipe,
3000 struct pipe_surface *surface)
3001 {
3002 pipe_resource_reference(&surface->texture, NULL);
3003 FREE(surface);
3004 }
3005
3006 static boolean si_dma_copy(struct pipe_context *ctx,
3007 struct pipe_resource *dst,
3008 unsigned dst_level,
3009 unsigned dst_x, unsigned dst_y, unsigned dst_z,
3010 struct pipe_resource *src,
3011 unsigned src_level,
3012 const struct pipe_box *src_box)
3013 {
3014 /* XXX implement this or share evergreen_dma_blit with r600g */
3015 return FALSE;
3016 }
3017
3018 void si_init_state_functions(struct r600_context *rctx)
3019 {
3020 int i;
3021
3022 rctx->b.b.create_blend_state = si_create_blend_state;
3023 rctx->b.b.bind_blend_state = si_bind_blend_state;
3024 rctx->b.b.delete_blend_state = si_delete_blend_state;
3025 rctx->b.b.set_blend_color = si_set_blend_color;
3026
3027 rctx->b.b.create_rasterizer_state = si_create_rs_state;
3028 rctx->b.b.bind_rasterizer_state = si_bind_rs_state;
3029 rctx->b.b.delete_rasterizer_state = si_delete_rs_state;
3030
3031 rctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
3032 rctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
3033 rctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
3034
3035 for (i = 0; i < 8; i++) {
3036 rctx->custom_dsa_flush_depth_stencil[i] = si_create_db_flush_dsa(rctx, true, true, i);
3037 rctx->custom_dsa_flush_depth[i] = si_create_db_flush_dsa(rctx, true, false, i);
3038 rctx->custom_dsa_flush_stencil[i] = si_create_db_flush_dsa(rctx, false, true, i);
3039 }
3040 rctx->custom_dsa_flush_inplace = si_create_db_flush_dsa(rctx, false, false, 0);
3041 rctx->custom_blend_resolve = si_create_blend_custom(rctx, V_028808_CB_RESOLVE);
3042 rctx->custom_blend_decompress = si_create_blend_custom(rctx, V_028808_CB_FMASK_DECOMPRESS);
3043
3044 rctx->b.b.set_clip_state = si_set_clip_state;
3045 rctx->b.b.set_scissor_states = si_set_scissor_states;
3046 rctx->b.b.set_viewport_states = si_set_viewport_states;
3047 rctx->b.b.set_stencil_ref = si_set_pipe_stencil_ref;
3048
3049 rctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
3050 rctx->b.b.get_sample_position = si_get_sample_position;
3051
3052 rctx->b.b.create_vs_state = si_create_vs_state;
3053 rctx->b.b.create_fs_state = si_create_fs_state;
3054 rctx->b.b.bind_vs_state = si_bind_vs_shader;
3055 rctx->b.b.bind_fs_state = si_bind_ps_shader;
3056 rctx->b.b.delete_vs_state = si_delete_vs_shader;
3057 rctx->b.b.delete_fs_state = si_delete_ps_shader;
3058
3059 rctx->b.b.create_sampler_state = si_create_sampler_state;
3060 rctx->b.b.bind_sampler_states = si_bind_sampler_states;
3061 rctx->b.b.delete_sampler_state = si_delete_sampler_state;
3062
3063 rctx->b.b.create_sampler_view = si_create_sampler_view;
3064 rctx->b.b.set_sampler_views = si_set_sampler_views;
3065 rctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
3066
3067 rctx->b.b.set_sample_mask = si_set_sample_mask;
3068
3069 rctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
3070 rctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
3071 rctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
3072 rctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
3073 rctx->b.b.set_index_buffer = si_set_index_buffer;
3074
3075 rctx->b.b.texture_barrier = si_texture_barrier;
3076 rctx->b.b.set_polygon_stipple = si_set_polygon_stipple;
3077 rctx->b.b.create_surface = r600_create_surface;
3078 rctx->b.b.surface_destroy = r600_surface_destroy;
3079 rctx->b.dma_copy = si_dma_copy;
3080
3081 rctx->b.b.draw_vbo = si_draw_vbo;
3082 }
3083
3084 void si_init_config(struct r600_context *rctx)
3085 {
3086 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
3087
3088 if (pm4 == NULL)
3089 return;
3090
3091 si_cmd_context_control(pm4);
3092
3093 si_pm4_set_reg(pm4, R_028A4C_PA_SC_MODE_CNTL_1, 0x0);
3094
3095 si_pm4_set_reg(pm4, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0);
3096 si_pm4_set_reg(pm4, R_028A14_VGT_HOS_CNTL, 0x0);
3097 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0);
3098 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0);
3099 si_pm4_set_reg(pm4, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0);
3100 si_pm4_set_reg(pm4, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0);
3101 si_pm4_set_reg(pm4, R_028A28_VGT_GROUP_FIRST_DECR, 0x0);
3102 si_pm4_set_reg(pm4, R_028A2C_VGT_GROUP_DECR, 0x0);
3103 si_pm4_set_reg(pm4, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0);
3104 si_pm4_set_reg(pm4, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0);
3105 si_pm4_set_reg(pm4, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0);
3106 si_pm4_set_reg(pm4, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0);
3107 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, 0x0);
3108 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0x0);
3109 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
3110 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3111 si_pm4_set_reg(pm4, R_028B94_VGT_STRMOUT_CONFIG, 0x0);
3112 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
3113 if (rctx->b.chip_class == SI) {
3114 si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM,
3115 S_028AA8_SWITCH_ON_EOP(1) |
3116 S_028AA8_PARTIAL_VS_WAVE_ON(1) |
3117 S_028AA8_PRIMGROUP_SIZE(63));
3118 }
3119 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0x00000000);
3120 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
3121 if (rctx->b.chip_class < CIK)
3122 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
3123 S_008A14_CLIP_VTX_REORDER_ENA(1));
3124
3125 si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, 0);
3126 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
3127 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
3128
3129 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
3130
3131 if (rctx->b.chip_class >= CIK) {
3132 switch (rctx->screen->b.family) {
3133 case CHIP_BONAIRE:
3134 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x16000012);
3135 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000);
3136 break;
3137 case CHIP_HAWAII:
3138 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x3a00161a);
3139 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x0000002e);
3140 break;
3141 case CHIP_KAVERI:
3142 /* XXX todo */
3143 case CHIP_KABINI:
3144 /* XXX todo */
3145 default:
3146 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
3147 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000);
3148 break;
3149 }
3150 } else {
3151 switch (rctx->screen->b.family) {
3152 case CHIP_TAHITI:
3153 case CHIP_PITCAIRN:
3154 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x2a00126a);
3155 break;
3156 case CHIP_VERDE:
3157 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x0000124a);
3158 break;
3159 case CHIP_OLAND:
3160 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000082);
3161 break;
3162 case CHIP_HAINAN:
3163 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
3164 break;
3165 default:
3166 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
3167 break;
3168 }
3169 }
3170
3171 si_pm4_set_reg(pm4, R_028200_PA_SC_WINDOW_OFFSET, 0x00000000);
3172 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
3173 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000);
3174 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000);
3175 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
3176 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0x00000000);
3177 si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000);
3178 si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000);
3179 si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000);
3180 si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000);
3181 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, 0x00000000);
3182 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, 0x00000000);
3183 si_pm4_set_reg(pm4, R_028028_DB_STENCIL_CLEAR, 0x00000000);
3184 si_pm4_set_reg(pm4, R_02802C_DB_DEPTH_CLEAR, 0x3F800000);
3185 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
3186 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
3187 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
3188 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE,
3189 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3190 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
3191 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
3192 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
3193
3194 if (rctx->b.chip_class >= CIK) {
3195 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
3196 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(0));
3197 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
3198 }
3199
3200 si_pm4_set_state(rctx, init, pm4);
3201 }