2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include "radeon/r600_cs.h"
28 #include "radeon/r600_query.h"
30 #include "util/u_dual_blend.h"
31 #include "util/u_format.h"
32 #include "util/u_format_s3tc.h"
33 #include "util/u_memory.h"
34 #include "util/u_resource.h"
35 #include "util/u_upload_mgr.h"
37 /* Initialize an external atom (owned by ../radeon). */
39 si_init_external_atom(struct si_context
*sctx
, struct r600_atom
*atom
,
40 struct r600_atom
**list_elem
)
42 atom
->id
= list_elem
- sctx
->atoms
.array
;
46 /* Initialize an atom owned by radeonsi. */
47 void si_init_atom(struct si_context
*sctx
, struct r600_atom
*atom
,
48 struct r600_atom
**list_elem
,
49 void (*emit_func
)(struct si_context
*ctx
, struct r600_atom
*state
))
51 atom
->emit
= (void*)emit_func
;
52 atom
->id
= list_elem
- sctx
->atoms
.array
;
56 static unsigned si_map_swizzle(unsigned swizzle
)
60 return V_008F0C_SQ_SEL_Y
;
62 return V_008F0C_SQ_SEL_Z
;
64 return V_008F0C_SQ_SEL_W
;
66 return V_008F0C_SQ_SEL_0
;
68 return V_008F0C_SQ_SEL_1
;
69 default: /* PIPE_SWIZZLE_X */
70 return V_008F0C_SQ_SEL_X
;
74 /* 12.4 fixed-point */
75 static unsigned si_pack_float_12p4(float x
)
78 x
>= 4096 ? 0xffff : x
* 16;
82 * Inferred framebuffer and blender state.
84 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
85 * if there is not enough PS outputs.
87 static void si_emit_cb_render_state(struct si_context
*sctx
, struct r600_atom
*atom
)
89 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
90 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
91 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
92 * but you never know. */
93 uint32_t cb_target_mask
= sctx
->framebuffer
.colorbuf_enabled_4bit
;
97 cb_target_mask
&= blend
->cb_target_mask
;
99 /* Avoid a hang that happens when dual source blending is enabled
100 * but there is not enough color outputs. This is undefined behavior,
101 * so disable color writes completely.
103 * Reproducible with Unigine Heaven 4.0 and drirc missing.
105 if (blend
&& blend
->dual_src_blend
&&
106 sctx
->ps_shader
.cso
&&
107 (sctx
->ps_shader
.cso
->info
.colors_written
& 0x3) != 0x3)
110 radeon_set_context_reg(cs
, R_028238_CB_TARGET_MASK
, cb_target_mask
);
112 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
113 * I think we don't have to do anything between IBs.
115 if (sctx
->screen
->dfsm_allowed
&&
116 sctx
->last_cb_target_mask
!= cb_target_mask
) {
117 sctx
->last_cb_target_mask
= cb_target_mask
;
119 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
120 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
123 if (sctx
->b
.chip_class
>= VI
) {
124 /* DCC MSAA workaround for blending.
125 * Alternatively, we can set CB_COLORi_DCC_CONTROL.OVERWRITE_-
126 * COMBINER_DISABLE, but that would be more complicated.
128 bool oc_disable
= (sctx
->b
.chip_class
== VI
||
129 sctx
->b
.chip_class
== GFX9
) &&
131 blend
->blend_enable_4bit
& cb_target_mask
&&
132 sctx
->framebuffer
.nr_samples
>= 2;
134 radeon_set_context_reg(cs
, R_028424_CB_DCC_CONTROL
,
135 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
136 S_028424_OVERWRITE_COMBINER_WATERMARK(4) |
137 S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable
));
140 /* RB+ register settings. */
141 if (sctx
->screen
->rbplus_allowed
) {
142 unsigned spi_shader_col_format
=
143 sctx
->ps_shader
.cso
?
144 sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.spi_shader_col_format
: 0;
145 unsigned sx_ps_downconvert
= 0;
146 unsigned sx_blend_opt_epsilon
= 0;
147 unsigned sx_blend_opt_control
= 0;
149 for (i
= 0; i
< sctx
->framebuffer
.state
.nr_cbufs
; i
++) {
150 struct r600_surface
*surf
=
151 (struct r600_surface
*)sctx
->framebuffer
.state
.cbufs
[i
];
152 unsigned format
, swap
, spi_format
, colormask
;
153 bool has_alpha
, has_rgb
;
158 format
= G_028C70_FORMAT(surf
->cb_color_info
);
159 swap
= G_028C70_COMP_SWAP(surf
->cb_color_info
);
160 spi_format
= (spi_shader_col_format
>> (i
* 4)) & 0xf;
161 colormask
= (cb_target_mask
>> (i
* 4)) & 0xf;
163 /* Set if RGB and A are present. */
164 has_alpha
= !G_028C74_FORCE_DST_ALPHA_1(surf
->cb_color_attrib
);
166 if (format
== V_028C70_COLOR_8
||
167 format
== V_028C70_COLOR_16
||
168 format
== V_028C70_COLOR_32
)
169 has_rgb
= !has_alpha
;
173 /* Check the colormask and export format. */
174 if (!(colormask
& (PIPE_MASK_RGBA
& ~PIPE_MASK_A
)))
176 if (!(colormask
& PIPE_MASK_A
))
179 if (spi_format
== V_028714_SPI_SHADER_ZERO
) {
184 /* Disable value checking for disabled channels. */
186 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
188 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
190 /* Enable down-conversion for 32bpp and smaller formats. */
192 case V_028C70_COLOR_8
:
193 case V_028C70_COLOR_8_8
:
194 case V_028C70_COLOR_8_8_8_8
:
195 /* For 1 and 2-channel formats, use the superset thereof. */
196 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
||
197 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
198 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
199 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_8_8_8_8
<< (i
* 4);
200 sx_blend_opt_epsilon
|= V_028758_8BIT_FORMAT
<< (i
* 4);
204 case V_028C70_COLOR_5_6_5
:
205 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
206 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_5_6_5
<< (i
* 4);
207 sx_blend_opt_epsilon
|= V_028758_6BIT_FORMAT
<< (i
* 4);
211 case V_028C70_COLOR_1_5_5_5
:
212 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
213 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_1_5_5_5
<< (i
* 4);
214 sx_blend_opt_epsilon
|= V_028758_5BIT_FORMAT
<< (i
* 4);
218 case V_028C70_COLOR_4_4_4_4
:
219 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
220 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_4_4_4_4
<< (i
* 4);
221 sx_blend_opt_epsilon
|= V_028758_4BIT_FORMAT
<< (i
* 4);
225 case V_028C70_COLOR_32
:
226 if (swap
== V_028C70_SWAP_STD
&&
227 spi_format
== V_028714_SPI_SHADER_32_R
)
228 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_R
<< (i
* 4);
229 else if (swap
== V_028C70_SWAP_ALT_REV
&&
230 spi_format
== V_028714_SPI_SHADER_32_AR
)
231 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_A
<< (i
* 4);
234 case V_028C70_COLOR_16
:
235 case V_028C70_COLOR_16_16
:
236 /* For 1-channel formats, use the superset thereof. */
237 if (spi_format
== V_028714_SPI_SHADER_UNORM16_ABGR
||
238 spi_format
== V_028714_SPI_SHADER_SNORM16_ABGR
||
239 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
240 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
241 if (swap
== V_028C70_SWAP_STD
||
242 swap
== V_028C70_SWAP_STD_REV
)
243 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_GR
<< (i
* 4);
245 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_AR
<< (i
* 4);
249 case V_028C70_COLOR_10_11_11
:
250 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
251 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_10_11_11
<< (i
* 4);
252 sx_blend_opt_epsilon
|= V_028758_11BIT_FORMAT
<< (i
* 4);
256 case V_028C70_COLOR_2_10_10_10
:
257 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
258 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_2_10_10_10
<< (i
* 4);
259 sx_blend_opt_epsilon
|= V_028758_10BIT_FORMAT
<< (i
* 4);
265 radeon_set_context_reg_seq(cs
, R_028754_SX_PS_DOWNCONVERT
, 3);
266 radeon_emit(cs
, sx_ps_downconvert
); /* R_028754_SX_PS_DOWNCONVERT */
267 radeon_emit(cs
, sx_blend_opt_epsilon
); /* R_028758_SX_BLEND_OPT_EPSILON */
268 radeon_emit(cs
, sx_blend_opt_control
); /* R_02875C_SX_BLEND_OPT_CONTROL */
269 } else if (sctx
->screen
->has_rbplus
) {
270 radeon_set_context_reg_seq(cs
, R_028754_SX_PS_DOWNCONVERT
, 3);
271 radeon_emit(cs
, 0); /* R_028754_SX_PS_DOWNCONVERT */
272 radeon_emit(cs
, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
273 radeon_emit(cs
, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
281 static uint32_t si_translate_blend_function(int blend_func
)
283 switch (blend_func
) {
285 return V_028780_COMB_DST_PLUS_SRC
;
286 case PIPE_BLEND_SUBTRACT
:
287 return V_028780_COMB_SRC_MINUS_DST
;
288 case PIPE_BLEND_REVERSE_SUBTRACT
:
289 return V_028780_COMB_DST_MINUS_SRC
;
291 return V_028780_COMB_MIN_DST_SRC
;
293 return V_028780_COMB_MAX_DST_SRC
;
295 R600_ERR("Unknown blend function %d\n", blend_func
);
302 static uint32_t si_translate_blend_factor(int blend_fact
)
304 switch (blend_fact
) {
305 case PIPE_BLENDFACTOR_ONE
:
306 return V_028780_BLEND_ONE
;
307 case PIPE_BLENDFACTOR_SRC_COLOR
:
308 return V_028780_BLEND_SRC_COLOR
;
309 case PIPE_BLENDFACTOR_SRC_ALPHA
:
310 return V_028780_BLEND_SRC_ALPHA
;
311 case PIPE_BLENDFACTOR_DST_ALPHA
:
312 return V_028780_BLEND_DST_ALPHA
;
313 case PIPE_BLENDFACTOR_DST_COLOR
:
314 return V_028780_BLEND_DST_COLOR
;
315 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
316 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
317 case PIPE_BLENDFACTOR_CONST_COLOR
:
318 return V_028780_BLEND_CONSTANT_COLOR
;
319 case PIPE_BLENDFACTOR_CONST_ALPHA
:
320 return V_028780_BLEND_CONSTANT_ALPHA
;
321 case PIPE_BLENDFACTOR_ZERO
:
322 return V_028780_BLEND_ZERO
;
323 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
324 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
325 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
326 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
327 case PIPE_BLENDFACTOR_INV_DST_ALPHA
:
328 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
329 case PIPE_BLENDFACTOR_INV_DST_COLOR
:
330 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
331 case PIPE_BLENDFACTOR_INV_CONST_COLOR
:
332 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR
;
333 case PIPE_BLENDFACTOR_INV_CONST_ALPHA
:
334 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA
;
335 case PIPE_BLENDFACTOR_SRC1_COLOR
:
336 return V_028780_BLEND_SRC1_COLOR
;
337 case PIPE_BLENDFACTOR_SRC1_ALPHA
:
338 return V_028780_BLEND_SRC1_ALPHA
;
339 case PIPE_BLENDFACTOR_INV_SRC1_COLOR
:
340 return V_028780_BLEND_INV_SRC1_COLOR
;
341 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA
:
342 return V_028780_BLEND_INV_SRC1_ALPHA
;
344 R600_ERR("Bad blend factor %d not supported!\n", blend_fact
);
351 static uint32_t si_translate_blend_opt_function(int blend_func
)
353 switch (blend_func
) {
355 return V_028760_OPT_COMB_ADD
;
356 case PIPE_BLEND_SUBTRACT
:
357 return V_028760_OPT_COMB_SUBTRACT
;
358 case PIPE_BLEND_REVERSE_SUBTRACT
:
359 return V_028760_OPT_COMB_REVSUBTRACT
;
361 return V_028760_OPT_COMB_MIN
;
363 return V_028760_OPT_COMB_MAX
;
365 return V_028760_OPT_COMB_BLEND_DISABLED
;
369 static uint32_t si_translate_blend_opt_factor(int blend_fact
, bool is_alpha
)
371 switch (blend_fact
) {
372 case PIPE_BLENDFACTOR_ZERO
:
373 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL
;
374 case PIPE_BLENDFACTOR_ONE
:
375 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
;
376 case PIPE_BLENDFACTOR_SRC_COLOR
:
377 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
378 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0
;
379 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
380 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
381 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1
;
382 case PIPE_BLENDFACTOR_SRC_ALPHA
:
383 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
;
384 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
385 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
;
386 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
387 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
388 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
390 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
394 static void si_blend_check_commutativity(struct si_screen
*sscreen
,
395 struct si_state_blend
*blend
,
396 enum pipe_blend_func func
,
397 enum pipe_blendfactor src
,
398 enum pipe_blendfactor dst
,
401 /* Src factor is allowed when it does not depend on Dst */
402 static const uint32_t src_allowed
=
403 (1u << PIPE_BLENDFACTOR_ONE
) |
404 (1u << PIPE_BLENDFACTOR_SRC_COLOR
) |
405 (1u << PIPE_BLENDFACTOR_SRC_ALPHA
) |
406 (1u << PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
) |
407 (1u << PIPE_BLENDFACTOR_CONST_COLOR
) |
408 (1u << PIPE_BLENDFACTOR_CONST_ALPHA
) |
409 (1u << PIPE_BLENDFACTOR_SRC1_COLOR
) |
410 (1u << PIPE_BLENDFACTOR_SRC1_ALPHA
) |
411 (1u << PIPE_BLENDFACTOR_ZERO
) |
412 (1u << PIPE_BLENDFACTOR_INV_SRC_COLOR
) |
413 (1u << PIPE_BLENDFACTOR_INV_SRC_ALPHA
) |
414 (1u << PIPE_BLENDFACTOR_INV_CONST_COLOR
) |
415 (1u << PIPE_BLENDFACTOR_INV_CONST_ALPHA
) |
416 (1u << PIPE_BLENDFACTOR_INV_SRC1_COLOR
) |
417 (1u << PIPE_BLENDFACTOR_INV_SRC1_ALPHA
);
419 if (dst
== PIPE_BLENDFACTOR_ONE
&&
420 (src_allowed
& (1u << src
))) {
421 /* Addition is commutative, but floating point addition isn't
422 * associative: subtle changes can be introduced via different
425 * Out-of-order is also non-deterministic, which means that
426 * this breaks OpenGL invariance requirements. So only enable
427 * out-of-order additive blending if explicitly allowed by a
430 if (func
== PIPE_BLEND_MAX
|| func
== PIPE_BLEND_MIN
||
431 (func
== PIPE_BLEND_ADD
&& sscreen
->commutative_blend_add
))
432 blend
->commutative_4bit
|= chanmask
;
437 * Get rid of DST in the blend factors by commuting the operands:
438 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
440 static void si_blend_remove_dst(unsigned *func
, unsigned *src_factor
,
441 unsigned *dst_factor
, unsigned expected_dst
,
442 unsigned replacement_src
)
444 if (*src_factor
== expected_dst
&&
445 *dst_factor
== PIPE_BLENDFACTOR_ZERO
) {
446 *src_factor
= PIPE_BLENDFACTOR_ZERO
;
447 *dst_factor
= replacement_src
;
449 /* Commuting the operands requires reversing subtractions. */
450 if (*func
== PIPE_BLEND_SUBTRACT
)
451 *func
= PIPE_BLEND_REVERSE_SUBTRACT
;
452 else if (*func
== PIPE_BLEND_REVERSE_SUBTRACT
)
453 *func
= PIPE_BLEND_SUBTRACT
;
457 static bool si_blend_factor_uses_dst(unsigned factor
)
459 return factor
== PIPE_BLENDFACTOR_DST_COLOR
||
460 factor
== PIPE_BLENDFACTOR_DST_ALPHA
||
461 factor
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
462 factor
== PIPE_BLENDFACTOR_INV_DST_ALPHA
||
463 factor
== PIPE_BLENDFACTOR_INV_DST_COLOR
;
466 static void *si_create_blend_state_mode(struct pipe_context
*ctx
,
467 const struct pipe_blend_state
*state
,
470 struct si_context
*sctx
= (struct si_context
*)ctx
;
471 struct si_state_blend
*blend
= CALLOC_STRUCT(si_state_blend
);
472 struct si_pm4_state
*pm4
= &blend
->pm4
;
473 uint32_t sx_mrt_blend_opt
[8] = {0};
474 uint32_t color_control
= 0;
479 blend
->alpha_to_coverage
= state
->alpha_to_coverage
;
480 blend
->alpha_to_one
= state
->alpha_to_one
;
481 blend
->dual_src_blend
= util_blend_state_is_dual(state
, 0);
482 blend
->logicop_enable
= state
->logicop_enable
;
484 if (state
->logicop_enable
) {
485 color_control
|= S_028808_ROP3(state
->logicop_func
| (state
->logicop_func
<< 4));
487 color_control
|= S_028808_ROP3(0xcc);
490 si_pm4_set_reg(pm4
, R_028B70_DB_ALPHA_TO_MASK
,
491 S_028B70_ALPHA_TO_MASK_ENABLE(state
->alpha_to_coverage
) |
492 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
493 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
494 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
495 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
497 if (state
->alpha_to_coverage
)
498 blend
->need_src_alpha_4bit
|= 0xf;
500 blend
->cb_target_mask
= 0;
501 blend
->cb_target_enabled_4bit
= 0;
503 for (int i
= 0; i
< 8; i
++) {
504 /* state->rt entries > 0 only written if independent blending */
505 const int j
= state
->independent_blend_enable
? i
: 0;
507 unsigned eqRGB
= state
->rt
[j
].rgb_func
;
508 unsigned srcRGB
= state
->rt
[j
].rgb_src_factor
;
509 unsigned dstRGB
= state
->rt
[j
].rgb_dst_factor
;
510 unsigned eqA
= state
->rt
[j
].alpha_func
;
511 unsigned srcA
= state
->rt
[j
].alpha_src_factor
;
512 unsigned dstA
= state
->rt
[j
].alpha_dst_factor
;
514 unsigned srcRGB_opt
, dstRGB_opt
, srcA_opt
, dstA_opt
;
515 unsigned blend_cntl
= 0;
517 sx_mrt_blend_opt
[i
] =
518 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) |
519 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
521 /* Only set dual source blending for MRT0 to avoid a hang. */
522 if (i
>= 1 && blend
->dual_src_blend
) {
523 /* Vulkan does this for dual source blending. */
525 blend_cntl
|= S_028780_ENABLE(1);
527 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
531 /* Only addition and subtraction equations are supported with
532 * dual source blending.
534 if (blend
->dual_src_blend
&&
535 (eqRGB
== PIPE_BLEND_MIN
|| eqRGB
== PIPE_BLEND_MAX
||
536 eqA
== PIPE_BLEND_MIN
|| eqA
== PIPE_BLEND_MAX
)) {
537 assert(!"Unsupported equation for dual source blending");
538 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
542 /* cb_render_state will disable unused ones */
543 blend
->cb_target_mask
|= (unsigned)state
->rt
[j
].colormask
<< (4 * i
);
544 if (state
->rt
[j
].colormask
)
545 blend
->cb_target_enabled_4bit
|= 0xf << (4 * i
);
547 if (!state
->rt
[j
].colormask
|| !state
->rt
[j
].blend_enable
) {
548 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
552 si_blend_check_commutativity(sctx
->screen
, blend
,
553 eqRGB
, srcRGB
, dstRGB
, 0x7 << (4 * i
));
554 si_blend_check_commutativity(sctx
->screen
, blend
,
555 eqA
, srcA
, dstA
, 0x8 << (4 * i
));
557 /* Blending optimizations for RB+.
558 * These transformations don't change the behavior.
560 * First, get rid of DST in the blend factors:
561 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
563 si_blend_remove_dst(&eqRGB
, &srcRGB
, &dstRGB
,
564 PIPE_BLENDFACTOR_DST_COLOR
,
565 PIPE_BLENDFACTOR_SRC_COLOR
);
566 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
567 PIPE_BLENDFACTOR_DST_COLOR
,
568 PIPE_BLENDFACTOR_SRC_COLOR
);
569 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
570 PIPE_BLENDFACTOR_DST_ALPHA
,
571 PIPE_BLENDFACTOR_SRC_ALPHA
);
573 /* Look up the ideal settings from tables. */
574 srcRGB_opt
= si_translate_blend_opt_factor(srcRGB
, false);
575 dstRGB_opt
= si_translate_blend_opt_factor(dstRGB
, false);
576 srcA_opt
= si_translate_blend_opt_factor(srcA
, true);
577 dstA_opt
= si_translate_blend_opt_factor(dstA
, true);
579 /* Handle interdependencies. */
580 if (si_blend_factor_uses_dst(srcRGB
))
581 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
582 if (si_blend_factor_uses_dst(srcA
))
583 dstA_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
585 if (srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
&&
586 (dstRGB
== PIPE_BLENDFACTOR_ZERO
||
587 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
588 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
))
589 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
591 /* Set the final value. */
592 sx_mrt_blend_opt
[i
] =
593 S_028760_COLOR_SRC_OPT(srcRGB_opt
) |
594 S_028760_COLOR_DST_OPT(dstRGB_opt
) |
595 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB
)) |
596 S_028760_ALPHA_SRC_OPT(srcA_opt
) |
597 S_028760_ALPHA_DST_OPT(dstA_opt
) |
598 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA
));
600 /* Set blend state. */
601 blend_cntl
|= S_028780_ENABLE(1);
602 blend_cntl
|= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB
));
603 blend_cntl
|= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB
));
604 blend_cntl
|= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB
));
606 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
607 blend_cntl
|= S_028780_SEPARATE_ALPHA_BLEND(1);
608 blend_cntl
|= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA
));
609 blend_cntl
|= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA
));
610 blend_cntl
|= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA
));
612 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
614 blend
->blend_enable_4bit
|= 0xfu
<< (i
* 4);
616 /* This is only important for formats without alpha. */
617 if (srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
618 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
619 srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
620 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
621 srcRGB
== PIPE_BLENDFACTOR_INV_SRC_ALPHA
||
622 dstRGB
== PIPE_BLENDFACTOR_INV_SRC_ALPHA
)
623 blend
->need_src_alpha_4bit
|= 0xfu
<< (i
* 4);
626 if (blend
->cb_target_mask
) {
627 color_control
|= S_028808_MODE(mode
);
629 color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
632 if (sctx
->screen
->has_rbplus
) {
633 /* Disable RB+ blend optimizations for dual source blending.
636 if (blend
->dual_src_blend
) {
637 for (int i
= 0; i
< 8; i
++) {
638 sx_mrt_blend_opt
[i
] =
639 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE
) |
640 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE
);
644 for (int i
= 0; i
< 8; i
++)
645 si_pm4_set_reg(pm4
, R_028760_SX_MRT0_BLEND_OPT
+ i
* 4,
646 sx_mrt_blend_opt
[i
]);
648 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
649 if (blend
->dual_src_blend
|| state
->logicop_enable
||
650 mode
== V_028808_CB_RESOLVE
)
651 color_control
|= S_028808_DISABLE_DUAL_QUAD(1);
654 si_pm4_set_reg(pm4
, R_028808_CB_COLOR_CONTROL
, color_control
);
658 static void *si_create_blend_state(struct pipe_context
*ctx
,
659 const struct pipe_blend_state
*state
)
661 return si_create_blend_state_mode(ctx
, state
, V_028808_CB_NORMAL
);
664 static void si_bind_blend_state(struct pipe_context
*ctx
, void *state
)
666 struct si_context
*sctx
= (struct si_context
*)ctx
;
667 struct si_state_blend
*old_blend
= sctx
->queued
.named
.blend
;
668 struct si_state_blend
*blend
= (struct si_state_blend
*)state
;
673 si_pm4_bind_state(sctx
, blend
, state
);
676 old_blend
->cb_target_mask
!= blend
->cb_target_mask
||
677 old_blend
->dual_src_blend
!= blend
->dual_src_blend
||
678 (old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
&&
679 sctx
->framebuffer
.nr_samples
>= 2 &&
680 sctx
->screen
->dcc_msaa_allowed
))
681 si_mark_atom_dirty(sctx
, &sctx
->cb_render_state
);
684 old_blend
->cb_target_mask
!= blend
->cb_target_mask
||
685 old_blend
->alpha_to_coverage
!= blend
->alpha_to_coverage
||
686 old_blend
->alpha_to_one
!= blend
->alpha_to_one
||
687 old_blend
->dual_src_blend
!= blend
->dual_src_blend
||
688 old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
||
689 old_blend
->need_src_alpha_4bit
!= blend
->need_src_alpha_4bit
)
690 sctx
->do_update_shaders
= true;
692 if (sctx
->screen
->dpbb_allowed
&&
694 old_blend
->alpha_to_coverage
!= blend
->alpha_to_coverage
||
695 old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
||
696 old_blend
->cb_target_enabled_4bit
!= blend
->cb_target_enabled_4bit
))
697 si_mark_atom_dirty(sctx
, &sctx
->dpbb_state
);
699 if (sctx
->screen
->has_out_of_order_rast
&&
701 (old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
||
702 old_blend
->cb_target_enabled_4bit
!= blend
->cb_target_enabled_4bit
||
703 old_blend
->commutative_4bit
!= blend
->commutative_4bit
||
704 old_blend
->logicop_enable
!= blend
->logicop_enable
)))
705 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
708 static void si_delete_blend_state(struct pipe_context
*ctx
, void *state
)
710 struct si_context
*sctx
= (struct si_context
*)ctx
;
711 si_pm4_delete_state(sctx
, blend
, (struct si_state_blend
*)state
);
714 static void si_set_blend_color(struct pipe_context
*ctx
,
715 const struct pipe_blend_color
*state
)
717 struct si_context
*sctx
= (struct si_context
*)ctx
;
718 static const struct pipe_blend_color zeros
;
720 sctx
->blend_color
.state
= *state
;
721 sctx
->blend_color
.any_nonzeros
= memcmp(state
, &zeros
, sizeof(*state
)) != 0;
722 si_mark_atom_dirty(sctx
, &sctx
->blend_color
.atom
);
725 static void si_emit_blend_color(struct si_context
*sctx
, struct r600_atom
*atom
)
727 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
729 radeon_set_context_reg_seq(cs
, R_028414_CB_BLEND_RED
, 4);
730 radeon_emit_array(cs
, (uint32_t*)sctx
->blend_color
.state
.color
, 4);
737 static void si_set_clip_state(struct pipe_context
*ctx
,
738 const struct pipe_clip_state
*state
)
740 struct si_context
*sctx
= (struct si_context
*)ctx
;
741 struct pipe_constant_buffer cb
;
742 static const struct pipe_clip_state zeros
;
744 if (memcmp(&sctx
->clip_state
.state
, state
, sizeof(*state
)) == 0)
747 sctx
->clip_state
.state
= *state
;
748 sctx
->clip_state
.any_nonzeros
= memcmp(state
, &zeros
, sizeof(*state
)) != 0;
749 si_mark_atom_dirty(sctx
, &sctx
->clip_state
.atom
);
752 cb
.user_buffer
= state
->ucp
;
753 cb
.buffer_offset
= 0;
754 cb
.buffer_size
= 4*4*8;
755 si_set_rw_buffer(sctx
, SI_VS_CONST_CLIP_PLANES
, &cb
);
756 pipe_resource_reference(&cb
.buffer
, NULL
);
759 static void si_emit_clip_state(struct si_context
*sctx
, struct r600_atom
*atom
)
761 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
763 radeon_set_context_reg_seq(cs
, R_0285BC_PA_CL_UCP_0_X
, 6*4);
764 radeon_emit_array(cs
, (uint32_t*)sctx
->clip_state
.state
.ucp
, 6*4);
767 static void si_emit_clip_regs(struct si_context
*sctx
, struct r600_atom
*atom
)
769 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
770 struct si_shader
*vs
= si_get_vs_state(sctx
);
771 struct si_shader_selector
*vs_sel
= vs
->selector
;
772 struct tgsi_shader_info
*info
= &vs_sel
->info
;
773 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
774 unsigned window_space
=
775 info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
776 unsigned clipdist_mask
= vs_sel
->clipdist_mask
;
777 unsigned ucp_mask
= clipdist_mask
? 0 : rs
->clip_plane_enable
& SIX_BITS
;
778 unsigned culldist_mask
= vs_sel
->culldist_mask
;
781 if (vs
->key
.opt
.clip_disable
) {
782 assert(!info
->culldist_writemask
);
786 total_mask
= clipdist_mask
| culldist_mask
;
788 /* Clip distances on points have no effect, so need to be implemented
789 * as cull distances. This applies for the clipvertex case as well.
791 * Setting this for primitives other than points should have no adverse
794 clipdist_mask
&= rs
->clip_plane_enable
;
795 culldist_mask
|= clipdist_mask
;
797 radeon_set_context_reg(cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
798 vs_sel
->pa_cl_vs_out_cntl
|
799 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0F) != 0) |
800 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xF0) != 0) |
801 clipdist_mask
| (culldist_mask
<< 8));
802 radeon_set_context_reg(cs
, R_028810_PA_CL_CLIP_CNTL
,
803 rs
->pa_cl_clip_cntl
|
805 S_028810_CLIP_DISABLE(window_space
));
809 * inferred state between framebuffer and rasterizer
811 static void si_update_poly_offset_state(struct si_context
*sctx
)
813 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
815 if (!rs
|| !rs
->uses_poly_offset
|| !sctx
->framebuffer
.state
.zsbuf
) {
816 si_pm4_bind_state(sctx
, poly_offset
, NULL
);
820 /* Use the user format, not db_render_format, so that the polygon
821 * offset behaves as expected by applications.
823 switch (sctx
->framebuffer
.state
.zsbuf
->texture
->format
) {
824 case PIPE_FORMAT_Z16_UNORM
:
825 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[0]);
827 default: /* 24-bit */
828 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[1]);
830 case PIPE_FORMAT_Z32_FLOAT
:
831 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
832 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[2]);
841 static uint32_t si_translate_fill(uint32_t func
)
844 case PIPE_POLYGON_MODE_FILL
:
845 return V_028814_X_DRAW_TRIANGLES
;
846 case PIPE_POLYGON_MODE_LINE
:
847 return V_028814_X_DRAW_LINES
;
848 case PIPE_POLYGON_MODE_POINT
:
849 return V_028814_X_DRAW_POINTS
;
852 return V_028814_X_DRAW_POINTS
;
856 static void *si_create_rs_state(struct pipe_context
*ctx
,
857 const struct pipe_rasterizer_state
*state
)
859 struct si_screen
*sscreen
= ((struct si_context
*)ctx
)->screen
;
860 struct si_state_rasterizer
*rs
= CALLOC_STRUCT(si_state_rasterizer
);
861 struct si_pm4_state
*pm4
= &rs
->pm4
;
863 float psize_min
, psize_max
;
869 rs
->scissor_enable
= state
->scissor
;
870 rs
->clip_halfz
= state
->clip_halfz
;
871 rs
->two_side
= state
->light_twoside
;
872 rs
->multisample_enable
= state
->multisample
;
873 rs
->force_persample_interp
= state
->force_persample_interp
;
874 rs
->clip_plane_enable
= state
->clip_plane_enable
;
875 rs
->line_stipple_enable
= state
->line_stipple_enable
;
876 rs
->poly_stipple_enable
= state
->poly_stipple_enable
;
877 rs
->line_smooth
= state
->line_smooth
;
878 rs
->line_width
= state
->line_width
;
879 rs
->poly_smooth
= state
->poly_smooth
;
880 rs
->uses_poly_offset
= state
->offset_point
|| state
->offset_line
||
882 rs
->clamp_fragment_color
= state
->clamp_fragment_color
;
883 rs
->clamp_vertex_color
= state
->clamp_vertex_color
;
884 rs
->flatshade
= state
->flatshade
;
885 rs
->sprite_coord_enable
= state
->sprite_coord_enable
;
886 rs
->rasterizer_discard
= state
->rasterizer_discard
;
887 rs
->pa_sc_line_stipple
= state
->line_stipple_enable
?
888 S_028A0C_LINE_PATTERN(state
->line_stipple_pattern
) |
889 S_028A0C_REPEAT_COUNT(state
->line_stipple_factor
) : 0;
890 rs
->pa_cl_clip_cntl
=
891 S_028810_DX_CLIP_SPACE_DEF(state
->clip_halfz
) |
892 S_028810_ZCLIP_NEAR_DISABLE(!state
->depth_clip
) |
893 S_028810_ZCLIP_FAR_DISABLE(!state
->depth_clip
) |
894 S_028810_DX_RASTERIZATION_KILL(state
->rasterizer_discard
) |
895 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
897 si_pm4_set_reg(pm4
, R_0286D4_SPI_INTERP_CONTROL_0
,
898 S_0286D4_FLAT_SHADE_ENA(1) |
899 S_0286D4_PNT_SPRITE_ENA(1) |
900 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S
) |
901 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T
) |
902 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0
) |
903 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1
) |
904 S_0286D4_PNT_SPRITE_TOP_1(state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
));
906 /* point size 12.4 fixed point */
907 tmp
= (unsigned)(state
->point_size
* 8.0);
908 si_pm4_set_reg(pm4
, R_028A00_PA_SU_POINT_SIZE
, S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
));
910 if (state
->point_size_per_vertex
) {
911 psize_min
= util_get_min_point_size(state
);
914 /* Force the point size to be as if the vertex output was disabled. */
915 psize_min
= state
->point_size
;
916 psize_max
= state
->point_size
;
918 rs
->max_point_size
= psize_max
;
920 /* Divide by two, because 0.5 = 1 pixel. */
921 si_pm4_set_reg(pm4
, R_028A04_PA_SU_POINT_MINMAX
,
922 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min
/2)) |
923 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max
/2)));
925 si_pm4_set_reg(pm4
, R_028A08_PA_SU_LINE_CNTL
,
926 S_028A08_WIDTH(si_pack_float_12p4(state
->line_width
/2)));
927 si_pm4_set_reg(pm4
, R_028A48_PA_SC_MODE_CNTL_0
,
928 S_028A48_LINE_STIPPLE_ENABLE(state
->line_stipple_enable
) |
929 S_028A48_MSAA_ENABLE(state
->multisample
||
930 state
->poly_smooth
||
931 state
->line_smooth
) |
932 S_028A48_VPORT_SCISSOR_ENABLE(1) |
933 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen
->info
.chip_class
>= GFX9
));
935 si_pm4_set_reg(pm4
, R_028BE4_PA_SU_VTX_CNTL
,
936 S_028BE4_PIX_CENTER(state
->half_pixel_center
) |
937 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH
));
939 si_pm4_set_reg(pm4
, R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, fui(state
->offset_clamp
));
940 si_pm4_set_reg(pm4
, R_028814_PA_SU_SC_MODE_CNTL
,
941 S_028814_PROVOKING_VTX_LAST(!state
->flatshade_first
) |
942 S_028814_CULL_FRONT((state
->cull_face
& PIPE_FACE_FRONT
) ? 1 : 0) |
943 S_028814_CULL_BACK((state
->cull_face
& PIPE_FACE_BACK
) ? 1 : 0) |
944 S_028814_FACE(!state
->front_ccw
) |
945 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state
, state
->fill_front
)) |
946 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state
, state
->fill_back
)) |
947 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_point
|| state
->offset_line
) |
948 S_028814_POLY_MODE(state
->fill_front
!= PIPE_POLYGON_MODE_FILL
||
949 state
->fill_back
!= PIPE_POLYGON_MODE_FILL
) |
950 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state
->fill_front
)) |
951 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state
->fill_back
)));
953 if (!rs
->uses_poly_offset
)
956 rs
->pm4_poly_offset
= CALLOC(3, sizeof(struct si_pm4_state
));
957 if (!rs
->pm4_poly_offset
) {
962 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
963 for (i
= 0; i
< 3; i
++) {
964 struct si_pm4_state
*pm4
= &rs
->pm4_poly_offset
[i
];
965 float offset_units
= state
->offset_units
;
966 float offset_scale
= state
->offset_scale
* 16.0f
;
967 uint32_t pa_su_poly_offset_db_fmt_cntl
= 0;
969 if (!state
->offset_units_unscaled
) {
971 case 0: /* 16-bit zbuffer */
972 offset_units
*= 4.0f
;
973 pa_su_poly_offset_db_fmt_cntl
=
974 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
976 case 1: /* 24-bit zbuffer */
977 offset_units
*= 2.0f
;
978 pa_su_poly_offset_db_fmt_cntl
=
979 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
981 case 2: /* 32-bit zbuffer */
982 offset_units
*= 1.0f
;
983 pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
984 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
989 si_pm4_set_reg(pm4
, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE
,
991 si_pm4_set_reg(pm4
, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET
,
993 si_pm4_set_reg(pm4
, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE
,
995 si_pm4_set_reg(pm4
, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET
,
997 si_pm4_set_reg(pm4
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
998 pa_su_poly_offset_db_fmt_cntl
);
1004 static void si_bind_rs_state(struct pipe_context
*ctx
, void *state
)
1006 struct si_context
*sctx
= (struct si_context
*)ctx
;
1007 struct si_state_rasterizer
*old_rs
=
1008 (struct si_state_rasterizer
*)sctx
->queued
.named
.rasterizer
;
1009 struct si_state_rasterizer
*rs
= (struct si_state_rasterizer
*)state
;
1014 if (!old_rs
|| old_rs
->multisample_enable
!= rs
->multisample_enable
) {
1015 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
1017 /* Update the small primitive filter workaround if necessary. */
1018 if (sctx
->screen
->has_msaa_sample_loc_bug
&&
1019 sctx
->framebuffer
.nr_samples
> 1)
1020 si_mark_atom_dirty(sctx
, &sctx
->msaa_sample_locs
.atom
);
1023 sctx
->current_vs_state
&= C_VS_STATE_CLAMP_VERTEX_COLOR
;
1024 sctx
->current_vs_state
|= S_VS_STATE_CLAMP_VERTEX_COLOR(rs
->clamp_vertex_color
);
1026 si_pm4_bind_state(sctx
, rasterizer
, rs
);
1027 si_update_poly_offset_state(sctx
);
1030 (old_rs
->scissor_enable
!= rs
->scissor_enable
||
1031 old_rs
->line_width
!= rs
->line_width
||
1032 old_rs
->max_point_size
!= rs
->max_point_size
)) {
1033 sctx
->scissors
.dirty_mask
= (1 << SI_MAX_VIEWPORTS
) - 1;
1034 si_mark_atom_dirty(sctx
, &sctx
->scissors
.atom
);
1038 old_rs
->clip_halfz
!= rs
->clip_halfz
) {
1039 sctx
->viewports
.depth_range_dirty_mask
= (1 << SI_MAX_VIEWPORTS
) - 1;
1040 si_mark_atom_dirty(sctx
, &sctx
->viewports
.atom
);
1044 old_rs
->clip_plane_enable
!= rs
->clip_plane_enable
||
1045 old_rs
->pa_cl_clip_cntl
!= rs
->pa_cl_clip_cntl
)
1046 si_mark_atom_dirty(sctx
, &sctx
->clip_regs
);
1048 sctx
->ia_multi_vgt_param_key
.u
.line_stipple_enabled
=
1049 rs
->line_stipple_enable
;
1052 old_rs
->clip_plane_enable
!= rs
->clip_plane_enable
||
1053 old_rs
->rasterizer_discard
!= rs
->rasterizer_discard
||
1054 old_rs
->sprite_coord_enable
!= rs
->sprite_coord_enable
||
1055 old_rs
->flatshade
!= rs
->flatshade
||
1056 old_rs
->two_side
!= rs
->two_side
||
1057 old_rs
->multisample_enable
!= rs
->multisample_enable
||
1058 old_rs
->poly_stipple_enable
!= rs
->poly_stipple_enable
||
1059 old_rs
->poly_smooth
!= rs
->poly_smooth
||
1060 old_rs
->line_smooth
!= rs
->line_smooth
||
1061 old_rs
->clamp_fragment_color
!= rs
->clamp_fragment_color
||
1062 old_rs
->force_persample_interp
!= rs
->force_persample_interp
)
1063 sctx
->do_update_shaders
= true;
1066 static void si_delete_rs_state(struct pipe_context
*ctx
, void *state
)
1068 struct si_context
*sctx
= (struct si_context
*)ctx
;
1069 struct si_state_rasterizer
*rs
= (struct si_state_rasterizer
*)state
;
1071 if (sctx
->queued
.named
.rasterizer
== state
)
1072 si_pm4_bind_state(sctx
, poly_offset
, NULL
);
1074 FREE(rs
->pm4_poly_offset
);
1075 si_pm4_delete_state(sctx
, rasterizer
, rs
);
1079 * infeered state between dsa and stencil ref
1081 static void si_emit_stencil_ref(struct si_context
*sctx
, struct r600_atom
*atom
)
1083 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
1084 struct pipe_stencil_ref
*ref
= &sctx
->stencil_ref
.state
;
1085 struct si_dsa_stencil_ref_part
*dsa
= &sctx
->stencil_ref
.dsa_part
;
1087 radeon_set_context_reg_seq(cs
, R_028430_DB_STENCILREFMASK
, 2);
1088 radeon_emit(cs
, S_028430_STENCILTESTVAL(ref
->ref_value
[0]) |
1089 S_028430_STENCILMASK(dsa
->valuemask
[0]) |
1090 S_028430_STENCILWRITEMASK(dsa
->writemask
[0]) |
1091 S_028430_STENCILOPVAL(1));
1092 radeon_emit(cs
, S_028434_STENCILTESTVAL_BF(ref
->ref_value
[1]) |
1093 S_028434_STENCILMASK_BF(dsa
->valuemask
[1]) |
1094 S_028434_STENCILWRITEMASK_BF(dsa
->writemask
[1]) |
1095 S_028434_STENCILOPVAL_BF(1));
1098 static void si_set_stencil_ref(struct pipe_context
*ctx
,
1099 const struct pipe_stencil_ref
*state
)
1101 struct si_context
*sctx
= (struct si_context
*)ctx
;
1103 if (memcmp(&sctx
->stencil_ref
.state
, state
, sizeof(*state
)) == 0)
1106 sctx
->stencil_ref
.state
= *state
;
1107 si_mark_atom_dirty(sctx
, &sctx
->stencil_ref
.atom
);
1115 static uint32_t si_translate_stencil_op(int s_op
)
1118 case PIPE_STENCIL_OP_KEEP
:
1119 return V_02842C_STENCIL_KEEP
;
1120 case PIPE_STENCIL_OP_ZERO
:
1121 return V_02842C_STENCIL_ZERO
;
1122 case PIPE_STENCIL_OP_REPLACE
:
1123 return V_02842C_STENCIL_REPLACE_TEST
;
1124 case PIPE_STENCIL_OP_INCR
:
1125 return V_02842C_STENCIL_ADD_CLAMP
;
1126 case PIPE_STENCIL_OP_DECR
:
1127 return V_02842C_STENCIL_SUB_CLAMP
;
1128 case PIPE_STENCIL_OP_INCR_WRAP
:
1129 return V_02842C_STENCIL_ADD_WRAP
;
1130 case PIPE_STENCIL_OP_DECR_WRAP
:
1131 return V_02842C_STENCIL_SUB_WRAP
;
1132 case PIPE_STENCIL_OP_INVERT
:
1133 return V_02842C_STENCIL_INVERT
;
1135 R600_ERR("Unknown stencil op %d", s_op
);
1142 static bool si_dsa_writes_stencil(const struct pipe_stencil_state
*s
)
1144 return s
->enabled
&& s
->writemask
&&
1145 (s
->fail_op
!= PIPE_STENCIL_OP_KEEP
||
1146 s
->zfail_op
!= PIPE_STENCIL_OP_KEEP
||
1147 s
->zpass_op
!= PIPE_STENCIL_OP_KEEP
);
1150 static bool si_order_invariant_stencil_op(enum pipe_stencil_op op
)
1152 /* REPLACE is normally order invariant, except when the stencil
1153 * reference value is written by the fragment shader. Tracking this
1154 * interaction does not seem worth the effort, so be conservative. */
1155 return op
!= PIPE_STENCIL_OP_INCR
&&
1156 op
!= PIPE_STENCIL_OP_DECR
&&
1157 op
!= PIPE_STENCIL_OP_REPLACE
;
1160 /* Compute whether, assuming Z writes are disabled, this stencil state is order
1161 * invariant in the sense that the set of passing fragments as well as the
1162 * final stencil buffer result does not depend on the order of fragments. */
1163 static bool si_order_invariant_stencil_state(const struct pipe_stencil_state
*state
)
1165 return !state
->enabled
|| !state
->writemask
||
1166 /* The following assumes that Z writes are disabled. */
1167 (state
->func
== PIPE_FUNC_ALWAYS
&&
1168 si_order_invariant_stencil_op(state
->zpass_op
) &&
1169 si_order_invariant_stencil_op(state
->zfail_op
)) ||
1170 (state
->func
== PIPE_FUNC_NEVER
&&
1171 si_order_invariant_stencil_op(state
->fail_op
));
1174 static void *si_create_dsa_state(struct pipe_context
*ctx
,
1175 const struct pipe_depth_stencil_alpha_state
*state
)
1177 struct si_context
*sctx
= (struct si_context
*)ctx
;
1178 struct si_state_dsa
*dsa
= CALLOC_STRUCT(si_state_dsa
);
1179 struct si_pm4_state
*pm4
= &dsa
->pm4
;
1180 unsigned db_depth_control
;
1181 uint32_t db_stencil_control
= 0;
1187 dsa
->stencil_ref
.valuemask
[0] = state
->stencil
[0].valuemask
;
1188 dsa
->stencil_ref
.valuemask
[1] = state
->stencil
[1].valuemask
;
1189 dsa
->stencil_ref
.writemask
[0] = state
->stencil
[0].writemask
;
1190 dsa
->stencil_ref
.writemask
[1] = state
->stencil
[1].writemask
;
1192 db_depth_control
= S_028800_Z_ENABLE(state
->depth
.enabled
) |
1193 S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
1194 S_028800_ZFUNC(state
->depth
.func
) |
1195 S_028800_DEPTH_BOUNDS_ENABLE(state
->depth
.bounds_test
);
1198 if (state
->stencil
[0].enabled
) {
1199 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
1200 db_depth_control
|= S_028800_STENCILFUNC(state
->stencil
[0].func
);
1201 db_stencil_control
|= S_02842C_STENCILFAIL(si_translate_stencil_op(state
->stencil
[0].fail_op
));
1202 db_stencil_control
|= S_02842C_STENCILZPASS(si_translate_stencil_op(state
->stencil
[0].zpass_op
));
1203 db_stencil_control
|= S_02842C_STENCILZFAIL(si_translate_stencil_op(state
->stencil
[0].zfail_op
));
1205 if (state
->stencil
[1].enabled
) {
1206 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
1207 db_depth_control
|= S_028800_STENCILFUNC_BF(state
->stencil
[1].func
);
1208 db_stencil_control
|= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state
->stencil
[1].fail_op
));
1209 db_stencil_control
|= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state
->stencil
[1].zpass_op
));
1210 db_stencil_control
|= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state
->stencil
[1].zfail_op
));
1215 if (state
->alpha
.enabled
) {
1216 dsa
->alpha_func
= state
->alpha
.func
;
1218 si_pm4_set_reg(pm4
, R_00B030_SPI_SHADER_USER_DATA_PS_0
+
1219 SI_SGPR_ALPHA_REF
* 4, fui(state
->alpha
.ref_value
));
1221 dsa
->alpha_func
= PIPE_FUNC_ALWAYS
;
1224 si_pm4_set_reg(pm4
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
1225 if (state
->stencil
[0].enabled
)
1226 si_pm4_set_reg(pm4
, R_02842C_DB_STENCIL_CONTROL
, db_stencil_control
);
1227 if (state
->depth
.bounds_test
) {
1228 si_pm4_set_reg(pm4
, R_028020_DB_DEPTH_BOUNDS_MIN
, fui(state
->depth
.bounds_min
));
1229 si_pm4_set_reg(pm4
, R_028024_DB_DEPTH_BOUNDS_MAX
, fui(state
->depth
.bounds_max
));
1232 dsa
->depth_enabled
= state
->depth
.enabled
;
1233 dsa
->depth_write_enabled
= state
->depth
.enabled
&&
1234 state
->depth
.writemask
;
1235 dsa
->stencil_enabled
= state
->stencil
[0].enabled
;
1236 dsa
->stencil_write_enabled
= state
->stencil
[0].enabled
&&
1237 (si_dsa_writes_stencil(&state
->stencil
[0]) ||
1238 si_dsa_writes_stencil(&state
->stencil
[1]));
1239 dsa
->db_can_write
= dsa
->depth_write_enabled
||
1240 dsa
->stencil_write_enabled
;
1242 bool zfunc_is_ordered
=
1243 state
->depth
.func
== PIPE_FUNC_NEVER
||
1244 state
->depth
.func
== PIPE_FUNC_LESS
||
1245 state
->depth
.func
== PIPE_FUNC_LEQUAL
||
1246 state
->depth
.func
== PIPE_FUNC_GREATER
||
1247 state
->depth
.func
== PIPE_FUNC_GEQUAL
;
1249 bool nozwrite_and_order_invariant_stencil
=
1250 !dsa
->db_can_write
||
1251 (!dsa
->depth_write_enabled
&&
1252 si_order_invariant_stencil_state(&state
->stencil
[0]) &&
1253 si_order_invariant_stencil_state(&state
->stencil
[1]));
1255 dsa
->order_invariance
[1].zs
=
1256 nozwrite_and_order_invariant_stencil
||
1257 (!dsa
->stencil_write_enabled
&& zfunc_is_ordered
);
1258 dsa
->order_invariance
[0].zs
= !dsa
->depth_write_enabled
|| zfunc_is_ordered
;
1260 dsa
->order_invariance
[1].pass_set
=
1261 nozwrite_and_order_invariant_stencil
||
1262 (!dsa
->stencil_write_enabled
&&
1263 (state
->depth
.func
== PIPE_FUNC_ALWAYS
||
1264 state
->depth
.func
== PIPE_FUNC_NEVER
));
1265 dsa
->order_invariance
[0].pass_set
=
1266 !dsa
->depth_write_enabled
||
1267 (state
->depth
.func
== PIPE_FUNC_ALWAYS
||
1268 state
->depth
.func
== PIPE_FUNC_NEVER
);
1270 dsa
->order_invariance
[1].pass_last
=
1271 sctx
->screen
->assume_no_z_fights
&&
1272 !dsa
->stencil_write_enabled
&&
1273 dsa
->depth_write_enabled
&& zfunc_is_ordered
;
1274 dsa
->order_invariance
[0].pass_last
=
1275 sctx
->screen
->assume_no_z_fights
&&
1276 dsa
->depth_write_enabled
&& zfunc_is_ordered
;
1281 static void si_bind_dsa_state(struct pipe_context
*ctx
, void *state
)
1283 struct si_context
*sctx
= (struct si_context
*)ctx
;
1284 struct si_state_dsa
*old_dsa
= sctx
->queued
.named
.dsa
;
1285 struct si_state_dsa
*dsa
= state
;
1290 si_pm4_bind_state(sctx
, dsa
, dsa
);
1292 if (memcmp(&dsa
->stencil_ref
, &sctx
->stencil_ref
.dsa_part
,
1293 sizeof(struct si_dsa_stencil_ref_part
)) != 0) {
1294 sctx
->stencil_ref
.dsa_part
= dsa
->stencil_ref
;
1295 si_mark_atom_dirty(sctx
, &sctx
->stencil_ref
.atom
);
1298 if (!old_dsa
|| old_dsa
->alpha_func
!= dsa
->alpha_func
)
1299 sctx
->do_update_shaders
= true;
1301 if (sctx
->screen
->dpbb_allowed
&&
1303 (old_dsa
->depth_enabled
!= dsa
->depth_enabled
||
1304 old_dsa
->stencil_enabled
!= dsa
->stencil_enabled
||
1305 old_dsa
->db_can_write
!= dsa
->db_can_write
)))
1306 si_mark_atom_dirty(sctx
, &sctx
->dpbb_state
);
1308 if (sctx
->screen
->has_out_of_order_rast
&&
1310 memcmp(old_dsa
->order_invariance
, dsa
->order_invariance
,
1311 sizeof(old_dsa
->order_invariance
))))
1312 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
1315 static void si_delete_dsa_state(struct pipe_context
*ctx
, void *state
)
1317 struct si_context
*sctx
= (struct si_context
*)ctx
;
1318 si_pm4_delete_state(sctx
, dsa
, (struct si_state_dsa
*)state
);
1321 static void *si_create_db_flush_dsa(struct si_context
*sctx
)
1323 struct pipe_depth_stencil_alpha_state dsa
= {};
1325 return sctx
->b
.b
.create_depth_stencil_alpha_state(&sctx
->b
.b
, &dsa
);
1328 /* DB RENDER STATE */
1330 static void si_set_active_query_state(struct pipe_context
*ctx
, boolean enable
)
1332 struct si_context
*sctx
= (struct si_context
*)ctx
;
1334 /* Pipeline stat & streamout queries. */
1336 sctx
->b
.flags
&= ~SI_CONTEXT_STOP_PIPELINE_STATS
;
1337 sctx
->b
.flags
|= SI_CONTEXT_START_PIPELINE_STATS
;
1339 sctx
->b
.flags
&= ~SI_CONTEXT_START_PIPELINE_STATS
;
1340 sctx
->b
.flags
|= SI_CONTEXT_STOP_PIPELINE_STATS
;
1343 /* Occlusion queries. */
1344 if (sctx
->occlusion_queries_disabled
!= !enable
) {
1345 sctx
->occlusion_queries_disabled
= !enable
;
1346 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
1350 static void si_set_occlusion_query_state(struct pipe_context
*ctx
,
1352 bool old_perfect_enable
)
1354 struct si_context
*sctx
= (struct si_context
*)ctx
;
1356 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
1358 bool perfect_enable
= sctx
->b
.num_perfect_occlusion_queries
!= 0;
1360 if (perfect_enable
!= old_perfect_enable
)
1361 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
1364 static void si_save_qbo_state(struct pipe_context
*ctx
, struct r600_qbo_state
*st
)
1366 struct si_context
*sctx
= (struct si_context
*)ctx
;
1368 st
->saved_compute
= sctx
->cs_shader_state
.program
;
1370 si_get_pipe_constant_buffer(sctx
, PIPE_SHADER_COMPUTE
, 0, &st
->saved_const0
);
1371 si_get_shader_buffers(sctx
, PIPE_SHADER_COMPUTE
, 0, 3, st
->saved_ssbo
);
1374 static void si_emit_db_render_state(struct si_context
*sctx
, struct r600_atom
*state
)
1376 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
1377 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
1378 unsigned db_shader_control
;
1380 radeon_set_context_reg_seq(cs
, R_028000_DB_RENDER_CONTROL
, 2);
1382 /* DB_RENDER_CONTROL */
1383 if (sctx
->dbcb_depth_copy_enabled
||
1384 sctx
->dbcb_stencil_copy_enabled
) {
1386 S_028000_DEPTH_COPY(sctx
->dbcb_depth_copy_enabled
) |
1387 S_028000_STENCIL_COPY(sctx
->dbcb_stencil_copy_enabled
) |
1388 S_028000_COPY_CENTROID(1) |
1389 S_028000_COPY_SAMPLE(sctx
->dbcb_copy_sample
));
1390 } else if (sctx
->db_flush_depth_inplace
|| sctx
->db_flush_stencil_inplace
) {
1392 S_028000_DEPTH_COMPRESS_DISABLE(sctx
->db_flush_depth_inplace
) |
1393 S_028000_STENCIL_COMPRESS_DISABLE(sctx
->db_flush_stencil_inplace
));
1396 S_028000_DEPTH_CLEAR_ENABLE(sctx
->db_depth_clear
) |
1397 S_028000_STENCIL_CLEAR_ENABLE(sctx
->db_stencil_clear
));
1400 /* DB_COUNT_CONTROL (occlusion queries) */
1401 if (sctx
->b
.num_occlusion_queries
> 0 &&
1402 !sctx
->occlusion_queries_disabled
) {
1403 bool perfect
= sctx
->b
.num_perfect_occlusion_queries
> 0;
1405 if (sctx
->b
.chip_class
>= CIK
) {
1407 S_028004_PERFECT_ZPASS_COUNTS(perfect
) |
1408 S_028004_SAMPLE_RATE(sctx
->framebuffer
.log_samples
) |
1409 S_028004_ZPASS_ENABLE(1) |
1410 S_028004_SLICE_EVEN_ENABLE(1) |
1411 S_028004_SLICE_ODD_ENABLE(1));
1414 S_028004_PERFECT_ZPASS_COUNTS(perfect
) |
1415 S_028004_SAMPLE_RATE(sctx
->framebuffer
.log_samples
));
1418 /* Disable occlusion queries. */
1419 if (sctx
->b
.chip_class
>= CIK
) {
1422 radeon_emit(cs
, S_028004_ZPASS_INCREMENT_DISABLE(1));
1426 /* DB_RENDER_OVERRIDE2 */
1427 radeon_set_context_reg(cs
, R_028010_DB_RENDER_OVERRIDE2
,
1428 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx
->db_depth_disable_expclear
) |
1429 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx
->db_stencil_disable_expclear
) |
1430 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx
->framebuffer
.nr_samples
>= 4));
1432 db_shader_control
= sctx
->ps_db_shader_control
;
1434 /* Bug workaround for smoothing (overrasterization) on SI. */
1435 if (sctx
->b
.chip_class
== SI
&& sctx
->smoothing_enabled
) {
1436 db_shader_control
&= C_02880C_Z_ORDER
;
1437 db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
);
1440 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1441 if (!rs
|| !rs
->multisample_enable
)
1442 db_shader_control
&= C_02880C_MASK_EXPORT_ENABLE
;
1444 if (sctx
->screen
->has_rbplus
&&
1445 !sctx
->screen
->rbplus_allowed
)
1446 db_shader_control
|= S_02880C_DUAL_QUAD_DISABLE(1);
1448 radeon_set_context_reg(cs
, R_02880C_DB_SHADER_CONTROL
,
1453 * format translation
1455 static uint32_t si_translate_colorformat(enum pipe_format format
)
1457 const struct util_format_description
*desc
= util_format_description(format
);
1459 return V_028C70_COLOR_INVALID
;
1461 #define HAS_SIZE(x,y,z,w) \
1462 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1463 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1465 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
1466 return V_028C70_COLOR_10_11_11
;
1468 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
1469 return V_028C70_COLOR_INVALID
;
1471 /* hw cannot support mixed formats (except depth/stencil, since
1472 * stencil is not written to). */
1473 if (desc
->is_mixed
&& desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
)
1474 return V_028C70_COLOR_INVALID
;
1476 switch (desc
->nr_channels
) {
1478 switch (desc
->channel
[0].size
) {
1480 return V_028C70_COLOR_8
;
1482 return V_028C70_COLOR_16
;
1484 return V_028C70_COLOR_32
;
1488 if (desc
->channel
[0].size
== desc
->channel
[1].size
) {
1489 switch (desc
->channel
[0].size
) {
1491 return V_028C70_COLOR_8_8
;
1493 return V_028C70_COLOR_16_16
;
1495 return V_028C70_COLOR_32_32
;
1497 } else if (HAS_SIZE(8,24,0,0)) {
1498 return V_028C70_COLOR_24_8
;
1499 } else if (HAS_SIZE(24,8,0,0)) {
1500 return V_028C70_COLOR_8_24
;
1504 if (HAS_SIZE(5,6,5,0)) {
1505 return V_028C70_COLOR_5_6_5
;
1506 } else if (HAS_SIZE(32,8,24,0)) {
1507 return V_028C70_COLOR_X24_8_32_FLOAT
;
1511 if (desc
->channel
[0].size
== desc
->channel
[1].size
&&
1512 desc
->channel
[0].size
== desc
->channel
[2].size
&&
1513 desc
->channel
[0].size
== desc
->channel
[3].size
) {
1514 switch (desc
->channel
[0].size
) {
1516 return V_028C70_COLOR_4_4_4_4
;
1518 return V_028C70_COLOR_8_8_8_8
;
1520 return V_028C70_COLOR_16_16_16_16
;
1522 return V_028C70_COLOR_32_32_32_32
;
1524 } else if (HAS_SIZE(5,5,5,1)) {
1525 return V_028C70_COLOR_1_5_5_5
;
1526 } else if (HAS_SIZE(1,5,5,5)) {
1527 return V_028C70_COLOR_5_5_5_1
;
1528 } else if (HAS_SIZE(10,10,10,2)) {
1529 return V_028C70_COLOR_2_10_10_10
;
1533 return V_028C70_COLOR_INVALID
;
1536 static uint32_t si_colorformat_endian_swap(uint32_t colorformat
)
1538 if (SI_BIG_ENDIAN
) {
1539 switch(colorformat
) {
1540 /* 8-bit buffers. */
1541 case V_028C70_COLOR_8
:
1542 return V_028C70_ENDIAN_NONE
;
1544 /* 16-bit buffers. */
1545 case V_028C70_COLOR_5_6_5
:
1546 case V_028C70_COLOR_1_5_5_5
:
1547 case V_028C70_COLOR_4_4_4_4
:
1548 case V_028C70_COLOR_16
:
1549 case V_028C70_COLOR_8_8
:
1550 return V_028C70_ENDIAN_8IN16
;
1552 /* 32-bit buffers. */
1553 case V_028C70_COLOR_8_8_8_8
:
1554 case V_028C70_COLOR_2_10_10_10
:
1555 case V_028C70_COLOR_8_24
:
1556 case V_028C70_COLOR_24_8
:
1557 case V_028C70_COLOR_16_16
:
1558 return V_028C70_ENDIAN_8IN32
;
1560 /* 64-bit buffers. */
1561 case V_028C70_COLOR_16_16_16_16
:
1562 return V_028C70_ENDIAN_8IN16
;
1564 case V_028C70_COLOR_32_32
:
1565 return V_028C70_ENDIAN_8IN32
;
1567 /* 128-bit buffers. */
1568 case V_028C70_COLOR_32_32_32_32
:
1569 return V_028C70_ENDIAN_8IN32
;
1571 return V_028C70_ENDIAN_NONE
; /* Unsupported. */
1574 return V_028C70_ENDIAN_NONE
;
1578 static uint32_t si_translate_dbformat(enum pipe_format format
)
1581 case PIPE_FORMAT_Z16_UNORM
:
1582 return V_028040_Z_16
;
1583 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1584 case PIPE_FORMAT_X8Z24_UNORM
:
1585 case PIPE_FORMAT_Z24X8_UNORM
:
1586 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1587 return V_028040_Z_24
; /* deprecated on SI */
1588 case PIPE_FORMAT_Z32_FLOAT
:
1589 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1590 return V_028040_Z_32_FLOAT
;
1592 return V_028040_Z_INVALID
;
1597 * Texture translation
1600 static uint32_t si_translate_texformat(struct pipe_screen
*screen
,
1601 enum pipe_format format
,
1602 const struct util_format_description
*desc
,
1605 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1606 bool enable_compressed_formats
= (sscreen
->info
.drm_major
== 2 &&
1607 sscreen
->info
.drm_minor
>= 31) ||
1608 sscreen
->info
.drm_major
== 3;
1609 bool uniform
= true;
1612 /* Colorspace (return non-RGB formats directly). */
1613 switch (desc
->colorspace
) {
1614 /* Depth stencil formats */
1615 case UTIL_FORMAT_COLORSPACE_ZS
:
1617 case PIPE_FORMAT_Z16_UNORM
:
1618 return V_008F14_IMG_DATA_FORMAT_16
;
1619 case PIPE_FORMAT_X24S8_UINT
:
1620 case PIPE_FORMAT_S8X24_UINT
:
1622 * Implemented as an 8_8_8_8 data format to fix texture
1623 * gathers in stencil sampling. This affects at least
1624 * GL45-CTS.texture_cube_map_array.sampling on VI.
1626 return V_008F14_IMG_DATA_FORMAT_8_8_8_8
;
1627 case PIPE_FORMAT_Z24X8_UNORM
:
1628 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1629 return V_008F14_IMG_DATA_FORMAT_8_24
;
1630 case PIPE_FORMAT_X8Z24_UNORM
:
1631 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1632 return V_008F14_IMG_DATA_FORMAT_24_8
;
1633 case PIPE_FORMAT_S8_UINT
:
1634 return V_008F14_IMG_DATA_FORMAT_8
;
1635 case PIPE_FORMAT_Z32_FLOAT
:
1636 return V_008F14_IMG_DATA_FORMAT_32
;
1637 case PIPE_FORMAT_X32_S8X24_UINT
:
1638 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1639 return V_008F14_IMG_DATA_FORMAT_X24_8_32
;
1644 case UTIL_FORMAT_COLORSPACE_YUV
:
1645 goto out_unknown
; /* TODO */
1647 case UTIL_FORMAT_COLORSPACE_SRGB
:
1648 if (desc
->nr_channels
!= 4 && desc
->nr_channels
!= 1)
1656 if (desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
) {
1657 if (!enable_compressed_formats
)
1661 case PIPE_FORMAT_RGTC1_SNORM
:
1662 case PIPE_FORMAT_LATC1_SNORM
:
1663 case PIPE_FORMAT_RGTC1_UNORM
:
1664 case PIPE_FORMAT_LATC1_UNORM
:
1665 return V_008F14_IMG_DATA_FORMAT_BC4
;
1666 case PIPE_FORMAT_RGTC2_SNORM
:
1667 case PIPE_FORMAT_LATC2_SNORM
:
1668 case PIPE_FORMAT_RGTC2_UNORM
:
1669 case PIPE_FORMAT_LATC2_UNORM
:
1670 return V_008F14_IMG_DATA_FORMAT_BC5
;
1676 if (desc
->layout
== UTIL_FORMAT_LAYOUT_ETC
&&
1677 (sscreen
->info
.family
== CHIP_STONEY
||
1678 sscreen
->info
.chip_class
>= GFX9
)) {
1680 case PIPE_FORMAT_ETC1_RGB8
:
1681 case PIPE_FORMAT_ETC2_RGB8
:
1682 case PIPE_FORMAT_ETC2_SRGB8
:
1683 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB
;
1684 case PIPE_FORMAT_ETC2_RGB8A1
:
1685 case PIPE_FORMAT_ETC2_SRGB8A1
:
1686 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1
;
1687 case PIPE_FORMAT_ETC2_RGBA8
:
1688 case PIPE_FORMAT_ETC2_SRGBA8
:
1689 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA
;
1690 case PIPE_FORMAT_ETC2_R11_UNORM
:
1691 case PIPE_FORMAT_ETC2_R11_SNORM
:
1692 return V_008F14_IMG_DATA_FORMAT_ETC2_R
;
1693 case PIPE_FORMAT_ETC2_RG11_UNORM
:
1694 case PIPE_FORMAT_ETC2_RG11_SNORM
:
1695 return V_008F14_IMG_DATA_FORMAT_ETC2_RG
;
1701 if (desc
->layout
== UTIL_FORMAT_LAYOUT_BPTC
) {
1702 if (!enable_compressed_formats
)
1706 case PIPE_FORMAT_BPTC_RGBA_UNORM
:
1707 case PIPE_FORMAT_BPTC_SRGBA
:
1708 return V_008F14_IMG_DATA_FORMAT_BC7
;
1709 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
1710 case PIPE_FORMAT_BPTC_RGB_UFLOAT
:
1711 return V_008F14_IMG_DATA_FORMAT_BC6
;
1717 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
1719 case PIPE_FORMAT_R8G8_B8G8_UNORM
:
1720 case PIPE_FORMAT_G8R8_B8R8_UNORM
:
1721 return V_008F14_IMG_DATA_FORMAT_GB_GR
;
1722 case PIPE_FORMAT_G8R8_G8B8_UNORM
:
1723 case PIPE_FORMAT_R8G8_R8B8_UNORM
:
1724 return V_008F14_IMG_DATA_FORMAT_BG_RG
;
1730 if (desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
1731 if (!enable_compressed_formats
)
1735 case PIPE_FORMAT_DXT1_RGB
:
1736 case PIPE_FORMAT_DXT1_RGBA
:
1737 case PIPE_FORMAT_DXT1_SRGB
:
1738 case PIPE_FORMAT_DXT1_SRGBA
:
1739 return V_008F14_IMG_DATA_FORMAT_BC1
;
1740 case PIPE_FORMAT_DXT3_RGBA
:
1741 case PIPE_FORMAT_DXT3_SRGBA
:
1742 return V_008F14_IMG_DATA_FORMAT_BC2
;
1743 case PIPE_FORMAT_DXT5_RGBA
:
1744 case PIPE_FORMAT_DXT5_SRGBA
:
1745 return V_008F14_IMG_DATA_FORMAT_BC3
;
1751 if (format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
1752 return V_008F14_IMG_DATA_FORMAT_5_9_9_9
;
1753 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
1754 return V_008F14_IMG_DATA_FORMAT_10_11_11
;
1757 /* R8G8Bx_SNORM - TODO CxV8U8 */
1759 /* hw cannot support mixed formats (except depth/stencil, since only
1761 if (desc
->is_mixed
&& desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
)
1764 /* See whether the components are of the same size. */
1765 for (i
= 1; i
< desc
->nr_channels
; i
++) {
1766 uniform
= uniform
&& desc
->channel
[0].size
== desc
->channel
[i
].size
;
1769 /* Non-uniform formats. */
1771 switch(desc
->nr_channels
) {
1773 if (desc
->channel
[0].size
== 5 &&
1774 desc
->channel
[1].size
== 6 &&
1775 desc
->channel
[2].size
== 5) {
1776 return V_008F14_IMG_DATA_FORMAT_5_6_5
;
1780 if (desc
->channel
[0].size
== 5 &&
1781 desc
->channel
[1].size
== 5 &&
1782 desc
->channel
[2].size
== 5 &&
1783 desc
->channel
[3].size
== 1) {
1784 return V_008F14_IMG_DATA_FORMAT_1_5_5_5
;
1786 if (desc
->channel
[0].size
== 1 &&
1787 desc
->channel
[1].size
== 5 &&
1788 desc
->channel
[2].size
== 5 &&
1789 desc
->channel
[3].size
== 5) {
1790 return V_008F14_IMG_DATA_FORMAT_5_5_5_1
;
1792 if (desc
->channel
[0].size
== 10 &&
1793 desc
->channel
[1].size
== 10 &&
1794 desc
->channel
[2].size
== 10 &&
1795 desc
->channel
[3].size
== 2) {
1796 return V_008F14_IMG_DATA_FORMAT_2_10_10_10
;
1803 if (first_non_void
< 0 || first_non_void
> 3)
1806 /* uniform formats */
1807 switch (desc
->channel
[first_non_void
].size
) {
1809 switch (desc
->nr_channels
) {
1810 #if 0 /* Not supported for render targets */
1812 return V_008F14_IMG_DATA_FORMAT_4_4
;
1815 return V_008F14_IMG_DATA_FORMAT_4_4_4_4
;
1819 switch (desc
->nr_channels
) {
1821 return V_008F14_IMG_DATA_FORMAT_8
;
1823 return V_008F14_IMG_DATA_FORMAT_8_8
;
1825 return V_008F14_IMG_DATA_FORMAT_8_8_8_8
;
1829 switch (desc
->nr_channels
) {
1831 return V_008F14_IMG_DATA_FORMAT_16
;
1833 return V_008F14_IMG_DATA_FORMAT_16_16
;
1835 return V_008F14_IMG_DATA_FORMAT_16_16_16_16
;
1839 switch (desc
->nr_channels
) {
1841 return V_008F14_IMG_DATA_FORMAT_32
;
1843 return V_008F14_IMG_DATA_FORMAT_32_32
;
1844 #if 0 /* Not supported for render targets */
1846 return V_008F14_IMG_DATA_FORMAT_32_32_32
;
1849 return V_008F14_IMG_DATA_FORMAT_32_32_32_32
;
1854 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1858 static unsigned si_tex_wrap(unsigned wrap
)
1862 case PIPE_TEX_WRAP_REPEAT
:
1863 return V_008F30_SQ_TEX_WRAP
;
1864 case PIPE_TEX_WRAP_CLAMP
:
1865 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER
;
1866 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
1867 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL
;
1868 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
1869 return V_008F30_SQ_TEX_CLAMP_BORDER
;
1870 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
1871 return V_008F30_SQ_TEX_MIRROR
;
1872 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
1873 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
1874 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
1875 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
1876 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
1877 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER
;
1881 static unsigned si_tex_mipfilter(unsigned filter
)
1884 case PIPE_TEX_MIPFILTER_NEAREST
:
1885 return V_008F38_SQ_TEX_Z_FILTER_POINT
;
1886 case PIPE_TEX_MIPFILTER_LINEAR
:
1887 return V_008F38_SQ_TEX_Z_FILTER_LINEAR
;
1889 case PIPE_TEX_MIPFILTER_NONE
:
1890 return V_008F38_SQ_TEX_Z_FILTER_NONE
;
1894 static unsigned si_tex_compare(unsigned compare
)
1898 case PIPE_FUNC_NEVER
:
1899 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
1900 case PIPE_FUNC_LESS
:
1901 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS
;
1902 case PIPE_FUNC_EQUAL
:
1903 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL
;
1904 case PIPE_FUNC_LEQUAL
:
1905 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
1906 case PIPE_FUNC_GREATER
:
1907 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER
;
1908 case PIPE_FUNC_NOTEQUAL
:
1909 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
1910 case PIPE_FUNC_GEQUAL
:
1911 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
1912 case PIPE_FUNC_ALWAYS
:
1913 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
1917 static unsigned si_tex_dim(struct si_screen
*sscreen
, struct r600_texture
*rtex
,
1918 unsigned view_target
, unsigned nr_samples
)
1920 unsigned res_target
= rtex
->resource
.b
.b
.target
;
1922 if (view_target
== PIPE_TEXTURE_CUBE
||
1923 view_target
== PIPE_TEXTURE_CUBE_ARRAY
)
1924 res_target
= view_target
;
1925 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1926 else if (res_target
== PIPE_TEXTURE_CUBE
||
1927 res_target
== PIPE_TEXTURE_CUBE_ARRAY
)
1928 res_target
= PIPE_TEXTURE_2D_ARRAY
;
1930 /* GFX9 allocates 1D textures as 2D. */
1931 if ((res_target
== PIPE_TEXTURE_1D
||
1932 res_target
== PIPE_TEXTURE_1D_ARRAY
) &&
1933 sscreen
->info
.chip_class
>= GFX9
&&
1934 rtex
->surface
.u
.gfx9
.resource_type
== RADEON_RESOURCE_2D
) {
1935 if (res_target
== PIPE_TEXTURE_1D
)
1936 res_target
= PIPE_TEXTURE_2D
;
1938 res_target
= PIPE_TEXTURE_2D_ARRAY
;
1941 switch (res_target
) {
1943 case PIPE_TEXTURE_1D
:
1944 return V_008F1C_SQ_RSRC_IMG_1D
;
1945 case PIPE_TEXTURE_1D_ARRAY
:
1946 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY
;
1947 case PIPE_TEXTURE_2D
:
1948 case PIPE_TEXTURE_RECT
:
1949 return nr_samples
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA
:
1950 V_008F1C_SQ_RSRC_IMG_2D
;
1951 case PIPE_TEXTURE_2D_ARRAY
:
1952 return nr_samples
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
:
1953 V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
1954 case PIPE_TEXTURE_3D
:
1955 return V_008F1C_SQ_RSRC_IMG_3D
;
1956 case PIPE_TEXTURE_CUBE
:
1957 case PIPE_TEXTURE_CUBE_ARRAY
:
1958 return V_008F1C_SQ_RSRC_IMG_CUBE
;
1963 * Format support testing
1966 static bool si_is_sampler_format_supported(struct pipe_screen
*screen
, enum pipe_format format
)
1968 const struct util_format_description
*desc
= util_format_description(format
);
1972 return si_translate_texformat(screen
, format
, desc
,
1973 util_format_get_first_non_void_channel(format
)) != ~0U;
1976 static uint32_t si_translate_buffer_dataformat(struct pipe_screen
*screen
,
1977 const struct util_format_description
*desc
,
1982 if (desc
->format
== PIPE_FORMAT_R11G11B10_FLOAT
)
1983 return V_008F0C_BUF_DATA_FORMAT_10_11_11
;
1985 assert(first_non_void
>= 0);
1987 if (desc
->nr_channels
== 4 &&
1988 desc
->channel
[0].size
== 10 &&
1989 desc
->channel
[1].size
== 10 &&
1990 desc
->channel
[2].size
== 10 &&
1991 desc
->channel
[3].size
== 2)
1992 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10
;
1994 /* See whether the components are of the same size. */
1995 for (i
= 0; i
< desc
->nr_channels
; i
++) {
1996 if (desc
->channel
[first_non_void
].size
!= desc
->channel
[i
].size
)
1997 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
2000 switch (desc
->channel
[first_non_void
].size
) {
2002 switch (desc
->nr_channels
) {
2004 case 3: /* 3 loads */
2005 return V_008F0C_BUF_DATA_FORMAT_8
;
2007 return V_008F0C_BUF_DATA_FORMAT_8_8
;
2009 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8
;
2013 switch (desc
->nr_channels
) {
2015 case 3: /* 3 loads */
2016 return V_008F0C_BUF_DATA_FORMAT_16
;
2018 return V_008F0C_BUF_DATA_FORMAT_16_16
;
2020 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16
;
2024 switch (desc
->nr_channels
) {
2026 return V_008F0C_BUF_DATA_FORMAT_32
;
2028 return V_008F0C_BUF_DATA_FORMAT_32_32
;
2030 return V_008F0C_BUF_DATA_FORMAT_32_32_32
;
2032 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
2036 /* Legacy double formats. */
2037 switch (desc
->nr_channels
) {
2038 case 1: /* 1 load */
2039 return V_008F0C_BUF_DATA_FORMAT_32_32
;
2040 case 2: /* 1 load */
2041 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
2042 case 3: /* 3 loads */
2043 return V_008F0C_BUF_DATA_FORMAT_32_32
;
2044 case 4: /* 2 loads */
2045 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
2050 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
2053 static uint32_t si_translate_buffer_numformat(struct pipe_screen
*screen
,
2054 const struct util_format_description
*desc
,
2057 if (desc
->format
== PIPE_FORMAT_R11G11B10_FLOAT
)
2058 return V_008F0C_BUF_NUM_FORMAT_FLOAT
;
2060 assert(first_non_void
>= 0);
2062 switch (desc
->channel
[first_non_void
].type
) {
2063 case UTIL_FORMAT_TYPE_SIGNED
:
2064 case UTIL_FORMAT_TYPE_FIXED
:
2065 if (desc
->channel
[first_non_void
].size
>= 32 ||
2066 desc
->channel
[first_non_void
].pure_integer
)
2067 return V_008F0C_BUF_NUM_FORMAT_SINT
;
2068 else if (desc
->channel
[first_non_void
].normalized
)
2069 return V_008F0C_BUF_NUM_FORMAT_SNORM
;
2071 return V_008F0C_BUF_NUM_FORMAT_SSCALED
;
2073 case UTIL_FORMAT_TYPE_UNSIGNED
:
2074 if (desc
->channel
[first_non_void
].size
>= 32 ||
2075 desc
->channel
[first_non_void
].pure_integer
)
2076 return V_008F0C_BUF_NUM_FORMAT_UINT
;
2077 else if (desc
->channel
[first_non_void
].normalized
)
2078 return V_008F0C_BUF_NUM_FORMAT_UNORM
;
2080 return V_008F0C_BUF_NUM_FORMAT_USCALED
;
2082 case UTIL_FORMAT_TYPE_FLOAT
:
2084 return V_008F0C_BUF_NUM_FORMAT_FLOAT
;
2088 static unsigned si_is_vertex_format_supported(struct pipe_screen
*screen
,
2089 enum pipe_format format
,
2092 const struct util_format_description
*desc
;
2094 unsigned data_format
;
2096 assert((usage
& ~(PIPE_BIND_SHADER_IMAGE
|
2097 PIPE_BIND_SAMPLER_VIEW
|
2098 PIPE_BIND_VERTEX_BUFFER
)) == 0);
2100 desc
= util_format_description(format
);
2104 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
2105 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
2106 * for read-only access (with caveats surrounding bounds checks), but
2107 * obviously fails for write access which we have to implement for
2108 * shader images. Luckily, OpenGL doesn't expect this to be supported
2109 * anyway, and so the only impact is on PBO uploads / downloads, which
2110 * shouldn't be expected to be fast for GL_RGB anyway.
2112 if (desc
->block
.bits
== 3 * 8 ||
2113 desc
->block
.bits
== 3 * 16) {
2114 if (usage
& (PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SAMPLER_VIEW
)) {
2115 usage
&= ~(PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SAMPLER_VIEW
);
2121 first_non_void
= util_format_get_first_non_void_channel(format
);
2122 data_format
= si_translate_buffer_dataformat(screen
, desc
, first_non_void
);
2123 if (data_format
== V_008F0C_BUF_DATA_FORMAT_INVALID
)
2129 static bool si_is_colorbuffer_format_supported(enum pipe_format format
)
2131 return si_translate_colorformat(format
) != V_028C70_COLOR_INVALID
&&
2132 si_translate_colorswap(format
, false) != ~0U;
2135 static bool si_is_zs_format_supported(enum pipe_format format
)
2137 return si_translate_dbformat(format
) != V_028040_Z_INVALID
;
2140 static boolean
si_is_format_supported(struct pipe_screen
*screen
,
2141 enum pipe_format format
,
2142 enum pipe_texture_target target
,
2143 unsigned sample_count
,
2146 unsigned retval
= 0;
2148 if (target
>= PIPE_MAX_TEXTURE_TYPES
) {
2149 R600_ERR("r600: unsupported texture type %d\n", target
);
2153 if (!util_format_is_supported(format
, usage
))
2156 if (sample_count
> 1) {
2157 if (!screen
->get_param(screen
, PIPE_CAP_TEXTURE_MULTISAMPLE
))
2160 if (usage
& PIPE_BIND_SHADER_IMAGE
)
2163 switch (sample_count
) {
2169 if (format
== PIPE_FORMAT_NONE
)
2178 if (usage
& (PIPE_BIND_SAMPLER_VIEW
|
2179 PIPE_BIND_SHADER_IMAGE
)) {
2180 if (target
== PIPE_BUFFER
) {
2181 retval
|= si_is_vertex_format_supported(
2182 screen
, format
, usage
& (PIPE_BIND_SAMPLER_VIEW
|
2183 PIPE_BIND_SHADER_IMAGE
));
2185 if (si_is_sampler_format_supported(screen
, format
))
2186 retval
|= usage
& (PIPE_BIND_SAMPLER_VIEW
|
2187 PIPE_BIND_SHADER_IMAGE
);
2191 if ((usage
& (PIPE_BIND_RENDER_TARGET
|
2192 PIPE_BIND_DISPLAY_TARGET
|
2195 PIPE_BIND_BLENDABLE
)) &&
2196 si_is_colorbuffer_format_supported(format
)) {
2198 (PIPE_BIND_RENDER_TARGET
|
2199 PIPE_BIND_DISPLAY_TARGET
|
2202 if (!util_format_is_pure_integer(format
) &&
2203 !util_format_is_depth_or_stencil(format
))
2204 retval
|= usage
& PIPE_BIND_BLENDABLE
;
2207 if ((usage
& PIPE_BIND_DEPTH_STENCIL
) &&
2208 si_is_zs_format_supported(format
)) {
2209 retval
|= PIPE_BIND_DEPTH_STENCIL
;
2212 if (usage
& PIPE_BIND_VERTEX_BUFFER
) {
2213 retval
|= si_is_vertex_format_supported(screen
, format
,
2214 PIPE_BIND_VERTEX_BUFFER
);
2217 if ((usage
& PIPE_BIND_LINEAR
) &&
2218 !util_format_is_compressed(format
) &&
2219 !(usage
& PIPE_BIND_DEPTH_STENCIL
))
2220 retval
|= PIPE_BIND_LINEAR
;
2222 return retval
== usage
;
2226 * framebuffer handling
2229 static void si_choose_spi_color_formats(struct r600_surface
*surf
,
2230 unsigned format
, unsigned swap
,
2231 unsigned ntype
, bool is_depth
)
2233 /* Alpha is needed for alpha-to-coverage.
2234 * Blending may be with or without alpha.
2236 unsigned normal
= 0; /* most optimal, may not support blending or export alpha */
2237 unsigned alpha
= 0; /* exports alpha, but may not support blending */
2238 unsigned blend
= 0; /* supports blending, but may not export alpha */
2239 unsigned blend_alpha
= 0; /* least optimal, supports blending and exports alpha */
2241 /* Choose the SPI color formats. These are required values for RB+.
2242 * Other chips have multiple choices, though they are not necessarily better.
2245 case V_028C70_COLOR_5_6_5
:
2246 case V_028C70_COLOR_1_5_5_5
:
2247 case V_028C70_COLOR_5_5_5_1
:
2248 case V_028C70_COLOR_4_4_4_4
:
2249 case V_028C70_COLOR_10_11_11
:
2250 case V_028C70_COLOR_11_11_10
:
2251 case V_028C70_COLOR_8
:
2252 case V_028C70_COLOR_8_8
:
2253 case V_028C70_COLOR_8_8_8_8
:
2254 case V_028C70_COLOR_10_10_10_2
:
2255 case V_028C70_COLOR_2_10_10_10
:
2256 if (ntype
== V_028C70_NUMBER_UINT
)
2257 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
2258 else if (ntype
== V_028C70_NUMBER_SINT
)
2259 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
2261 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
2264 case V_028C70_COLOR_16
:
2265 case V_028C70_COLOR_16_16
:
2266 case V_028C70_COLOR_16_16_16_16
:
2267 if (ntype
== V_028C70_NUMBER_UNORM
||
2268 ntype
== V_028C70_NUMBER_SNORM
) {
2269 /* UNORM16 and SNORM16 don't support blending */
2270 if (ntype
== V_028C70_NUMBER_UNORM
)
2271 normal
= alpha
= V_028714_SPI_SHADER_UNORM16_ABGR
;
2273 normal
= alpha
= V_028714_SPI_SHADER_SNORM16_ABGR
;
2275 /* Use 32 bits per channel for blending. */
2276 if (format
== V_028C70_COLOR_16
) {
2277 if (swap
== V_028C70_SWAP_STD
) { /* R */
2278 blend
= V_028714_SPI_SHADER_32_R
;
2279 blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2280 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
2281 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2284 } else if (format
== V_028C70_COLOR_16_16
) {
2285 if (swap
== V_028C70_SWAP_STD
) { /* RG */
2286 blend
= V_028714_SPI_SHADER_32_GR
;
2287 blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2288 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
2289 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2292 } else /* 16_16_16_16 */
2293 blend
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2294 } else if (ntype
== V_028C70_NUMBER_UINT
)
2295 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
2296 else if (ntype
== V_028C70_NUMBER_SINT
)
2297 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
2298 else if (ntype
== V_028C70_NUMBER_FLOAT
)
2299 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
2304 case V_028C70_COLOR_32
:
2305 if (swap
== V_028C70_SWAP_STD
) { /* R */
2306 blend
= normal
= V_028714_SPI_SHADER_32_R
;
2307 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2308 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
2309 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
2314 case V_028C70_COLOR_32_32
:
2315 if (swap
== V_028C70_SWAP_STD
) { /* RG */
2316 blend
= normal
= V_028714_SPI_SHADER_32_GR
;
2317 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2318 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
2319 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
2324 case V_028C70_COLOR_32_32_32_32
:
2325 case V_028C70_COLOR_8_24
:
2326 case V_028C70_COLOR_24_8
:
2327 case V_028C70_COLOR_X24_8_32_FLOAT
:
2328 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
2336 /* The DB->CB copy needs 32_ABGR. */
2338 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
2340 surf
->spi_shader_col_format
= normal
;
2341 surf
->spi_shader_col_format_alpha
= alpha
;
2342 surf
->spi_shader_col_format_blend
= blend
;
2343 surf
->spi_shader_col_format_blend_alpha
= blend_alpha
;
2346 static void si_initialize_color_surface(struct si_context
*sctx
,
2347 struct r600_surface
*surf
)
2349 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->base
.texture
;
2350 unsigned color_info
, color_attrib
;
2351 unsigned format
, swap
, ntype
, endian
;
2352 const struct util_format_description
*desc
;
2354 unsigned blend_clamp
= 0, blend_bypass
= 0;
2356 desc
= util_format_description(surf
->base
.format
);
2357 for (firstchan
= 0; firstchan
< 4; firstchan
++) {
2358 if (desc
->channel
[firstchan
].type
!= UTIL_FORMAT_TYPE_VOID
) {
2362 if (firstchan
== 4 || desc
->channel
[firstchan
].type
== UTIL_FORMAT_TYPE_FLOAT
) {
2363 ntype
= V_028C70_NUMBER_FLOAT
;
2365 ntype
= V_028C70_NUMBER_UNORM
;
2366 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
2367 ntype
= V_028C70_NUMBER_SRGB
;
2368 else if (desc
->channel
[firstchan
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2369 if (desc
->channel
[firstchan
].pure_integer
) {
2370 ntype
= V_028C70_NUMBER_SINT
;
2372 assert(desc
->channel
[firstchan
].normalized
);
2373 ntype
= V_028C70_NUMBER_SNORM
;
2375 } else if (desc
->channel
[firstchan
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
2376 if (desc
->channel
[firstchan
].pure_integer
) {
2377 ntype
= V_028C70_NUMBER_UINT
;
2379 assert(desc
->channel
[firstchan
].normalized
);
2380 ntype
= V_028C70_NUMBER_UNORM
;
2385 format
= si_translate_colorformat(surf
->base
.format
);
2386 if (format
== V_028C70_COLOR_INVALID
) {
2387 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf
->base
.format
);
2389 assert(format
!= V_028C70_COLOR_INVALID
);
2390 swap
= si_translate_colorswap(surf
->base
.format
, false);
2391 endian
= si_colorformat_endian_swap(format
);
2393 /* blend clamp should be set for all NORM/SRGB types */
2394 if (ntype
== V_028C70_NUMBER_UNORM
||
2395 ntype
== V_028C70_NUMBER_SNORM
||
2396 ntype
== V_028C70_NUMBER_SRGB
)
2399 /* set blend bypass according to docs if SINT/UINT or
2400 8/24 COLOR variants */
2401 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
2402 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
2403 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
2408 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
) {
2409 if (format
== V_028C70_COLOR_8
||
2410 format
== V_028C70_COLOR_8_8
||
2411 format
== V_028C70_COLOR_8_8_8_8
)
2412 surf
->color_is_int8
= true;
2413 else if (format
== V_028C70_COLOR_10_10_10_2
||
2414 format
== V_028C70_COLOR_2_10_10_10
)
2415 surf
->color_is_int10
= true;
2418 color_info
= S_028C70_FORMAT(format
) |
2419 S_028C70_COMP_SWAP(swap
) |
2420 S_028C70_BLEND_CLAMP(blend_clamp
) |
2421 S_028C70_BLEND_BYPASS(blend_bypass
) |
2422 S_028C70_SIMPLE_FLOAT(1) |
2423 S_028C70_ROUND_MODE(ntype
!= V_028C70_NUMBER_UNORM
&&
2424 ntype
!= V_028C70_NUMBER_SNORM
&&
2425 ntype
!= V_028C70_NUMBER_SRGB
&&
2426 format
!= V_028C70_COLOR_8_24
&&
2427 format
!= V_028C70_COLOR_24_8
) |
2428 S_028C70_NUMBER_TYPE(ntype
) |
2429 S_028C70_ENDIAN(endian
);
2431 /* Intensity is implemented as Red, so treat it that way. */
2432 color_attrib
= S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] == PIPE_SWIZZLE_1
||
2433 util_format_is_intensity(surf
->base
.format
));
2435 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
2436 unsigned log_samples
= util_logbase2(rtex
->resource
.b
.b
.nr_samples
);
2438 color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
2439 S_028C74_NUM_FRAGMENTS(log_samples
);
2441 if (rtex
->fmask
.size
) {
2442 color_info
|= S_028C70_COMPRESSION(1);
2443 unsigned fmask_bankh
= util_logbase2(rtex
->fmask
.bank_height
);
2445 if (sctx
->b
.chip_class
== SI
) {
2446 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2447 color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh
);
2452 if (sctx
->b
.chip_class
>= VI
) {
2453 unsigned max_uncompressed_block_size
= 2;
2455 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
2456 if (rtex
->surface
.bpe
== 1)
2457 max_uncompressed_block_size
= 0;
2458 else if (rtex
->surface
.bpe
== 2)
2459 max_uncompressed_block_size
= 1;
2462 surf
->cb_dcc_control
= S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size
) |
2463 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2466 /* This must be set for fast clear to work without FMASK. */
2467 if (!rtex
->fmask
.size
&& sctx
->b
.chip_class
== SI
) {
2468 unsigned bankh
= util_logbase2(rtex
->surface
.u
.legacy
.bankh
);
2469 color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(bankh
);
2472 unsigned color_view
= S_028C6C_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
2473 S_028C6C_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
2475 if (sctx
->b
.chip_class
>= GFX9
) {
2476 unsigned mip0_depth
= util_max_layer(&rtex
->resource
.b
.b
, 0);
2478 color_view
|= S_028C6C_MIP_LEVEL(surf
->base
.u
.tex
.level
);
2479 color_attrib
|= S_028C74_MIP0_DEPTH(mip0_depth
) |
2480 S_028C74_RESOURCE_TYPE(rtex
->surface
.u
.gfx9
.resource_type
);
2481 surf
->cb_color_attrib2
= S_028C68_MIP0_WIDTH(surf
->width0
- 1) |
2482 S_028C68_MIP0_HEIGHT(surf
->height0
- 1) |
2483 S_028C68_MAX_MIP(rtex
->resource
.b
.b
.last_level
);
2486 surf
->cb_color_view
= color_view
;
2487 surf
->cb_color_info
= color_info
;
2488 surf
->cb_color_attrib
= color_attrib
;
2490 /* Determine pixel shader export format */
2491 si_choose_spi_color_formats(surf
, format
, swap
, ntype
, rtex
->is_depth
);
2493 surf
->color_initialized
= true;
2496 static void si_init_depth_surface(struct si_context
*sctx
,
2497 struct r600_surface
*surf
)
2499 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->base
.texture
;
2500 unsigned level
= surf
->base
.u
.tex
.level
;
2501 unsigned format
, stencil_format
;
2502 uint32_t z_info
, s_info
;
2504 format
= si_translate_dbformat(rtex
->db_render_format
);
2505 stencil_format
= rtex
->surface
.has_stencil
?
2506 V_028044_STENCIL_8
: V_028044_STENCIL_INVALID
;
2508 assert(format
!= V_028040_Z_INVALID
);
2509 if (format
== V_028040_Z_INVALID
)
2510 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex
->resource
.b
.b
.format
);
2512 surf
->db_depth_view
= S_028008_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
2513 S_028008_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
2514 surf
->db_htile_data_base
= 0;
2515 surf
->db_htile_surface
= 0;
2517 if (sctx
->b
.chip_class
>= GFX9
) {
2518 assert(rtex
->surface
.u
.gfx9
.surf_offset
== 0);
2519 surf
->db_depth_base
= rtex
->resource
.gpu_address
>> 8;
2520 surf
->db_stencil_base
= (rtex
->resource
.gpu_address
+
2521 rtex
->surface
.u
.gfx9
.stencil_offset
) >> 8;
2522 z_info
= S_028038_FORMAT(format
) |
2523 S_028038_NUM_SAMPLES(util_logbase2(rtex
->resource
.b
.b
.nr_samples
)) |
2524 S_028038_SW_MODE(rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
2525 S_028038_MAXMIP(rtex
->resource
.b
.b
.last_level
);
2526 s_info
= S_02803C_FORMAT(stencil_format
) |
2527 S_02803C_SW_MODE(rtex
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
2528 surf
->db_z_info2
= S_028068_EPITCH(rtex
->surface
.u
.gfx9
.surf
.epitch
);
2529 surf
->db_stencil_info2
= S_02806C_EPITCH(rtex
->surface
.u
.gfx9
.stencil
.epitch
);
2530 surf
->db_depth_view
|= S_028008_MIPID(level
);
2531 surf
->db_depth_size
= S_02801C_X_MAX(rtex
->resource
.b
.b
.width0
- 1) |
2532 S_02801C_Y_MAX(rtex
->resource
.b
.b
.height0
- 1);
2534 if (si_htile_enabled(rtex
, level
)) {
2535 z_info
|= S_028038_TILE_SURFACE_ENABLE(1) |
2536 S_028038_ALLOW_EXPCLEAR(1);
2538 if (rtex
->tc_compatible_htile
) {
2539 unsigned max_zplanes
= 4;
2541 if (rtex
->db_render_format
== PIPE_FORMAT_Z16_UNORM
&&
2542 rtex
->resource
.b
.b
.nr_samples
> 1)
2545 z_info
|= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes
+ 1) |
2546 S_028038_ITERATE_FLUSH(1);
2547 s_info
|= S_02803C_ITERATE_FLUSH(1);
2550 if (rtex
->surface
.has_stencil
) {
2551 /* Stencil buffer workaround ported from the SI-CI-VI code.
2552 * See that for explanation.
2554 s_info
|= S_02803C_ALLOW_EXPCLEAR(rtex
->resource
.b
.b
.nr_samples
<= 1);
2556 /* Use all HTILE for depth if there's no stencil. */
2557 s_info
|= S_02803C_TILE_STENCIL_DISABLE(1);
2560 surf
->db_htile_data_base
= (rtex
->resource
.gpu_address
+
2561 rtex
->htile_offset
) >> 8;
2562 surf
->db_htile_surface
= S_028ABC_FULL_CACHE(1) |
2563 S_028ABC_PIPE_ALIGNED(rtex
->surface
.u
.gfx9
.htile
.pipe_aligned
) |
2564 S_028ABC_RB_ALIGNED(rtex
->surface
.u
.gfx9
.htile
.rb_aligned
);
2568 struct legacy_surf_level
*levelinfo
= &rtex
->surface
.u
.legacy
.level
[level
];
2570 assert(levelinfo
->nblk_x
% 8 == 0 && levelinfo
->nblk_y
% 8 == 0);
2572 surf
->db_depth_base
= (rtex
->resource
.gpu_address
+
2573 rtex
->surface
.u
.legacy
.level
[level
].offset
) >> 8;
2574 surf
->db_stencil_base
= (rtex
->resource
.gpu_address
+
2575 rtex
->surface
.u
.legacy
.stencil_level
[level
].offset
) >> 8;
2577 z_info
= S_028040_FORMAT(format
) |
2578 S_028040_NUM_SAMPLES(util_logbase2(rtex
->resource
.b
.b
.nr_samples
));
2579 s_info
= S_028044_FORMAT(stencil_format
);
2580 surf
->db_depth_info
= S_02803C_ADDR5_SWIZZLE_MASK(!rtex
->tc_compatible_htile
);
2582 if (sctx
->b
.chip_class
>= CIK
) {
2583 struct radeon_info
*info
= &sctx
->screen
->info
;
2584 unsigned index
= rtex
->surface
.u
.legacy
.tiling_index
[level
];
2585 unsigned stencil_index
= rtex
->surface
.u
.legacy
.stencil_tiling_index
[level
];
2586 unsigned macro_index
= rtex
->surface
.u
.legacy
.macro_tile_index
;
2587 unsigned tile_mode
= info
->si_tile_mode_array
[index
];
2588 unsigned stencil_tile_mode
= info
->si_tile_mode_array
[stencil_index
];
2589 unsigned macro_mode
= info
->cik_macrotile_mode_array
[macro_index
];
2591 surf
->db_depth_info
|=
2592 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode
)) |
2593 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode
)) |
2594 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode
)) |
2595 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode
)) |
2596 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode
)) |
2597 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode
));
2598 z_info
|= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode
));
2599 s_info
|= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode
));
2601 unsigned tile_mode_index
= si_tile_mode_index(rtex
, level
, false);
2602 z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
2603 tile_mode_index
= si_tile_mode_index(rtex
, level
, true);
2604 s_info
|= S_028044_TILE_MODE_INDEX(tile_mode_index
);
2607 surf
->db_depth_size
= S_028058_PITCH_TILE_MAX((levelinfo
->nblk_x
/ 8) - 1) |
2608 S_028058_HEIGHT_TILE_MAX((levelinfo
->nblk_y
/ 8) - 1);
2609 surf
->db_depth_slice
= S_02805C_SLICE_TILE_MAX((levelinfo
->nblk_x
*
2610 levelinfo
->nblk_y
) / 64 - 1);
2612 if (si_htile_enabled(rtex
, level
)) {
2613 z_info
|= S_028040_TILE_SURFACE_ENABLE(1) |
2614 S_028040_ALLOW_EXPCLEAR(1);
2616 if (rtex
->surface
.has_stencil
) {
2617 /* Workaround: For a not yet understood reason, the
2618 * combination of MSAA, fast stencil clear and stencil
2619 * decompress messes with subsequent stencil buffer
2620 * uses. Problem was reproduced on Verde, Bonaire,
2621 * Tonga, and Carrizo.
2623 * Disabling EXPCLEAR works around the problem.
2625 * Check piglit's arb_texture_multisample-stencil-clear
2626 * test if you want to try changing this.
2628 if (rtex
->resource
.b
.b
.nr_samples
<= 1)
2629 s_info
|= S_028044_ALLOW_EXPCLEAR(1);
2630 } else if (!rtex
->tc_compatible_htile
) {
2631 /* Use all of the htile_buffer for depth if there's no stencil.
2632 * This must not be set when TC-compatible HTILE is enabled
2635 s_info
|= S_028044_TILE_STENCIL_DISABLE(1);
2638 surf
->db_htile_data_base
= (rtex
->resource
.gpu_address
+
2639 rtex
->htile_offset
) >> 8;
2640 surf
->db_htile_surface
= S_028ABC_FULL_CACHE(1);
2642 if (rtex
->tc_compatible_htile
) {
2643 surf
->db_htile_surface
|= S_028ABC_TC_COMPATIBLE(1);
2645 if (rtex
->resource
.b
.b
.nr_samples
<= 1)
2646 z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2647 else if (rtex
->resource
.b
.b
.nr_samples
<= 4)
2648 z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2650 z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2655 surf
->db_z_info
= z_info
;
2656 surf
->db_stencil_info
= s_info
;
2658 surf
->depth_initialized
= true;
2661 void si_update_fb_dirtiness_after_rendering(struct si_context
*sctx
)
2663 if (sctx
->decompression_enabled
)
2666 if (sctx
->framebuffer
.state
.zsbuf
) {
2667 struct pipe_surface
*surf
= sctx
->framebuffer
.state
.zsbuf
;
2668 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->texture
;
2670 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2672 if (rtex
->surface
.has_stencil
)
2673 rtex
->stencil_dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2676 unsigned compressed_cb_mask
= sctx
->framebuffer
.compressed_cb_mask
;
2677 while (compressed_cb_mask
) {
2678 unsigned i
= u_bit_scan(&compressed_cb_mask
);
2679 struct pipe_surface
*surf
= sctx
->framebuffer
.state
.cbufs
[i
];
2680 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->texture
;
2682 if (rtex
->fmask
.size
)
2683 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2684 if (rtex
->dcc_gather_statistics
)
2685 rtex
->separate_dcc_dirty
= true;
2689 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state
*state
)
2691 for (int i
= 0; i
< state
->nr_cbufs
; ++i
) {
2692 struct r600_surface
*surf
= NULL
;
2693 struct r600_texture
*rtex
;
2695 if (!state
->cbufs
[i
])
2697 surf
= (struct r600_surface
*)state
->cbufs
[i
];
2698 rtex
= (struct r600_texture
*)surf
->base
.texture
;
2700 p_atomic_dec(&rtex
->framebuffers_bound
);
2704 static void si_set_framebuffer_state(struct pipe_context
*ctx
,
2705 const struct pipe_framebuffer_state
*state
)
2707 struct si_context
*sctx
= (struct si_context
*)ctx
;
2708 struct pipe_constant_buffer constbuf
= {0};
2709 struct r600_surface
*surf
= NULL
;
2710 struct r600_texture
*rtex
;
2711 bool old_any_dst_linear
= sctx
->framebuffer
.any_dst_linear
;
2712 unsigned old_nr_samples
= sctx
->framebuffer
.nr_samples
;
2713 unsigned old_colorbuf_enabled_4bit
= sctx
->framebuffer
.colorbuf_enabled_4bit
;
2714 bool old_has_zsbuf
= !!sctx
->framebuffer
.state
.zsbuf
;
2715 bool old_has_stencil
=
2717 ((struct r600_texture
*)sctx
->framebuffer
.state
.zsbuf
->texture
)->surface
.has_stencil
;
2718 bool unbound
= false;
2721 si_update_fb_dirtiness_after_rendering(sctx
);
2723 for (i
= 0; i
< sctx
->framebuffer
.state
.nr_cbufs
; i
++) {
2724 if (!sctx
->framebuffer
.state
.cbufs
[i
])
2727 rtex
= (struct r600_texture
*)sctx
->framebuffer
.state
.cbufs
[i
]->texture
;
2728 if (rtex
->dcc_gather_statistics
)
2729 vi_separate_dcc_stop_query(ctx
, rtex
);
2732 /* Disable DCC if the formats are incompatible. */
2733 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
2734 if (!state
->cbufs
[i
])
2737 surf
= (struct r600_surface
*)state
->cbufs
[i
];
2738 rtex
= (struct r600_texture
*)surf
->base
.texture
;
2740 if (!surf
->dcc_incompatible
)
2743 /* Since the DCC decompression calls back into set_framebuffer-
2744 * _state, we need to unbind the framebuffer, so that
2745 * vi_separate_dcc_stop_query isn't called twice with the same
2749 util_copy_framebuffer_state(&sctx
->framebuffer
.state
, NULL
);
2753 if (vi_dcc_enabled(rtex
, surf
->base
.u
.tex
.level
))
2754 if (!si_texture_disable_dcc(&sctx
->b
, rtex
))
2755 sctx
->b
.decompress_dcc(ctx
, rtex
);
2757 surf
->dcc_incompatible
= false;
2760 /* Only flush TC when changing the framebuffer state, because
2761 * the only client not using TC that can change textures is
2764 * Wait for compute shaders because of possible transitions:
2765 * - FB write -> shader read
2766 * - shader write -> FB read
2768 * DB caches are flushed on demand (using si_decompress_textures).
2770 * When MSAA is enabled, CB and TC caches are flushed on demand
2771 * (after FMASK decompression). Shader write -> FB read transitions
2772 * cannot happen for MSAA textures, because MSAA shader images are
2775 * Only flush and wait for CB if there is actually a bound color buffer.
2777 if (sctx
->framebuffer
.nr_samples
<= 1 &&
2778 sctx
->framebuffer
.state
.nr_cbufs
)
2779 si_make_CB_shader_coherent(sctx
, sctx
->framebuffer
.nr_samples
,
2780 sctx
->framebuffer
.CB_has_shader_readable_metadata
);
2782 sctx
->b
.flags
|= SI_CONTEXT_CS_PARTIAL_FLUSH
;
2784 /* u_blitter doesn't invoke depth decompression when it does multiple
2785 * blits in a row, but the only case when it matters for DB is when
2786 * doing generate_mipmap. So here we flush DB manually between
2787 * individual generate_mipmap blits.
2788 * Note that lower mipmap levels aren't compressed.
2790 if (sctx
->generate_mipmap_for_depth
) {
2791 si_make_DB_shader_coherent(sctx
, 1, false,
2792 sctx
->framebuffer
.DB_has_shader_readable_metadata
);
2793 } else if (sctx
->b
.chip_class
== GFX9
) {
2794 /* It appears that DB metadata "leaks" in a sequence of:
2796 * - DCC decompress for shader image writes (with DB disabled)
2797 * - render with DEPTH_BEFORE_SHADER=1
2798 * Flushing DB metadata works around the problem.
2800 sctx
->b
.flags
|= SI_CONTEXT_FLUSH_AND_INV_DB_META
;
2803 /* Take the maximum of the old and new count. If the new count is lower,
2804 * dirtying is needed to disable the unbound colorbuffers.
2806 sctx
->framebuffer
.dirty_cbufs
|=
2807 (1 << MAX2(sctx
->framebuffer
.state
.nr_cbufs
, state
->nr_cbufs
)) - 1;
2808 sctx
->framebuffer
.dirty_zsbuf
|= sctx
->framebuffer
.state
.zsbuf
!= state
->zsbuf
;
2810 si_dec_framebuffer_counters(&sctx
->framebuffer
.state
);
2811 util_copy_framebuffer_state(&sctx
->framebuffer
.state
, state
);
2813 sctx
->framebuffer
.colorbuf_enabled_4bit
= 0;
2814 sctx
->framebuffer
.spi_shader_col_format
= 0;
2815 sctx
->framebuffer
.spi_shader_col_format_alpha
= 0;
2816 sctx
->framebuffer
.spi_shader_col_format_blend
= 0;
2817 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
= 0;
2818 sctx
->framebuffer
.color_is_int8
= 0;
2819 sctx
->framebuffer
.color_is_int10
= 0;
2821 sctx
->framebuffer
.compressed_cb_mask
= 0;
2822 sctx
->framebuffer
.nr_samples
= util_framebuffer_get_num_samples(state
);
2823 sctx
->framebuffer
.log_samples
= util_logbase2(sctx
->framebuffer
.nr_samples
);
2824 sctx
->framebuffer
.any_dst_linear
= false;
2825 sctx
->framebuffer
.CB_has_shader_readable_metadata
= false;
2826 sctx
->framebuffer
.DB_has_shader_readable_metadata
= false;
2828 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
2829 if (!state
->cbufs
[i
])
2832 surf
= (struct r600_surface
*)state
->cbufs
[i
];
2833 rtex
= (struct r600_texture
*)surf
->base
.texture
;
2835 if (!surf
->color_initialized
) {
2836 si_initialize_color_surface(sctx
, surf
);
2839 sctx
->framebuffer
.colorbuf_enabled_4bit
|= 0xf << (i
* 4);
2840 sctx
->framebuffer
.spi_shader_col_format
|=
2841 surf
->spi_shader_col_format
<< (i
* 4);
2842 sctx
->framebuffer
.spi_shader_col_format_alpha
|=
2843 surf
->spi_shader_col_format_alpha
<< (i
* 4);
2844 sctx
->framebuffer
.spi_shader_col_format_blend
|=
2845 surf
->spi_shader_col_format_blend
<< (i
* 4);
2846 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
|=
2847 surf
->spi_shader_col_format_blend_alpha
<< (i
* 4);
2849 if (surf
->color_is_int8
)
2850 sctx
->framebuffer
.color_is_int8
|= 1 << i
;
2851 if (surf
->color_is_int10
)
2852 sctx
->framebuffer
.color_is_int10
|= 1 << i
;
2854 if (rtex
->fmask
.size
) {
2855 sctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
2858 if (rtex
->surface
.is_linear
)
2859 sctx
->framebuffer
.any_dst_linear
= true;
2861 if (vi_dcc_enabled(rtex
, surf
->base
.u
.tex
.level
))
2862 sctx
->framebuffer
.CB_has_shader_readable_metadata
= true;
2864 si_context_add_resource_size(ctx
, surf
->base
.texture
);
2866 p_atomic_inc(&rtex
->framebuffers_bound
);
2868 if (rtex
->dcc_gather_statistics
) {
2869 /* Dirty tracking must be enabled for DCC usage analysis. */
2870 sctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
2871 vi_separate_dcc_start_query(ctx
, rtex
);
2875 struct r600_texture
*zstex
= NULL
;
2878 surf
= (struct r600_surface
*)state
->zsbuf
;
2879 zstex
= (struct r600_texture
*)surf
->base
.texture
;
2881 if (!surf
->depth_initialized
) {
2882 si_init_depth_surface(sctx
, surf
);
2885 if (vi_tc_compat_htile_enabled(zstex
, surf
->base
.u
.tex
.level
))
2886 sctx
->framebuffer
.DB_has_shader_readable_metadata
= true;
2888 si_context_add_resource_size(ctx
, surf
->base
.texture
);
2891 si_update_poly_offset_state(sctx
);
2892 si_mark_atom_dirty(sctx
, &sctx
->cb_render_state
);
2893 si_mark_atom_dirty(sctx
, &sctx
->framebuffer
.atom
);
2895 if (sctx
->screen
->dpbb_allowed
)
2896 si_mark_atom_dirty(sctx
, &sctx
->dpbb_state
);
2898 if (sctx
->framebuffer
.any_dst_linear
!= old_any_dst_linear
)
2899 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
2901 if (sctx
->screen
->has_out_of_order_rast
&&
2902 (sctx
->framebuffer
.colorbuf_enabled_4bit
!= old_colorbuf_enabled_4bit
||
2903 !!sctx
->framebuffer
.state
.zsbuf
!= old_has_zsbuf
||
2904 (zstex
&& zstex
->surface
.has_stencil
!= old_has_stencil
)))
2905 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
2907 if (sctx
->framebuffer
.nr_samples
!= old_nr_samples
) {
2908 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
2909 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
2911 /* Set sample locations as fragment shader constants. */
2912 switch (sctx
->framebuffer
.nr_samples
) {
2914 constbuf
.user_buffer
= sctx
->sample_locations_1x
;
2917 constbuf
.user_buffer
= sctx
->sample_locations_2x
;
2920 constbuf
.user_buffer
= sctx
->sample_locations_4x
;
2923 constbuf
.user_buffer
= sctx
->sample_locations_8x
;
2926 constbuf
.user_buffer
= sctx
->sample_locations_16x
;
2929 R600_ERR("Requested an invalid number of samples %i.\n",
2930 sctx
->framebuffer
.nr_samples
);
2933 constbuf
.buffer_size
= sctx
->framebuffer
.nr_samples
* 2 * 4;
2934 si_set_rw_buffer(sctx
, SI_PS_CONST_SAMPLE_POSITIONS
, &constbuf
);
2936 si_mark_atom_dirty(sctx
, &sctx
->msaa_sample_locs
.atom
);
2939 sctx
->do_update_shaders
= true;
2941 if (!sctx
->decompression_enabled
) {
2942 /* Prevent textures decompression when the framebuffer state
2943 * changes come from the decompression passes themselves.
2945 sctx
->need_check_render_feedback
= true;
2949 static void si_emit_framebuffer_state(struct si_context
*sctx
, struct r600_atom
*atom
)
2951 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
2952 struct pipe_framebuffer_state
*state
= &sctx
->framebuffer
.state
;
2953 unsigned i
, nr_cbufs
= state
->nr_cbufs
;
2954 struct r600_texture
*tex
= NULL
;
2955 struct r600_surface
*cb
= NULL
;
2956 unsigned cb_color_info
= 0;
2959 for (i
= 0; i
< nr_cbufs
; i
++) {
2960 uint64_t cb_color_base
, cb_color_fmask
, cb_dcc_base
;
2961 unsigned cb_color_attrib
;
2963 if (!(sctx
->framebuffer
.dirty_cbufs
& (1 << i
)))
2966 cb
= (struct r600_surface
*)state
->cbufs
[i
];
2968 radeon_set_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
2969 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
2973 tex
= (struct r600_texture
*)cb
->base
.texture
;
2974 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
2975 &tex
->resource
, RADEON_USAGE_READWRITE
,
2976 tex
->resource
.b
.b
.nr_samples
> 1 ?
2977 RADEON_PRIO_COLOR_BUFFER_MSAA
:
2978 RADEON_PRIO_COLOR_BUFFER
);
2980 if (tex
->cmask_buffer
&& tex
->cmask_buffer
!= &tex
->resource
) {
2981 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
2982 tex
->cmask_buffer
, RADEON_USAGE_READWRITE
,
2986 if (tex
->dcc_separate_buffer
)
2987 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
2988 tex
->dcc_separate_buffer
,
2989 RADEON_USAGE_READWRITE
,
2992 /* Compute mutable surface parameters. */
2993 cb_color_base
= tex
->resource
.gpu_address
>> 8;
2996 cb_color_info
= cb
->cb_color_info
| tex
->cb_color_info
;
2997 cb_color_attrib
= cb
->cb_color_attrib
;
2999 if (tex
->fmask
.size
) {
3000 cb_color_fmask
= (tex
->resource
.gpu_address
+ tex
->fmask
.offset
) >> 8;
3001 cb_color_fmask
|= tex
->fmask
.tile_swizzle
;
3005 if (vi_dcc_enabled(tex
, cb
->base
.u
.tex
.level
)) {
3006 bool is_msaa_resolve_dst
= state
->cbufs
[0] &&
3007 state
->cbufs
[0]->texture
->nr_samples
> 1 &&
3008 state
->cbufs
[1] == &cb
->base
&&
3009 state
->cbufs
[1]->texture
->nr_samples
<= 1;
3011 if (!is_msaa_resolve_dst
)
3012 cb_color_info
|= S_028C70_DCC_ENABLE(1);
3014 cb_dcc_base
= ((!tex
->dcc_separate_buffer
? tex
->resource
.gpu_address
: 0) +
3015 tex
->dcc_offset
) >> 8;
3016 cb_dcc_base
|= tex
->surface
.tile_swizzle
;
3019 if (sctx
->b
.chip_class
>= GFX9
) {
3020 struct gfx9_surf_meta_flags meta
;
3022 if (tex
->dcc_offset
)
3023 meta
= tex
->surface
.u
.gfx9
.dcc
;
3025 meta
= tex
->surface
.u
.gfx9
.cmask
;
3027 /* Set mutable surface parameters. */
3028 cb_color_base
+= tex
->surface
.u
.gfx9
.surf_offset
>> 8;
3029 cb_color_base
|= tex
->surface
.tile_swizzle
;
3030 if (!tex
->fmask
.size
)
3031 cb_color_fmask
= cb_color_base
;
3032 cb_color_attrib
|= S_028C74_COLOR_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
3033 S_028C74_FMASK_SW_MODE(tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
) |
3034 S_028C74_RB_ALIGNED(meta
.rb_aligned
) |
3035 S_028C74_PIPE_ALIGNED(meta
.pipe_aligned
);
3037 radeon_set_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C, 15);
3038 radeon_emit(cs
, cb_color_base
); /* CB_COLOR0_BASE */
3039 radeon_emit(cs
, cb_color_base
>> 32); /* CB_COLOR0_BASE_EXT */
3040 radeon_emit(cs
, cb
->cb_color_attrib2
); /* CB_COLOR0_ATTRIB2 */
3041 radeon_emit(cs
, cb
->cb_color_view
); /* CB_COLOR0_VIEW */
3042 radeon_emit(cs
, cb_color_info
); /* CB_COLOR0_INFO */
3043 radeon_emit(cs
, cb_color_attrib
); /* CB_COLOR0_ATTRIB */
3044 radeon_emit(cs
, cb
->cb_dcc_control
); /* CB_COLOR0_DCC_CONTROL */
3045 radeon_emit(cs
, tex
->cmask
.base_address_reg
); /* CB_COLOR0_CMASK */
3046 radeon_emit(cs
, tex
->cmask
.base_address_reg
>> 32); /* CB_COLOR0_CMASK_BASE_EXT */
3047 radeon_emit(cs
, cb_color_fmask
); /* CB_COLOR0_FMASK */
3048 radeon_emit(cs
, cb_color_fmask
>> 32); /* CB_COLOR0_FMASK_BASE_EXT */
3049 radeon_emit(cs
, tex
->color_clear_value
[0]); /* CB_COLOR0_CLEAR_WORD0 */
3050 radeon_emit(cs
, tex
->color_clear_value
[1]); /* CB_COLOR0_CLEAR_WORD1 */
3051 radeon_emit(cs
, cb_dcc_base
); /* CB_COLOR0_DCC_BASE */
3052 radeon_emit(cs
, cb_dcc_base
>> 32); /* CB_COLOR0_DCC_BASE_EXT */
3054 radeon_set_context_reg(cs
, R_0287A0_CB_MRT0_EPITCH
+ i
* 4,
3055 S_0287A0_EPITCH(tex
->surface
.u
.gfx9
.surf
.epitch
));
3057 /* Compute mutable surface parameters (SI-CI-VI). */
3058 const struct legacy_surf_level
*level_info
=
3059 &tex
->surface
.u
.legacy
.level
[cb
->base
.u
.tex
.level
];
3060 unsigned pitch_tile_max
, slice_tile_max
, tile_mode_index
;
3061 unsigned cb_color_pitch
, cb_color_slice
, cb_color_fmask_slice
;
3063 cb_color_base
+= level_info
->offset
>> 8;
3064 /* Only macrotiled modes can set tile swizzle. */
3065 if (level_info
->mode
== RADEON_SURF_MODE_2D
)
3066 cb_color_base
|= tex
->surface
.tile_swizzle
;
3068 if (!tex
->fmask
.size
)
3069 cb_color_fmask
= cb_color_base
;
3071 cb_dcc_base
+= level_info
->dcc_offset
>> 8;
3073 pitch_tile_max
= level_info
->nblk_x
/ 8 - 1;
3074 slice_tile_max
= level_info
->nblk_x
*
3075 level_info
->nblk_y
/ 64 - 1;
3076 tile_mode_index
= si_tile_mode_index(tex
, cb
->base
.u
.tex
.level
, false);
3078 cb_color_attrib
|= S_028C74_TILE_MODE_INDEX(tile_mode_index
);
3079 cb_color_pitch
= S_028C64_TILE_MAX(pitch_tile_max
);
3080 cb_color_slice
= S_028C68_TILE_MAX(slice_tile_max
);
3082 if (tex
->fmask
.size
) {
3083 if (sctx
->b
.chip_class
>= CIK
)
3084 cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(tex
->fmask
.pitch_in_pixels
/ 8 - 1);
3085 cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tex
->fmask
.tile_mode_index
);
3086 cb_color_fmask_slice
= S_028C88_TILE_MAX(tex
->fmask
.slice_tile_max
);
3088 /* This must be set for fast clear to work without FMASK. */
3089 if (sctx
->b
.chip_class
>= CIK
)
3090 cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(pitch_tile_max
);
3091 cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index
);
3092 cb_color_fmask_slice
= S_028C88_TILE_MAX(slice_tile_max
);
3095 radeon_set_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C,
3096 sctx
->b
.chip_class
>= VI
? 14 : 13);
3097 radeon_emit(cs
, cb_color_base
); /* CB_COLOR0_BASE */
3098 radeon_emit(cs
, cb_color_pitch
); /* CB_COLOR0_PITCH */
3099 radeon_emit(cs
, cb_color_slice
); /* CB_COLOR0_SLICE */
3100 radeon_emit(cs
, cb
->cb_color_view
); /* CB_COLOR0_VIEW */
3101 radeon_emit(cs
, cb_color_info
); /* CB_COLOR0_INFO */
3102 radeon_emit(cs
, cb_color_attrib
); /* CB_COLOR0_ATTRIB */
3103 radeon_emit(cs
, cb
->cb_dcc_control
); /* CB_COLOR0_DCC_CONTROL */
3104 radeon_emit(cs
, tex
->cmask
.base_address_reg
); /* CB_COLOR0_CMASK */
3105 radeon_emit(cs
, tex
->cmask
.slice_tile_max
); /* CB_COLOR0_CMASK_SLICE */
3106 radeon_emit(cs
, cb_color_fmask
); /* CB_COLOR0_FMASK */
3107 radeon_emit(cs
, cb_color_fmask_slice
); /* CB_COLOR0_FMASK_SLICE */
3108 radeon_emit(cs
, tex
->color_clear_value
[0]); /* CB_COLOR0_CLEAR_WORD0 */
3109 radeon_emit(cs
, tex
->color_clear_value
[1]); /* CB_COLOR0_CLEAR_WORD1 */
3111 if (sctx
->b
.chip_class
>= VI
) /* R_028C94_CB_COLOR0_DCC_BASE */
3112 radeon_emit(cs
, cb_dcc_base
);
3116 if (sctx
->framebuffer
.dirty_cbufs
& (1 << i
))
3117 radeon_set_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C, 0);
3120 if (state
->zsbuf
&& sctx
->framebuffer
.dirty_zsbuf
) {
3121 struct r600_surface
*zb
= (struct r600_surface
*)state
->zsbuf
;
3122 struct r600_texture
*rtex
= (struct r600_texture
*)zb
->base
.texture
;
3124 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
3125 &rtex
->resource
, RADEON_USAGE_READWRITE
,
3126 zb
->base
.texture
->nr_samples
> 1 ?
3127 RADEON_PRIO_DEPTH_BUFFER_MSAA
:
3128 RADEON_PRIO_DEPTH_BUFFER
);
3130 if (sctx
->b
.chip_class
>= GFX9
) {
3131 radeon_set_context_reg_seq(cs
, R_028014_DB_HTILE_DATA_BASE
, 3);
3132 radeon_emit(cs
, zb
->db_htile_data_base
); /* DB_HTILE_DATA_BASE */
3133 radeon_emit(cs
, zb
->db_htile_data_base
>> 32); /* DB_HTILE_DATA_BASE_HI */
3134 radeon_emit(cs
, zb
->db_depth_size
); /* DB_DEPTH_SIZE */
3136 radeon_set_context_reg_seq(cs
, R_028038_DB_Z_INFO
, 10);
3137 radeon_emit(cs
, zb
->db_z_info
| /* DB_Z_INFO */
3138 S_028038_ZRANGE_PRECISION(rtex
->depth_clear_value
!= 0));
3139 radeon_emit(cs
, zb
->db_stencil_info
); /* DB_STENCIL_INFO */
3140 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_READ_BASE */
3141 radeon_emit(cs
, zb
->db_depth_base
>> 32); /* DB_Z_READ_BASE_HI */
3142 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_READ_BASE */
3143 radeon_emit(cs
, zb
->db_stencil_base
>> 32); /* DB_STENCIL_READ_BASE_HI */
3144 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_WRITE_BASE */
3145 radeon_emit(cs
, zb
->db_depth_base
>> 32); /* DB_Z_WRITE_BASE_HI */
3146 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_WRITE_BASE */
3147 radeon_emit(cs
, zb
->db_stencil_base
>> 32); /* DB_STENCIL_WRITE_BASE_HI */
3149 radeon_set_context_reg_seq(cs
, R_028068_DB_Z_INFO2
, 2);
3150 radeon_emit(cs
, zb
->db_z_info2
); /* DB_Z_INFO2 */
3151 radeon_emit(cs
, zb
->db_stencil_info2
); /* DB_STENCIL_INFO2 */
3153 radeon_set_context_reg(cs
, R_028014_DB_HTILE_DATA_BASE
, zb
->db_htile_data_base
);
3155 radeon_set_context_reg_seq(cs
, R_02803C_DB_DEPTH_INFO
, 9);
3156 radeon_emit(cs
, zb
->db_depth_info
); /* DB_DEPTH_INFO */
3157 radeon_emit(cs
, zb
->db_z_info
| /* DB_Z_INFO */
3158 S_028040_ZRANGE_PRECISION(rtex
->depth_clear_value
!= 0));
3159 radeon_emit(cs
, zb
->db_stencil_info
); /* DB_STENCIL_INFO */
3160 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_READ_BASE */
3161 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_READ_BASE */
3162 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_WRITE_BASE */
3163 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_WRITE_BASE */
3164 radeon_emit(cs
, zb
->db_depth_size
); /* DB_DEPTH_SIZE */
3165 radeon_emit(cs
, zb
->db_depth_slice
); /* DB_DEPTH_SLICE */
3168 radeon_set_context_reg_seq(cs
, R_028028_DB_STENCIL_CLEAR
, 2);
3169 radeon_emit(cs
, rtex
->stencil_clear_value
); /* R_028028_DB_STENCIL_CLEAR */
3170 radeon_emit(cs
, fui(rtex
->depth_clear_value
)); /* R_02802C_DB_DEPTH_CLEAR */
3172 radeon_set_context_reg(cs
, R_028008_DB_DEPTH_VIEW
, zb
->db_depth_view
);
3173 radeon_set_context_reg(cs
, R_028ABC_DB_HTILE_SURFACE
, zb
->db_htile_surface
);
3174 } else if (sctx
->framebuffer
.dirty_zsbuf
) {
3175 if (sctx
->b
.chip_class
>= GFX9
)
3176 radeon_set_context_reg_seq(cs
, R_028038_DB_Z_INFO
, 2);
3178 radeon_set_context_reg_seq(cs
, R_028040_DB_Z_INFO
, 2);
3180 radeon_emit(cs
, S_028040_FORMAT(V_028040_Z_INVALID
)); /* DB_Z_INFO */
3181 radeon_emit(cs
, S_028044_FORMAT(V_028044_STENCIL_INVALID
)); /* DB_STENCIL_INFO */
3184 /* Framebuffer dimensions. */
3185 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
3186 radeon_set_context_reg(cs
, R_028208_PA_SC_WINDOW_SCISSOR_BR
,
3187 S_028208_BR_X(state
->width
) | S_028208_BR_Y(state
->height
));
3189 if (sctx
->screen
->dfsm_allowed
) {
3190 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3191 radeon_emit(cs
, EVENT_TYPE(V_028A90_BREAK_BATCH
) | EVENT_INDEX(0));
3194 sctx
->framebuffer
.dirty_cbufs
= 0;
3195 sctx
->framebuffer
.dirty_zsbuf
= false;
3198 static void si_emit_msaa_sample_locs(struct si_context
*sctx
,
3199 struct r600_atom
*atom
)
3201 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
3202 unsigned nr_samples
= sctx
->framebuffer
.nr_samples
;
3203 bool has_msaa_sample_loc_bug
= sctx
->screen
->has_msaa_sample_loc_bug
;
3205 /* Smoothing (only possible with nr_samples == 1) uses the same
3206 * sample locations as the MSAA it simulates.
3208 if (nr_samples
<= 1 && sctx
->smoothing_enabled
)
3209 nr_samples
= SI_NUM_SMOOTH_AA_SAMPLES
;
3211 /* On Polaris, the small primitive filter uses the sample locations
3212 * even when MSAA is off, so we need to make sure they're set to 0.
3214 if (has_msaa_sample_loc_bug
)
3215 nr_samples
= MAX2(nr_samples
, 1);
3217 if (nr_samples
!= sctx
->msaa_sample_locs
.nr_samples
) {
3218 sctx
->msaa_sample_locs
.nr_samples
= nr_samples
;
3219 si_emit_sample_locations(cs
, nr_samples
);
3222 if (sctx
->b
.family
>= CHIP_POLARIS10
) {
3223 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
3224 unsigned small_prim_filter_cntl
=
3225 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
3227 S_028830_LINE_FILTER_DISABLE(sctx
->b
.family
<= CHIP_POLARIS12
);
3229 /* The alternative of setting sample locations to 0 would
3230 * require a DB flush to avoid Z errors, see
3231 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
3233 if (has_msaa_sample_loc_bug
&&
3234 sctx
->framebuffer
.nr_samples
> 1 &&
3235 rs
&& !rs
->multisample_enable
)
3236 small_prim_filter_cntl
&= C_028830_SMALL_PRIM_FILTER_ENABLE
;
3238 radeon_set_context_reg(cs
, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL
,
3239 small_prim_filter_cntl
);
3243 static bool si_out_of_order_rasterization(struct si_context
*sctx
)
3245 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
3246 struct si_state_dsa
*dsa
= sctx
->queued
.named
.dsa
;
3248 if (!sctx
->screen
->has_out_of_order_rast
)
3251 unsigned colormask
= sctx
->framebuffer
.colorbuf_enabled_4bit
;
3254 colormask
&= blend
->cb_target_enabled_4bit
;
3259 /* Conservative: No logic op. */
3260 if (colormask
&& blend
->logicop_enable
)
3263 struct si_dsa_order_invariance dsa_order_invariant
= {
3264 .zs
= true, .pass_set
= true, .pass_last
= false
3267 if (sctx
->framebuffer
.state
.zsbuf
) {
3268 struct r600_texture
*zstex
=
3269 (struct r600_texture
*)sctx
->framebuffer
.state
.zsbuf
->texture
;
3270 bool has_stencil
= zstex
->surface
.has_stencil
;
3271 dsa_order_invariant
= dsa
->order_invariance
[has_stencil
];
3272 if (!dsa_order_invariant
.zs
)
3275 /* The set of PS invocations is always order invariant,
3276 * except when early Z/S tests are requested. */
3277 if (sctx
->ps_shader
.cso
&&
3278 sctx
->ps_shader
.cso
->info
.writes_memory
&&
3279 sctx
->ps_shader
.cso
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
] &&
3280 !dsa_order_invariant
.pass_set
)
3283 if (sctx
->b
.num_perfect_occlusion_queries
!= 0 &&
3284 !dsa_order_invariant
.pass_set
)
3291 unsigned blendmask
= colormask
& blend
->blend_enable_4bit
;
3294 /* Only commutative blending. */
3295 if (blendmask
& ~blend
->commutative_4bit
)
3298 if (!dsa_order_invariant
.pass_set
)
3302 if (colormask
& ~blendmask
) {
3303 if (!dsa_order_invariant
.pass_last
)
3310 static void si_emit_msaa_config(struct si_context
*sctx
, struct r600_atom
*atom
)
3312 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
3313 unsigned num_tile_pipes
= sctx
->screen
->info
.num_tile_pipes
;
3314 /* 33% faster rendering to linear color buffers */
3315 bool dst_is_linear
= sctx
->framebuffer
.any_dst_linear
;
3316 bool out_of_order_rast
= si_out_of_order_rasterization(sctx
);
3317 unsigned sc_mode_cntl_1
=
3318 S_028A4C_WALK_SIZE(dst_is_linear
) |
3319 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear
) |
3320 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes
== 2 ? 2 : 3) |
3321 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast
) |
3322 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
3324 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
3325 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
3326 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
3327 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
3328 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
3329 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
3331 int setup_samples
= sctx
->framebuffer
.nr_samples
> 1 ? sctx
->framebuffer
.nr_samples
:
3332 sctx
->smoothing_enabled
? SI_NUM_SMOOTH_AA_SAMPLES
: 0;
3334 /* Required by OpenGL line rasterization.
3336 * TODO: We should also enable perpendicular endcaps for AA lines,
3337 * but that requires implementing line stippling in the pixel
3338 * shader. SC can only do line stippling with axis-aligned
3341 unsigned sc_line_cntl
= S_028BDC_DX10_DIAMOND_TEST_ENA(1);
3343 if (setup_samples
> 1) {
3344 /* distance from the pixel center, indexed by log2(nr_samples) */
3345 static unsigned max_dist
[] = {
3352 unsigned log_samples
= util_logbase2(setup_samples
);
3353 unsigned log_ps_iter_samples
=
3354 util_logbase2(util_next_power_of_two(sctx
->ps_iter_samples
));
3356 radeon_set_context_reg_seq(cs
, R_028BDC_PA_SC_LINE_CNTL
, 2);
3357 radeon_emit(cs
, sc_line_cntl
|
3358 S_028BDC_EXPAND_LINE_WIDTH(1)); /* CM_R_028BDC_PA_SC_LINE_CNTL */
3359 radeon_emit(cs
, S_028BE0_MSAA_NUM_SAMPLES(log_samples
) |
3360 S_028BE0_MAX_SAMPLE_DIST(max_dist
[log_samples
]) |
3361 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples
)); /* CM_R_028BE0_PA_SC_AA_CONFIG */
3363 if (sctx
->framebuffer
.nr_samples
> 1) {
3364 radeon_set_context_reg(cs
, R_028804_DB_EQAA
,
3365 S_028804_MAX_ANCHOR_SAMPLES(log_samples
) |
3366 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples
) |
3367 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples
) |
3368 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples
) |
3369 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3370 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
3371 radeon_set_context_reg(cs
, R_028A4C_PA_SC_MODE_CNTL_1
,
3372 S_028A4C_PS_ITER_SAMPLE(sctx
->ps_iter_samples
> 1) |
3374 } else if (sctx
->smoothing_enabled
) {
3375 radeon_set_context_reg(cs
, R_028804_DB_EQAA
,
3376 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3377 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1) |
3378 S_028804_OVERRASTERIZATION_AMOUNT(log_samples
));
3379 radeon_set_context_reg(cs
, R_028A4C_PA_SC_MODE_CNTL_1
,
3383 radeon_set_context_reg_seq(cs
, R_028BDC_PA_SC_LINE_CNTL
, 2);
3384 radeon_emit(cs
, sc_line_cntl
); /* CM_R_028BDC_PA_SC_LINE_CNTL */
3385 radeon_emit(cs
, 0); /* CM_R_028BE0_PA_SC_AA_CONFIG */
3387 radeon_set_context_reg(cs
, R_028804_DB_EQAA
,
3388 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3389 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
3390 radeon_set_context_reg(cs
, R_028A4C_PA_SC_MODE_CNTL_1
,
3394 /* GFX9: Flush DFSM when the AA mode changes. */
3395 if (sctx
->screen
->dfsm_allowed
) {
3396 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3397 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
3401 static void si_set_min_samples(struct pipe_context
*ctx
, unsigned min_samples
)
3403 struct si_context
*sctx
= (struct si_context
*)ctx
;
3405 if (sctx
->ps_iter_samples
== min_samples
)
3408 sctx
->ps_iter_samples
= min_samples
;
3409 sctx
->do_update_shaders
= true;
3411 if (sctx
->framebuffer
.nr_samples
> 1)
3412 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
3413 if (sctx
->screen
->dpbb_allowed
)
3414 si_mark_atom_dirty(sctx
, &sctx
->dpbb_state
);
3422 * Build the sampler view descriptor for a buffer texture.
3423 * @param state 256-bit descriptor; only the high 128 bits are filled in
3426 si_make_buffer_descriptor(struct si_screen
*screen
, struct r600_resource
*buf
,
3427 enum pipe_format format
,
3428 unsigned offset
, unsigned size
,
3431 const struct util_format_description
*desc
;
3434 unsigned num_records
;
3435 unsigned num_format
, data_format
;
3437 desc
= util_format_description(format
);
3438 first_non_void
= util_format_get_first_non_void_channel(format
);
3439 stride
= desc
->block
.bits
/ 8;
3440 num_format
= si_translate_buffer_numformat(&screen
->b
, desc
, first_non_void
);
3441 data_format
= si_translate_buffer_dataformat(&screen
->b
, desc
, first_non_void
);
3443 num_records
= size
/ stride
;
3444 num_records
= MIN2(num_records
, (buf
->b
.b
.width0
- offset
) / stride
);
3446 /* The NUM_RECORDS field has a different meaning depending on the chip,
3447 * instruction type, STRIDE, and SWIZZLE_ENABLE.
3450 * - If STRIDE == 0, it's in byte units.
3451 * - If STRIDE != 0, it's in units of STRIDE, used with inst.IDXEN.
3454 * - For SMEM and STRIDE == 0, it's in byte units.
3455 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3456 * - For VMEM and STRIDE == 0 or SWIZZLE_ENABLE == 0, it's in byte units.
3457 * - For VMEM and STRIDE != 0 and SWIZZLE_ENABLE == 1, it's in units of STRIDE.
3458 * NOTE: There is incompatibility between VMEM and SMEM opcodes due to SWIZZLE_-
3459 * ENABLE. The workaround is to set STRIDE = 0 if SWIZZLE_ENABLE == 0 when
3460 * using SMEM. This can be done in the shader by clearing STRIDE with s_and.
3461 * That way the same descriptor can be used by both SMEM and VMEM.
3464 * - For SMEM and STRIDE == 0, it's in byte units.
3465 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3466 * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
3467 * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
3469 if (screen
->info
.chip_class
>= GFX9
)
3470 /* When vindex == 0, LLVM sets IDXEN = 0, thus changing units
3471 * from STRIDE to bytes. This works around it by setting
3472 * NUM_RECORDS to at least the size of one element, so that
3473 * the first element is readable when IDXEN == 0.
3475 * TODO: Fix this in LLVM, but do we need a new intrinsic where
3476 * IDXEN is enforced?
3478 num_records
= num_records
? MAX2(num_records
, stride
) : 0;
3479 else if (screen
->info
.chip_class
== VI
)
3480 num_records
*= stride
;
3483 state
[5] = S_008F04_STRIDE(stride
);
3484 state
[6] = num_records
;
3485 state
[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc
->swizzle
[0])) |
3486 S_008F0C_DST_SEL_Y(si_map_swizzle(desc
->swizzle
[1])) |
3487 S_008F0C_DST_SEL_Z(si_map_swizzle(desc
->swizzle
[2])) |
3488 S_008F0C_DST_SEL_W(si_map_swizzle(desc
->swizzle
[3])) |
3489 S_008F0C_NUM_FORMAT(num_format
) |
3490 S_008F0C_DATA_FORMAT(data_format
);
3493 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle
[4])
3495 unsigned bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
3497 if (swizzle
[3] == PIPE_SWIZZLE_X
) {
3498 /* For the pre-defined border color values (white, opaque
3499 * black, transparent black), the only thing that matters is
3500 * that the alpha channel winds up in the correct place
3501 * (because the RGB channels are all the same) so either of
3502 * these enumerations will work.
3504 if (swizzle
[2] == PIPE_SWIZZLE_Y
)
3505 bc_swizzle
= V_008F20_BC_SWIZZLE_WZYX
;
3507 bc_swizzle
= V_008F20_BC_SWIZZLE_WXYZ
;
3508 } else if (swizzle
[0] == PIPE_SWIZZLE_X
) {
3509 if (swizzle
[1] == PIPE_SWIZZLE_Y
)
3510 bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
3512 bc_swizzle
= V_008F20_BC_SWIZZLE_XWYZ
;
3513 } else if (swizzle
[1] == PIPE_SWIZZLE_X
) {
3514 bc_swizzle
= V_008F20_BC_SWIZZLE_YXWZ
;
3515 } else if (swizzle
[2] == PIPE_SWIZZLE_X
) {
3516 bc_swizzle
= V_008F20_BC_SWIZZLE_ZYXW
;
3523 * Build the sampler view descriptor for a texture.
3526 si_make_texture_descriptor(struct si_screen
*screen
,
3527 struct r600_texture
*tex
,
3529 enum pipe_texture_target target
,
3530 enum pipe_format pipe_format
,
3531 const unsigned char state_swizzle
[4],
3532 unsigned first_level
, unsigned last_level
,
3533 unsigned first_layer
, unsigned last_layer
,
3534 unsigned width
, unsigned height
, unsigned depth
,
3536 uint32_t *fmask_state
)
3538 struct pipe_resource
*res
= &tex
->resource
.b
.b
;
3539 const struct util_format_description
*desc
;
3540 unsigned char swizzle
[4];
3542 unsigned num_format
, data_format
, type
;
3545 desc
= util_format_description(pipe_format
);
3547 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
) {
3548 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
3549 const unsigned char swizzle_yyyy
[4] = {1, 1, 1, 1};
3550 const unsigned char swizzle_wwww
[4] = {3, 3, 3, 3};
3552 switch (pipe_format
) {
3553 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
3554 case PIPE_FORMAT_X32_S8X24_UINT
:
3555 case PIPE_FORMAT_X8Z24_UNORM
:
3556 util_format_compose_swizzles(swizzle_yyyy
, state_swizzle
, swizzle
);
3558 case PIPE_FORMAT_X24S8_UINT
:
3560 * X24S8 is implemented as an 8_8_8_8 data format, to
3561 * fix texture gathers. This affects at least
3562 * GL45-CTS.texture_cube_map_array.sampling on VI.
3564 util_format_compose_swizzles(swizzle_wwww
, state_swizzle
, swizzle
);
3567 util_format_compose_swizzles(swizzle_xxxx
, state_swizzle
, swizzle
);
3570 util_format_compose_swizzles(desc
->swizzle
, state_swizzle
, swizzle
);
3573 first_non_void
= util_format_get_first_non_void_channel(pipe_format
);
3575 switch (pipe_format
) {
3576 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
3577 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3580 if (first_non_void
< 0) {
3581 if (util_format_is_compressed(pipe_format
)) {
3582 switch (pipe_format
) {
3583 case PIPE_FORMAT_DXT1_SRGB
:
3584 case PIPE_FORMAT_DXT1_SRGBA
:
3585 case PIPE_FORMAT_DXT3_SRGBA
:
3586 case PIPE_FORMAT_DXT5_SRGBA
:
3587 case PIPE_FORMAT_BPTC_SRGBA
:
3588 case PIPE_FORMAT_ETC2_SRGB8
:
3589 case PIPE_FORMAT_ETC2_SRGB8A1
:
3590 case PIPE_FORMAT_ETC2_SRGBA8
:
3591 num_format
= V_008F14_IMG_NUM_FORMAT_SRGB
;
3593 case PIPE_FORMAT_RGTC1_SNORM
:
3594 case PIPE_FORMAT_LATC1_SNORM
:
3595 case PIPE_FORMAT_RGTC2_SNORM
:
3596 case PIPE_FORMAT_LATC2_SNORM
:
3597 case PIPE_FORMAT_ETC2_R11_SNORM
:
3598 case PIPE_FORMAT_ETC2_RG11_SNORM
:
3599 /* implies float, so use SNORM/UNORM to determine
3600 whether data is signed or not */
3601 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
3602 num_format
= V_008F14_IMG_NUM_FORMAT_SNORM
;
3605 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3608 } else if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
3609 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3611 num_format
= V_008F14_IMG_NUM_FORMAT_FLOAT
;
3613 } else if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
) {
3614 num_format
= V_008F14_IMG_NUM_FORMAT_SRGB
;
3616 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3618 switch (desc
->channel
[first_non_void
].type
) {
3619 case UTIL_FORMAT_TYPE_FLOAT
:
3620 num_format
= V_008F14_IMG_NUM_FORMAT_FLOAT
;
3622 case UTIL_FORMAT_TYPE_SIGNED
:
3623 if (desc
->channel
[first_non_void
].normalized
)
3624 num_format
= V_008F14_IMG_NUM_FORMAT_SNORM
;
3625 else if (desc
->channel
[first_non_void
].pure_integer
)
3626 num_format
= V_008F14_IMG_NUM_FORMAT_SINT
;
3628 num_format
= V_008F14_IMG_NUM_FORMAT_SSCALED
;
3630 case UTIL_FORMAT_TYPE_UNSIGNED
:
3631 if (desc
->channel
[first_non_void
].normalized
)
3632 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3633 else if (desc
->channel
[first_non_void
].pure_integer
)
3634 num_format
= V_008F14_IMG_NUM_FORMAT_UINT
;
3636 num_format
= V_008F14_IMG_NUM_FORMAT_USCALED
;
3641 data_format
= si_translate_texformat(&screen
->b
, pipe_format
, desc
, first_non_void
);
3642 if (data_format
== ~0) {
3646 /* S8 with Z32 HTILE needs a special format. */
3647 if (screen
->info
.chip_class
>= GFX9
&&
3648 pipe_format
== PIPE_FORMAT_S8_UINT
&&
3649 tex
->tc_compatible_htile
)
3650 data_format
= V_008F14_IMG_DATA_FORMAT_S8_32
;
3653 (res
->target
== PIPE_TEXTURE_CUBE
||
3654 res
->target
== PIPE_TEXTURE_CUBE_ARRAY
||
3655 (screen
->info
.chip_class
<= VI
&&
3656 res
->target
== PIPE_TEXTURE_3D
))) {
3657 /* For the purpose of shader images, treat cube maps and 3D
3658 * textures as 2D arrays. For 3D textures, the address
3659 * calculations for mipmaps are different, so we rely on the
3660 * caller to effectively disable mipmaps.
3662 type
= V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
3664 assert(res
->target
!= PIPE_TEXTURE_3D
|| (first_level
== 0 && last_level
== 0));
3666 type
= si_tex_dim(screen
, tex
, target
, res
->nr_samples
);
3669 if (type
== V_008F1C_SQ_RSRC_IMG_1D_ARRAY
) {
3671 depth
= res
->array_size
;
3672 } else if (type
== V_008F1C_SQ_RSRC_IMG_2D_ARRAY
||
3673 type
== V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
) {
3674 if (sampler
|| res
->target
!= PIPE_TEXTURE_3D
)
3675 depth
= res
->array_size
;
3676 } else if (type
== V_008F1C_SQ_RSRC_IMG_CUBE
)
3677 depth
= res
->array_size
/ 6;
3680 state
[1] = (S_008F14_DATA_FORMAT_GFX6(data_format
) |
3681 S_008F14_NUM_FORMAT_GFX6(num_format
));
3682 state
[2] = (S_008F18_WIDTH(width
- 1) |
3683 S_008F18_HEIGHT(height
- 1) |
3684 S_008F18_PERF_MOD(4));
3685 state
[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle
[0])) |
3686 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle
[1])) |
3687 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle
[2])) |
3688 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle
[3])) |
3689 S_008F1C_BASE_LEVEL(res
->nr_samples
> 1 ?
3691 S_008F1C_LAST_LEVEL(res
->nr_samples
> 1 ?
3692 util_logbase2(res
->nr_samples
) :
3694 S_008F1C_TYPE(type
));
3696 state
[5] = S_008F24_BASE_ARRAY(first_layer
);
3700 if (screen
->info
.chip_class
>= GFX9
) {
3701 unsigned bc_swizzle
= gfx9_border_color_swizzle(desc
->swizzle
);
3703 /* Depth is the the last accessible layer on Gfx9.
3704 * The hw doesn't need to know the total number of layers.
3706 if (type
== V_008F1C_SQ_RSRC_IMG_3D
)
3707 state
[4] |= S_008F20_DEPTH(depth
- 1);
3709 state
[4] |= S_008F20_DEPTH(last_layer
);
3711 state
[4] |= S_008F20_BC_SWIZZLE(bc_swizzle
);
3712 state
[5] |= S_008F24_MAX_MIP(res
->nr_samples
> 1 ?
3713 util_logbase2(res
->nr_samples
) :
3714 tex
->resource
.b
.b
.last_level
);
3716 state
[3] |= S_008F1C_POW2_PAD(res
->last_level
> 0);
3717 state
[4] |= S_008F20_DEPTH(depth
- 1);
3718 state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
3721 if (tex
->dcc_offset
) {
3722 unsigned swap
= si_translate_colorswap(pipe_format
, false);
3724 state
[6] = S_008F28_ALPHA_IS_ON_MSB(swap
<= 1);
3726 /* The last dword is unused by hw. The shader uses it to clear
3727 * bits in the first dword of sampler state.
3729 if (screen
->info
.chip_class
<= CIK
&& res
->nr_samples
<= 1) {
3730 if (first_level
== last_level
)
3731 state
[7] = C_008F30_MAX_ANISO_RATIO
;
3733 state
[7] = 0xffffffff;
3737 /* Initialize the sampler view for FMASK. */
3738 if (tex
->fmask
.size
) {
3739 uint32_t data_format
, num_format
;
3741 va
= tex
->resource
.gpu_address
+ tex
->fmask
.offset
;
3743 if (screen
->info
.chip_class
>= GFX9
) {
3744 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK
;
3745 switch (res
->nr_samples
) {
3747 num_format
= V_008F14_IMG_FMASK_8_2_2
;
3750 num_format
= V_008F14_IMG_FMASK_8_4_4
;
3753 num_format
= V_008F14_IMG_FMASK_32_8_8
;
3756 unreachable("invalid nr_samples");
3759 switch (res
->nr_samples
) {
3761 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2
;
3764 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4
;
3767 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8
;
3770 unreachable("invalid nr_samples");
3772 num_format
= V_008F14_IMG_NUM_FORMAT_UINT
;
3775 fmask_state
[0] = (va
>> 8) | tex
->fmask
.tile_swizzle
;
3776 fmask_state
[1] = S_008F14_BASE_ADDRESS_HI(va
>> 40) |
3777 S_008F14_DATA_FORMAT_GFX6(data_format
) |
3778 S_008F14_NUM_FORMAT_GFX6(num_format
);
3779 fmask_state
[2] = S_008F18_WIDTH(width
- 1) |
3780 S_008F18_HEIGHT(height
- 1);
3781 fmask_state
[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X
) |
3782 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X
) |
3783 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X
) |
3784 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X
) |
3785 S_008F1C_TYPE(si_tex_dim(screen
, tex
, target
, 0));
3787 fmask_state
[5] = S_008F24_BASE_ARRAY(first_layer
);
3791 if (screen
->info
.chip_class
>= GFX9
) {
3792 fmask_state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
);
3793 fmask_state
[4] |= S_008F20_DEPTH(last_layer
) |
3794 S_008F20_PITCH_GFX9(tex
->surface
.u
.gfx9
.fmask
.epitch
);
3795 fmask_state
[5] |= S_008F24_META_PIPE_ALIGNED(tex
->surface
.u
.gfx9
.cmask
.pipe_aligned
) |
3796 S_008F24_META_RB_ALIGNED(tex
->surface
.u
.gfx9
.cmask
.rb_aligned
);
3798 fmask_state
[3] |= S_008F1C_TILING_INDEX(tex
->fmask
.tile_mode_index
);
3799 fmask_state
[4] |= S_008F20_DEPTH(depth
- 1) |
3800 S_008F20_PITCH_GFX6(tex
->fmask
.pitch_in_pixels
- 1);
3801 fmask_state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
3807 * Create a sampler view.
3809 * @param ctx context
3810 * @param texture texture
3811 * @param state sampler view template
3812 * @param width0 width0 override (for compressed textures as int)
3813 * @param height0 height0 override (for compressed textures as int)
3814 * @param force_level set the base address to the level (for compressed textures)
3816 struct pipe_sampler_view
*
3817 si_create_sampler_view_custom(struct pipe_context
*ctx
,
3818 struct pipe_resource
*texture
,
3819 const struct pipe_sampler_view
*state
,
3820 unsigned width0
, unsigned height0
,
3821 unsigned force_level
)
3823 struct si_context
*sctx
= (struct si_context
*)ctx
;
3824 struct si_sampler_view
*view
= CALLOC_STRUCT(si_sampler_view
);
3825 struct r600_texture
*tmp
= (struct r600_texture
*)texture
;
3826 unsigned base_level
, first_level
, last_level
;
3827 unsigned char state_swizzle
[4];
3828 unsigned height
, depth
, width
;
3829 unsigned last_layer
= state
->u
.tex
.last_layer
;
3830 enum pipe_format pipe_format
;
3831 const struct legacy_surf_level
*surflevel
;
3836 /* initialize base object */
3837 view
->base
= *state
;
3838 view
->base
.texture
= NULL
;
3839 view
->base
.reference
.count
= 1;
3840 view
->base
.context
= ctx
;
3843 pipe_resource_reference(&view
->base
.texture
, texture
);
3845 if (state
->format
== PIPE_FORMAT_X24S8_UINT
||
3846 state
->format
== PIPE_FORMAT_S8X24_UINT
||
3847 state
->format
== PIPE_FORMAT_X32_S8X24_UINT
||
3848 state
->format
== PIPE_FORMAT_S8_UINT
)
3849 view
->is_stencil_sampler
= true;
3851 /* Buffer resource. */
3852 if (texture
->target
== PIPE_BUFFER
) {
3853 si_make_buffer_descriptor(sctx
->screen
,
3854 (struct r600_resource
*)texture
,
3856 state
->u
.buf
.offset
,
3862 state_swizzle
[0] = state
->swizzle_r
;
3863 state_swizzle
[1] = state
->swizzle_g
;
3864 state_swizzle
[2] = state
->swizzle_b
;
3865 state_swizzle
[3] = state
->swizzle_a
;
3868 first_level
= state
->u
.tex
.first_level
;
3869 last_level
= state
->u
.tex
.last_level
;
3872 depth
= texture
->depth0
;
3874 if (sctx
->b
.chip_class
<= VI
&& force_level
) {
3875 assert(force_level
== first_level
&&
3876 force_level
== last_level
);
3877 base_level
= force_level
;
3880 width
= u_minify(width
, force_level
);
3881 height
= u_minify(height
, force_level
);
3882 depth
= u_minify(depth
, force_level
);
3885 /* This is not needed if state trackers set last_layer correctly. */
3886 if (state
->target
== PIPE_TEXTURE_1D
||
3887 state
->target
== PIPE_TEXTURE_2D
||
3888 state
->target
== PIPE_TEXTURE_RECT
||
3889 state
->target
== PIPE_TEXTURE_CUBE
)
3890 last_layer
= state
->u
.tex
.first_layer
;
3892 /* Texturing with separate depth and stencil. */
3893 pipe_format
= state
->format
;
3895 /* Depth/stencil texturing sometimes needs separate texture. */
3896 if (tmp
->is_depth
&& !si_can_sample_zs(tmp
, view
->is_stencil_sampler
)) {
3897 if (!tmp
->flushed_depth_texture
&&
3898 !si_init_flushed_depth_texture(ctx
, texture
, NULL
)) {
3899 pipe_resource_reference(&view
->base
.texture
, NULL
);
3904 assert(tmp
->flushed_depth_texture
);
3906 /* Override format for the case where the flushed texture
3907 * contains only Z or only S.
3909 if (tmp
->flushed_depth_texture
->resource
.b
.b
.format
!= tmp
->resource
.b
.b
.format
)
3910 pipe_format
= tmp
->flushed_depth_texture
->resource
.b
.b
.format
;
3912 tmp
= tmp
->flushed_depth_texture
;
3915 surflevel
= tmp
->surface
.u
.legacy
.level
;
3917 if (tmp
->db_compatible
) {
3918 if (!view
->is_stencil_sampler
)
3919 pipe_format
= tmp
->db_render_format
;
3921 switch (pipe_format
) {
3922 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
3923 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
3925 case PIPE_FORMAT_X8Z24_UNORM
:
3926 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
3927 /* Z24 is always stored like this for DB
3930 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
3932 case PIPE_FORMAT_X24S8_UINT
:
3933 case PIPE_FORMAT_S8X24_UINT
:
3934 case PIPE_FORMAT_X32_S8X24_UINT
:
3935 pipe_format
= PIPE_FORMAT_S8_UINT
;
3936 surflevel
= tmp
->surface
.u
.legacy
.stencil_level
;
3942 view
->dcc_incompatible
=
3943 vi_dcc_formats_are_incompatible(texture
,
3944 state
->u
.tex
.first_level
,
3947 si_make_texture_descriptor(sctx
->screen
, tmp
, true,
3948 state
->target
, pipe_format
, state_swizzle
,
3949 first_level
, last_level
,
3950 state
->u
.tex
.first_layer
, last_layer
,
3951 width
, height
, depth
,
3952 view
->state
, view
->fmask_state
);
3954 unsigned num_format
= G_008F14_NUM_FORMAT_GFX6(view
->state
[1]);
3956 num_format
== V_008F14_IMG_NUM_FORMAT_USCALED
||
3957 num_format
== V_008F14_IMG_NUM_FORMAT_SSCALED
||
3958 num_format
== V_008F14_IMG_NUM_FORMAT_UINT
||
3959 num_format
== V_008F14_IMG_NUM_FORMAT_SINT
;
3960 view
->base_level_info
= &surflevel
[base_level
];
3961 view
->base_level
= base_level
;
3962 view
->block_width
= util_format_get_blockwidth(pipe_format
);
3966 static struct pipe_sampler_view
*
3967 si_create_sampler_view(struct pipe_context
*ctx
,
3968 struct pipe_resource
*texture
,
3969 const struct pipe_sampler_view
*state
)
3971 return si_create_sampler_view_custom(ctx
, texture
, state
,
3972 texture
? texture
->width0
: 0,
3973 texture
? texture
->height0
: 0, 0);
3976 static void si_sampler_view_destroy(struct pipe_context
*ctx
,
3977 struct pipe_sampler_view
*state
)
3979 struct si_sampler_view
*view
= (struct si_sampler_view
*)state
;
3981 pipe_resource_reference(&state
->texture
, NULL
);
3985 static bool wrap_mode_uses_border_color(unsigned wrap
, bool linear_filter
)
3987 return wrap
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
||
3988 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
||
3990 (wrap
== PIPE_TEX_WRAP_CLAMP
||
3991 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP
));
3994 static uint32_t si_translate_border_color(struct si_context
*sctx
,
3995 const struct pipe_sampler_state
*state
,
3996 const union pipe_color_union
*color
,
3999 bool linear_filter
= state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
||
4000 state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
;
4002 if (!wrap_mode_uses_border_color(state
->wrap_s
, linear_filter
) &&
4003 !wrap_mode_uses_border_color(state
->wrap_t
, linear_filter
) &&
4004 !wrap_mode_uses_border_color(state
->wrap_r
, linear_filter
))
4005 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
);
4007 #define simple_border_types(elt) \
4009 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4010 color->elt[2] == 0 && color->elt[3] == 0) \
4011 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK); \
4012 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4013 color->elt[2] == 0 && color->elt[3] == 1) \
4014 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK); \
4015 if (color->elt[0] == 1 && color->elt[1] == 1 && \
4016 color->elt[2] == 1 && color->elt[3] == 1) \
4017 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE); \
4021 simple_border_types(ui
);
4023 simple_border_types(f
);
4025 #undef simple_border_types
4029 /* Check if the border has been uploaded already. */
4030 for (i
= 0; i
< sctx
->border_color_count
; i
++)
4031 if (memcmp(&sctx
->border_color_table
[i
], color
,
4032 sizeof(*color
)) == 0)
4035 if (i
>= SI_MAX_BORDER_COLORS
) {
4036 /* Getting 4096 unique border colors is very unlikely. */
4037 fprintf(stderr
, "radeonsi: The border color table is full. "
4038 "Any new border colors will be just black. "
4039 "Please file a bug.\n");
4040 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
);
4043 if (i
== sctx
->border_color_count
) {
4044 /* Upload a new border color. */
4045 memcpy(&sctx
->border_color_table
[i
], color
,
4047 util_memcpy_cpu_to_le32(&sctx
->border_color_map
[i
],
4048 color
, sizeof(*color
));
4049 sctx
->border_color_count
++;
4052 return S_008F3C_BORDER_COLOR_PTR(i
) |
4053 S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER
);
4056 static inline int S_FIXED(float value
, unsigned frac_bits
)
4058 return value
* (1 << frac_bits
);
4061 static inline unsigned si_tex_filter(unsigned filter
, unsigned max_aniso
)
4063 if (filter
== PIPE_TEX_FILTER_LINEAR
)
4064 return max_aniso
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
4065 : V_008F38_SQ_TEX_XY_FILTER_BILINEAR
;
4067 return max_aniso
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
4068 : V_008F38_SQ_TEX_XY_FILTER_POINT
;
4071 static inline unsigned si_tex_aniso_filter(unsigned filter
)
4084 static void *si_create_sampler_state(struct pipe_context
*ctx
,
4085 const struct pipe_sampler_state
*state
)
4087 struct si_context
*sctx
= (struct si_context
*)ctx
;
4088 struct si_screen
*sscreen
= sctx
->screen
;
4089 struct si_sampler_state
*rstate
= CALLOC_STRUCT(si_sampler_state
);
4090 unsigned max_aniso
= sscreen
->force_aniso
>= 0 ? sscreen
->force_aniso
4091 : state
->max_anisotropy
;
4092 unsigned max_aniso_ratio
= si_tex_aniso_filter(max_aniso
);
4093 union pipe_color_union clamped_border_color
;
4100 rstate
->magic
= SI_SAMPLER_STATE_MAGIC
;
4102 rstate
->val
[0] = (S_008F30_CLAMP_X(si_tex_wrap(state
->wrap_s
)) |
4103 S_008F30_CLAMP_Y(si_tex_wrap(state
->wrap_t
)) |
4104 S_008F30_CLAMP_Z(si_tex_wrap(state
->wrap_r
)) |
4105 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio
) |
4106 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state
->compare_func
)) |
4107 S_008F30_FORCE_UNNORMALIZED(!state
->normalized_coords
) |
4108 S_008F30_ANISO_THRESHOLD(max_aniso_ratio
>> 1) |
4109 S_008F30_ANISO_BIAS(max_aniso_ratio
) |
4110 S_008F30_DISABLE_CUBE_WRAP(!state
->seamless_cube_map
) |
4111 S_008F30_COMPAT_MODE(sctx
->b
.chip_class
>= VI
));
4112 rstate
->val
[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 8)) |
4113 S_008F34_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 8)) |
4114 S_008F34_PERF_MIP(max_aniso_ratio
? max_aniso_ratio
+ 6 : 0));
4115 rstate
->val
[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 8)) |
4116 S_008F38_XY_MAG_FILTER(si_tex_filter(state
->mag_img_filter
, max_aniso
)) |
4117 S_008F38_XY_MIN_FILTER(si_tex_filter(state
->min_img_filter
, max_aniso
)) |
4118 S_008F38_MIP_FILTER(si_tex_mipfilter(state
->min_mip_filter
)) |
4119 S_008F38_MIP_POINT_PRECLAMP(0) |
4120 S_008F38_DISABLE_LSB_CEIL(sctx
->b
.chip_class
<= VI
) |
4121 S_008F38_FILTER_PREC_FIX(1) |
4122 S_008F38_ANISO_OVERRIDE(sctx
->b
.chip_class
>= VI
));
4123 rstate
->val
[3] = si_translate_border_color(sctx
, state
, &state
->border_color
, false);
4125 /* Create sampler resource for integer textures. */
4126 memcpy(rstate
->integer_val
, rstate
->val
, sizeof(rstate
->val
));
4127 rstate
->integer_val
[3] = si_translate_border_color(sctx
, state
, &state
->border_color
, true);
4129 /* Create sampler resource for upgraded depth textures. */
4130 memcpy(rstate
->upgraded_depth_val
, rstate
->val
, sizeof(rstate
->val
));
4132 for (unsigned i
= 0; i
< 4; ++i
) {
4133 /* Use channel 0 on purpose, so that we can use OPAQUE_WHITE
4134 * when the border color is 1.0. */
4135 clamped_border_color
.f
[i
] = CLAMP(state
->border_color
.f
[0], 0, 1);
4138 if (memcmp(&state
->border_color
, &clamped_border_color
, sizeof(clamped_border_color
)) == 0)
4139 rstate
->upgraded_depth_val
[3] |= S_008F3C_UPGRADED_DEPTH(1);
4141 rstate
->upgraded_depth_val
[3] =
4142 si_translate_border_color(sctx
, state
, &clamped_border_color
, false) |
4143 S_008F3C_UPGRADED_DEPTH(1);
4148 static void si_set_sample_mask(struct pipe_context
*ctx
, unsigned sample_mask
)
4150 struct si_context
*sctx
= (struct si_context
*)ctx
;
4152 if (sctx
->sample_mask
.sample_mask
== (uint16_t)sample_mask
)
4155 sctx
->sample_mask
.sample_mask
= sample_mask
;
4156 si_mark_atom_dirty(sctx
, &sctx
->sample_mask
.atom
);
4159 static void si_emit_sample_mask(struct si_context
*sctx
, struct r600_atom
*atom
)
4161 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
4162 unsigned mask
= sctx
->sample_mask
.sample_mask
;
4164 /* Needed for line and polygon smoothing as well as for the Polaris
4165 * small primitive filter. We expect the state tracker to take care of
4168 assert(mask
== 0xffff || sctx
->framebuffer
.nr_samples
> 1 ||
4169 (mask
& 1 && sctx
->blitter
->running
));
4171 radeon_set_context_reg_seq(cs
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
4172 radeon_emit(cs
, mask
| (mask
<< 16));
4173 radeon_emit(cs
, mask
| (mask
<< 16));
4176 static void si_delete_sampler_state(struct pipe_context
*ctx
, void *state
)
4179 struct si_sampler_state
*s
= state
;
4181 assert(s
->magic
== SI_SAMPLER_STATE_MAGIC
);
4188 * Vertex elements & buffers
4191 static void *si_create_vertex_elements(struct pipe_context
*ctx
,
4193 const struct pipe_vertex_element
*elements
)
4195 struct si_screen
*sscreen
= (struct si_screen
*)ctx
->screen
;
4196 struct si_vertex_elements
*v
= CALLOC_STRUCT(si_vertex_elements
);
4197 bool used
[SI_NUM_VERTEX_BUFFERS
] = {};
4200 assert(count
<= SI_MAX_ATTRIBS
);
4205 v
->desc_list_byte_size
= align(count
* 16, SI_CPDMA_ALIGNMENT
);
4207 for (i
= 0; i
< count
; ++i
) {
4208 const struct util_format_description
*desc
;
4209 const struct util_format_channel_description
*channel
;
4210 unsigned data_format
, num_format
;
4212 unsigned vbo_index
= elements
[i
].vertex_buffer_index
;
4213 unsigned char swizzle
[4];
4215 if (vbo_index
>= SI_NUM_VERTEX_BUFFERS
) {
4220 if (elements
[i
].instance_divisor
) {
4221 v
->uses_instance_divisors
= true;
4222 v
->instance_divisors
[i
] = elements
[i
].instance_divisor
;
4224 if (v
->instance_divisors
[i
] == 1)
4225 v
->instance_divisor_is_one
|= 1u << i
;
4227 v
->instance_divisor_is_fetched
|= 1u << i
;
4230 if (!used
[vbo_index
]) {
4231 v
->first_vb_use_mask
|= 1 << i
;
4232 used
[vbo_index
] = true;
4235 desc
= util_format_description(elements
[i
].src_format
);
4236 first_non_void
= util_format_get_first_non_void_channel(elements
[i
].src_format
);
4237 data_format
= si_translate_buffer_dataformat(ctx
->screen
, desc
, first_non_void
);
4238 num_format
= si_translate_buffer_numformat(ctx
->screen
, desc
, first_non_void
);
4239 channel
= first_non_void
>= 0 ? &desc
->channel
[first_non_void
] : NULL
;
4240 memcpy(swizzle
, desc
->swizzle
, sizeof(swizzle
));
4242 v
->format_size
[i
] = desc
->block
.bits
/ 8;
4243 v
->src_offset
[i
] = elements
[i
].src_offset
;
4244 v
->vertex_buffer_index
[i
] = vbo_index
;
4246 /* The hardware always treats the 2-bit alpha channel as
4247 * unsigned, so a shader workaround is needed. The affected
4248 * chips are VI and older except Stoney (GFX8.1).
4250 if (data_format
== V_008F0C_BUF_DATA_FORMAT_2_10_10_10
&&
4251 sscreen
->info
.chip_class
<= VI
&&
4252 sscreen
->info
.family
!= CHIP_STONEY
) {
4253 if (num_format
== V_008F0C_BUF_NUM_FORMAT_SNORM
) {
4254 v
->fix_fetch
[i
] = SI_FIX_FETCH_A2_SNORM
;
4255 } else if (num_format
== V_008F0C_BUF_NUM_FORMAT_SSCALED
) {
4256 v
->fix_fetch
[i
] = SI_FIX_FETCH_A2_SSCALED
;
4257 } else if (num_format
== V_008F0C_BUF_NUM_FORMAT_SINT
) {
4258 /* This isn't actually used in OpenGL. */
4259 v
->fix_fetch
[i
] = SI_FIX_FETCH_A2_SINT
;
4261 } else if (channel
&& channel
->type
== UTIL_FORMAT_TYPE_FIXED
) {
4262 if (desc
->swizzle
[3] == PIPE_SWIZZLE_1
)
4263 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBX_32_FIXED
;
4265 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_32_FIXED
;
4266 } else if (channel
&& channel
->size
== 32 && !channel
->pure_integer
) {
4267 if (channel
->type
== UTIL_FORMAT_TYPE_SIGNED
) {
4268 if (channel
->normalized
) {
4269 if (desc
->swizzle
[3] == PIPE_SWIZZLE_1
)
4270 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBX_32_SNORM
;
4272 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_32_SNORM
;
4274 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_32_SSCALED
;
4276 } else if (channel
->type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
4277 if (channel
->normalized
) {
4278 if (desc
->swizzle
[3] == PIPE_SWIZZLE_1
)
4279 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBX_32_UNORM
;
4281 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_32_UNORM
;
4283 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_32_USCALED
;
4286 } else if (channel
&& channel
->size
== 64 &&
4287 channel
->type
== UTIL_FORMAT_TYPE_FLOAT
) {
4288 switch (desc
->nr_channels
) {
4291 v
->fix_fetch
[i
] = SI_FIX_FETCH_RG_64_FLOAT
;
4292 swizzle
[0] = PIPE_SWIZZLE_X
;
4293 swizzle
[1] = PIPE_SWIZZLE_Y
;
4294 swizzle
[2] = desc
->nr_channels
== 2 ? PIPE_SWIZZLE_Z
: PIPE_SWIZZLE_0
;
4295 swizzle
[3] = desc
->nr_channels
== 2 ? PIPE_SWIZZLE_W
: PIPE_SWIZZLE_0
;
4298 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGB_64_FLOAT
;
4299 swizzle
[0] = PIPE_SWIZZLE_X
; /* 3 loads */
4300 swizzle
[1] = PIPE_SWIZZLE_Y
;
4301 swizzle
[2] = PIPE_SWIZZLE_0
;
4302 swizzle
[3] = PIPE_SWIZZLE_0
;
4305 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_64_FLOAT
;
4306 swizzle
[0] = PIPE_SWIZZLE_X
; /* 2 loads */
4307 swizzle
[1] = PIPE_SWIZZLE_Y
;
4308 swizzle
[2] = PIPE_SWIZZLE_Z
;
4309 swizzle
[3] = PIPE_SWIZZLE_W
;
4314 } else if (channel
&& desc
->nr_channels
== 3) {
4315 assert(desc
->swizzle
[0] == PIPE_SWIZZLE_X
);
4317 if (channel
->size
== 8) {
4318 if (channel
->pure_integer
)
4319 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGB_8_INT
;
4321 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGB_8
;
4322 } else if (channel
->size
== 16) {
4323 if (channel
->pure_integer
)
4324 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGB_16_INT
;
4326 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGB_16
;
4330 v
->rsrc_word3
[i
] = S_008F0C_DST_SEL_X(si_map_swizzle(swizzle
[0])) |
4331 S_008F0C_DST_SEL_Y(si_map_swizzle(swizzle
[1])) |
4332 S_008F0C_DST_SEL_Z(si_map_swizzle(swizzle
[2])) |
4333 S_008F0C_DST_SEL_W(si_map_swizzle(swizzle
[3])) |
4334 S_008F0C_NUM_FORMAT(num_format
) |
4335 S_008F0C_DATA_FORMAT(data_format
);
4340 static void si_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
4342 struct si_context
*sctx
= (struct si_context
*)ctx
;
4343 struct si_vertex_elements
*old
= sctx
->vertex_elements
;
4344 struct si_vertex_elements
*v
= (struct si_vertex_elements
*)state
;
4346 sctx
->vertex_elements
= v
;
4347 sctx
->vertex_buffers_dirty
= true;
4351 old
->count
!= v
->count
||
4352 old
->uses_instance_divisors
!= v
->uses_instance_divisors
||
4353 v
->uses_instance_divisors
|| /* we don't check which divisors changed */
4354 memcmp(old
->fix_fetch
, v
->fix_fetch
, sizeof(v
->fix_fetch
[0]) * v
->count
)))
4355 sctx
->do_update_shaders
= true;
4357 if (v
&& v
->instance_divisor_is_fetched
) {
4358 struct pipe_constant_buffer cb
;
4361 cb
.user_buffer
= v
->instance_divisors
;
4362 cb
.buffer_offset
= 0;
4363 cb
.buffer_size
= sizeof(uint32_t) * v
->count
;
4364 si_set_rw_buffer(sctx
, SI_VS_CONST_INSTANCE_DIVISORS
, &cb
);
4368 static void si_delete_vertex_element(struct pipe_context
*ctx
, void *state
)
4370 struct si_context
*sctx
= (struct si_context
*)ctx
;
4372 if (sctx
->vertex_elements
== state
)
4373 sctx
->vertex_elements
= NULL
;
4377 static void si_set_vertex_buffers(struct pipe_context
*ctx
,
4378 unsigned start_slot
, unsigned count
,
4379 const struct pipe_vertex_buffer
*buffers
)
4381 struct si_context
*sctx
= (struct si_context
*)ctx
;
4382 struct pipe_vertex_buffer
*dst
= sctx
->vertex_buffer
+ start_slot
;
4385 assert(start_slot
+ count
<= ARRAY_SIZE(sctx
->vertex_buffer
));
4388 for (i
= 0; i
< count
; i
++) {
4389 const struct pipe_vertex_buffer
*src
= buffers
+ i
;
4390 struct pipe_vertex_buffer
*dsti
= dst
+ i
;
4391 struct pipe_resource
*buf
= src
->buffer
.resource
;
4393 pipe_resource_reference(&dsti
->buffer
.resource
, buf
);
4394 dsti
->buffer_offset
= src
->buffer_offset
;
4395 dsti
->stride
= src
->stride
;
4396 si_context_add_resource_size(ctx
, buf
);
4398 r600_resource(buf
)->bind_history
|= PIPE_BIND_VERTEX_BUFFER
;
4401 for (i
= 0; i
< count
; i
++) {
4402 pipe_resource_reference(&dst
[i
].buffer
.resource
, NULL
);
4405 sctx
->vertex_buffers_dirty
= true;
4412 static void si_set_tess_state(struct pipe_context
*ctx
,
4413 const float default_outer_level
[4],
4414 const float default_inner_level
[2])
4416 struct si_context
*sctx
= (struct si_context
*)ctx
;
4417 struct pipe_constant_buffer cb
;
4420 memcpy(array
, default_outer_level
, sizeof(float) * 4);
4421 memcpy(array
+4, default_inner_level
, sizeof(float) * 2);
4424 cb
.user_buffer
= NULL
;
4425 cb
.buffer_size
= sizeof(array
);
4427 si_upload_const_buffer(sctx
, (struct r600_resource
**)&cb
.buffer
,
4428 (void*)array
, sizeof(array
),
4431 si_set_rw_buffer(sctx
, SI_HS_CONST_DEFAULT_TESS_LEVELS
, &cb
);
4432 pipe_resource_reference(&cb
.buffer
, NULL
);
4435 static void si_texture_barrier(struct pipe_context
*ctx
, unsigned flags
)
4437 struct si_context
*sctx
= (struct si_context
*)ctx
;
4439 si_update_fb_dirtiness_after_rendering(sctx
);
4441 /* Multisample surfaces are flushed in si_decompress_textures. */
4442 if (sctx
->framebuffer
.nr_samples
<= 1 &&
4443 sctx
->framebuffer
.state
.nr_cbufs
)
4444 si_make_CB_shader_coherent(sctx
, sctx
->framebuffer
.nr_samples
,
4445 sctx
->framebuffer
.CB_has_shader_readable_metadata
);
4448 /* This only ensures coherency for shader image/buffer stores. */
4449 static void si_memory_barrier(struct pipe_context
*ctx
, unsigned flags
)
4451 struct si_context
*sctx
= (struct si_context
*)ctx
;
4453 /* Subsequent commands must wait for all shader invocations to
4455 sctx
->b
.flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
|
4456 SI_CONTEXT_CS_PARTIAL_FLUSH
;
4458 if (flags
& PIPE_BARRIER_CONSTANT_BUFFER
)
4459 sctx
->b
.flags
|= SI_CONTEXT_INV_SMEM_L1
|
4460 SI_CONTEXT_INV_VMEM_L1
;
4462 if (flags
& (PIPE_BARRIER_VERTEX_BUFFER
|
4463 PIPE_BARRIER_SHADER_BUFFER
|
4464 PIPE_BARRIER_TEXTURE
|
4465 PIPE_BARRIER_IMAGE
|
4466 PIPE_BARRIER_STREAMOUT_BUFFER
|
4467 PIPE_BARRIER_GLOBAL_BUFFER
)) {
4468 /* As far as I can tell, L1 contents are written back to L2
4469 * automatically at end of shader, but the contents of other
4470 * L1 caches might still be stale. */
4471 sctx
->b
.flags
|= SI_CONTEXT_INV_VMEM_L1
;
4474 if (flags
& PIPE_BARRIER_INDEX_BUFFER
) {
4475 /* Indices are read through TC L2 since VI.
4478 if (sctx
->screen
->info
.chip_class
<= CIK
)
4479 sctx
->b
.flags
|= SI_CONTEXT_WRITEBACK_GLOBAL_L2
;
4482 /* MSAA color, any depth and any stencil are flushed in
4483 * si_decompress_textures when needed.
4485 if (flags
& PIPE_BARRIER_FRAMEBUFFER
&&
4486 sctx
->framebuffer
.nr_samples
<= 1 &&
4487 sctx
->framebuffer
.state
.nr_cbufs
) {
4488 sctx
->b
.flags
|= SI_CONTEXT_FLUSH_AND_INV_CB
;
4490 if (sctx
->b
.chip_class
<= VI
)
4491 sctx
->b
.flags
|= SI_CONTEXT_WRITEBACK_GLOBAL_L2
;
4494 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
4495 if (sctx
->screen
->info
.chip_class
<= VI
&&
4496 flags
& PIPE_BARRIER_INDIRECT_BUFFER
)
4497 sctx
->b
.flags
|= SI_CONTEXT_WRITEBACK_GLOBAL_L2
;
4500 static void *si_create_blend_custom(struct si_context
*sctx
, unsigned mode
)
4502 struct pipe_blend_state blend
;
4504 memset(&blend
, 0, sizeof(blend
));
4505 blend
.independent_blend_enable
= true;
4506 blend
.rt
[0].colormask
= 0xf;
4507 return si_create_blend_state_mode(&sctx
->b
.b
, &blend
, mode
);
4510 static void si_need_gfx_cs_space(struct pipe_context
*ctx
, unsigned num_dw
,
4511 bool include_draw_vbo
)
4513 si_need_cs_space((struct si_context
*)ctx
);
4516 static void si_init_config(struct si_context
*sctx
);
4518 void si_init_state_functions(struct si_context
*sctx
)
4520 si_init_external_atom(sctx
, &sctx
->b
.render_cond_atom
, &sctx
->atoms
.s
.render_cond
);
4521 si_init_external_atom(sctx
, &sctx
->streamout
.begin_atom
, &sctx
->atoms
.s
.streamout_begin
);
4522 si_init_external_atom(sctx
, &sctx
->streamout
.enable_atom
, &sctx
->atoms
.s
.streamout_enable
);
4523 si_init_external_atom(sctx
, &sctx
->scissors
.atom
, &sctx
->atoms
.s
.scissors
);
4524 si_init_external_atom(sctx
, &sctx
->viewports
.atom
, &sctx
->atoms
.s
.viewports
);
4526 si_init_atom(sctx
, &sctx
->framebuffer
.atom
, &sctx
->atoms
.s
.framebuffer
, si_emit_framebuffer_state
);
4527 si_init_atom(sctx
, &sctx
->msaa_sample_locs
.atom
, &sctx
->atoms
.s
.msaa_sample_locs
, si_emit_msaa_sample_locs
);
4528 si_init_atom(sctx
, &sctx
->db_render_state
, &sctx
->atoms
.s
.db_render_state
, si_emit_db_render_state
);
4529 si_init_atom(sctx
, &sctx
->dpbb_state
, &sctx
->atoms
.s
.dpbb_state
, si_emit_dpbb_state
);
4530 si_init_atom(sctx
, &sctx
->msaa_config
, &sctx
->atoms
.s
.msaa_config
, si_emit_msaa_config
);
4531 si_init_atom(sctx
, &sctx
->sample_mask
.atom
, &sctx
->atoms
.s
.sample_mask
, si_emit_sample_mask
);
4532 si_init_atom(sctx
, &sctx
->cb_render_state
, &sctx
->atoms
.s
.cb_render_state
, si_emit_cb_render_state
);
4533 si_init_atom(sctx
, &sctx
->blend_color
.atom
, &sctx
->atoms
.s
.blend_color
, si_emit_blend_color
);
4534 si_init_atom(sctx
, &sctx
->clip_regs
, &sctx
->atoms
.s
.clip_regs
, si_emit_clip_regs
);
4535 si_init_atom(sctx
, &sctx
->clip_state
.atom
, &sctx
->atoms
.s
.clip_state
, si_emit_clip_state
);
4536 si_init_atom(sctx
, &sctx
->stencil_ref
.atom
, &sctx
->atoms
.s
.stencil_ref
, si_emit_stencil_ref
);
4538 sctx
->b
.b
.create_blend_state
= si_create_blend_state
;
4539 sctx
->b
.b
.bind_blend_state
= si_bind_blend_state
;
4540 sctx
->b
.b
.delete_blend_state
= si_delete_blend_state
;
4541 sctx
->b
.b
.set_blend_color
= si_set_blend_color
;
4543 sctx
->b
.b
.create_rasterizer_state
= si_create_rs_state
;
4544 sctx
->b
.b
.bind_rasterizer_state
= si_bind_rs_state
;
4545 sctx
->b
.b
.delete_rasterizer_state
= si_delete_rs_state
;
4547 sctx
->b
.b
.create_depth_stencil_alpha_state
= si_create_dsa_state
;
4548 sctx
->b
.b
.bind_depth_stencil_alpha_state
= si_bind_dsa_state
;
4549 sctx
->b
.b
.delete_depth_stencil_alpha_state
= si_delete_dsa_state
;
4551 sctx
->custom_dsa_flush
= si_create_db_flush_dsa(sctx
);
4552 sctx
->custom_blend_resolve
= si_create_blend_custom(sctx
, V_028808_CB_RESOLVE
);
4553 sctx
->custom_blend_fmask_decompress
= si_create_blend_custom(sctx
, V_028808_CB_FMASK_DECOMPRESS
);
4554 sctx
->custom_blend_eliminate_fastclear
= si_create_blend_custom(sctx
, V_028808_CB_ELIMINATE_FAST_CLEAR
);
4555 sctx
->custom_blend_dcc_decompress
= si_create_blend_custom(sctx
, V_028808_CB_DCC_DECOMPRESS
);
4557 sctx
->b
.b
.set_clip_state
= si_set_clip_state
;
4558 sctx
->b
.b
.set_stencil_ref
= si_set_stencil_ref
;
4560 sctx
->b
.b
.set_framebuffer_state
= si_set_framebuffer_state
;
4562 sctx
->b
.b
.create_sampler_state
= si_create_sampler_state
;
4563 sctx
->b
.b
.delete_sampler_state
= si_delete_sampler_state
;
4565 sctx
->b
.b
.create_sampler_view
= si_create_sampler_view
;
4566 sctx
->b
.b
.sampler_view_destroy
= si_sampler_view_destroy
;
4568 sctx
->b
.b
.set_sample_mask
= si_set_sample_mask
;
4570 sctx
->b
.b
.create_vertex_elements_state
= si_create_vertex_elements
;
4571 sctx
->b
.b
.bind_vertex_elements_state
= si_bind_vertex_elements
;
4572 sctx
->b
.b
.delete_vertex_elements_state
= si_delete_vertex_element
;
4573 sctx
->b
.b
.set_vertex_buffers
= si_set_vertex_buffers
;
4575 sctx
->b
.b
.texture_barrier
= si_texture_barrier
;
4576 sctx
->b
.b
.memory_barrier
= si_memory_barrier
;
4577 sctx
->b
.b
.set_min_samples
= si_set_min_samples
;
4578 sctx
->b
.b
.set_tess_state
= si_set_tess_state
;
4580 sctx
->b
.b
.set_active_query_state
= si_set_active_query_state
;
4581 sctx
->b
.set_occlusion_query_state
= si_set_occlusion_query_state
;
4582 sctx
->b
.save_qbo_state
= si_save_qbo_state
;
4583 sctx
->b
.need_gfx_cs_space
= si_need_gfx_cs_space
;
4585 sctx
->b
.b
.draw_vbo
= si_draw_vbo
;
4587 si_init_config(sctx
);
4590 void si_init_screen_state_functions(struct si_screen
*sscreen
)
4592 sscreen
->b
.is_format_supported
= si_is_format_supported
;
4595 static void si_set_grbm_gfx_index(struct si_context
*sctx
,
4596 struct si_pm4_state
*pm4
, unsigned value
)
4598 unsigned reg
= sctx
->b
.chip_class
>= CIK
? R_030800_GRBM_GFX_INDEX
:
4599 R_00802C_GRBM_GFX_INDEX
;
4600 si_pm4_set_reg(pm4
, reg
, value
);
4603 static void si_set_grbm_gfx_index_se(struct si_context
*sctx
,
4604 struct si_pm4_state
*pm4
, unsigned se
)
4606 assert(se
== ~0 || se
< sctx
->screen
->info
.max_se
);
4607 si_set_grbm_gfx_index(sctx
, pm4
,
4608 (se
== ~0 ? S_030800_SE_BROADCAST_WRITES(1) :
4609 S_030800_SE_INDEX(se
)) |
4610 S_030800_SH_BROADCAST_WRITES(1) |
4611 S_030800_INSTANCE_BROADCAST_WRITES(1));
4615 si_write_harvested_raster_configs(struct si_context
*sctx
,
4616 struct si_pm4_state
*pm4
,
4617 unsigned raster_config
,
4618 unsigned raster_config_1
)
4620 unsigned sh_per_se
= MAX2(sctx
->screen
->info
.max_sh_per_se
, 1);
4621 unsigned num_se
= MAX2(sctx
->screen
->info
.max_se
, 1);
4622 unsigned rb_mask
= sctx
->screen
->info
.enabled_rb_mask
;
4623 unsigned num_rb
= MIN2(sctx
->screen
->info
.num_render_backends
, 16);
4624 unsigned rb_per_pkr
= MIN2(num_rb
/ num_se
/ sh_per_se
, 2);
4625 unsigned rb_per_se
= num_rb
/ num_se
;
4626 unsigned se_mask
[4];
4629 se_mask
[0] = ((1 << rb_per_se
) - 1);
4630 se_mask
[1] = (se_mask
[0] << rb_per_se
);
4631 se_mask
[2] = (se_mask
[1] << rb_per_se
);
4632 se_mask
[3] = (se_mask
[2] << rb_per_se
);
4634 se_mask
[0] &= rb_mask
;
4635 se_mask
[1] &= rb_mask
;
4636 se_mask
[2] &= rb_mask
;
4637 se_mask
[3] &= rb_mask
;
4639 assert(num_se
== 1 || num_se
== 2 || num_se
== 4);
4640 assert(sh_per_se
== 1 || sh_per_se
== 2);
4641 assert(rb_per_pkr
== 1 || rb_per_pkr
== 2);
4643 /* XXX: I can't figure out what the *_XSEL and *_YSEL
4644 * fields are for, so I'm leaving them as their default
4647 for (se
= 0; se
< num_se
; se
++) {
4648 unsigned raster_config_se
= raster_config
;
4649 unsigned pkr0_mask
= ((1 << rb_per_pkr
) - 1) << (se
* rb_per_se
);
4650 unsigned pkr1_mask
= pkr0_mask
<< rb_per_pkr
;
4651 int idx
= (se
/ 2) * 2;
4653 if ((num_se
> 1) && (!se_mask
[idx
] || !se_mask
[idx
+ 1])) {
4654 raster_config_se
&= C_028350_SE_MAP
;
4656 if (!se_mask
[idx
]) {
4658 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3
);
4661 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0
);
4665 pkr0_mask
&= rb_mask
;
4666 pkr1_mask
&= rb_mask
;
4667 if (rb_per_se
> 2 && (!pkr0_mask
|| !pkr1_mask
)) {
4668 raster_config_se
&= C_028350_PKR_MAP
;
4672 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3
);
4675 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0
);
4679 if (rb_per_se
>= 2) {
4680 unsigned rb0_mask
= 1 << (se
* rb_per_se
);
4681 unsigned rb1_mask
= rb0_mask
<< 1;
4683 rb0_mask
&= rb_mask
;
4684 rb1_mask
&= rb_mask
;
4685 if (!rb0_mask
|| !rb1_mask
) {
4686 raster_config_se
&= C_028350_RB_MAP_PKR0
;
4690 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3
);
4693 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0
);
4697 if (rb_per_se
> 2) {
4698 rb0_mask
= 1 << (se
* rb_per_se
+ rb_per_pkr
);
4699 rb1_mask
= rb0_mask
<< 1;
4700 rb0_mask
&= rb_mask
;
4701 rb1_mask
&= rb_mask
;
4702 if (!rb0_mask
|| !rb1_mask
) {
4703 raster_config_se
&= C_028350_RB_MAP_PKR1
;
4707 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3
);
4710 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0
);
4716 si_set_grbm_gfx_index_se(sctx
, pm4
, se
);
4717 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
, raster_config_se
);
4719 si_set_grbm_gfx_index(sctx
, pm4
, ~0);
4721 if (sctx
->b
.chip_class
>= CIK
) {
4722 if ((num_se
> 2) && ((!se_mask
[0] && !se_mask
[1]) ||
4723 (!se_mask
[2] && !se_mask
[3]))) {
4724 raster_config_1
&= C_028354_SE_PAIR_MAP
;
4726 if (!se_mask
[0] && !se_mask
[1]) {
4728 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3
);
4731 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0
);
4735 si_pm4_set_reg(pm4
, R_028354_PA_SC_RASTER_CONFIG_1
, raster_config_1
);
4739 static void si_set_raster_config(struct si_context
*sctx
, struct si_pm4_state
*pm4
)
4741 struct si_screen
*sscreen
= sctx
->screen
;
4742 unsigned num_rb
= MIN2(sctx
->screen
->info
.num_render_backends
, 16);
4743 unsigned rb_mask
= sctx
->screen
->info
.enabled_rb_mask
;
4744 unsigned raster_config
, raster_config_1
;
4746 switch (sctx
->b
.family
) {
4749 raster_config
= 0x2a00126a;
4750 raster_config_1
= 0x00000000;
4753 raster_config
= 0x0000124a;
4754 raster_config_1
= 0x00000000;
4757 raster_config
= 0x00000082;
4758 raster_config_1
= 0x00000000;
4761 raster_config
= 0x00000000;
4762 raster_config_1
= 0x00000000;
4765 raster_config
= 0x16000012;
4766 raster_config_1
= 0x00000000;
4769 raster_config
= 0x3a00161a;
4770 raster_config_1
= 0x0000002e;
4773 if (sscreen
->info
.cik_macrotile_mode_array
[0] == 0x000000e8) {
4774 /* old kernels with old tiling config */
4775 raster_config
= 0x16000012;
4776 raster_config_1
= 0x0000002a;
4778 raster_config
= 0x3a00161a;
4779 raster_config_1
= 0x0000002e;
4782 case CHIP_POLARIS10
:
4783 raster_config
= 0x16000012;
4784 raster_config_1
= 0x0000002a;
4786 case CHIP_POLARIS11
:
4787 case CHIP_POLARIS12
:
4788 raster_config
= 0x16000012;
4789 raster_config_1
= 0x00000000;
4792 raster_config
= 0x16000012;
4793 raster_config_1
= 0x0000002a;
4797 raster_config
= 0x00000000;
4799 raster_config
= 0x00000002;
4800 raster_config_1
= 0x00000000;
4803 raster_config
= 0x00000002;
4804 raster_config_1
= 0x00000000;
4807 /* KV should be 0x00000002, but that causes problems with radeon */
4808 raster_config
= 0x00000000; /* 0x00000002 */
4809 raster_config_1
= 0x00000000;
4814 raster_config
= 0x00000000;
4815 raster_config_1
= 0x00000000;
4819 "radeonsi: Unknown GPU, using 0 for raster_config\n");
4820 raster_config
= 0x00000000;
4821 raster_config_1
= 0x00000000;
4824 if (!rb_mask
|| util_bitcount(rb_mask
) >= num_rb
) {
4825 /* Always use the default config when all backends are enabled
4826 * (or when we failed to determine the enabled backends).
4828 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
,
4830 if (sctx
->b
.chip_class
>= CIK
)
4831 si_pm4_set_reg(pm4
, R_028354_PA_SC_RASTER_CONFIG_1
,
4834 si_write_harvested_raster_configs(sctx
, pm4
, raster_config
, raster_config_1
);
4838 static void si_init_config(struct si_context
*sctx
)
4840 struct si_screen
*sscreen
= sctx
->screen
;
4841 uint64_t border_color_va
= sctx
->border_color_buffer
->gpu_address
;
4842 bool has_clear_state
= sscreen
->has_clear_state
;
4843 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
4845 /* Only SI can disable CLEAR_STATE for now. */
4846 assert(has_clear_state
|| sscreen
->info
.chip_class
== SI
);
4851 si_pm4_cmd_begin(pm4
, PKT3_CONTEXT_CONTROL
);
4852 si_pm4_cmd_add(pm4
, CONTEXT_CONTROL_LOAD_ENABLE(1));
4853 si_pm4_cmd_add(pm4
, CONTEXT_CONTROL_SHADOW_ENABLE(1));
4854 si_pm4_cmd_end(pm4
, false);
4856 if (has_clear_state
) {
4857 si_pm4_cmd_begin(pm4
, PKT3_CLEAR_STATE
);
4858 si_pm4_cmd_add(pm4
, 0);
4859 si_pm4_cmd_end(pm4
, false);
4862 if (sctx
->b
.chip_class
<= VI
)
4863 si_set_raster_config(sctx
, pm4
);
4865 si_pm4_set_reg(pm4
, R_028A18_VGT_HOS_MAX_TESS_LEVEL
, fui(64));
4866 if (!has_clear_state
)
4867 si_pm4_set_reg(pm4
, R_028A1C_VGT_HOS_MIN_TESS_LEVEL
, fui(0));
4869 /* FIXME calculate these values somehow ??? */
4870 if (sctx
->b
.chip_class
<= VI
) {
4871 si_pm4_set_reg(pm4
, R_028A54_VGT_GS_PER_ES
, SI_GS_PER_ES
);
4872 si_pm4_set_reg(pm4
, R_028A58_VGT_ES_PER_GS
, 0x40);
4875 if (!has_clear_state
) {
4876 si_pm4_set_reg(pm4
, R_028A5C_VGT_GS_PER_VS
, 0x2);
4877 si_pm4_set_reg(pm4
, R_028A8C_VGT_PRIMITIVEID_RESET
, 0x0);
4878 si_pm4_set_reg(pm4
, R_028B98_VGT_STRMOUT_BUFFER_CONFIG
, 0x0);
4881 si_pm4_set_reg(pm4
, R_028AA0_VGT_INSTANCE_STEP_RATE_0
, 1);
4882 if (!has_clear_state
)
4883 si_pm4_set_reg(pm4
, R_028AB8_VGT_VTX_CNT_EN
, 0x0);
4884 if (sctx
->b
.chip_class
< CIK
)
4885 si_pm4_set_reg(pm4
, R_008A14_PA_CL_ENHANCE
, S_008A14_NUM_CLIP_SEQ(3) |
4886 S_008A14_CLIP_VTX_REORDER_ENA(1));
4888 si_pm4_set_reg(pm4
, R_028BD4_PA_SC_CENTROID_PRIORITY_0
, 0x76543210);
4889 si_pm4_set_reg(pm4
, R_028BD8_PA_SC_CENTROID_PRIORITY_1
, 0xfedcba98);
4891 if (!has_clear_state
)
4892 si_pm4_set_reg(pm4
, R_02882C_PA_SU_PRIM_FILTER_CNTL
, 0);
4894 /* CLEAR_STATE doesn't clear these correctly on certain generations.
4895 * I don't know why. Deduced by trial and error.
4897 if (sctx
->b
.chip_class
<= CIK
) {
4898 si_pm4_set_reg(pm4
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
4899 si_pm4_set_reg(pm4
, R_028204_PA_SC_WINDOW_SCISSOR_TL
, S_028204_WINDOW_OFFSET_DISABLE(1));
4900 si_pm4_set_reg(pm4
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, S_028240_WINDOW_OFFSET_DISABLE(1));
4901 si_pm4_set_reg(pm4
, R_028244_PA_SC_GENERIC_SCISSOR_BR
,
4902 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
4903 si_pm4_set_reg(pm4
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 0);
4904 si_pm4_set_reg(pm4
, R_028034_PA_SC_SCREEN_SCISSOR_BR
,
4905 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
4908 if (!has_clear_state
) {
4909 si_pm4_set_reg(pm4
, R_02820C_PA_SC_CLIPRECT_RULE
, 0xFFFF);
4910 si_pm4_set_reg(pm4
, R_028230_PA_SC_EDGERULE
,
4911 S_028230_ER_TRI(0xA) |
4912 S_028230_ER_POINT(0xA) |
4913 S_028230_ER_RECT(0xA) |
4914 /* Required by DX10_DIAMOND_TEST_ENA: */
4915 S_028230_ER_LINE_LR(0x1A) |
4916 S_028230_ER_LINE_RL(0x26) |
4917 S_028230_ER_LINE_TB(0xA) |
4918 S_028230_ER_LINE_BT(0xA));
4919 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
4920 si_pm4_set_reg(pm4
, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET
, 0);
4921 si_pm4_set_reg(pm4
, R_028820_PA_CL_NANINF_CNTL
, 0);
4922 si_pm4_set_reg(pm4
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 0x0);
4923 si_pm4_set_reg(pm4
, R_028AC4_DB_SRESULTS_COMPARE_STATE1
, 0x0);
4924 si_pm4_set_reg(pm4
, R_028AC8_DB_PRELOAD_CONTROL
, 0x0);
4925 si_pm4_set_reg(pm4
, R_02800C_DB_RENDER_OVERRIDE
, 0);
4928 if (sctx
->b
.chip_class
>= GFX9
) {
4929 si_pm4_set_reg(pm4
, R_030920_VGT_MAX_VTX_INDX
, ~0);
4930 si_pm4_set_reg(pm4
, R_030924_VGT_MIN_VTX_INDX
, 0);
4931 si_pm4_set_reg(pm4
, R_030928_VGT_INDX_OFFSET
, 0);
4933 /* These registers, when written, also overwrite the CLEAR_STATE
4934 * context, so we can't rely on CLEAR_STATE setting them.
4935 * It would be an issue if there was another UMD changing them.
4937 si_pm4_set_reg(pm4
, R_028400_VGT_MAX_VTX_INDX
, ~0);
4938 si_pm4_set_reg(pm4
, R_028404_VGT_MIN_VTX_INDX
, 0);
4939 si_pm4_set_reg(pm4
, R_028408_VGT_INDX_OFFSET
, 0);
4942 if (sctx
->b
.chip_class
>= CIK
) {
4943 if (sctx
->b
.chip_class
>= GFX9
) {
4944 si_pm4_set_reg(pm4
, R_00B41C_SPI_SHADER_PGM_RSRC3_HS
,
4945 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
4947 si_pm4_set_reg(pm4
, R_00B51C_SPI_SHADER_PGM_RSRC3_LS
,
4948 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
4949 si_pm4_set_reg(pm4
, R_00B41C_SPI_SHADER_PGM_RSRC3_HS
,
4950 S_00B41C_WAVE_LIMIT(0x3F));
4951 si_pm4_set_reg(pm4
, R_00B31C_SPI_SHADER_PGM_RSRC3_ES
,
4952 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
4954 /* If this is 0, Bonaire can hang even if GS isn't being used.
4955 * Other chips are unaffected. These are suboptimal values,
4956 * but we don't use on-chip GS.
4958 si_pm4_set_reg(pm4
, R_028A44_VGT_GS_ONCHIP_CNTL
,
4959 S_028A44_ES_VERTS_PER_SUBGRP(64) |
4960 S_028A44_GS_PRIMS_PER_SUBGRP(4));
4962 si_pm4_set_reg(pm4
, R_00B21C_SPI_SHADER_PGM_RSRC3_GS
,
4963 S_00B21C_CU_EN(0xffff) | S_00B21C_WAVE_LIMIT(0x3F));
4965 /* Compute LATE_ALLOC_VS.LIMIT. */
4966 unsigned num_cu_per_sh
= sscreen
->info
.num_good_compute_units
/
4967 (sscreen
->info
.max_se
*
4968 sscreen
->info
.max_sh_per_se
);
4969 unsigned late_alloc_limit
; /* The limit is per SH. */
4971 if (sctx
->b
.family
== CHIP_KABINI
) {
4972 late_alloc_limit
= 0; /* Potential hang on Kabini. */
4973 } else if (num_cu_per_sh
<= 4) {
4974 /* Too few available compute units per SH. Disallowing
4975 * VS to run on one CU could hurt us more than late VS
4976 * allocation would help.
4978 * 2 is the highest safe number that allows us to keep
4981 late_alloc_limit
= 2;
4983 /* This is a good initial value, allowing 1 late_alloc
4984 * wave per SIMD on num_cu - 2.
4986 late_alloc_limit
= (num_cu_per_sh
- 2) * 4;
4988 /* The limit is 0-based, so 0 means 1. */
4989 assert(late_alloc_limit
> 0 && late_alloc_limit
<= 64);
4990 late_alloc_limit
-= 1;
4993 /* VS can't execute on one CU if the limit is > 2. */
4994 si_pm4_set_reg(pm4
, R_00B118_SPI_SHADER_PGM_RSRC3_VS
,
4995 S_00B118_CU_EN(late_alloc_limit
> 2 ? 0xfffe : 0xffff) |
4996 S_00B118_WAVE_LIMIT(0x3F));
4997 si_pm4_set_reg(pm4
, R_00B11C_SPI_SHADER_LATE_ALLOC_VS
,
4998 S_00B11C_LIMIT(late_alloc_limit
));
4999 si_pm4_set_reg(pm4
, R_00B01C_SPI_SHADER_PGM_RSRC3_PS
,
5000 S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
5003 if (sctx
->b
.chip_class
>= VI
) {
5004 unsigned vgt_tess_distribution
;
5006 vgt_tess_distribution
=
5007 S_028B50_ACCUM_ISOLINE(32) |
5008 S_028B50_ACCUM_TRI(11) |
5009 S_028B50_ACCUM_QUAD(11) |
5010 S_028B50_DONUT_SPLIT(16);
5012 /* Testing with Unigine Heaven extreme tesselation yielded best results
5013 * with TRAP_SPLIT = 3.
5015 if (sctx
->b
.family
== CHIP_FIJI
||
5016 sctx
->b
.family
>= CHIP_POLARIS10
)
5017 vgt_tess_distribution
|= S_028B50_TRAP_SPLIT(3);
5019 si_pm4_set_reg(pm4
, R_028B50_VGT_TESS_DISTRIBUTION
, vgt_tess_distribution
);
5020 } else if (!has_clear_state
) {
5021 si_pm4_set_reg(pm4
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
, 14);
5022 si_pm4_set_reg(pm4
, R_028C5C_VGT_OUT_DEALLOC_CNTL
, 16);
5025 si_pm4_set_reg(pm4
, R_028080_TA_BC_BASE_ADDR
, border_color_va
>> 8);
5026 if (sctx
->b
.chip_class
>= CIK
)
5027 si_pm4_set_reg(pm4
, R_028084_TA_BC_BASE_ADDR_HI
, border_color_va
>> 40);
5028 si_pm4_add_bo(pm4
, sctx
->border_color_buffer
, RADEON_USAGE_READ
,
5029 RADEON_PRIO_BORDER_COLORS
);
5031 if (sctx
->b
.chip_class
>= GFX9
) {
5032 unsigned num_se
= sscreen
->info
.max_se
;
5033 unsigned pc_lines
= 0;
5035 switch (sctx
->b
.family
) {
5046 si_pm4_set_reg(pm4
, R_028C48_PA_SC_BINNER_CNTL_1
,
5047 S_028C48_MAX_ALLOC_COUNT(MIN2(128, pc_lines
/ (4 * num_se
))) |
5048 S_028C48_MAX_PRIM_PER_BATCH(1023));
5049 si_pm4_set_reg(pm4
, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
,
5050 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
5051 si_pm4_set_reg(pm4
, R_030968_VGT_INSTANCE_BASE_ID
, 0);
5054 si_pm4_upload_indirect_buffer(sctx
, pm4
);
5055 sctx
->init_config
= pm4
;