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r600g/llvm: Support for TBO
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "util/u_memory.h"
28 #include "util/u_framebuffer.h"
29 #include "util/u_blitter.h"
30 #include "util/u_helpers.h"
31 #include "util/u_math.h"
32 #include "util/u_pack_color.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "radeonsi_pipe.h"
35 #include "radeonsi_shader.h"
36 #include "si_state.h"
37 #include "sid.h"
38
39 /*
40 * inferred framebuffer and blender state
41 */
42 static void si_update_fb_blend_state(struct r600_context *rctx)
43 {
44 struct si_pm4_state *pm4;
45 struct si_state_blend *blend = rctx->queued.named.blend;
46 uint32_t mask;
47
48 if (blend == NULL)
49 return;
50
51 pm4 = CALLOC_STRUCT(si_pm4_state);
52 if (pm4 == NULL)
53 return;
54
55 mask = (1ULL << ((unsigned)rctx->framebuffer.nr_cbufs * 4)) - 1;
56 mask &= blend->cb_target_mask;
57 si_pm4_set_reg(pm4, R_028238_CB_TARGET_MASK, mask);
58
59 si_pm4_set_state(rctx, fb_blend, pm4);
60 }
61
62 /*
63 * Blender functions
64 */
65
66 static uint32_t si_translate_blend_function(int blend_func)
67 {
68 switch (blend_func) {
69 case PIPE_BLEND_ADD:
70 return V_028780_COMB_DST_PLUS_SRC;
71 case PIPE_BLEND_SUBTRACT:
72 return V_028780_COMB_SRC_MINUS_DST;
73 case PIPE_BLEND_REVERSE_SUBTRACT:
74 return V_028780_COMB_DST_MINUS_SRC;
75 case PIPE_BLEND_MIN:
76 return V_028780_COMB_MIN_DST_SRC;
77 case PIPE_BLEND_MAX:
78 return V_028780_COMB_MAX_DST_SRC;
79 default:
80 R600_ERR("Unknown blend function %d\n", blend_func);
81 assert(0);
82 break;
83 }
84 return 0;
85 }
86
87 static uint32_t si_translate_blend_factor(int blend_fact)
88 {
89 switch (blend_fact) {
90 case PIPE_BLENDFACTOR_ONE:
91 return V_028780_BLEND_ONE;
92 case PIPE_BLENDFACTOR_SRC_COLOR:
93 return V_028780_BLEND_SRC_COLOR;
94 case PIPE_BLENDFACTOR_SRC_ALPHA:
95 return V_028780_BLEND_SRC_ALPHA;
96 case PIPE_BLENDFACTOR_DST_ALPHA:
97 return V_028780_BLEND_DST_ALPHA;
98 case PIPE_BLENDFACTOR_DST_COLOR:
99 return V_028780_BLEND_DST_COLOR;
100 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
101 return V_028780_BLEND_SRC_ALPHA_SATURATE;
102 case PIPE_BLENDFACTOR_CONST_COLOR:
103 return V_028780_BLEND_CONSTANT_COLOR;
104 case PIPE_BLENDFACTOR_CONST_ALPHA:
105 return V_028780_BLEND_CONSTANT_ALPHA;
106 case PIPE_BLENDFACTOR_ZERO:
107 return V_028780_BLEND_ZERO;
108 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
109 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
110 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
111 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
112 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
113 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
114 case PIPE_BLENDFACTOR_INV_DST_COLOR:
115 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
116 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
117 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
118 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
119 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
120 case PIPE_BLENDFACTOR_SRC1_COLOR:
121 return V_028780_BLEND_SRC1_COLOR;
122 case PIPE_BLENDFACTOR_SRC1_ALPHA:
123 return V_028780_BLEND_SRC1_ALPHA;
124 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
125 return V_028780_BLEND_INV_SRC1_COLOR;
126 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
127 return V_028780_BLEND_INV_SRC1_ALPHA;
128 default:
129 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
130 assert(0);
131 break;
132 }
133 return 0;
134 }
135
136 static void *si_create_blend_state(struct pipe_context *ctx,
137 const struct pipe_blend_state *state)
138 {
139 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
140 struct si_pm4_state *pm4 = &blend->pm4;
141
142 uint32_t color_control;
143
144 if (blend == NULL)
145 return NULL;
146
147 color_control = S_028808_MODE(V_028808_CB_NORMAL);
148 if (state->logicop_enable) {
149 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
150 } else {
151 color_control |= S_028808_ROP3(0xcc);
152 }
153 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
154
155 si_pm4_set_reg(pm4, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, ~0);
156 si_pm4_set_reg(pm4, R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, ~0);
157
158 blend->cb_target_mask = 0;
159 for (int i = 0; i < 8; i++) {
160 /* state->rt entries > 0 only written if independent blending */
161 const int j = state->independent_blend_enable ? i : 0;
162
163 unsigned eqRGB = state->rt[j].rgb_func;
164 unsigned srcRGB = state->rt[j].rgb_src_factor;
165 unsigned dstRGB = state->rt[j].rgb_dst_factor;
166 unsigned eqA = state->rt[j].alpha_func;
167 unsigned srcA = state->rt[j].alpha_src_factor;
168 unsigned dstA = state->rt[j].alpha_dst_factor;
169
170 unsigned blend_cntl = 0;
171
172 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
173 blend->cb_target_mask |= state->rt[j].colormask << (4 * i);
174
175 if (!state->rt[j].blend_enable) {
176 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
177 continue;
178 }
179
180 blend_cntl |= S_028780_ENABLE(1);
181 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
182 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
183 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
184
185 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
186 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
187 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
188 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
189 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
190 }
191 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
192 }
193
194 return blend;
195 }
196
197 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
198 {
199 struct r600_context *rctx = (struct r600_context *)ctx;
200 si_pm4_bind_state(rctx, blend, (struct si_state_blend *)state);
201 si_update_fb_blend_state(rctx);
202 }
203
204 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
205 {
206 struct r600_context *rctx = (struct r600_context *)ctx;
207 si_pm4_delete_state(rctx, blend, (struct si_state_blend *)state);
208 }
209
210 static void si_set_blend_color(struct pipe_context *ctx,
211 const struct pipe_blend_color *state)
212 {
213 struct r600_context *rctx = (struct r600_context *)ctx;
214 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
215
216 if (pm4 == NULL)
217 return;
218
219 si_pm4_set_reg(pm4, R_028414_CB_BLEND_RED, fui(state->color[0]));
220 si_pm4_set_reg(pm4, R_028418_CB_BLEND_GREEN, fui(state->color[1]));
221 si_pm4_set_reg(pm4, R_02841C_CB_BLEND_BLUE, fui(state->color[2]));
222 si_pm4_set_reg(pm4, R_028420_CB_BLEND_ALPHA, fui(state->color[3]));
223
224 si_pm4_set_state(rctx, blend_color, pm4);
225 }
226
227 /*
228 * Clipping, scissors and viewport
229 */
230
231 static void si_set_clip_state(struct pipe_context *ctx,
232 const struct pipe_clip_state *state)
233 {
234 struct r600_context *rctx = (struct r600_context *)ctx;
235 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
236
237 if (pm4 == NULL)
238 return;
239
240 for (int i = 0; i < 6; i++) {
241 si_pm4_set_reg(pm4, R_0285BC_PA_CL_UCP_0_X + i * 16,
242 fui(state->ucp[i][0]));
243 si_pm4_set_reg(pm4, R_0285C0_PA_CL_UCP_0_Y + i * 16,
244 fui(state->ucp[i][1]));
245 si_pm4_set_reg(pm4, R_0285C4_PA_CL_UCP_0_Z + i * 16,
246 fui(state->ucp[i][2]));
247 si_pm4_set_reg(pm4, R_0285C8_PA_CL_UCP_0_W + i * 16,
248 fui(state->ucp[i][3]));
249 }
250
251 si_pm4_set_state(rctx, clip, pm4);
252 }
253
254 static void si_set_scissor_state(struct pipe_context *ctx,
255 const struct pipe_scissor_state *state)
256 {
257 struct r600_context *rctx = (struct r600_context *)ctx;
258 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
259 uint32_t tl, br;
260
261 if (pm4 == NULL)
262 return;
263
264 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny);
265 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
266 si_pm4_set_reg(pm4, R_028210_PA_SC_CLIPRECT_0_TL, tl);
267 si_pm4_set_reg(pm4, R_028214_PA_SC_CLIPRECT_0_BR, br);
268 si_pm4_set_reg(pm4, R_028218_PA_SC_CLIPRECT_1_TL, tl);
269 si_pm4_set_reg(pm4, R_02821C_PA_SC_CLIPRECT_1_BR, br);
270 si_pm4_set_reg(pm4, R_028220_PA_SC_CLIPRECT_2_TL, tl);
271 si_pm4_set_reg(pm4, R_028224_PA_SC_CLIPRECT_2_BR, br);
272 si_pm4_set_reg(pm4, R_028228_PA_SC_CLIPRECT_3_TL, tl);
273 si_pm4_set_reg(pm4, R_02822C_PA_SC_CLIPRECT_3_BR, br);
274
275 si_pm4_set_state(rctx, scissor, pm4);
276 }
277
278 static void si_set_viewport_state(struct pipe_context *ctx,
279 const struct pipe_viewport_state *state)
280 {
281 struct r600_context *rctx = (struct r600_context *)ctx;
282 struct si_state_viewport *viewport = CALLOC_STRUCT(si_state_viewport);
283 struct si_pm4_state *pm4 = &viewport->pm4;
284
285 if (viewport == NULL)
286 return;
287
288 viewport->viewport = *state;
289 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000);
290 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000);
291 si_pm4_set_reg(pm4, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
292 si_pm4_set_reg(pm4, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
293 si_pm4_set_reg(pm4, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
294 si_pm4_set_reg(pm4, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
295 si_pm4_set_reg(pm4, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
296 si_pm4_set_reg(pm4, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
297 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
298
299 si_pm4_set_state(rctx, viewport, viewport);
300 }
301
302 /*
303 * inferred state between framebuffer and rasterizer
304 */
305 static void si_update_fb_rs_state(struct r600_context *rctx)
306 {
307 struct si_state_rasterizer *rs = rctx->queued.named.rasterizer;
308 struct si_pm4_state *pm4;
309 unsigned offset_db_fmt_cntl = 0, depth;
310 float offset_units;
311
312 if (!rs || !rctx->framebuffer.zsbuf)
313 return;
314
315 offset_units = rctx->queued.named.rasterizer->offset_units;
316 switch (rctx->framebuffer.zsbuf->texture->format) {
317 case PIPE_FORMAT_Z24X8_UNORM:
318 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
319 depth = -24;
320 offset_units *= 2.0f;
321 break;
322 case PIPE_FORMAT_Z32_FLOAT:
323 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
324 depth = -23;
325 offset_units *= 1.0f;
326 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
327 break;
328 case PIPE_FORMAT_Z16_UNORM:
329 depth = -16;
330 offset_units *= 4.0f;
331 break;
332 default:
333 return;
334 }
335
336 pm4 = CALLOC_STRUCT(si_pm4_state);
337 /* FIXME some of those reg can be computed with cso */
338 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
339 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
340 fui(rctx->queued.named.rasterizer->offset_scale));
341 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units));
342 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
343 fui(rctx->queued.named.rasterizer->offset_scale));
344 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units));
345 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, offset_db_fmt_cntl);
346
347 si_pm4_set_state(rctx, fb_rs, pm4);
348 }
349
350 /*
351 * Rasterizer
352 */
353
354 static uint32_t si_translate_fill(uint32_t func)
355 {
356 switch(func) {
357 case PIPE_POLYGON_MODE_FILL:
358 return V_028814_X_DRAW_TRIANGLES;
359 case PIPE_POLYGON_MODE_LINE:
360 return V_028814_X_DRAW_LINES;
361 case PIPE_POLYGON_MODE_POINT:
362 return V_028814_X_DRAW_POINTS;
363 default:
364 assert(0);
365 return V_028814_X_DRAW_POINTS;
366 }
367 }
368
369 static void *si_create_rs_state(struct pipe_context *ctx,
370 const struct pipe_rasterizer_state *state)
371 {
372 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
373 struct si_pm4_state *pm4 = &rs->pm4;
374 unsigned tmp;
375 unsigned prov_vtx = 1, polygon_dual_mode;
376 unsigned clip_rule;
377 float psize_min, psize_max;
378
379 if (rs == NULL) {
380 return NULL;
381 }
382
383 rs->two_side = state->light_twoside;
384
385 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
386 state->fill_back != PIPE_POLYGON_MODE_FILL);
387
388 if (state->flatshade_first)
389 prov_vtx = 0;
390
391 rs->flatshade = state->flatshade;
392 rs->sprite_coord_enable = state->sprite_coord_enable;
393 rs->pa_sc_line_stipple = state->line_stipple_enable ?
394 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
395 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
396 rs->pa_su_sc_mode_cntl =
397 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
398 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
399 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
400 S_028814_FACE(!state->front_ccw) |
401 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
402 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
403 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
404 S_028814_POLY_MODE(polygon_dual_mode) |
405 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
406 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back));
407 rs->pa_cl_clip_cntl =
408 S_028810_PS_UCP_MODE(3) |
409 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
410 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
411 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
412 rs->pa_cl_vs_out_cntl =
413 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
414 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex);
415
416 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
417
418 /* offset */
419 rs->offset_units = state->offset_units;
420 rs->offset_scale = state->offset_scale * 12.0f;
421
422 /* XXX: Flat shading hangs the GPU */
423 tmp = S_0286D4_FLAT_SHADE_ENA(0);
424 if (state->sprite_coord_enable) {
425 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
426 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
427 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
428 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
429 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1);
430 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
431 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
432 }
433 }
434 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
435
436 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0x00000000);
437 /* point size 12.4 fixed point */
438 tmp = (unsigned)(state->point_size * 8.0);
439 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
440
441 if (state->point_size_per_vertex) {
442 psize_min = util_get_min_point_size(state);
443 psize_max = 8192;
444 } else {
445 /* Force the point size to be as if the vertex output was disabled. */
446 psize_min = state->point_size;
447 psize_max = state->point_size;
448 }
449 /* Divide by two, because 0.5 = 1 pixel. */
450 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
451 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
452 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
453
454 tmp = (unsigned)state->line_width * 8;
455 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
456 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
457 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable));
458
459 si_pm4_set_reg(pm4, R_028BDC_PA_SC_LINE_CNTL, 0x00000400);
460 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
461 S_028BE4_PIX_CENTER(state->gl_rasterization_rules));
462 si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000);
463 si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000);
464 si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000);
465 si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000);
466
467 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
468 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule);
469
470 return rs;
471 }
472
473 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
474 {
475 struct r600_context *rctx = (struct r600_context *)ctx;
476 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
477
478 if (state == NULL)
479 return;
480
481 // TODO
482 rctx->sprite_coord_enable = rs->sprite_coord_enable;
483 rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
484 rctx->pa_su_sc_mode_cntl = rs->pa_su_sc_mode_cntl;
485 rctx->pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
486 rctx->pa_cl_vs_out_cntl = rs->pa_cl_vs_out_cntl;
487
488 si_pm4_bind_state(rctx, rasterizer, rs);
489 si_update_fb_rs_state(rctx);
490 }
491
492 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
493 {
494 struct r600_context *rctx = (struct r600_context *)ctx;
495 si_pm4_delete_state(rctx, rasterizer, (struct si_state_rasterizer *)state);
496 }
497
498 /*
499 * infeered state between dsa and stencil ref
500 */
501 static void si_update_dsa_stencil_ref(struct r600_context *rctx)
502 {
503 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
504 struct pipe_stencil_ref *ref = &rctx->stencil_ref;
505 struct si_state_dsa *dsa = rctx->queued.named.dsa;
506
507 if (pm4 == NULL)
508 return;
509
510 si_pm4_set_reg(pm4, R_028430_DB_STENCILREFMASK,
511 S_028430_STENCILTESTVAL(ref->ref_value[0]) |
512 S_028430_STENCILMASK(dsa->valuemask[0]) |
513 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
514 S_028430_STENCILOPVAL(1));
515 si_pm4_set_reg(pm4, R_028434_DB_STENCILREFMASK_BF,
516 S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
517 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
518 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
519 S_028434_STENCILOPVAL_BF(1));
520
521 si_pm4_set_state(rctx, dsa_stencil_ref, pm4);
522 }
523
524 static void si_set_pipe_stencil_ref(struct pipe_context *ctx,
525 const struct pipe_stencil_ref *state)
526 {
527 struct r600_context *rctx = (struct r600_context *)ctx;
528 rctx->stencil_ref = *state;
529 si_update_dsa_stencil_ref(rctx);
530 }
531
532
533 /*
534 * DSA
535 */
536
537 static uint32_t si_translate_stencil_op(int s_op)
538 {
539 switch (s_op) {
540 case PIPE_STENCIL_OP_KEEP:
541 return V_02842C_STENCIL_KEEP;
542 case PIPE_STENCIL_OP_ZERO:
543 return V_02842C_STENCIL_ZERO;
544 case PIPE_STENCIL_OP_REPLACE:
545 return V_02842C_STENCIL_REPLACE_TEST;
546 case PIPE_STENCIL_OP_INCR:
547 return V_02842C_STENCIL_ADD_CLAMP;
548 case PIPE_STENCIL_OP_DECR:
549 return V_02842C_STENCIL_SUB_CLAMP;
550 case PIPE_STENCIL_OP_INCR_WRAP:
551 return V_02842C_STENCIL_ADD_WRAP;
552 case PIPE_STENCIL_OP_DECR_WRAP:
553 return V_02842C_STENCIL_SUB_WRAP;
554 case PIPE_STENCIL_OP_INVERT:
555 return V_02842C_STENCIL_INVERT;
556 default:
557 R600_ERR("Unknown stencil op %d", s_op);
558 assert(0);
559 break;
560 }
561 return 0;
562 }
563
564 static void *si_create_dsa_state(struct pipe_context *ctx,
565 const struct pipe_depth_stencil_alpha_state *state)
566 {
567 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
568 struct si_pm4_state *pm4 = &dsa->pm4;
569 unsigned db_depth_control;
570 unsigned db_render_override, db_render_control;
571 uint32_t db_stencil_control = 0;
572
573 if (dsa == NULL) {
574 return NULL;
575 }
576
577 dsa->valuemask[0] = state->stencil[0].valuemask;
578 dsa->valuemask[1] = state->stencil[1].valuemask;
579 dsa->writemask[0] = state->stencil[0].writemask;
580 dsa->writemask[1] = state->stencil[1].writemask;
581
582 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
583 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
584 S_028800_ZFUNC(state->depth.func);
585
586 /* stencil */
587 if (state->stencil[0].enabled) {
588 db_depth_control |= S_028800_STENCIL_ENABLE(1);
589 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
590 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
591 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
592 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
593
594 if (state->stencil[1].enabled) {
595 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
596 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
597 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
598 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
599 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
600 }
601 }
602
603 /* alpha */
604 if (state->alpha.enabled) {
605 dsa->alpha_func = state->alpha.func;
606 dsa->alpha_ref = state->alpha.ref_value;
607 } else {
608 dsa->alpha_func = PIPE_FUNC_ALWAYS;
609 }
610
611 /* misc */
612 db_render_control = 0;
613 db_render_override = S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
614 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
615 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
616 /* TODO db_render_override depends on query */
617 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, 0x00000000);
618 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, 0x00000000);
619 si_pm4_set_reg(pm4, R_028028_DB_STENCIL_CLEAR, 0x00000000);
620 si_pm4_set_reg(pm4, R_02802C_DB_DEPTH_CLEAR, 0x3F800000);
621 //si_pm4_set_reg(pm4, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control);
622 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
623 si_pm4_set_reg(pm4, R_028000_DB_RENDER_CONTROL, db_render_control);
624 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
625 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
626 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
627 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
628 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
629 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00);
630 dsa->db_render_override = db_render_override;
631
632 return dsa;
633 }
634
635 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
636 {
637 struct r600_context *rctx = (struct r600_context *)ctx;
638 struct si_state_dsa *dsa = state;
639
640 if (state == NULL)
641 return;
642
643 si_pm4_bind_state(rctx, dsa, dsa);
644 si_update_dsa_stencil_ref(rctx);
645 }
646
647 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
648 {
649 struct r600_context *rctx = (struct r600_context *)ctx;
650 si_pm4_delete_state(rctx, dsa, (struct si_state_dsa *)state);
651 }
652
653 static void *si_create_db_flush_dsa(struct r600_context *rctx, bool copy_depth,
654 bool copy_stencil)
655 {
656 struct pipe_depth_stencil_alpha_state dsa;
657 struct si_state_dsa *state;
658
659 memset(&dsa, 0, sizeof(dsa));
660
661 state = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
662 if (copy_depth || copy_stencil) {
663 si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL,
664 S_028000_DEPTH_COPY(copy_depth) |
665 S_028000_STENCIL_COPY(copy_stencil) |
666 S_028000_COPY_CENTROID(1));
667 } else {
668 si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL,
669 S_028000_DEPTH_COMPRESS_DISABLE(1) |
670 S_028000_STENCIL_COMPRESS_DISABLE(1));
671 si_pm4_set_reg(&state->pm4, R_02800C_DB_RENDER_OVERRIDE,
672 S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
673 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
674 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE) |
675 S_02800C_DISABLE_TILE_RATE_TILES(1));
676 }
677
678 return state;
679 }
680
681 /*
682 * format translation
683 */
684 static uint32_t si_translate_colorformat(enum pipe_format format)
685 {
686 switch (format) {
687 /* 8-bit buffers. */
688 case PIPE_FORMAT_A8_UNORM:
689 case PIPE_FORMAT_A8_SNORM:
690 case PIPE_FORMAT_A8_UINT:
691 case PIPE_FORMAT_A8_SINT:
692 case PIPE_FORMAT_I8_UNORM:
693 case PIPE_FORMAT_I8_SNORM:
694 case PIPE_FORMAT_I8_UINT:
695 case PIPE_FORMAT_I8_SINT:
696 case PIPE_FORMAT_L8_UNORM:
697 case PIPE_FORMAT_L8_SNORM:
698 case PIPE_FORMAT_L8_UINT:
699 case PIPE_FORMAT_L8_SINT:
700 case PIPE_FORMAT_L8_SRGB:
701 case PIPE_FORMAT_R8_UNORM:
702 case PIPE_FORMAT_R8_SNORM:
703 case PIPE_FORMAT_R8_UINT:
704 case PIPE_FORMAT_R8_SINT:
705 return V_028C70_COLOR_8;
706
707 /* 16-bit buffers. */
708 case PIPE_FORMAT_B5G6R5_UNORM:
709 return V_028C70_COLOR_5_6_5;
710
711 case PIPE_FORMAT_B5G5R5A1_UNORM:
712 case PIPE_FORMAT_B5G5R5X1_UNORM:
713 return V_028C70_COLOR_1_5_5_5;
714
715 case PIPE_FORMAT_B4G4R4A4_UNORM:
716 case PIPE_FORMAT_B4G4R4X4_UNORM:
717 return V_028C70_COLOR_4_4_4_4;
718
719 case PIPE_FORMAT_L8A8_UNORM:
720 case PIPE_FORMAT_L8A8_SNORM:
721 case PIPE_FORMAT_L8A8_UINT:
722 case PIPE_FORMAT_L8A8_SINT:
723 case PIPE_FORMAT_R8G8_SNORM:
724 case PIPE_FORMAT_R8G8_UNORM:
725 case PIPE_FORMAT_R8G8_UINT:
726 case PIPE_FORMAT_R8G8_SINT:
727 return V_028C70_COLOR_8_8;
728
729 case PIPE_FORMAT_Z16_UNORM:
730 case PIPE_FORMAT_R16_UNORM:
731 case PIPE_FORMAT_R16_SNORM:
732 case PIPE_FORMAT_R16_UINT:
733 case PIPE_FORMAT_R16_SINT:
734 case PIPE_FORMAT_R16_FLOAT:
735 case PIPE_FORMAT_L16_UNORM:
736 case PIPE_FORMAT_L16_SNORM:
737 case PIPE_FORMAT_L16_FLOAT:
738 case PIPE_FORMAT_I16_UNORM:
739 case PIPE_FORMAT_I16_SNORM:
740 case PIPE_FORMAT_I16_FLOAT:
741 case PIPE_FORMAT_A16_UNORM:
742 case PIPE_FORMAT_A16_SNORM:
743 case PIPE_FORMAT_A16_FLOAT:
744 return V_028C70_COLOR_16;
745
746 /* 32-bit buffers. */
747 case PIPE_FORMAT_A8B8G8R8_SRGB:
748 case PIPE_FORMAT_A8B8G8R8_UNORM:
749 case PIPE_FORMAT_A8R8G8B8_UNORM:
750 case PIPE_FORMAT_B8G8R8A8_SRGB:
751 case PIPE_FORMAT_B8G8R8A8_UNORM:
752 case PIPE_FORMAT_B8G8R8X8_UNORM:
753 case PIPE_FORMAT_R8G8B8A8_SNORM:
754 case PIPE_FORMAT_R8G8B8A8_UNORM:
755 case PIPE_FORMAT_R8G8B8X8_UNORM:
756 case PIPE_FORMAT_R8G8B8X8_SNORM:
757 case PIPE_FORMAT_R8G8B8X8_SRGB:
758 case PIPE_FORMAT_R8G8B8X8_UINT:
759 case PIPE_FORMAT_R8G8B8X8_SINT:
760 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
761 case PIPE_FORMAT_X8B8G8R8_UNORM:
762 case PIPE_FORMAT_X8R8G8B8_UNORM:
763 case PIPE_FORMAT_R8G8B8_UNORM:
764 case PIPE_FORMAT_R8G8B8A8_SSCALED:
765 case PIPE_FORMAT_R8G8B8A8_USCALED:
766 case PIPE_FORMAT_R8G8B8A8_SINT:
767 case PIPE_FORMAT_R8G8B8A8_UINT:
768 return V_028C70_COLOR_8_8_8_8;
769
770 case PIPE_FORMAT_R10G10B10A2_UNORM:
771 case PIPE_FORMAT_R10G10B10X2_SNORM:
772 case PIPE_FORMAT_B10G10R10A2_UNORM:
773 case PIPE_FORMAT_B10G10R10A2_UINT:
774 case PIPE_FORMAT_B10G10R10X2_UNORM:
775 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
776 return V_028C70_COLOR_2_10_10_10;
777
778 case PIPE_FORMAT_Z24X8_UNORM:
779 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
780 return V_028C70_COLOR_8_24;
781
782 case PIPE_FORMAT_X8Z24_UNORM:
783 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
784 return V_028C70_COLOR_24_8;
785
786 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
787 return V_028C70_COLOR_X24_8_32_FLOAT;
788
789 case PIPE_FORMAT_I32_FLOAT:
790 case PIPE_FORMAT_L32_FLOAT:
791 case PIPE_FORMAT_R32_FLOAT:
792 case PIPE_FORMAT_A32_FLOAT:
793 case PIPE_FORMAT_Z32_FLOAT:
794 return V_028C70_COLOR_32;
795
796 case PIPE_FORMAT_L16A16_UNORM:
797 case PIPE_FORMAT_L16A16_SNORM:
798 case PIPE_FORMAT_L16A16_FLOAT:
799 case PIPE_FORMAT_R16G16_SSCALED:
800 case PIPE_FORMAT_R16G16_UNORM:
801 case PIPE_FORMAT_R16G16_SNORM:
802 case PIPE_FORMAT_R16G16_UINT:
803 case PIPE_FORMAT_R16G16_SINT:
804 case PIPE_FORMAT_R16G16_FLOAT:
805 return V_028C70_COLOR_16_16;
806
807 case PIPE_FORMAT_R11G11B10_FLOAT:
808 return V_028C70_COLOR_10_11_11;
809
810 /* 64-bit buffers. */
811 case PIPE_FORMAT_R16G16B16A16_UINT:
812 case PIPE_FORMAT_R16G16B16A16_SINT:
813 case PIPE_FORMAT_R16G16B16A16_USCALED:
814 case PIPE_FORMAT_R16G16B16A16_SSCALED:
815 case PIPE_FORMAT_R16G16B16A16_UNORM:
816 case PIPE_FORMAT_R16G16B16A16_SNORM:
817 case PIPE_FORMAT_R16G16B16A16_FLOAT:
818 case PIPE_FORMAT_R16G16B16X16_UNORM:
819 case PIPE_FORMAT_R16G16B16X16_SNORM:
820 case PIPE_FORMAT_R16G16B16X16_FLOAT:
821 case PIPE_FORMAT_R16G16B16X16_UINT:
822 case PIPE_FORMAT_R16G16B16X16_SINT:
823 return V_028C70_COLOR_16_16_16_16;
824
825 case PIPE_FORMAT_L32A32_FLOAT:
826 case PIPE_FORMAT_L32A32_UINT:
827 case PIPE_FORMAT_L32A32_SINT:
828 case PIPE_FORMAT_R32G32_FLOAT:
829 case PIPE_FORMAT_R32G32_USCALED:
830 case PIPE_FORMAT_R32G32_SSCALED:
831 case PIPE_FORMAT_R32G32_SINT:
832 case PIPE_FORMAT_R32G32_UINT:
833 return V_028C70_COLOR_32_32;
834
835 /* 128-bit buffers. */
836 case PIPE_FORMAT_R32G32B32A32_SNORM:
837 case PIPE_FORMAT_R32G32B32A32_UNORM:
838 case PIPE_FORMAT_R32G32B32A32_SSCALED:
839 case PIPE_FORMAT_R32G32B32A32_USCALED:
840 case PIPE_FORMAT_R32G32B32A32_SINT:
841 case PIPE_FORMAT_R32G32B32A32_UINT:
842 case PIPE_FORMAT_R32G32B32A32_FLOAT:
843 case PIPE_FORMAT_R32G32B32X32_FLOAT:
844 case PIPE_FORMAT_R32G32B32X32_UINT:
845 case PIPE_FORMAT_R32G32B32X32_SINT:
846 return V_028C70_COLOR_32_32_32_32;
847
848 /* YUV buffers. */
849 case PIPE_FORMAT_UYVY:
850 case PIPE_FORMAT_YUYV:
851 /* 96-bit buffers. */
852 case PIPE_FORMAT_R32G32B32_FLOAT:
853 /* 8-bit buffers. */
854 case PIPE_FORMAT_L4A4_UNORM:
855 case PIPE_FORMAT_R4A4_UNORM:
856 case PIPE_FORMAT_A4R4_UNORM:
857 default:
858 return V_028C70_COLOR_INVALID; /* Unsupported. */
859 }
860 }
861
862 static uint32_t si_translate_colorswap(enum pipe_format format)
863 {
864 switch (format) {
865 /* 8-bit buffers. */
866 case PIPE_FORMAT_L4A4_UNORM:
867 case PIPE_FORMAT_A4R4_UNORM:
868 return V_028C70_SWAP_ALT;
869
870 case PIPE_FORMAT_A8_UNORM:
871 case PIPE_FORMAT_A8_SNORM:
872 case PIPE_FORMAT_A8_UINT:
873 case PIPE_FORMAT_A8_SINT:
874 case PIPE_FORMAT_R4A4_UNORM:
875 return V_028C70_SWAP_ALT_REV;
876 case PIPE_FORMAT_I8_UNORM:
877 case PIPE_FORMAT_I8_SNORM:
878 case PIPE_FORMAT_L8_UNORM:
879 case PIPE_FORMAT_L8_SNORM:
880 case PIPE_FORMAT_I8_UINT:
881 case PIPE_FORMAT_I8_SINT:
882 case PIPE_FORMAT_L8_UINT:
883 case PIPE_FORMAT_L8_SINT:
884 case PIPE_FORMAT_L8_SRGB:
885 case PIPE_FORMAT_R8_UNORM:
886 case PIPE_FORMAT_R8_SNORM:
887 case PIPE_FORMAT_R8_UINT:
888 case PIPE_FORMAT_R8_SINT:
889 return V_028C70_SWAP_STD;
890
891 /* 16-bit buffers. */
892 case PIPE_FORMAT_B5G6R5_UNORM:
893 return V_028C70_SWAP_STD_REV;
894
895 case PIPE_FORMAT_B5G5R5A1_UNORM:
896 case PIPE_FORMAT_B5G5R5X1_UNORM:
897 return V_028C70_SWAP_ALT;
898
899 case PIPE_FORMAT_B4G4R4A4_UNORM:
900 case PIPE_FORMAT_B4G4R4X4_UNORM:
901 return V_028C70_SWAP_ALT;
902
903 case PIPE_FORMAT_Z16_UNORM:
904 return V_028C70_SWAP_STD;
905
906 case PIPE_FORMAT_L8A8_UNORM:
907 case PIPE_FORMAT_L8A8_SNORM:
908 case PIPE_FORMAT_L8A8_UINT:
909 case PIPE_FORMAT_L8A8_SINT:
910 return V_028C70_SWAP_ALT;
911 case PIPE_FORMAT_R8G8_SNORM:
912 case PIPE_FORMAT_R8G8_UNORM:
913 case PIPE_FORMAT_R8G8_UINT:
914 case PIPE_FORMAT_R8G8_SINT:
915 return V_028C70_SWAP_STD;
916
917 case PIPE_FORMAT_I16_UNORM:
918 case PIPE_FORMAT_I16_SNORM:
919 case PIPE_FORMAT_I16_FLOAT:
920 case PIPE_FORMAT_L16_UNORM:
921 case PIPE_FORMAT_L16_SNORM:
922 case PIPE_FORMAT_L16_FLOAT:
923 case PIPE_FORMAT_R16_UNORM:
924 case PIPE_FORMAT_R16_SNORM:
925 case PIPE_FORMAT_R16_UINT:
926 case PIPE_FORMAT_R16_SINT:
927 case PIPE_FORMAT_R16_FLOAT:
928 return V_028C70_SWAP_STD;
929
930 case PIPE_FORMAT_A16_UNORM:
931 case PIPE_FORMAT_A16_SNORM:
932 case PIPE_FORMAT_A16_FLOAT:
933 return V_028C70_SWAP_ALT_REV;
934
935 /* 32-bit buffers. */
936 case PIPE_FORMAT_A8B8G8R8_SRGB:
937 return V_028C70_SWAP_STD_REV;
938 case PIPE_FORMAT_B8G8R8A8_SRGB:
939 return V_028C70_SWAP_ALT;
940
941 case PIPE_FORMAT_B8G8R8A8_UNORM:
942 case PIPE_FORMAT_B8G8R8X8_UNORM:
943 return V_028C70_SWAP_ALT;
944
945 case PIPE_FORMAT_A8R8G8B8_UNORM:
946 case PIPE_FORMAT_X8R8G8B8_UNORM:
947 return V_028C70_SWAP_ALT_REV;
948 case PIPE_FORMAT_R8G8B8A8_SNORM:
949 case PIPE_FORMAT_R8G8B8A8_UNORM:
950 case PIPE_FORMAT_R8G8B8A8_SSCALED:
951 case PIPE_FORMAT_R8G8B8A8_USCALED:
952 case PIPE_FORMAT_R8G8B8A8_SINT:
953 case PIPE_FORMAT_R8G8B8A8_UINT:
954 case PIPE_FORMAT_R8G8B8X8_UNORM:
955 case PIPE_FORMAT_R8G8B8X8_SNORM:
956 case PIPE_FORMAT_R8G8B8X8_SRGB:
957 case PIPE_FORMAT_R8G8B8X8_UINT:
958 case PIPE_FORMAT_R8G8B8X8_SINT:
959 return V_028C70_SWAP_STD;
960
961 case PIPE_FORMAT_A8B8G8R8_UNORM:
962 case PIPE_FORMAT_X8B8G8R8_UNORM:
963 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
964 return V_028C70_SWAP_STD_REV;
965
966 case PIPE_FORMAT_Z24X8_UNORM:
967 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
968 return V_028C70_SWAP_STD;
969
970 case PIPE_FORMAT_X8Z24_UNORM:
971 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
972 return V_028C70_SWAP_STD;
973
974 case PIPE_FORMAT_R10G10B10A2_UNORM:
975 case PIPE_FORMAT_R10G10B10X2_SNORM:
976 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
977 return V_028C70_SWAP_STD;
978
979 case PIPE_FORMAT_B10G10R10A2_UNORM:
980 case PIPE_FORMAT_B10G10R10A2_UINT:
981 case PIPE_FORMAT_B10G10R10X2_UNORM:
982 return V_028C70_SWAP_ALT;
983
984 case PIPE_FORMAT_R11G11B10_FLOAT:
985 case PIPE_FORMAT_I32_FLOAT:
986 case PIPE_FORMAT_L32_FLOAT:
987 case PIPE_FORMAT_R32_FLOAT:
988 case PIPE_FORMAT_R32_UINT:
989 case PIPE_FORMAT_R32_SINT:
990 case PIPE_FORMAT_Z32_FLOAT:
991 case PIPE_FORMAT_R16G16_FLOAT:
992 case PIPE_FORMAT_R16G16_UNORM:
993 case PIPE_FORMAT_R16G16_SNORM:
994 case PIPE_FORMAT_R16G16_UINT:
995 case PIPE_FORMAT_R16G16_SINT:
996 return V_028C70_SWAP_STD;
997
998 case PIPE_FORMAT_L16A16_UNORM:
999 case PIPE_FORMAT_L16A16_SNORM:
1000 case PIPE_FORMAT_L16A16_FLOAT:
1001 return V_028C70_SWAP_ALT;
1002
1003 case PIPE_FORMAT_A32_FLOAT:
1004 return V_028C70_SWAP_ALT_REV;
1005
1006 /* 64-bit buffers. */
1007 case PIPE_FORMAT_R32G32_FLOAT:
1008 case PIPE_FORMAT_R32G32_UINT:
1009 case PIPE_FORMAT_R32G32_SINT:
1010 case PIPE_FORMAT_R16G16B16A16_UNORM:
1011 case PIPE_FORMAT_R16G16B16A16_SNORM:
1012 case PIPE_FORMAT_R16G16B16A16_USCALED:
1013 case PIPE_FORMAT_R16G16B16A16_SSCALED:
1014 case PIPE_FORMAT_R16G16B16A16_UINT:
1015 case PIPE_FORMAT_R16G16B16A16_SINT:
1016 case PIPE_FORMAT_R16G16B16A16_FLOAT:
1017 case PIPE_FORMAT_R16G16B16X16_UNORM:
1018 case PIPE_FORMAT_R16G16B16X16_SNORM:
1019 case PIPE_FORMAT_R16G16B16X16_FLOAT:
1020 case PIPE_FORMAT_R16G16B16X16_UINT:
1021 case PIPE_FORMAT_R16G16B16X16_SINT:
1022 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1023 return V_028C70_SWAP_STD;
1024
1025 case PIPE_FORMAT_L32A32_FLOAT:
1026 case PIPE_FORMAT_L32A32_UINT:
1027 case PIPE_FORMAT_L32A32_SINT:
1028 return V_028C70_SWAP_ALT;
1029
1030 /* 128-bit buffers. */
1031 case PIPE_FORMAT_R32G32B32A32_FLOAT:
1032 case PIPE_FORMAT_R32G32B32A32_SNORM:
1033 case PIPE_FORMAT_R32G32B32A32_UNORM:
1034 case PIPE_FORMAT_R32G32B32A32_SSCALED:
1035 case PIPE_FORMAT_R32G32B32A32_USCALED:
1036 case PIPE_FORMAT_R32G32B32A32_SINT:
1037 case PIPE_FORMAT_R32G32B32A32_UINT:
1038 case PIPE_FORMAT_R32G32B32X32_FLOAT:
1039 case PIPE_FORMAT_R32G32B32X32_UINT:
1040 case PIPE_FORMAT_R32G32B32X32_SINT:
1041 return V_028C70_SWAP_STD;
1042 default:
1043 R600_ERR("unsupported colorswap format %d\n", format);
1044 return ~0U;
1045 }
1046 return ~0U;
1047 }
1048
1049 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1050 {
1051 if (R600_BIG_ENDIAN) {
1052 switch(colorformat) {
1053 /* 8-bit buffers. */
1054 case V_028C70_COLOR_8:
1055 return V_028C70_ENDIAN_NONE;
1056
1057 /* 16-bit buffers. */
1058 case V_028C70_COLOR_5_6_5:
1059 case V_028C70_COLOR_1_5_5_5:
1060 case V_028C70_COLOR_4_4_4_4:
1061 case V_028C70_COLOR_16:
1062 case V_028C70_COLOR_8_8:
1063 return V_028C70_ENDIAN_8IN16;
1064
1065 /* 32-bit buffers. */
1066 case V_028C70_COLOR_8_8_8_8:
1067 case V_028C70_COLOR_2_10_10_10:
1068 case V_028C70_COLOR_8_24:
1069 case V_028C70_COLOR_24_8:
1070 case V_028C70_COLOR_16_16:
1071 return V_028C70_ENDIAN_8IN32;
1072
1073 /* 64-bit buffers. */
1074 case V_028C70_COLOR_16_16_16_16:
1075 return V_028C70_ENDIAN_8IN16;
1076
1077 case V_028C70_COLOR_32_32:
1078 return V_028C70_ENDIAN_8IN32;
1079
1080 /* 128-bit buffers. */
1081 case V_028C70_COLOR_32_32_32_32:
1082 return V_028C70_ENDIAN_8IN32;
1083 default:
1084 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1085 }
1086 } else {
1087 return V_028C70_ENDIAN_NONE;
1088 }
1089 }
1090
1091 /* Returns the size in bits of the widest component of a CB format */
1092 static unsigned si_colorformat_max_comp_size(uint32_t colorformat)
1093 {
1094 switch(colorformat) {
1095 case V_028C70_COLOR_4_4_4_4:
1096 return 4;
1097
1098 case V_028C70_COLOR_1_5_5_5:
1099 case V_028C70_COLOR_5_5_5_1:
1100 return 5;
1101
1102 case V_028C70_COLOR_5_6_5:
1103 return 6;
1104
1105 case V_028C70_COLOR_8:
1106 case V_028C70_COLOR_8_8:
1107 case V_028C70_COLOR_8_8_8_8:
1108 return 8;
1109
1110 case V_028C70_COLOR_10_10_10_2:
1111 case V_028C70_COLOR_2_10_10_10:
1112 return 10;
1113
1114 case V_028C70_COLOR_10_11_11:
1115 case V_028C70_COLOR_11_11_10:
1116 return 11;
1117
1118 case V_028C70_COLOR_16:
1119 case V_028C70_COLOR_16_16:
1120 case V_028C70_COLOR_16_16_16_16:
1121 return 16;
1122
1123 case V_028C70_COLOR_8_24:
1124 case V_028C70_COLOR_24_8:
1125 return 24;
1126
1127 case V_028C70_COLOR_32:
1128 case V_028C70_COLOR_32_32:
1129 case V_028C70_COLOR_32_32_32_32:
1130 case V_028C70_COLOR_X24_8_32_FLOAT:
1131 return 32;
1132 }
1133
1134 assert(!"Unknown maximum component size");
1135 return 0;
1136 }
1137
1138 static uint32_t si_translate_dbformat(enum pipe_format format)
1139 {
1140 switch (format) {
1141 case PIPE_FORMAT_Z16_UNORM:
1142 return V_028040_Z_16;
1143 case PIPE_FORMAT_Z24X8_UNORM:
1144 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1145 return V_028040_Z_24; /* XXX no longer supported on SI */
1146 case PIPE_FORMAT_Z32_FLOAT:
1147 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1148 return V_028040_Z_32_FLOAT;
1149 default:
1150 return V_028040_Z_INVALID;
1151 }
1152 }
1153
1154 /*
1155 * Texture translation
1156 */
1157
1158 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1159 enum pipe_format format,
1160 const struct util_format_description *desc,
1161 int first_non_void)
1162 {
1163 boolean uniform = TRUE;
1164 int i;
1165
1166 /* Colorspace (return non-RGB formats directly). */
1167 switch (desc->colorspace) {
1168 /* Depth stencil formats */
1169 case UTIL_FORMAT_COLORSPACE_ZS:
1170 switch (format) {
1171 case PIPE_FORMAT_Z16_UNORM:
1172 return V_008F14_IMG_DATA_FORMAT_16;
1173 case PIPE_FORMAT_X24S8_UINT:
1174 case PIPE_FORMAT_Z24X8_UNORM:
1175 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1176 return V_008F14_IMG_DATA_FORMAT_8_24;
1177 case PIPE_FORMAT_X8Z24_UNORM:
1178 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1179 return V_008F14_IMG_DATA_FORMAT_24_8;
1180 case PIPE_FORMAT_X32_S8X24_UINT:
1181 case PIPE_FORMAT_S8X24_UINT:
1182 case PIPE_FORMAT_S8_UINT:
1183 return V_008F14_IMG_DATA_FORMAT_8;
1184 case PIPE_FORMAT_Z32_FLOAT:
1185 return V_008F14_IMG_DATA_FORMAT_32;
1186 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1187 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1188 default:
1189 goto out_unknown;
1190 }
1191
1192 case UTIL_FORMAT_COLORSPACE_YUV:
1193 goto out_unknown; /* TODO */
1194
1195 case UTIL_FORMAT_COLORSPACE_SRGB:
1196 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1197 goto out_unknown;
1198 break;
1199
1200 default:
1201 break;
1202 }
1203
1204 /* TODO compressed formats */
1205
1206 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1207 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1208 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1209 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1210 }
1211
1212 /* R8G8Bx_SNORM - TODO CxV8U8 */
1213
1214 /* See whether the components are of the same size. */
1215 for (i = 1; i < desc->nr_channels; i++) {
1216 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1217 }
1218
1219 /* Non-uniform formats. */
1220 if (!uniform) {
1221 switch(desc->nr_channels) {
1222 case 3:
1223 if (desc->channel[0].size == 5 &&
1224 desc->channel[1].size == 6 &&
1225 desc->channel[2].size == 5) {
1226 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1227 }
1228 goto out_unknown;
1229 case 4:
1230 if (desc->channel[0].size == 5 &&
1231 desc->channel[1].size == 5 &&
1232 desc->channel[2].size == 5 &&
1233 desc->channel[3].size == 1) {
1234 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1235 }
1236 if (desc->channel[0].size == 10 &&
1237 desc->channel[1].size == 10 &&
1238 desc->channel[2].size == 10 &&
1239 desc->channel[3].size == 2) {
1240 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1241 }
1242 goto out_unknown;
1243 }
1244 goto out_unknown;
1245 }
1246
1247 if (first_non_void < 0 || first_non_void > 3)
1248 goto out_unknown;
1249
1250 /* uniform formats */
1251 switch (desc->channel[first_non_void].size) {
1252 case 4:
1253 switch (desc->nr_channels) {
1254 #if 0 /* Not supported for render targets */
1255 case 2:
1256 return V_008F14_IMG_DATA_FORMAT_4_4;
1257 #endif
1258 case 4:
1259 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1260 }
1261 break;
1262 case 8:
1263 switch (desc->nr_channels) {
1264 case 1:
1265 return V_008F14_IMG_DATA_FORMAT_8;
1266 case 2:
1267 return V_008F14_IMG_DATA_FORMAT_8_8;
1268 case 4:
1269 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1270 }
1271 break;
1272 case 16:
1273 switch (desc->nr_channels) {
1274 case 1:
1275 return V_008F14_IMG_DATA_FORMAT_16;
1276 case 2:
1277 return V_008F14_IMG_DATA_FORMAT_16_16;
1278 case 4:
1279 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1280 }
1281 break;
1282 case 32:
1283 switch (desc->nr_channels) {
1284 case 1:
1285 return V_008F14_IMG_DATA_FORMAT_32;
1286 case 2:
1287 return V_008F14_IMG_DATA_FORMAT_32_32;
1288 #if 0 /* Not supported for render targets */
1289 case 3:
1290 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1291 #endif
1292 case 4:
1293 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1294 }
1295 }
1296
1297 out_unknown:
1298 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1299 return ~0;
1300 }
1301
1302 static unsigned si_tex_wrap(unsigned wrap)
1303 {
1304 switch (wrap) {
1305 default:
1306 case PIPE_TEX_WRAP_REPEAT:
1307 return V_008F30_SQ_TEX_WRAP;
1308 case PIPE_TEX_WRAP_CLAMP:
1309 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1310 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1311 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1312 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1313 return V_008F30_SQ_TEX_CLAMP_BORDER;
1314 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1315 return V_008F30_SQ_TEX_MIRROR;
1316 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1317 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1318 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1319 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1320 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1321 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1322 }
1323 }
1324
1325 static unsigned si_tex_filter(unsigned filter)
1326 {
1327 switch (filter) {
1328 default:
1329 case PIPE_TEX_FILTER_NEAREST:
1330 return V_008F38_SQ_TEX_XY_FILTER_POINT;
1331 case PIPE_TEX_FILTER_LINEAR:
1332 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
1333 }
1334 }
1335
1336 static unsigned si_tex_mipfilter(unsigned filter)
1337 {
1338 switch (filter) {
1339 case PIPE_TEX_MIPFILTER_NEAREST:
1340 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1341 case PIPE_TEX_MIPFILTER_LINEAR:
1342 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1343 default:
1344 case PIPE_TEX_MIPFILTER_NONE:
1345 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1346 }
1347 }
1348
1349 static unsigned si_tex_compare(unsigned compare)
1350 {
1351 switch (compare) {
1352 default:
1353 case PIPE_FUNC_NEVER:
1354 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1355 case PIPE_FUNC_LESS:
1356 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1357 case PIPE_FUNC_EQUAL:
1358 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1359 case PIPE_FUNC_LEQUAL:
1360 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1361 case PIPE_FUNC_GREATER:
1362 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1363 case PIPE_FUNC_NOTEQUAL:
1364 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1365 case PIPE_FUNC_GEQUAL:
1366 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1367 case PIPE_FUNC_ALWAYS:
1368 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1369 }
1370 }
1371
1372 static unsigned si_tex_dim(unsigned dim)
1373 {
1374 switch (dim) {
1375 default:
1376 case PIPE_TEXTURE_1D:
1377 return V_008F1C_SQ_RSRC_IMG_1D;
1378 case PIPE_TEXTURE_1D_ARRAY:
1379 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1380 case PIPE_TEXTURE_2D:
1381 case PIPE_TEXTURE_RECT:
1382 return V_008F1C_SQ_RSRC_IMG_2D;
1383 case PIPE_TEXTURE_2D_ARRAY:
1384 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1385 case PIPE_TEXTURE_3D:
1386 return V_008F1C_SQ_RSRC_IMG_3D;
1387 case PIPE_TEXTURE_CUBE:
1388 return V_008F1C_SQ_RSRC_IMG_CUBE;
1389 }
1390 }
1391
1392 /*
1393 * Format support testing
1394 */
1395
1396 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1397 {
1398 return si_translate_texformat(screen, format, util_format_description(format),
1399 util_format_get_first_non_void_channel(format)) != ~0U;
1400 }
1401
1402 static uint32_t si_translate_vertexformat(struct pipe_screen *screen,
1403 enum pipe_format format,
1404 const struct util_format_description *desc,
1405 int first_non_void)
1406 {
1407 unsigned type = desc->channel[first_non_void].type;
1408 int i;
1409
1410 if (type == UTIL_FORMAT_TYPE_FIXED)
1411 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1412
1413 /* See whether the components are of the same size. */
1414 for (i = 0; i < desc->nr_channels; i++) {
1415 if (desc->channel[first_non_void].size != desc->channel[i].size)
1416 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1417 }
1418
1419 switch (desc->channel[first_non_void].size) {
1420 case 8:
1421 switch (desc->nr_channels) {
1422 case 1:
1423 return V_008F0C_BUF_DATA_FORMAT_8;
1424 case 2:
1425 return V_008F0C_BUF_DATA_FORMAT_8_8;
1426 case 3:
1427 case 4:
1428 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1429 }
1430 break;
1431 case 16:
1432 switch (desc->nr_channels) {
1433 case 1:
1434 return V_008F0C_BUF_DATA_FORMAT_16;
1435 case 2:
1436 return V_008F0C_BUF_DATA_FORMAT_16_16;
1437 case 3:
1438 case 4:
1439 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1440 }
1441 break;
1442 case 32:
1443 if (type != UTIL_FORMAT_TYPE_FLOAT)
1444 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1445
1446 switch (desc->nr_channels) {
1447 case 1:
1448 return V_008F0C_BUF_DATA_FORMAT_32;
1449 case 2:
1450 return V_008F0C_BUF_DATA_FORMAT_32_32;
1451 case 3:
1452 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1453 case 4:
1454 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1455 }
1456 break;
1457 }
1458
1459 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1460 }
1461
1462 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
1463 {
1464 const struct util_format_description *desc;
1465 int first_non_void;
1466 unsigned data_format;
1467
1468 desc = util_format_description(format);
1469 first_non_void = util_format_get_first_non_void_channel(format);
1470 data_format = si_translate_vertexformat(screen, format, desc, first_non_void);
1471 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
1472 }
1473
1474 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1475 {
1476 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1477 si_translate_colorswap(format) != ~0U;
1478 }
1479
1480 static bool si_is_zs_format_supported(enum pipe_format format)
1481 {
1482 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1483 }
1484
1485 boolean si_is_format_supported(struct pipe_screen *screen,
1486 enum pipe_format format,
1487 enum pipe_texture_target target,
1488 unsigned sample_count,
1489 unsigned usage)
1490 {
1491 unsigned retval = 0;
1492
1493 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1494 R600_ERR("r600: unsupported texture type %d\n", target);
1495 return FALSE;
1496 }
1497
1498 if (!util_format_is_supported(format, usage))
1499 return FALSE;
1500
1501 /* Multisample */
1502 if (sample_count > 1)
1503 return FALSE;
1504
1505 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
1506 si_is_sampler_format_supported(screen, format)) {
1507 retval |= PIPE_BIND_SAMPLER_VIEW;
1508 }
1509
1510 if ((usage & (PIPE_BIND_RENDER_TARGET |
1511 PIPE_BIND_DISPLAY_TARGET |
1512 PIPE_BIND_SCANOUT |
1513 PIPE_BIND_SHARED)) &&
1514 si_is_colorbuffer_format_supported(format)) {
1515 retval |= usage &
1516 (PIPE_BIND_RENDER_TARGET |
1517 PIPE_BIND_DISPLAY_TARGET |
1518 PIPE_BIND_SCANOUT |
1519 PIPE_BIND_SHARED);
1520 }
1521
1522 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1523 si_is_zs_format_supported(format)) {
1524 retval |= PIPE_BIND_DEPTH_STENCIL;
1525 }
1526
1527 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
1528 si_is_vertex_format_supported(screen, format)) {
1529 retval |= PIPE_BIND_VERTEX_BUFFER;
1530 }
1531
1532 if (usage & PIPE_BIND_TRANSFER_READ)
1533 retval |= PIPE_BIND_TRANSFER_READ;
1534 if (usage & PIPE_BIND_TRANSFER_WRITE)
1535 retval |= PIPE_BIND_TRANSFER_WRITE;
1536
1537 return retval == usage;
1538 }
1539
1540 static unsigned si_tile_mode_index(struct r600_resource_texture *rtex, unsigned level)
1541 {
1542 if (util_format_is_depth_or_stencil(rtex->real_format)) {
1543 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_1D) {
1544 return 4;
1545 } else if (rtex->surface.level[level].mode == RADEON_SURF_MODE_2D) {
1546 switch (rtex->real_format) {
1547 case PIPE_FORMAT_Z16_UNORM:
1548 return 5;
1549 case PIPE_FORMAT_Z24X8_UNORM:
1550 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1551 case PIPE_FORMAT_Z32_FLOAT:
1552 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1553 return 6;
1554 default:
1555 return 7;
1556 }
1557 }
1558 }
1559
1560 switch (rtex->surface.level[level].mode) {
1561 default:
1562 assert(!"Invalid surface mode");
1563 /* Fall through */
1564 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1565 return 8;
1566 case RADEON_SURF_MODE_1D:
1567 if (rtex->surface.flags & RADEON_SURF_SCANOUT)
1568 return 9;
1569 else
1570 return 13;
1571 case RADEON_SURF_MODE_2D:
1572 if (rtex->surface.flags & RADEON_SURF_SCANOUT) {
1573 switch (util_format_get_blocksize(rtex->real_format)) {
1574 case 1:
1575 return 10;
1576 case 2:
1577 return 11;
1578 default:
1579 assert(!"Invalid block size");
1580 /* Fall through */
1581 case 4:
1582 return 12;
1583 }
1584 } else {
1585 switch (util_format_get_blocksize(rtex->real_format)) {
1586 case 1:
1587 return 14;
1588 case 2:
1589 return 15;
1590 case 4:
1591 return 16;
1592 case 8:
1593 return 17;
1594 default:
1595 return 13;
1596 }
1597 }
1598 }
1599 }
1600
1601 /*
1602 * framebuffer handling
1603 */
1604
1605 static void si_cb(struct r600_context *rctx, struct si_pm4_state *pm4,
1606 const struct pipe_framebuffer_state *state, int cb)
1607 {
1608 struct r600_resource_texture *rtex;
1609 struct r600_surface *surf;
1610 unsigned level = state->cbufs[cb]->u.tex.level;
1611 unsigned pitch, slice;
1612 unsigned color_info;
1613 unsigned tile_mode_index;
1614 unsigned format, swap, ntype, endian;
1615 uint64_t offset;
1616 const struct util_format_description *desc;
1617 int i;
1618 unsigned blend_clamp = 0, blend_bypass = 0;
1619 unsigned max_comp_size;
1620
1621 surf = (struct r600_surface *)state->cbufs[cb];
1622 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
1623
1624 offset = rtex->surface.level[level].offset;
1625 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1626 offset += rtex->surface.level[level].slice_size *
1627 state->cbufs[cb]->u.tex.first_layer;
1628 }
1629 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1630 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1631 if (slice) {
1632 slice = slice - 1;
1633 }
1634
1635 tile_mode_index = si_tile_mode_index(rtex, level);
1636
1637 desc = util_format_description(surf->base.format);
1638 for (i = 0; i < 4; i++) {
1639 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1640 break;
1641 }
1642 }
1643 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1644 ntype = V_028C70_NUMBER_FLOAT;
1645 } else {
1646 ntype = V_028C70_NUMBER_UNORM;
1647 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1648 ntype = V_028C70_NUMBER_SRGB;
1649 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1650 if (desc->channel[i].pure_integer) {
1651 ntype = V_028C70_NUMBER_SINT;
1652 } else {
1653 assert(desc->channel[i].normalized);
1654 ntype = V_028C70_NUMBER_SNORM;
1655 }
1656 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1657 if (desc->channel[i].pure_integer) {
1658 ntype = V_028C70_NUMBER_UINT;
1659 } else {
1660 assert(desc->channel[i].normalized);
1661 ntype = V_028C70_NUMBER_UNORM;
1662 }
1663 }
1664 }
1665
1666 format = si_translate_colorformat(surf->base.format);
1667 if (format == V_028C70_COLOR_INVALID) {
1668 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
1669 }
1670 assert(format != V_028C70_COLOR_INVALID);
1671 swap = si_translate_colorswap(surf->base.format);
1672 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1673 endian = V_028C70_ENDIAN_NONE;
1674 } else {
1675 endian = si_colorformat_endian_swap(format);
1676 }
1677
1678 /* blend clamp should be set for all NORM/SRGB types */
1679 if (ntype == V_028C70_NUMBER_UNORM ||
1680 ntype == V_028C70_NUMBER_SNORM ||
1681 ntype == V_028C70_NUMBER_SRGB)
1682 blend_clamp = 1;
1683
1684 /* set blend bypass according to docs if SINT/UINT or
1685 8/24 COLOR variants */
1686 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1687 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1688 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1689 blend_clamp = 0;
1690 blend_bypass = 1;
1691 }
1692
1693 color_info = S_028C70_FORMAT(format) |
1694 S_028C70_COMP_SWAP(swap) |
1695 S_028C70_BLEND_CLAMP(blend_clamp) |
1696 S_028C70_BLEND_BYPASS(blend_bypass) |
1697 S_028C70_NUMBER_TYPE(ntype) |
1698 S_028C70_ENDIAN(endian);
1699
1700 offset += r600_resource_va(rctx->context.screen, state->cbufs[cb]->texture);
1701 offset >>= 8;
1702
1703 /* FIXME handle enabling of CB beyond BASE8 which has different offset */
1704 si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE);
1705 si_pm4_set_reg(pm4, R_028C60_CB_COLOR0_BASE + cb * 0x3C, offset);
1706 si_pm4_set_reg(pm4, R_028C64_CB_COLOR0_PITCH + cb * 0x3C, S_028C64_TILE_MAX(pitch));
1707 si_pm4_set_reg(pm4, R_028C68_CB_COLOR0_SLICE + cb * 0x3C, S_028C68_TILE_MAX(slice));
1708
1709 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1710 si_pm4_set_reg(pm4, R_028C6C_CB_COLOR0_VIEW + cb * 0x3C, 0x00000000);
1711 } else {
1712 si_pm4_set_reg(pm4, R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1713 S_028C6C_SLICE_START(state->cbufs[cb]->u.tex.first_layer) |
1714 S_028C6C_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer));
1715 }
1716 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + cb * 0x3C, color_info);
1717 si_pm4_set_reg(pm4, R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C,
1718 S_028C74_TILE_MODE_INDEX(tile_mode_index));
1719
1720 /* Determine pixel shader export format */
1721 max_comp_size = si_colorformat_max_comp_size(format);
1722 if (ntype == V_028C70_NUMBER_SRGB ||
1723 ((ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM) &&
1724 max_comp_size <= 10) ||
1725 (ntype == V_028C70_NUMBER_FLOAT && max_comp_size <= 16)) {
1726 rctx->export_16bpc |= 1 << cb;
1727 }
1728 }
1729
1730 static void si_db(struct r600_context *rctx, struct si_pm4_state *pm4,
1731 const struct pipe_framebuffer_state *state)
1732 {
1733 struct r600_resource_texture *rtex;
1734 struct r600_surface *surf;
1735 unsigned level, pitch, slice, format, tile_mode_index;
1736 uint32_t z_info, s_info;
1737 uint64_t z_offs, s_offs;
1738
1739 if (state->zsbuf == NULL) {
1740 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, S_028040_FORMAT(V_028040_Z_INVALID));
1741 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, S_028044_FORMAT(V_028044_STENCIL_INVALID));
1742 return;
1743 }
1744
1745 surf = (struct r600_surface *)state->zsbuf;
1746 level = surf->base.u.tex.level;
1747 rtex = (struct r600_resource_texture*)surf->base.texture;
1748
1749 format = si_translate_dbformat(rtex->real_format);
1750
1751 if (format == V_028040_Z_INVALID) {
1752 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->real_format);
1753 }
1754 assert(format != V_028040_Z_INVALID);
1755
1756 s_offs = z_offs = r600_resource_va(rctx->context.screen, surf->base.texture);
1757 z_offs += rtex->surface.level[level].offset;
1758 s_offs += rtex->surface.stencil_level[level].offset;
1759
1760 z_offs >>= 8;
1761 s_offs >>= 8;
1762
1763 pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
1764 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1765 if (slice) {
1766 slice = slice - 1;
1767 }
1768
1769 z_info = S_028040_FORMAT(format);
1770 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
1771 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
1772 else
1773 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
1774
1775 tile_mode_index = si_tile_mode_index(rtex, level);
1776 if (tile_mode_index < 4 || tile_mode_index > 7) {
1777 R600_ERR("Invalid DB tiling mode %d!\n",
1778 rtex->surface.level[level].mode);
1779 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, S_028040_FORMAT(V_028040_Z_INVALID));
1780 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, S_028044_FORMAT(V_028044_STENCIL_INVALID));
1781 return;
1782 }
1783 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
1784 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
1785
1786 si_pm4_set_reg(pm4, R_028008_DB_DEPTH_VIEW,
1787 S_028008_SLICE_START(state->zsbuf->u.tex.first_layer) |
1788 S_028008_SLICE_MAX(state->zsbuf->u.tex.last_layer));
1789
1790 si_pm4_set_reg(pm4, R_02803C_DB_DEPTH_INFO, S_02803C_ADDR5_SWIZZLE_MASK(1));
1791 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, z_info);
1792 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, s_info);
1793
1794 si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE);
1795 si_pm4_set_reg(pm4, R_028048_DB_Z_READ_BASE, z_offs);
1796 si_pm4_set_reg(pm4, R_02804C_DB_STENCIL_READ_BASE, s_offs);
1797 si_pm4_set_reg(pm4, R_028050_DB_Z_WRITE_BASE, z_offs);
1798 si_pm4_set_reg(pm4, R_028054_DB_STENCIL_WRITE_BASE, s_offs);
1799
1800 si_pm4_set_reg(pm4, R_028058_DB_DEPTH_SIZE, S_028058_PITCH_TILE_MAX(pitch));
1801 si_pm4_set_reg(pm4, R_02805C_DB_DEPTH_SLICE, S_02805C_SLICE_TILE_MAX(slice));
1802 }
1803
1804 static void si_set_framebuffer_state(struct pipe_context *ctx,
1805 const struct pipe_framebuffer_state *state)
1806 {
1807 struct r600_context *rctx = (struct r600_context *)ctx;
1808 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
1809 uint32_t shader_mask, tl, br;
1810 int tl_x, tl_y, br_x, br_y;
1811
1812 if (pm4 == NULL)
1813 return;
1814
1815 si_pm4_inval_fb_cache(pm4, state->nr_cbufs);
1816
1817 if (state->zsbuf)
1818 si_pm4_inval_zsbuf_cache(pm4);
1819
1820 util_copy_framebuffer_state(&rctx->framebuffer, state);
1821
1822 /* build states */
1823 rctx->export_16bpc = 0;
1824 for (int i = 0; i < state->nr_cbufs; i++) {
1825 si_cb(rctx, pm4, state, i);
1826 }
1827 assert(!(rctx->export_16bpc & ~0xff));
1828 si_db(rctx, pm4, state);
1829
1830 shader_mask = 0;
1831 for (int i = 0; i < state->nr_cbufs; i++) {
1832 shader_mask |= 0xf << (i * 4);
1833 }
1834 tl_x = 0;
1835 tl_y = 0;
1836 br_x = state->width;
1837 br_y = state->height;
1838
1839 tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
1840 br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
1841
1842 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, tl);
1843 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR, br);
1844 si_pm4_set_reg(pm4, R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl);
1845 si_pm4_set_reg(pm4, R_028254_PA_SC_VPORT_SCISSOR_0_BR, br);
1846 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, tl);
1847 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR, br);
1848 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, tl);
1849 si_pm4_set_reg(pm4, R_028208_PA_SC_WINDOW_SCISSOR_BR, br);
1850 si_pm4_set_reg(pm4, R_028200_PA_SC_WINDOW_OFFSET, 0x00000000);
1851 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
1852 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, shader_mask);
1853 si_pm4_set_reg(pm4, R_028BE0_PA_SC_AA_CONFIG, 0x00000000);
1854
1855 si_pm4_set_state(rctx, framebuffer, pm4);
1856 si_update_fb_rs_state(rctx);
1857 si_update_fb_blend_state(rctx);
1858 }
1859
1860 /*
1861 * shaders
1862 */
1863
1864 /* Compute the key for the hw shader variant */
1865 static INLINE struct si_shader_key si_shader_selector_key(struct pipe_context *ctx,
1866 struct si_pipe_shader_selector *sel)
1867 {
1868 struct r600_context *rctx = (struct r600_context *)ctx;
1869 struct si_shader_key key;
1870 memset(&key, 0, sizeof(key));
1871
1872 if (sel->type == PIPE_SHADER_FRAGMENT) {
1873 if (sel->fs_write_all)
1874 key.nr_cbufs = rctx->framebuffer.nr_cbufs;
1875 key.export_16bpc = rctx->export_16bpc;
1876 if (rctx->queued.named.rasterizer) {
1877 key.color_two_side = rctx->queued.named.rasterizer->two_side;
1878 /*key.flatshade = rctx->queued.named.rasterizer->flatshade;*/
1879 }
1880 if (rctx->queued.named.dsa) {
1881 key.alpha_func = rctx->queued.named.dsa->alpha_func;
1882 key.alpha_ref = rctx->queued.named.dsa->alpha_ref;
1883 } else {
1884 key.alpha_func = PIPE_FUNC_ALWAYS;
1885 }
1886 }
1887
1888 return key;
1889 }
1890
1891 /* Select the hw shader variant depending on the current state.
1892 * (*dirty) is set to 1 if current variant was changed */
1893 int si_shader_select(struct pipe_context *ctx,
1894 struct si_pipe_shader_selector *sel,
1895 unsigned *dirty)
1896 {
1897 struct si_shader_key key;
1898 struct si_pipe_shader * shader = NULL;
1899 int r;
1900
1901 key = si_shader_selector_key(ctx, sel);
1902
1903 /* Check if we don't need to change anything.
1904 * This path is also used for most shaders that don't need multiple
1905 * variants, it will cost just a computation of the key and this
1906 * test. */
1907 if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
1908 return 0;
1909 }
1910
1911 /* lookup if we have other variants in the list */
1912 if (sel->num_shaders > 1) {
1913 struct si_pipe_shader *p = sel->current, *c = p->next_variant;
1914
1915 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
1916 p = c;
1917 c = c->next_variant;
1918 }
1919
1920 if (c) {
1921 p->next_variant = c->next_variant;
1922 shader = c;
1923 }
1924 }
1925
1926 if (unlikely(!shader)) {
1927 shader = CALLOC(1, sizeof(struct si_pipe_shader));
1928 shader->selector = sel;
1929
1930 r = si_pipe_shader_create(ctx, shader, key);
1931 if (unlikely(r)) {
1932 R600_ERR("Failed to build shader variant (type=%u) %d\n",
1933 sel->type, r);
1934 sel->current = NULL;
1935 return r;
1936 }
1937
1938 /* We don't know the value of fs_write_all property until we built
1939 * at least one variant, so we may need to recompute the key (include
1940 * rctx->framebuffer.nr_cbufs) after building first variant. */
1941 if (sel->type == PIPE_SHADER_FRAGMENT &&
1942 sel->num_shaders == 0 &&
1943 shader->shader.fs_write_all) {
1944 sel->fs_write_all = 1;
1945 key = si_shader_selector_key(ctx, sel);
1946 }
1947
1948 shader->key = key;
1949 sel->num_shaders++;
1950 }
1951
1952 if (dirty)
1953 *dirty = 1;
1954
1955 shader->next_variant = sel->current;
1956 sel->current = shader;
1957
1958 return 0;
1959 }
1960
1961 static void *si_create_shader_state(struct pipe_context *ctx,
1962 const struct pipe_shader_state *state,
1963 unsigned pipe_shader_type)
1964 {
1965 struct si_pipe_shader_selector *sel = CALLOC_STRUCT(si_pipe_shader_selector);
1966 int r;
1967
1968 sel->type = pipe_shader_type;
1969 sel->tokens = tgsi_dup_tokens(state->tokens);
1970 sel->so = state->stream_output;
1971
1972 r = si_shader_select(ctx, sel, NULL);
1973 if (r) {
1974 free(sel);
1975 return NULL;
1976 }
1977
1978 return sel;
1979 }
1980
1981 static void *si_create_fs_state(struct pipe_context *ctx,
1982 const struct pipe_shader_state *state)
1983 {
1984 return si_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
1985 }
1986
1987 static void *si_create_vs_state(struct pipe_context *ctx,
1988 const struct pipe_shader_state *state)
1989 {
1990 return si_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
1991 }
1992
1993 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
1994 {
1995 struct r600_context *rctx = (struct r600_context *)ctx;
1996 struct si_pipe_shader_selector *sel = state;
1997
1998 if (rctx->vs_shader == sel)
1999 return;
2000
2001 rctx->vs_shader = sel;
2002
2003 if (sel && sel->current)
2004 si_pm4_bind_state(rctx, vs, sel->current->pm4);
2005 else
2006 si_pm4_bind_state(rctx, vs, rctx->dummy_pixel_shader->pm4);
2007 }
2008
2009 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
2010 {
2011 struct r600_context *rctx = (struct r600_context *)ctx;
2012 struct si_pipe_shader_selector *sel = state;
2013
2014 if (rctx->ps_shader == sel)
2015 return;
2016
2017 rctx->ps_shader = sel;
2018
2019 if (sel && sel->current)
2020 si_pm4_bind_state(rctx, ps, sel->current->pm4);
2021 else
2022 si_pm4_bind_state(rctx, ps, rctx->dummy_pixel_shader->pm4);
2023 }
2024
2025 static void si_delete_shader_selector(struct pipe_context *ctx,
2026 struct si_pipe_shader_selector *sel)
2027 {
2028 struct r600_context *rctx = (struct r600_context *)ctx;
2029 struct si_pipe_shader *p = sel->current, *c;
2030
2031 while (p) {
2032 c = p->next_variant;
2033 si_pm4_delete_state(rctx, vs, p->pm4);
2034 si_pipe_shader_destroy(ctx, p);
2035 free(p);
2036 p = c;
2037 }
2038
2039 free(sel->tokens);
2040 free(sel);
2041 }
2042
2043 static void si_delete_vs_shader(struct pipe_context *ctx, void *state)
2044 {
2045 struct r600_context *rctx = (struct r600_context *)ctx;
2046 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state;
2047
2048 if (rctx->vs_shader == sel) {
2049 rctx->vs_shader = NULL;
2050 }
2051
2052 si_delete_shader_selector(ctx, sel);
2053 }
2054
2055 static void si_delete_ps_shader(struct pipe_context *ctx, void *state)
2056 {
2057 struct r600_context *rctx = (struct r600_context *)ctx;
2058 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state;
2059
2060 if (rctx->ps_shader == sel) {
2061 rctx->ps_shader = NULL;
2062 }
2063
2064 si_delete_shader_selector(ctx, sel);
2065 }
2066
2067 /*
2068 * Samplers
2069 */
2070
2071 static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx,
2072 struct pipe_resource *texture,
2073 const struct pipe_sampler_view *state)
2074 {
2075 struct si_pipe_sampler_view *view = CALLOC_STRUCT(si_pipe_sampler_view);
2076 struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
2077 const struct util_format_description *desc;
2078 unsigned format, num_format;
2079 uint32_t pitch = 0;
2080 unsigned char state_swizzle[4], swizzle[4];
2081 unsigned height, depth, width;
2082 enum pipe_format pipe_format = state->format;
2083 int first_non_void;
2084 uint64_t va;
2085
2086 if (view == NULL)
2087 return NULL;
2088
2089 /* initialize base object */
2090 view->base = *state;
2091 view->base.texture = NULL;
2092 pipe_reference(NULL, &texture->reference);
2093 view->base.texture = texture;
2094 view->base.reference.count = 1;
2095 view->base.context = ctx;
2096
2097 state_swizzle[0] = state->swizzle_r;
2098 state_swizzle[1] = state->swizzle_g;
2099 state_swizzle[2] = state->swizzle_b;
2100 state_swizzle[3] = state->swizzle_a;
2101
2102 /* Texturing with separate depth and stencil. */
2103 if (tmp->is_depth && !tmp->is_flushing_texture) {
2104 switch (pipe_format) {
2105 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2106 pipe_format = PIPE_FORMAT_Z32_FLOAT;
2107 break;
2108 case PIPE_FORMAT_X24S8_UINT:
2109 case PIPE_FORMAT_S8X24_UINT:
2110 case PIPE_FORMAT_X32_S8X24_UINT:
2111 pipe_format = PIPE_FORMAT_S8_UINT;
2112 break;
2113 default:;
2114 }
2115 }
2116
2117 desc = util_format_description(pipe_format);
2118 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2119
2120 first_non_void = util_format_get_first_non_void_channel(pipe_format);
2121 if (first_non_void < 0) {
2122 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2123 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
2124 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2125 } else {
2126 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2127
2128 switch (desc->channel[first_non_void].type) {
2129 case UTIL_FORMAT_TYPE_FLOAT:
2130 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2131 break;
2132 case UTIL_FORMAT_TYPE_SIGNED:
2133 if (desc->channel[first_non_void].normalized)
2134 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2135 else if (desc->channel[first_non_void].pure_integer)
2136 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
2137 else
2138 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
2139 break;
2140 case UTIL_FORMAT_TYPE_UNSIGNED:
2141 if (desc->channel[first_non_void].normalized)
2142 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2143 else if (desc->channel[first_non_void].pure_integer)
2144 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
2145 else
2146 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
2147 }
2148 }
2149
2150 format = si_translate_texformat(ctx->screen, pipe_format, desc, first_non_void);
2151 if (format == ~0) {
2152 format = 0;
2153 }
2154
2155 view->resource = &tmp->resource;
2156
2157 /* not supported any more */
2158 //endian = si_colorformat_endian_swap(format);
2159
2160 width = tmp->surface.level[0].npix_x;
2161 height = tmp->surface.level[0].npix_y;
2162 depth = tmp->surface.level[0].npix_z;
2163 pitch = tmp->surface.level[0].nblk_x * util_format_get_blockwidth(pipe_format);
2164
2165 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
2166 height = 1;
2167 depth = texture->array_size;
2168 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
2169 depth = texture->array_size;
2170 }
2171
2172 va = r600_resource_va(ctx->screen, texture);
2173 va += tmp->surface.level[0].offset;
2174 view->state[0] = va >> 8;
2175 view->state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) |
2176 S_008F14_DATA_FORMAT(format) |
2177 S_008F14_NUM_FORMAT(num_format));
2178 view->state[2] = (S_008F18_WIDTH(width - 1) |
2179 S_008F18_HEIGHT(height - 1));
2180 view->state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2181 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2182 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2183 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2184 S_008F1C_BASE_LEVEL(state->u.tex.first_level) |
2185 S_008F1C_LAST_LEVEL(state->u.tex.last_level) |
2186 S_008F1C_TILING_INDEX(si_tile_mode_index(tmp, 0)) |
2187 S_008F1C_POW2_PAD(texture->last_level > 0) |
2188 S_008F1C_TYPE(si_tex_dim(texture->target)));
2189 view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
2190 view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2191 S_008F24_LAST_ARRAY(state->u.tex.last_layer));
2192 view->state[6] = 0;
2193 view->state[7] = 0;
2194
2195 return &view->base;
2196 }
2197
2198 static void si_sampler_view_destroy(struct pipe_context *ctx,
2199 struct pipe_sampler_view *state)
2200 {
2201 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
2202
2203 pipe_resource_reference(&state->texture, NULL);
2204 FREE(resource);
2205 }
2206
2207 static void *si_create_sampler_state(struct pipe_context *ctx,
2208 const struct pipe_sampler_state *state)
2209 {
2210 struct si_pipe_sampler_state *rstate = CALLOC_STRUCT(si_pipe_sampler_state);
2211 union util_color uc;
2212 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
2213 unsigned border_color_type;
2214
2215 if (rstate == NULL) {
2216 return NULL;
2217 }
2218
2219 util_pack_color(state->border_color.f, PIPE_FORMAT_A8R8G8B8_UNORM, &uc);
2220 switch (uc.ui) {
2221 case 0x000000FF:
2222 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
2223 break;
2224 case 0x00000000:
2225 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
2226 break;
2227 case 0xFFFFFFFF:
2228 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
2229 break;
2230 default: /* Use border color pointer */
2231 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
2232 }
2233
2234 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
2235 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
2236 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
2237 (state->max_anisotropy & 0x7) << 9 | /* XXX */
2238 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
2239 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
2240 aniso_flag_offset << 16 | /* XXX */
2241 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map));
2242 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
2243 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
2244 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
2245 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter)) |
2246 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter)) |
2247 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)));
2248 rstate->val[3] = S_008F3C_BORDER_COLOR_TYPE(border_color_type);
2249
2250 if (border_color_type == V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2251 memcpy(rstate->border_color, state->border_color.f,
2252 sizeof(rstate->border_color));
2253 }
2254
2255 return rstate;
2256 }
2257
2258 static struct si_pm4_state *si_set_sampler_view(struct r600_context *rctx,
2259 unsigned count,
2260 struct pipe_sampler_view **views,
2261 struct r600_textures_info *samplers,
2262 unsigned user_data_reg)
2263 {
2264 struct si_pipe_sampler_view **resource = (struct si_pipe_sampler_view **)views;
2265 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
2266 int i, j;
2267
2268 if (!count)
2269 goto out;
2270
2271 si_pm4_inval_texture_cache(pm4);
2272
2273 si_pm4_sh_data_begin(pm4);
2274 for (i = 0; i < count; i++) {
2275 pipe_sampler_view_reference(
2276 (struct pipe_sampler_view **)&samplers->views[i],
2277 views[i]);
2278
2279 if (views[i]) {
2280 struct r600_resource_texture *rtex =
2281 (struct r600_resource_texture*)views[i]->texture;
2282
2283 if (rtex->is_depth && !rtex->is_flushing_texture) {
2284 samplers->depth_texture_mask |= 1 << i;
2285 } else {
2286 samplers->depth_texture_mask &= ~(1 << i);
2287 }
2288
2289 si_pm4_add_bo(pm4, resource[i]->resource, RADEON_USAGE_READ);
2290 } else {
2291 samplers->depth_texture_mask &= ~(1 << i);
2292 }
2293
2294 for (j = 0; j < Elements(resource[i]->state); ++j) {
2295 si_pm4_sh_data_add(pm4, resource[i] ? resource[i]->state[j] : 0);
2296 }
2297 }
2298
2299 for (i = count; i < NUM_TEX_UNITS; i++) {
2300 if (samplers->views[i])
2301 pipe_sampler_view_reference((struct pipe_sampler_view **)&samplers->views[i], NULL);
2302 }
2303
2304 si_pm4_sh_data_end(pm4, user_data_reg, SI_SGPR_RESOURCE);
2305
2306 out:
2307 rctx->ps_samplers.n_views = count;
2308 return pm4;
2309 }
2310
2311 static void si_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
2312 struct pipe_sampler_view **views)
2313 {
2314 struct r600_context *rctx = (struct r600_context *)ctx;
2315 struct si_pm4_state *pm4;
2316
2317 pm4 = si_set_sampler_view(rctx, count, views, &rctx->vs_samplers,
2318 R_00B130_SPI_SHADER_USER_DATA_VS_0);
2319 si_pm4_set_state(rctx, vs_sampler_views, pm4);
2320 }
2321
2322 static void si_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
2323 struct pipe_sampler_view **views)
2324 {
2325 struct r600_context *rctx = (struct r600_context *)ctx;
2326 struct si_pm4_state *pm4;
2327
2328 pm4 = si_set_sampler_view(rctx, count, views, &rctx->ps_samplers,
2329 R_00B030_SPI_SHADER_USER_DATA_PS_0);
2330 si_pm4_set_state(rctx, ps_sampler_views, pm4);
2331 }
2332
2333 static struct si_pm4_state *si_bind_sampler(struct r600_context *rctx, unsigned count,
2334 void **states,
2335 struct r600_textures_info *samplers,
2336 unsigned user_data_reg)
2337 {
2338 struct si_pipe_sampler_state **rstates = (struct si_pipe_sampler_state **)states;
2339 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
2340 uint32_t *border_color_table = NULL;
2341 int i, j;
2342
2343 if (!count)
2344 goto out;
2345
2346 si_pm4_inval_texture_cache(pm4);
2347
2348 si_pm4_sh_data_begin(pm4);
2349 for (i = 0; i < count; i++) {
2350 if (rstates[i] &&
2351 G_008F3C_BORDER_COLOR_TYPE(rstates[i]->val[3]) ==
2352 V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2353 if (!rctx->border_color_table ||
2354 ((rctx->border_color_offset + count - i) &
2355 C_008F3C_BORDER_COLOR_PTR)) {
2356 si_resource_reference(&rctx->border_color_table, NULL);
2357 rctx->border_color_offset = 0;
2358
2359 rctx->border_color_table =
2360 si_resource_create_custom(&rctx->screen->screen,
2361 PIPE_USAGE_STAGING,
2362 4096 * 4 * 4);
2363 }
2364
2365 if (!border_color_table) {
2366 border_color_table =
2367 rctx->ws->buffer_map(rctx->border_color_table->cs_buf,
2368 rctx->cs,
2369 PIPE_TRANSFER_WRITE |
2370 PIPE_TRANSFER_UNSYNCHRONIZED);
2371 }
2372
2373 for (j = 0; j < 4; j++) {
2374 union fi border_color;
2375
2376 border_color.f = rstates[i]->border_color[j];
2377 border_color_table[4 * rctx->border_color_offset + j] =
2378 util_le32_to_cpu(border_color.i);
2379 }
2380
2381 rstates[i]->val[3] &= C_008F3C_BORDER_COLOR_PTR;
2382 rstates[i]->val[3] |= S_008F3C_BORDER_COLOR_PTR(rctx->border_color_offset++);
2383 }
2384
2385 for (j = 0; j < Elements(rstates[i]->val); ++j) {
2386 si_pm4_sh_data_add(pm4, rstates[i] ? rstates[i]->val[j] : 0);
2387 }
2388 }
2389 si_pm4_sh_data_end(pm4, user_data_reg, SI_SGPR_SAMPLER);
2390
2391 if (border_color_table) {
2392 uint64_t va_offset =
2393 r600_resource_va(&rctx->screen->screen,
2394 (void*)rctx->border_color_table);
2395
2396 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, va_offset >> 8);
2397 rctx->ws->buffer_unmap(rctx->border_color_table->cs_buf);
2398 si_pm4_add_bo(pm4, rctx->border_color_table, RADEON_USAGE_READ);
2399 }
2400
2401 memcpy(samplers->samplers, states, sizeof(void*) * count);
2402
2403 out:
2404 samplers->n_samplers = count;
2405 return pm4;
2406 }
2407
2408 static void si_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
2409 {
2410 struct r600_context *rctx = (struct r600_context *)ctx;
2411 struct si_pm4_state *pm4;
2412
2413 pm4 = si_bind_sampler(rctx, count, states, &rctx->vs_samplers,
2414 R_00B130_SPI_SHADER_USER_DATA_VS_0);
2415 si_pm4_set_state(rctx, vs_sampler, pm4);
2416 }
2417
2418 static void si_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
2419 {
2420 struct r600_context *rctx = (struct r600_context *)ctx;
2421 struct si_pm4_state *pm4;
2422
2423 pm4 = si_bind_sampler(rctx, count, states, &rctx->ps_samplers,
2424 R_00B030_SPI_SHADER_USER_DATA_PS_0);
2425 si_pm4_set_state(rctx, ps_sampler, pm4);
2426 }
2427
2428 static void si_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
2429 {
2430 }
2431
2432 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
2433 {
2434 free(state);
2435 }
2436
2437 /*
2438 * Constants
2439 */
2440 static void si_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
2441 struct pipe_constant_buffer *cb)
2442 {
2443 struct r600_context *rctx = (struct r600_context *)ctx;
2444 struct si_resource *rbuffer = cb ? si_resource(cb->buffer) : NULL;
2445 struct si_pm4_state *pm4;
2446 uint64_t va_offset;
2447 uint32_t reg, offset;
2448
2449 /* Note that the state tracker can unbind constant buffers by
2450 * passing NULL here.
2451 */
2452 if (cb == NULL)
2453 return;
2454
2455 pm4 = CALLOC_STRUCT(si_pm4_state);
2456 si_pm4_inval_shader_cache(pm4);
2457
2458 if (cb->user_buffer)
2459 r600_upload_const_buffer(rctx, &rbuffer, cb->user_buffer, cb->buffer_size, &offset);
2460 else
2461 offset = 0;
2462 va_offset = r600_resource_va(ctx->screen, (void*)rbuffer);
2463 va_offset += offset;
2464
2465 si_pm4_add_bo(pm4, rbuffer, RADEON_USAGE_READ);
2466
2467 switch (shader) {
2468 case PIPE_SHADER_VERTEX:
2469 reg = R_00B130_SPI_SHADER_USER_DATA_VS_0 + SI_SGPR_CONST * 4;
2470 si_pm4_set_reg(pm4, reg, va_offset);
2471 si_pm4_set_reg(pm4, reg + 4, va_offset >> 32);
2472 si_pm4_set_state(rctx, vs_const, pm4);
2473 break;
2474
2475 case PIPE_SHADER_FRAGMENT:
2476 reg = R_00B030_SPI_SHADER_USER_DATA_PS_0 + SI_SGPR_CONST * 4;
2477 si_pm4_set_reg(pm4, reg, va_offset);
2478 si_pm4_set_reg(pm4, reg + 4, va_offset >> 32);
2479 si_pm4_set_state(rctx, ps_const, pm4);
2480 break;
2481
2482 default:
2483 R600_ERR("unsupported %d\n", shader);
2484 }
2485
2486 if (cb->buffer != &rbuffer->b.b)
2487 si_resource_reference(&rbuffer, NULL);
2488 }
2489
2490 /*
2491 * Vertex elements & buffers
2492 */
2493
2494 static void *si_create_vertex_elements(struct pipe_context *ctx,
2495 unsigned count,
2496 const struct pipe_vertex_element *elements)
2497 {
2498 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
2499 int i;
2500
2501 assert(count < PIPE_MAX_ATTRIBS);
2502 if (!v)
2503 return NULL;
2504
2505 v->count = count;
2506 for (i = 0; i < count; ++i) {
2507 const struct util_format_description *desc;
2508 unsigned data_format, num_format;
2509 int first_non_void;
2510
2511 desc = util_format_description(elements[i].src_format);
2512 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
2513 data_format = si_translate_vertexformat(ctx->screen, elements[i].src_format,
2514 desc, first_non_void);
2515
2516 switch (desc->channel[first_non_void].type) {
2517 case UTIL_FORMAT_TYPE_FIXED:
2518 num_format = V_008F0C_BUF_NUM_FORMAT_USCALED; /* XXX */
2519 break;
2520 case UTIL_FORMAT_TYPE_SIGNED:
2521 if (desc->channel[first_non_void].normalized)
2522 num_format = V_008F0C_BUF_NUM_FORMAT_SNORM;
2523 else if (desc->channel[first_non_void].pure_integer)
2524 num_format = V_008F0C_BUF_NUM_FORMAT_SINT;
2525 else
2526 num_format = V_008F0C_BUF_NUM_FORMAT_SSCALED;
2527 break;
2528 case UTIL_FORMAT_TYPE_UNSIGNED:
2529 if (desc->channel[first_non_void].normalized)
2530 num_format = V_008F0C_BUF_NUM_FORMAT_UNORM;
2531 else if (desc->channel[first_non_void].pure_integer)
2532 num_format = V_008F0C_BUF_NUM_FORMAT_UINT;
2533 else
2534 num_format = V_008F0C_BUF_NUM_FORMAT_USCALED;
2535 break;
2536 case UTIL_FORMAT_TYPE_FLOAT:
2537 default:
2538 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2539 }
2540
2541 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2542 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2543 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2544 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2545 S_008F0C_NUM_FORMAT(num_format) |
2546 S_008F0C_DATA_FORMAT(data_format);
2547 }
2548 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
2549
2550 return v;
2551 }
2552
2553 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
2554 {
2555 struct r600_context *rctx = (struct r600_context *)ctx;
2556 struct si_vertex_element *v = (struct si_vertex_element*)state;
2557
2558 rctx->vertex_elements = v;
2559 }
2560
2561 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
2562 {
2563 struct r600_context *rctx = (struct r600_context *)ctx;
2564
2565 if (rctx->vertex_elements == state)
2566 rctx->vertex_elements = NULL;
2567 FREE(state);
2568 }
2569
2570 static void si_set_vertex_buffers(struct pipe_context *ctx, unsigned start_slot, unsigned count,
2571 const struct pipe_vertex_buffer *buffers)
2572 {
2573 struct r600_context *rctx = (struct r600_context *)ctx;
2574
2575 util_set_vertex_buffers_count(rctx->vertex_buffer, &rctx->nr_vertex_buffers, buffers, start_slot, count);
2576 }
2577
2578 static void si_set_index_buffer(struct pipe_context *ctx,
2579 const struct pipe_index_buffer *ib)
2580 {
2581 struct r600_context *rctx = (struct r600_context *)ctx;
2582
2583 if (ib) {
2584 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
2585 memcpy(&rctx->index_buffer, ib, sizeof(*ib));
2586 } else {
2587 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
2588 }
2589 }
2590
2591 /*
2592 * Misc
2593 */
2594 static void si_set_polygon_stipple(struct pipe_context *ctx,
2595 const struct pipe_poly_stipple *state)
2596 {
2597 }
2598
2599 static void si_texture_barrier(struct pipe_context *ctx)
2600 {
2601 struct r600_context *rctx = (struct r600_context *)ctx;
2602 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
2603
2604 si_pm4_inval_texture_cache(pm4);
2605 si_pm4_inval_fb_cache(pm4, rctx->framebuffer.nr_cbufs);
2606 si_pm4_set_state(rctx, texture_barrier, pm4);
2607 }
2608
2609 void si_init_state_functions(struct r600_context *rctx)
2610 {
2611 rctx->context.create_blend_state = si_create_blend_state;
2612 rctx->context.bind_blend_state = si_bind_blend_state;
2613 rctx->context.delete_blend_state = si_delete_blend_state;
2614 rctx->context.set_blend_color = si_set_blend_color;
2615
2616 rctx->context.create_rasterizer_state = si_create_rs_state;
2617 rctx->context.bind_rasterizer_state = si_bind_rs_state;
2618 rctx->context.delete_rasterizer_state = si_delete_rs_state;
2619
2620 rctx->context.create_depth_stencil_alpha_state = si_create_dsa_state;
2621 rctx->context.bind_depth_stencil_alpha_state = si_bind_dsa_state;
2622 rctx->context.delete_depth_stencil_alpha_state = si_delete_dsa_state;
2623 rctx->custom_dsa_flush_depth_stencil = si_create_db_flush_dsa(rctx, true, true);
2624 rctx->custom_dsa_flush_depth = si_create_db_flush_dsa(rctx, true, false);
2625 rctx->custom_dsa_flush_stencil = si_create_db_flush_dsa(rctx, false, true);
2626 rctx->custom_dsa_flush_inplace = si_create_db_flush_dsa(rctx, false, false);
2627
2628 rctx->context.set_clip_state = si_set_clip_state;
2629 rctx->context.set_scissor_state = si_set_scissor_state;
2630 rctx->context.set_viewport_state = si_set_viewport_state;
2631 rctx->context.set_stencil_ref = si_set_pipe_stencil_ref;
2632
2633 rctx->context.set_framebuffer_state = si_set_framebuffer_state;
2634
2635 rctx->context.create_vs_state = si_create_vs_state;
2636 rctx->context.create_fs_state = si_create_fs_state;
2637 rctx->context.bind_vs_state = si_bind_vs_shader;
2638 rctx->context.bind_fs_state = si_bind_ps_shader;
2639 rctx->context.delete_vs_state = si_delete_vs_shader;
2640 rctx->context.delete_fs_state = si_delete_ps_shader;
2641
2642 rctx->context.create_sampler_state = si_create_sampler_state;
2643 rctx->context.bind_vertex_sampler_states = si_bind_vs_sampler;
2644 rctx->context.bind_fragment_sampler_states = si_bind_ps_sampler;
2645 rctx->context.delete_sampler_state = si_delete_sampler_state;
2646
2647 rctx->context.create_sampler_view = si_create_sampler_view;
2648 rctx->context.set_vertex_sampler_views = si_set_vs_sampler_view;
2649 rctx->context.set_fragment_sampler_views = si_set_ps_sampler_view;
2650 rctx->context.sampler_view_destroy = si_sampler_view_destroy;
2651
2652 rctx->context.set_sample_mask = si_set_sample_mask;
2653
2654 rctx->context.set_constant_buffer = si_set_constant_buffer;
2655
2656 rctx->context.create_vertex_elements_state = si_create_vertex_elements;
2657 rctx->context.bind_vertex_elements_state = si_bind_vertex_elements;
2658 rctx->context.delete_vertex_elements_state = si_delete_vertex_element;
2659 rctx->context.set_vertex_buffers = si_set_vertex_buffers;
2660 rctx->context.set_index_buffer = si_set_index_buffer;
2661
2662 rctx->context.create_stream_output_target = si_create_so_target;
2663 rctx->context.stream_output_target_destroy = si_so_target_destroy;
2664 rctx->context.set_stream_output_targets = si_set_so_targets;
2665
2666 rctx->context.texture_barrier = si_texture_barrier;
2667 rctx->context.set_polygon_stipple = si_set_polygon_stipple;
2668
2669 rctx->context.draw_vbo = si_draw_vbo;
2670 }
2671
2672 void si_init_config(struct r600_context *rctx)
2673 {
2674 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
2675
2676 si_cmd_context_control(pm4);
2677
2678 si_pm4_set_reg(pm4, R_028A4C_PA_SC_MODE_CNTL_1, 0x0);
2679
2680 si_pm4_set_reg(pm4, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0);
2681 si_pm4_set_reg(pm4, R_028A14_VGT_HOS_CNTL, 0x0);
2682 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0);
2683 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0);
2684 si_pm4_set_reg(pm4, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0);
2685 si_pm4_set_reg(pm4, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0);
2686 si_pm4_set_reg(pm4, R_028A28_VGT_GROUP_FIRST_DECR, 0x0);
2687 si_pm4_set_reg(pm4, R_028A2C_VGT_GROUP_DECR, 0x0);
2688 si_pm4_set_reg(pm4, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0);
2689 si_pm4_set_reg(pm4, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0);
2690 si_pm4_set_reg(pm4, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0);
2691 si_pm4_set_reg(pm4, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0);
2692 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, 0x0);
2693 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0x0);
2694 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
2695 si_pm4_set_reg(pm4, R_028B94_VGT_STRMOUT_CONFIG, 0x0);
2696 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
2697 si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM,
2698 S_028AA8_SWITCH_ON_EOP(1) |
2699 S_028AA8_PARTIAL_VS_WAVE_ON(1) |
2700 S_028AA8_PRIMGROUP_SIZE(63));
2701 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0x00000000);
2702 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
2703 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
2704 S_008A14_CLIP_VTX_REORDER_ENA(1));
2705
2706 si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, 0);
2707 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
2708 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
2709
2710 si_pm4_set_reg(pm4, R_028804_DB_EQAA, 0x110000);
2711
2712 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
2713
2714 switch (rctx->screen->family) {
2715 case CHIP_TAHITI:
2716 case CHIP_PITCAIRN:
2717 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x2a00126a);
2718 break;
2719 case CHIP_VERDE:
2720 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x0000124a);
2721 break;
2722 case CHIP_OLAND:
2723 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000082);
2724 break;
2725 default:
2726 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
2727 break;
2728 }
2729
2730 si_pm4_set_state(rctx, init, pm4);
2731 }