2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Christian König <christian.koenig@amd.com>
30 #include "radeon/r600_cs.h"
31 #include "radeon/r600_query.h"
33 #include "util/u_dual_blend.h"
34 #include "util/u_format.h"
35 #include "util/u_format_s3tc.h"
36 #include "util/u_memory.h"
37 #include "util/u_resource.h"
38 #include "util/u_upload_mgr.h"
40 /* Initialize an external atom (owned by ../radeon). */
42 si_init_external_atom(struct si_context
*sctx
, struct r600_atom
*atom
,
43 struct r600_atom
**list_elem
)
45 atom
->id
= list_elem
- sctx
->atoms
.array
;
49 /* Initialize an atom owned by radeonsi. */
50 void si_init_atom(struct si_context
*sctx
, struct r600_atom
*atom
,
51 struct r600_atom
**list_elem
,
52 void (*emit_func
)(struct si_context
*ctx
, struct r600_atom
*state
))
54 atom
->emit
= (void*)emit_func
;
55 atom
->id
= list_elem
- sctx
->atoms
.array
;
59 static unsigned si_map_swizzle(unsigned swizzle
)
63 return V_008F0C_SQ_SEL_Y
;
65 return V_008F0C_SQ_SEL_Z
;
67 return V_008F0C_SQ_SEL_W
;
69 return V_008F0C_SQ_SEL_0
;
71 return V_008F0C_SQ_SEL_1
;
72 default: /* PIPE_SWIZZLE_X */
73 return V_008F0C_SQ_SEL_X
;
77 static uint32_t S_FIXED(float value
, uint32_t frac_bits
)
79 return value
* (1 << frac_bits
);
82 /* 12.4 fixed-point */
83 static unsigned si_pack_float_12p4(float x
)
86 x
>= 4096 ? 0xffff : x
* 16;
90 * Inferred framebuffer and blender state.
92 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
93 * if there is not enough PS outputs.
95 static void si_emit_cb_render_state(struct si_context
*sctx
, struct r600_atom
*atom
)
97 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
98 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
99 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
100 * but you never know. */
101 uint32_t cb_target_mask
= sctx
->framebuffer
.colorbuf_enabled_4bit
;
105 cb_target_mask
&= blend
->cb_target_mask
;
107 /* Avoid a hang that happens when dual source blending is enabled
108 * but there is not enough color outputs. This is undefined behavior,
109 * so disable color writes completely.
111 * Reproducible with Unigine Heaven 4.0 and drirc missing.
113 if (blend
&& blend
->dual_src_blend
&&
114 sctx
->ps_shader
.cso
&&
115 (sctx
->ps_shader
.cso
->info
.colors_written
& 0x3) != 0x3)
118 radeon_set_context_reg(cs
, R_028238_CB_TARGET_MASK
, cb_target_mask
);
120 /* RB+ register settings. */
121 if (sctx
->screen
->b
.rbplus_allowed
) {
122 unsigned spi_shader_col_format
=
123 sctx
->ps_shader
.cso
?
124 sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.spi_shader_col_format
: 0;
125 unsigned sx_ps_downconvert
= 0;
126 unsigned sx_blend_opt_epsilon
= 0;
127 unsigned sx_blend_opt_control
= 0;
129 for (i
= 0; i
< sctx
->framebuffer
.state
.nr_cbufs
; i
++) {
130 struct r600_surface
*surf
=
131 (struct r600_surface
*)sctx
->framebuffer
.state
.cbufs
[i
];
132 unsigned format
, swap
, spi_format
, colormask
;
133 bool has_alpha
, has_rgb
;
138 format
= G_028C70_FORMAT(surf
->cb_color_info
);
139 swap
= G_028C70_COMP_SWAP(surf
->cb_color_info
);
140 spi_format
= (spi_shader_col_format
>> (i
* 4)) & 0xf;
141 colormask
= (cb_target_mask
>> (i
* 4)) & 0xf;
143 /* Set if RGB and A are present. */
144 has_alpha
= !G_028C74_FORCE_DST_ALPHA_1(surf
->cb_color_attrib
);
146 if (format
== V_028C70_COLOR_8
||
147 format
== V_028C70_COLOR_16
||
148 format
== V_028C70_COLOR_32
)
149 has_rgb
= !has_alpha
;
153 /* Check the colormask and export format. */
154 if (!(colormask
& (PIPE_MASK_RGBA
& ~PIPE_MASK_A
)))
156 if (!(colormask
& PIPE_MASK_A
))
159 if (spi_format
== V_028714_SPI_SHADER_ZERO
) {
164 /* Disable value checking for disabled channels. */
166 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
168 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
170 /* Enable down-conversion for 32bpp and smaller formats. */
172 case V_028C70_COLOR_8
:
173 case V_028C70_COLOR_8_8
:
174 case V_028C70_COLOR_8_8_8_8
:
175 /* For 1 and 2-channel formats, use the superset thereof. */
176 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
||
177 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
178 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
179 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_8_8_8_8
<< (i
* 4);
180 sx_blend_opt_epsilon
|= V_028758_8BIT_FORMAT
<< (i
* 4);
184 case V_028C70_COLOR_5_6_5
:
185 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
186 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_5_6_5
<< (i
* 4);
187 sx_blend_opt_epsilon
|= V_028758_6BIT_FORMAT
<< (i
* 4);
191 case V_028C70_COLOR_1_5_5_5
:
192 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
193 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_1_5_5_5
<< (i
* 4);
194 sx_blend_opt_epsilon
|= V_028758_5BIT_FORMAT
<< (i
* 4);
198 case V_028C70_COLOR_4_4_4_4
:
199 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
200 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_4_4_4_4
<< (i
* 4);
201 sx_blend_opt_epsilon
|= V_028758_4BIT_FORMAT
<< (i
* 4);
205 case V_028C70_COLOR_32
:
206 if (swap
== V_0280A0_SWAP_STD
&&
207 spi_format
== V_028714_SPI_SHADER_32_R
)
208 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_R
<< (i
* 4);
209 else if (swap
== V_0280A0_SWAP_ALT_REV
&&
210 spi_format
== V_028714_SPI_SHADER_32_AR
)
211 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_A
<< (i
* 4);
214 case V_028C70_COLOR_16
:
215 case V_028C70_COLOR_16_16
:
216 /* For 1-channel formats, use the superset thereof. */
217 if (spi_format
== V_028714_SPI_SHADER_UNORM16_ABGR
||
218 spi_format
== V_028714_SPI_SHADER_SNORM16_ABGR
||
219 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
220 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
221 if (swap
== V_0280A0_SWAP_STD
||
222 swap
== V_0280A0_SWAP_STD_REV
)
223 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_GR
<< (i
* 4);
225 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_AR
<< (i
* 4);
229 case V_028C70_COLOR_10_11_11
:
230 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
231 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_10_11_11
<< (i
* 4);
232 sx_blend_opt_epsilon
|= V_028758_11BIT_FORMAT
<< (i
* 4);
236 case V_028C70_COLOR_2_10_10_10
:
237 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
238 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_2_10_10_10
<< (i
* 4);
239 sx_blend_opt_epsilon
|= V_028758_10BIT_FORMAT
<< (i
* 4);
245 radeon_set_context_reg_seq(cs
, R_028754_SX_PS_DOWNCONVERT
, 3);
246 radeon_emit(cs
, sx_ps_downconvert
); /* R_028754_SX_PS_DOWNCONVERT */
247 radeon_emit(cs
, sx_blend_opt_epsilon
); /* R_028758_SX_BLEND_OPT_EPSILON */
248 radeon_emit(cs
, sx_blend_opt_control
); /* R_02875C_SX_BLEND_OPT_CONTROL */
249 } else if (sctx
->screen
->b
.has_rbplus
) {
250 radeon_set_context_reg_seq(cs
, R_028754_SX_PS_DOWNCONVERT
, 3);
251 radeon_emit(cs
, 0); /* R_028754_SX_PS_DOWNCONVERT */
252 radeon_emit(cs
, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
253 radeon_emit(cs
, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
261 static uint32_t si_translate_blend_function(int blend_func
)
263 switch (blend_func
) {
265 return V_028780_COMB_DST_PLUS_SRC
;
266 case PIPE_BLEND_SUBTRACT
:
267 return V_028780_COMB_SRC_MINUS_DST
;
268 case PIPE_BLEND_REVERSE_SUBTRACT
:
269 return V_028780_COMB_DST_MINUS_SRC
;
271 return V_028780_COMB_MIN_DST_SRC
;
273 return V_028780_COMB_MAX_DST_SRC
;
275 R600_ERR("Unknown blend function %d\n", blend_func
);
282 static uint32_t si_translate_blend_factor(int blend_fact
)
284 switch (blend_fact
) {
285 case PIPE_BLENDFACTOR_ONE
:
286 return V_028780_BLEND_ONE
;
287 case PIPE_BLENDFACTOR_SRC_COLOR
:
288 return V_028780_BLEND_SRC_COLOR
;
289 case PIPE_BLENDFACTOR_SRC_ALPHA
:
290 return V_028780_BLEND_SRC_ALPHA
;
291 case PIPE_BLENDFACTOR_DST_ALPHA
:
292 return V_028780_BLEND_DST_ALPHA
;
293 case PIPE_BLENDFACTOR_DST_COLOR
:
294 return V_028780_BLEND_DST_COLOR
;
295 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
296 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
297 case PIPE_BLENDFACTOR_CONST_COLOR
:
298 return V_028780_BLEND_CONSTANT_COLOR
;
299 case PIPE_BLENDFACTOR_CONST_ALPHA
:
300 return V_028780_BLEND_CONSTANT_ALPHA
;
301 case PIPE_BLENDFACTOR_ZERO
:
302 return V_028780_BLEND_ZERO
;
303 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
304 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
305 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
306 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
307 case PIPE_BLENDFACTOR_INV_DST_ALPHA
:
308 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
309 case PIPE_BLENDFACTOR_INV_DST_COLOR
:
310 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
311 case PIPE_BLENDFACTOR_INV_CONST_COLOR
:
312 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR
;
313 case PIPE_BLENDFACTOR_INV_CONST_ALPHA
:
314 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA
;
315 case PIPE_BLENDFACTOR_SRC1_COLOR
:
316 return V_028780_BLEND_SRC1_COLOR
;
317 case PIPE_BLENDFACTOR_SRC1_ALPHA
:
318 return V_028780_BLEND_SRC1_ALPHA
;
319 case PIPE_BLENDFACTOR_INV_SRC1_COLOR
:
320 return V_028780_BLEND_INV_SRC1_COLOR
;
321 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA
:
322 return V_028780_BLEND_INV_SRC1_ALPHA
;
324 R600_ERR("Bad blend factor %d not supported!\n", blend_fact
);
331 static uint32_t si_translate_blend_opt_function(int blend_func
)
333 switch (blend_func
) {
335 return V_028760_OPT_COMB_ADD
;
336 case PIPE_BLEND_SUBTRACT
:
337 return V_028760_OPT_COMB_SUBTRACT
;
338 case PIPE_BLEND_REVERSE_SUBTRACT
:
339 return V_028760_OPT_COMB_REVSUBTRACT
;
341 return V_028760_OPT_COMB_MIN
;
343 return V_028760_OPT_COMB_MAX
;
345 return V_028760_OPT_COMB_BLEND_DISABLED
;
349 static uint32_t si_translate_blend_opt_factor(int blend_fact
, bool is_alpha
)
351 switch (blend_fact
) {
352 case PIPE_BLENDFACTOR_ZERO
:
353 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL
;
354 case PIPE_BLENDFACTOR_ONE
:
355 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
;
356 case PIPE_BLENDFACTOR_SRC_COLOR
:
357 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
358 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0
;
359 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
360 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
361 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1
;
362 case PIPE_BLENDFACTOR_SRC_ALPHA
:
363 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
;
364 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
365 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
;
366 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
367 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
368 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
370 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
375 * Get rid of DST in the blend factors by commuting the operands:
376 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
378 static void si_blend_remove_dst(unsigned *func
, unsigned *src_factor
,
379 unsigned *dst_factor
, unsigned expected_dst
,
380 unsigned replacement_src
)
382 if (*src_factor
== expected_dst
&&
383 *dst_factor
== PIPE_BLENDFACTOR_ZERO
) {
384 *src_factor
= PIPE_BLENDFACTOR_ZERO
;
385 *dst_factor
= replacement_src
;
387 /* Commuting the operands requires reversing subtractions. */
388 if (*func
== PIPE_BLEND_SUBTRACT
)
389 *func
= PIPE_BLEND_REVERSE_SUBTRACT
;
390 else if (*func
== PIPE_BLEND_REVERSE_SUBTRACT
)
391 *func
= PIPE_BLEND_SUBTRACT
;
395 static bool si_blend_factor_uses_dst(unsigned factor
)
397 return factor
== PIPE_BLENDFACTOR_DST_COLOR
||
398 factor
== PIPE_BLENDFACTOR_DST_ALPHA
||
399 factor
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
400 factor
== PIPE_BLENDFACTOR_INV_DST_ALPHA
||
401 factor
== PIPE_BLENDFACTOR_INV_DST_COLOR
;
404 static void *si_create_blend_state_mode(struct pipe_context
*ctx
,
405 const struct pipe_blend_state
*state
,
408 struct si_context
*sctx
= (struct si_context
*)ctx
;
409 struct si_state_blend
*blend
= CALLOC_STRUCT(si_state_blend
);
410 struct si_pm4_state
*pm4
= &blend
->pm4
;
411 uint32_t sx_mrt_blend_opt
[8] = {0};
412 uint32_t color_control
= 0;
417 blend
->alpha_to_coverage
= state
->alpha_to_coverage
;
418 blend
->alpha_to_one
= state
->alpha_to_one
;
419 blend
->dual_src_blend
= util_blend_state_is_dual(state
, 0);
421 if (state
->logicop_enable
) {
422 color_control
|= S_028808_ROP3(state
->logicop_func
| (state
->logicop_func
<< 4));
424 color_control
|= S_028808_ROP3(0xcc);
427 si_pm4_set_reg(pm4
, R_028B70_DB_ALPHA_TO_MASK
,
428 S_028B70_ALPHA_TO_MASK_ENABLE(state
->alpha_to_coverage
) |
429 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
430 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
431 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
432 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
434 if (state
->alpha_to_coverage
)
435 blend
->need_src_alpha_4bit
|= 0xf;
437 blend
->cb_target_mask
= 0;
438 for (int i
= 0; i
< 8; i
++) {
439 /* state->rt entries > 0 only written if independent blending */
440 const int j
= state
->independent_blend_enable
? i
: 0;
442 unsigned eqRGB
= state
->rt
[j
].rgb_func
;
443 unsigned srcRGB
= state
->rt
[j
].rgb_src_factor
;
444 unsigned dstRGB
= state
->rt
[j
].rgb_dst_factor
;
445 unsigned eqA
= state
->rt
[j
].alpha_func
;
446 unsigned srcA
= state
->rt
[j
].alpha_src_factor
;
447 unsigned dstA
= state
->rt
[j
].alpha_dst_factor
;
449 unsigned srcRGB_opt
, dstRGB_opt
, srcA_opt
, dstA_opt
;
450 unsigned blend_cntl
= 0;
452 sx_mrt_blend_opt
[i
] =
453 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) |
454 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
456 /* Only set dual source blending for MRT0 to avoid a hang. */
457 if (i
>= 1 && blend
->dual_src_blend
) {
458 /* Vulkan does this for dual source blending. */
460 blend_cntl
|= S_028780_ENABLE(1);
462 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
466 /* Only addition and subtraction equations are supported with
467 * dual source blending.
469 if (blend
->dual_src_blend
&&
470 (eqRGB
== PIPE_BLEND_MIN
|| eqRGB
== PIPE_BLEND_MAX
||
471 eqA
== PIPE_BLEND_MIN
|| eqA
== PIPE_BLEND_MAX
)) {
472 assert(!"Unsupported equation for dual source blending");
473 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
477 /* cb_render_state will disable unused ones */
478 blend
->cb_target_mask
|= (unsigned)state
->rt
[j
].colormask
<< (4 * i
);
480 if (!state
->rt
[j
].colormask
|| !state
->rt
[j
].blend_enable
) {
481 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
485 /* Blending optimizations for RB+.
486 * These transformations don't change the behavior.
488 * First, get rid of DST in the blend factors:
489 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
491 si_blend_remove_dst(&eqRGB
, &srcRGB
, &dstRGB
,
492 PIPE_BLENDFACTOR_DST_COLOR
,
493 PIPE_BLENDFACTOR_SRC_COLOR
);
494 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
495 PIPE_BLENDFACTOR_DST_COLOR
,
496 PIPE_BLENDFACTOR_SRC_COLOR
);
497 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
498 PIPE_BLENDFACTOR_DST_ALPHA
,
499 PIPE_BLENDFACTOR_SRC_ALPHA
);
501 /* Look up the ideal settings from tables. */
502 srcRGB_opt
= si_translate_blend_opt_factor(srcRGB
, false);
503 dstRGB_opt
= si_translate_blend_opt_factor(dstRGB
, false);
504 srcA_opt
= si_translate_blend_opt_factor(srcA
, true);
505 dstA_opt
= si_translate_blend_opt_factor(dstA
, true);
507 /* Handle interdependencies. */
508 if (si_blend_factor_uses_dst(srcRGB
))
509 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
510 if (si_blend_factor_uses_dst(srcA
))
511 dstA_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
513 if (srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
&&
514 (dstRGB
== PIPE_BLENDFACTOR_ZERO
||
515 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
516 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
))
517 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
519 /* Set the final value. */
520 sx_mrt_blend_opt
[i
] =
521 S_028760_COLOR_SRC_OPT(srcRGB_opt
) |
522 S_028760_COLOR_DST_OPT(dstRGB_opt
) |
523 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB
)) |
524 S_028760_ALPHA_SRC_OPT(srcA_opt
) |
525 S_028760_ALPHA_DST_OPT(dstA_opt
) |
526 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA
));
528 /* Set blend state. */
529 blend_cntl
|= S_028780_ENABLE(1);
530 blend_cntl
|= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB
));
531 blend_cntl
|= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB
));
532 blend_cntl
|= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB
));
534 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
535 blend_cntl
|= S_028780_SEPARATE_ALPHA_BLEND(1);
536 blend_cntl
|= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA
));
537 blend_cntl
|= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA
));
538 blend_cntl
|= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA
));
540 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
542 blend
->blend_enable_4bit
|= 0xfu
<< (i
* 4);
544 /* This is only important for formats without alpha. */
545 if (srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
546 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
547 srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
548 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
549 srcRGB
== PIPE_BLENDFACTOR_INV_SRC_ALPHA
||
550 dstRGB
== PIPE_BLENDFACTOR_INV_SRC_ALPHA
)
551 blend
->need_src_alpha_4bit
|= 0xfu
<< (i
* 4);
554 if (blend
->cb_target_mask
) {
555 color_control
|= S_028808_MODE(mode
);
557 color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
560 if (sctx
->screen
->b
.has_rbplus
) {
561 /* Disable RB+ blend optimizations for dual source blending.
564 if (blend
->dual_src_blend
) {
565 for (int i
= 0; i
< 8; i
++) {
566 sx_mrt_blend_opt
[i
] =
567 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE
) |
568 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE
);
572 for (int i
= 0; i
< 8; i
++)
573 si_pm4_set_reg(pm4
, R_028760_SX_MRT0_BLEND_OPT
+ i
* 4,
574 sx_mrt_blend_opt
[i
]);
576 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
577 if (blend
->dual_src_blend
|| state
->logicop_enable
||
578 mode
== V_028808_CB_RESOLVE
)
579 color_control
|= S_028808_DISABLE_DUAL_QUAD(1);
582 si_pm4_set_reg(pm4
, R_028808_CB_COLOR_CONTROL
, color_control
);
586 static void *si_create_blend_state(struct pipe_context
*ctx
,
587 const struct pipe_blend_state
*state
)
589 return si_create_blend_state_mode(ctx
, state
, V_028808_CB_NORMAL
);
592 static void si_bind_blend_state(struct pipe_context
*ctx
, void *state
)
594 struct si_context
*sctx
= (struct si_context
*)ctx
;
595 si_pm4_bind_state(sctx
, blend
, (struct si_state_blend
*)state
);
596 si_mark_atom_dirty(sctx
, &sctx
->cb_render_state
);
597 sctx
->do_update_shaders
= true;
600 static void si_delete_blend_state(struct pipe_context
*ctx
, void *state
)
602 struct si_context
*sctx
= (struct si_context
*)ctx
;
603 si_pm4_delete_state(sctx
, blend
, (struct si_state_blend
*)state
);
606 static void si_set_blend_color(struct pipe_context
*ctx
,
607 const struct pipe_blend_color
*state
)
609 struct si_context
*sctx
= (struct si_context
*)ctx
;
611 if (memcmp(&sctx
->blend_color
.state
, state
, sizeof(*state
)) == 0)
614 sctx
->blend_color
.state
= *state
;
615 si_mark_atom_dirty(sctx
, &sctx
->blend_color
.atom
);
618 static void si_emit_blend_color(struct si_context
*sctx
, struct r600_atom
*atom
)
620 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
622 radeon_set_context_reg_seq(cs
, R_028414_CB_BLEND_RED
, 4);
623 radeon_emit_array(cs
, (uint32_t*)sctx
->blend_color
.state
.color
, 4);
630 static void si_set_clip_state(struct pipe_context
*ctx
,
631 const struct pipe_clip_state
*state
)
633 struct si_context
*sctx
= (struct si_context
*)ctx
;
634 struct pipe_constant_buffer cb
;
636 if (memcmp(&sctx
->clip_state
.state
, state
, sizeof(*state
)) == 0)
639 sctx
->clip_state
.state
= *state
;
640 si_mark_atom_dirty(sctx
, &sctx
->clip_state
.atom
);
643 cb
.user_buffer
= state
->ucp
;
644 cb
.buffer_offset
= 0;
645 cb
.buffer_size
= 4*4*8;
646 si_set_rw_buffer(sctx
, SI_VS_CONST_CLIP_PLANES
, &cb
);
647 pipe_resource_reference(&cb
.buffer
, NULL
);
650 static void si_emit_clip_state(struct si_context
*sctx
, struct r600_atom
*atom
)
652 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
654 radeon_set_context_reg_seq(cs
, R_0285BC_PA_CL_UCP_0_X
, 6*4);
655 radeon_emit_array(cs
, (uint32_t*)sctx
->clip_state
.state
.ucp
, 6*4);
658 #define SIX_BITS 0x3F
660 static void si_emit_clip_regs(struct si_context
*sctx
, struct r600_atom
*atom
)
662 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
663 struct si_shader
*vs
= si_get_vs_state(sctx
);
664 struct tgsi_shader_info
*info
= si_get_vs_info(sctx
);
665 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
666 unsigned window_space
=
667 info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
668 unsigned clipdist_mask
=
669 info
->writes_clipvertex
? SIX_BITS
: info
->clipdist_writemask
;
670 unsigned ucp_mask
= clipdist_mask
? 0 : rs
->clip_plane_enable
& SIX_BITS
;
671 unsigned culldist_mask
= info
->culldist_writemask
<< info
->num_written_clipdistance
;
675 if (vs
->key
.opt
.hw_vs
.clip_disable
) {
676 assert(!info
->culldist_writemask
);
680 total_mask
= clipdist_mask
| culldist_mask
;
682 /* Clip distances on points have no effect, so need to be implemented
683 * as cull distances. This applies for the clipvertex case as well.
685 * Setting this for primitives other than points should have no adverse
688 clipdist_mask
&= rs
->clip_plane_enable
;
689 culldist_mask
|= clipdist_mask
;
691 misc_vec_ena
= info
->writes_psize
|| info
->writes_edgeflag
||
692 info
->writes_layer
|| info
->writes_viewport_index
;
694 radeon_set_context_reg(cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
695 S_02881C_USE_VTX_POINT_SIZE(info
->writes_psize
) |
696 S_02881C_USE_VTX_EDGE_FLAG(info
->writes_edgeflag
) |
697 S_02881C_USE_VTX_RENDER_TARGET_INDX(info
->writes_layer
) |
698 S_02881C_USE_VTX_VIEWPORT_INDX(info
->writes_viewport_index
) |
699 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0F) != 0) |
700 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xF0) != 0) |
701 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
702 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
) |
703 clipdist_mask
| (culldist_mask
<< 8));
704 radeon_set_context_reg(cs
, R_028810_PA_CL_CLIP_CNTL
,
705 rs
->pa_cl_clip_cntl
|
707 S_028810_CLIP_DISABLE(window_space
));
709 /* reuse needs to be set off if we write oViewport */
710 radeon_set_context_reg(cs
, R_028AB4_VGT_REUSE_OFF
,
711 S_028AB4_REUSE_OFF(info
->writes_viewport_index
));
715 * inferred state between framebuffer and rasterizer
717 static void si_update_poly_offset_state(struct si_context
*sctx
)
719 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
721 if (!rs
|| !rs
->uses_poly_offset
|| !sctx
->framebuffer
.state
.zsbuf
) {
722 si_pm4_bind_state(sctx
, poly_offset
, NULL
);
726 /* Use the user format, not db_render_format, so that the polygon
727 * offset behaves as expected by applications.
729 switch (sctx
->framebuffer
.state
.zsbuf
->texture
->format
) {
730 case PIPE_FORMAT_Z16_UNORM
:
731 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[0]);
733 default: /* 24-bit */
734 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[1]);
736 case PIPE_FORMAT_Z32_FLOAT
:
737 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
738 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[2]);
747 static uint32_t si_translate_fill(uint32_t func
)
750 case PIPE_POLYGON_MODE_FILL
:
751 return V_028814_X_DRAW_TRIANGLES
;
752 case PIPE_POLYGON_MODE_LINE
:
753 return V_028814_X_DRAW_LINES
;
754 case PIPE_POLYGON_MODE_POINT
:
755 return V_028814_X_DRAW_POINTS
;
758 return V_028814_X_DRAW_POINTS
;
762 static void *si_create_rs_state(struct pipe_context
*ctx
,
763 const struct pipe_rasterizer_state
*state
)
765 struct si_screen
*sscreen
= ((struct si_context
*)ctx
)->screen
;
766 struct si_state_rasterizer
*rs
= CALLOC_STRUCT(si_state_rasterizer
);
767 struct si_pm4_state
*pm4
= &rs
->pm4
;
769 float psize_min
, psize_max
;
775 rs
->scissor_enable
= state
->scissor
;
776 rs
->clip_halfz
= state
->clip_halfz
;
777 rs
->two_side
= state
->light_twoside
;
778 rs
->multisample_enable
= state
->multisample
;
779 rs
->force_persample_interp
= state
->force_persample_interp
;
780 rs
->clip_plane_enable
= state
->clip_plane_enable
;
781 rs
->line_stipple_enable
= state
->line_stipple_enable
;
782 rs
->poly_stipple_enable
= state
->poly_stipple_enable
;
783 rs
->line_smooth
= state
->line_smooth
;
784 rs
->poly_smooth
= state
->poly_smooth
;
785 rs
->uses_poly_offset
= state
->offset_point
|| state
->offset_line
||
787 rs
->clamp_fragment_color
= state
->clamp_fragment_color
;
788 rs
->flatshade
= state
->flatshade
;
789 rs
->sprite_coord_enable
= state
->sprite_coord_enable
;
790 rs
->rasterizer_discard
= state
->rasterizer_discard
;
791 rs
->pa_sc_line_stipple
= state
->line_stipple_enable
?
792 S_028A0C_LINE_PATTERN(state
->line_stipple_pattern
) |
793 S_028A0C_REPEAT_COUNT(state
->line_stipple_factor
) : 0;
794 rs
->pa_cl_clip_cntl
=
795 S_028810_DX_CLIP_SPACE_DEF(state
->clip_halfz
) |
796 S_028810_ZCLIP_NEAR_DISABLE(!state
->depth_clip
) |
797 S_028810_ZCLIP_FAR_DISABLE(!state
->depth_clip
) |
798 S_028810_DX_RASTERIZATION_KILL(state
->rasterizer_discard
) |
799 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
801 si_pm4_set_reg(pm4
, R_0286D4_SPI_INTERP_CONTROL_0
,
802 S_0286D4_FLAT_SHADE_ENA(1) |
803 S_0286D4_PNT_SPRITE_ENA(1) |
804 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S
) |
805 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T
) |
806 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0
) |
807 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1
) |
808 S_0286D4_PNT_SPRITE_TOP_1(state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
));
810 /* point size 12.4 fixed point */
811 tmp
= (unsigned)(state
->point_size
* 8.0);
812 si_pm4_set_reg(pm4
, R_028A00_PA_SU_POINT_SIZE
, S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
));
814 if (state
->point_size_per_vertex
) {
815 psize_min
= util_get_min_point_size(state
);
818 /* Force the point size to be as if the vertex output was disabled. */
819 psize_min
= state
->point_size
;
820 psize_max
= state
->point_size
;
822 /* Divide by two, because 0.5 = 1 pixel. */
823 si_pm4_set_reg(pm4
, R_028A04_PA_SU_POINT_MINMAX
,
824 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min
/2)) |
825 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max
/2)));
827 tmp
= (unsigned)state
->line_width
* 8;
828 si_pm4_set_reg(pm4
, R_028A08_PA_SU_LINE_CNTL
, S_028A08_WIDTH(tmp
));
829 si_pm4_set_reg(pm4
, R_028A48_PA_SC_MODE_CNTL_0
,
830 S_028A48_LINE_STIPPLE_ENABLE(state
->line_stipple_enable
) |
831 S_028A48_MSAA_ENABLE(state
->multisample
||
832 state
->poly_smooth
||
833 state
->line_smooth
) |
834 S_028A48_VPORT_SCISSOR_ENABLE(1) |
835 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen
->b
.chip_class
>= GFX9
));
837 si_pm4_set_reg(pm4
, R_028BE4_PA_SU_VTX_CNTL
,
838 S_028BE4_PIX_CENTER(state
->half_pixel_center
) |
839 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH
));
841 si_pm4_set_reg(pm4
, R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, fui(state
->offset_clamp
));
842 si_pm4_set_reg(pm4
, R_028814_PA_SU_SC_MODE_CNTL
,
843 S_028814_PROVOKING_VTX_LAST(!state
->flatshade_first
) |
844 S_028814_CULL_FRONT((state
->cull_face
& PIPE_FACE_FRONT
) ? 1 : 0) |
845 S_028814_CULL_BACK((state
->cull_face
& PIPE_FACE_BACK
) ? 1 : 0) |
846 S_028814_FACE(!state
->front_ccw
) |
847 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state
, state
->fill_front
)) |
848 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state
, state
->fill_back
)) |
849 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_point
|| state
->offset_line
) |
850 S_028814_POLY_MODE(state
->fill_front
!= PIPE_POLYGON_MODE_FILL
||
851 state
->fill_back
!= PIPE_POLYGON_MODE_FILL
) |
852 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state
->fill_front
)) |
853 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state
->fill_back
)));
854 si_pm4_set_reg(pm4
, R_00B130_SPI_SHADER_USER_DATA_VS_0
+
855 SI_SGPR_VS_STATE_BITS
* 4, state
->clamp_vertex_color
);
857 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
858 for (i
= 0; i
< 3; i
++) {
859 struct si_pm4_state
*pm4
= &rs
->pm4_poly_offset
[i
];
860 float offset_units
= state
->offset_units
;
861 float offset_scale
= state
->offset_scale
* 16.0f
;
862 uint32_t pa_su_poly_offset_db_fmt_cntl
= 0;
864 if (!state
->offset_units_unscaled
) {
866 case 0: /* 16-bit zbuffer */
867 offset_units
*= 4.0f
;
868 pa_su_poly_offset_db_fmt_cntl
=
869 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
871 case 1: /* 24-bit zbuffer */
872 offset_units
*= 2.0f
;
873 pa_su_poly_offset_db_fmt_cntl
=
874 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
876 case 2: /* 32-bit zbuffer */
877 offset_units
*= 1.0f
;
878 pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
879 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
884 si_pm4_set_reg(pm4
, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE
,
886 si_pm4_set_reg(pm4
, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET
,
888 si_pm4_set_reg(pm4
, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE
,
890 si_pm4_set_reg(pm4
, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET
,
892 si_pm4_set_reg(pm4
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
893 pa_su_poly_offset_db_fmt_cntl
);
899 static void si_bind_rs_state(struct pipe_context
*ctx
, void *state
)
901 struct si_context
*sctx
= (struct si_context
*)ctx
;
902 struct si_state_rasterizer
*old_rs
=
903 (struct si_state_rasterizer
*)sctx
->queued
.named
.rasterizer
;
904 struct si_state_rasterizer
*rs
= (struct si_state_rasterizer
*)state
;
909 if (!old_rs
|| old_rs
->multisample_enable
!= rs
->multisample_enable
) {
910 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
912 /* Update the small primitive filter workaround if necessary. */
913 if (sctx
->b
.family
>= CHIP_POLARIS10
&&
914 sctx
->framebuffer
.nr_samples
> 1)
915 si_mark_atom_dirty(sctx
, &sctx
->msaa_sample_locs
.atom
);
918 r600_viewport_set_rast_deps(&sctx
->b
, rs
->scissor_enable
, rs
->clip_halfz
);
920 si_pm4_bind_state(sctx
, rasterizer
, rs
);
921 si_update_poly_offset_state(sctx
);
923 si_mark_atom_dirty(sctx
, &sctx
->clip_regs
);
924 sctx
->ia_multi_vgt_param_key
.u
.line_stipple_enabled
=
925 rs
->line_stipple_enable
;
926 sctx
->do_update_shaders
= true;
929 static void si_delete_rs_state(struct pipe_context
*ctx
, void *state
)
931 struct si_context
*sctx
= (struct si_context
*)ctx
;
933 if (sctx
->queued
.named
.rasterizer
== state
)
934 si_pm4_bind_state(sctx
, poly_offset
, NULL
);
935 si_pm4_delete_state(sctx
, rasterizer
, (struct si_state_rasterizer
*)state
);
939 * infeered state between dsa and stencil ref
941 static void si_emit_stencil_ref(struct si_context
*sctx
, struct r600_atom
*atom
)
943 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
944 struct pipe_stencil_ref
*ref
= &sctx
->stencil_ref
.state
;
945 struct si_dsa_stencil_ref_part
*dsa
= &sctx
->stencil_ref
.dsa_part
;
947 radeon_set_context_reg_seq(cs
, R_028430_DB_STENCILREFMASK
, 2);
948 radeon_emit(cs
, S_028430_STENCILTESTVAL(ref
->ref_value
[0]) |
949 S_028430_STENCILMASK(dsa
->valuemask
[0]) |
950 S_028430_STENCILWRITEMASK(dsa
->writemask
[0]) |
951 S_028430_STENCILOPVAL(1));
952 radeon_emit(cs
, S_028434_STENCILTESTVAL_BF(ref
->ref_value
[1]) |
953 S_028434_STENCILMASK_BF(dsa
->valuemask
[1]) |
954 S_028434_STENCILWRITEMASK_BF(dsa
->writemask
[1]) |
955 S_028434_STENCILOPVAL_BF(1));
958 static void si_set_stencil_ref(struct pipe_context
*ctx
,
959 const struct pipe_stencil_ref
*state
)
961 struct si_context
*sctx
= (struct si_context
*)ctx
;
963 if (memcmp(&sctx
->stencil_ref
.state
, state
, sizeof(*state
)) == 0)
966 sctx
->stencil_ref
.state
= *state
;
967 si_mark_atom_dirty(sctx
, &sctx
->stencil_ref
.atom
);
975 static uint32_t si_translate_stencil_op(int s_op
)
978 case PIPE_STENCIL_OP_KEEP
:
979 return V_02842C_STENCIL_KEEP
;
980 case PIPE_STENCIL_OP_ZERO
:
981 return V_02842C_STENCIL_ZERO
;
982 case PIPE_STENCIL_OP_REPLACE
:
983 return V_02842C_STENCIL_REPLACE_TEST
;
984 case PIPE_STENCIL_OP_INCR
:
985 return V_02842C_STENCIL_ADD_CLAMP
;
986 case PIPE_STENCIL_OP_DECR
:
987 return V_02842C_STENCIL_SUB_CLAMP
;
988 case PIPE_STENCIL_OP_INCR_WRAP
:
989 return V_02842C_STENCIL_ADD_WRAP
;
990 case PIPE_STENCIL_OP_DECR_WRAP
:
991 return V_02842C_STENCIL_SUB_WRAP
;
992 case PIPE_STENCIL_OP_INVERT
:
993 return V_02842C_STENCIL_INVERT
;
995 R600_ERR("Unknown stencil op %d", s_op
);
1002 static void *si_create_dsa_state(struct pipe_context
*ctx
,
1003 const struct pipe_depth_stencil_alpha_state
*state
)
1005 struct si_state_dsa
*dsa
= CALLOC_STRUCT(si_state_dsa
);
1006 struct si_pm4_state
*pm4
= &dsa
->pm4
;
1007 unsigned db_depth_control
;
1008 uint32_t db_stencil_control
= 0;
1014 dsa
->stencil_ref
.valuemask
[0] = state
->stencil
[0].valuemask
;
1015 dsa
->stencil_ref
.valuemask
[1] = state
->stencil
[1].valuemask
;
1016 dsa
->stencil_ref
.writemask
[0] = state
->stencil
[0].writemask
;
1017 dsa
->stencil_ref
.writemask
[1] = state
->stencil
[1].writemask
;
1019 db_depth_control
= S_028800_Z_ENABLE(state
->depth
.enabled
) |
1020 S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
1021 S_028800_ZFUNC(state
->depth
.func
) |
1022 S_028800_DEPTH_BOUNDS_ENABLE(state
->depth
.bounds_test
);
1025 if (state
->stencil
[0].enabled
) {
1026 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
1027 db_depth_control
|= S_028800_STENCILFUNC(state
->stencil
[0].func
);
1028 db_stencil_control
|= S_02842C_STENCILFAIL(si_translate_stencil_op(state
->stencil
[0].fail_op
));
1029 db_stencil_control
|= S_02842C_STENCILZPASS(si_translate_stencil_op(state
->stencil
[0].zpass_op
));
1030 db_stencil_control
|= S_02842C_STENCILZFAIL(si_translate_stencil_op(state
->stencil
[0].zfail_op
));
1032 if (state
->stencil
[1].enabled
) {
1033 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
1034 db_depth_control
|= S_028800_STENCILFUNC_BF(state
->stencil
[1].func
);
1035 db_stencil_control
|= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state
->stencil
[1].fail_op
));
1036 db_stencil_control
|= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state
->stencil
[1].zpass_op
));
1037 db_stencil_control
|= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state
->stencil
[1].zfail_op
));
1042 if (state
->alpha
.enabled
) {
1043 dsa
->alpha_func
= state
->alpha
.func
;
1045 si_pm4_set_reg(pm4
, R_00B030_SPI_SHADER_USER_DATA_PS_0
+
1046 SI_SGPR_ALPHA_REF
* 4, fui(state
->alpha
.ref_value
));
1048 dsa
->alpha_func
= PIPE_FUNC_ALWAYS
;
1051 si_pm4_set_reg(pm4
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
1052 si_pm4_set_reg(pm4
, R_02842C_DB_STENCIL_CONTROL
, db_stencil_control
);
1053 if (state
->depth
.bounds_test
) {
1054 si_pm4_set_reg(pm4
, R_028020_DB_DEPTH_BOUNDS_MIN
, fui(state
->depth
.bounds_min
));
1055 si_pm4_set_reg(pm4
, R_028024_DB_DEPTH_BOUNDS_MAX
, fui(state
->depth
.bounds_max
));
1061 static void si_bind_dsa_state(struct pipe_context
*ctx
, void *state
)
1063 struct si_context
*sctx
= (struct si_context
*)ctx
;
1064 struct si_state_dsa
*dsa
= state
;
1069 si_pm4_bind_state(sctx
, dsa
, dsa
);
1071 if (memcmp(&dsa
->stencil_ref
, &sctx
->stencil_ref
.dsa_part
,
1072 sizeof(struct si_dsa_stencil_ref_part
)) != 0) {
1073 sctx
->stencil_ref
.dsa_part
= dsa
->stencil_ref
;
1074 si_mark_atom_dirty(sctx
, &sctx
->stencil_ref
.atom
);
1076 sctx
->do_update_shaders
= true;
1079 static void si_delete_dsa_state(struct pipe_context
*ctx
, void *state
)
1081 struct si_context
*sctx
= (struct si_context
*)ctx
;
1082 si_pm4_delete_state(sctx
, dsa
, (struct si_state_dsa
*)state
);
1085 static void *si_create_db_flush_dsa(struct si_context
*sctx
)
1087 struct pipe_depth_stencil_alpha_state dsa
= {};
1089 return sctx
->b
.b
.create_depth_stencil_alpha_state(&sctx
->b
.b
, &dsa
);
1092 /* DB RENDER STATE */
1094 static void si_set_active_query_state(struct pipe_context
*ctx
, boolean enable
)
1096 struct si_context
*sctx
= (struct si_context
*)ctx
;
1098 /* Pipeline stat & streamout queries. */
1100 sctx
->b
.flags
&= ~R600_CONTEXT_STOP_PIPELINE_STATS
;
1101 sctx
->b
.flags
|= R600_CONTEXT_START_PIPELINE_STATS
;
1103 sctx
->b
.flags
&= ~R600_CONTEXT_START_PIPELINE_STATS
;
1104 sctx
->b
.flags
|= R600_CONTEXT_STOP_PIPELINE_STATS
;
1107 /* Occlusion queries. */
1108 if (sctx
->occlusion_queries_disabled
!= !enable
) {
1109 sctx
->occlusion_queries_disabled
= !enable
;
1110 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
1114 static void si_set_occlusion_query_state(struct pipe_context
*ctx
, bool enable
)
1116 struct si_context
*sctx
= (struct si_context
*)ctx
;
1118 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
1121 static void si_save_qbo_state(struct pipe_context
*ctx
, struct r600_qbo_state
*st
)
1123 struct si_context
*sctx
= (struct si_context
*)ctx
;
1125 st
->saved_compute
= sctx
->cs_shader_state
.program
;
1127 si_get_pipe_constant_buffer(sctx
, PIPE_SHADER_COMPUTE
, 0, &st
->saved_const0
);
1128 si_get_shader_buffers(sctx
, PIPE_SHADER_COMPUTE
, 0, 3, st
->saved_ssbo
);
1131 static void si_emit_db_render_state(struct si_context
*sctx
, struct r600_atom
*state
)
1133 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
1134 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
1135 unsigned db_shader_control
;
1137 radeon_set_context_reg_seq(cs
, R_028000_DB_RENDER_CONTROL
, 2);
1139 /* DB_RENDER_CONTROL */
1140 if (sctx
->dbcb_depth_copy_enabled
||
1141 sctx
->dbcb_stencil_copy_enabled
) {
1143 S_028000_DEPTH_COPY(sctx
->dbcb_depth_copy_enabled
) |
1144 S_028000_STENCIL_COPY(sctx
->dbcb_stencil_copy_enabled
) |
1145 S_028000_COPY_CENTROID(1) |
1146 S_028000_COPY_SAMPLE(sctx
->dbcb_copy_sample
));
1147 } else if (sctx
->db_flush_depth_inplace
|| sctx
->db_flush_stencil_inplace
) {
1149 S_028000_DEPTH_COMPRESS_DISABLE(sctx
->db_flush_depth_inplace
) |
1150 S_028000_STENCIL_COMPRESS_DISABLE(sctx
->db_flush_stencil_inplace
));
1153 S_028000_DEPTH_CLEAR_ENABLE(sctx
->db_depth_clear
) |
1154 S_028000_STENCIL_CLEAR_ENABLE(sctx
->db_stencil_clear
));
1157 /* DB_COUNT_CONTROL (occlusion queries) */
1158 if (sctx
->b
.num_occlusion_queries
> 0 &&
1159 !sctx
->occlusion_queries_disabled
) {
1160 bool perfect
= sctx
->b
.num_perfect_occlusion_queries
> 0;
1162 if (sctx
->b
.chip_class
>= CIK
) {
1164 S_028004_PERFECT_ZPASS_COUNTS(perfect
) |
1165 S_028004_SAMPLE_RATE(sctx
->framebuffer
.log_samples
) |
1166 S_028004_ZPASS_ENABLE(1) |
1167 S_028004_SLICE_EVEN_ENABLE(1) |
1168 S_028004_SLICE_ODD_ENABLE(1));
1171 S_028004_PERFECT_ZPASS_COUNTS(perfect
) |
1172 S_028004_SAMPLE_RATE(sctx
->framebuffer
.log_samples
));
1175 /* Disable occlusion queries. */
1176 if (sctx
->b
.chip_class
>= CIK
) {
1179 radeon_emit(cs
, S_028004_ZPASS_INCREMENT_DISABLE(1));
1183 /* DB_RENDER_OVERRIDE2 */
1184 radeon_set_context_reg(cs
, R_028010_DB_RENDER_OVERRIDE2
,
1185 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx
->db_depth_disable_expclear
) |
1186 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx
->db_stencil_disable_expclear
) |
1187 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx
->framebuffer
.nr_samples
>= 4));
1189 db_shader_control
= sctx
->ps_db_shader_control
;
1191 /* Bug workaround for smoothing (overrasterization) on SI. */
1192 if (sctx
->b
.chip_class
== SI
&& sctx
->smoothing_enabled
) {
1193 db_shader_control
&= C_02880C_Z_ORDER
;
1194 db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
);
1197 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1198 if (!rs
|| !rs
->multisample_enable
)
1199 db_shader_control
&= C_02880C_MASK_EXPORT_ENABLE
;
1201 if (sctx
->screen
->b
.has_rbplus
&&
1202 !sctx
->screen
->b
.rbplus_allowed
)
1203 db_shader_control
|= S_02880C_DUAL_QUAD_DISABLE(1);
1205 radeon_set_context_reg(cs
, R_02880C_DB_SHADER_CONTROL
,
1210 * format translation
1212 static uint32_t si_translate_colorformat(enum pipe_format format
)
1214 const struct util_format_description
*desc
= util_format_description(format
);
1216 #define HAS_SIZE(x,y,z,w) \
1217 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1218 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1220 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
1221 return V_028C70_COLOR_10_11_11
;
1223 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
1224 return V_028C70_COLOR_INVALID
;
1226 /* hw cannot support mixed formats (except depth/stencil, since
1227 * stencil is not written to). */
1228 if (desc
->is_mixed
&& desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
)
1229 return V_028C70_COLOR_INVALID
;
1231 switch (desc
->nr_channels
) {
1233 switch (desc
->channel
[0].size
) {
1235 return V_028C70_COLOR_8
;
1237 return V_028C70_COLOR_16
;
1239 return V_028C70_COLOR_32
;
1243 if (desc
->channel
[0].size
== desc
->channel
[1].size
) {
1244 switch (desc
->channel
[0].size
) {
1246 return V_028C70_COLOR_8_8
;
1248 return V_028C70_COLOR_16_16
;
1250 return V_028C70_COLOR_32_32
;
1252 } else if (HAS_SIZE(8,24,0,0)) {
1253 return V_028C70_COLOR_24_8
;
1254 } else if (HAS_SIZE(24,8,0,0)) {
1255 return V_028C70_COLOR_8_24
;
1259 if (HAS_SIZE(5,6,5,0)) {
1260 return V_028C70_COLOR_5_6_5
;
1261 } else if (HAS_SIZE(32,8,24,0)) {
1262 return V_028C70_COLOR_X24_8_32_FLOAT
;
1266 if (desc
->channel
[0].size
== desc
->channel
[1].size
&&
1267 desc
->channel
[0].size
== desc
->channel
[2].size
&&
1268 desc
->channel
[0].size
== desc
->channel
[3].size
) {
1269 switch (desc
->channel
[0].size
) {
1271 return V_028C70_COLOR_4_4_4_4
;
1273 return V_028C70_COLOR_8_8_8_8
;
1275 return V_028C70_COLOR_16_16_16_16
;
1277 return V_028C70_COLOR_32_32_32_32
;
1279 } else if (HAS_SIZE(5,5,5,1)) {
1280 return V_028C70_COLOR_1_5_5_5
;
1281 } else if (HAS_SIZE(10,10,10,2)) {
1282 return V_028C70_COLOR_2_10_10_10
;
1286 return V_028C70_COLOR_INVALID
;
1289 static uint32_t si_colorformat_endian_swap(uint32_t colorformat
)
1291 if (SI_BIG_ENDIAN
) {
1292 switch(colorformat
) {
1293 /* 8-bit buffers. */
1294 case V_028C70_COLOR_8
:
1295 return V_028C70_ENDIAN_NONE
;
1297 /* 16-bit buffers. */
1298 case V_028C70_COLOR_5_6_5
:
1299 case V_028C70_COLOR_1_5_5_5
:
1300 case V_028C70_COLOR_4_4_4_4
:
1301 case V_028C70_COLOR_16
:
1302 case V_028C70_COLOR_8_8
:
1303 return V_028C70_ENDIAN_8IN16
;
1305 /* 32-bit buffers. */
1306 case V_028C70_COLOR_8_8_8_8
:
1307 case V_028C70_COLOR_2_10_10_10
:
1308 case V_028C70_COLOR_8_24
:
1309 case V_028C70_COLOR_24_8
:
1310 case V_028C70_COLOR_16_16
:
1311 return V_028C70_ENDIAN_8IN32
;
1313 /* 64-bit buffers. */
1314 case V_028C70_COLOR_16_16_16_16
:
1315 return V_028C70_ENDIAN_8IN16
;
1317 case V_028C70_COLOR_32_32
:
1318 return V_028C70_ENDIAN_8IN32
;
1320 /* 128-bit buffers. */
1321 case V_028C70_COLOR_32_32_32_32
:
1322 return V_028C70_ENDIAN_8IN32
;
1324 return V_028C70_ENDIAN_NONE
; /* Unsupported. */
1327 return V_028C70_ENDIAN_NONE
;
1331 static uint32_t si_translate_dbformat(enum pipe_format format
)
1334 case PIPE_FORMAT_Z16_UNORM
:
1335 return V_028040_Z_16
;
1336 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1337 case PIPE_FORMAT_X8Z24_UNORM
:
1338 case PIPE_FORMAT_Z24X8_UNORM
:
1339 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1340 return V_028040_Z_24
; /* deprecated on SI */
1341 case PIPE_FORMAT_Z32_FLOAT
:
1342 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1343 return V_028040_Z_32_FLOAT
;
1345 return V_028040_Z_INVALID
;
1350 * Texture translation
1353 static uint32_t si_translate_texformat(struct pipe_screen
*screen
,
1354 enum pipe_format format
,
1355 const struct util_format_description
*desc
,
1358 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1359 bool enable_compressed_formats
= (sscreen
->b
.info
.drm_major
== 2 &&
1360 sscreen
->b
.info
.drm_minor
>= 31) ||
1361 sscreen
->b
.info
.drm_major
== 3;
1362 bool uniform
= true;
1365 /* Colorspace (return non-RGB formats directly). */
1366 switch (desc
->colorspace
) {
1367 /* Depth stencil formats */
1368 case UTIL_FORMAT_COLORSPACE_ZS
:
1370 case PIPE_FORMAT_Z16_UNORM
:
1371 return V_008F14_IMG_DATA_FORMAT_16
;
1372 case PIPE_FORMAT_X24S8_UINT
:
1373 case PIPE_FORMAT_S8X24_UINT
:
1375 * Implemented as an 8_8_8_8 data format to fix texture
1376 * gathers in stencil sampling. This affects at least
1377 * GL45-CTS.texture_cube_map_array.sampling on VI.
1379 return V_008F14_IMG_DATA_FORMAT_8_8_8_8
;
1380 case PIPE_FORMAT_Z24X8_UNORM
:
1381 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1382 return V_008F14_IMG_DATA_FORMAT_8_24
;
1383 case PIPE_FORMAT_X8Z24_UNORM
:
1384 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1385 return V_008F14_IMG_DATA_FORMAT_24_8
;
1386 case PIPE_FORMAT_S8_UINT
:
1387 return V_008F14_IMG_DATA_FORMAT_8
;
1388 case PIPE_FORMAT_Z32_FLOAT
:
1389 return V_008F14_IMG_DATA_FORMAT_32
;
1390 case PIPE_FORMAT_X32_S8X24_UINT
:
1391 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1392 return V_008F14_IMG_DATA_FORMAT_X24_8_32
;
1397 case UTIL_FORMAT_COLORSPACE_YUV
:
1398 goto out_unknown
; /* TODO */
1400 case UTIL_FORMAT_COLORSPACE_SRGB
:
1401 if (desc
->nr_channels
!= 4 && desc
->nr_channels
!= 1)
1409 if (desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
) {
1410 if (!enable_compressed_formats
)
1414 case PIPE_FORMAT_RGTC1_SNORM
:
1415 case PIPE_FORMAT_LATC1_SNORM
:
1416 case PIPE_FORMAT_RGTC1_UNORM
:
1417 case PIPE_FORMAT_LATC1_UNORM
:
1418 return V_008F14_IMG_DATA_FORMAT_BC4
;
1419 case PIPE_FORMAT_RGTC2_SNORM
:
1420 case PIPE_FORMAT_LATC2_SNORM
:
1421 case PIPE_FORMAT_RGTC2_UNORM
:
1422 case PIPE_FORMAT_LATC2_UNORM
:
1423 return V_008F14_IMG_DATA_FORMAT_BC5
;
1429 if (desc
->layout
== UTIL_FORMAT_LAYOUT_ETC
&&
1430 (sscreen
->b
.family
== CHIP_STONEY
||
1431 sscreen
->b
.chip_class
>= GFX9
)) {
1433 case PIPE_FORMAT_ETC1_RGB8
:
1434 case PIPE_FORMAT_ETC2_RGB8
:
1435 case PIPE_FORMAT_ETC2_SRGB8
:
1436 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB
;
1437 case PIPE_FORMAT_ETC2_RGB8A1
:
1438 case PIPE_FORMAT_ETC2_SRGB8A1
:
1439 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1
;
1440 case PIPE_FORMAT_ETC2_RGBA8
:
1441 case PIPE_FORMAT_ETC2_SRGBA8
:
1442 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA
;
1443 case PIPE_FORMAT_ETC2_R11_UNORM
:
1444 case PIPE_FORMAT_ETC2_R11_SNORM
:
1445 return V_008F14_IMG_DATA_FORMAT_ETC2_R
;
1446 case PIPE_FORMAT_ETC2_RG11_UNORM
:
1447 case PIPE_FORMAT_ETC2_RG11_SNORM
:
1448 return V_008F14_IMG_DATA_FORMAT_ETC2_RG
;
1454 if (desc
->layout
== UTIL_FORMAT_LAYOUT_BPTC
) {
1455 if (!enable_compressed_formats
)
1459 case PIPE_FORMAT_BPTC_RGBA_UNORM
:
1460 case PIPE_FORMAT_BPTC_SRGBA
:
1461 return V_008F14_IMG_DATA_FORMAT_BC7
;
1462 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
1463 case PIPE_FORMAT_BPTC_RGB_UFLOAT
:
1464 return V_008F14_IMG_DATA_FORMAT_BC6
;
1470 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
1472 case PIPE_FORMAT_R8G8_B8G8_UNORM
:
1473 case PIPE_FORMAT_G8R8_B8R8_UNORM
:
1474 return V_008F14_IMG_DATA_FORMAT_GB_GR
;
1475 case PIPE_FORMAT_G8R8_G8B8_UNORM
:
1476 case PIPE_FORMAT_R8G8_R8B8_UNORM
:
1477 return V_008F14_IMG_DATA_FORMAT_BG_RG
;
1483 if (desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
1484 if (!enable_compressed_formats
)
1487 if (!util_format_s3tc_enabled
) {
1492 case PIPE_FORMAT_DXT1_RGB
:
1493 case PIPE_FORMAT_DXT1_RGBA
:
1494 case PIPE_FORMAT_DXT1_SRGB
:
1495 case PIPE_FORMAT_DXT1_SRGBA
:
1496 return V_008F14_IMG_DATA_FORMAT_BC1
;
1497 case PIPE_FORMAT_DXT3_RGBA
:
1498 case PIPE_FORMAT_DXT3_SRGBA
:
1499 return V_008F14_IMG_DATA_FORMAT_BC2
;
1500 case PIPE_FORMAT_DXT5_RGBA
:
1501 case PIPE_FORMAT_DXT5_SRGBA
:
1502 return V_008F14_IMG_DATA_FORMAT_BC3
;
1508 if (format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
1509 return V_008F14_IMG_DATA_FORMAT_5_9_9_9
;
1510 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
1511 return V_008F14_IMG_DATA_FORMAT_10_11_11
;
1514 /* R8G8Bx_SNORM - TODO CxV8U8 */
1516 /* hw cannot support mixed formats (except depth/stencil, since only
1518 if (desc
->is_mixed
&& desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
)
1521 /* See whether the components are of the same size. */
1522 for (i
= 1; i
< desc
->nr_channels
; i
++) {
1523 uniform
= uniform
&& desc
->channel
[0].size
== desc
->channel
[i
].size
;
1526 /* Non-uniform formats. */
1528 switch(desc
->nr_channels
) {
1530 if (desc
->channel
[0].size
== 5 &&
1531 desc
->channel
[1].size
== 6 &&
1532 desc
->channel
[2].size
== 5) {
1533 return V_008F14_IMG_DATA_FORMAT_5_6_5
;
1537 if (desc
->channel
[0].size
== 5 &&
1538 desc
->channel
[1].size
== 5 &&
1539 desc
->channel
[2].size
== 5 &&
1540 desc
->channel
[3].size
== 1) {
1541 return V_008F14_IMG_DATA_FORMAT_1_5_5_5
;
1543 if (desc
->channel
[0].size
== 10 &&
1544 desc
->channel
[1].size
== 10 &&
1545 desc
->channel
[2].size
== 10 &&
1546 desc
->channel
[3].size
== 2) {
1547 return V_008F14_IMG_DATA_FORMAT_2_10_10_10
;
1554 if (first_non_void
< 0 || first_non_void
> 3)
1557 /* uniform formats */
1558 switch (desc
->channel
[first_non_void
].size
) {
1560 switch (desc
->nr_channels
) {
1561 #if 0 /* Not supported for render targets */
1563 return V_008F14_IMG_DATA_FORMAT_4_4
;
1566 return V_008F14_IMG_DATA_FORMAT_4_4_4_4
;
1570 switch (desc
->nr_channels
) {
1572 return V_008F14_IMG_DATA_FORMAT_8
;
1574 return V_008F14_IMG_DATA_FORMAT_8_8
;
1576 return V_008F14_IMG_DATA_FORMAT_8_8_8_8
;
1580 switch (desc
->nr_channels
) {
1582 return V_008F14_IMG_DATA_FORMAT_16
;
1584 return V_008F14_IMG_DATA_FORMAT_16_16
;
1586 return V_008F14_IMG_DATA_FORMAT_16_16_16_16
;
1590 switch (desc
->nr_channels
) {
1592 return V_008F14_IMG_DATA_FORMAT_32
;
1594 return V_008F14_IMG_DATA_FORMAT_32_32
;
1595 #if 0 /* Not supported for render targets */
1597 return V_008F14_IMG_DATA_FORMAT_32_32_32
;
1600 return V_008F14_IMG_DATA_FORMAT_32_32_32_32
;
1605 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1609 static unsigned si_tex_wrap(unsigned wrap
)
1613 case PIPE_TEX_WRAP_REPEAT
:
1614 return V_008F30_SQ_TEX_WRAP
;
1615 case PIPE_TEX_WRAP_CLAMP
:
1616 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER
;
1617 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
1618 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL
;
1619 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
1620 return V_008F30_SQ_TEX_CLAMP_BORDER
;
1621 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
1622 return V_008F30_SQ_TEX_MIRROR
;
1623 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
1624 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
1625 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
1626 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
1627 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
1628 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER
;
1632 static unsigned si_tex_mipfilter(unsigned filter
)
1635 case PIPE_TEX_MIPFILTER_NEAREST
:
1636 return V_008F38_SQ_TEX_Z_FILTER_POINT
;
1637 case PIPE_TEX_MIPFILTER_LINEAR
:
1638 return V_008F38_SQ_TEX_Z_FILTER_LINEAR
;
1640 case PIPE_TEX_MIPFILTER_NONE
:
1641 return V_008F38_SQ_TEX_Z_FILTER_NONE
;
1645 static unsigned si_tex_compare(unsigned compare
)
1649 case PIPE_FUNC_NEVER
:
1650 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
1651 case PIPE_FUNC_LESS
:
1652 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS
;
1653 case PIPE_FUNC_EQUAL
:
1654 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL
;
1655 case PIPE_FUNC_LEQUAL
:
1656 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
1657 case PIPE_FUNC_GREATER
:
1658 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER
;
1659 case PIPE_FUNC_NOTEQUAL
:
1660 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
1661 case PIPE_FUNC_GEQUAL
:
1662 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
1663 case PIPE_FUNC_ALWAYS
:
1664 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
1668 static unsigned si_tex_dim(struct si_screen
*sscreen
, struct r600_texture
*rtex
,
1669 unsigned view_target
, unsigned nr_samples
)
1671 unsigned res_target
= rtex
->resource
.b
.b
.target
;
1673 if (view_target
== PIPE_TEXTURE_CUBE
||
1674 view_target
== PIPE_TEXTURE_CUBE_ARRAY
)
1675 res_target
= view_target
;
1676 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1677 else if (res_target
== PIPE_TEXTURE_CUBE
||
1678 res_target
== PIPE_TEXTURE_CUBE_ARRAY
)
1679 res_target
= PIPE_TEXTURE_2D_ARRAY
;
1681 /* GFX9 allocates 1D textures as 2D. */
1682 if ((res_target
== PIPE_TEXTURE_1D
||
1683 res_target
== PIPE_TEXTURE_1D_ARRAY
) &&
1684 sscreen
->b
.chip_class
>= GFX9
&&
1685 rtex
->surface
.u
.gfx9
.resource_type
== RADEON_RESOURCE_2D
) {
1686 if (res_target
== PIPE_TEXTURE_1D
)
1687 res_target
= PIPE_TEXTURE_2D
;
1689 res_target
= PIPE_TEXTURE_2D_ARRAY
;
1692 switch (res_target
) {
1694 case PIPE_TEXTURE_1D
:
1695 return V_008F1C_SQ_RSRC_IMG_1D
;
1696 case PIPE_TEXTURE_1D_ARRAY
:
1697 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY
;
1698 case PIPE_TEXTURE_2D
:
1699 case PIPE_TEXTURE_RECT
:
1700 return nr_samples
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA
:
1701 V_008F1C_SQ_RSRC_IMG_2D
;
1702 case PIPE_TEXTURE_2D_ARRAY
:
1703 return nr_samples
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
:
1704 V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
1705 case PIPE_TEXTURE_3D
:
1706 return V_008F1C_SQ_RSRC_IMG_3D
;
1707 case PIPE_TEXTURE_CUBE
:
1708 case PIPE_TEXTURE_CUBE_ARRAY
:
1709 return V_008F1C_SQ_RSRC_IMG_CUBE
;
1714 * Format support testing
1717 static bool si_is_sampler_format_supported(struct pipe_screen
*screen
, enum pipe_format format
)
1719 return si_translate_texformat(screen
, format
, util_format_description(format
),
1720 util_format_get_first_non_void_channel(format
)) != ~0U;
1723 static uint32_t si_translate_buffer_dataformat(struct pipe_screen
*screen
,
1724 const struct util_format_description
*desc
,
1729 if (desc
->format
== PIPE_FORMAT_R11G11B10_FLOAT
)
1730 return V_008F0C_BUF_DATA_FORMAT_10_11_11
;
1732 assert(first_non_void
>= 0);
1734 if (desc
->nr_channels
== 4 &&
1735 desc
->channel
[0].size
== 10 &&
1736 desc
->channel
[1].size
== 10 &&
1737 desc
->channel
[2].size
== 10 &&
1738 desc
->channel
[3].size
== 2)
1739 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10
;
1741 /* See whether the components are of the same size. */
1742 for (i
= 0; i
< desc
->nr_channels
; i
++) {
1743 if (desc
->channel
[first_non_void
].size
!= desc
->channel
[i
].size
)
1744 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
1747 switch (desc
->channel
[first_non_void
].size
) {
1749 switch (desc
->nr_channels
) {
1751 case 3: /* 3 loads */
1752 return V_008F0C_BUF_DATA_FORMAT_8
;
1754 return V_008F0C_BUF_DATA_FORMAT_8_8
;
1756 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8
;
1760 switch (desc
->nr_channels
) {
1762 case 3: /* 3 loads */
1763 return V_008F0C_BUF_DATA_FORMAT_16
;
1765 return V_008F0C_BUF_DATA_FORMAT_16_16
;
1767 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16
;
1771 switch (desc
->nr_channels
) {
1773 return V_008F0C_BUF_DATA_FORMAT_32
;
1775 return V_008F0C_BUF_DATA_FORMAT_32_32
;
1777 return V_008F0C_BUF_DATA_FORMAT_32_32_32
;
1779 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
1783 /* Legacy double formats. */
1784 switch (desc
->nr_channels
) {
1785 case 1: /* 1 load */
1786 return V_008F0C_BUF_DATA_FORMAT_32_32
;
1787 case 2: /* 1 load */
1788 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
1789 case 3: /* 3 loads */
1790 return V_008F0C_BUF_DATA_FORMAT_32_32
;
1791 case 4: /* 2 loads */
1792 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
1797 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
1800 static uint32_t si_translate_buffer_numformat(struct pipe_screen
*screen
,
1801 const struct util_format_description
*desc
,
1804 if (desc
->format
== PIPE_FORMAT_R11G11B10_FLOAT
)
1805 return V_008F0C_BUF_NUM_FORMAT_FLOAT
;
1807 assert(first_non_void
>= 0);
1809 switch (desc
->channel
[first_non_void
].type
) {
1810 case UTIL_FORMAT_TYPE_SIGNED
:
1811 case UTIL_FORMAT_TYPE_FIXED
:
1812 if (desc
->channel
[first_non_void
].size
>= 32 ||
1813 desc
->channel
[first_non_void
].pure_integer
)
1814 return V_008F0C_BUF_NUM_FORMAT_SINT
;
1815 else if (desc
->channel
[first_non_void
].normalized
)
1816 return V_008F0C_BUF_NUM_FORMAT_SNORM
;
1818 return V_008F0C_BUF_NUM_FORMAT_SSCALED
;
1820 case UTIL_FORMAT_TYPE_UNSIGNED
:
1821 if (desc
->channel
[first_non_void
].size
>= 32 ||
1822 desc
->channel
[first_non_void
].pure_integer
)
1823 return V_008F0C_BUF_NUM_FORMAT_UINT
;
1824 else if (desc
->channel
[first_non_void
].normalized
)
1825 return V_008F0C_BUF_NUM_FORMAT_UNORM
;
1827 return V_008F0C_BUF_NUM_FORMAT_USCALED
;
1829 case UTIL_FORMAT_TYPE_FLOAT
:
1831 return V_008F0C_BUF_NUM_FORMAT_FLOAT
;
1835 static unsigned si_is_vertex_format_supported(struct pipe_screen
*screen
,
1836 enum pipe_format format
,
1839 const struct util_format_description
*desc
;
1841 unsigned data_format
;
1843 assert((usage
& ~(PIPE_BIND_SHADER_IMAGE
|
1844 PIPE_BIND_SAMPLER_VIEW
|
1845 PIPE_BIND_VERTEX_BUFFER
)) == 0);
1847 desc
= util_format_description(format
);
1849 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
1850 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
1851 * for read-only access (with caveats surrounding bounds checks), but
1852 * obviously fails for write access which we have to implement for
1853 * shader images. Luckily, OpenGL doesn't expect this to be supported
1854 * anyway, and so the only impact is on PBO uploads / downloads, which
1855 * shouldn't be expected to be fast for GL_RGB anyway.
1857 if (desc
->block
.bits
== 3 * 8 ||
1858 desc
->block
.bits
== 3 * 16) {
1859 if (usage
& (PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SAMPLER_VIEW
)) {
1860 usage
&= ~(PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SAMPLER_VIEW
);
1866 first_non_void
= util_format_get_first_non_void_channel(format
);
1867 data_format
= si_translate_buffer_dataformat(screen
, desc
, first_non_void
);
1868 if (data_format
== V_008F0C_BUF_DATA_FORMAT_INVALID
)
1874 static bool si_is_colorbuffer_format_supported(enum pipe_format format
)
1876 return si_translate_colorformat(format
) != V_028C70_COLOR_INVALID
&&
1877 r600_translate_colorswap(format
, false) != ~0U;
1880 static bool si_is_zs_format_supported(enum pipe_format format
)
1882 return si_translate_dbformat(format
) != V_028040_Z_INVALID
;
1885 static boolean
si_is_format_supported(struct pipe_screen
*screen
,
1886 enum pipe_format format
,
1887 enum pipe_texture_target target
,
1888 unsigned sample_count
,
1891 unsigned retval
= 0;
1893 if (target
>= PIPE_MAX_TEXTURE_TYPES
) {
1894 R600_ERR("r600: unsupported texture type %d\n", target
);
1898 if (!util_format_is_supported(format
, usage
))
1901 if (sample_count
> 1) {
1902 if (!screen
->get_param(screen
, PIPE_CAP_TEXTURE_MULTISAMPLE
))
1905 if (usage
& PIPE_BIND_SHADER_IMAGE
)
1908 switch (sample_count
) {
1914 if (format
== PIPE_FORMAT_NONE
)
1923 if (usage
& (PIPE_BIND_SAMPLER_VIEW
|
1924 PIPE_BIND_SHADER_IMAGE
)) {
1925 if (target
== PIPE_BUFFER
) {
1926 retval
|= si_is_vertex_format_supported(
1927 screen
, format
, usage
& (PIPE_BIND_SAMPLER_VIEW
|
1928 PIPE_BIND_SHADER_IMAGE
));
1930 if (si_is_sampler_format_supported(screen
, format
))
1931 retval
|= usage
& (PIPE_BIND_SAMPLER_VIEW
|
1932 PIPE_BIND_SHADER_IMAGE
);
1936 if ((usage
& (PIPE_BIND_RENDER_TARGET
|
1937 PIPE_BIND_DISPLAY_TARGET
|
1940 PIPE_BIND_BLENDABLE
)) &&
1941 si_is_colorbuffer_format_supported(format
)) {
1943 (PIPE_BIND_RENDER_TARGET
|
1944 PIPE_BIND_DISPLAY_TARGET
|
1947 if (!util_format_is_pure_integer(format
) &&
1948 !util_format_is_depth_or_stencil(format
))
1949 retval
|= usage
& PIPE_BIND_BLENDABLE
;
1952 if ((usage
& PIPE_BIND_DEPTH_STENCIL
) &&
1953 si_is_zs_format_supported(format
)) {
1954 retval
|= PIPE_BIND_DEPTH_STENCIL
;
1957 if (usage
& PIPE_BIND_VERTEX_BUFFER
) {
1958 retval
|= si_is_vertex_format_supported(screen
, format
,
1959 PIPE_BIND_VERTEX_BUFFER
);
1962 if ((usage
& PIPE_BIND_LINEAR
) &&
1963 !util_format_is_compressed(format
) &&
1964 !(usage
& PIPE_BIND_DEPTH_STENCIL
))
1965 retval
|= PIPE_BIND_LINEAR
;
1967 return retval
== usage
;
1971 * framebuffer handling
1974 static void si_choose_spi_color_formats(struct r600_surface
*surf
,
1975 unsigned format
, unsigned swap
,
1976 unsigned ntype
, bool is_depth
)
1978 /* Alpha is needed for alpha-to-coverage.
1979 * Blending may be with or without alpha.
1981 unsigned normal
= 0; /* most optimal, may not support blending or export alpha */
1982 unsigned alpha
= 0; /* exports alpha, but may not support blending */
1983 unsigned blend
= 0; /* supports blending, but may not export alpha */
1984 unsigned blend_alpha
= 0; /* least optimal, supports blending and exports alpha */
1986 /* Choose the SPI color formats. These are required values for RB+.
1987 * Other chips have multiple choices, though they are not necessarily better.
1990 case V_028C70_COLOR_5_6_5
:
1991 case V_028C70_COLOR_1_5_5_5
:
1992 case V_028C70_COLOR_5_5_5_1
:
1993 case V_028C70_COLOR_4_4_4_4
:
1994 case V_028C70_COLOR_10_11_11
:
1995 case V_028C70_COLOR_11_11_10
:
1996 case V_028C70_COLOR_8
:
1997 case V_028C70_COLOR_8_8
:
1998 case V_028C70_COLOR_8_8_8_8
:
1999 case V_028C70_COLOR_10_10_10_2
:
2000 case V_028C70_COLOR_2_10_10_10
:
2001 if (ntype
== V_028C70_NUMBER_UINT
)
2002 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
2003 else if (ntype
== V_028C70_NUMBER_SINT
)
2004 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
2006 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
2009 case V_028C70_COLOR_16
:
2010 case V_028C70_COLOR_16_16
:
2011 case V_028C70_COLOR_16_16_16_16
:
2012 if (ntype
== V_028C70_NUMBER_UNORM
||
2013 ntype
== V_028C70_NUMBER_SNORM
) {
2014 /* UNORM16 and SNORM16 don't support blending */
2015 if (ntype
== V_028C70_NUMBER_UNORM
)
2016 normal
= alpha
= V_028714_SPI_SHADER_UNORM16_ABGR
;
2018 normal
= alpha
= V_028714_SPI_SHADER_SNORM16_ABGR
;
2020 /* Use 32 bits per channel for blending. */
2021 if (format
== V_028C70_COLOR_16
) {
2022 if (swap
== V_028C70_SWAP_STD
) { /* R */
2023 blend
= V_028714_SPI_SHADER_32_R
;
2024 blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2025 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
2026 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2029 } else if (format
== V_028C70_COLOR_16_16
) {
2030 if (swap
== V_028C70_SWAP_STD
) { /* RG */
2031 blend
= V_028714_SPI_SHADER_32_GR
;
2032 blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2033 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
2034 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2037 } else /* 16_16_16_16 */
2038 blend
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2039 } else if (ntype
== V_028C70_NUMBER_UINT
)
2040 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
2041 else if (ntype
== V_028C70_NUMBER_SINT
)
2042 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
2043 else if (ntype
== V_028C70_NUMBER_FLOAT
)
2044 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
2049 case V_028C70_COLOR_32
:
2050 if (swap
== V_028C70_SWAP_STD
) { /* R */
2051 blend
= normal
= V_028714_SPI_SHADER_32_R
;
2052 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2053 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
2054 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
2059 case V_028C70_COLOR_32_32
:
2060 if (swap
== V_028C70_SWAP_STD
) { /* RG */
2061 blend
= normal
= V_028714_SPI_SHADER_32_GR
;
2062 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2063 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
2064 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
2069 case V_028C70_COLOR_32_32_32_32
:
2070 case V_028C70_COLOR_8_24
:
2071 case V_028C70_COLOR_24_8
:
2072 case V_028C70_COLOR_X24_8_32_FLOAT
:
2073 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
2081 /* The DB->CB copy needs 32_ABGR. */
2083 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
2085 surf
->spi_shader_col_format
= normal
;
2086 surf
->spi_shader_col_format_alpha
= alpha
;
2087 surf
->spi_shader_col_format_blend
= blend
;
2088 surf
->spi_shader_col_format_blend_alpha
= blend_alpha
;
2091 static void si_initialize_color_surface(struct si_context
*sctx
,
2092 struct r600_surface
*surf
)
2094 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->base
.texture
;
2095 unsigned color_info
, color_attrib
, color_view
;
2096 unsigned format
, swap
, ntype
, endian
;
2097 const struct util_format_description
*desc
;
2099 unsigned blend_clamp
= 0, blend_bypass
= 0;
2101 color_view
= S_028C6C_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
2102 S_028C6C_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
2104 desc
= util_format_description(surf
->base
.format
);
2105 for (i
= 0; i
< 4; i
++) {
2106 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
2110 if (i
== 4 || desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
) {
2111 ntype
= V_028C70_NUMBER_FLOAT
;
2113 ntype
= V_028C70_NUMBER_UNORM
;
2114 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
2115 ntype
= V_028C70_NUMBER_SRGB
;
2116 else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2117 if (desc
->channel
[i
].pure_integer
) {
2118 ntype
= V_028C70_NUMBER_SINT
;
2120 assert(desc
->channel
[i
].normalized
);
2121 ntype
= V_028C70_NUMBER_SNORM
;
2123 } else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
2124 if (desc
->channel
[i
].pure_integer
) {
2125 ntype
= V_028C70_NUMBER_UINT
;
2127 assert(desc
->channel
[i
].normalized
);
2128 ntype
= V_028C70_NUMBER_UNORM
;
2133 format
= si_translate_colorformat(surf
->base
.format
);
2134 if (format
== V_028C70_COLOR_INVALID
) {
2135 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf
->base
.format
);
2137 assert(format
!= V_028C70_COLOR_INVALID
);
2138 swap
= r600_translate_colorswap(surf
->base
.format
, false);
2139 endian
= si_colorformat_endian_swap(format
);
2141 /* blend clamp should be set for all NORM/SRGB types */
2142 if (ntype
== V_028C70_NUMBER_UNORM
||
2143 ntype
== V_028C70_NUMBER_SNORM
||
2144 ntype
== V_028C70_NUMBER_SRGB
)
2147 /* set blend bypass according to docs if SINT/UINT or
2148 8/24 COLOR variants */
2149 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
2150 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
2151 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
2156 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
) {
2157 if (format
== V_028C70_COLOR_8
||
2158 format
== V_028C70_COLOR_8_8
||
2159 format
== V_028C70_COLOR_8_8_8_8
)
2160 surf
->color_is_int8
= true;
2161 else if (format
== V_028C70_COLOR_10_10_10_2
||
2162 format
== V_028C70_COLOR_2_10_10_10
)
2163 surf
->color_is_int10
= true;
2166 color_info
= S_028C70_FORMAT(format
) |
2167 S_028C70_COMP_SWAP(swap
) |
2168 S_028C70_BLEND_CLAMP(blend_clamp
) |
2169 S_028C70_BLEND_BYPASS(blend_bypass
) |
2170 S_028C70_SIMPLE_FLOAT(1) |
2171 S_028C70_ROUND_MODE(ntype
!= V_028C70_NUMBER_UNORM
&&
2172 ntype
!= V_028C70_NUMBER_SNORM
&&
2173 ntype
!= V_028C70_NUMBER_SRGB
&&
2174 format
!= V_028C70_COLOR_8_24
&&
2175 format
!= V_028C70_COLOR_24_8
) |
2176 S_028C70_NUMBER_TYPE(ntype
) |
2177 S_028C70_ENDIAN(endian
);
2179 /* Intensity is implemented as Red, so treat it that way. */
2180 color_attrib
= S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] == PIPE_SWIZZLE_1
||
2181 util_format_is_intensity(surf
->base
.format
));
2183 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
2184 unsigned log_samples
= util_logbase2(rtex
->resource
.b
.b
.nr_samples
);
2186 color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
2187 S_028C74_NUM_FRAGMENTS(log_samples
);
2189 if (rtex
->fmask
.size
) {
2190 color_info
|= S_028C70_COMPRESSION(1);
2191 unsigned fmask_bankh
= util_logbase2(rtex
->fmask
.bank_height
);
2193 if (sctx
->b
.chip_class
== SI
) {
2194 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2195 color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh
);
2200 surf
->cb_color_view
= color_view
;
2201 surf
->cb_color_info
= color_info
;
2202 surf
->cb_color_attrib
= color_attrib
;
2204 if (sctx
->b
.chip_class
>= VI
) {
2205 unsigned max_uncompressed_block_size
= 2;
2207 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
2208 if (rtex
->surface
.bpe
== 1)
2209 max_uncompressed_block_size
= 0;
2210 else if (rtex
->surface
.bpe
== 2)
2211 max_uncompressed_block_size
= 1;
2214 surf
->cb_dcc_control
= S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size
) |
2215 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2218 /* This must be set for fast clear to work without FMASK. */
2219 if (!rtex
->fmask
.size
&& sctx
->b
.chip_class
== SI
) {
2220 unsigned bankh
= util_logbase2(rtex
->surface
.u
.legacy
.bankh
);
2221 surf
->cb_color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(bankh
);
2224 if (sctx
->b
.chip_class
>= GFX9
) {
2225 unsigned mip0_depth
= util_max_layer(&rtex
->resource
.b
.b
, 0);
2227 surf
->cb_color_view
|= S_028C6C_MIP_LEVEL(surf
->base
.u
.tex
.level
);
2228 surf
->cb_color_attrib
|= S_028C74_MIP0_DEPTH(mip0_depth
) |
2229 S_028C74_RESOURCE_TYPE(rtex
->surface
.u
.gfx9
.resource_type
);
2230 surf
->cb_color_attrib2
= S_028C68_MIP0_WIDTH(rtex
->resource
.b
.b
.width0
- 1) |
2231 S_028C68_MIP0_HEIGHT(rtex
->resource
.b
.b
.height0
- 1) |
2232 S_028C68_MAX_MIP(rtex
->resource
.b
.b
.last_level
);
2235 /* Determine pixel shader export format */
2236 si_choose_spi_color_formats(surf
, format
, swap
, ntype
, rtex
->is_depth
);
2238 surf
->color_initialized
= true;
2241 static void si_init_depth_surface(struct si_context
*sctx
,
2242 struct r600_surface
*surf
)
2244 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->base
.texture
;
2245 unsigned level
= surf
->base
.u
.tex
.level
;
2246 unsigned format
, stencil_format
;
2247 uint32_t z_info
, s_info
;
2249 format
= si_translate_dbformat(rtex
->db_render_format
);
2250 stencil_format
= rtex
->surface
.flags
& RADEON_SURF_SBUFFER
?
2251 V_028044_STENCIL_8
: V_028044_STENCIL_INVALID
;
2253 assert(format
!= V_028040_Z_INVALID
);
2254 if (format
== V_028040_Z_INVALID
)
2255 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex
->resource
.b
.b
.format
);
2257 surf
->db_depth_view
= S_028008_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
2258 S_028008_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
2259 surf
->db_htile_data_base
= 0;
2260 surf
->db_htile_surface
= 0;
2262 if (sctx
->b
.chip_class
>= GFX9
) {
2263 surf
->db_depth_base
= rtex
->resource
.gpu_address
>> 8;
2264 surf
->db_stencil_base
= (rtex
->resource
.gpu_address
+
2265 rtex
->surface
.u
.gfx9
.stencil_offset
) >> 8;
2266 z_info
= S_028038_FORMAT(format
) |
2267 S_028038_NUM_SAMPLES(util_logbase2(rtex
->resource
.b
.b
.nr_samples
)) |
2268 S_028038_SW_MODE(rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
2269 S_028038_MAXMIP(rtex
->resource
.b
.b
.last_level
);
2270 s_info
= S_02803C_FORMAT(stencil_format
) |
2271 S_02803C_SW_MODE(rtex
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
2272 surf
->db_z_info2
= S_028068_EPITCH(rtex
->surface
.u
.gfx9
.surf
.epitch
);
2273 surf
->db_stencil_info2
= S_02806C_EPITCH(rtex
->surface
.u
.gfx9
.stencil
.epitch
);
2274 surf
->db_depth_view
|= S_028008_MIPID(level
);
2275 surf
->db_depth_size
= S_02801C_X_MAX(rtex
->resource
.b
.b
.width0
- 1) |
2276 S_02801C_Y_MAX(rtex
->resource
.b
.b
.height0
- 1);
2278 /* Only use HTILE for the first level. */
2279 if (rtex
->htile_buffer
&& !level
) {
2280 z_info
|= S_028038_TILE_SURFACE_ENABLE(1) |
2281 S_028038_ALLOW_EXPCLEAR(1);
2283 if (rtex
->tc_compatible_htile
) {
2284 unsigned max_zplanes
= 4;
2286 if (rtex
->db_render_format
== PIPE_FORMAT_Z16_UNORM
&&
2287 rtex
->resource
.b
.b
.nr_samples
> 1)
2290 z_info
|= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes
+ 1) |
2291 S_028038_ITERATE_FLUSH(1);
2292 s_info
|= S_02803C_ITERATE_FLUSH(1);
2295 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
2296 /* Stencil buffer workaround ported from the SI-CI-VI code.
2297 * See that for explanation.
2299 s_info
|= S_02803C_ALLOW_EXPCLEAR(rtex
->resource
.b
.b
.nr_samples
<= 1);
2301 /* Use all HTILE for depth if there's no stencil. */
2302 s_info
|= S_02803C_TILE_STENCIL_DISABLE(1);
2305 surf
->db_htile_data_base
= rtex
->htile_buffer
->gpu_address
>> 8;
2306 surf
->db_htile_surface
= S_028ABC_FULL_CACHE(1) |
2307 S_028ABC_PIPE_ALIGNED(rtex
->surface
.u
.gfx9
.htile
.pipe_aligned
) |
2308 S_028ABC_RB_ALIGNED(rtex
->surface
.u
.gfx9
.htile
.rb_aligned
);
2312 struct legacy_surf_level
*levelinfo
= &rtex
->surface
.u
.legacy
.level
[level
];
2314 assert(levelinfo
->nblk_x
% 8 == 0 && levelinfo
->nblk_y
% 8 == 0);
2316 surf
->db_depth_base
= (rtex
->resource
.gpu_address
+
2317 rtex
->surface
.u
.legacy
.level
[level
].offset
) >> 8;
2318 surf
->db_stencil_base
= (rtex
->resource
.gpu_address
+
2319 rtex
->surface
.u
.legacy
.stencil_level
[level
].offset
) >> 8;
2321 z_info
= S_028040_FORMAT(format
) |
2322 S_028040_NUM_SAMPLES(util_logbase2(rtex
->resource
.b
.b
.nr_samples
));
2323 s_info
= S_028044_FORMAT(stencil_format
);
2324 surf
->db_depth_info
= S_02803C_ADDR5_SWIZZLE_MASK(!rtex
->tc_compatible_htile
);
2326 if (sctx
->b
.chip_class
>= CIK
) {
2327 struct radeon_info
*info
= &sctx
->screen
->b
.info
;
2328 unsigned index
= rtex
->surface
.u
.legacy
.tiling_index
[level
];
2329 unsigned stencil_index
= rtex
->surface
.u
.legacy
.stencil_tiling_index
[level
];
2330 unsigned macro_index
= rtex
->surface
.u
.legacy
.macro_tile_index
;
2331 unsigned tile_mode
= info
->si_tile_mode_array
[index
];
2332 unsigned stencil_tile_mode
= info
->si_tile_mode_array
[stencil_index
];
2333 unsigned macro_mode
= info
->cik_macrotile_mode_array
[macro_index
];
2335 surf
->db_depth_info
|=
2336 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode
)) |
2337 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode
)) |
2338 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode
)) |
2339 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode
)) |
2340 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode
)) |
2341 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode
));
2342 z_info
|= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode
));
2343 s_info
|= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode
));
2345 unsigned tile_mode_index
= si_tile_mode_index(rtex
, level
, false);
2346 z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
2347 tile_mode_index
= si_tile_mode_index(rtex
, level
, true);
2348 s_info
|= S_028044_TILE_MODE_INDEX(tile_mode_index
);
2351 surf
->db_depth_size
= S_028058_PITCH_TILE_MAX((levelinfo
->nblk_x
/ 8) - 1) |
2352 S_028058_HEIGHT_TILE_MAX((levelinfo
->nblk_y
/ 8) - 1);
2353 surf
->db_depth_slice
= S_02805C_SLICE_TILE_MAX((levelinfo
->nblk_x
*
2354 levelinfo
->nblk_y
) / 64 - 1);
2356 /* Only use HTILE for the first level. */
2357 if (rtex
->htile_buffer
&& !level
) {
2358 z_info
|= S_028040_TILE_SURFACE_ENABLE(1) |
2359 S_028040_ALLOW_EXPCLEAR(1);
2361 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
2362 /* Workaround: For a not yet understood reason, the
2363 * combination of MSAA, fast stencil clear and stencil
2364 * decompress messes with subsequent stencil buffer
2365 * uses. Problem was reproduced on Verde, Bonaire,
2366 * Tonga, and Carrizo.
2368 * Disabling EXPCLEAR works around the problem.
2370 * Check piglit's arb_texture_multisample-stencil-clear
2371 * test if you want to try changing this.
2373 if (rtex
->resource
.b
.b
.nr_samples
<= 1)
2374 s_info
|= S_028044_ALLOW_EXPCLEAR(1);
2375 } else if (!rtex
->tc_compatible_htile
) {
2376 /* Use all of the htile_buffer for depth if there's no stencil.
2377 * This must not be set when TC-compatible HTILE is enabled
2380 s_info
|= S_028044_TILE_STENCIL_DISABLE(1);
2383 surf
->db_htile_data_base
= rtex
->htile_buffer
->gpu_address
>> 8;
2384 surf
->db_htile_surface
= S_028ABC_FULL_CACHE(1);
2386 if (rtex
->tc_compatible_htile
) {
2387 surf
->db_htile_surface
|= S_028ABC_TC_COMPATIBLE(1);
2389 if (rtex
->resource
.b
.b
.nr_samples
<= 1)
2390 z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2391 else if (rtex
->resource
.b
.b
.nr_samples
<= 4)
2392 z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2394 z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2399 surf
->db_z_info
= z_info
;
2400 surf
->db_stencil_info
= s_info
;
2402 surf
->depth_initialized
= true;
2405 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state
*state
)
2407 for (int i
= 0; i
< state
->nr_cbufs
; ++i
) {
2408 struct r600_surface
*surf
= NULL
;
2409 struct r600_texture
*rtex
;
2411 if (!state
->cbufs
[i
])
2413 surf
= (struct r600_surface
*)state
->cbufs
[i
];
2414 rtex
= (struct r600_texture
*)surf
->base
.texture
;
2416 p_atomic_dec(&rtex
->framebuffers_bound
);
2420 static void si_set_framebuffer_state(struct pipe_context
*ctx
,
2421 const struct pipe_framebuffer_state
*state
)
2423 struct si_context
*sctx
= (struct si_context
*)ctx
;
2424 struct pipe_constant_buffer constbuf
= {0};
2425 struct r600_surface
*surf
= NULL
;
2426 struct r600_texture
*rtex
;
2427 bool old_any_dst_linear
= sctx
->framebuffer
.any_dst_linear
;
2428 unsigned old_nr_samples
= sctx
->framebuffer
.nr_samples
;
2431 for (i
= 0; i
< sctx
->framebuffer
.state
.nr_cbufs
; i
++) {
2432 if (!sctx
->framebuffer
.state
.cbufs
[i
])
2435 rtex
= (struct r600_texture
*)sctx
->framebuffer
.state
.cbufs
[i
]->texture
;
2436 if (rtex
->dcc_gather_statistics
)
2437 vi_separate_dcc_stop_query(ctx
, rtex
);
2440 /* Only flush TC when changing the framebuffer state, because
2441 * the only client not using TC that can change textures is
2444 * Flush all CB and DB caches here because all buffers can be used
2445 * for write by both TC (with shader image stores) and CB/DB.
2447 sctx
->b
.flags
|= SI_CONTEXT_INV_VMEM_L1
|
2448 SI_CONTEXT_INV_GLOBAL_L2
|
2449 SI_CONTEXT_FLUSH_AND_INV_CB
|
2450 SI_CONTEXT_FLUSH_AND_INV_DB
|
2451 SI_CONTEXT_CS_PARTIAL_FLUSH
;
2453 /* Take the maximum of the old and new count. If the new count is lower,
2454 * dirtying is needed to disable the unbound colorbuffers.
2456 sctx
->framebuffer
.dirty_cbufs
|=
2457 (1 << MAX2(sctx
->framebuffer
.state
.nr_cbufs
, state
->nr_cbufs
)) - 1;
2458 sctx
->framebuffer
.dirty_zsbuf
|= sctx
->framebuffer
.state
.zsbuf
!= state
->zsbuf
;
2460 si_dec_framebuffer_counters(&sctx
->framebuffer
.state
);
2461 util_copy_framebuffer_state(&sctx
->framebuffer
.state
, state
);
2463 sctx
->framebuffer
.colorbuf_enabled_4bit
= 0;
2464 sctx
->framebuffer
.spi_shader_col_format
= 0;
2465 sctx
->framebuffer
.spi_shader_col_format_alpha
= 0;
2466 sctx
->framebuffer
.spi_shader_col_format_blend
= 0;
2467 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
= 0;
2468 sctx
->framebuffer
.color_is_int8
= 0;
2469 sctx
->framebuffer
.color_is_int10
= 0;
2471 sctx
->framebuffer
.compressed_cb_mask
= 0;
2472 sctx
->framebuffer
.nr_samples
= util_framebuffer_get_num_samples(state
);
2473 sctx
->framebuffer
.log_samples
= util_logbase2(sctx
->framebuffer
.nr_samples
);
2474 sctx
->framebuffer
.any_dst_linear
= false;
2476 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
2477 if (!state
->cbufs
[i
])
2480 surf
= (struct r600_surface
*)state
->cbufs
[i
];
2481 rtex
= (struct r600_texture
*)surf
->base
.texture
;
2483 if (!surf
->color_initialized
) {
2484 si_initialize_color_surface(sctx
, surf
);
2487 sctx
->framebuffer
.colorbuf_enabled_4bit
|= 0xf << (i
* 4);
2488 sctx
->framebuffer
.spi_shader_col_format
|=
2489 surf
->spi_shader_col_format
<< (i
* 4);
2490 sctx
->framebuffer
.spi_shader_col_format_alpha
|=
2491 surf
->spi_shader_col_format_alpha
<< (i
* 4);
2492 sctx
->framebuffer
.spi_shader_col_format_blend
|=
2493 surf
->spi_shader_col_format_blend
<< (i
* 4);
2494 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
|=
2495 surf
->spi_shader_col_format_blend_alpha
<< (i
* 4);
2497 if (surf
->color_is_int8
)
2498 sctx
->framebuffer
.color_is_int8
|= 1 << i
;
2499 if (surf
->color_is_int10
)
2500 sctx
->framebuffer
.color_is_int10
|= 1 << i
;
2502 if (rtex
->fmask
.size
) {
2503 sctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
2506 if (rtex
->surface
.is_linear
)
2507 sctx
->framebuffer
.any_dst_linear
= true;
2509 r600_context_add_resource_size(ctx
, surf
->base
.texture
);
2511 p_atomic_inc(&rtex
->framebuffers_bound
);
2513 if (rtex
->dcc_gather_statistics
) {
2514 /* Dirty tracking must be enabled for DCC usage analysis. */
2515 sctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
2516 vi_separate_dcc_start_query(ctx
, rtex
);
2521 surf
= (struct r600_surface
*)state
->zsbuf
;
2522 rtex
= (struct r600_texture
*)surf
->base
.texture
;
2524 if (!surf
->depth_initialized
) {
2525 si_init_depth_surface(sctx
, surf
);
2527 r600_context_add_resource_size(ctx
, surf
->base
.texture
);
2530 si_update_poly_offset_state(sctx
);
2531 si_mark_atom_dirty(sctx
, &sctx
->cb_render_state
);
2532 si_mark_atom_dirty(sctx
, &sctx
->framebuffer
.atom
);
2534 if (sctx
->framebuffer
.any_dst_linear
!= old_any_dst_linear
)
2535 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
2537 if (sctx
->framebuffer
.nr_samples
!= old_nr_samples
) {
2538 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
2539 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
2541 /* Set sample locations as fragment shader constants. */
2542 switch (sctx
->framebuffer
.nr_samples
) {
2544 constbuf
.user_buffer
= sctx
->b
.sample_locations_1x
;
2547 constbuf
.user_buffer
= sctx
->b
.sample_locations_2x
;
2550 constbuf
.user_buffer
= sctx
->b
.sample_locations_4x
;
2553 constbuf
.user_buffer
= sctx
->b
.sample_locations_8x
;
2556 constbuf
.user_buffer
= sctx
->b
.sample_locations_16x
;
2559 R600_ERR("Requested an invalid number of samples %i.\n",
2560 sctx
->framebuffer
.nr_samples
);
2563 constbuf
.buffer_size
= sctx
->framebuffer
.nr_samples
* 2 * 4;
2564 si_set_rw_buffer(sctx
, SI_PS_CONST_SAMPLE_POSITIONS
, &constbuf
);
2566 si_mark_atom_dirty(sctx
, &sctx
->msaa_sample_locs
.atom
);
2569 sctx
->need_check_render_feedback
= true;
2570 sctx
->do_update_shaders
= true;
2571 sctx
->framebuffer
.do_update_surf_dirtiness
= true;
2574 static void si_emit_framebuffer_state(struct si_context
*sctx
, struct r600_atom
*atom
)
2576 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
2577 struct pipe_framebuffer_state
*state
= &sctx
->framebuffer
.state
;
2578 unsigned i
, nr_cbufs
= state
->nr_cbufs
;
2579 struct r600_texture
*tex
= NULL
;
2580 struct r600_surface
*cb
= NULL
;
2581 unsigned cb_color_info
= 0;
2584 for (i
= 0; i
< nr_cbufs
; i
++) {
2585 uint64_t cb_color_base
, cb_color_fmask
, cb_dcc_base
;
2586 unsigned cb_color_attrib
;
2588 if (!(sctx
->framebuffer
.dirty_cbufs
& (1 << i
)))
2591 cb
= (struct r600_surface
*)state
->cbufs
[i
];
2593 radeon_set_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
2594 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
2598 tex
= (struct r600_texture
*)cb
->base
.texture
;
2599 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
2600 &tex
->resource
, RADEON_USAGE_READWRITE
,
2601 tex
->resource
.b
.b
.nr_samples
> 1 ?
2602 RADEON_PRIO_COLOR_BUFFER_MSAA
:
2603 RADEON_PRIO_COLOR_BUFFER
);
2605 if (tex
->cmask_buffer
&& tex
->cmask_buffer
!= &tex
->resource
) {
2606 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
2607 tex
->cmask_buffer
, RADEON_USAGE_READWRITE
,
2611 if (tex
->dcc_separate_buffer
)
2612 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
2613 tex
->dcc_separate_buffer
,
2614 RADEON_USAGE_READWRITE
,
2617 /* Compute mutable surface parameters. */
2618 cb_color_base
= tex
->resource
.gpu_address
>> 8;
2619 cb_color_fmask
= cb_color_base
;
2621 cb_color_info
= cb
->cb_color_info
| tex
->cb_color_info
;
2622 cb_color_attrib
= cb
->cb_color_attrib
;
2624 if (tex
->fmask
.size
)
2625 cb_color_fmask
= (tex
->resource
.gpu_address
+ tex
->fmask
.offset
) >> 8;
2628 if (tex
->dcc_offset
&& cb
->base
.u
.tex
.level
< tex
->surface
.num_dcc_levels
) {
2629 bool is_msaa_resolve_dst
= state
->cbufs
[0] &&
2630 state
->cbufs
[0]->texture
->nr_samples
> 1 &&
2631 state
->cbufs
[1] == &cb
->base
&&
2632 state
->cbufs
[1]->texture
->nr_samples
<= 1;
2634 if (!is_msaa_resolve_dst
)
2635 cb_color_info
|= S_028C70_DCC_ENABLE(1);
2637 cb_dcc_base
= ((!tex
->dcc_separate_buffer
? tex
->resource
.gpu_address
: 0) +
2638 tex
->dcc_offset
) >> 8;
2641 if (sctx
->b
.chip_class
>= GFX9
) {
2642 struct gfx9_surf_meta_flags meta
;
2644 if (tex
->dcc_offset
)
2645 meta
= tex
->surface
.u
.gfx9
.dcc
;
2647 meta
= tex
->surface
.u
.gfx9
.cmask
;
2649 /* Set mutable surface parameters. */
2650 cb_color_attrib
|= S_028C74_COLOR_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
2651 S_028C74_FMASK_SW_MODE(tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
) |
2652 S_028C74_RB_ALIGNED(meta
.rb_aligned
) |
2653 S_028C74_PIPE_ALIGNED(meta
.pipe_aligned
);
2655 radeon_set_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C, 15);
2656 radeon_emit(cs
, cb_color_base
); /* CB_COLOR0_BASE */
2657 radeon_emit(cs
, cb_color_base
>> 32); /* CB_COLOR0_BASE_EXT */
2658 radeon_emit(cs
, cb
->cb_color_attrib2
); /* CB_COLOR0_ATTRIB2 */
2659 radeon_emit(cs
, cb
->cb_color_view
); /* CB_COLOR0_VIEW */
2660 radeon_emit(cs
, cb_color_info
); /* CB_COLOR0_INFO */
2661 radeon_emit(cs
, cb_color_attrib
); /* CB_COLOR0_ATTRIB */
2662 radeon_emit(cs
, cb
->cb_dcc_control
); /* CB_COLOR0_DCC_CONTROL */
2663 radeon_emit(cs
, tex
->cmask
.base_address_reg
); /* CB_COLOR0_CMASK */
2664 radeon_emit(cs
, tex
->cmask
.base_address_reg
>> 32); /* CB_COLOR0_CMASK_BASE_EXT */
2665 radeon_emit(cs
, cb_color_fmask
); /* CB_COLOR0_FMASK */
2666 radeon_emit(cs
, cb_color_fmask
>> 32); /* CB_COLOR0_FMASK_BASE_EXT */
2667 radeon_emit(cs
, tex
->color_clear_value
[0]); /* CB_COLOR0_CLEAR_WORD0 */
2668 radeon_emit(cs
, tex
->color_clear_value
[1]); /* CB_COLOR0_CLEAR_WORD1 */
2669 radeon_emit(cs
, cb_dcc_base
); /* CB_COLOR0_DCC_BASE */
2670 radeon_emit(cs
, cb_dcc_base
>> 32); /* CB_COLOR0_DCC_BASE_EXT */
2672 radeon_set_context_reg(cs
, R_0287A0_CB_MRT0_EPITCH
+ i
* 4,
2673 S_0287A0_EPITCH(tex
->surface
.u
.gfx9
.surf
.epitch
));
2675 /* Compute mutable surface parameters (SI-CI-VI). */
2676 const struct legacy_surf_level
*level_info
=
2677 &tex
->surface
.u
.legacy
.level
[cb
->base
.u
.tex
.level
];
2678 unsigned pitch_tile_max
, slice_tile_max
, tile_mode_index
;
2679 unsigned cb_color_pitch
, cb_color_slice
, cb_color_fmask_slice
;
2681 cb_color_base
+= level_info
->offset
>> 8;
2683 cb_dcc_base
+= level_info
->dcc_offset
>> 8;
2685 pitch_tile_max
= level_info
->nblk_x
/ 8 - 1;
2686 slice_tile_max
= level_info
->nblk_x
*
2687 level_info
->nblk_y
/ 64 - 1;
2688 tile_mode_index
= si_tile_mode_index(tex
, cb
->base
.u
.tex
.level
, false);
2690 cb_color_attrib
|= S_028C74_TILE_MODE_INDEX(tile_mode_index
);
2691 cb_color_pitch
= S_028C64_TILE_MAX(pitch_tile_max
);
2692 cb_color_slice
= S_028C68_TILE_MAX(slice_tile_max
);
2694 if (tex
->fmask
.size
) {
2695 if (sctx
->b
.chip_class
>= CIK
)
2696 cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(tex
->fmask
.pitch_in_pixels
/ 8 - 1);
2697 cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tex
->fmask
.tile_mode_index
);
2698 cb_color_fmask_slice
= S_028C88_TILE_MAX(tex
->fmask
.slice_tile_max
);
2700 /* This must be set for fast clear to work without FMASK. */
2701 if (sctx
->b
.chip_class
>= CIK
)
2702 cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(pitch_tile_max
);
2703 cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index
);
2704 cb_color_fmask_slice
= S_028C88_TILE_MAX(slice_tile_max
);
2707 radeon_set_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C,
2708 sctx
->b
.chip_class
>= VI
? 14 : 13);
2709 radeon_emit(cs
, cb_color_base
); /* CB_COLOR0_BASE */
2710 radeon_emit(cs
, cb_color_pitch
); /* CB_COLOR0_PITCH */
2711 radeon_emit(cs
, cb_color_slice
); /* CB_COLOR0_SLICE */
2712 radeon_emit(cs
, cb
->cb_color_view
); /* CB_COLOR0_VIEW */
2713 radeon_emit(cs
, cb_color_info
); /* CB_COLOR0_INFO */
2714 radeon_emit(cs
, cb_color_attrib
); /* CB_COLOR0_ATTRIB */
2715 radeon_emit(cs
, cb
->cb_dcc_control
); /* CB_COLOR0_DCC_CONTROL */
2716 radeon_emit(cs
, tex
->cmask
.base_address_reg
); /* CB_COLOR0_CMASK */
2717 radeon_emit(cs
, tex
->cmask
.slice_tile_max
); /* CB_COLOR0_CMASK_SLICE */
2718 radeon_emit(cs
, cb_color_fmask
); /* CB_COLOR0_FMASK */
2719 radeon_emit(cs
, cb_color_fmask_slice
); /* CB_COLOR0_FMASK_SLICE */
2720 radeon_emit(cs
, tex
->color_clear_value
[0]); /* CB_COLOR0_CLEAR_WORD0 */
2721 radeon_emit(cs
, tex
->color_clear_value
[1]); /* CB_COLOR0_CLEAR_WORD1 */
2723 if (sctx
->b
.chip_class
>= VI
) /* R_028C94_CB_COLOR0_DCC_BASE */
2724 radeon_emit(cs
, cb_dcc_base
);
2728 if (sctx
->framebuffer
.dirty_cbufs
& (1 << i
))
2729 radeon_set_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C, 0);
2732 if (state
->zsbuf
&& sctx
->framebuffer
.dirty_zsbuf
) {
2733 struct r600_surface
*zb
= (struct r600_surface
*)state
->zsbuf
;
2734 struct r600_texture
*rtex
= (struct r600_texture
*)zb
->base
.texture
;
2736 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
2737 &rtex
->resource
, RADEON_USAGE_READWRITE
,
2738 zb
->base
.texture
->nr_samples
> 1 ?
2739 RADEON_PRIO_DEPTH_BUFFER_MSAA
:
2740 RADEON_PRIO_DEPTH_BUFFER
);
2742 if (zb
->db_htile_data_base
) {
2743 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
2744 rtex
->htile_buffer
, RADEON_USAGE_READWRITE
,
2748 if (sctx
->b
.chip_class
>= GFX9
) {
2749 radeon_set_context_reg_seq(cs
, R_028014_DB_HTILE_DATA_BASE
, 3);
2750 radeon_emit(cs
, zb
->db_htile_data_base
); /* DB_HTILE_DATA_BASE */
2751 radeon_emit(cs
, zb
->db_htile_data_base
>> 32); /* DB_HTILE_DATA_BASE_HI */
2752 radeon_emit(cs
, zb
->db_depth_size
); /* DB_DEPTH_SIZE */
2754 radeon_set_context_reg_seq(cs
, R_028038_DB_Z_INFO
, 10);
2755 radeon_emit(cs
, zb
->db_z_info
| /* DB_Z_INFO */
2756 S_028038_ZRANGE_PRECISION(rtex
->depth_clear_value
!= 0));
2757 radeon_emit(cs
, zb
->db_stencil_info
); /* DB_STENCIL_INFO */
2758 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_READ_BASE */
2759 radeon_emit(cs
, zb
->db_depth_base
>> 32); /* DB_Z_READ_BASE_HI */
2760 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_READ_BASE */
2761 radeon_emit(cs
, zb
->db_stencil_base
>> 32); /* DB_STENCIL_READ_BASE_HI */
2762 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_WRITE_BASE */
2763 radeon_emit(cs
, zb
->db_depth_base
>> 32); /* DB_Z_WRITE_BASE_HI */
2764 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_WRITE_BASE */
2765 radeon_emit(cs
, zb
->db_stencil_base
>> 32); /* DB_STENCIL_WRITE_BASE_HI */
2767 radeon_set_context_reg_seq(cs
, R_028068_DB_Z_INFO2
, 2);
2768 radeon_emit(cs
, zb
->db_z_info2
); /* DB_Z_INFO2 */
2769 radeon_emit(cs
, zb
->db_stencil_info2
); /* DB_STENCIL_INFO2 */
2771 radeon_set_context_reg(cs
, R_028014_DB_HTILE_DATA_BASE
, zb
->db_htile_data_base
);
2773 radeon_set_context_reg_seq(cs
, R_02803C_DB_DEPTH_INFO
, 9);
2774 radeon_emit(cs
, zb
->db_depth_info
); /* DB_DEPTH_INFO */
2775 radeon_emit(cs
, zb
->db_z_info
| /* DB_Z_INFO */
2776 S_028040_ZRANGE_PRECISION(rtex
->depth_clear_value
!= 0));
2777 radeon_emit(cs
, zb
->db_stencil_info
); /* DB_STENCIL_INFO */
2778 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_READ_BASE */
2779 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_READ_BASE */
2780 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_WRITE_BASE */
2781 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_WRITE_BASE */
2782 radeon_emit(cs
, zb
->db_depth_size
); /* DB_DEPTH_SIZE */
2783 radeon_emit(cs
, zb
->db_depth_slice
); /* DB_DEPTH_SLICE */
2786 radeon_set_context_reg_seq(cs
, R_028028_DB_STENCIL_CLEAR
, 2);
2787 radeon_emit(cs
, rtex
->stencil_clear_value
); /* R_028028_DB_STENCIL_CLEAR */
2788 radeon_emit(cs
, fui(rtex
->depth_clear_value
)); /* R_02802C_DB_DEPTH_CLEAR */
2790 radeon_set_context_reg(cs
, R_028008_DB_DEPTH_VIEW
, zb
->db_depth_view
);
2791 radeon_set_context_reg(cs
, R_028ABC_DB_HTILE_SURFACE
, zb
->db_htile_surface
);
2792 } else if (sctx
->framebuffer
.dirty_zsbuf
) {
2793 if (sctx
->b
.chip_class
>= GFX9
)
2794 radeon_set_context_reg_seq(cs
, R_028038_DB_Z_INFO
, 2);
2796 radeon_set_context_reg_seq(cs
, R_028040_DB_Z_INFO
, 2);
2798 radeon_emit(cs
, S_028040_FORMAT(V_028040_Z_INVALID
)); /* DB_Z_INFO */
2799 radeon_emit(cs
, S_028044_FORMAT(V_028044_STENCIL_INVALID
)); /* DB_STENCIL_INFO */
2802 /* Framebuffer dimensions. */
2803 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2804 radeon_set_context_reg(cs
, R_028208_PA_SC_WINDOW_SCISSOR_BR
,
2805 S_028208_BR_X(state
->width
) | S_028208_BR_Y(state
->height
));
2807 sctx
->framebuffer
.dirty_cbufs
= 0;
2808 sctx
->framebuffer
.dirty_zsbuf
= false;
2811 static void si_emit_msaa_sample_locs(struct si_context
*sctx
,
2812 struct r600_atom
*atom
)
2814 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
2815 unsigned nr_samples
= sctx
->framebuffer
.nr_samples
;
2817 /* Smoothing (only possible with nr_samples == 1) uses the same
2818 * sample locations as the MSAA it simulates.
2820 if (nr_samples
<= 1 && sctx
->smoothing_enabled
)
2821 nr_samples
= SI_NUM_SMOOTH_AA_SAMPLES
;
2823 /* On Polaris, the small primitive filter uses the sample locations
2824 * even when MSAA is off, so we need to make sure they're set to 0.
2826 if (sctx
->b
.family
>= CHIP_POLARIS10
)
2827 nr_samples
= MAX2(nr_samples
, 1);
2829 if (nr_samples
>= 1 &&
2830 (nr_samples
!= sctx
->msaa_sample_locs
.nr_samples
)) {
2831 sctx
->msaa_sample_locs
.nr_samples
= nr_samples
;
2832 cayman_emit_msaa_sample_locs(cs
, nr_samples
);
2835 if (sctx
->b
.family
>= CHIP_POLARIS10
) {
2836 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
2837 unsigned small_prim_filter_cntl
=
2838 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
2839 S_028830_LINE_FILTER_DISABLE(sctx
->b
.chip_class
== VI
); /* line bug */
2841 /* The alternative of setting sample locations to 0 would
2842 * require a DB flush to avoid Z errors, see
2843 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
2845 if (sctx
->framebuffer
.nr_samples
> 1 && rs
&& !rs
->multisample_enable
)
2846 small_prim_filter_cntl
&= C_028830_SMALL_PRIM_FILTER_ENABLE
;
2848 radeon_set_context_reg(cs
, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL
,
2849 small_prim_filter_cntl
);
2853 static void si_emit_msaa_config(struct si_context
*sctx
, struct r600_atom
*atom
)
2855 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
2856 unsigned num_tile_pipes
= sctx
->screen
->b
.info
.num_tile_pipes
;
2857 /* 33% faster rendering to linear color buffers */
2858 bool dst_is_linear
= sctx
->framebuffer
.any_dst_linear
;
2859 unsigned sc_mode_cntl_1
=
2860 S_028A4C_WALK_SIZE(dst_is_linear
) |
2861 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear
) |
2862 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes
== 2 ? 2 : 3) |
2864 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
2865 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
2866 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
2867 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
2868 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
2869 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
2871 cayman_emit_msaa_config(cs
, sctx
->framebuffer
.nr_samples
,
2872 sctx
->ps_iter_samples
,
2873 sctx
->smoothing_enabled
? SI_NUM_SMOOTH_AA_SAMPLES
: 0,
2877 static void si_set_min_samples(struct pipe_context
*ctx
, unsigned min_samples
)
2879 struct si_context
*sctx
= (struct si_context
*)ctx
;
2881 if (sctx
->ps_iter_samples
== min_samples
)
2884 sctx
->ps_iter_samples
= min_samples
;
2885 sctx
->do_update_shaders
= true;
2887 if (sctx
->framebuffer
.nr_samples
> 1)
2888 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
2896 * Build the sampler view descriptor for a buffer texture.
2897 * @param state 256-bit descriptor; only the high 128 bits are filled in
2900 si_make_buffer_descriptor(struct si_screen
*screen
, struct r600_resource
*buf
,
2901 enum pipe_format format
,
2902 unsigned offset
, unsigned size
,
2905 const struct util_format_description
*desc
;
2908 unsigned num_records
;
2909 unsigned num_format
, data_format
;
2911 desc
= util_format_description(format
);
2912 first_non_void
= util_format_get_first_non_void_channel(format
);
2913 stride
= desc
->block
.bits
/ 8;
2914 num_format
= si_translate_buffer_numformat(&screen
->b
.b
, desc
, first_non_void
);
2915 data_format
= si_translate_buffer_dataformat(&screen
->b
.b
, desc
, first_non_void
);
2917 num_records
= size
/ stride
;
2918 num_records
= MIN2(num_records
, (buf
->b
.b
.width0
- offset
) / stride
);
2920 if (screen
->b
.chip_class
== VI
)
2921 num_records
*= stride
;
2924 state
[5] = S_008F04_STRIDE(stride
);
2925 state
[6] = num_records
;
2926 state
[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc
->swizzle
[0])) |
2927 S_008F0C_DST_SEL_Y(si_map_swizzle(desc
->swizzle
[1])) |
2928 S_008F0C_DST_SEL_Z(si_map_swizzle(desc
->swizzle
[2])) |
2929 S_008F0C_DST_SEL_W(si_map_swizzle(desc
->swizzle
[3])) |
2930 S_008F0C_NUM_FORMAT(num_format
) |
2931 S_008F0C_DATA_FORMAT(data_format
);
2934 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle
[4])
2936 unsigned bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
2938 if (swizzle
[3] == PIPE_SWIZZLE_X
) {
2939 /* For the pre-defined border color values (white, opaque
2940 * black, transparent black), the only thing that matters is
2941 * that the alpha channel winds up in the correct place
2942 * (because the RGB channels are all the same) so either of
2943 * these enumerations will work.
2945 if (swizzle
[2] == PIPE_SWIZZLE_Y
)
2946 bc_swizzle
= V_008F20_BC_SWIZZLE_WZYX
;
2948 bc_swizzle
= V_008F20_BC_SWIZZLE_WXYZ
;
2949 } else if (swizzle
[0] == PIPE_SWIZZLE_X
) {
2950 if (swizzle
[1] == PIPE_SWIZZLE_Y
)
2951 bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
2953 bc_swizzle
= V_008F20_BC_SWIZZLE_XWYZ
;
2954 } else if (swizzle
[1] == PIPE_SWIZZLE_X
) {
2955 bc_swizzle
= V_008F20_BC_SWIZZLE_YXWZ
;
2956 } else if (swizzle
[2] == PIPE_SWIZZLE_X
) {
2957 bc_swizzle
= V_008F20_BC_SWIZZLE_ZYXW
;
2964 * Build the sampler view descriptor for a texture.
2967 si_make_texture_descriptor(struct si_screen
*screen
,
2968 struct r600_texture
*tex
,
2970 enum pipe_texture_target target
,
2971 enum pipe_format pipe_format
,
2972 const unsigned char state_swizzle
[4],
2973 unsigned first_level
, unsigned last_level
,
2974 unsigned first_layer
, unsigned last_layer
,
2975 unsigned width
, unsigned height
, unsigned depth
,
2977 uint32_t *fmask_state
)
2979 struct pipe_resource
*res
= &tex
->resource
.b
.b
;
2980 const struct util_format_description
*base_desc
, *desc
;
2981 unsigned char swizzle
[4];
2983 unsigned num_format
, data_format
, type
;
2986 desc
= util_format_description(pipe_format
);
2987 base_desc
= util_format_description(res
->format
);
2989 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
) {
2990 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
2991 const unsigned char swizzle_yyyy
[4] = {1, 1, 1, 1};
2992 const unsigned char swizzle_wwww
[4] = {3, 3, 3, 3};
2994 switch (pipe_format
) {
2995 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
2996 case PIPE_FORMAT_X32_S8X24_UINT
:
2997 case PIPE_FORMAT_X8Z24_UNORM
:
2998 util_format_compose_swizzles(swizzle_yyyy
, state_swizzle
, swizzle
);
3000 case PIPE_FORMAT_X24S8_UINT
:
3002 * X24S8 is implemented as an 8_8_8_8 data format, to
3003 * fix texture gathers. This affects at least
3004 * GL45-CTS.texture_cube_map_array.sampling on VI.
3006 util_format_compose_swizzles(swizzle_wwww
, state_swizzle
, swizzle
);
3009 util_format_compose_swizzles(swizzle_xxxx
, state_swizzle
, swizzle
);
3012 util_format_compose_swizzles(desc
->swizzle
, state_swizzle
, swizzle
);
3015 first_non_void
= util_format_get_first_non_void_channel(pipe_format
);
3017 switch (pipe_format
) {
3018 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
3019 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3022 if (first_non_void
< 0) {
3023 if (util_format_is_compressed(pipe_format
)) {
3024 switch (pipe_format
) {
3025 case PIPE_FORMAT_DXT1_SRGB
:
3026 case PIPE_FORMAT_DXT1_SRGBA
:
3027 case PIPE_FORMAT_DXT3_SRGBA
:
3028 case PIPE_FORMAT_DXT5_SRGBA
:
3029 case PIPE_FORMAT_BPTC_SRGBA
:
3030 case PIPE_FORMAT_ETC2_SRGB8
:
3031 case PIPE_FORMAT_ETC2_SRGB8A1
:
3032 case PIPE_FORMAT_ETC2_SRGBA8
:
3033 num_format
= V_008F14_IMG_NUM_FORMAT_SRGB
;
3035 case PIPE_FORMAT_RGTC1_SNORM
:
3036 case PIPE_FORMAT_LATC1_SNORM
:
3037 case PIPE_FORMAT_RGTC2_SNORM
:
3038 case PIPE_FORMAT_LATC2_SNORM
:
3039 case PIPE_FORMAT_ETC2_R11_SNORM
:
3040 case PIPE_FORMAT_ETC2_RG11_SNORM
:
3041 /* implies float, so use SNORM/UNORM to determine
3042 whether data is signed or not */
3043 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
3044 num_format
= V_008F14_IMG_NUM_FORMAT_SNORM
;
3047 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3050 } else if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
3051 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3053 num_format
= V_008F14_IMG_NUM_FORMAT_FLOAT
;
3055 } else if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
) {
3056 num_format
= V_008F14_IMG_NUM_FORMAT_SRGB
;
3058 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3060 switch (desc
->channel
[first_non_void
].type
) {
3061 case UTIL_FORMAT_TYPE_FLOAT
:
3062 num_format
= V_008F14_IMG_NUM_FORMAT_FLOAT
;
3064 case UTIL_FORMAT_TYPE_SIGNED
:
3065 if (desc
->channel
[first_non_void
].normalized
)
3066 num_format
= V_008F14_IMG_NUM_FORMAT_SNORM
;
3067 else if (desc
->channel
[first_non_void
].pure_integer
)
3068 num_format
= V_008F14_IMG_NUM_FORMAT_SINT
;
3070 num_format
= V_008F14_IMG_NUM_FORMAT_SSCALED
;
3072 case UTIL_FORMAT_TYPE_UNSIGNED
:
3073 if (desc
->channel
[first_non_void
].normalized
)
3074 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3075 else if (desc
->channel
[first_non_void
].pure_integer
)
3076 num_format
= V_008F14_IMG_NUM_FORMAT_UINT
;
3078 num_format
= V_008F14_IMG_NUM_FORMAT_USCALED
;
3083 data_format
= si_translate_texformat(&screen
->b
.b
, pipe_format
, desc
, first_non_void
);
3084 if (data_format
== ~0) {
3088 /* Enable clamping for UNORM depth formats promoted to Z32F. */
3089 if (screen
->b
.chip_class
>= GFX9
&&
3090 util_format_has_depth(desc
) &&
3091 num_format
== V_008F14_IMG_NUM_FORMAT_FLOAT
&&
3092 util_get_depth_format_type(base_desc
) != UTIL_FORMAT_TYPE_FLOAT
) {
3093 /* NUM_FORMAT=FLOAT and DATA_FORMAT=24_8 means "clamp to [0,1]". */
3094 data_format
= V_008F14_IMG_DATA_FORMAT_24_8
;
3098 (res
->target
== PIPE_TEXTURE_CUBE
||
3099 res
->target
== PIPE_TEXTURE_CUBE_ARRAY
||
3100 res
->target
== PIPE_TEXTURE_3D
)) {
3101 /* For the purpose of shader images, treat cube maps and 3D
3102 * textures as 2D arrays. For 3D textures, the address
3103 * calculations for mipmaps are different, so we rely on the
3104 * caller to effectively disable mipmaps.
3106 type
= V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
3108 assert(res
->target
!= PIPE_TEXTURE_3D
|| (first_level
== 0 && last_level
== 0));
3110 type
= si_tex_dim(screen
, tex
, target
, res
->nr_samples
);
3113 if (type
== V_008F1C_SQ_RSRC_IMG_1D_ARRAY
) {
3115 depth
= res
->array_size
;
3116 } else if (type
== V_008F1C_SQ_RSRC_IMG_2D_ARRAY
||
3117 type
== V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
) {
3118 if (sampler
|| res
->target
!= PIPE_TEXTURE_3D
)
3119 depth
= res
->array_size
;
3120 } else if (type
== V_008F1C_SQ_RSRC_IMG_CUBE
)
3121 depth
= res
->array_size
/ 6;
3124 state
[1] = (S_008F14_DATA_FORMAT_GFX6(data_format
) |
3125 S_008F14_NUM_FORMAT_GFX6(num_format
));
3126 state
[2] = (S_008F18_WIDTH(width
- 1) |
3127 S_008F18_HEIGHT(height
- 1) |
3128 S_008F18_PERF_MOD(4));
3129 state
[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle
[0])) |
3130 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle
[1])) |
3131 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle
[2])) |
3132 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle
[3])) |
3133 S_008F1C_BASE_LEVEL(res
->nr_samples
> 1 ?
3135 S_008F1C_LAST_LEVEL(res
->nr_samples
> 1 ?
3136 util_logbase2(res
->nr_samples
) :
3138 S_008F1C_TYPE(type
));
3140 state
[5] = S_008F24_BASE_ARRAY(first_layer
);
3144 if (screen
->b
.chip_class
>= GFX9
) {
3145 unsigned bc_swizzle
= gfx9_border_color_swizzle(desc
->swizzle
);
3147 /* Depth is the the last accessible layer on Gfx9.
3148 * The hw doesn't need to know the total number of layers.
3150 if (type
== V_008F1C_SQ_RSRC_IMG_3D
)
3151 state
[4] |= S_008F20_DEPTH(depth
- 1);
3153 state
[4] |= S_008F20_DEPTH(last_layer
);
3155 state
[4] |= S_008F20_BC_SWIZZLE(bc_swizzle
);
3156 state
[5] |= S_008F24_MAX_MIP(res
->nr_samples
> 1 ?
3157 util_logbase2(res
->nr_samples
) :
3158 tex
->resource
.b
.b
.last_level
);
3160 state
[3] |= S_008F1C_POW2_PAD(res
->last_level
> 0);
3161 state
[4] |= S_008F20_DEPTH(depth
- 1);
3162 state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
3165 if (tex
->dcc_offset
) {
3166 unsigned swap
= r600_translate_colorswap(pipe_format
, false);
3168 state
[6] = S_008F28_ALPHA_IS_ON_MSB(swap
<= 1);
3170 /* The last dword is unused by hw. The shader uses it to clear
3171 * bits in the first dword of sampler state.
3173 if (screen
->b
.chip_class
<= CIK
&& res
->nr_samples
<= 1) {
3174 if (first_level
== last_level
)
3175 state
[7] = C_008F30_MAX_ANISO_RATIO
;
3177 state
[7] = 0xffffffff;
3181 /* Initialize the sampler view for FMASK. */
3182 if (tex
->fmask
.size
) {
3183 uint32_t data_format
, num_format
;
3185 va
= tex
->resource
.gpu_address
+ tex
->fmask
.offset
;
3187 if (screen
->b
.chip_class
>= GFX9
) {
3188 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK
;
3189 switch (res
->nr_samples
) {
3191 num_format
= V_008F14_IMG_FMASK_8_2_2
;
3194 num_format
= V_008F14_IMG_FMASK_8_4_4
;
3197 num_format
= V_008F14_IMG_FMASK_32_8_8
;
3203 switch (res
->nr_samples
) {
3205 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2
;
3208 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4
;
3211 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8
;
3216 num_format
= V_008F14_IMG_NUM_FORMAT_UINT
;
3219 fmask_state
[0] = va
>> 8;
3220 fmask_state
[1] = S_008F14_BASE_ADDRESS_HI(va
>> 40) |
3221 S_008F14_DATA_FORMAT_GFX6(data_format
) |
3222 S_008F14_NUM_FORMAT_GFX6(num_format
);
3223 fmask_state
[2] = S_008F18_WIDTH(width
- 1) |
3224 S_008F18_HEIGHT(height
- 1);
3225 fmask_state
[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X
) |
3226 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X
) |
3227 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X
) |
3228 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X
) |
3229 S_008F1C_TYPE(si_tex_dim(screen
, tex
, target
, 0));
3231 fmask_state
[5] = S_008F24_BASE_ARRAY(first_layer
);
3235 if (screen
->b
.chip_class
>= GFX9
) {
3236 fmask_state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
);
3237 fmask_state
[4] |= S_008F20_DEPTH(last_layer
) |
3238 S_008F20_PITCH_GFX9(tex
->surface
.u
.gfx9
.fmask
.epitch
);
3239 fmask_state
[5] |= S_008F24_META_PIPE_ALIGNED(tex
->surface
.u
.gfx9
.cmask
.pipe_aligned
) |
3240 S_008F24_META_RB_ALIGNED(tex
->surface
.u
.gfx9
.cmask
.rb_aligned
);
3242 fmask_state
[3] |= S_008F1C_TILING_INDEX(tex
->fmask
.tile_mode_index
);
3243 fmask_state
[4] |= S_008F20_DEPTH(depth
- 1) |
3244 S_008F20_PITCH_GFX6(tex
->fmask
.pitch_in_pixels
- 1);
3245 fmask_state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
3251 * Create a sampler view.
3253 * @param ctx context
3254 * @param texture texture
3255 * @param state sampler view template
3256 * @param width0 width0 override (for compressed textures as int)
3257 * @param height0 height0 override (for compressed textures as int)
3258 * @param force_level set the base address to the level (for compressed textures)
3260 struct pipe_sampler_view
*
3261 si_create_sampler_view_custom(struct pipe_context
*ctx
,
3262 struct pipe_resource
*texture
,
3263 const struct pipe_sampler_view
*state
,
3264 unsigned width0
, unsigned height0
,
3265 unsigned force_level
)
3267 struct si_context
*sctx
= (struct si_context
*)ctx
;
3268 struct si_sampler_view
*view
= CALLOC_STRUCT(si_sampler_view
);
3269 struct r600_texture
*tmp
= (struct r600_texture
*)texture
;
3270 unsigned base_level
, first_level
, last_level
;
3271 unsigned char state_swizzle
[4];
3272 unsigned height
, depth
, width
;
3273 unsigned last_layer
= state
->u
.tex
.last_layer
;
3274 enum pipe_format pipe_format
;
3275 const struct legacy_surf_level
*surflevel
;
3280 /* initialize base object */
3281 view
->base
= *state
;
3282 view
->base
.texture
= NULL
;
3283 view
->base
.reference
.count
= 1;
3284 view
->base
.context
= ctx
;
3287 pipe_resource_reference(&view
->base
.texture
, texture
);
3289 if (state
->format
== PIPE_FORMAT_X24S8_UINT
||
3290 state
->format
== PIPE_FORMAT_S8X24_UINT
||
3291 state
->format
== PIPE_FORMAT_X32_S8X24_UINT
||
3292 state
->format
== PIPE_FORMAT_S8_UINT
)
3293 view
->is_stencil_sampler
= true;
3295 /* Buffer resource. */
3296 if (texture
->target
== PIPE_BUFFER
) {
3297 si_make_buffer_descriptor(sctx
->screen
,
3298 (struct r600_resource
*)texture
,
3300 state
->u
.buf
.offset
,
3306 state_swizzle
[0] = state
->swizzle_r
;
3307 state_swizzle
[1] = state
->swizzle_g
;
3308 state_swizzle
[2] = state
->swizzle_b
;
3309 state_swizzle
[3] = state
->swizzle_a
;
3312 first_level
= state
->u
.tex
.first_level
;
3313 last_level
= state
->u
.tex
.last_level
;
3316 depth
= texture
->depth0
;
3319 assert(force_level
== first_level
&&
3320 force_level
== last_level
);
3321 base_level
= force_level
;
3324 width
= u_minify(width
, force_level
);
3325 height
= u_minify(height
, force_level
);
3326 depth
= u_minify(depth
, force_level
);
3329 /* This is not needed if state trackers set last_layer correctly. */
3330 if (state
->target
== PIPE_TEXTURE_1D
||
3331 state
->target
== PIPE_TEXTURE_2D
||
3332 state
->target
== PIPE_TEXTURE_RECT
||
3333 state
->target
== PIPE_TEXTURE_CUBE
)
3334 last_layer
= state
->u
.tex
.first_layer
;
3336 /* Texturing with separate depth and stencil. */
3337 pipe_format
= state
->format
;
3339 /* Depth/stencil texturing sometimes needs separate texture. */
3340 if (tmp
->is_depth
&& !r600_can_sample_zs(tmp
, view
->is_stencil_sampler
)) {
3341 if (!tmp
->flushed_depth_texture
&&
3342 !r600_init_flushed_depth_texture(ctx
, texture
, NULL
)) {
3343 pipe_resource_reference(&view
->base
.texture
, NULL
);
3348 assert(tmp
->flushed_depth_texture
);
3350 /* Override format for the case where the flushed texture
3351 * contains only Z or only S.
3353 if (tmp
->flushed_depth_texture
->resource
.b
.b
.format
!= tmp
->resource
.b
.b
.format
)
3354 pipe_format
= tmp
->flushed_depth_texture
->resource
.b
.b
.format
;
3356 tmp
= tmp
->flushed_depth_texture
;
3359 surflevel
= tmp
->surface
.u
.legacy
.level
;
3361 if (tmp
->db_compatible
) {
3362 if (!view
->is_stencil_sampler
)
3363 pipe_format
= tmp
->db_render_format
;
3365 switch (pipe_format
) {
3366 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
3367 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
3369 case PIPE_FORMAT_X8Z24_UNORM
:
3370 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
3371 /* Z24 is always stored like this for DB
3374 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
3376 case PIPE_FORMAT_X24S8_UINT
:
3377 case PIPE_FORMAT_S8X24_UINT
:
3378 case PIPE_FORMAT_X32_S8X24_UINT
:
3379 pipe_format
= PIPE_FORMAT_S8_UINT
;
3380 surflevel
= tmp
->surface
.u
.legacy
.stencil_level
;
3386 vi_dcc_disable_if_incompatible_format(&sctx
->b
, texture
,
3387 state
->u
.tex
.first_level
,
3390 si_make_texture_descriptor(sctx
->screen
, tmp
, true,
3391 state
->target
, pipe_format
, state_swizzle
,
3392 first_level
, last_level
,
3393 state
->u
.tex
.first_layer
, last_layer
,
3394 width
, height
, depth
,
3395 view
->state
, view
->fmask_state
);
3397 view
->base_level_info
= &surflevel
[base_level
];
3398 view
->base_level
= base_level
;
3399 view
->block_width
= util_format_get_blockwidth(pipe_format
);
3403 static struct pipe_sampler_view
*
3404 si_create_sampler_view(struct pipe_context
*ctx
,
3405 struct pipe_resource
*texture
,
3406 const struct pipe_sampler_view
*state
)
3408 return si_create_sampler_view_custom(ctx
, texture
, state
,
3409 texture
? texture
->width0
: 0,
3410 texture
? texture
->height0
: 0, 0);
3413 static void si_sampler_view_destroy(struct pipe_context
*ctx
,
3414 struct pipe_sampler_view
*state
)
3416 struct si_sampler_view
*view
= (struct si_sampler_view
*)state
;
3418 pipe_resource_reference(&state
->texture
, NULL
);
3422 static bool wrap_mode_uses_border_color(unsigned wrap
, bool linear_filter
)
3424 return wrap
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
||
3425 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
||
3427 (wrap
== PIPE_TEX_WRAP_CLAMP
||
3428 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP
));
3431 static bool sampler_state_needs_border_color(const struct pipe_sampler_state
*state
)
3433 bool linear_filter
= state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
||
3434 state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
;
3436 return (state
->border_color
.ui
[0] || state
->border_color
.ui
[1] ||
3437 state
->border_color
.ui
[2] || state
->border_color
.ui
[3]) &&
3438 (wrap_mode_uses_border_color(state
->wrap_s
, linear_filter
) ||
3439 wrap_mode_uses_border_color(state
->wrap_t
, linear_filter
) ||
3440 wrap_mode_uses_border_color(state
->wrap_r
, linear_filter
));
3443 static void *si_create_sampler_state(struct pipe_context
*ctx
,
3444 const struct pipe_sampler_state
*state
)
3446 struct si_context
*sctx
= (struct si_context
*)ctx
;
3447 struct r600_common_screen
*rscreen
= sctx
->b
.screen
;
3448 struct si_sampler_state
*rstate
= CALLOC_STRUCT(si_sampler_state
);
3449 unsigned border_color_type
, border_color_index
= 0;
3450 unsigned max_aniso
= rscreen
->force_aniso
>= 0 ? rscreen
->force_aniso
3451 : state
->max_anisotropy
;
3452 unsigned max_aniso_ratio
= r600_tex_aniso_filter(max_aniso
);
3458 if (!sampler_state_needs_border_color(state
))
3459 border_color_type
= V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
;
3460 else if (state
->border_color
.f
[0] == 0 &&
3461 state
->border_color
.f
[1] == 0 &&
3462 state
->border_color
.f
[2] == 0 &&
3463 state
->border_color
.f
[3] == 0)
3464 border_color_type
= V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
;
3465 else if (state
->border_color
.f
[0] == 0 &&
3466 state
->border_color
.f
[1] == 0 &&
3467 state
->border_color
.f
[2] == 0 &&
3468 state
->border_color
.f
[3] == 1)
3469 border_color_type
= V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK
;
3470 else if (state
->border_color
.f
[0] == 1 &&
3471 state
->border_color
.f
[1] == 1 &&
3472 state
->border_color
.f
[2] == 1 &&
3473 state
->border_color
.f
[3] == 1)
3474 border_color_type
= V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE
;
3478 border_color_type
= V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER
;
3480 /* Check if the border has been uploaded already. */
3481 for (i
= 0; i
< sctx
->border_color_count
; i
++)
3482 if (memcmp(&sctx
->border_color_table
[i
], &state
->border_color
,
3483 sizeof(state
->border_color
)) == 0)
3486 if (i
>= SI_MAX_BORDER_COLORS
) {
3487 /* Getting 4096 unique border colors is very unlikely. */
3488 fprintf(stderr
, "radeonsi: The border color table is full. "
3489 "Any new border colors will be just black. "
3490 "Please file a bug.\n");
3491 border_color_type
= V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
;
3493 if (i
== sctx
->border_color_count
) {
3494 /* Upload a new border color. */
3495 memcpy(&sctx
->border_color_table
[i
], &state
->border_color
,
3496 sizeof(state
->border_color
));
3497 util_memcpy_cpu_to_le32(&sctx
->border_color_map
[i
],
3498 &state
->border_color
,
3499 sizeof(state
->border_color
));
3500 sctx
->border_color_count
++;
3503 border_color_index
= i
;
3508 rstate
->magic
= SI_SAMPLER_STATE_MAGIC
;
3510 rstate
->val
[0] = (S_008F30_CLAMP_X(si_tex_wrap(state
->wrap_s
)) |
3511 S_008F30_CLAMP_Y(si_tex_wrap(state
->wrap_t
)) |
3512 S_008F30_CLAMP_Z(si_tex_wrap(state
->wrap_r
)) |
3513 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio
) |
3514 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state
->compare_func
)) |
3515 S_008F30_FORCE_UNNORMALIZED(!state
->normalized_coords
) |
3516 S_008F30_ANISO_THRESHOLD(max_aniso_ratio
>> 1) |
3517 S_008F30_ANISO_BIAS(max_aniso_ratio
) |
3518 S_008F30_DISABLE_CUBE_WRAP(!state
->seamless_cube_map
) |
3519 S_008F30_COMPAT_MODE(sctx
->b
.chip_class
>= VI
));
3520 rstate
->val
[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 8)) |
3521 S_008F34_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 8)) |
3522 S_008F34_PERF_MIP(max_aniso_ratio
? max_aniso_ratio
+ 6 : 0));
3523 rstate
->val
[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 8)) |
3524 S_008F38_XY_MAG_FILTER(eg_tex_filter(state
->mag_img_filter
, max_aniso
)) |
3525 S_008F38_XY_MIN_FILTER(eg_tex_filter(state
->min_img_filter
, max_aniso
)) |
3526 S_008F38_MIP_FILTER(si_tex_mipfilter(state
->min_mip_filter
)) |
3527 S_008F38_MIP_POINT_PRECLAMP(1) |
3528 S_008F38_DISABLE_LSB_CEIL(sctx
->b
.chip_class
<= VI
) |
3529 S_008F38_FILTER_PREC_FIX(1) |
3530 S_008F38_ANISO_OVERRIDE(sctx
->b
.chip_class
>= VI
));
3531 rstate
->val
[3] = S_008F3C_BORDER_COLOR_PTR(border_color_index
) |
3532 S_008F3C_BORDER_COLOR_TYPE(border_color_type
);
3536 static void si_set_sample_mask(struct pipe_context
*ctx
, unsigned sample_mask
)
3538 struct si_context
*sctx
= (struct si_context
*)ctx
;
3540 if (sctx
->sample_mask
.sample_mask
== (uint16_t)sample_mask
)
3543 sctx
->sample_mask
.sample_mask
= sample_mask
;
3544 si_mark_atom_dirty(sctx
, &sctx
->sample_mask
.atom
);
3547 static void si_emit_sample_mask(struct si_context
*sctx
, struct r600_atom
*atom
)
3549 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
3550 unsigned mask
= sctx
->sample_mask
.sample_mask
;
3552 /* Needed for line and polygon smoothing as well as for the Polaris
3553 * small primitive filter. We expect the state tracker to take care of
3556 assert(mask
== 0xffff || sctx
->framebuffer
.nr_samples
> 1 ||
3557 (mask
& 1 && sctx
->blitter
->running
));
3559 radeon_set_context_reg_seq(cs
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
3560 radeon_emit(cs
, mask
| (mask
<< 16));
3561 radeon_emit(cs
, mask
| (mask
<< 16));
3564 static void si_delete_sampler_state(struct pipe_context
*ctx
, void *state
)
3567 struct si_sampler_state
*s
= state
;
3569 assert(s
->magic
== SI_SAMPLER_STATE_MAGIC
);
3576 * Vertex elements & buffers
3579 static void *si_create_vertex_elements(struct pipe_context
*ctx
,
3581 const struct pipe_vertex_element
*elements
)
3583 struct si_screen
*sscreen
= (struct si_screen
*)ctx
->screen
;
3584 struct si_vertex_element
*v
= CALLOC_STRUCT(si_vertex_element
);
3585 bool used
[SI_NUM_VERTEX_BUFFERS
] = {};
3588 assert(count
<= SI_MAX_ATTRIBS
);
3593 v
->desc_list_byte_size
= align(count
* 16, SI_CPDMA_ALIGNMENT
);
3595 for (i
= 0; i
< count
; ++i
) {
3596 const struct util_format_description
*desc
;
3597 const struct util_format_channel_description
*channel
;
3598 unsigned data_format
, num_format
;
3600 unsigned vbo_index
= elements
[i
].vertex_buffer_index
;
3601 unsigned char swizzle
[4];
3603 if (vbo_index
>= SI_NUM_VERTEX_BUFFERS
) {
3608 if (!used
[vbo_index
]) {
3609 v
->first_vb_use_mask
|= 1 << i
;
3610 used
[vbo_index
] = true;
3613 desc
= util_format_description(elements
[i
].src_format
);
3614 first_non_void
= util_format_get_first_non_void_channel(elements
[i
].src_format
);
3615 data_format
= si_translate_buffer_dataformat(ctx
->screen
, desc
, first_non_void
);
3616 num_format
= si_translate_buffer_numformat(ctx
->screen
, desc
, first_non_void
);
3617 channel
= first_non_void
>= 0 ? &desc
->channel
[first_non_void
] : NULL
;
3618 memcpy(swizzle
, desc
->swizzle
, sizeof(swizzle
));
3620 v
->format_size
[i
] = desc
->block
.bits
/ 8;
3622 /* The hardware always treats the 2-bit alpha channel as
3623 * unsigned, so a shader workaround is needed. The affected
3624 * chips are VI and older except Stoney (GFX8.1).
3626 if (data_format
== V_008F0C_BUF_DATA_FORMAT_2_10_10_10
&&
3627 sscreen
->b
.chip_class
<= VI
&&
3628 sscreen
->b
.family
!= CHIP_STONEY
) {
3629 if (num_format
== V_008F0C_BUF_NUM_FORMAT_SNORM
) {
3630 v
->fix_fetch
[i
] = SI_FIX_FETCH_A2_SNORM
;
3631 } else if (num_format
== V_008F0C_BUF_NUM_FORMAT_SSCALED
) {
3632 v
->fix_fetch
[i
] = SI_FIX_FETCH_A2_SSCALED
;
3633 } else if (num_format
== V_008F0C_BUF_NUM_FORMAT_SINT
) {
3634 /* This isn't actually used in OpenGL. */
3635 v
->fix_fetch
[i
] = SI_FIX_FETCH_A2_SINT
;
3637 } else if (channel
&& channel
->type
== UTIL_FORMAT_TYPE_FIXED
) {
3638 if (desc
->swizzle
[3] == PIPE_SWIZZLE_1
)
3639 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBX_32_FIXED
;
3641 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_32_FIXED
;
3642 } else if (channel
&& channel
->size
== 32 && !channel
->pure_integer
) {
3643 if (channel
->type
== UTIL_FORMAT_TYPE_SIGNED
) {
3644 if (channel
->normalized
) {
3645 if (desc
->swizzle
[3] == PIPE_SWIZZLE_1
)
3646 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBX_32_SNORM
;
3648 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_32_SNORM
;
3650 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_32_SSCALED
;
3652 } else if (channel
->type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
3653 if (channel
->normalized
) {
3654 if (desc
->swizzle
[3] == PIPE_SWIZZLE_1
)
3655 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBX_32_UNORM
;
3657 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_32_UNORM
;
3659 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_32_USCALED
;
3662 } else if (channel
&& channel
->size
== 64 &&
3663 channel
->type
== UTIL_FORMAT_TYPE_FLOAT
) {
3664 switch (desc
->nr_channels
) {
3667 v
->fix_fetch
[i
] = SI_FIX_FETCH_RG_64_FLOAT
;
3668 swizzle
[0] = PIPE_SWIZZLE_X
;
3669 swizzle
[1] = PIPE_SWIZZLE_Y
;
3670 swizzle
[2] = desc
->nr_channels
== 2 ? PIPE_SWIZZLE_Z
: PIPE_SWIZZLE_0
;
3671 swizzle
[3] = desc
->nr_channels
== 2 ? PIPE_SWIZZLE_W
: PIPE_SWIZZLE_0
;
3674 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGB_64_FLOAT
;
3675 swizzle
[0] = PIPE_SWIZZLE_X
; /* 3 loads */
3676 swizzle
[1] = PIPE_SWIZZLE_Y
;
3677 swizzle
[2] = PIPE_SWIZZLE_0
;
3678 swizzle
[3] = PIPE_SWIZZLE_0
;
3681 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_64_FLOAT
;
3682 swizzle
[0] = PIPE_SWIZZLE_X
; /* 2 loads */
3683 swizzle
[1] = PIPE_SWIZZLE_Y
;
3684 swizzle
[2] = PIPE_SWIZZLE_Z
;
3685 swizzle
[3] = PIPE_SWIZZLE_W
;
3690 } else if (channel
&& desc
->nr_channels
== 3) {
3691 assert(desc
->swizzle
[0] == PIPE_SWIZZLE_X
);
3693 if (channel
->size
== 8) {
3694 if (channel
->pure_integer
)
3695 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGB_8_INT
;
3697 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGB_8
;
3698 } else if (channel
->size
== 16) {
3699 if (channel
->pure_integer
)
3700 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGB_16_INT
;
3702 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGB_16
;
3706 v
->rsrc_word3
[i
] = S_008F0C_DST_SEL_X(si_map_swizzle(swizzle
[0])) |
3707 S_008F0C_DST_SEL_Y(si_map_swizzle(swizzle
[1])) |
3708 S_008F0C_DST_SEL_Z(si_map_swizzle(swizzle
[2])) |
3709 S_008F0C_DST_SEL_W(si_map_swizzle(swizzle
[3])) |
3710 S_008F0C_NUM_FORMAT(num_format
) |
3711 S_008F0C_DATA_FORMAT(data_format
);
3713 memcpy(v
->elements
, elements
, sizeof(struct pipe_vertex_element
) * count
);
3718 static void si_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
3720 struct si_context
*sctx
= (struct si_context
*)ctx
;
3721 struct si_vertex_element
*v
= (struct si_vertex_element
*)state
;
3723 sctx
->vertex_elements
= v
;
3724 sctx
->vertex_buffers_dirty
= true;
3725 sctx
->do_update_shaders
= true;
3728 static void si_delete_vertex_element(struct pipe_context
*ctx
, void *state
)
3730 struct si_context
*sctx
= (struct si_context
*)ctx
;
3732 if (sctx
->vertex_elements
== state
)
3733 sctx
->vertex_elements
= NULL
;
3737 static void si_set_vertex_buffers(struct pipe_context
*ctx
,
3738 unsigned start_slot
, unsigned count
,
3739 const struct pipe_vertex_buffer
*buffers
)
3741 struct si_context
*sctx
= (struct si_context
*)ctx
;
3742 struct pipe_vertex_buffer
*dst
= sctx
->vertex_buffer
+ start_slot
;
3745 assert(start_slot
+ count
<= ARRAY_SIZE(sctx
->vertex_buffer
));
3748 for (i
= 0; i
< count
; i
++) {
3749 const struct pipe_vertex_buffer
*src
= buffers
+ i
;
3750 struct pipe_vertex_buffer
*dsti
= dst
+ i
;
3752 if (unlikely(src
->user_buffer
)) {
3753 /* Zero-stride attribs only. */
3754 assert(src
->stride
== 0);
3756 /* Assume that the user_buffer comes from
3757 * gl_current_attrib, which implies it has
3758 * 4 * 8 bytes (for dvec4 attributes).
3760 * Use const_uploader to upload into VRAM directly.
3762 u_upload_data(sctx
->b
.b
.const_uploader
, 0, 32, 32,
3764 &dsti
->buffer_offset
,
3768 struct pipe_resource
*buf
= src
->buffer
;
3770 pipe_resource_reference(&dsti
->buffer
, buf
);
3771 dsti
->buffer_offset
= src
->buffer_offset
;
3772 dsti
->stride
= src
->stride
;
3773 r600_context_add_resource_size(ctx
, buf
);
3775 r600_resource(buf
)->bind_history
|= PIPE_BIND_VERTEX_BUFFER
;
3779 for (i
= 0; i
< count
; i
++) {
3780 pipe_resource_reference(&dst
[i
].buffer
, NULL
);
3783 sctx
->vertex_buffers_dirty
= true;
3786 static void si_set_index_buffer(struct pipe_context
*ctx
,
3787 const struct pipe_index_buffer
*ib
)
3789 struct si_context
*sctx
= (struct si_context
*)ctx
;
3792 struct pipe_resource
*buf
= ib
->buffer
;
3794 pipe_resource_reference(&sctx
->index_buffer
.buffer
, buf
);
3795 memcpy(&sctx
->index_buffer
, ib
, sizeof(*ib
));
3796 r600_context_add_resource_size(ctx
, buf
);
3798 r600_resource(buf
)->bind_history
|= PIPE_BIND_INDEX_BUFFER
;
3800 pipe_resource_reference(&sctx
->index_buffer
.buffer
, NULL
);
3808 static void si_set_tess_state(struct pipe_context
*ctx
,
3809 const float default_outer_level
[4],
3810 const float default_inner_level
[2])
3812 struct si_context
*sctx
= (struct si_context
*)ctx
;
3813 struct pipe_constant_buffer cb
;
3816 memcpy(array
, default_outer_level
, sizeof(float) * 4);
3817 memcpy(array
+4, default_inner_level
, sizeof(float) * 2);
3820 cb
.user_buffer
= NULL
;
3821 cb
.buffer_size
= sizeof(array
);
3823 si_upload_const_buffer(sctx
, (struct r600_resource
**)&cb
.buffer
,
3824 (void*)array
, sizeof(array
),
3827 si_set_rw_buffer(sctx
, SI_HS_CONST_DEFAULT_TESS_LEVELS
, &cb
);
3828 pipe_resource_reference(&cb
.buffer
, NULL
);
3831 static void si_texture_barrier(struct pipe_context
*ctx
, unsigned flags
)
3833 struct si_context
*sctx
= (struct si_context
*)ctx
;
3835 sctx
->b
.flags
|= SI_CONTEXT_INV_VMEM_L1
|
3836 SI_CONTEXT_INV_GLOBAL_L2
|
3837 SI_CONTEXT_FLUSH_AND_INV_CB
;
3838 sctx
->framebuffer
.do_update_surf_dirtiness
= true;
3841 /* This only ensures coherency for shader image/buffer stores. */
3842 static void si_memory_barrier(struct pipe_context
*ctx
, unsigned flags
)
3844 struct si_context
*sctx
= (struct si_context
*)ctx
;
3846 /* Subsequent commands must wait for all shader invocations to
3848 sctx
->b
.flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
|
3849 SI_CONTEXT_CS_PARTIAL_FLUSH
;
3851 if (flags
& PIPE_BARRIER_CONSTANT_BUFFER
)
3852 sctx
->b
.flags
|= SI_CONTEXT_INV_SMEM_L1
|
3853 SI_CONTEXT_INV_VMEM_L1
;
3855 if (flags
& (PIPE_BARRIER_VERTEX_BUFFER
|
3856 PIPE_BARRIER_SHADER_BUFFER
|
3857 PIPE_BARRIER_TEXTURE
|
3858 PIPE_BARRIER_IMAGE
|
3859 PIPE_BARRIER_STREAMOUT_BUFFER
|
3860 PIPE_BARRIER_GLOBAL_BUFFER
)) {
3861 /* As far as I can tell, L1 contents are written back to L2
3862 * automatically at end of shader, but the contents of other
3863 * L1 caches might still be stale. */
3864 sctx
->b
.flags
|= SI_CONTEXT_INV_VMEM_L1
;
3867 if (flags
& PIPE_BARRIER_INDEX_BUFFER
) {
3868 /* Indices are read through TC L2 since VI.
3871 if (sctx
->screen
->b
.chip_class
<= CIK
)
3872 sctx
->b
.flags
|= SI_CONTEXT_WRITEBACK_GLOBAL_L2
;
3875 if (flags
& PIPE_BARRIER_FRAMEBUFFER
)
3876 sctx
->b
.flags
|= SI_CONTEXT_FLUSH_AND_INV_CB
|
3877 SI_CONTEXT_FLUSH_AND_INV_DB
;
3879 if (flags
& (PIPE_BARRIER_FRAMEBUFFER
|
3880 PIPE_BARRIER_INDIRECT_BUFFER
))
3881 sctx
->b
.flags
|= SI_CONTEXT_WRITEBACK_GLOBAL_L2
;
3884 static void *si_create_blend_custom(struct si_context
*sctx
, unsigned mode
)
3886 struct pipe_blend_state blend
;
3888 memset(&blend
, 0, sizeof(blend
));
3889 blend
.independent_blend_enable
= true;
3890 blend
.rt
[0].colormask
= 0xf;
3891 return si_create_blend_state_mode(&sctx
->b
.b
, &blend
, mode
);
3894 static void si_need_gfx_cs_space(struct pipe_context
*ctx
, unsigned num_dw
,
3895 bool include_draw_vbo
)
3897 si_need_cs_space((struct si_context
*)ctx
);
3900 static void si_init_config(struct si_context
*sctx
);
3902 void si_init_state_functions(struct si_context
*sctx
)
3904 si_init_external_atom(sctx
, &sctx
->b
.render_cond_atom
, &sctx
->atoms
.s
.render_cond
);
3905 si_init_external_atom(sctx
, &sctx
->b
.streamout
.begin_atom
, &sctx
->atoms
.s
.streamout_begin
);
3906 si_init_external_atom(sctx
, &sctx
->b
.streamout
.enable_atom
, &sctx
->atoms
.s
.streamout_enable
);
3907 si_init_external_atom(sctx
, &sctx
->b
.scissors
.atom
, &sctx
->atoms
.s
.scissors
);
3908 si_init_external_atom(sctx
, &sctx
->b
.viewports
.atom
, &sctx
->atoms
.s
.viewports
);
3910 si_init_atom(sctx
, &sctx
->framebuffer
.atom
, &sctx
->atoms
.s
.framebuffer
, si_emit_framebuffer_state
);
3911 si_init_atom(sctx
, &sctx
->msaa_sample_locs
.atom
, &sctx
->atoms
.s
.msaa_sample_locs
, si_emit_msaa_sample_locs
);
3912 si_init_atom(sctx
, &sctx
->db_render_state
, &sctx
->atoms
.s
.db_render_state
, si_emit_db_render_state
);
3913 si_init_atom(sctx
, &sctx
->msaa_config
, &sctx
->atoms
.s
.msaa_config
, si_emit_msaa_config
);
3914 si_init_atom(sctx
, &sctx
->sample_mask
.atom
, &sctx
->atoms
.s
.sample_mask
, si_emit_sample_mask
);
3915 si_init_atom(sctx
, &sctx
->cb_render_state
, &sctx
->atoms
.s
.cb_render_state
, si_emit_cb_render_state
);
3916 si_init_atom(sctx
, &sctx
->blend_color
.atom
, &sctx
->atoms
.s
.blend_color
, si_emit_blend_color
);
3917 si_init_atom(sctx
, &sctx
->clip_regs
, &sctx
->atoms
.s
.clip_regs
, si_emit_clip_regs
);
3918 si_init_atom(sctx
, &sctx
->clip_state
.atom
, &sctx
->atoms
.s
.clip_state
, si_emit_clip_state
);
3919 si_init_atom(sctx
, &sctx
->stencil_ref
.atom
, &sctx
->atoms
.s
.stencil_ref
, si_emit_stencil_ref
);
3921 sctx
->b
.b
.create_blend_state
= si_create_blend_state
;
3922 sctx
->b
.b
.bind_blend_state
= si_bind_blend_state
;
3923 sctx
->b
.b
.delete_blend_state
= si_delete_blend_state
;
3924 sctx
->b
.b
.set_blend_color
= si_set_blend_color
;
3926 sctx
->b
.b
.create_rasterizer_state
= si_create_rs_state
;
3927 sctx
->b
.b
.bind_rasterizer_state
= si_bind_rs_state
;
3928 sctx
->b
.b
.delete_rasterizer_state
= si_delete_rs_state
;
3930 sctx
->b
.b
.create_depth_stencil_alpha_state
= si_create_dsa_state
;
3931 sctx
->b
.b
.bind_depth_stencil_alpha_state
= si_bind_dsa_state
;
3932 sctx
->b
.b
.delete_depth_stencil_alpha_state
= si_delete_dsa_state
;
3934 sctx
->custom_dsa_flush
= si_create_db_flush_dsa(sctx
);
3935 sctx
->custom_blend_resolve
= si_create_blend_custom(sctx
, V_028808_CB_RESOLVE
);
3936 sctx
->custom_blend_decompress
= si_create_blend_custom(sctx
, V_028808_CB_FMASK_DECOMPRESS
);
3937 sctx
->custom_blend_fastclear
= si_create_blend_custom(sctx
, V_028808_CB_ELIMINATE_FAST_CLEAR
);
3938 sctx
->custom_blend_dcc_decompress
= si_create_blend_custom(sctx
, V_028808_CB_DCC_DECOMPRESS
);
3940 sctx
->b
.b
.set_clip_state
= si_set_clip_state
;
3941 sctx
->b
.b
.set_stencil_ref
= si_set_stencil_ref
;
3943 sctx
->b
.b
.set_framebuffer_state
= si_set_framebuffer_state
;
3944 sctx
->b
.b
.get_sample_position
= cayman_get_sample_position
;
3946 sctx
->b
.b
.create_sampler_state
= si_create_sampler_state
;
3947 sctx
->b
.b
.delete_sampler_state
= si_delete_sampler_state
;
3949 sctx
->b
.b
.create_sampler_view
= si_create_sampler_view
;
3950 sctx
->b
.b
.sampler_view_destroy
= si_sampler_view_destroy
;
3952 sctx
->b
.b
.set_sample_mask
= si_set_sample_mask
;
3954 sctx
->b
.b
.create_vertex_elements_state
= si_create_vertex_elements
;
3955 sctx
->b
.b
.bind_vertex_elements_state
= si_bind_vertex_elements
;
3956 sctx
->b
.b
.delete_vertex_elements_state
= si_delete_vertex_element
;
3957 sctx
->b
.b
.set_vertex_buffers
= si_set_vertex_buffers
;
3958 sctx
->b
.b
.set_index_buffer
= si_set_index_buffer
;
3960 sctx
->b
.b
.texture_barrier
= si_texture_barrier
;
3961 sctx
->b
.b
.memory_barrier
= si_memory_barrier
;
3962 sctx
->b
.b
.set_min_samples
= si_set_min_samples
;
3963 sctx
->b
.b
.set_tess_state
= si_set_tess_state
;
3965 sctx
->b
.b
.set_active_query_state
= si_set_active_query_state
;
3966 sctx
->b
.set_occlusion_query_state
= si_set_occlusion_query_state
;
3967 sctx
->b
.save_qbo_state
= si_save_qbo_state
;
3968 sctx
->b
.need_gfx_cs_space
= si_need_gfx_cs_space
;
3970 sctx
->b
.b
.draw_vbo
= si_draw_vbo
;
3972 si_init_config(sctx
);
3975 static uint32_t si_get_bo_metadata_word1(struct r600_common_screen
*rscreen
)
3977 return (ATI_VENDOR_ID
<< 16) | rscreen
->info
.pci_id
;
3980 static void si_query_opaque_metadata(struct r600_common_screen
*rscreen
,
3981 struct r600_texture
*rtex
,
3982 struct radeon_bo_metadata
*md
)
3984 struct si_screen
*sscreen
= (struct si_screen
*)rscreen
;
3985 struct pipe_resource
*res
= &rtex
->resource
.b
.b
;
3986 static const unsigned char swizzle
[] = {
3992 uint32_t desc
[8], i
;
3993 bool is_array
= util_resource_is_array_texture(res
);
3995 /* DRM 2.x.x doesn't support this. */
3996 if (rscreen
->info
.drm_major
!= 3)
3999 assert(rtex
->dcc_separate_buffer
== NULL
);
4000 assert(rtex
->fmask
.size
== 0);
4002 /* Metadata image format format version 1:
4003 * [0] = 1 (metadata format identifier)
4004 * [1] = (VENDOR_ID << 16) | PCI_ID
4005 * [2:9] = image descriptor for the whole resource
4006 * [2] is always 0, because the base address is cleared
4007 * [9] is the DCC offset bits [39:8] from the beginning of
4009 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
4012 md
->metadata
[0] = 1; /* metadata image format version 1 */
4014 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
4015 md
->metadata
[1] = si_get_bo_metadata_word1(rscreen
);
4017 si_make_texture_descriptor(sscreen
, rtex
, true,
4018 res
->target
, res
->format
,
4019 swizzle
, 0, res
->last_level
, 0,
4020 is_array
? res
->array_size
- 1 : 0,
4021 res
->width0
, res
->height0
, res
->depth0
,
4024 si_set_mutable_tex_desc_fields(sscreen
, rtex
, &rtex
->surface
.u
.legacy
.level
[0],
4025 0, 0, rtex
->surface
.blk_w
, false, desc
);
4027 /* Clear the base address and set the relative DCC offset. */
4029 desc
[1] &= C_008F14_BASE_ADDRESS_HI
;
4030 desc
[7] = rtex
->dcc_offset
>> 8;
4032 /* Dwords [2:9] contain the image descriptor. */
4033 memcpy(&md
->metadata
[2], desc
, sizeof(desc
));
4035 /* Dwords [10:..] contain the mipmap level offsets. */
4036 for (i
= 0; i
<= res
->last_level
; i
++)
4037 md
->metadata
[10+i
] = rtex
->surface
.u
.legacy
.level
[i
].offset
>> 8;
4039 md
->size_metadata
= (11 + res
->last_level
) * 4;
4042 static void si_apply_opaque_metadata(struct r600_common_screen
*rscreen
,
4043 struct r600_texture
*rtex
,
4044 struct radeon_bo_metadata
*md
)
4046 uint32_t *desc
= &md
->metadata
[2];
4048 if (rscreen
->chip_class
< VI
)
4051 /* Return if DCC is enabled. The texture should be set up with it
4054 if (md
->size_metadata
>= 11 * 4 &&
4055 md
->metadata
[0] != 0 &&
4056 md
->metadata
[1] == si_get_bo_metadata_word1(rscreen
) &&
4057 G_008F28_COMPRESSION_EN(desc
[6])) {
4058 assert(rtex
->dcc_offset
== ((uint64_t)desc
[7] << 8));
4062 /* Disable DCC. These are always set by texture_from_handle and must
4065 rtex
->dcc_offset
= 0;
4068 void si_init_screen_state_functions(struct si_screen
*sscreen
)
4070 sscreen
->b
.b
.is_format_supported
= si_is_format_supported
;
4071 sscreen
->b
.query_opaque_metadata
= si_query_opaque_metadata
;
4072 sscreen
->b
.apply_opaque_metadata
= si_apply_opaque_metadata
;
4076 si_write_harvested_raster_configs(struct si_context
*sctx
,
4077 struct si_pm4_state
*pm4
,
4078 unsigned raster_config
,
4079 unsigned raster_config_1
)
4081 unsigned sh_per_se
= MAX2(sctx
->screen
->b
.info
.max_sh_per_se
, 1);
4082 unsigned num_se
= MAX2(sctx
->screen
->b
.info
.max_se
, 1);
4083 unsigned rb_mask
= sctx
->screen
->b
.info
.enabled_rb_mask
;
4084 unsigned num_rb
= MIN2(sctx
->screen
->b
.info
.num_render_backends
, 16);
4085 unsigned rb_per_pkr
= MIN2(num_rb
/ num_se
/ sh_per_se
, 2);
4086 unsigned rb_per_se
= num_rb
/ num_se
;
4087 unsigned se_mask
[4];
4090 se_mask
[0] = ((1 << rb_per_se
) - 1);
4091 se_mask
[1] = (se_mask
[0] << rb_per_se
);
4092 se_mask
[2] = (se_mask
[1] << rb_per_se
);
4093 se_mask
[3] = (se_mask
[2] << rb_per_se
);
4095 se_mask
[0] &= rb_mask
;
4096 se_mask
[1] &= rb_mask
;
4097 se_mask
[2] &= rb_mask
;
4098 se_mask
[3] &= rb_mask
;
4100 assert(num_se
== 1 || num_se
== 2 || num_se
== 4);
4101 assert(sh_per_se
== 1 || sh_per_se
== 2);
4102 assert(rb_per_pkr
== 1 || rb_per_pkr
== 2);
4104 /* XXX: I can't figure out what the *_XSEL and *_YSEL
4105 * fields are for, so I'm leaving them as their default
4108 for (se
= 0; se
< num_se
; se
++) {
4109 unsigned raster_config_se
= raster_config
;
4110 unsigned pkr0_mask
= ((1 << rb_per_pkr
) - 1) << (se
* rb_per_se
);
4111 unsigned pkr1_mask
= pkr0_mask
<< rb_per_pkr
;
4112 int idx
= (se
/ 2) * 2;
4114 if ((num_se
> 1) && (!se_mask
[idx
] || !se_mask
[idx
+ 1])) {
4115 raster_config_se
&= C_028350_SE_MAP
;
4117 if (!se_mask
[idx
]) {
4119 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3
);
4122 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0
);
4126 pkr0_mask
&= rb_mask
;
4127 pkr1_mask
&= rb_mask
;
4128 if (rb_per_se
> 2 && (!pkr0_mask
|| !pkr1_mask
)) {
4129 raster_config_se
&= C_028350_PKR_MAP
;
4133 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3
);
4136 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0
);
4140 if (rb_per_se
>= 2) {
4141 unsigned rb0_mask
= 1 << (se
* rb_per_se
);
4142 unsigned rb1_mask
= rb0_mask
<< 1;
4144 rb0_mask
&= rb_mask
;
4145 rb1_mask
&= rb_mask
;
4146 if (!rb0_mask
|| !rb1_mask
) {
4147 raster_config_se
&= C_028350_RB_MAP_PKR0
;
4151 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3
);
4154 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0
);
4158 if (rb_per_se
> 2) {
4159 rb0_mask
= 1 << (se
* rb_per_se
+ rb_per_pkr
);
4160 rb1_mask
= rb0_mask
<< 1;
4161 rb0_mask
&= rb_mask
;
4162 rb1_mask
&= rb_mask
;
4163 if (!rb0_mask
|| !rb1_mask
) {
4164 raster_config_se
&= C_028350_RB_MAP_PKR1
;
4168 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3
);
4171 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0
);
4177 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
4178 if (sctx
->b
.chip_class
< CIK
)
4179 si_pm4_set_reg(pm4
, GRBM_GFX_INDEX
,
4180 SE_INDEX(se
) | SH_BROADCAST_WRITES
|
4181 INSTANCE_BROADCAST_WRITES
);
4183 si_pm4_set_reg(pm4
, R_030800_GRBM_GFX_INDEX
,
4184 S_030800_SE_INDEX(se
) | S_030800_SH_BROADCAST_WRITES(1) |
4185 S_030800_INSTANCE_BROADCAST_WRITES(1));
4186 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
, raster_config_se
);
4189 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
4190 if (sctx
->b
.chip_class
< CIK
)
4191 si_pm4_set_reg(pm4
, GRBM_GFX_INDEX
,
4192 SE_BROADCAST_WRITES
| SH_BROADCAST_WRITES
|
4193 INSTANCE_BROADCAST_WRITES
);
4195 si_pm4_set_reg(pm4
, R_030800_GRBM_GFX_INDEX
,
4196 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
4197 S_030800_INSTANCE_BROADCAST_WRITES(1));
4199 if ((num_se
> 2) && ((!se_mask
[0] && !se_mask
[1]) ||
4200 (!se_mask
[2] && !se_mask
[3]))) {
4201 raster_config_1
&= C_028354_SE_PAIR_MAP
;
4203 if (!se_mask
[0] && !se_mask
[1]) {
4205 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3
);
4208 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0
);
4212 si_pm4_set_reg(pm4
, R_028354_PA_SC_RASTER_CONFIG_1
, raster_config_1
);
4216 static void si_init_config(struct si_context
*sctx
)
4218 struct si_screen
*sscreen
= sctx
->screen
;
4219 unsigned num_rb
= MIN2(sctx
->screen
->b
.info
.num_render_backends
, 16);
4220 unsigned rb_mask
= sctx
->screen
->b
.info
.enabled_rb_mask
;
4221 unsigned raster_config
, raster_config_1
;
4222 uint64_t border_color_va
= sctx
->border_color_buffer
->gpu_address
;
4223 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
4228 si_pm4_cmd_begin(pm4
, PKT3_CONTEXT_CONTROL
);
4229 si_pm4_cmd_add(pm4
, CONTEXT_CONTROL_LOAD_ENABLE(1));
4230 si_pm4_cmd_add(pm4
, CONTEXT_CONTROL_SHADOW_ENABLE(1));
4231 si_pm4_cmd_end(pm4
, false);
4233 si_pm4_set_reg(pm4
, R_028A18_VGT_HOS_MAX_TESS_LEVEL
, fui(64));
4234 si_pm4_set_reg(pm4
, R_028A1C_VGT_HOS_MIN_TESS_LEVEL
, fui(0));
4236 /* FIXME calculate these values somehow ??? */
4237 si_pm4_set_reg(pm4
, R_028A54_VGT_GS_PER_ES
, SI_GS_PER_ES
);
4238 si_pm4_set_reg(pm4
, R_028A58_VGT_ES_PER_GS
, 0x40);
4239 si_pm4_set_reg(pm4
, R_028A5C_VGT_GS_PER_VS
, 0x2);
4241 si_pm4_set_reg(pm4
, R_028A8C_VGT_PRIMITIVEID_RESET
, 0x0);
4242 si_pm4_set_reg(pm4
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
4244 si_pm4_set_reg(pm4
, R_028B98_VGT_STRMOUT_BUFFER_CONFIG
, 0x0);
4245 si_pm4_set_reg(pm4
, R_028AB8_VGT_VTX_CNT_EN
, 0x0);
4246 if (sctx
->b
.chip_class
< CIK
)
4247 si_pm4_set_reg(pm4
, R_008A14_PA_CL_ENHANCE
, S_008A14_NUM_CLIP_SEQ(3) |
4248 S_008A14_CLIP_VTX_REORDER_ENA(1));
4250 si_pm4_set_reg(pm4
, R_028BD4_PA_SC_CENTROID_PRIORITY_0
, 0x76543210);
4251 si_pm4_set_reg(pm4
, R_028BD8_PA_SC_CENTROID_PRIORITY_1
, 0xfedcba98);
4253 si_pm4_set_reg(pm4
, R_02882C_PA_SU_PRIM_FILTER_CNTL
, 0);
4255 switch (sctx
->screen
->b
.family
) {
4258 raster_config
= 0x2a00126a;
4259 raster_config_1
= 0x00000000;
4262 raster_config
= 0x0000124a;
4263 raster_config_1
= 0x00000000;
4266 raster_config
= 0x00000082;
4267 raster_config_1
= 0x00000000;
4270 raster_config
= 0x00000000;
4271 raster_config_1
= 0x00000000;
4274 raster_config
= 0x16000012;
4275 raster_config_1
= 0x00000000;
4278 raster_config
= 0x3a00161a;
4279 raster_config_1
= 0x0000002e;
4282 if (sscreen
->b
.info
.cik_macrotile_mode_array
[0] == 0x000000e8) {
4283 /* old kernels with old tiling config */
4284 raster_config
= 0x16000012;
4285 raster_config_1
= 0x0000002a;
4287 raster_config
= 0x3a00161a;
4288 raster_config_1
= 0x0000002e;
4291 case CHIP_POLARIS10
:
4292 raster_config
= 0x16000012;
4293 raster_config_1
= 0x0000002a;
4295 case CHIP_POLARIS11
:
4296 case CHIP_POLARIS12
:
4297 raster_config
= 0x16000012;
4298 raster_config_1
= 0x00000000;
4301 raster_config
= 0x16000012;
4302 raster_config_1
= 0x0000002a;
4306 raster_config
= 0x00000000;
4308 raster_config
= 0x00000002;
4309 raster_config_1
= 0x00000000;
4312 raster_config
= 0x00000002;
4313 raster_config_1
= 0x00000000;
4316 /* KV should be 0x00000002, but that causes problems with radeon */
4317 raster_config
= 0x00000000; /* 0x00000002 */
4318 raster_config_1
= 0x00000000;
4323 raster_config
= 0x00000000;
4324 raster_config_1
= 0x00000000;
4327 if (sctx
->b
.chip_class
<= VI
) {
4329 "radeonsi: Unknown GPU, using 0 for raster_config\n");
4330 raster_config
= 0x00000000;
4331 raster_config_1
= 0x00000000;
4336 if (sctx
->b
.chip_class
<= VI
) {
4337 if (!rb_mask
|| util_bitcount(rb_mask
) >= num_rb
) {
4338 /* Always use the default config when all backends are enabled
4339 * (or when we failed to determine the enabled backends).
4341 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
,
4343 if (sctx
->b
.chip_class
>= CIK
)
4344 si_pm4_set_reg(pm4
, R_028354_PA_SC_RASTER_CONFIG_1
,
4347 si_write_harvested_raster_configs(sctx
, pm4
, raster_config
, raster_config_1
);
4351 si_pm4_set_reg(pm4
, R_028204_PA_SC_WINDOW_SCISSOR_TL
, S_028204_WINDOW_OFFSET_DISABLE(1));
4352 si_pm4_set_reg(pm4
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, S_028240_WINDOW_OFFSET_DISABLE(1));
4353 si_pm4_set_reg(pm4
, R_028244_PA_SC_GENERIC_SCISSOR_BR
,
4354 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
4355 si_pm4_set_reg(pm4
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 0);
4356 si_pm4_set_reg(pm4
, R_028034_PA_SC_SCREEN_SCISSOR_BR
,
4357 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
4359 si_pm4_set_reg(pm4
, R_02820C_PA_SC_CLIPRECT_RULE
, 0xFFFF);
4360 si_pm4_set_reg(pm4
, R_028230_PA_SC_EDGERULE
,
4361 S_028230_ER_TRI(0xA) |
4362 S_028230_ER_POINT(0xA) |
4363 S_028230_ER_RECT(0xA) |
4364 /* Required by DX10_DIAMOND_TEST_ENA: */
4365 S_028230_ER_LINE_LR(0x1A) |
4366 S_028230_ER_LINE_RL(0x26) |
4367 S_028230_ER_LINE_TB(0xA) |
4368 S_028230_ER_LINE_BT(0xA));
4369 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
4370 si_pm4_set_reg(pm4
, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET
, 0);
4371 si_pm4_set_reg(pm4
, R_028820_PA_CL_NANINF_CNTL
, 0);
4372 si_pm4_set_reg(pm4
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 0x0);
4373 si_pm4_set_reg(pm4
, R_028AC4_DB_SRESULTS_COMPARE_STATE1
, 0x0);
4374 si_pm4_set_reg(pm4
, R_028AC8_DB_PRELOAD_CONTROL
, 0x0);
4375 si_pm4_set_reg(pm4
, R_02800C_DB_RENDER_OVERRIDE
, 0);
4377 if (sctx
->b
.chip_class
>= GFX9
) {
4378 si_pm4_set_reg(pm4
, R_030920_VGT_MAX_VTX_INDX
, ~0);
4379 si_pm4_set_reg(pm4
, R_030924_VGT_MIN_VTX_INDX
, 0);
4380 si_pm4_set_reg(pm4
, R_030928_VGT_INDX_OFFSET
, 0);
4382 si_pm4_set_reg(pm4
, R_028400_VGT_MAX_VTX_INDX
, ~0);
4383 si_pm4_set_reg(pm4
, R_028404_VGT_MIN_VTX_INDX
, 0);
4384 si_pm4_set_reg(pm4
, R_028408_VGT_INDX_OFFSET
, 0);
4387 if (sctx
->b
.chip_class
>= CIK
) {
4388 /* If this is 0, Bonaire can hang even if GS isn't being used.
4389 * Other chips are unaffected. These are suboptimal values,
4390 * but we don't use on-chip GS.
4392 si_pm4_set_reg(pm4
, R_028A44_VGT_GS_ONCHIP_CNTL
,
4393 S_028A44_ES_VERTS_PER_SUBGRP(64) |
4394 S_028A44_GS_PRIMS_PER_SUBGRP(4));
4396 if (sctx
->b
.chip_class
>= GFX9
) {
4397 si_pm4_set_reg(pm4
, R_00B41C_SPI_SHADER_PGM_RSRC3_HS
, S_00B41C_CU_EN(0xffff));
4399 si_pm4_set_reg(pm4
, R_00B51C_SPI_SHADER_PGM_RSRC3_LS
, S_00B51C_CU_EN(0xffff));
4400 si_pm4_set_reg(pm4
, R_00B41C_SPI_SHADER_PGM_RSRC3_HS
, 0);
4401 si_pm4_set_reg(pm4
, R_00B31C_SPI_SHADER_PGM_RSRC3_ES
, S_00B31C_CU_EN(0xffff));
4403 si_pm4_set_reg(pm4
, R_00B21C_SPI_SHADER_PGM_RSRC3_GS
, S_00B21C_CU_EN(0xffff));
4405 if (sscreen
->b
.info
.num_good_compute_units
/
4406 (sscreen
->b
.info
.max_se
* sscreen
->b
.info
.max_sh_per_se
) <= 4) {
4407 /* Too few available compute units per SH. Disallowing
4408 * VS to run on CU0 could hurt us more than late VS
4409 * allocation would help.
4411 * LATE_ALLOC_VS = 2 is the highest safe number.
4413 si_pm4_set_reg(pm4
, R_00B118_SPI_SHADER_PGM_RSRC3_VS
, S_00B118_CU_EN(0xffff));
4414 si_pm4_set_reg(pm4
, R_00B11C_SPI_SHADER_LATE_ALLOC_VS
, S_00B11C_LIMIT(2));
4416 /* Set LATE_ALLOC_VS == 31. It should be less than
4417 * the number of scratch waves. Limitations:
4418 * - VS can't execute on CU0.
4419 * - If HS writes outputs to LDS, LS can't execute on CU0.
4421 si_pm4_set_reg(pm4
, R_00B118_SPI_SHADER_PGM_RSRC3_VS
, S_00B118_CU_EN(0xfffe));
4422 si_pm4_set_reg(pm4
, R_00B11C_SPI_SHADER_LATE_ALLOC_VS
, S_00B11C_LIMIT(31));
4425 si_pm4_set_reg(pm4
, R_00B01C_SPI_SHADER_PGM_RSRC3_PS
, S_00B01C_CU_EN(0xffff));
4428 if (sctx
->b
.chip_class
>= VI
) {
4429 unsigned vgt_tess_distribution
;
4431 si_pm4_set_reg(pm4
, R_028424_CB_DCC_CONTROL
,
4432 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
4433 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
4434 if (sctx
->b
.family
< CHIP_POLARIS10
)
4435 si_pm4_set_reg(pm4
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
, 30);
4436 si_pm4_set_reg(pm4
, R_028C5C_VGT_OUT_DEALLOC_CNTL
, 32);
4438 vgt_tess_distribution
=
4439 S_028B50_ACCUM_ISOLINE(32) |
4440 S_028B50_ACCUM_TRI(11) |
4441 S_028B50_ACCUM_QUAD(11) |
4442 S_028B50_DONUT_SPLIT(16);
4444 /* Testing with Unigine Heaven extreme tesselation yielded best results
4445 * with TRAP_SPLIT = 3.
4447 if (sctx
->b
.family
== CHIP_FIJI
||
4448 sctx
->b
.family
>= CHIP_POLARIS10
)
4449 vgt_tess_distribution
|= S_028B50_TRAP_SPLIT(3);
4451 si_pm4_set_reg(pm4
, R_028B50_VGT_TESS_DISTRIBUTION
, vgt_tess_distribution
);
4453 si_pm4_set_reg(pm4
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
, 14);
4454 si_pm4_set_reg(pm4
, R_028C5C_VGT_OUT_DEALLOC_CNTL
, 16);
4457 if (sctx
->screen
->b
.has_rbplus
)
4458 si_pm4_set_reg(pm4
, R_028C40_PA_SC_SHADER_CONTROL
, 0);
4460 si_pm4_set_reg(pm4
, R_028080_TA_BC_BASE_ADDR
, border_color_va
>> 8);
4461 if (sctx
->b
.chip_class
>= CIK
)
4462 si_pm4_set_reg(pm4
, R_028084_TA_BC_BASE_ADDR_HI
, border_color_va
>> 40);
4463 si_pm4_add_bo(pm4
, sctx
->border_color_buffer
, RADEON_USAGE_READ
,
4464 RADEON_PRIO_BORDER_COLORS
);
4466 if (sctx
->b
.chip_class
>= GFX9
) {
4467 si_pm4_set_reg(pm4
, R_028060_DB_DFSM_CONTROL
, 0);
4468 si_pm4_set_reg(pm4
, R_028064_DB_RENDER_FILTER
, 0);
4469 /* TODO: We can use this to disable RBs for rendering to GART: */
4470 si_pm4_set_reg(pm4
, R_02835C_PA_SC_TILE_STEERING_OVERRIDE
, 0);
4471 si_pm4_set_reg(pm4
, R_02883C_PA_SU_OVER_RASTERIZATION_CNTL
, 0);
4472 /* TODO: Enable the binner: */
4473 si_pm4_set_reg(pm4
, R_028C44_PA_SC_BINNER_CNTL_0
,
4474 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC
));
4475 si_pm4_set_reg(pm4
, R_028C48_PA_SC_BINNER_CNTL_1
, 0);
4476 si_pm4_set_reg(pm4
, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
,
4477 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
4478 si_pm4_set_reg(pm4
, R_030968_VGT_INSTANCE_BASE_ID
, 0);
4481 si_pm4_upload_indirect_buffer(sctx
, pm4
);
4482 sctx
->init_config
= pm4
;