2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Christian König <christian.koenig@amd.com>
28 #include "si_shader.h"
30 #include "radeon/r600_cs.h"
32 #include "util/u_format.h"
33 #include "util/u_format_s3tc.h"
34 #include "util/u_memory.h"
35 #include "util/u_pstipple.h"
37 static void si_init_atom(struct r600_atom
*atom
, struct r600_atom
**list_elem
,
38 void (*emit
)(struct si_context
*ctx
, struct r600_atom
*state
),
41 atom
->emit
= (void*)emit
;
42 atom
->num_dw
= num_dw
;
47 unsigned si_array_mode(unsigned mode
)
50 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
51 return V_009910_ARRAY_LINEAR_ALIGNED
;
52 case RADEON_SURF_MODE_1D
:
53 return V_009910_ARRAY_1D_TILED_THIN1
;
54 case RADEON_SURF_MODE_2D
:
55 return V_009910_ARRAY_2D_TILED_THIN1
;
57 case RADEON_SURF_MODE_LINEAR
:
58 return V_009910_ARRAY_LINEAR_GENERAL
;
62 uint32_t si_num_banks(struct si_screen
*sscreen
, struct r600_texture
*tex
)
64 if (sscreen
->b
.chip_class
>= CIK
&&
65 sscreen
->b
.info
.cik_macrotile_mode_array_valid
) {
66 unsigned index
, tileb
;
68 tileb
= 8 * 8 * tex
->surface
.bpe
;
69 tileb
= MIN2(tex
->surface
.tile_split
, tileb
);
71 for (index
= 0; tileb
> 64; index
++) {
76 return (sscreen
->b
.info
.cik_macrotile_mode_array
[index
] >> 6) & 0x3;
79 if (sscreen
->b
.chip_class
== SI
&&
80 sscreen
->b
.info
.si_tile_mode_array_valid
) {
81 /* Don't use stencil_tiling_index, because num_banks is always
82 * read from the depth mode. */
83 unsigned tile_mode_index
= tex
->surface
.tiling_index
[0];
84 assert(tile_mode_index
< 32);
86 return G_009910_NUM_BANKS(sscreen
->b
.info
.si_tile_mode_array
[tile_mode_index
]);
90 switch (sscreen
->b
.tiling_info
.num_banks
) {
92 return V_02803C_ADDR_SURF_2_BANK
;
94 return V_02803C_ADDR_SURF_4_BANK
;
97 return V_02803C_ADDR_SURF_8_BANK
;
99 return V_02803C_ADDR_SURF_16_BANK
;
103 unsigned cik_tile_split(unsigned tile_split
)
105 switch (tile_split
) {
107 tile_split
= V_028040_ADDR_SURF_TILE_SPLIT_64B
;
110 tile_split
= V_028040_ADDR_SURF_TILE_SPLIT_128B
;
113 tile_split
= V_028040_ADDR_SURF_TILE_SPLIT_256B
;
116 tile_split
= V_028040_ADDR_SURF_TILE_SPLIT_512B
;
120 tile_split
= V_028040_ADDR_SURF_TILE_SPLIT_1KB
;
123 tile_split
= V_028040_ADDR_SURF_TILE_SPLIT_2KB
;
126 tile_split
= V_028040_ADDR_SURF_TILE_SPLIT_4KB
;
132 unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect
)
134 switch (macro_tile_aspect
) {
137 macro_tile_aspect
= V_02803C_ADDR_SURF_MACRO_ASPECT_1
;
140 macro_tile_aspect
= V_02803C_ADDR_SURF_MACRO_ASPECT_2
;
143 macro_tile_aspect
= V_02803C_ADDR_SURF_MACRO_ASPECT_4
;
146 macro_tile_aspect
= V_02803C_ADDR_SURF_MACRO_ASPECT_8
;
149 return macro_tile_aspect
;
152 unsigned cik_bank_wh(unsigned bankwh
)
157 bankwh
= V_02803C_ADDR_SURF_BANK_WIDTH_1
;
160 bankwh
= V_02803C_ADDR_SURF_BANK_WIDTH_2
;
163 bankwh
= V_02803C_ADDR_SURF_BANK_WIDTH_4
;
166 bankwh
= V_02803C_ADDR_SURF_BANK_WIDTH_8
;
172 unsigned cik_db_pipe_config(struct si_screen
*sscreen
, unsigned tile_mode
)
174 if (sscreen
->b
.info
.si_tile_mode_array_valid
) {
175 uint32_t gb_tile_mode
= sscreen
->b
.info
.si_tile_mode_array
[tile_mode
];
177 return G_009910_PIPE_CONFIG(gb_tile_mode
);
180 /* This is probably broken for a lot of chips, but it's only used
181 * if the kernel cannot return the tile mode array for CIK. */
182 switch (sscreen
->b
.info
.r600_num_tile_pipes
) {
184 return V_02803C_X_ADDR_SURF_P16_32X32_16X16
;
186 return V_02803C_X_ADDR_SURF_P8_32X32_16X16
;
189 if (sscreen
->b
.info
.r600_num_backends
== 4)
190 return V_02803C_X_ADDR_SURF_P4_16X16
;
192 return V_02803C_X_ADDR_SURF_P4_8X16
;
194 return V_02803C_ADDR_SURF_P2
;
198 static unsigned si_map_swizzle(unsigned swizzle
)
201 case UTIL_FORMAT_SWIZZLE_Y
:
202 return V_008F0C_SQ_SEL_Y
;
203 case UTIL_FORMAT_SWIZZLE_Z
:
204 return V_008F0C_SQ_SEL_Z
;
205 case UTIL_FORMAT_SWIZZLE_W
:
206 return V_008F0C_SQ_SEL_W
;
207 case UTIL_FORMAT_SWIZZLE_0
:
208 return V_008F0C_SQ_SEL_0
;
209 case UTIL_FORMAT_SWIZZLE_1
:
210 return V_008F0C_SQ_SEL_1
;
211 default: /* UTIL_FORMAT_SWIZZLE_X */
212 return V_008F0C_SQ_SEL_X
;
216 static uint32_t S_FIXED(float value
, uint32_t frac_bits
)
218 return value
* (1 << frac_bits
);
221 /* 12.4 fixed-point */
222 static unsigned si_pack_float_12p4(float x
)
225 x
>= 4096 ? 0xffff : x
* 16;
229 * Inferred framebuffer and blender state.
231 * One of the reasons this must be derived from the framebuffer state is that:
232 * - The blend state mask is 0xf most of the time.
233 * - The COLOR1 format isn't INVALID because of possible dual-source blending,
234 * so COLOR1 is enabled pretty much all the time.
235 * So CB_TARGET_MASK is the only register that can disable COLOR1.
237 static void si_update_fb_blend_state(struct si_context
*sctx
)
239 struct si_pm4_state
*pm4
;
240 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
241 uint32_t mask
= 0, i
;
246 pm4
= CALLOC_STRUCT(si_pm4_state
);
250 for (i
= 0; i
< sctx
->framebuffer
.state
.nr_cbufs
; i
++)
251 if (sctx
->framebuffer
.state
.cbufs
[i
])
252 mask
|= 0xf << (4*i
);
253 mask
&= blend
->cb_target_mask
;
255 si_pm4_set_reg(pm4
, R_028238_CB_TARGET_MASK
, mask
);
256 si_pm4_set_state(sctx
, fb_blend
, pm4
);
263 static uint32_t si_translate_blend_function(int blend_func
)
265 switch (blend_func
) {
267 return V_028780_COMB_DST_PLUS_SRC
;
268 case PIPE_BLEND_SUBTRACT
:
269 return V_028780_COMB_SRC_MINUS_DST
;
270 case PIPE_BLEND_REVERSE_SUBTRACT
:
271 return V_028780_COMB_DST_MINUS_SRC
;
273 return V_028780_COMB_MIN_DST_SRC
;
275 return V_028780_COMB_MAX_DST_SRC
;
277 R600_ERR("Unknown blend function %d\n", blend_func
);
284 static uint32_t si_translate_blend_factor(int blend_fact
)
286 switch (blend_fact
) {
287 case PIPE_BLENDFACTOR_ONE
:
288 return V_028780_BLEND_ONE
;
289 case PIPE_BLENDFACTOR_SRC_COLOR
:
290 return V_028780_BLEND_SRC_COLOR
;
291 case PIPE_BLENDFACTOR_SRC_ALPHA
:
292 return V_028780_BLEND_SRC_ALPHA
;
293 case PIPE_BLENDFACTOR_DST_ALPHA
:
294 return V_028780_BLEND_DST_ALPHA
;
295 case PIPE_BLENDFACTOR_DST_COLOR
:
296 return V_028780_BLEND_DST_COLOR
;
297 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
298 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
299 case PIPE_BLENDFACTOR_CONST_COLOR
:
300 return V_028780_BLEND_CONSTANT_COLOR
;
301 case PIPE_BLENDFACTOR_CONST_ALPHA
:
302 return V_028780_BLEND_CONSTANT_ALPHA
;
303 case PIPE_BLENDFACTOR_ZERO
:
304 return V_028780_BLEND_ZERO
;
305 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
306 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
307 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
308 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
309 case PIPE_BLENDFACTOR_INV_DST_ALPHA
:
310 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
311 case PIPE_BLENDFACTOR_INV_DST_COLOR
:
312 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
313 case PIPE_BLENDFACTOR_INV_CONST_COLOR
:
314 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR
;
315 case PIPE_BLENDFACTOR_INV_CONST_ALPHA
:
316 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA
;
317 case PIPE_BLENDFACTOR_SRC1_COLOR
:
318 return V_028780_BLEND_SRC1_COLOR
;
319 case PIPE_BLENDFACTOR_SRC1_ALPHA
:
320 return V_028780_BLEND_SRC1_ALPHA
;
321 case PIPE_BLENDFACTOR_INV_SRC1_COLOR
:
322 return V_028780_BLEND_INV_SRC1_COLOR
;
323 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA
:
324 return V_028780_BLEND_INV_SRC1_ALPHA
;
326 R600_ERR("Bad blend factor %d not supported!\n", blend_fact
);
333 static void *si_create_blend_state_mode(struct pipe_context
*ctx
,
334 const struct pipe_blend_state
*state
,
337 struct si_state_blend
*blend
= CALLOC_STRUCT(si_state_blend
);
338 struct si_pm4_state
*pm4
= &blend
->pm4
;
340 uint32_t color_control
= 0;
345 blend
->alpha_to_one
= state
->alpha_to_one
;
347 if (state
->logicop_enable
) {
348 color_control
|= S_028808_ROP3(state
->logicop_func
| (state
->logicop_func
<< 4));
350 color_control
|= S_028808_ROP3(0xcc);
353 si_pm4_set_reg(pm4
, R_028B70_DB_ALPHA_TO_MASK
,
354 S_028B70_ALPHA_TO_MASK_ENABLE(state
->alpha_to_coverage
) |
355 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
356 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
357 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
358 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
360 blend
->cb_target_mask
= 0;
361 for (int i
= 0; i
< 8; i
++) {
362 /* state->rt entries > 0 only written if independent blending */
363 const int j
= state
->independent_blend_enable
? i
: 0;
365 unsigned eqRGB
= state
->rt
[j
].rgb_func
;
366 unsigned srcRGB
= state
->rt
[j
].rgb_src_factor
;
367 unsigned dstRGB
= state
->rt
[j
].rgb_dst_factor
;
368 unsigned eqA
= state
->rt
[j
].alpha_func
;
369 unsigned srcA
= state
->rt
[j
].alpha_src_factor
;
370 unsigned dstA
= state
->rt
[j
].alpha_dst_factor
;
372 unsigned blend_cntl
= 0;
374 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
375 blend
->cb_target_mask
|= state
->rt
[j
].colormask
<< (4 * i
);
377 if (!state
->rt
[j
].blend_enable
) {
378 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
382 blend_cntl
|= S_028780_ENABLE(1);
383 blend_cntl
|= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB
));
384 blend_cntl
|= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB
));
385 blend_cntl
|= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB
));
387 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
388 blend_cntl
|= S_028780_SEPARATE_ALPHA_BLEND(1);
389 blend_cntl
|= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA
));
390 blend_cntl
|= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA
));
391 blend_cntl
|= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA
));
393 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
396 if (blend
->cb_target_mask
) {
397 color_control
|= S_028808_MODE(mode
);
399 color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
401 si_pm4_set_reg(pm4
, R_028808_CB_COLOR_CONTROL
, color_control
);
406 static void *si_create_blend_state(struct pipe_context
*ctx
,
407 const struct pipe_blend_state
*state
)
409 return si_create_blend_state_mode(ctx
, state
, V_028808_CB_NORMAL
);
412 static void si_bind_blend_state(struct pipe_context
*ctx
, void *state
)
414 struct si_context
*sctx
= (struct si_context
*)ctx
;
415 si_pm4_bind_state(sctx
, blend
, (struct si_state_blend
*)state
);
416 si_update_fb_blend_state(sctx
);
419 static void si_delete_blend_state(struct pipe_context
*ctx
, void *state
)
421 struct si_context
*sctx
= (struct si_context
*)ctx
;
422 si_pm4_delete_state(sctx
, blend
, (struct si_state_blend
*)state
);
425 static void si_set_blend_color(struct pipe_context
*ctx
,
426 const struct pipe_blend_color
*state
)
428 struct si_context
*sctx
= (struct si_context
*)ctx
;
429 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
434 si_pm4_set_reg(pm4
, R_028414_CB_BLEND_RED
, fui(state
->color
[0]));
435 si_pm4_set_reg(pm4
, R_028418_CB_BLEND_GREEN
, fui(state
->color
[1]));
436 si_pm4_set_reg(pm4
, R_02841C_CB_BLEND_BLUE
, fui(state
->color
[2]));
437 si_pm4_set_reg(pm4
, R_028420_CB_BLEND_ALPHA
, fui(state
->color
[3]));
439 si_pm4_set_state(sctx
, blend_color
, pm4
);
443 * Clipping, scissors and viewport
446 static void si_set_clip_state(struct pipe_context
*ctx
,
447 const struct pipe_clip_state
*state
)
449 struct si_context
*sctx
= (struct si_context
*)ctx
;
450 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
451 struct pipe_constant_buffer cb
;
456 for (int i
= 0; i
< 6; i
++) {
457 si_pm4_set_reg(pm4
, R_0285BC_PA_CL_UCP_0_X
+ i
* 16,
458 fui(state
->ucp
[i
][0]));
459 si_pm4_set_reg(pm4
, R_0285C0_PA_CL_UCP_0_Y
+ i
* 16,
460 fui(state
->ucp
[i
][1]));
461 si_pm4_set_reg(pm4
, R_0285C4_PA_CL_UCP_0_Z
+ i
* 16,
462 fui(state
->ucp
[i
][2]));
463 si_pm4_set_reg(pm4
, R_0285C8_PA_CL_UCP_0_W
+ i
* 16,
464 fui(state
->ucp
[i
][3]));
468 cb
.user_buffer
= state
->ucp
;
469 cb
.buffer_offset
= 0;
470 cb
.buffer_size
= 4*4*8;
471 ctx
->set_constant_buffer(ctx
, PIPE_SHADER_VERTEX
, SI_DRIVER_STATE_CONST_BUF
, &cb
);
472 pipe_resource_reference(&cb
.buffer
, NULL
);
474 si_pm4_set_state(sctx
, clip
, pm4
);
477 #define SIX_BITS 0x3F
479 static void si_emit_clip_regs(struct si_context
*sctx
, struct r600_atom
*atom
)
481 struct radeon_winsys_cs
*cs
= sctx
->b
.rings
.gfx
.cs
;
482 struct tgsi_shader_info
*info
= si_get_vs_info(sctx
);
483 unsigned window_space
=
484 info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
485 unsigned clipdist_mask
=
486 info
->writes_clipvertex
? SIX_BITS
: info
->clipdist_writemask
;
488 r600_write_context_reg(cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
489 S_02881C_USE_VTX_POINT_SIZE(info
->writes_psize
) |
490 S_02881C_USE_VTX_EDGE_FLAG(info
->writes_edgeflag
) |
491 S_02881C_USE_VTX_RENDER_TARGET_INDX(info
->writes_layer
) |
492 S_02881C_USE_VTX_VIEWPORT_INDX(info
->writes_viewport_index
) |
493 S_02881C_VS_OUT_CCDIST0_VEC_ENA((clipdist_mask
& 0x0F) != 0) |
494 S_02881C_VS_OUT_CCDIST1_VEC_ENA((clipdist_mask
& 0xF0) != 0) |
495 S_02881C_VS_OUT_MISC_VEC_ENA(info
->writes_psize
||
496 info
->writes_edgeflag
||
497 info
->writes_layer
||
498 info
->writes_viewport_index
) |
499 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(1) |
500 (sctx
->queued
.named
.rasterizer
->clip_plane_enable
&
502 r600_write_context_reg(cs
, R_028810_PA_CL_CLIP_CNTL
,
503 sctx
->queued
.named
.rasterizer
->pa_cl_clip_cntl
|
505 sctx
->queued
.named
.rasterizer
->clip_plane_enable
& SIX_BITS
) |
506 S_028810_CLIP_DISABLE(window_space
));
509 static void si_set_scissor_states(struct pipe_context
*ctx
,
511 unsigned num_scissors
,
512 const struct pipe_scissor_state
*state
)
514 struct si_context
*sctx
= (struct si_context
*)ctx
;
515 struct si_state_scissor
*scissor
;
516 struct si_pm4_state
*pm4
;
519 for (i
= start_slot
; i
< start_slot
+ num_scissors
; i
++) {
520 int idx
= i
- start_slot
;
521 int offset
= i
* 4 * 2;
523 scissor
= CALLOC_STRUCT(si_state_scissor
);
527 scissor
->scissor
= state
[idx
];
528 si_pm4_set_reg(pm4
, R_028250_PA_SC_VPORT_SCISSOR_0_TL
+ offset
,
529 S_028250_TL_X(state
[idx
].minx
) | S_028250_TL_Y(state
[idx
].miny
) |
530 S_028250_WINDOW_OFFSET_DISABLE(1));
531 si_pm4_set_reg(pm4
, R_028254_PA_SC_VPORT_SCISSOR_0_BR
+ offset
,
532 S_028254_BR_X(state
[idx
].maxx
) | S_028254_BR_Y(state
[idx
].maxy
));
533 si_pm4_set_state(sctx
, scissor
[i
], scissor
);
537 static void si_set_viewport_states(struct pipe_context
*ctx
,
539 unsigned num_viewports
,
540 const struct pipe_viewport_state
*state
)
542 struct si_context
*sctx
= (struct si_context
*)ctx
;
543 struct si_state_viewport
*viewport
;
544 struct si_pm4_state
*pm4
;
547 for (i
= start_slot
; i
< start_slot
+ num_viewports
; i
++) {
548 int idx
= i
- start_slot
;
549 int offset
= i
* 4 * 6;
551 viewport
= CALLOC_STRUCT(si_state_viewport
);
554 pm4
= &viewport
->pm4
;
556 viewport
->viewport
= state
[idx
];
557 si_pm4_set_reg(pm4
, R_02843C_PA_CL_VPORT_XSCALE
+ offset
, fui(state
[idx
].scale
[0]));
558 si_pm4_set_reg(pm4
, R_028440_PA_CL_VPORT_XOFFSET
+ offset
, fui(state
[idx
].translate
[0]));
559 si_pm4_set_reg(pm4
, R_028444_PA_CL_VPORT_YSCALE
+ offset
, fui(state
[idx
].scale
[1]));
560 si_pm4_set_reg(pm4
, R_028448_PA_CL_VPORT_YOFFSET
+ offset
, fui(state
[idx
].translate
[1]));
561 si_pm4_set_reg(pm4
, R_02844C_PA_CL_VPORT_ZSCALE
+ offset
, fui(state
[idx
].scale
[2]));
562 si_pm4_set_reg(pm4
, R_028450_PA_CL_VPORT_ZOFFSET
+ offset
, fui(state
[idx
].translate
[2]));
564 si_pm4_set_state(sctx
, viewport
[i
], viewport
);
569 * inferred state between framebuffer and rasterizer
571 static void si_update_fb_rs_state(struct si_context
*sctx
)
573 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
574 struct si_pm4_state
*pm4
;
577 if (!rs
|| !sctx
->framebuffer
.state
.zsbuf
)
580 offset_units
= sctx
->queued
.named
.rasterizer
->offset_units
;
581 switch (sctx
->framebuffer
.state
.zsbuf
->texture
->format
) {
582 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
583 case PIPE_FORMAT_X8Z24_UNORM
:
584 case PIPE_FORMAT_Z24X8_UNORM
:
585 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
586 offset_units
*= 2.0f
;
588 case PIPE_FORMAT_Z32_FLOAT
:
589 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
590 offset_units
*= 1.0f
;
592 case PIPE_FORMAT_Z16_UNORM
:
593 offset_units
*= 4.0f
;
599 pm4
= CALLOC_STRUCT(si_pm4_state
);
604 /* FIXME some of those reg can be computed with cso */
605 si_pm4_set_reg(pm4
, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE
,
606 fui(sctx
->queued
.named
.rasterizer
->offset_scale
));
607 si_pm4_set_reg(pm4
, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET
, fui(offset_units
));
608 si_pm4_set_reg(pm4
, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE
,
609 fui(sctx
->queued
.named
.rasterizer
->offset_scale
));
610 si_pm4_set_reg(pm4
, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET
, fui(offset_units
));
612 si_pm4_set_state(sctx
, fb_rs
, pm4
);
619 static uint32_t si_translate_fill(uint32_t func
)
622 case PIPE_POLYGON_MODE_FILL
:
623 return V_028814_X_DRAW_TRIANGLES
;
624 case PIPE_POLYGON_MODE_LINE
:
625 return V_028814_X_DRAW_LINES
;
626 case PIPE_POLYGON_MODE_POINT
:
627 return V_028814_X_DRAW_POINTS
;
630 return V_028814_X_DRAW_POINTS
;
634 static void *si_create_rs_state(struct pipe_context
*ctx
,
635 const struct pipe_rasterizer_state
*state
)
637 struct si_state_rasterizer
*rs
= CALLOC_STRUCT(si_state_rasterizer
);
638 struct si_pm4_state
*pm4
= &rs
->pm4
;
640 float psize_min
, psize_max
;
646 rs
->two_side
= state
->light_twoside
;
647 rs
->multisample_enable
= state
->multisample
;
648 rs
->clip_plane_enable
= state
->clip_plane_enable
;
649 rs
->line_stipple_enable
= state
->line_stipple_enable
;
650 rs
->poly_stipple_enable
= state
->poly_stipple_enable
;
651 rs
->line_smooth
= state
->line_smooth
;
652 rs
->poly_smooth
= state
->poly_smooth
;
654 rs
->flatshade
= state
->flatshade
;
655 rs
->sprite_coord_enable
= state
->sprite_coord_enable
;
656 rs
->pa_sc_line_stipple
= state
->line_stipple_enable
?
657 S_028A0C_LINE_PATTERN(state
->line_stipple_pattern
) |
658 S_028A0C_REPEAT_COUNT(state
->line_stipple_factor
) : 0;
659 rs
->pa_cl_clip_cntl
=
660 S_028810_PS_UCP_MODE(3) |
661 S_028810_DX_CLIP_SPACE_DEF(state
->clip_halfz
) |
662 S_028810_ZCLIP_NEAR_DISABLE(!state
->depth_clip
) |
663 S_028810_ZCLIP_FAR_DISABLE(!state
->depth_clip
) |
664 S_028810_DX_RASTERIZATION_KILL(state
->rasterizer_discard
) |
665 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
668 rs
->offset_units
= state
->offset_units
;
669 rs
->offset_scale
= state
->offset_scale
* 16.0f
;
671 si_pm4_set_reg(pm4
, R_0286D4_SPI_INTERP_CONTROL_0
,
672 S_0286D4_FLAT_SHADE_ENA(1) |
673 S_0286D4_PNT_SPRITE_ENA(1) |
674 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S
) |
675 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T
) |
676 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0
) |
677 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1
) |
678 S_0286D4_PNT_SPRITE_TOP_1(state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
));
680 /* point size 12.4 fixed point */
681 tmp
= (unsigned)(state
->point_size
* 8.0);
682 si_pm4_set_reg(pm4
, R_028A00_PA_SU_POINT_SIZE
, S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
));
684 if (state
->point_size_per_vertex
) {
685 psize_min
= util_get_min_point_size(state
);
688 /* Force the point size to be as if the vertex output was disabled. */
689 psize_min
= state
->point_size
;
690 psize_max
= state
->point_size
;
692 /* Divide by two, because 0.5 = 1 pixel. */
693 si_pm4_set_reg(pm4
, R_028A04_PA_SU_POINT_MINMAX
,
694 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min
/2)) |
695 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max
/2)));
697 tmp
= (unsigned)state
->line_width
* 8;
698 si_pm4_set_reg(pm4
, R_028A08_PA_SU_LINE_CNTL
, S_028A08_WIDTH(tmp
));
699 si_pm4_set_reg(pm4
, R_028A48_PA_SC_MODE_CNTL_0
,
700 S_028A48_LINE_STIPPLE_ENABLE(state
->line_stipple_enable
) |
701 S_028A48_MSAA_ENABLE(state
->multisample
||
702 state
->poly_smooth
||
703 state
->line_smooth
) |
704 S_028A48_VPORT_SCISSOR_ENABLE(state
->scissor
));
706 si_pm4_set_reg(pm4
, R_028BE4_PA_SU_VTX_CNTL
,
707 S_028BE4_PIX_CENTER(state
->half_pixel_center
) |
708 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH
));
710 si_pm4_set_reg(pm4
, R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, fui(state
->offset_clamp
));
711 si_pm4_set_reg(pm4
, R_028814_PA_SU_SC_MODE_CNTL
,
712 S_028814_PROVOKING_VTX_LAST(!state
->flatshade_first
) |
713 S_028814_CULL_FRONT((state
->cull_face
& PIPE_FACE_FRONT
) ? 1 : 0) |
714 S_028814_CULL_BACK((state
->cull_face
& PIPE_FACE_BACK
) ? 1 : 0) |
715 S_028814_FACE(!state
->front_ccw
) |
716 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state
, state
->fill_front
)) |
717 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state
, state
->fill_back
)) |
718 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_point
|| state
->offset_line
) |
719 S_028814_POLY_MODE(state
->fill_front
!= PIPE_POLYGON_MODE_FILL
||
720 state
->fill_back
!= PIPE_POLYGON_MODE_FILL
) |
721 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state
->fill_front
)) |
722 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state
->fill_back
)));
726 static void si_bind_rs_state(struct pipe_context
*ctx
, void *state
)
728 struct si_context
*sctx
= (struct si_context
*)ctx
;
729 struct si_state_rasterizer
*old_rs
=
730 (struct si_state_rasterizer
*)sctx
->queued
.named
.rasterizer
;
731 struct si_state_rasterizer
*rs
= (struct si_state_rasterizer
*)state
;
736 if (sctx
->framebuffer
.nr_samples
> 1 &&
737 (!old_rs
|| old_rs
->multisample_enable
!= rs
->multisample_enable
))
738 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
740 si_pm4_bind_state(sctx
, rasterizer
, rs
);
741 si_update_fb_rs_state(sctx
);
743 si_mark_atom_dirty(sctx
, &sctx
->clip_regs
);
746 static void si_delete_rs_state(struct pipe_context
*ctx
, void *state
)
748 struct si_context
*sctx
= (struct si_context
*)ctx
;
749 si_pm4_delete_state(sctx
, rasterizer
, (struct si_state_rasterizer
*)state
);
753 * infeered state between dsa and stencil ref
755 static void si_update_dsa_stencil_ref(struct si_context
*sctx
)
757 struct si_pm4_state
*pm4
;
758 struct pipe_stencil_ref
*ref
= &sctx
->stencil_ref
;
759 struct si_state_dsa
*dsa
= sctx
->queued
.named
.dsa
;
764 pm4
= CALLOC_STRUCT(si_pm4_state
);
768 si_pm4_set_reg(pm4
, R_028430_DB_STENCILREFMASK
,
769 S_028430_STENCILTESTVAL(ref
->ref_value
[0]) |
770 S_028430_STENCILMASK(dsa
->valuemask
[0]) |
771 S_028430_STENCILWRITEMASK(dsa
->writemask
[0]) |
772 S_028430_STENCILOPVAL(1));
773 si_pm4_set_reg(pm4
, R_028434_DB_STENCILREFMASK_BF
,
774 S_028434_STENCILTESTVAL_BF(ref
->ref_value
[1]) |
775 S_028434_STENCILMASK_BF(dsa
->valuemask
[1]) |
776 S_028434_STENCILWRITEMASK_BF(dsa
->writemask
[1]) |
777 S_028434_STENCILOPVAL_BF(1));
779 si_pm4_set_state(sctx
, dsa_stencil_ref
, pm4
);
782 static void si_set_pipe_stencil_ref(struct pipe_context
*ctx
,
783 const struct pipe_stencil_ref
*state
)
785 struct si_context
*sctx
= (struct si_context
*)ctx
;
786 sctx
->stencil_ref
= *state
;
787 si_update_dsa_stencil_ref(sctx
);
795 static uint32_t si_translate_stencil_op(int s_op
)
798 case PIPE_STENCIL_OP_KEEP
:
799 return V_02842C_STENCIL_KEEP
;
800 case PIPE_STENCIL_OP_ZERO
:
801 return V_02842C_STENCIL_ZERO
;
802 case PIPE_STENCIL_OP_REPLACE
:
803 return V_02842C_STENCIL_REPLACE_TEST
;
804 case PIPE_STENCIL_OP_INCR
:
805 return V_02842C_STENCIL_ADD_CLAMP
;
806 case PIPE_STENCIL_OP_DECR
:
807 return V_02842C_STENCIL_SUB_CLAMP
;
808 case PIPE_STENCIL_OP_INCR_WRAP
:
809 return V_02842C_STENCIL_ADD_WRAP
;
810 case PIPE_STENCIL_OP_DECR_WRAP
:
811 return V_02842C_STENCIL_SUB_WRAP
;
812 case PIPE_STENCIL_OP_INVERT
:
813 return V_02842C_STENCIL_INVERT
;
815 R600_ERR("Unknown stencil op %d", s_op
);
822 static void *si_create_dsa_state(struct pipe_context
*ctx
,
823 const struct pipe_depth_stencil_alpha_state
*state
)
825 struct si_state_dsa
*dsa
= CALLOC_STRUCT(si_state_dsa
);
826 struct si_pm4_state
*pm4
= &dsa
->pm4
;
827 unsigned db_depth_control
;
828 uint32_t db_stencil_control
= 0;
834 dsa
->valuemask
[0] = state
->stencil
[0].valuemask
;
835 dsa
->valuemask
[1] = state
->stencil
[1].valuemask
;
836 dsa
->writemask
[0] = state
->stencil
[0].writemask
;
837 dsa
->writemask
[1] = state
->stencil
[1].writemask
;
839 db_depth_control
= S_028800_Z_ENABLE(state
->depth
.enabled
) |
840 S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
841 S_028800_ZFUNC(state
->depth
.func
) |
842 S_028800_DEPTH_BOUNDS_ENABLE(state
->depth
.bounds_test
);
845 if (state
->stencil
[0].enabled
) {
846 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
847 db_depth_control
|= S_028800_STENCILFUNC(state
->stencil
[0].func
);
848 db_stencil_control
|= S_02842C_STENCILFAIL(si_translate_stencil_op(state
->stencil
[0].fail_op
));
849 db_stencil_control
|= S_02842C_STENCILZPASS(si_translate_stencil_op(state
->stencil
[0].zpass_op
));
850 db_stencil_control
|= S_02842C_STENCILZFAIL(si_translate_stencil_op(state
->stencil
[0].zfail_op
));
852 if (state
->stencil
[1].enabled
) {
853 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
854 db_depth_control
|= S_028800_STENCILFUNC_BF(state
->stencil
[1].func
);
855 db_stencil_control
|= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state
->stencil
[1].fail_op
));
856 db_stencil_control
|= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state
->stencil
[1].zpass_op
));
857 db_stencil_control
|= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state
->stencil
[1].zfail_op
));
862 if (state
->alpha
.enabled
) {
863 dsa
->alpha_func
= state
->alpha
.func
;
865 si_pm4_set_reg(pm4
, R_00B030_SPI_SHADER_USER_DATA_PS_0
+
866 SI_SGPR_ALPHA_REF
* 4, fui(state
->alpha
.ref_value
));
868 dsa
->alpha_func
= PIPE_FUNC_ALWAYS
;
871 si_pm4_set_reg(pm4
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
872 si_pm4_set_reg(pm4
, R_02842C_DB_STENCIL_CONTROL
, db_stencil_control
);
873 if (state
->depth
.bounds_test
) {
874 si_pm4_set_reg(pm4
, R_028020_DB_DEPTH_BOUNDS_MIN
, fui(state
->depth
.bounds_min
));
875 si_pm4_set_reg(pm4
, R_028024_DB_DEPTH_BOUNDS_MAX
, fui(state
->depth
.bounds_max
));
881 static void si_bind_dsa_state(struct pipe_context
*ctx
, void *state
)
883 struct si_context
*sctx
= (struct si_context
*)ctx
;
884 struct si_state_dsa
*dsa
= state
;
889 si_pm4_bind_state(sctx
, dsa
, dsa
);
890 si_update_dsa_stencil_ref(sctx
);
893 static void si_delete_dsa_state(struct pipe_context
*ctx
, void *state
)
895 struct si_context
*sctx
= (struct si_context
*)ctx
;
896 si_pm4_delete_state(sctx
, dsa
, (struct si_state_dsa
*)state
);
899 static void *si_create_db_flush_dsa(struct si_context
*sctx
)
901 struct pipe_depth_stencil_alpha_state dsa
= {};
903 return sctx
->b
.b
.create_depth_stencil_alpha_state(&sctx
->b
.b
, &dsa
);
906 /* DB RENDER STATE */
908 static void si_set_occlusion_query_state(struct pipe_context
*ctx
, bool enable
)
910 struct si_context
*sctx
= (struct si_context
*)ctx
;
912 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
915 static void si_emit_db_render_state(struct si_context
*sctx
, struct r600_atom
*state
)
917 struct radeon_winsys_cs
*cs
= sctx
->b
.rings
.gfx
.cs
;
918 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
919 unsigned db_shader_control
;
921 r600_write_context_reg_seq(cs
, R_028000_DB_RENDER_CONTROL
, 2);
923 /* DB_RENDER_CONTROL */
924 if (sctx
->dbcb_depth_copy_enabled
||
925 sctx
->dbcb_stencil_copy_enabled
) {
927 S_028000_DEPTH_COPY(sctx
->dbcb_depth_copy_enabled
) |
928 S_028000_STENCIL_COPY(sctx
->dbcb_stencil_copy_enabled
) |
929 S_028000_COPY_CENTROID(1) |
930 S_028000_COPY_SAMPLE(sctx
->dbcb_copy_sample
));
931 } else if (sctx
->db_inplace_flush_enabled
) {
933 S_028000_DEPTH_COMPRESS_DISABLE(1) |
934 S_028000_STENCIL_COMPRESS_DISABLE(1));
935 } else if (sctx
->db_depth_clear
) {
936 radeon_emit(cs
, S_028000_DEPTH_CLEAR_ENABLE(1));
941 /* DB_COUNT_CONTROL (occlusion queries) */
942 if (sctx
->b
.num_occlusion_queries
> 0) {
943 if (sctx
->b
.chip_class
>= CIK
) {
945 S_028004_PERFECT_ZPASS_COUNTS(1) |
946 S_028004_SAMPLE_RATE(sctx
->framebuffer
.log_samples
) |
947 S_028004_ZPASS_ENABLE(1) |
948 S_028004_SLICE_EVEN_ENABLE(1) |
949 S_028004_SLICE_ODD_ENABLE(1));
952 S_028004_PERFECT_ZPASS_COUNTS(1) |
953 S_028004_SAMPLE_RATE(sctx
->framebuffer
.log_samples
));
956 /* Disable occlusion queries. */
957 if (sctx
->b
.chip_class
>= CIK
) {
960 radeon_emit(cs
, S_028004_ZPASS_INCREMENT_DISABLE(1));
964 /* DB_RENDER_OVERRIDE2 */
965 if (sctx
->db_depth_disable_expclear
) {
966 r600_write_context_reg(cs
, R_028010_DB_RENDER_OVERRIDE2
,
967 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(1));
969 r600_write_context_reg(cs
, R_028010_DB_RENDER_OVERRIDE2
, 0);
972 db_shader_control
= S_02880C_ALPHA_TO_MASK_DISABLE(sctx
->framebuffer
.cb0_is_integer
) |
973 sctx
->ps_db_shader_control
;
975 /* Bug workaround for smoothing (overrasterization) on SI. */
976 if (sctx
->b
.chip_class
== SI
&& sctx
->smoothing_enabled
)
977 db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
);
979 db_shader_control
|= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
);
981 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
982 if (sctx
->framebuffer
.nr_samples
<= 1 || (rs
&& !rs
->multisample_enable
))
983 db_shader_control
&= C_02880C_MASK_EXPORT_ENABLE
;
985 r600_write_context_reg(cs
, R_02880C_DB_SHADER_CONTROL
,
992 static uint32_t si_translate_colorformat(enum pipe_format format
)
994 const struct util_format_description
*desc
= util_format_description(format
);
996 #define HAS_SIZE(x,y,z,w) \
997 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
998 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1000 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
1001 return V_028C70_COLOR_10_11_11
;
1003 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
1004 return V_028C70_COLOR_INVALID
;
1006 switch (desc
->nr_channels
) {
1008 switch (desc
->channel
[0].size
) {
1010 return V_028C70_COLOR_8
;
1012 return V_028C70_COLOR_16
;
1014 return V_028C70_COLOR_32
;
1018 if (desc
->channel
[0].size
== desc
->channel
[1].size
) {
1019 switch (desc
->channel
[0].size
) {
1021 return V_028C70_COLOR_8_8
;
1023 return V_028C70_COLOR_16_16
;
1025 return V_028C70_COLOR_32_32
;
1027 } else if (HAS_SIZE(8,24,0,0)) {
1028 return V_028C70_COLOR_24_8
;
1029 } else if (HAS_SIZE(24,8,0,0)) {
1030 return V_028C70_COLOR_8_24
;
1034 if (HAS_SIZE(5,6,5,0)) {
1035 return V_028C70_COLOR_5_6_5
;
1036 } else if (HAS_SIZE(32,8,24,0)) {
1037 return V_028C70_COLOR_X24_8_32_FLOAT
;
1041 if (desc
->channel
[0].size
== desc
->channel
[1].size
&&
1042 desc
->channel
[0].size
== desc
->channel
[2].size
&&
1043 desc
->channel
[0].size
== desc
->channel
[3].size
) {
1044 switch (desc
->channel
[0].size
) {
1046 return V_028C70_COLOR_4_4_4_4
;
1048 return V_028C70_COLOR_8_8_8_8
;
1050 return V_028C70_COLOR_16_16_16_16
;
1052 return V_028C70_COLOR_32_32_32_32
;
1054 } else if (HAS_SIZE(5,5,5,1)) {
1055 return V_028C70_COLOR_1_5_5_5
;
1056 } else if (HAS_SIZE(10,10,10,2)) {
1057 return V_028C70_COLOR_2_10_10_10
;
1061 return V_028C70_COLOR_INVALID
;
1064 static uint32_t si_colorformat_endian_swap(uint32_t colorformat
)
1066 if (SI_BIG_ENDIAN
) {
1067 switch(colorformat
) {
1068 /* 8-bit buffers. */
1069 case V_028C70_COLOR_8
:
1070 return V_028C70_ENDIAN_NONE
;
1072 /* 16-bit buffers. */
1073 case V_028C70_COLOR_5_6_5
:
1074 case V_028C70_COLOR_1_5_5_5
:
1075 case V_028C70_COLOR_4_4_4_4
:
1076 case V_028C70_COLOR_16
:
1077 case V_028C70_COLOR_8_8
:
1078 return V_028C70_ENDIAN_8IN16
;
1080 /* 32-bit buffers. */
1081 case V_028C70_COLOR_8_8_8_8
:
1082 case V_028C70_COLOR_2_10_10_10
:
1083 case V_028C70_COLOR_8_24
:
1084 case V_028C70_COLOR_24_8
:
1085 case V_028C70_COLOR_16_16
:
1086 return V_028C70_ENDIAN_8IN32
;
1088 /* 64-bit buffers. */
1089 case V_028C70_COLOR_16_16_16_16
:
1090 return V_028C70_ENDIAN_8IN16
;
1092 case V_028C70_COLOR_32_32
:
1093 return V_028C70_ENDIAN_8IN32
;
1095 /* 128-bit buffers. */
1096 case V_028C70_COLOR_32_32_32_32
:
1097 return V_028C70_ENDIAN_8IN32
;
1099 return V_028C70_ENDIAN_NONE
; /* Unsupported. */
1102 return V_028C70_ENDIAN_NONE
;
1106 /* Returns the size in bits of the widest component of a CB format */
1107 static unsigned si_colorformat_max_comp_size(uint32_t colorformat
)
1109 switch(colorformat
) {
1110 case V_028C70_COLOR_4_4_4_4
:
1113 case V_028C70_COLOR_1_5_5_5
:
1114 case V_028C70_COLOR_5_5_5_1
:
1117 case V_028C70_COLOR_5_6_5
:
1120 case V_028C70_COLOR_8
:
1121 case V_028C70_COLOR_8_8
:
1122 case V_028C70_COLOR_8_8_8_8
:
1125 case V_028C70_COLOR_10_10_10_2
:
1126 case V_028C70_COLOR_2_10_10_10
:
1129 case V_028C70_COLOR_10_11_11
:
1130 case V_028C70_COLOR_11_11_10
:
1133 case V_028C70_COLOR_16
:
1134 case V_028C70_COLOR_16_16
:
1135 case V_028C70_COLOR_16_16_16_16
:
1138 case V_028C70_COLOR_8_24
:
1139 case V_028C70_COLOR_24_8
:
1142 case V_028C70_COLOR_32
:
1143 case V_028C70_COLOR_32_32
:
1144 case V_028C70_COLOR_32_32_32_32
:
1145 case V_028C70_COLOR_X24_8_32_FLOAT
:
1149 assert(!"Unknown maximum component size");
1153 static uint32_t si_translate_dbformat(enum pipe_format format
)
1156 case PIPE_FORMAT_Z16_UNORM
:
1157 return V_028040_Z_16
;
1158 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1159 case PIPE_FORMAT_X8Z24_UNORM
:
1160 case PIPE_FORMAT_Z24X8_UNORM
:
1161 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1162 return V_028040_Z_24
; /* deprecated on SI */
1163 case PIPE_FORMAT_Z32_FLOAT
:
1164 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1165 return V_028040_Z_32_FLOAT
;
1167 return V_028040_Z_INVALID
;
1172 * Texture translation
1175 static uint32_t si_translate_texformat(struct pipe_screen
*screen
,
1176 enum pipe_format format
,
1177 const struct util_format_description
*desc
,
1180 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1181 bool enable_compressed_formats
= (sscreen
->b
.info
.drm_major
== 2 &&
1182 sscreen
->b
.info
.drm_minor
>= 31) ||
1183 sscreen
->b
.info
.drm_major
== 3;
1184 boolean uniform
= TRUE
;
1187 /* Colorspace (return non-RGB formats directly). */
1188 switch (desc
->colorspace
) {
1189 /* Depth stencil formats */
1190 case UTIL_FORMAT_COLORSPACE_ZS
:
1192 case PIPE_FORMAT_Z16_UNORM
:
1193 return V_008F14_IMG_DATA_FORMAT_16
;
1194 case PIPE_FORMAT_X24S8_UINT
:
1195 case PIPE_FORMAT_Z24X8_UNORM
:
1196 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1197 return V_008F14_IMG_DATA_FORMAT_8_24
;
1198 case PIPE_FORMAT_X8Z24_UNORM
:
1199 case PIPE_FORMAT_S8X24_UINT
:
1200 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1201 return V_008F14_IMG_DATA_FORMAT_24_8
;
1202 case PIPE_FORMAT_S8_UINT
:
1203 return V_008F14_IMG_DATA_FORMAT_8
;
1204 case PIPE_FORMAT_Z32_FLOAT
:
1205 return V_008F14_IMG_DATA_FORMAT_32
;
1206 case PIPE_FORMAT_X32_S8X24_UINT
:
1207 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1208 return V_008F14_IMG_DATA_FORMAT_X24_8_32
;
1213 case UTIL_FORMAT_COLORSPACE_YUV
:
1214 goto out_unknown
; /* TODO */
1216 case UTIL_FORMAT_COLORSPACE_SRGB
:
1217 if (desc
->nr_channels
!= 4 && desc
->nr_channels
!= 1)
1225 if (desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
) {
1226 if (!enable_compressed_formats
)
1230 case PIPE_FORMAT_RGTC1_SNORM
:
1231 case PIPE_FORMAT_LATC1_SNORM
:
1232 case PIPE_FORMAT_RGTC1_UNORM
:
1233 case PIPE_FORMAT_LATC1_UNORM
:
1234 return V_008F14_IMG_DATA_FORMAT_BC4
;
1235 case PIPE_FORMAT_RGTC2_SNORM
:
1236 case PIPE_FORMAT_LATC2_SNORM
:
1237 case PIPE_FORMAT_RGTC2_UNORM
:
1238 case PIPE_FORMAT_LATC2_UNORM
:
1239 return V_008F14_IMG_DATA_FORMAT_BC5
;
1245 if (desc
->layout
== UTIL_FORMAT_LAYOUT_BPTC
) {
1246 if (!enable_compressed_formats
)
1250 case PIPE_FORMAT_BPTC_RGBA_UNORM
:
1251 case PIPE_FORMAT_BPTC_SRGBA
:
1252 return V_008F14_IMG_DATA_FORMAT_BC7
;
1253 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
1254 case PIPE_FORMAT_BPTC_RGB_UFLOAT
:
1255 return V_008F14_IMG_DATA_FORMAT_BC6
;
1261 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
1263 case PIPE_FORMAT_R8G8_B8G8_UNORM
:
1264 case PIPE_FORMAT_G8R8_B8R8_UNORM
:
1265 return V_008F14_IMG_DATA_FORMAT_GB_GR
;
1266 case PIPE_FORMAT_G8R8_G8B8_UNORM
:
1267 case PIPE_FORMAT_R8G8_R8B8_UNORM
:
1268 return V_008F14_IMG_DATA_FORMAT_BG_RG
;
1274 if (desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
1275 if (!enable_compressed_formats
)
1278 if (!util_format_s3tc_enabled
) {
1283 case PIPE_FORMAT_DXT1_RGB
:
1284 case PIPE_FORMAT_DXT1_RGBA
:
1285 case PIPE_FORMAT_DXT1_SRGB
:
1286 case PIPE_FORMAT_DXT1_SRGBA
:
1287 return V_008F14_IMG_DATA_FORMAT_BC1
;
1288 case PIPE_FORMAT_DXT3_RGBA
:
1289 case PIPE_FORMAT_DXT3_SRGBA
:
1290 return V_008F14_IMG_DATA_FORMAT_BC2
;
1291 case PIPE_FORMAT_DXT5_RGBA
:
1292 case PIPE_FORMAT_DXT5_SRGBA
:
1293 return V_008F14_IMG_DATA_FORMAT_BC3
;
1299 if (format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
1300 return V_008F14_IMG_DATA_FORMAT_5_9_9_9
;
1301 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
1302 return V_008F14_IMG_DATA_FORMAT_10_11_11
;
1305 /* R8G8Bx_SNORM - TODO CxV8U8 */
1307 /* See whether the components are of the same size. */
1308 for (i
= 1; i
< desc
->nr_channels
; i
++) {
1309 uniform
= uniform
&& desc
->channel
[0].size
== desc
->channel
[i
].size
;
1312 /* Non-uniform formats. */
1314 switch(desc
->nr_channels
) {
1316 if (desc
->channel
[0].size
== 5 &&
1317 desc
->channel
[1].size
== 6 &&
1318 desc
->channel
[2].size
== 5) {
1319 return V_008F14_IMG_DATA_FORMAT_5_6_5
;
1323 if (desc
->channel
[0].size
== 5 &&
1324 desc
->channel
[1].size
== 5 &&
1325 desc
->channel
[2].size
== 5 &&
1326 desc
->channel
[3].size
== 1) {
1327 return V_008F14_IMG_DATA_FORMAT_1_5_5_5
;
1329 if (desc
->channel
[0].size
== 10 &&
1330 desc
->channel
[1].size
== 10 &&
1331 desc
->channel
[2].size
== 10 &&
1332 desc
->channel
[3].size
== 2) {
1333 return V_008F14_IMG_DATA_FORMAT_2_10_10_10
;
1340 if (first_non_void
< 0 || first_non_void
> 3)
1343 /* uniform formats */
1344 switch (desc
->channel
[first_non_void
].size
) {
1346 switch (desc
->nr_channels
) {
1347 #if 0 /* Not supported for render targets */
1349 return V_008F14_IMG_DATA_FORMAT_4_4
;
1352 return V_008F14_IMG_DATA_FORMAT_4_4_4_4
;
1356 switch (desc
->nr_channels
) {
1358 return V_008F14_IMG_DATA_FORMAT_8
;
1360 return V_008F14_IMG_DATA_FORMAT_8_8
;
1362 return V_008F14_IMG_DATA_FORMAT_8_8_8_8
;
1366 switch (desc
->nr_channels
) {
1368 return V_008F14_IMG_DATA_FORMAT_16
;
1370 return V_008F14_IMG_DATA_FORMAT_16_16
;
1372 return V_008F14_IMG_DATA_FORMAT_16_16_16_16
;
1376 switch (desc
->nr_channels
) {
1378 return V_008F14_IMG_DATA_FORMAT_32
;
1380 return V_008F14_IMG_DATA_FORMAT_32_32
;
1381 #if 0 /* Not supported for render targets */
1383 return V_008F14_IMG_DATA_FORMAT_32_32_32
;
1386 return V_008F14_IMG_DATA_FORMAT_32_32_32_32
;
1391 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1395 static unsigned si_tex_wrap(unsigned wrap
)
1399 case PIPE_TEX_WRAP_REPEAT
:
1400 return V_008F30_SQ_TEX_WRAP
;
1401 case PIPE_TEX_WRAP_CLAMP
:
1402 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER
;
1403 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
1404 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL
;
1405 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
1406 return V_008F30_SQ_TEX_CLAMP_BORDER
;
1407 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
1408 return V_008F30_SQ_TEX_MIRROR
;
1409 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
1410 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
1411 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
1412 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
1413 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
1414 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER
;
1418 static unsigned si_tex_filter(unsigned filter
)
1422 case PIPE_TEX_FILTER_NEAREST
:
1423 return V_008F38_SQ_TEX_XY_FILTER_POINT
;
1424 case PIPE_TEX_FILTER_LINEAR
:
1425 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR
;
1429 static unsigned si_tex_mipfilter(unsigned filter
)
1432 case PIPE_TEX_MIPFILTER_NEAREST
:
1433 return V_008F38_SQ_TEX_Z_FILTER_POINT
;
1434 case PIPE_TEX_MIPFILTER_LINEAR
:
1435 return V_008F38_SQ_TEX_Z_FILTER_LINEAR
;
1437 case PIPE_TEX_MIPFILTER_NONE
:
1438 return V_008F38_SQ_TEX_Z_FILTER_NONE
;
1442 static unsigned si_tex_compare(unsigned compare
)
1446 case PIPE_FUNC_NEVER
:
1447 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
1448 case PIPE_FUNC_LESS
:
1449 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS
;
1450 case PIPE_FUNC_EQUAL
:
1451 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL
;
1452 case PIPE_FUNC_LEQUAL
:
1453 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
1454 case PIPE_FUNC_GREATER
:
1455 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER
;
1456 case PIPE_FUNC_NOTEQUAL
:
1457 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
1458 case PIPE_FUNC_GEQUAL
:
1459 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
1460 case PIPE_FUNC_ALWAYS
:
1461 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
1465 static unsigned si_tex_dim(unsigned dim
, unsigned nr_samples
)
1469 case PIPE_TEXTURE_1D
:
1470 return V_008F1C_SQ_RSRC_IMG_1D
;
1471 case PIPE_TEXTURE_1D_ARRAY
:
1472 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY
;
1473 case PIPE_TEXTURE_2D
:
1474 case PIPE_TEXTURE_RECT
:
1475 return nr_samples
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA
:
1476 V_008F1C_SQ_RSRC_IMG_2D
;
1477 case PIPE_TEXTURE_2D_ARRAY
:
1478 return nr_samples
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
:
1479 V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
1480 case PIPE_TEXTURE_3D
:
1481 return V_008F1C_SQ_RSRC_IMG_3D
;
1482 case PIPE_TEXTURE_CUBE
:
1483 case PIPE_TEXTURE_CUBE_ARRAY
:
1484 return V_008F1C_SQ_RSRC_IMG_CUBE
;
1489 * Format support testing
1492 static bool si_is_sampler_format_supported(struct pipe_screen
*screen
, enum pipe_format format
)
1494 return si_translate_texformat(screen
, format
, util_format_description(format
),
1495 util_format_get_first_non_void_channel(format
)) != ~0U;
1498 static uint32_t si_translate_buffer_dataformat(struct pipe_screen
*screen
,
1499 const struct util_format_description
*desc
,
1502 unsigned type
= desc
->channel
[first_non_void
].type
;
1505 if (type
== UTIL_FORMAT_TYPE_FIXED
)
1506 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
1508 if (desc
->format
== PIPE_FORMAT_R11G11B10_FLOAT
)
1509 return V_008F0C_BUF_DATA_FORMAT_10_11_11
;
1511 if (desc
->nr_channels
== 4 &&
1512 desc
->channel
[0].size
== 10 &&
1513 desc
->channel
[1].size
== 10 &&
1514 desc
->channel
[2].size
== 10 &&
1515 desc
->channel
[3].size
== 2)
1516 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10
;
1518 /* See whether the components are of the same size. */
1519 for (i
= 0; i
< desc
->nr_channels
; i
++) {
1520 if (desc
->channel
[first_non_void
].size
!= desc
->channel
[i
].size
)
1521 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
1524 switch (desc
->channel
[first_non_void
].size
) {
1526 switch (desc
->nr_channels
) {
1528 return V_008F0C_BUF_DATA_FORMAT_8
;
1530 return V_008F0C_BUF_DATA_FORMAT_8_8
;
1533 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8
;
1537 switch (desc
->nr_channels
) {
1539 return V_008F0C_BUF_DATA_FORMAT_16
;
1541 return V_008F0C_BUF_DATA_FORMAT_16_16
;
1544 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16
;
1548 /* From the Southern Islands ISA documentation about MTBUF:
1549 * 'Memory reads of data in memory that is 32 or 64 bits do not
1550 * undergo any format conversion.'
1552 if (type
!= UTIL_FORMAT_TYPE_FLOAT
&&
1553 !desc
->channel
[first_non_void
].pure_integer
)
1554 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
1556 switch (desc
->nr_channels
) {
1558 return V_008F0C_BUF_DATA_FORMAT_32
;
1560 return V_008F0C_BUF_DATA_FORMAT_32_32
;
1562 return V_008F0C_BUF_DATA_FORMAT_32_32_32
;
1564 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
1569 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
1572 static uint32_t si_translate_buffer_numformat(struct pipe_screen
*screen
,
1573 const struct util_format_description
*desc
,
1576 if (desc
->format
== PIPE_FORMAT_R11G11B10_FLOAT
)
1577 return V_008F0C_BUF_NUM_FORMAT_FLOAT
;
1579 switch (desc
->channel
[first_non_void
].type
) {
1580 case UTIL_FORMAT_TYPE_SIGNED
:
1581 if (desc
->channel
[first_non_void
].normalized
)
1582 return V_008F0C_BUF_NUM_FORMAT_SNORM
;
1583 else if (desc
->channel
[first_non_void
].pure_integer
)
1584 return V_008F0C_BUF_NUM_FORMAT_SINT
;
1586 return V_008F0C_BUF_NUM_FORMAT_SSCALED
;
1588 case UTIL_FORMAT_TYPE_UNSIGNED
:
1589 if (desc
->channel
[first_non_void
].normalized
)
1590 return V_008F0C_BUF_NUM_FORMAT_UNORM
;
1591 else if (desc
->channel
[first_non_void
].pure_integer
)
1592 return V_008F0C_BUF_NUM_FORMAT_UINT
;
1594 return V_008F0C_BUF_NUM_FORMAT_USCALED
;
1596 case UTIL_FORMAT_TYPE_FLOAT
:
1598 return V_008F0C_BUF_NUM_FORMAT_FLOAT
;
1602 static bool si_is_vertex_format_supported(struct pipe_screen
*screen
, enum pipe_format format
)
1604 const struct util_format_description
*desc
;
1606 unsigned data_format
;
1608 desc
= util_format_description(format
);
1609 first_non_void
= util_format_get_first_non_void_channel(format
);
1610 data_format
= si_translate_buffer_dataformat(screen
, desc
, first_non_void
);
1611 return data_format
!= V_008F0C_BUF_DATA_FORMAT_INVALID
;
1614 static bool si_is_colorbuffer_format_supported(enum pipe_format format
)
1616 return si_translate_colorformat(format
) != V_028C70_COLOR_INVALID
&&
1617 r600_translate_colorswap(format
) != ~0U;
1620 static bool si_is_zs_format_supported(enum pipe_format format
)
1622 return si_translate_dbformat(format
) != V_028040_Z_INVALID
;
1625 boolean
si_is_format_supported(struct pipe_screen
*screen
,
1626 enum pipe_format format
,
1627 enum pipe_texture_target target
,
1628 unsigned sample_count
,
1631 unsigned retval
= 0;
1633 if (target
>= PIPE_MAX_TEXTURE_TYPES
) {
1634 R600_ERR("r600: unsupported texture type %d\n", target
);
1638 if (!util_format_is_supported(format
, usage
))
1641 if (sample_count
> 1) {
1642 if (!screen
->get_param(screen
, PIPE_CAP_TEXTURE_MULTISAMPLE
))
1645 switch (sample_count
) {
1655 if (usage
& PIPE_BIND_SAMPLER_VIEW
) {
1656 if (target
== PIPE_BUFFER
) {
1657 if (si_is_vertex_format_supported(screen
, format
))
1658 retval
|= PIPE_BIND_SAMPLER_VIEW
;
1660 if (si_is_sampler_format_supported(screen
, format
))
1661 retval
|= PIPE_BIND_SAMPLER_VIEW
;
1665 if ((usage
& (PIPE_BIND_RENDER_TARGET
|
1666 PIPE_BIND_DISPLAY_TARGET
|
1669 PIPE_BIND_BLENDABLE
)) &&
1670 si_is_colorbuffer_format_supported(format
)) {
1672 (PIPE_BIND_RENDER_TARGET
|
1673 PIPE_BIND_DISPLAY_TARGET
|
1676 if (!util_format_is_pure_integer(format
) &&
1677 !util_format_is_depth_or_stencil(format
))
1678 retval
|= usage
& PIPE_BIND_BLENDABLE
;
1681 if ((usage
& PIPE_BIND_DEPTH_STENCIL
) &&
1682 si_is_zs_format_supported(format
)) {
1683 retval
|= PIPE_BIND_DEPTH_STENCIL
;
1686 if ((usage
& PIPE_BIND_VERTEX_BUFFER
) &&
1687 si_is_vertex_format_supported(screen
, format
)) {
1688 retval
|= PIPE_BIND_VERTEX_BUFFER
;
1691 if (usage
& PIPE_BIND_TRANSFER_READ
)
1692 retval
|= PIPE_BIND_TRANSFER_READ
;
1693 if (usage
& PIPE_BIND_TRANSFER_WRITE
)
1694 retval
|= PIPE_BIND_TRANSFER_WRITE
;
1696 return retval
== usage
;
1699 unsigned si_tile_mode_index(struct r600_texture
*rtex
, unsigned level
, bool stencil
)
1701 unsigned tile_mode_index
= 0;
1704 tile_mode_index
= rtex
->surface
.stencil_tiling_index
[level
];
1706 tile_mode_index
= rtex
->surface
.tiling_index
[level
];
1708 return tile_mode_index
;
1712 * framebuffer handling
1715 static void si_initialize_color_surface(struct si_context
*sctx
,
1716 struct r600_surface
*surf
)
1718 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->base
.texture
;
1719 unsigned level
= surf
->base
.u
.tex
.level
;
1720 uint64_t offset
= rtex
->surface
.level
[level
].offset
;
1721 unsigned pitch
, slice
;
1722 unsigned color_info
, color_attrib
, color_pitch
, color_view
;
1723 unsigned tile_mode_index
;
1724 unsigned format
, swap
, ntype
, endian
;
1725 const struct util_format_description
*desc
;
1727 unsigned blend_clamp
= 0, blend_bypass
= 0;
1728 unsigned max_comp_size
;
1730 /* Layered rendering doesn't work with LINEAR_GENERAL.
1731 * (LINEAR_ALIGNED and others work) */
1732 if (rtex
->surface
.level
[level
].mode
== RADEON_SURF_MODE_LINEAR
) {
1733 assert(surf
->base
.u
.tex
.first_layer
== surf
->base
.u
.tex
.last_layer
);
1734 offset
+= rtex
->surface
.level
[level
].slice_size
*
1735 surf
->base
.u
.tex
.first_layer
;
1738 color_view
= S_028C6C_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
1739 S_028C6C_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
1742 pitch
= (rtex
->surface
.level
[level
].nblk_x
) / 8 - 1;
1743 slice
= (rtex
->surface
.level
[level
].nblk_x
* rtex
->surface
.level
[level
].nblk_y
) / 64;
1748 tile_mode_index
= si_tile_mode_index(rtex
, level
, false);
1750 desc
= util_format_description(surf
->base
.format
);
1751 for (i
= 0; i
< 4; i
++) {
1752 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
1756 if (i
== 4 || desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
) {
1757 ntype
= V_028C70_NUMBER_FLOAT
;
1759 ntype
= V_028C70_NUMBER_UNORM
;
1760 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
1761 ntype
= V_028C70_NUMBER_SRGB
;
1762 else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
1763 if (desc
->channel
[i
].pure_integer
) {
1764 ntype
= V_028C70_NUMBER_SINT
;
1766 assert(desc
->channel
[i
].normalized
);
1767 ntype
= V_028C70_NUMBER_SNORM
;
1769 } else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
1770 if (desc
->channel
[i
].pure_integer
) {
1771 ntype
= V_028C70_NUMBER_UINT
;
1773 assert(desc
->channel
[i
].normalized
);
1774 ntype
= V_028C70_NUMBER_UNORM
;
1779 format
= si_translate_colorformat(surf
->base
.format
);
1780 if (format
== V_028C70_COLOR_INVALID
) {
1781 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf
->base
.format
);
1783 assert(format
!= V_028C70_COLOR_INVALID
);
1784 swap
= r600_translate_colorswap(surf
->base
.format
);
1785 if (rtex
->resource
.b
.b
.usage
== PIPE_USAGE_STAGING
) {
1786 endian
= V_028C70_ENDIAN_NONE
;
1788 endian
= si_colorformat_endian_swap(format
);
1791 /* blend clamp should be set for all NORM/SRGB types */
1792 if (ntype
== V_028C70_NUMBER_UNORM
||
1793 ntype
== V_028C70_NUMBER_SNORM
||
1794 ntype
== V_028C70_NUMBER_SRGB
)
1797 /* set blend bypass according to docs if SINT/UINT or
1798 8/24 COLOR variants */
1799 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
1800 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
1801 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
1806 color_info
= S_028C70_FORMAT(format
) |
1807 S_028C70_COMP_SWAP(swap
) |
1808 S_028C70_BLEND_CLAMP(blend_clamp
) |
1809 S_028C70_BLEND_BYPASS(blend_bypass
) |
1810 S_028C70_NUMBER_TYPE(ntype
) |
1811 S_028C70_ENDIAN(endian
);
1813 color_pitch
= S_028C64_TILE_MAX(pitch
);
1815 color_attrib
= S_028C74_TILE_MODE_INDEX(tile_mode_index
) |
1816 S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] == UTIL_FORMAT_SWIZZLE_1
);
1818 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
1819 unsigned log_samples
= util_logbase2(rtex
->resource
.b
.b
.nr_samples
);
1821 color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
1822 S_028C74_NUM_FRAGMENTS(log_samples
);
1824 if (rtex
->fmask
.size
) {
1825 color_info
|= S_028C70_COMPRESSION(1);
1826 unsigned fmask_bankh
= util_logbase2(rtex
->fmask
.bank_height
);
1828 color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(rtex
->fmask
.tile_mode_index
);
1830 if (sctx
->b
.chip_class
== SI
) {
1831 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
1832 color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh
);
1834 if (sctx
->b
.chip_class
>= CIK
) {
1835 color_pitch
|= S_028C64_FMASK_TILE_MAX(rtex
->fmask
.pitch
/ 8 - 1);
1840 offset
+= rtex
->resource
.gpu_address
;
1842 surf
->cb_color_base
= offset
>> 8;
1843 surf
->cb_color_pitch
= color_pitch
;
1844 surf
->cb_color_slice
= S_028C68_TILE_MAX(slice
);
1845 surf
->cb_color_view
= color_view
;
1846 surf
->cb_color_info
= color_info
;
1847 surf
->cb_color_attrib
= color_attrib
;
1849 if (sctx
->b
.chip_class
>= VI
)
1850 surf
->cb_dcc_control
= S_028C78_OVERWRITE_COMBINER_DISABLE(1);
1852 if (rtex
->fmask
.size
) {
1853 surf
->cb_color_fmask
= (offset
+ rtex
->fmask
.offset
) >> 8;
1854 surf
->cb_color_fmask_slice
= S_028C88_TILE_MAX(rtex
->fmask
.slice_tile_max
);
1856 /* This must be set for fast clear to work without FMASK. */
1857 surf
->cb_color_fmask
= surf
->cb_color_base
;
1858 surf
->cb_color_fmask_slice
= surf
->cb_color_slice
;
1859 surf
->cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index
);
1861 if (sctx
->b
.chip_class
== SI
) {
1862 unsigned bankh
= util_logbase2(rtex
->surface
.bankh
);
1863 surf
->cb_color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(bankh
);
1866 if (sctx
->b
.chip_class
>= CIK
) {
1867 surf
->cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(pitch
);
1871 /* Determine pixel shader export format */
1872 max_comp_size
= si_colorformat_max_comp_size(format
);
1873 if (ntype
== V_028C70_NUMBER_SRGB
||
1874 ((ntype
== V_028C70_NUMBER_UNORM
|| ntype
== V_028C70_NUMBER_SNORM
) &&
1875 max_comp_size
<= 10) ||
1876 (ntype
== V_028C70_NUMBER_FLOAT
&& max_comp_size
<= 16)) {
1877 surf
->export_16bpc
= true;
1880 surf
->color_initialized
= true;
1883 static void si_init_depth_surface(struct si_context
*sctx
,
1884 struct r600_surface
*surf
)
1886 struct si_screen
*sscreen
= sctx
->screen
;
1887 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->base
.texture
;
1888 unsigned level
= surf
->base
.u
.tex
.level
;
1889 struct radeon_surf_level
*levelinfo
= &rtex
->surface
.level
[level
];
1890 unsigned format
, tile_mode_index
, array_mode
;
1891 unsigned macro_aspect
, tile_split
, stile_split
, bankh
, bankw
, nbanks
, pipe_config
;
1892 uint32_t z_info
, s_info
, db_depth_info
;
1893 uint64_t z_offs
, s_offs
;
1894 uint32_t db_htile_data_base
, db_htile_surface
, pa_su_poly_offset_db_fmt_cntl
= 0;
1896 switch (sctx
->framebuffer
.state
.zsbuf
->texture
->format
) {
1897 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1898 case PIPE_FORMAT_X8Z24_UNORM
:
1899 case PIPE_FORMAT_Z24X8_UNORM
:
1900 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1901 pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
1903 case PIPE_FORMAT_Z32_FLOAT
:
1904 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1905 pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
1906 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1908 case PIPE_FORMAT_Z16_UNORM
:
1909 pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
1915 format
= si_translate_dbformat(rtex
->resource
.b
.b
.format
);
1917 if (format
== V_028040_Z_INVALID
) {
1918 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex
->resource
.b
.b
.format
);
1920 assert(format
!= V_028040_Z_INVALID
);
1922 s_offs
= z_offs
= rtex
->resource
.gpu_address
;
1923 z_offs
+= rtex
->surface
.level
[level
].offset
;
1924 s_offs
+= rtex
->surface
.stencil_level
[level
].offset
;
1926 db_depth_info
= S_02803C_ADDR5_SWIZZLE_MASK(1);
1928 z_info
= S_028040_FORMAT(format
);
1929 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
1930 z_info
|= S_028040_NUM_SAMPLES(util_logbase2(rtex
->resource
.b
.b
.nr_samples
));
1933 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
)
1934 s_info
= S_028044_FORMAT(V_028044_STENCIL_8
);
1936 s_info
= S_028044_FORMAT(V_028044_STENCIL_INVALID
);
1938 if (sctx
->b
.chip_class
>= CIK
) {
1939 switch (rtex
->surface
.level
[level
].mode
) {
1940 case RADEON_SURF_MODE_2D
:
1941 array_mode
= V_02803C_ARRAY_2D_TILED_THIN1
;
1943 case RADEON_SURF_MODE_1D
:
1944 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
1945 case RADEON_SURF_MODE_LINEAR
:
1947 array_mode
= V_02803C_ARRAY_1D_TILED_THIN1
;
1950 tile_split
= rtex
->surface
.tile_split
;
1951 stile_split
= rtex
->surface
.stencil_tile_split
;
1952 macro_aspect
= rtex
->surface
.mtilea
;
1953 bankw
= rtex
->surface
.bankw
;
1954 bankh
= rtex
->surface
.bankh
;
1955 tile_split
= cik_tile_split(tile_split
);
1956 stile_split
= cik_tile_split(stile_split
);
1957 macro_aspect
= cik_macro_tile_aspect(macro_aspect
);
1958 bankw
= cik_bank_wh(bankw
);
1959 bankh
= cik_bank_wh(bankh
);
1960 nbanks
= si_num_banks(sscreen
, rtex
);
1961 tile_mode_index
= si_tile_mode_index(rtex
, level
, false);
1962 pipe_config
= cik_db_pipe_config(sscreen
, tile_mode_index
);
1964 db_depth_info
|= S_02803C_ARRAY_MODE(array_mode
) |
1965 S_02803C_PIPE_CONFIG(pipe_config
) |
1966 S_02803C_BANK_WIDTH(bankw
) |
1967 S_02803C_BANK_HEIGHT(bankh
) |
1968 S_02803C_MACRO_TILE_ASPECT(macro_aspect
) |
1969 S_02803C_NUM_BANKS(nbanks
);
1970 z_info
|= S_028040_TILE_SPLIT(tile_split
);
1971 s_info
|= S_028044_TILE_SPLIT(stile_split
);
1973 tile_mode_index
= si_tile_mode_index(rtex
, level
, false);
1974 z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
1975 tile_mode_index
= si_tile_mode_index(rtex
, level
, true);
1976 s_info
|= S_028044_TILE_MODE_INDEX(tile_mode_index
);
1979 /* HiZ aka depth buffer htile */
1980 /* use htile only for first level */
1981 if (rtex
->htile_buffer
&& !level
) {
1982 z_info
|= S_028040_TILE_SURFACE_ENABLE(1) |
1983 S_028040_ALLOW_EXPCLEAR(1);
1985 /* Use all of the htile_buffer for depth, because we don't
1986 * use HTILE for stencil because of FAST_STENCIL_DISABLE. */
1987 s_info
|= S_028044_TILE_STENCIL_DISABLE(1);
1989 uint64_t va
= rtex
->htile_buffer
->gpu_address
;
1990 db_htile_data_base
= va
>> 8;
1991 db_htile_surface
= S_028ABC_FULL_CACHE(1);
1993 db_htile_data_base
= 0;
1994 db_htile_surface
= 0;
1997 /* Bug workaround. */
1998 if (sctx
->b
.chip_class
>= VI
)
1999 s_info
|= S_028044_TILE_STENCIL_DISABLE(1);
2001 assert(levelinfo
->nblk_x
% 8 == 0 && levelinfo
->nblk_y
% 8 == 0);
2003 surf
->db_depth_view
= S_028008_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
2004 S_028008_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
2005 surf
->db_htile_data_base
= db_htile_data_base
;
2006 surf
->db_depth_info
= db_depth_info
;
2007 surf
->db_z_info
= z_info
;
2008 surf
->db_stencil_info
= s_info
;
2009 surf
->db_depth_base
= z_offs
>> 8;
2010 surf
->db_stencil_base
= s_offs
>> 8;
2011 surf
->db_depth_size
= S_028058_PITCH_TILE_MAX((levelinfo
->nblk_x
/ 8) - 1) |
2012 S_028058_HEIGHT_TILE_MAX((levelinfo
->nblk_y
/ 8) - 1);
2013 surf
->db_depth_slice
= S_02805C_SLICE_TILE_MAX((levelinfo
->nblk_x
*
2014 levelinfo
->nblk_y
) / 64 - 1);
2015 surf
->db_htile_surface
= db_htile_surface
;
2016 surf
->pa_su_poly_offset_db_fmt_cntl
= pa_su_poly_offset_db_fmt_cntl
;
2018 surf
->depth_initialized
= true;
2021 static void si_set_framebuffer_state(struct pipe_context
*ctx
,
2022 const struct pipe_framebuffer_state
*state
)
2024 struct si_context
*sctx
= (struct si_context
*)ctx
;
2025 struct pipe_constant_buffer constbuf
= {0};
2026 struct r600_surface
*surf
= NULL
;
2027 struct r600_texture
*rtex
;
2028 bool old_cb0_is_integer
= sctx
->framebuffer
.cb0_is_integer
;
2029 unsigned old_nr_samples
= sctx
->framebuffer
.nr_samples
;
2032 /* Only flush TC when changing the framebuffer state, because
2033 * the only client not using TC that can change textures is
2036 * Flush all CB and DB caches here because all buffers can be used
2037 * for write by both TC (with shader image stores) and CB/DB.
2039 sctx
->b
.flags
|= SI_CONTEXT_INV_TC_L1
|
2040 SI_CONTEXT_INV_TC_L2
|
2041 SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER
;
2043 util_copy_framebuffer_state(&sctx
->framebuffer
.state
, state
);
2045 sctx
->framebuffer
.export_16bpc
= 0;
2046 sctx
->framebuffer
.compressed_cb_mask
= 0;
2047 sctx
->framebuffer
.nr_samples
= util_framebuffer_get_num_samples(state
);
2048 sctx
->framebuffer
.log_samples
= util_logbase2(sctx
->framebuffer
.nr_samples
);
2049 sctx
->framebuffer
.cb0_is_integer
= state
->nr_cbufs
&& state
->cbufs
[0] &&
2050 util_format_is_pure_integer(state
->cbufs
[0]->format
);
2052 if (sctx
->framebuffer
.cb0_is_integer
!= old_cb0_is_integer
)
2053 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
2055 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
2056 if (!state
->cbufs
[i
])
2059 surf
= (struct r600_surface
*)state
->cbufs
[i
];
2060 rtex
= (struct r600_texture
*)surf
->base
.texture
;
2062 if (!surf
->color_initialized
) {
2063 si_initialize_color_surface(sctx
, surf
);
2066 if (surf
->export_16bpc
) {
2067 sctx
->framebuffer
.export_16bpc
|= 1 << i
;
2070 if (rtex
->fmask
.size
&& rtex
->cmask
.size
) {
2071 sctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
2073 r600_context_add_resource_size(ctx
, surf
->base
.texture
);
2075 /* Set the 16BPC export for possible dual-src blending. */
2076 if (i
== 1 && surf
&& surf
->export_16bpc
) {
2077 sctx
->framebuffer
.export_16bpc
|= 1 << 1;
2080 assert(!(sctx
->framebuffer
.export_16bpc
& ~0xff));
2083 surf
= (struct r600_surface
*)state
->zsbuf
;
2085 if (!surf
->depth_initialized
) {
2086 si_init_depth_surface(sctx
, surf
);
2088 r600_context_add_resource_size(ctx
, surf
->base
.texture
);
2091 si_update_fb_rs_state(sctx
);
2092 si_update_fb_blend_state(sctx
);
2094 sctx
->framebuffer
.atom
.num_dw
= state
->nr_cbufs
*16 + (8 - state
->nr_cbufs
)*3;
2095 sctx
->framebuffer
.atom
.num_dw
+= state
->zsbuf
? 26 : 4;
2096 sctx
->framebuffer
.atom
.num_dw
+= 3; /* WINDOW_SCISSOR_BR */
2097 sctx
->framebuffer
.atom
.num_dw
+= 18; /* MSAA sample locations */
2098 si_mark_atom_dirty(sctx
, &sctx
->framebuffer
.atom
);
2100 if (sctx
->framebuffer
.nr_samples
!= old_nr_samples
) {
2101 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
2102 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
2104 /* Set sample locations as fragment shader constants. */
2105 switch (sctx
->framebuffer
.nr_samples
) {
2107 constbuf
.user_buffer
= sctx
->b
.sample_locations_1x
;
2110 constbuf
.user_buffer
= sctx
->b
.sample_locations_2x
;
2113 constbuf
.user_buffer
= sctx
->b
.sample_locations_4x
;
2116 constbuf
.user_buffer
= sctx
->b
.sample_locations_8x
;
2119 constbuf
.user_buffer
= sctx
->b
.sample_locations_16x
;
2124 constbuf
.buffer_size
= sctx
->framebuffer
.nr_samples
* 2 * 4;
2125 ctx
->set_constant_buffer(ctx
, PIPE_SHADER_FRAGMENT
,
2126 SI_DRIVER_STATE_CONST_BUF
, &constbuf
);
2128 /* Smoothing (only possible with nr_samples == 1) uses the same
2129 * sample locations as the MSAA it simulates.
2131 * Therefore, don't update the sample locations when
2132 * transitioning from no AA to smoothing-equivalent AA, and
2135 if ((sctx
->framebuffer
.nr_samples
!= 1 ||
2136 old_nr_samples
!= SI_NUM_SMOOTH_AA_SAMPLES
) &&
2137 (sctx
->framebuffer
.nr_samples
!= SI_NUM_SMOOTH_AA_SAMPLES
||
2138 old_nr_samples
!= 1))
2139 si_mark_atom_dirty(sctx
, &sctx
->msaa_sample_locs
);
2143 static void si_emit_framebuffer_state(struct si_context
*sctx
, struct r600_atom
*atom
)
2145 struct radeon_winsys_cs
*cs
= sctx
->b
.rings
.gfx
.cs
;
2146 struct pipe_framebuffer_state
*state
= &sctx
->framebuffer
.state
;
2147 unsigned i
, nr_cbufs
= state
->nr_cbufs
;
2148 struct r600_texture
*tex
= NULL
;
2149 struct r600_surface
*cb
= NULL
;
2152 for (i
= 0; i
< nr_cbufs
; i
++) {
2153 cb
= (struct r600_surface
*)state
->cbufs
[i
];
2155 r600_write_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
2156 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
2160 tex
= (struct r600_texture
*)cb
->base
.texture
;
2161 r600_context_bo_reloc(&sctx
->b
, &sctx
->b
.rings
.gfx
,
2162 &tex
->resource
, RADEON_USAGE_READWRITE
,
2163 tex
->surface
.nsamples
> 1 ?
2164 RADEON_PRIO_COLOR_BUFFER_MSAA
:
2165 RADEON_PRIO_COLOR_BUFFER
);
2167 if (tex
->cmask_buffer
&& tex
->cmask_buffer
!= &tex
->resource
) {
2168 r600_context_bo_reloc(&sctx
->b
, &sctx
->b
.rings
.gfx
,
2169 tex
->cmask_buffer
, RADEON_USAGE_READWRITE
,
2170 RADEON_PRIO_COLOR_META
);
2173 r600_write_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C,
2174 sctx
->b
.chip_class
>= VI
? 14 : 13);
2175 radeon_emit(cs
, cb
->cb_color_base
); /* R_028C60_CB_COLOR0_BASE */
2176 radeon_emit(cs
, cb
->cb_color_pitch
); /* R_028C64_CB_COLOR0_PITCH */
2177 radeon_emit(cs
, cb
->cb_color_slice
); /* R_028C68_CB_COLOR0_SLICE */
2178 radeon_emit(cs
, cb
->cb_color_view
); /* R_028C6C_CB_COLOR0_VIEW */
2179 radeon_emit(cs
, cb
->cb_color_info
| tex
->cb_color_info
); /* R_028C70_CB_COLOR0_INFO */
2180 radeon_emit(cs
, cb
->cb_color_attrib
); /* R_028C74_CB_COLOR0_ATTRIB */
2181 radeon_emit(cs
, cb
->cb_dcc_control
); /* R_028C78_CB_COLOR0_DCC_CONTROL */
2182 radeon_emit(cs
, tex
->cmask
.base_address_reg
); /* R_028C7C_CB_COLOR0_CMASK */
2183 radeon_emit(cs
, tex
->cmask
.slice_tile_max
); /* R_028C80_CB_COLOR0_CMASK_SLICE */
2184 radeon_emit(cs
, cb
->cb_color_fmask
); /* R_028C84_CB_COLOR0_FMASK */
2185 radeon_emit(cs
, cb
->cb_color_fmask_slice
); /* R_028C88_CB_COLOR0_FMASK_SLICE */
2186 radeon_emit(cs
, tex
->color_clear_value
[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
2187 radeon_emit(cs
, tex
->color_clear_value
[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
2189 if (sctx
->b
.chip_class
>= VI
)
2190 radeon_emit(cs
, 0); /* R_028C94_CB_COLOR0_DCC_BASE */
2192 /* set CB_COLOR1_INFO for possible dual-src blending */
2193 if (i
== 1 && state
->cbufs
[0]) {
2194 r600_write_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ 1 * 0x3C,
2195 cb
->cb_color_info
| tex
->cb_color_info
);
2198 for (; i
< 8 ; i
++) {
2199 r600_write_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C, 0);
2204 struct r600_surface
*zb
= (struct r600_surface
*)state
->zsbuf
;
2205 struct r600_texture
*rtex
= (struct r600_texture
*)zb
->base
.texture
;
2207 r600_context_bo_reloc(&sctx
->b
, &sctx
->b
.rings
.gfx
,
2208 &rtex
->resource
, RADEON_USAGE_READWRITE
,
2209 zb
->base
.texture
->nr_samples
> 1 ?
2210 RADEON_PRIO_DEPTH_BUFFER_MSAA
:
2211 RADEON_PRIO_DEPTH_BUFFER
);
2213 if (zb
->db_htile_data_base
) {
2214 r600_context_bo_reloc(&sctx
->b
, &sctx
->b
.rings
.gfx
,
2215 rtex
->htile_buffer
, RADEON_USAGE_READWRITE
,
2216 RADEON_PRIO_DEPTH_META
);
2219 r600_write_context_reg(cs
, R_028008_DB_DEPTH_VIEW
, zb
->db_depth_view
);
2220 r600_write_context_reg(cs
, R_028014_DB_HTILE_DATA_BASE
, zb
->db_htile_data_base
);
2222 r600_write_context_reg_seq(cs
, R_02803C_DB_DEPTH_INFO
, 9);
2223 radeon_emit(cs
, zb
->db_depth_info
); /* R_02803C_DB_DEPTH_INFO */
2224 radeon_emit(cs
, zb
->db_z_info
| /* R_028040_DB_Z_INFO */
2225 S_028040_ZRANGE_PRECISION(rtex
->depth_clear_value
!= 0));
2226 radeon_emit(cs
, zb
->db_stencil_info
); /* R_028044_DB_STENCIL_INFO */
2227 radeon_emit(cs
, zb
->db_depth_base
); /* R_028048_DB_Z_READ_BASE */
2228 radeon_emit(cs
, zb
->db_stencil_base
); /* R_02804C_DB_STENCIL_READ_BASE */
2229 radeon_emit(cs
, zb
->db_depth_base
); /* R_028050_DB_Z_WRITE_BASE */
2230 radeon_emit(cs
, zb
->db_stencil_base
); /* R_028054_DB_STENCIL_WRITE_BASE */
2231 radeon_emit(cs
, zb
->db_depth_size
); /* R_028058_DB_DEPTH_SIZE */
2232 radeon_emit(cs
, zb
->db_depth_slice
); /* R_02805C_DB_DEPTH_SLICE */
2234 r600_write_context_reg(cs
, R_028ABC_DB_HTILE_SURFACE
, zb
->db_htile_surface
);
2235 r600_write_context_reg(cs
, R_02802C_DB_DEPTH_CLEAR
, fui(rtex
->depth_clear_value
));
2236 r600_write_context_reg(cs
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
2237 zb
->pa_su_poly_offset_db_fmt_cntl
);
2239 r600_write_context_reg_seq(cs
, R_028040_DB_Z_INFO
, 2);
2240 radeon_emit(cs
, S_028040_FORMAT(V_028040_Z_INVALID
)); /* R_028040_DB_Z_INFO */
2241 radeon_emit(cs
, S_028044_FORMAT(V_028044_STENCIL_INVALID
)); /* R_028044_DB_STENCIL_INFO */
2244 /* Framebuffer dimensions. */
2245 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2246 r600_write_context_reg(cs
, R_028208_PA_SC_WINDOW_SCISSOR_BR
,
2247 S_028208_BR_X(state
->width
) | S_028208_BR_Y(state
->height
));
2250 static void si_emit_msaa_sample_locs(struct r600_common_context
*rctx
,
2251 struct r600_atom
*atom
)
2253 struct si_context
*sctx
= (struct si_context
*)rctx
;
2254 struct radeon_winsys_cs
*cs
= sctx
->b
.rings
.gfx
.cs
;
2255 unsigned nr_samples
= sctx
->framebuffer
.nr_samples
;
2257 cayman_emit_msaa_sample_locs(cs
, nr_samples
> 1 ? nr_samples
:
2258 SI_NUM_SMOOTH_AA_SAMPLES
);
2261 const struct r600_atom si_atom_msaa_sample_locs
= { si_emit_msaa_sample_locs
, 18 }; /* number of CS dwords */
2263 static void si_emit_msaa_config(struct r600_common_context
*rctx
, struct r600_atom
*atom
)
2265 struct si_context
*sctx
= (struct si_context
*)rctx
;
2266 struct radeon_winsys_cs
*cs
= sctx
->b
.rings
.gfx
.cs
;
2268 cayman_emit_msaa_config(cs
, sctx
->framebuffer
.nr_samples
,
2269 sctx
->ps_iter_samples
,
2270 sctx
->smoothing_enabled
? SI_NUM_SMOOTH_AA_SAMPLES
: 0);
2273 const struct r600_atom si_atom_msaa_config
= { si_emit_msaa_config
, 10 }; /* number of CS dwords */
2275 static void si_set_min_samples(struct pipe_context
*ctx
, unsigned min_samples
)
2277 struct si_context
*sctx
= (struct si_context
*)ctx
;
2279 if (sctx
->ps_iter_samples
== min_samples
)
2282 sctx
->ps_iter_samples
= min_samples
;
2284 if (sctx
->framebuffer
.nr_samples
> 1)
2285 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
2293 * Create a sampler view.
2295 * @param ctx context
2296 * @param texture texture
2297 * @param state sampler view template
2298 * @param width0 width0 override (for compressed textures as int)
2299 * @param height0 height0 override (for compressed textures as int)
2300 * @param force_level set the base address to the level (for compressed textures)
2302 struct pipe_sampler_view
*
2303 si_create_sampler_view_custom(struct pipe_context
*ctx
,
2304 struct pipe_resource
*texture
,
2305 const struct pipe_sampler_view
*state
,
2306 unsigned width0
, unsigned height0
,
2307 unsigned force_level
)
2309 struct si_context
*sctx
= (struct si_context
*)ctx
;
2310 struct si_sampler_view
*view
= CALLOC_STRUCT(si_sampler_view
);
2311 struct r600_texture
*tmp
= (struct r600_texture
*)texture
;
2312 const struct util_format_description
*desc
;
2313 unsigned format
, num_format
, base_level
, first_level
, last_level
;
2315 unsigned char state_swizzle
[4], swizzle
[4];
2316 unsigned height
, depth
, width
;
2317 enum pipe_format pipe_format
= state
->format
;
2318 struct radeon_surf_level
*surflevel
;
2325 /* initialize base object */
2326 view
->base
= *state
;
2327 view
->base
.texture
= NULL
;
2328 view
->base
.reference
.count
= 1;
2329 view
->base
.context
= ctx
;
2331 /* NULL resource, obey swizzle (only ZERO and ONE make sense). */
2333 view
->state
[3] = S_008F1C_DST_SEL_X(si_map_swizzle(state
->swizzle_r
)) |
2334 S_008F1C_DST_SEL_Y(si_map_swizzle(state
->swizzle_g
)) |
2335 S_008F1C_DST_SEL_Z(si_map_swizzle(state
->swizzle_b
)) |
2336 S_008F1C_DST_SEL_W(si_map_swizzle(state
->swizzle_a
)) |
2337 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D
);
2341 pipe_resource_reference(&view
->base
.texture
, texture
);
2342 view
->resource
= &tmp
->resource
;
2344 /* Buffer resource. */
2345 if (texture
->target
== PIPE_BUFFER
) {
2346 unsigned stride
, num_records
;
2348 desc
= util_format_description(state
->format
);
2349 first_non_void
= util_format_get_first_non_void_channel(state
->format
);
2350 stride
= desc
->block
.bits
/ 8;
2351 va
= tmp
->resource
.gpu_address
+ state
->u
.buf
.first_element
*stride
;
2352 format
= si_translate_buffer_dataformat(ctx
->screen
, desc
, first_non_void
);
2353 num_format
= si_translate_buffer_numformat(ctx
->screen
, desc
, first_non_void
);
2355 num_records
= state
->u
.buf
.last_element
+ 1 - state
->u
.buf
.first_element
;
2356 num_records
= MIN2(num_records
, texture
->width0
/ stride
);
2358 if (sctx
->b
.chip_class
>= VI
)
2359 num_records
*= stride
;
2361 view
->state
[4] = va
;
2362 view
->state
[5] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
2363 S_008F04_STRIDE(stride
);
2364 view
->state
[6] = num_records
;
2365 view
->state
[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc
->swizzle
[0])) |
2366 S_008F0C_DST_SEL_Y(si_map_swizzle(desc
->swizzle
[1])) |
2367 S_008F0C_DST_SEL_Z(si_map_swizzle(desc
->swizzle
[2])) |
2368 S_008F0C_DST_SEL_W(si_map_swizzle(desc
->swizzle
[3])) |
2369 S_008F0C_NUM_FORMAT(num_format
) |
2370 S_008F0C_DATA_FORMAT(format
);
2372 LIST_ADDTAIL(&view
->list
, &sctx
->b
.texture_buffers
);
2376 state_swizzle
[0] = state
->swizzle_r
;
2377 state_swizzle
[1] = state
->swizzle_g
;
2378 state_swizzle
[2] = state
->swizzle_b
;
2379 state_swizzle
[3] = state
->swizzle_a
;
2381 surflevel
= tmp
->surface
.level
;
2383 /* Texturing with separate depth and stencil. */
2384 if (tmp
->is_depth
&& !tmp
->is_flushing_texture
) {
2385 switch (pipe_format
) {
2386 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
2387 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
2389 case PIPE_FORMAT_X8Z24_UNORM
:
2390 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
2391 /* Z24 is always stored like this. */
2392 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
2394 case PIPE_FORMAT_X24S8_UINT
:
2395 case PIPE_FORMAT_S8X24_UINT
:
2396 case PIPE_FORMAT_X32_S8X24_UINT
:
2397 pipe_format
= PIPE_FORMAT_S8_UINT
;
2398 surflevel
= tmp
->surface
.stencil_level
;
2404 desc
= util_format_description(pipe_format
);
2406 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
) {
2407 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
2408 const unsigned char swizzle_yyyy
[4] = {1, 1, 1, 1};
2410 switch (pipe_format
) {
2411 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
2412 case PIPE_FORMAT_X24S8_UINT
:
2413 case PIPE_FORMAT_X32_S8X24_UINT
:
2414 case PIPE_FORMAT_X8Z24_UNORM
:
2415 util_format_compose_swizzles(swizzle_yyyy
, state_swizzle
, swizzle
);
2418 util_format_compose_swizzles(swizzle_xxxx
, state_swizzle
, swizzle
);
2421 util_format_compose_swizzles(desc
->swizzle
, state_swizzle
, swizzle
);
2424 first_non_void
= util_format_get_first_non_void_channel(pipe_format
);
2426 switch (pipe_format
) {
2427 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
2428 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
2431 if (first_non_void
< 0) {
2432 if (util_format_is_compressed(pipe_format
)) {
2433 switch (pipe_format
) {
2434 case PIPE_FORMAT_DXT1_SRGB
:
2435 case PIPE_FORMAT_DXT1_SRGBA
:
2436 case PIPE_FORMAT_DXT3_SRGBA
:
2437 case PIPE_FORMAT_DXT5_SRGBA
:
2438 case PIPE_FORMAT_BPTC_SRGBA
:
2439 num_format
= V_008F14_IMG_NUM_FORMAT_SRGB
;
2441 case PIPE_FORMAT_RGTC1_SNORM
:
2442 case PIPE_FORMAT_LATC1_SNORM
:
2443 case PIPE_FORMAT_RGTC2_SNORM
:
2444 case PIPE_FORMAT_LATC2_SNORM
:
2445 /* implies float, so use SNORM/UNORM to determine
2446 whether data is signed or not */
2447 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
2448 num_format
= V_008F14_IMG_NUM_FORMAT_SNORM
;
2451 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
2454 } else if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
2455 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
2457 num_format
= V_008F14_IMG_NUM_FORMAT_FLOAT
;
2459 } else if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
) {
2460 num_format
= V_008F14_IMG_NUM_FORMAT_SRGB
;
2462 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
2464 switch (desc
->channel
[first_non_void
].type
) {
2465 case UTIL_FORMAT_TYPE_FLOAT
:
2466 num_format
= V_008F14_IMG_NUM_FORMAT_FLOAT
;
2468 case UTIL_FORMAT_TYPE_SIGNED
:
2469 if (desc
->channel
[first_non_void
].normalized
)
2470 num_format
= V_008F14_IMG_NUM_FORMAT_SNORM
;
2471 else if (desc
->channel
[first_non_void
].pure_integer
)
2472 num_format
= V_008F14_IMG_NUM_FORMAT_SINT
;
2474 num_format
= V_008F14_IMG_NUM_FORMAT_SSCALED
;
2476 case UTIL_FORMAT_TYPE_UNSIGNED
:
2477 if (desc
->channel
[first_non_void
].normalized
)
2478 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
2479 else if (desc
->channel
[first_non_void
].pure_integer
)
2480 num_format
= V_008F14_IMG_NUM_FORMAT_UINT
;
2482 num_format
= V_008F14_IMG_NUM_FORMAT_USCALED
;
2487 format
= si_translate_texformat(ctx
->screen
, pipe_format
, desc
, first_non_void
);
2493 first_level
= state
->u
.tex
.first_level
;
2494 last_level
= state
->u
.tex
.last_level
;
2497 depth
= texture
->depth0
;
2500 assert(force_level
== first_level
&&
2501 force_level
== last_level
);
2502 base_level
= force_level
;
2505 width
= u_minify(width
, force_level
);
2506 height
= u_minify(height
, force_level
);
2507 depth
= u_minify(depth
, force_level
);
2510 pitch
= surflevel
[base_level
].nblk_x
* util_format_get_blockwidth(pipe_format
);
2512 if (texture
->target
== PIPE_TEXTURE_1D_ARRAY
) {
2514 depth
= texture
->array_size
;
2515 } else if (texture
->target
== PIPE_TEXTURE_2D_ARRAY
) {
2516 depth
= texture
->array_size
;
2517 } else if (texture
->target
== PIPE_TEXTURE_CUBE_ARRAY
)
2518 depth
= texture
->array_size
/ 6;
2520 va
= tmp
->resource
.gpu_address
+ surflevel
[base_level
].offset
;
2522 view
->state
[0] = va
>> 8;
2523 view
->state
[1] = (S_008F14_BASE_ADDRESS_HI(va
>> 40) |
2524 S_008F14_DATA_FORMAT(format
) |
2525 S_008F14_NUM_FORMAT(num_format
));
2526 view
->state
[2] = (S_008F18_WIDTH(width
- 1) |
2527 S_008F18_HEIGHT(height
- 1));
2528 view
->state
[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle
[0])) |
2529 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle
[1])) |
2530 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle
[2])) |
2531 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle
[3])) |
2532 S_008F1C_BASE_LEVEL(texture
->nr_samples
> 1 ?
2534 S_008F1C_LAST_LEVEL(texture
->nr_samples
> 1 ?
2535 util_logbase2(texture
->nr_samples
) :
2537 S_008F1C_TILING_INDEX(si_tile_mode_index(tmp
, base_level
, false)) |
2538 S_008F1C_POW2_PAD(texture
->last_level
> 0) |
2539 S_008F1C_TYPE(si_tex_dim(texture
->target
, texture
->nr_samples
)));
2540 view
->state
[4] = (S_008F20_DEPTH(depth
- 1) | S_008F20_PITCH(pitch
- 1));
2541 view
->state
[5] = (S_008F24_BASE_ARRAY(state
->u
.tex
.first_layer
) |
2542 S_008F24_LAST_ARRAY(state
->u
.tex
.last_layer
));
2546 /* Initialize the sampler view for FMASK. */
2547 if (tmp
->fmask
.size
) {
2548 uint64_t va
= tmp
->resource
.gpu_address
+ tmp
->fmask
.offset
;
2549 uint32_t fmask_format
;
2551 switch (texture
->nr_samples
) {
2553 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2
;
2556 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4
;
2559 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8
;
2563 fmask_format
= V_008F14_IMG_DATA_FORMAT_INVALID
;
2566 view
->fmask_state
[0] = va
>> 8;
2567 view
->fmask_state
[1] = S_008F14_BASE_ADDRESS_HI(va
>> 40) |
2568 S_008F14_DATA_FORMAT(fmask_format
) |
2569 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT
);
2570 view
->fmask_state
[2] = S_008F18_WIDTH(width
- 1) |
2571 S_008F18_HEIGHT(height
- 1);
2572 view
->fmask_state
[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X
) |
2573 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X
) |
2574 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X
) |
2575 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X
) |
2576 S_008F1C_TILING_INDEX(tmp
->fmask
.tile_mode_index
) |
2577 S_008F1C_TYPE(si_tex_dim(texture
->target
, 0));
2578 view
->fmask_state
[4] = S_008F20_DEPTH(depth
- 1) |
2579 S_008F20_PITCH(tmp
->fmask
.pitch
- 1);
2580 view
->fmask_state
[5] = S_008F24_BASE_ARRAY(state
->u
.tex
.first_layer
) |
2581 S_008F24_LAST_ARRAY(state
->u
.tex
.last_layer
);
2582 view
->fmask_state
[6] = 0;
2583 view
->fmask_state
[7] = 0;
2589 static struct pipe_sampler_view
*
2590 si_create_sampler_view(struct pipe_context
*ctx
,
2591 struct pipe_resource
*texture
,
2592 const struct pipe_sampler_view
*state
)
2594 return si_create_sampler_view_custom(ctx
, texture
, state
,
2595 texture
? texture
->width0
: 0,
2596 texture
? texture
->height0
: 0, 0);
2599 static void si_sampler_view_destroy(struct pipe_context
*ctx
,
2600 struct pipe_sampler_view
*state
)
2602 struct si_sampler_view
*view
= (struct si_sampler_view
*)state
;
2604 if (view
->resource
&& view
->resource
->b
.b
.target
== PIPE_BUFFER
)
2605 LIST_DELINIT(&view
->list
);
2607 pipe_resource_reference(&state
->texture
, NULL
);
2611 static bool wrap_mode_uses_border_color(unsigned wrap
, bool linear_filter
)
2613 return wrap
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
||
2614 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
||
2616 (wrap
== PIPE_TEX_WRAP_CLAMP
||
2617 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP
));
2620 static bool sampler_state_needs_border_color(const struct pipe_sampler_state
*state
)
2622 bool linear_filter
= state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
||
2623 state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
;
2625 return (state
->border_color
.ui
[0] || state
->border_color
.ui
[1] ||
2626 state
->border_color
.ui
[2] || state
->border_color
.ui
[3]) &&
2627 (wrap_mode_uses_border_color(state
->wrap_s
, linear_filter
) ||
2628 wrap_mode_uses_border_color(state
->wrap_t
, linear_filter
) ||
2629 wrap_mode_uses_border_color(state
->wrap_r
, linear_filter
));
2632 static void *si_create_sampler_state(struct pipe_context
*ctx
,
2633 const struct pipe_sampler_state
*state
)
2635 struct si_sampler_state
*rstate
= CALLOC_STRUCT(si_sampler_state
);
2636 unsigned aniso_flag_offset
= state
->max_anisotropy
> 1 ? 2 : 0;
2637 unsigned border_color_type
;
2639 if (rstate
== NULL
) {
2643 if (sampler_state_needs_border_color(state
))
2644 border_color_type
= V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER
;
2646 border_color_type
= V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
;
2648 rstate
->val
[0] = (S_008F30_CLAMP_X(si_tex_wrap(state
->wrap_s
)) |
2649 S_008F30_CLAMP_Y(si_tex_wrap(state
->wrap_t
)) |
2650 S_008F30_CLAMP_Z(si_tex_wrap(state
->wrap_r
)) |
2651 r600_tex_aniso_filter(state
->max_anisotropy
) << 9 |
2652 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state
->compare_func
)) |
2653 S_008F30_FORCE_UNNORMALIZED(!state
->normalized_coords
) |
2654 S_008F30_DISABLE_CUBE_WRAP(!state
->seamless_cube_map
));
2655 rstate
->val
[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 8)) |
2656 S_008F34_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 8)));
2657 rstate
->val
[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 8)) |
2658 S_008F38_XY_MAG_FILTER(si_tex_filter(state
->mag_img_filter
) | aniso_flag_offset
) |
2659 S_008F38_XY_MIN_FILTER(si_tex_filter(state
->min_img_filter
) | aniso_flag_offset
) |
2660 S_008F38_MIP_FILTER(si_tex_mipfilter(state
->min_mip_filter
)));
2661 rstate
->val
[3] = S_008F3C_BORDER_COLOR_TYPE(border_color_type
);
2663 if (border_color_type
== V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER
) {
2664 memcpy(rstate
->border_color
, state
->border_color
.ui
,
2665 sizeof(rstate
->border_color
));
2671 /* Upload border colors and update the pointers in resource descriptors.
2672 * There can only be 4096 border colors per context.
2674 * XXX: This is broken if the buffer gets reallocated.
2676 static void si_set_border_colors(struct si_context
*sctx
, unsigned count
,
2679 struct si_sampler_state
**rstates
= (struct si_sampler_state
**)states
;
2680 uint32_t *border_color_table
= NULL
;
2683 for (i
= 0; i
< count
; i
++) {
2685 G_008F3C_BORDER_COLOR_TYPE(rstates
[i
]->val
[3]) ==
2686 V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER
) {
2687 if (!sctx
->border_color_table
||
2688 ((sctx
->border_color_offset
+ count
- i
) &
2689 C_008F3C_BORDER_COLOR_PTR
)) {
2690 r600_resource_reference(&sctx
->border_color_table
, NULL
);
2691 sctx
->border_color_offset
= 0;
2693 sctx
->border_color_table
=
2694 si_resource_create_custom(&sctx
->screen
->b
.b
,
2699 if (!border_color_table
) {
2700 border_color_table
=
2701 sctx
->b
.ws
->buffer_map(sctx
->border_color_table
->cs_buf
,
2702 sctx
->b
.rings
.gfx
.cs
,
2703 PIPE_TRANSFER_WRITE
|
2704 PIPE_TRANSFER_UNSYNCHRONIZED
);
2707 for (j
= 0; j
< 4; j
++) {
2708 border_color_table
[4 * sctx
->border_color_offset
+ j
] =
2709 util_le32_to_cpu(rstates
[i
]->border_color
[j
]);
2712 rstates
[i
]->val
[3] &= C_008F3C_BORDER_COLOR_PTR
;
2713 rstates
[i
]->val
[3] |= S_008F3C_BORDER_COLOR_PTR(sctx
->border_color_offset
++);
2717 if (border_color_table
) {
2718 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
2720 uint64_t va_offset
= sctx
->border_color_table
->gpu_address
;
2722 si_pm4_set_reg(pm4
, R_028080_TA_BC_BASE_ADDR
, va_offset
>> 8);
2723 if (sctx
->b
.chip_class
>= CIK
)
2724 si_pm4_set_reg(pm4
, R_028084_TA_BC_BASE_ADDR_HI
, va_offset
>> 40);
2725 si_pm4_add_bo(pm4
, sctx
->border_color_table
, RADEON_USAGE_READ
,
2726 RADEON_PRIO_SHADER_DATA
);
2727 si_pm4_set_state(sctx
, ta_bordercolor_base
, pm4
);
2731 static void si_bind_sampler_states(struct pipe_context
*ctx
, unsigned shader
,
2732 unsigned start
, unsigned count
,
2735 struct si_context
*sctx
= (struct si_context
*)ctx
;
2737 if (!count
|| shader
>= SI_NUM_SHADERS
)
2740 si_set_border_colors(sctx
, count
, states
);
2741 si_set_sampler_descriptors(sctx
, shader
, start
, count
, states
);
2744 static void si_set_sample_mask(struct pipe_context
*ctx
, unsigned sample_mask
)
2746 struct si_context
*sctx
= (struct si_context
*)ctx
;
2747 struct si_state_sample_mask
*state
= CALLOC_STRUCT(si_state_sample_mask
);
2748 struct si_pm4_state
*pm4
= &state
->pm4
;
2749 uint16_t mask
= sample_mask
;
2754 state
->sample_mask
= mask
;
2755 si_pm4_set_reg(pm4
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, mask
| (mask
<< 16));
2756 si_pm4_set_reg(pm4
, R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1
, mask
| (mask
<< 16));
2758 si_pm4_set_state(sctx
, sample_mask
, state
);
2761 static void si_delete_sampler_state(struct pipe_context
*ctx
, void *state
)
2767 * Vertex elements & buffers
2770 static void *si_create_vertex_elements(struct pipe_context
*ctx
,
2772 const struct pipe_vertex_element
*elements
)
2774 struct si_vertex_element
*v
= CALLOC_STRUCT(si_vertex_element
);
2777 assert(count
< PIPE_MAX_ATTRIBS
);
2782 for (i
= 0; i
< count
; ++i
) {
2783 const struct util_format_description
*desc
;
2784 unsigned data_format
, num_format
;
2787 desc
= util_format_description(elements
[i
].src_format
);
2788 first_non_void
= util_format_get_first_non_void_channel(elements
[i
].src_format
);
2789 data_format
= si_translate_buffer_dataformat(ctx
->screen
, desc
, first_non_void
);
2790 num_format
= si_translate_buffer_numformat(ctx
->screen
, desc
, first_non_void
);
2792 v
->rsrc_word3
[i
] = S_008F0C_DST_SEL_X(si_map_swizzle(desc
->swizzle
[0])) |
2793 S_008F0C_DST_SEL_Y(si_map_swizzle(desc
->swizzle
[1])) |
2794 S_008F0C_DST_SEL_Z(si_map_swizzle(desc
->swizzle
[2])) |
2795 S_008F0C_DST_SEL_W(si_map_swizzle(desc
->swizzle
[3])) |
2796 S_008F0C_NUM_FORMAT(num_format
) |
2797 S_008F0C_DATA_FORMAT(data_format
);
2798 v
->format_size
[i
] = desc
->block
.bits
/ 8;
2800 memcpy(v
->elements
, elements
, sizeof(struct pipe_vertex_element
) * count
);
2805 static void si_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
2807 struct si_context
*sctx
= (struct si_context
*)ctx
;
2808 struct si_vertex_element
*v
= (struct si_vertex_element
*)state
;
2810 sctx
->vertex_elements
= v
;
2811 sctx
->vertex_buffers_dirty
= true;
2814 static void si_delete_vertex_element(struct pipe_context
*ctx
, void *state
)
2816 struct si_context
*sctx
= (struct si_context
*)ctx
;
2818 if (sctx
->vertex_elements
== state
)
2819 sctx
->vertex_elements
= NULL
;
2823 static void si_set_vertex_buffers(struct pipe_context
*ctx
,
2824 unsigned start_slot
, unsigned count
,
2825 const struct pipe_vertex_buffer
*buffers
)
2827 struct si_context
*sctx
= (struct si_context
*)ctx
;
2828 struct pipe_vertex_buffer
*dst
= sctx
->vertex_buffer
+ start_slot
;
2831 assert(start_slot
+ count
<= Elements(sctx
->vertex_buffer
));
2834 for (i
= 0; i
< count
; i
++) {
2835 const struct pipe_vertex_buffer
*src
= buffers
+ i
;
2836 struct pipe_vertex_buffer
*dsti
= dst
+ i
;
2838 pipe_resource_reference(&dsti
->buffer
, src
->buffer
);
2839 dsti
->buffer_offset
= src
->buffer_offset
;
2840 dsti
->stride
= src
->stride
;
2841 r600_context_add_resource_size(ctx
, src
->buffer
);
2844 for (i
= 0; i
< count
; i
++) {
2845 pipe_resource_reference(&dst
[i
].buffer
, NULL
);
2848 sctx
->vertex_buffers_dirty
= true;
2851 static void si_set_index_buffer(struct pipe_context
*ctx
,
2852 const struct pipe_index_buffer
*ib
)
2854 struct si_context
*sctx
= (struct si_context
*)ctx
;
2857 pipe_resource_reference(&sctx
->index_buffer
.buffer
, ib
->buffer
);
2858 memcpy(&sctx
->index_buffer
, ib
, sizeof(*ib
));
2859 r600_context_add_resource_size(ctx
, ib
->buffer
);
2861 pipe_resource_reference(&sctx
->index_buffer
.buffer
, NULL
);
2868 static void si_set_polygon_stipple(struct pipe_context
*ctx
,
2869 const struct pipe_poly_stipple
*state
)
2871 struct si_context
*sctx
= (struct si_context
*)ctx
;
2872 struct pipe_resource
*tex
;
2873 struct pipe_sampler_view
*view
;
2874 bool is_zero
= true;
2878 /* The hardware obeys 0 and 1 swizzles in the descriptor even if
2879 * the resource is NULL/invalid. Take advantage of this fact and skip
2880 * texture allocation if the stipple pattern is constant.
2882 * This is an optimization for the common case when stippling isn't
2883 * used but set_polygon_stipple is still called by st/mesa.
2885 for (i
= 0; i
< Elements(state
->stipple
); i
++) {
2886 is_zero
= is_zero
&& state
->stipple
[i
] == 0;
2887 is_one
= is_one
&& state
->stipple
[i
] == 0xffffffff;
2890 if (is_zero
|| is_one
) {
2891 struct pipe_sampler_view templ
= {{0}};
2893 templ
.swizzle_r
= PIPE_SWIZZLE_ZERO
;
2894 templ
.swizzle_g
= PIPE_SWIZZLE_ZERO
;
2895 templ
.swizzle_b
= PIPE_SWIZZLE_ZERO
;
2896 /* The pattern should be inverted in the texture. */
2897 templ
.swizzle_a
= is_zero
? PIPE_SWIZZLE_ONE
: PIPE_SWIZZLE_ZERO
;
2899 view
= ctx
->create_sampler_view(ctx
, NULL
, &templ
);
2901 /* Create a new texture. */
2902 tex
= util_pstipple_create_stipple_texture(ctx
, state
->stipple
);
2906 view
= util_pstipple_create_sampler_view(ctx
, tex
);
2907 pipe_resource_reference(&tex
, NULL
);
2910 ctx
->set_sampler_views(ctx
, PIPE_SHADER_FRAGMENT
,
2911 SI_POLY_STIPPLE_SAMPLER
, 1, &view
);
2912 pipe_sampler_view_reference(&view
, NULL
);
2914 /* Bind the sampler state if needed. */
2915 if (!sctx
->pstipple_sampler_state
) {
2916 sctx
->pstipple_sampler_state
= util_pstipple_create_sampler(ctx
);
2917 ctx
->bind_sampler_states(ctx
, PIPE_SHADER_FRAGMENT
,
2918 SI_POLY_STIPPLE_SAMPLER
, 1,
2919 &sctx
->pstipple_sampler_state
);
2923 static void si_set_tess_state(struct pipe_context
*ctx
,
2924 const float default_outer_level
[4],
2925 const float default_inner_level
[2])
2927 struct si_context
*sctx
= (struct si_context
*)ctx
;
2928 struct pipe_constant_buffer cb
;
2931 memcpy(array
, default_outer_level
, sizeof(float) * 4);
2932 memcpy(array
+4, default_inner_level
, sizeof(float) * 2);
2935 cb
.user_buffer
= NULL
;
2936 cb
.buffer_size
= sizeof(array
);
2938 si_upload_const_buffer(sctx
, (struct r600_resource
**)&cb
.buffer
,
2939 (void*)array
, sizeof(array
),
2942 ctx
->set_constant_buffer(ctx
, PIPE_SHADER_TESS_CTRL
,
2943 SI_DRIVER_STATE_CONST_BUF
, &cb
);
2944 pipe_resource_reference(&cb
.buffer
, NULL
);
2947 static void si_texture_barrier(struct pipe_context
*ctx
)
2949 struct si_context
*sctx
= (struct si_context
*)ctx
;
2951 sctx
->b
.flags
|= SI_CONTEXT_INV_TC_L1
|
2952 SI_CONTEXT_INV_TC_L2
|
2953 SI_CONTEXT_FLUSH_AND_INV_CB
;
2956 static void *si_create_blend_custom(struct si_context
*sctx
, unsigned mode
)
2958 struct pipe_blend_state blend
;
2960 memset(&blend
, 0, sizeof(blend
));
2961 blend
.independent_blend_enable
= true;
2962 blend
.rt
[0].colormask
= 0xf;
2963 return si_create_blend_state_mode(&sctx
->b
.b
, &blend
, mode
);
2966 static void si_need_gfx_cs_space(struct pipe_context
*ctx
, unsigned num_dw
,
2967 bool include_draw_vbo
)
2969 si_need_cs_space((struct si_context
*)ctx
, num_dw
, include_draw_vbo
);
2972 static void si_init_config(struct si_context
*sctx
);
2974 void si_init_state_functions(struct si_context
*sctx
)
2976 si_init_atom(&sctx
->framebuffer
.atom
, &sctx
->atoms
.s
.framebuffer
, si_emit_framebuffer_state
, 0);
2977 si_init_atom(&sctx
->db_render_state
, &sctx
->atoms
.s
.db_render_state
, si_emit_db_render_state
, 10);
2978 si_init_atom(&sctx
->clip_regs
, &sctx
->atoms
.s
.clip_regs
, si_emit_clip_regs
, 6);
2980 sctx
->b
.b
.create_blend_state
= si_create_blend_state
;
2981 sctx
->b
.b
.bind_blend_state
= si_bind_blend_state
;
2982 sctx
->b
.b
.delete_blend_state
= si_delete_blend_state
;
2983 sctx
->b
.b
.set_blend_color
= si_set_blend_color
;
2985 sctx
->b
.b
.create_rasterizer_state
= si_create_rs_state
;
2986 sctx
->b
.b
.bind_rasterizer_state
= si_bind_rs_state
;
2987 sctx
->b
.b
.delete_rasterizer_state
= si_delete_rs_state
;
2989 sctx
->b
.b
.create_depth_stencil_alpha_state
= si_create_dsa_state
;
2990 sctx
->b
.b
.bind_depth_stencil_alpha_state
= si_bind_dsa_state
;
2991 sctx
->b
.b
.delete_depth_stencil_alpha_state
= si_delete_dsa_state
;
2993 sctx
->custom_dsa_flush
= si_create_db_flush_dsa(sctx
);
2994 sctx
->custom_blend_resolve
= si_create_blend_custom(sctx
, V_028808_CB_RESOLVE
);
2995 sctx
->custom_blend_decompress
= si_create_blend_custom(sctx
, V_028808_CB_FMASK_DECOMPRESS
);
2996 sctx
->custom_blend_fastclear
= si_create_blend_custom(sctx
, V_028808_CB_ELIMINATE_FAST_CLEAR
);
2998 sctx
->b
.b
.set_clip_state
= si_set_clip_state
;
2999 sctx
->b
.b
.set_scissor_states
= si_set_scissor_states
;
3000 sctx
->b
.b
.set_viewport_states
= si_set_viewport_states
;
3001 sctx
->b
.b
.set_stencil_ref
= si_set_pipe_stencil_ref
;
3003 sctx
->b
.b
.set_framebuffer_state
= si_set_framebuffer_state
;
3004 sctx
->b
.b
.get_sample_position
= cayman_get_sample_position
;
3006 sctx
->b
.b
.create_sampler_state
= si_create_sampler_state
;
3007 sctx
->b
.b
.bind_sampler_states
= si_bind_sampler_states
;
3008 sctx
->b
.b
.delete_sampler_state
= si_delete_sampler_state
;
3010 sctx
->b
.b
.create_sampler_view
= si_create_sampler_view
;
3011 sctx
->b
.b
.sampler_view_destroy
= si_sampler_view_destroy
;
3013 sctx
->b
.b
.set_sample_mask
= si_set_sample_mask
;
3015 sctx
->b
.b
.create_vertex_elements_state
= si_create_vertex_elements
;
3016 sctx
->b
.b
.bind_vertex_elements_state
= si_bind_vertex_elements
;
3017 sctx
->b
.b
.delete_vertex_elements_state
= si_delete_vertex_element
;
3018 sctx
->b
.b
.set_vertex_buffers
= si_set_vertex_buffers
;
3019 sctx
->b
.b
.set_index_buffer
= si_set_index_buffer
;
3021 sctx
->b
.b
.texture_barrier
= si_texture_barrier
;
3022 sctx
->b
.b
.set_polygon_stipple
= si_set_polygon_stipple
;
3023 sctx
->b
.b
.set_min_samples
= si_set_min_samples
;
3024 sctx
->b
.b
.set_tess_state
= si_set_tess_state
;
3026 sctx
->b
.set_occlusion_query_state
= si_set_occlusion_query_state
;
3027 sctx
->b
.need_gfx_cs_space
= si_need_gfx_cs_space
;
3029 sctx
->b
.b
.draw_vbo
= si_draw_vbo
;
3031 if (sctx
->b
.chip_class
>= CIK
) {
3032 sctx
->b
.dma_copy
= cik_sdma_copy
;
3034 sctx
->b
.dma_copy
= si_dma_copy
;
3037 si_init_config(sctx
);
3041 si_write_harvested_raster_configs(struct si_context
*sctx
,
3042 struct si_pm4_state
*pm4
,
3043 unsigned raster_config
)
3045 unsigned sh_per_se
= MAX2(sctx
->screen
->b
.info
.max_sh_per_se
, 1);
3046 unsigned num_se
= MAX2(sctx
->screen
->b
.info
.max_se
, 1);
3047 unsigned rb_mask
= sctx
->screen
->b
.info
.si_backend_enabled_mask
;
3048 unsigned num_rb
= sctx
->screen
->b
.info
.r600_num_backends
;
3049 unsigned rb_per_pkr
= num_rb
/ num_se
/ sh_per_se
;
3050 unsigned rb_per_se
= num_rb
/ num_se
;
3051 unsigned se0_mask
= (1 << rb_per_se
) - 1;
3052 unsigned se1_mask
= se0_mask
<< rb_per_se
;
3055 assert(num_se
== 1 || num_se
== 2);
3056 assert(sh_per_se
== 1 || sh_per_se
== 2);
3057 assert(rb_per_pkr
== 1 || rb_per_pkr
== 2);
3059 /* XXX: I can't figure out what the *_XSEL and *_YSEL
3060 * fields are for, so I'm leaving them as their default
3063 se0_mask
&= rb_mask
;
3064 se1_mask
&= rb_mask
;
3065 if (num_se
== 2 && (!se0_mask
|| !se1_mask
)) {
3066 raster_config
&= C_028350_SE_MAP
;
3070 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3
);
3073 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0
);
3077 for (se
= 0; se
< num_se
; se
++) {
3078 unsigned raster_config_se
= raster_config
;
3079 unsigned pkr0_mask
= ((1 << rb_per_pkr
) - 1) << (se
* rb_per_se
);
3080 unsigned pkr1_mask
= pkr0_mask
<< rb_per_pkr
;
3082 pkr0_mask
&= rb_mask
;
3083 pkr1_mask
&= rb_mask
;
3084 if (sh_per_se
== 2 && (!pkr0_mask
|| !pkr1_mask
)) {
3085 raster_config_se
&= C_028350_PKR_MAP
;
3089 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3
);
3092 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0
);
3096 if (rb_per_pkr
== 2) {
3097 unsigned rb0_mask
= 1 << (se
* rb_per_se
);
3098 unsigned rb1_mask
= rb0_mask
<< 1;
3100 rb0_mask
&= rb_mask
;
3101 rb1_mask
&= rb_mask
;
3102 if (!rb0_mask
|| !rb1_mask
) {
3103 raster_config_se
&= C_028350_RB_MAP_PKR0
;
3107 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3
);
3110 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0
);
3114 if (sh_per_se
== 2) {
3115 rb0_mask
= 1 << (se
* rb_per_se
+ rb_per_pkr
);
3116 rb1_mask
= rb0_mask
<< 1;
3117 rb0_mask
&= rb_mask
;
3118 rb1_mask
&= rb_mask
;
3119 if (!rb0_mask
|| !rb1_mask
) {
3120 raster_config_se
&= C_028350_RB_MAP_PKR1
;
3124 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3
);
3127 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0
);
3133 si_pm4_set_reg(pm4
, GRBM_GFX_INDEX
,
3134 SE_INDEX(se
) | SH_BROADCAST_WRITES
|
3135 INSTANCE_BROADCAST_WRITES
);
3136 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
, raster_config_se
);
3139 si_pm4_set_reg(pm4
, GRBM_GFX_INDEX
,
3140 SE_BROADCAST_WRITES
| SH_BROADCAST_WRITES
|
3141 INSTANCE_BROADCAST_WRITES
);
3144 static void si_init_config(struct si_context
*sctx
)
3146 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
3151 si_cmd_context_control(pm4
);
3153 si_pm4_set_reg(pm4
, R_028A18_VGT_HOS_MAX_TESS_LEVEL
, fui(64));
3154 si_pm4_set_reg(pm4
, R_028A1C_VGT_HOS_MIN_TESS_LEVEL
, fui(0));
3156 /* FIXME calculate these values somehow ??? */
3157 si_pm4_set_reg(pm4
, R_028A54_VGT_GS_PER_ES
, 0x80);
3158 si_pm4_set_reg(pm4
, R_028A58_VGT_ES_PER_GS
, 0x40);
3159 si_pm4_set_reg(pm4
, R_028A5C_VGT_GS_PER_VS
, 0x2);
3161 si_pm4_set_reg(pm4
, R_028A8C_VGT_PRIMITIVEID_RESET
, 0x0);
3162 si_pm4_set_reg(pm4
, R_028AB8_VGT_VTX_CNT_EN
, 0);
3163 si_pm4_set_reg(pm4
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
3165 si_pm4_set_reg(pm4
, R_028B98_VGT_STRMOUT_BUFFER_CONFIG
, 0x0);
3166 si_pm4_set_reg(pm4
, R_028AB4_VGT_REUSE_OFF
, 0);
3167 si_pm4_set_reg(pm4
, R_028AB8_VGT_VTX_CNT_EN
, 0x0);
3168 if (sctx
->b
.chip_class
< CIK
)
3169 si_pm4_set_reg(pm4
, R_008A14_PA_CL_ENHANCE
, S_008A14_NUM_CLIP_SEQ(3) |
3170 S_008A14_CLIP_VTX_REORDER_ENA(1));
3172 si_pm4_set_reg(pm4
, R_028BD4_PA_SC_CENTROID_PRIORITY_0
, 0x76543210);
3173 si_pm4_set_reg(pm4
, R_028BD8_PA_SC_CENTROID_PRIORITY_1
, 0xfedcba98);
3175 si_pm4_set_reg(pm4
, R_02882C_PA_SU_PRIM_FILTER_CNTL
, 0);
3177 if (sctx
->b
.chip_class
>= CIK
) {
3178 switch (sctx
->screen
->b
.family
) {
3180 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
, 0x16000012);
3181 si_pm4_set_reg(pm4
, R_028354_PA_SC_RASTER_CONFIG_1
, 0);
3184 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
, 0x3a00161a);
3185 si_pm4_set_reg(pm4
, R_028354_PA_SC_RASTER_CONFIG_1
, 0x0000002e);
3188 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
, 0x16000012);
3189 si_pm4_set_reg(pm4
, R_028354_PA_SC_RASTER_CONFIG_1
, 0x0000002a);
3193 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
, 0x00000002);
3194 si_pm4_set_reg(pm4
, R_028354_PA_SC_RASTER_CONFIG_1
, 0x00000000);
3203 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
, 0);
3204 si_pm4_set_reg(pm4
, R_028354_PA_SC_RASTER_CONFIG_1
, 0);
3208 unsigned rb_mask
= sctx
->screen
->b
.info
.si_backend_enabled_mask
;
3209 unsigned num_rb
= sctx
->screen
->b
.info
.r600_num_backends
;
3210 unsigned raster_config
;
3212 switch (sctx
->screen
->b
.family
) {
3215 raster_config
= 0x2a00126a;
3218 raster_config
= 0x0000124a;
3221 raster_config
= 0x00000082;
3228 "radeonsi: Unknown GPU, using 0 for raster_config\n");
3233 /* Always use the default config when all backends are enabled
3234 * (or when we failed to determine the enabled backends).
3236 if (!rb_mask
|| util_bitcount(rb_mask
) >= num_rb
) {
3237 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
,
3240 si_write_harvested_raster_configs(sctx
, pm4
, raster_config
);
3244 si_pm4_set_reg(pm4
, R_028204_PA_SC_WINDOW_SCISSOR_TL
, S_028204_WINDOW_OFFSET_DISABLE(1));
3245 si_pm4_set_reg(pm4
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, S_028240_WINDOW_OFFSET_DISABLE(1));
3246 si_pm4_set_reg(pm4
, R_028244_PA_SC_GENERIC_SCISSOR_BR
,
3247 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
3248 si_pm4_set_reg(pm4
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 0);
3249 si_pm4_set_reg(pm4
, R_028034_PA_SC_SCREEN_SCISSOR_BR
,
3250 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
3252 si_pm4_set_reg(pm4
, R_02820C_PA_SC_CLIPRECT_RULE
, 0xFFFF);
3253 si_pm4_set_reg(pm4
, R_028230_PA_SC_EDGERULE
, 0xAAAAAAAA);
3254 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
3255 si_pm4_set_reg(pm4
, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET
, 0);
3256 si_pm4_set_reg(pm4
, R_0282D0_PA_SC_VPORT_ZMIN_0
, 0);
3257 si_pm4_set_reg(pm4
, R_0282D4_PA_SC_VPORT_ZMAX_0
, fui(1.0));
3258 si_pm4_set_reg(pm4
, R_028820_PA_CL_NANINF_CNTL
, 0);
3259 si_pm4_set_reg(pm4
, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ
, fui(1.0));
3260 si_pm4_set_reg(pm4
, R_028BEC_PA_CL_GB_VERT_DISC_ADJ
, fui(1.0));
3261 si_pm4_set_reg(pm4
, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ
, fui(1.0));
3262 si_pm4_set_reg(pm4
, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ
, fui(1.0));
3263 si_pm4_set_reg(pm4
, R_028028_DB_STENCIL_CLEAR
, 0);
3264 si_pm4_set_reg(pm4
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 0x0);
3265 si_pm4_set_reg(pm4
, R_028AC4_DB_SRESULTS_COMPARE_STATE1
, 0x0);
3266 si_pm4_set_reg(pm4
, R_028AC8_DB_PRELOAD_CONTROL
, 0x0);
3268 /* There is a hang if stencil is used and fast stencil is enabled
3269 * regardless of whether HTILE is depth-only or not.
3271 si_pm4_set_reg(pm4
, R_02800C_DB_RENDER_OVERRIDE
,
3272 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE
) |
3273 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE
) |
3274 S_02800C_FAST_STENCIL_DISABLE(1));
3276 si_pm4_set_reg(pm4
, R_028400_VGT_MAX_VTX_INDX
, ~0);
3277 si_pm4_set_reg(pm4
, R_028404_VGT_MIN_VTX_INDX
, 0);
3278 si_pm4_set_reg(pm4
, R_028408_VGT_INDX_OFFSET
, 0);
3280 if (sctx
->b
.chip_class
>= CIK
) {
3281 si_pm4_set_reg(pm4
, R_00B51C_SPI_SHADER_PGM_RSRC3_LS
, S_00B51C_CU_EN(0xfffc));
3282 si_pm4_set_reg(pm4
, R_00B41C_SPI_SHADER_PGM_RSRC3_HS
, 0);
3283 si_pm4_set_reg(pm4
, R_00B31C_SPI_SHADER_PGM_RSRC3_ES
, S_00B31C_CU_EN(0xfffe));
3284 si_pm4_set_reg(pm4
, R_00B21C_SPI_SHADER_PGM_RSRC3_GS
, S_00B21C_CU_EN(0xffff));
3285 si_pm4_set_reg(pm4
, R_00B118_SPI_SHADER_PGM_RSRC3_VS
, S_00B118_CU_EN(0xffff));
3286 si_pm4_set_reg(pm4
, R_00B11C_SPI_SHADER_LATE_ALLOC_VS
, S_00B11C_LIMIT(0));
3287 si_pm4_set_reg(pm4
, R_00B01C_SPI_SHADER_PGM_RSRC3_PS
, S_00B01C_CU_EN(0xffff));
3290 if (sctx
->b
.chip_class
>= VI
) {
3291 si_pm4_set_reg(pm4
, R_028424_CB_DCC_CONTROL
,
3292 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1));
3293 si_pm4_set_reg(pm4
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
, 30);
3294 si_pm4_set_reg(pm4
, R_028C5C_VGT_OUT_DEALLOC_CNTL
, 32);
3297 sctx
->init_config
= pm4
;