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radeonsi: Add CIK SDMA support
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "si_shader.h"
29 #include "sid.h"
30 #include "radeon/r600_cs.h"
31
32 #include "util/u_format.h"
33 #include "util/u_format_s3tc.h"
34 #include "util/u_memory.h"
35 #include "util/u_pstipple.h"
36
37 static void si_init_atom(struct r600_atom *atom, struct r600_atom **list_elem,
38 void (*emit)(struct si_context *ctx, struct r600_atom *state),
39 unsigned num_dw)
40 {
41 atom->emit = (void*)emit;
42 atom->num_dw = num_dw;
43 atom->dirty = false;
44 *list_elem = atom;
45 }
46
47 unsigned si_array_mode(unsigned mode)
48 {
49 switch (mode) {
50 case RADEON_SURF_MODE_LINEAR_ALIGNED:
51 return V_009910_ARRAY_LINEAR_ALIGNED;
52 case RADEON_SURF_MODE_1D:
53 return V_009910_ARRAY_1D_TILED_THIN1;
54 case RADEON_SURF_MODE_2D:
55 return V_009910_ARRAY_2D_TILED_THIN1;
56 default:
57 case RADEON_SURF_MODE_LINEAR:
58 return V_009910_ARRAY_LINEAR_GENERAL;
59 }
60 }
61
62 uint32_t si_num_banks(struct si_screen *sscreen, struct r600_texture *tex)
63 {
64 if (sscreen->b.chip_class == CIK &&
65 sscreen->b.info.cik_macrotile_mode_array_valid) {
66 unsigned index, tileb;
67
68 tileb = 8 * 8 * tex->surface.bpe;
69 tileb = MIN2(tex->surface.tile_split, tileb);
70
71 for (index = 0; tileb > 64; index++) {
72 tileb >>= 1;
73 }
74 assert(index < 16);
75
76 return (sscreen->b.info.cik_macrotile_mode_array[index] >> 6) & 0x3;
77 }
78
79 if (sscreen->b.chip_class == SI &&
80 sscreen->b.info.si_tile_mode_array_valid) {
81 /* Don't use stencil_tiling_index, because num_banks is always
82 * read from the depth mode. */
83 unsigned tile_mode_index = tex->surface.tiling_index[0];
84 assert(tile_mode_index < 32);
85
86 return G_009910_NUM_BANKS(sscreen->b.info.si_tile_mode_array[tile_mode_index]);
87 }
88
89 /* The old way. */
90 switch (sscreen->b.tiling_info.num_banks) {
91 case 2:
92 return V_02803C_ADDR_SURF_2_BANK;
93 case 4:
94 return V_02803C_ADDR_SURF_4_BANK;
95 case 8:
96 default:
97 return V_02803C_ADDR_SURF_8_BANK;
98 case 16:
99 return V_02803C_ADDR_SURF_16_BANK;
100 }
101 }
102
103 unsigned cik_tile_split(unsigned tile_split)
104 {
105 switch (tile_split) {
106 case 64:
107 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_64B;
108 break;
109 case 128:
110 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_128B;
111 break;
112 case 256:
113 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_256B;
114 break;
115 case 512:
116 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_512B;
117 break;
118 default:
119 case 1024:
120 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_1KB;
121 break;
122 case 2048:
123 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_2KB;
124 break;
125 case 4096:
126 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_4KB;
127 break;
128 }
129 return tile_split;
130 }
131
132 unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect)
133 {
134 switch (macro_tile_aspect) {
135 default:
136 case 1:
137 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_1;
138 break;
139 case 2:
140 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_2;
141 break;
142 case 4:
143 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_4;
144 break;
145 case 8:
146 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_8;
147 break;
148 }
149 return macro_tile_aspect;
150 }
151
152 unsigned cik_bank_wh(unsigned bankwh)
153 {
154 switch (bankwh) {
155 default:
156 case 1:
157 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_1;
158 break;
159 case 2:
160 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_2;
161 break;
162 case 4:
163 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_4;
164 break;
165 case 8:
166 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_8;
167 break;
168 }
169 return bankwh;
170 }
171
172 unsigned cik_db_pipe_config(struct si_screen *sscreen, unsigned tile_mode)
173 {
174 if (sscreen->b.info.si_tile_mode_array_valid) {
175 uint32_t gb_tile_mode = sscreen->b.info.si_tile_mode_array[tile_mode];
176
177 return G_009910_PIPE_CONFIG(gb_tile_mode);
178 }
179
180 /* This is probably broken for a lot of chips, but it's only used
181 * if the kernel cannot return the tile mode array for CIK. */
182 switch (sscreen->b.info.r600_num_tile_pipes) {
183 case 16:
184 return V_02803C_X_ADDR_SURF_P16_32X32_16X16;
185 case 8:
186 return V_02803C_X_ADDR_SURF_P8_32X32_16X16;
187 case 4:
188 default:
189 if (sscreen->b.info.r600_num_backends == 4)
190 return V_02803C_X_ADDR_SURF_P4_16X16;
191 else
192 return V_02803C_X_ADDR_SURF_P4_8X16;
193 case 2:
194 return V_02803C_ADDR_SURF_P2;
195 }
196 }
197
198 static unsigned si_map_swizzle(unsigned swizzle)
199 {
200 switch (swizzle) {
201 case UTIL_FORMAT_SWIZZLE_Y:
202 return V_008F0C_SQ_SEL_Y;
203 case UTIL_FORMAT_SWIZZLE_Z:
204 return V_008F0C_SQ_SEL_Z;
205 case UTIL_FORMAT_SWIZZLE_W:
206 return V_008F0C_SQ_SEL_W;
207 case UTIL_FORMAT_SWIZZLE_0:
208 return V_008F0C_SQ_SEL_0;
209 case UTIL_FORMAT_SWIZZLE_1:
210 return V_008F0C_SQ_SEL_1;
211 default: /* UTIL_FORMAT_SWIZZLE_X */
212 return V_008F0C_SQ_SEL_X;
213 }
214 }
215
216 static uint32_t S_FIXED(float value, uint32_t frac_bits)
217 {
218 return value * (1 << frac_bits);
219 }
220
221 /* 12.4 fixed-point */
222 static unsigned si_pack_float_12p4(float x)
223 {
224 return x <= 0 ? 0 :
225 x >= 4096 ? 0xffff : x * 16;
226 }
227
228 /*
229 * Inferred framebuffer and blender state.
230 *
231 * One of the reasons this must be derived from the framebuffer state is that:
232 * - The blend state mask is 0xf most of the time.
233 * - The COLOR1 format isn't INVALID because of possible dual-source blending,
234 * so COLOR1 is enabled pretty much all the time.
235 * So CB_TARGET_MASK is the only register that can disable COLOR1.
236 */
237 static void si_update_fb_blend_state(struct si_context *sctx)
238 {
239 struct si_pm4_state *pm4;
240 struct si_state_blend *blend = sctx->queued.named.blend;
241 uint32_t mask = 0, i;
242
243 if (blend == NULL)
244 return;
245
246 pm4 = CALLOC_STRUCT(si_pm4_state);
247 if (pm4 == NULL)
248 return;
249
250 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++)
251 if (sctx->framebuffer.state.cbufs[i])
252 mask |= 0xf << (4*i);
253 mask &= blend->cb_target_mask;
254
255 si_pm4_set_reg(pm4, R_028238_CB_TARGET_MASK, mask);
256 si_pm4_set_state(sctx, fb_blend, pm4);
257 }
258
259 /*
260 * Blender functions
261 */
262
263 static uint32_t si_translate_blend_function(int blend_func)
264 {
265 switch (blend_func) {
266 case PIPE_BLEND_ADD:
267 return V_028780_COMB_DST_PLUS_SRC;
268 case PIPE_BLEND_SUBTRACT:
269 return V_028780_COMB_SRC_MINUS_DST;
270 case PIPE_BLEND_REVERSE_SUBTRACT:
271 return V_028780_COMB_DST_MINUS_SRC;
272 case PIPE_BLEND_MIN:
273 return V_028780_COMB_MIN_DST_SRC;
274 case PIPE_BLEND_MAX:
275 return V_028780_COMB_MAX_DST_SRC;
276 default:
277 R600_ERR("Unknown blend function %d\n", blend_func);
278 assert(0);
279 break;
280 }
281 return 0;
282 }
283
284 static uint32_t si_translate_blend_factor(int blend_fact)
285 {
286 switch (blend_fact) {
287 case PIPE_BLENDFACTOR_ONE:
288 return V_028780_BLEND_ONE;
289 case PIPE_BLENDFACTOR_SRC_COLOR:
290 return V_028780_BLEND_SRC_COLOR;
291 case PIPE_BLENDFACTOR_SRC_ALPHA:
292 return V_028780_BLEND_SRC_ALPHA;
293 case PIPE_BLENDFACTOR_DST_ALPHA:
294 return V_028780_BLEND_DST_ALPHA;
295 case PIPE_BLENDFACTOR_DST_COLOR:
296 return V_028780_BLEND_DST_COLOR;
297 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
298 return V_028780_BLEND_SRC_ALPHA_SATURATE;
299 case PIPE_BLENDFACTOR_CONST_COLOR:
300 return V_028780_BLEND_CONSTANT_COLOR;
301 case PIPE_BLENDFACTOR_CONST_ALPHA:
302 return V_028780_BLEND_CONSTANT_ALPHA;
303 case PIPE_BLENDFACTOR_ZERO:
304 return V_028780_BLEND_ZERO;
305 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
306 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
307 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
308 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
309 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
310 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
311 case PIPE_BLENDFACTOR_INV_DST_COLOR:
312 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
313 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
314 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
315 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
316 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
317 case PIPE_BLENDFACTOR_SRC1_COLOR:
318 return V_028780_BLEND_SRC1_COLOR;
319 case PIPE_BLENDFACTOR_SRC1_ALPHA:
320 return V_028780_BLEND_SRC1_ALPHA;
321 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
322 return V_028780_BLEND_INV_SRC1_COLOR;
323 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
324 return V_028780_BLEND_INV_SRC1_ALPHA;
325 default:
326 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
327 assert(0);
328 break;
329 }
330 return 0;
331 }
332
333 static void *si_create_blend_state_mode(struct pipe_context *ctx,
334 const struct pipe_blend_state *state,
335 unsigned mode)
336 {
337 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
338 struct si_pm4_state *pm4 = &blend->pm4;
339
340 uint32_t color_control = 0;
341
342 if (blend == NULL)
343 return NULL;
344
345 blend->alpha_to_one = state->alpha_to_one;
346
347 if (state->logicop_enable) {
348 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
349 } else {
350 color_control |= S_028808_ROP3(0xcc);
351 }
352
353 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
354 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
355 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
356 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
357 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
358 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
359
360 blend->cb_target_mask = 0;
361 for (int i = 0; i < 8; i++) {
362 /* state->rt entries > 0 only written if independent blending */
363 const int j = state->independent_blend_enable ? i : 0;
364
365 unsigned eqRGB = state->rt[j].rgb_func;
366 unsigned srcRGB = state->rt[j].rgb_src_factor;
367 unsigned dstRGB = state->rt[j].rgb_dst_factor;
368 unsigned eqA = state->rt[j].alpha_func;
369 unsigned srcA = state->rt[j].alpha_src_factor;
370 unsigned dstA = state->rt[j].alpha_dst_factor;
371
372 unsigned blend_cntl = 0;
373
374 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
375 blend->cb_target_mask |= state->rt[j].colormask << (4 * i);
376
377 if (!state->rt[j].blend_enable) {
378 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
379 continue;
380 }
381
382 blend_cntl |= S_028780_ENABLE(1);
383 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
384 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
385 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
386
387 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
388 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
389 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
390 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
391 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
392 }
393 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
394 }
395
396 if (blend->cb_target_mask) {
397 color_control |= S_028808_MODE(mode);
398 } else {
399 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
400 }
401 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
402
403 return blend;
404 }
405
406 static void *si_create_blend_state(struct pipe_context *ctx,
407 const struct pipe_blend_state *state)
408 {
409 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
410 }
411
412 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
413 {
414 struct si_context *sctx = (struct si_context *)ctx;
415 si_pm4_bind_state(sctx, blend, (struct si_state_blend *)state);
416 si_update_fb_blend_state(sctx);
417 }
418
419 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
420 {
421 struct si_context *sctx = (struct si_context *)ctx;
422 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
423 }
424
425 static void si_set_blend_color(struct pipe_context *ctx,
426 const struct pipe_blend_color *state)
427 {
428 struct si_context *sctx = (struct si_context *)ctx;
429 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
430
431 if (pm4 == NULL)
432 return;
433
434 si_pm4_set_reg(pm4, R_028414_CB_BLEND_RED, fui(state->color[0]));
435 si_pm4_set_reg(pm4, R_028418_CB_BLEND_GREEN, fui(state->color[1]));
436 si_pm4_set_reg(pm4, R_02841C_CB_BLEND_BLUE, fui(state->color[2]));
437 si_pm4_set_reg(pm4, R_028420_CB_BLEND_ALPHA, fui(state->color[3]));
438
439 si_pm4_set_state(sctx, blend_color, pm4);
440 }
441
442 /*
443 * Clipping, scissors and viewport
444 */
445
446 static void si_set_clip_state(struct pipe_context *ctx,
447 const struct pipe_clip_state *state)
448 {
449 struct si_context *sctx = (struct si_context *)ctx;
450 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
451 struct pipe_constant_buffer cb;
452
453 if (pm4 == NULL)
454 return;
455
456 for (int i = 0; i < 6; i++) {
457 si_pm4_set_reg(pm4, R_0285BC_PA_CL_UCP_0_X + i * 16,
458 fui(state->ucp[i][0]));
459 si_pm4_set_reg(pm4, R_0285C0_PA_CL_UCP_0_Y + i * 16,
460 fui(state->ucp[i][1]));
461 si_pm4_set_reg(pm4, R_0285C4_PA_CL_UCP_0_Z + i * 16,
462 fui(state->ucp[i][2]));
463 si_pm4_set_reg(pm4, R_0285C8_PA_CL_UCP_0_W + i * 16,
464 fui(state->ucp[i][3]));
465 }
466
467 cb.buffer = NULL;
468 cb.user_buffer = state->ucp;
469 cb.buffer_offset = 0;
470 cb.buffer_size = 4*4*8;
471 ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, SI_DRIVER_STATE_CONST_BUF, &cb);
472 pipe_resource_reference(&cb.buffer, NULL);
473
474 si_pm4_set_state(sctx, clip, pm4);
475 }
476
477 #define SIX_BITS 0x3F
478
479 static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom)
480 {
481 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
482 struct tgsi_shader_info *info = si_get_vs_info(sctx);
483 unsigned window_space =
484 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
485 unsigned clipdist_mask =
486 info->writes_clipvertex ? SIX_BITS : info->clipdist_writemask;
487
488 r600_write_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
489 S_02881C_USE_VTX_POINT_SIZE(info->writes_psize) |
490 S_02881C_USE_VTX_EDGE_FLAG(info->writes_edgeflag) |
491 S_02881C_USE_VTX_RENDER_TARGET_INDX(info->writes_layer) |
492 S_02881C_VS_OUT_CCDIST0_VEC_ENA((clipdist_mask & 0x0F) != 0) |
493 S_02881C_VS_OUT_CCDIST1_VEC_ENA((clipdist_mask & 0xF0) != 0) |
494 S_02881C_VS_OUT_MISC_VEC_ENA(info->writes_psize ||
495 info->writes_edgeflag ||
496 info->writes_layer) |
497 (sctx->queued.named.rasterizer->clip_plane_enable &
498 clipdist_mask));
499 r600_write_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
500 sctx->queued.named.rasterizer->pa_cl_clip_cntl |
501 (clipdist_mask ? 0 :
502 sctx->queued.named.rasterizer->clip_plane_enable & SIX_BITS) |
503 S_028810_CLIP_DISABLE(window_space));
504 }
505
506 static void si_set_scissor_states(struct pipe_context *ctx,
507 unsigned start_slot,
508 unsigned num_scissors,
509 const struct pipe_scissor_state *state)
510 {
511 struct si_context *sctx = (struct si_context *)ctx;
512 struct si_state_scissor *scissor = CALLOC_STRUCT(si_state_scissor);
513 struct si_pm4_state *pm4 = &scissor->pm4;
514
515 if (scissor == NULL)
516 return;
517
518 scissor->scissor = *state;
519 si_pm4_set_reg(pm4, R_028250_PA_SC_VPORT_SCISSOR_0_TL,
520 S_028250_TL_X(state->minx) | S_028250_TL_Y(state->miny) |
521 S_028250_WINDOW_OFFSET_DISABLE(1));
522 si_pm4_set_reg(pm4, R_028254_PA_SC_VPORT_SCISSOR_0_BR,
523 S_028254_BR_X(state->maxx) | S_028254_BR_Y(state->maxy));
524
525 si_pm4_set_state(sctx, scissor, scissor);
526 }
527
528 static void si_set_viewport_states(struct pipe_context *ctx,
529 unsigned start_slot,
530 unsigned num_viewports,
531 const struct pipe_viewport_state *state)
532 {
533 struct si_context *sctx = (struct si_context *)ctx;
534 struct si_state_viewport *viewport = CALLOC_STRUCT(si_state_viewport);
535 struct si_pm4_state *pm4 = &viewport->pm4;
536
537 if (viewport == NULL)
538 return;
539
540 viewport->viewport = *state;
541 si_pm4_set_reg(pm4, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
542 si_pm4_set_reg(pm4, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
543 si_pm4_set_reg(pm4, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
544 si_pm4_set_reg(pm4, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
545 si_pm4_set_reg(pm4, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
546 si_pm4_set_reg(pm4, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
547
548 si_pm4_set_state(sctx, viewport, viewport);
549 }
550
551 /*
552 * inferred state between framebuffer and rasterizer
553 */
554 static void si_update_fb_rs_state(struct si_context *sctx)
555 {
556 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
557 struct si_pm4_state *pm4;
558 float offset_units;
559
560 if (!rs || !sctx->framebuffer.state.zsbuf)
561 return;
562
563 offset_units = sctx->queued.named.rasterizer->offset_units;
564 switch (sctx->framebuffer.state.zsbuf->texture->format) {
565 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
566 case PIPE_FORMAT_X8Z24_UNORM:
567 case PIPE_FORMAT_Z24X8_UNORM:
568 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
569 offset_units *= 2.0f;
570 break;
571 case PIPE_FORMAT_Z32_FLOAT:
572 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
573 offset_units *= 1.0f;
574 break;
575 case PIPE_FORMAT_Z16_UNORM:
576 offset_units *= 4.0f;
577 break;
578 default:
579 return;
580 }
581
582 pm4 = CALLOC_STRUCT(si_pm4_state);
583
584 if (pm4 == NULL)
585 return;
586
587 /* FIXME some of those reg can be computed with cso */
588 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
589 fui(sctx->queued.named.rasterizer->offset_scale));
590 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units));
591 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
592 fui(sctx->queued.named.rasterizer->offset_scale));
593 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units));
594
595 si_pm4_set_state(sctx, fb_rs, pm4);
596 }
597
598 /*
599 * Rasterizer
600 */
601
602 static uint32_t si_translate_fill(uint32_t func)
603 {
604 switch(func) {
605 case PIPE_POLYGON_MODE_FILL:
606 return V_028814_X_DRAW_TRIANGLES;
607 case PIPE_POLYGON_MODE_LINE:
608 return V_028814_X_DRAW_LINES;
609 case PIPE_POLYGON_MODE_POINT:
610 return V_028814_X_DRAW_POINTS;
611 default:
612 assert(0);
613 return V_028814_X_DRAW_POINTS;
614 }
615 }
616
617 static void *si_create_rs_state(struct pipe_context *ctx,
618 const struct pipe_rasterizer_state *state)
619 {
620 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
621 struct si_pm4_state *pm4 = &rs->pm4;
622 unsigned tmp;
623 float psize_min, psize_max;
624
625 if (rs == NULL) {
626 return NULL;
627 }
628
629 rs->two_side = state->light_twoside;
630 rs->multisample_enable = state->multisample;
631 rs->clip_plane_enable = state->clip_plane_enable;
632 rs->line_stipple_enable = state->line_stipple_enable;
633 rs->poly_stipple_enable = state->poly_stipple_enable;
634 rs->line_smooth = state->line_smooth;
635 rs->poly_smooth = state->poly_smooth;
636
637 rs->flatshade = state->flatshade;
638 rs->sprite_coord_enable = state->sprite_coord_enable;
639 rs->pa_sc_line_stipple = state->line_stipple_enable ?
640 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
641 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
642 rs->pa_cl_clip_cntl =
643 S_028810_PS_UCP_MODE(3) |
644 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
645 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
646 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
647 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
648 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
649
650 /* offset */
651 rs->offset_units = state->offset_units;
652 rs->offset_scale = state->offset_scale * 12.0f;
653
654 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
655 S_0286D4_FLAT_SHADE_ENA(1) |
656 S_0286D4_PNT_SPRITE_ENA(1) |
657 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
658 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
659 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
660 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
661 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
662
663 /* point size 12.4 fixed point */
664 tmp = (unsigned)(state->point_size * 8.0);
665 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
666
667 if (state->point_size_per_vertex) {
668 psize_min = util_get_min_point_size(state);
669 psize_max = 8192;
670 } else {
671 /* Force the point size to be as if the vertex output was disabled. */
672 psize_min = state->point_size;
673 psize_max = state->point_size;
674 }
675 /* Divide by two, because 0.5 = 1 pixel. */
676 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
677 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
678 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
679
680 tmp = (unsigned)state->line_width * 8;
681 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
682 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
683 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
684 S_028A48_MSAA_ENABLE(state->multisample ||
685 state->poly_smooth ||
686 state->line_smooth) |
687 S_028A48_VPORT_SCISSOR_ENABLE(state->scissor));
688
689 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
690 S_028BE4_PIX_CENTER(state->half_pixel_center) |
691 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
692
693 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
694 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
695 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
696 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
697 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
698 S_028814_FACE(!state->front_ccw) |
699 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
700 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
701 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
702 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
703 state->fill_back != PIPE_POLYGON_MODE_FILL) |
704 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
705 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
706 return rs;
707 }
708
709 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
710 {
711 struct si_context *sctx = (struct si_context *)ctx;
712 struct si_state_rasterizer *old_rs =
713 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
714 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
715
716 if (state == NULL)
717 return;
718
719 if (sctx->framebuffer.nr_samples > 1 &&
720 (!old_rs || old_rs->multisample_enable != rs->multisample_enable))
721 sctx->db_render_state.dirty = true;
722
723 si_pm4_bind_state(sctx, rasterizer, rs);
724 si_update_fb_rs_state(sctx);
725
726 sctx->clip_regs.dirty = true;
727 }
728
729 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
730 {
731 struct si_context *sctx = (struct si_context *)ctx;
732 si_pm4_delete_state(sctx, rasterizer, (struct si_state_rasterizer *)state);
733 }
734
735 /*
736 * infeered state between dsa and stencil ref
737 */
738 static void si_update_dsa_stencil_ref(struct si_context *sctx)
739 {
740 struct si_pm4_state *pm4;
741 struct pipe_stencil_ref *ref = &sctx->stencil_ref;
742 struct si_state_dsa *dsa = sctx->queued.named.dsa;
743
744 if (!dsa)
745 return;
746
747 pm4 = CALLOC_STRUCT(si_pm4_state);
748 if (pm4 == NULL)
749 return;
750
751 si_pm4_set_reg(pm4, R_028430_DB_STENCILREFMASK,
752 S_028430_STENCILTESTVAL(ref->ref_value[0]) |
753 S_028430_STENCILMASK(dsa->valuemask[0]) |
754 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
755 S_028430_STENCILOPVAL(1));
756 si_pm4_set_reg(pm4, R_028434_DB_STENCILREFMASK_BF,
757 S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
758 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
759 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
760 S_028434_STENCILOPVAL_BF(1));
761
762 si_pm4_set_state(sctx, dsa_stencil_ref, pm4);
763 }
764
765 static void si_set_pipe_stencil_ref(struct pipe_context *ctx,
766 const struct pipe_stencil_ref *state)
767 {
768 struct si_context *sctx = (struct si_context *)ctx;
769 sctx->stencil_ref = *state;
770 si_update_dsa_stencil_ref(sctx);
771 }
772
773
774 /*
775 * DSA
776 */
777
778 static uint32_t si_translate_stencil_op(int s_op)
779 {
780 switch (s_op) {
781 case PIPE_STENCIL_OP_KEEP:
782 return V_02842C_STENCIL_KEEP;
783 case PIPE_STENCIL_OP_ZERO:
784 return V_02842C_STENCIL_ZERO;
785 case PIPE_STENCIL_OP_REPLACE:
786 return V_02842C_STENCIL_REPLACE_TEST;
787 case PIPE_STENCIL_OP_INCR:
788 return V_02842C_STENCIL_ADD_CLAMP;
789 case PIPE_STENCIL_OP_DECR:
790 return V_02842C_STENCIL_SUB_CLAMP;
791 case PIPE_STENCIL_OP_INCR_WRAP:
792 return V_02842C_STENCIL_ADD_WRAP;
793 case PIPE_STENCIL_OP_DECR_WRAP:
794 return V_02842C_STENCIL_SUB_WRAP;
795 case PIPE_STENCIL_OP_INVERT:
796 return V_02842C_STENCIL_INVERT;
797 default:
798 R600_ERR("Unknown stencil op %d", s_op);
799 assert(0);
800 break;
801 }
802 return 0;
803 }
804
805 static void *si_create_dsa_state(struct pipe_context *ctx,
806 const struct pipe_depth_stencil_alpha_state *state)
807 {
808 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
809 struct si_pm4_state *pm4 = &dsa->pm4;
810 unsigned db_depth_control;
811 uint32_t db_stencil_control = 0;
812
813 if (dsa == NULL) {
814 return NULL;
815 }
816
817 dsa->valuemask[0] = state->stencil[0].valuemask;
818 dsa->valuemask[1] = state->stencil[1].valuemask;
819 dsa->writemask[0] = state->stencil[0].writemask;
820 dsa->writemask[1] = state->stencil[1].writemask;
821
822 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
823 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
824 S_028800_ZFUNC(state->depth.func);
825
826 /* stencil */
827 if (state->stencil[0].enabled) {
828 db_depth_control |= S_028800_STENCIL_ENABLE(1);
829 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
830 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
831 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
832 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
833
834 if (state->stencil[1].enabled) {
835 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
836 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
837 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
838 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
839 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
840 }
841 }
842
843 /* alpha */
844 if (state->alpha.enabled) {
845 dsa->alpha_func = state->alpha.func;
846
847 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
848 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
849 } else {
850 dsa->alpha_func = PIPE_FUNC_ALWAYS;
851 }
852
853 /* misc */
854 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
855 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
856
857 return dsa;
858 }
859
860 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
861 {
862 struct si_context *sctx = (struct si_context *)ctx;
863 struct si_state_dsa *dsa = state;
864
865 if (state == NULL)
866 return;
867
868 si_pm4_bind_state(sctx, dsa, dsa);
869 si_update_dsa_stencil_ref(sctx);
870 }
871
872 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
873 {
874 struct si_context *sctx = (struct si_context *)ctx;
875 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
876 }
877
878 static void *si_create_db_flush_dsa(struct si_context *sctx)
879 {
880 struct pipe_depth_stencil_alpha_state dsa = {};
881
882 return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
883 }
884
885 /* DB RENDER STATE */
886
887 static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
888 {
889 struct si_context *sctx = (struct si_context*)ctx;
890
891 sctx->db_render_state.dirty = true;
892 }
893
894 static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
895 {
896 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
897 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
898 unsigned db_shader_control;
899
900 r600_write_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
901
902 /* DB_RENDER_CONTROL */
903 if (sctx->dbcb_depth_copy_enabled ||
904 sctx->dbcb_stencil_copy_enabled) {
905 radeon_emit(cs,
906 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
907 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
908 S_028000_COPY_CENTROID(1) |
909 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
910 } else if (sctx->db_inplace_flush_enabled) {
911 radeon_emit(cs,
912 S_028000_DEPTH_COMPRESS_DISABLE(1) |
913 S_028000_STENCIL_COMPRESS_DISABLE(1));
914 } else if (sctx->db_depth_clear) {
915 radeon_emit(cs, S_028000_DEPTH_CLEAR_ENABLE(1));
916 } else {
917 radeon_emit(cs, 0);
918 }
919
920 /* DB_COUNT_CONTROL (occlusion queries) */
921 if (sctx->b.num_occlusion_queries > 0) {
922 if (sctx->b.chip_class >= CIK) {
923 radeon_emit(cs,
924 S_028004_PERFECT_ZPASS_COUNTS(1) |
925 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
926 S_028004_ZPASS_ENABLE(1) |
927 S_028004_SLICE_EVEN_ENABLE(1) |
928 S_028004_SLICE_ODD_ENABLE(1));
929 } else {
930 radeon_emit(cs,
931 S_028004_PERFECT_ZPASS_COUNTS(1) |
932 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
933 }
934 } else {
935 /* Disable occlusion queries. */
936 if (sctx->b.chip_class >= CIK) {
937 radeon_emit(cs, 0);
938 } else {
939 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
940 }
941 }
942
943 /* DB_RENDER_OVERRIDE2 */
944 if (sctx->db_depth_disable_expclear) {
945 r600_write_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
946 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(1));
947 } else {
948 r600_write_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2, 0);
949 }
950
951 db_shader_control = S_02880C_ALPHA_TO_MASK_DISABLE(sctx->framebuffer.cb0_is_integer) |
952 sctx->ps_db_shader_control;
953
954 /* Bug workaround for smoothing (overrasterization) on SI. */
955 if (sctx->b.chip_class == SI && sctx->smoothing_enabled)
956 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
957 else
958 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
959
960 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
961 if (sctx->framebuffer.nr_samples <= 1 || (rs && !rs->multisample_enable))
962 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
963
964 r600_write_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
965 db_shader_control);
966 }
967
968 /*
969 * format translation
970 */
971 static uint32_t si_translate_colorformat(enum pipe_format format)
972 {
973 const struct util_format_description *desc = util_format_description(format);
974
975 #define HAS_SIZE(x,y,z,w) \
976 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
977 desc->channel[2].size == (z) && desc->channel[3].size == (w))
978
979 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
980 return V_028C70_COLOR_10_11_11;
981
982 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
983 return V_028C70_COLOR_INVALID;
984
985 switch (desc->nr_channels) {
986 case 1:
987 switch (desc->channel[0].size) {
988 case 8:
989 return V_028C70_COLOR_8;
990 case 16:
991 return V_028C70_COLOR_16;
992 case 32:
993 return V_028C70_COLOR_32;
994 }
995 break;
996 case 2:
997 if (desc->channel[0].size == desc->channel[1].size) {
998 switch (desc->channel[0].size) {
999 case 8:
1000 return V_028C70_COLOR_8_8;
1001 case 16:
1002 return V_028C70_COLOR_16_16;
1003 case 32:
1004 return V_028C70_COLOR_32_32;
1005 }
1006 } else if (HAS_SIZE(8,24,0,0)) {
1007 return V_028C70_COLOR_24_8;
1008 } else if (HAS_SIZE(24,8,0,0)) {
1009 return V_028C70_COLOR_8_24;
1010 }
1011 break;
1012 case 3:
1013 if (HAS_SIZE(5,6,5,0)) {
1014 return V_028C70_COLOR_5_6_5;
1015 } else if (HAS_SIZE(32,8,24,0)) {
1016 return V_028C70_COLOR_X24_8_32_FLOAT;
1017 }
1018 break;
1019 case 4:
1020 if (desc->channel[0].size == desc->channel[1].size &&
1021 desc->channel[0].size == desc->channel[2].size &&
1022 desc->channel[0].size == desc->channel[3].size) {
1023 switch (desc->channel[0].size) {
1024 case 4:
1025 return V_028C70_COLOR_4_4_4_4;
1026 case 8:
1027 return V_028C70_COLOR_8_8_8_8;
1028 case 16:
1029 return V_028C70_COLOR_16_16_16_16;
1030 case 32:
1031 return V_028C70_COLOR_32_32_32_32;
1032 }
1033 } else if (HAS_SIZE(5,5,5,1)) {
1034 return V_028C70_COLOR_1_5_5_5;
1035 } else if (HAS_SIZE(10,10,10,2)) {
1036 return V_028C70_COLOR_2_10_10_10;
1037 }
1038 break;
1039 }
1040 return V_028C70_COLOR_INVALID;
1041 }
1042
1043 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1044 {
1045 if (SI_BIG_ENDIAN) {
1046 switch(colorformat) {
1047 /* 8-bit buffers. */
1048 case V_028C70_COLOR_8:
1049 return V_028C70_ENDIAN_NONE;
1050
1051 /* 16-bit buffers. */
1052 case V_028C70_COLOR_5_6_5:
1053 case V_028C70_COLOR_1_5_5_5:
1054 case V_028C70_COLOR_4_4_4_4:
1055 case V_028C70_COLOR_16:
1056 case V_028C70_COLOR_8_8:
1057 return V_028C70_ENDIAN_8IN16;
1058
1059 /* 32-bit buffers. */
1060 case V_028C70_COLOR_8_8_8_8:
1061 case V_028C70_COLOR_2_10_10_10:
1062 case V_028C70_COLOR_8_24:
1063 case V_028C70_COLOR_24_8:
1064 case V_028C70_COLOR_16_16:
1065 return V_028C70_ENDIAN_8IN32;
1066
1067 /* 64-bit buffers. */
1068 case V_028C70_COLOR_16_16_16_16:
1069 return V_028C70_ENDIAN_8IN16;
1070
1071 case V_028C70_COLOR_32_32:
1072 return V_028C70_ENDIAN_8IN32;
1073
1074 /* 128-bit buffers. */
1075 case V_028C70_COLOR_32_32_32_32:
1076 return V_028C70_ENDIAN_8IN32;
1077 default:
1078 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1079 }
1080 } else {
1081 return V_028C70_ENDIAN_NONE;
1082 }
1083 }
1084
1085 /* Returns the size in bits of the widest component of a CB format */
1086 static unsigned si_colorformat_max_comp_size(uint32_t colorformat)
1087 {
1088 switch(colorformat) {
1089 case V_028C70_COLOR_4_4_4_4:
1090 return 4;
1091
1092 case V_028C70_COLOR_1_5_5_5:
1093 case V_028C70_COLOR_5_5_5_1:
1094 return 5;
1095
1096 case V_028C70_COLOR_5_6_5:
1097 return 6;
1098
1099 case V_028C70_COLOR_8:
1100 case V_028C70_COLOR_8_8:
1101 case V_028C70_COLOR_8_8_8_8:
1102 return 8;
1103
1104 case V_028C70_COLOR_10_10_10_2:
1105 case V_028C70_COLOR_2_10_10_10:
1106 return 10;
1107
1108 case V_028C70_COLOR_10_11_11:
1109 case V_028C70_COLOR_11_11_10:
1110 return 11;
1111
1112 case V_028C70_COLOR_16:
1113 case V_028C70_COLOR_16_16:
1114 case V_028C70_COLOR_16_16_16_16:
1115 return 16;
1116
1117 case V_028C70_COLOR_8_24:
1118 case V_028C70_COLOR_24_8:
1119 return 24;
1120
1121 case V_028C70_COLOR_32:
1122 case V_028C70_COLOR_32_32:
1123 case V_028C70_COLOR_32_32_32_32:
1124 case V_028C70_COLOR_X24_8_32_FLOAT:
1125 return 32;
1126 }
1127
1128 assert(!"Unknown maximum component size");
1129 return 0;
1130 }
1131
1132 static uint32_t si_translate_dbformat(enum pipe_format format)
1133 {
1134 switch (format) {
1135 case PIPE_FORMAT_Z16_UNORM:
1136 return V_028040_Z_16;
1137 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1138 case PIPE_FORMAT_X8Z24_UNORM:
1139 case PIPE_FORMAT_Z24X8_UNORM:
1140 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1141 return V_028040_Z_24; /* deprecated on SI */
1142 case PIPE_FORMAT_Z32_FLOAT:
1143 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1144 return V_028040_Z_32_FLOAT;
1145 default:
1146 return V_028040_Z_INVALID;
1147 }
1148 }
1149
1150 /*
1151 * Texture translation
1152 */
1153
1154 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1155 enum pipe_format format,
1156 const struct util_format_description *desc,
1157 int first_non_void)
1158 {
1159 struct si_screen *sscreen = (struct si_screen*)screen;
1160 bool enable_s3tc = sscreen->b.info.drm_minor >= 31;
1161 boolean uniform = TRUE;
1162 int i;
1163
1164 /* Colorspace (return non-RGB formats directly). */
1165 switch (desc->colorspace) {
1166 /* Depth stencil formats */
1167 case UTIL_FORMAT_COLORSPACE_ZS:
1168 switch (format) {
1169 case PIPE_FORMAT_Z16_UNORM:
1170 return V_008F14_IMG_DATA_FORMAT_16;
1171 case PIPE_FORMAT_X24S8_UINT:
1172 case PIPE_FORMAT_Z24X8_UNORM:
1173 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1174 return V_008F14_IMG_DATA_FORMAT_8_24;
1175 case PIPE_FORMAT_X8Z24_UNORM:
1176 case PIPE_FORMAT_S8X24_UINT:
1177 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1178 return V_008F14_IMG_DATA_FORMAT_24_8;
1179 case PIPE_FORMAT_S8_UINT:
1180 return V_008F14_IMG_DATA_FORMAT_8;
1181 case PIPE_FORMAT_Z32_FLOAT:
1182 return V_008F14_IMG_DATA_FORMAT_32;
1183 case PIPE_FORMAT_X32_S8X24_UINT:
1184 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1185 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1186 default:
1187 goto out_unknown;
1188 }
1189
1190 case UTIL_FORMAT_COLORSPACE_YUV:
1191 goto out_unknown; /* TODO */
1192
1193 case UTIL_FORMAT_COLORSPACE_SRGB:
1194 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1195 goto out_unknown;
1196 break;
1197
1198 default:
1199 break;
1200 }
1201
1202 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1203 if (!enable_s3tc)
1204 goto out_unknown;
1205
1206 switch (format) {
1207 case PIPE_FORMAT_RGTC1_SNORM:
1208 case PIPE_FORMAT_LATC1_SNORM:
1209 case PIPE_FORMAT_RGTC1_UNORM:
1210 case PIPE_FORMAT_LATC1_UNORM:
1211 return V_008F14_IMG_DATA_FORMAT_BC4;
1212 case PIPE_FORMAT_RGTC2_SNORM:
1213 case PIPE_FORMAT_LATC2_SNORM:
1214 case PIPE_FORMAT_RGTC2_UNORM:
1215 case PIPE_FORMAT_LATC2_UNORM:
1216 return V_008F14_IMG_DATA_FORMAT_BC5;
1217 default:
1218 goto out_unknown;
1219 }
1220 }
1221
1222 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1223 if (!enable_s3tc)
1224 goto out_unknown;
1225
1226 switch (format) {
1227 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1228 case PIPE_FORMAT_BPTC_SRGBA:
1229 return V_008F14_IMG_DATA_FORMAT_BC7;
1230 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1231 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1232 return V_008F14_IMG_DATA_FORMAT_BC6;
1233 default:
1234 goto out_unknown;
1235 }
1236 }
1237
1238 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1239 switch (format) {
1240 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1241 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1242 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1243 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1244 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1245 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1246 default:
1247 goto out_unknown;
1248 }
1249 }
1250
1251 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1252
1253 if (!enable_s3tc)
1254 goto out_unknown;
1255
1256 if (!util_format_s3tc_enabled) {
1257 goto out_unknown;
1258 }
1259
1260 switch (format) {
1261 case PIPE_FORMAT_DXT1_RGB:
1262 case PIPE_FORMAT_DXT1_RGBA:
1263 case PIPE_FORMAT_DXT1_SRGB:
1264 case PIPE_FORMAT_DXT1_SRGBA:
1265 return V_008F14_IMG_DATA_FORMAT_BC1;
1266 case PIPE_FORMAT_DXT3_RGBA:
1267 case PIPE_FORMAT_DXT3_SRGBA:
1268 return V_008F14_IMG_DATA_FORMAT_BC2;
1269 case PIPE_FORMAT_DXT5_RGBA:
1270 case PIPE_FORMAT_DXT5_SRGBA:
1271 return V_008F14_IMG_DATA_FORMAT_BC3;
1272 default:
1273 goto out_unknown;
1274 }
1275 }
1276
1277 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1278 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1279 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1280 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1281 }
1282
1283 /* R8G8Bx_SNORM - TODO CxV8U8 */
1284
1285 /* See whether the components are of the same size. */
1286 for (i = 1; i < desc->nr_channels; i++) {
1287 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1288 }
1289
1290 /* Non-uniform formats. */
1291 if (!uniform) {
1292 switch(desc->nr_channels) {
1293 case 3:
1294 if (desc->channel[0].size == 5 &&
1295 desc->channel[1].size == 6 &&
1296 desc->channel[2].size == 5) {
1297 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1298 }
1299 goto out_unknown;
1300 case 4:
1301 if (desc->channel[0].size == 5 &&
1302 desc->channel[1].size == 5 &&
1303 desc->channel[2].size == 5 &&
1304 desc->channel[3].size == 1) {
1305 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1306 }
1307 if (desc->channel[0].size == 10 &&
1308 desc->channel[1].size == 10 &&
1309 desc->channel[2].size == 10 &&
1310 desc->channel[3].size == 2) {
1311 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1312 }
1313 goto out_unknown;
1314 }
1315 goto out_unknown;
1316 }
1317
1318 if (first_non_void < 0 || first_non_void > 3)
1319 goto out_unknown;
1320
1321 /* uniform formats */
1322 switch (desc->channel[first_non_void].size) {
1323 case 4:
1324 switch (desc->nr_channels) {
1325 #if 0 /* Not supported for render targets */
1326 case 2:
1327 return V_008F14_IMG_DATA_FORMAT_4_4;
1328 #endif
1329 case 4:
1330 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1331 }
1332 break;
1333 case 8:
1334 switch (desc->nr_channels) {
1335 case 1:
1336 return V_008F14_IMG_DATA_FORMAT_8;
1337 case 2:
1338 return V_008F14_IMG_DATA_FORMAT_8_8;
1339 case 4:
1340 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1341 }
1342 break;
1343 case 16:
1344 switch (desc->nr_channels) {
1345 case 1:
1346 return V_008F14_IMG_DATA_FORMAT_16;
1347 case 2:
1348 return V_008F14_IMG_DATA_FORMAT_16_16;
1349 case 4:
1350 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1351 }
1352 break;
1353 case 32:
1354 switch (desc->nr_channels) {
1355 case 1:
1356 return V_008F14_IMG_DATA_FORMAT_32;
1357 case 2:
1358 return V_008F14_IMG_DATA_FORMAT_32_32;
1359 #if 0 /* Not supported for render targets */
1360 case 3:
1361 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1362 #endif
1363 case 4:
1364 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1365 }
1366 }
1367
1368 out_unknown:
1369 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1370 return ~0;
1371 }
1372
1373 static unsigned si_tex_wrap(unsigned wrap)
1374 {
1375 switch (wrap) {
1376 default:
1377 case PIPE_TEX_WRAP_REPEAT:
1378 return V_008F30_SQ_TEX_WRAP;
1379 case PIPE_TEX_WRAP_CLAMP:
1380 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1381 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1382 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1383 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1384 return V_008F30_SQ_TEX_CLAMP_BORDER;
1385 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1386 return V_008F30_SQ_TEX_MIRROR;
1387 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1388 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1389 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1390 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1391 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1392 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1393 }
1394 }
1395
1396 static unsigned si_tex_filter(unsigned filter)
1397 {
1398 switch (filter) {
1399 default:
1400 case PIPE_TEX_FILTER_NEAREST:
1401 return V_008F38_SQ_TEX_XY_FILTER_POINT;
1402 case PIPE_TEX_FILTER_LINEAR:
1403 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
1404 }
1405 }
1406
1407 static unsigned si_tex_mipfilter(unsigned filter)
1408 {
1409 switch (filter) {
1410 case PIPE_TEX_MIPFILTER_NEAREST:
1411 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1412 case PIPE_TEX_MIPFILTER_LINEAR:
1413 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1414 default:
1415 case PIPE_TEX_MIPFILTER_NONE:
1416 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1417 }
1418 }
1419
1420 static unsigned si_tex_compare(unsigned compare)
1421 {
1422 switch (compare) {
1423 default:
1424 case PIPE_FUNC_NEVER:
1425 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1426 case PIPE_FUNC_LESS:
1427 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1428 case PIPE_FUNC_EQUAL:
1429 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1430 case PIPE_FUNC_LEQUAL:
1431 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1432 case PIPE_FUNC_GREATER:
1433 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1434 case PIPE_FUNC_NOTEQUAL:
1435 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1436 case PIPE_FUNC_GEQUAL:
1437 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1438 case PIPE_FUNC_ALWAYS:
1439 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1440 }
1441 }
1442
1443 static unsigned si_tex_dim(unsigned dim, unsigned nr_samples)
1444 {
1445 switch (dim) {
1446 default:
1447 case PIPE_TEXTURE_1D:
1448 return V_008F1C_SQ_RSRC_IMG_1D;
1449 case PIPE_TEXTURE_1D_ARRAY:
1450 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1451 case PIPE_TEXTURE_2D:
1452 case PIPE_TEXTURE_RECT:
1453 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1454 V_008F1C_SQ_RSRC_IMG_2D;
1455 case PIPE_TEXTURE_2D_ARRAY:
1456 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1457 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1458 case PIPE_TEXTURE_3D:
1459 return V_008F1C_SQ_RSRC_IMG_3D;
1460 case PIPE_TEXTURE_CUBE:
1461 case PIPE_TEXTURE_CUBE_ARRAY:
1462 return V_008F1C_SQ_RSRC_IMG_CUBE;
1463 }
1464 }
1465
1466 /*
1467 * Format support testing
1468 */
1469
1470 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1471 {
1472 return si_translate_texformat(screen, format, util_format_description(format),
1473 util_format_get_first_non_void_channel(format)) != ~0U;
1474 }
1475
1476 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1477 const struct util_format_description *desc,
1478 int first_non_void)
1479 {
1480 unsigned type = desc->channel[first_non_void].type;
1481 int i;
1482
1483 if (type == UTIL_FORMAT_TYPE_FIXED)
1484 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1485
1486 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1487 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1488
1489 if (desc->nr_channels == 4 &&
1490 desc->channel[0].size == 10 &&
1491 desc->channel[1].size == 10 &&
1492 desc->channel[2].size == 10 &&
1493 desc->channel[3].size == 2)
1494 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1495
1496 /* See whether the components are of the same size. */
1497 for (i = 0; i < desc->nr_channels; i++) {
1498 if (desc->channel[first_non_void].size != desc->channel[i].size)
1499 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1500 }
1501
1502 switch (desc->channel[first_non_void].size) {
1503 case 8:
1504 switch (desc->nr_channels) {
1505 case 1:
1506 return V_008F0C_BUF_DATA_FORMAT_8;
1507 case 2:
1508 return V_008F0C_BUF_DATA_FORMAT_8_8;
1509 case 3:
1510 case 4:
1511 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1512 }
1513 break;
1514 case 16:
1515 switch (desc->nr_channels) {
1516 case 1:
1517 return V_008F0C_BUF_DATA_FORMAT_16;
1518 case 2:
1519 return V_008F0C_BUF_DATA_FORMAT_16_16;
1520 case 3:
1521 case 4:
1522 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1523 }
1524 break;
1525 case 32:
1526 /* From the Southern Islands ISA documentation about MTBUF:
1527 * 'Memory reads of data in memory that is 32 or 64 bits do not
1528 * undergo any format conversion.'
1529 */
1530 if (type != UTIL_FORMAT_TYPE_FLOAT &&
1531 !desc->channel[first_non_void].pure_integer)
1532 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1533
1534 switch (desc->nr_channels) {
1535 case 1:
1536 return V_008F0C_BUF_DATA_FORMAT_32;
1537 case 2:
1538 return V_008F0C_BUF_DATA_FORMAT_32_32;
1539 case 3:
1540 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1541 case 4:
1542 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1543 }
1544 break;
1545 }
1546
1547 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1548 }
1549
1550 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1551 const struct util_format_description *desc,
1552 int first_non_void)
1553 {
1554 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1555 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1556
1557 switch (desc->channel[first_non_void].type) {
1558 case UTIL_FORMAT_TYPE_SIGNED:
1559 if (desc->channel[first_non_void].normalized)
1560 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1561 else if (desc->channel[first_non_void].pure_integer)
1562 return V_008F0C_BUF_NUM_FORMAT_SINT;
1563 else
1564 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1565 break;
1566 case UTIL_FORMAT_TYPE_UNSIGNED:
1567 if (desc->channel[first_non_void].normalized)
1568 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1569 else if (desc->channel[first_non_void].pure_integer)
1570 return V_008F0C_BUF_NUM_FORMAT_UINT;
1571 else
1572 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1573 break;
1574 case UTIL_FORMAT_TYPE_FLOAT:
1575 default:
1576 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1577 }
1578 }
1579
1580 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
1581 {
1582 const struct util_format_description *desc;
1583 int first_non_void;
1584 unsigned data_format;
1585
1586 desc = util_format_description(format);
1587 first_non_void = util_format_get_first_non_void_channel(format);
1588 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1589 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
1590 }
1591
1592 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1593 {
1594 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1595 r600_translate_colorswap(format) != ~0U;
1596 }
1597
1598 static bool si_is_zs_format_supported(enum pipe_format format)
1599 {
1600 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1601 }
1602
1603 boolean si_is_format_supported(struct pipe_screen *screen,
1604 enum pipe_format format,
1605 enum pipe_texture_target target,
1606 unsigned sample_count,
1607 unsigned usage)
1608 {
1609 struct si_screen *sscreen = (struct si_screen *)screen;
1610 unsigned retval = 0;
1611
1612 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1613 R600_ERR("r600: unsupported texture type %d\n", target);
1614 return FALSE;
1615 }
1616
1617 if (!util_format_is_supported(format, usage))
1618 return FALSE;
1619
1620 if (sample_count > 1) {
1621 /* 2D tiling on CIK is supported since DRM 2.35.0 */
1622 if (sscreen->b.chip_class >= CIK && sscreen->b.info.drm_minor < 35)
1623 return FALSE;
1624
1625 switch (sample_count) {
1626 case 2:
1627 case 4:
1628 case 8:
1629 break;
1630 default:
1631 return FALSE;
1632 }
1633 }
1634
1635 if (usage & PIPE_BIND_SAMPLER_VIEW) {
1636 if (target == PIPE_BUFFER) {
1637 if (si_is_vertex_format_supported(screen, format))
1638 retval |= PIPE_BIND_SAMPLER_VIEW;
1639 } else {
1640 if (si_is_sampler_format_supported(screen, format))
1641 retval |= PIPE_BIND_SAMPLER_VIEW;
1642 }
1643 }
1644
1645 if ((usage & (PIPE_BIND_RENDER_TARGET |
1646 PIPE_BIND_DISPLAY_TARGET |
1647 PIPE_BIND_SCANOUT |
1648 PIPE_BIND_SHARED |
1649 PIPE_BIND_BLENDABLE)) &&
1650 si_is_colorbuffer_format_supported(format)) {
1651 retval |= usage &
1652 (PIPE_BIND_RENDER_TARGET |
1653 PIPE_BIND_DISPLAY_TARGET |
1654 PIPE_BIND_SCANOUT |
1655 PIPE_BIND_SHARED);
1656 if (!util_format_is_pure_integer(format) &&
1657 !util_format_is_depth_or_stencil(format))
1658 retval |= usage & PIPE_BIND_BLENDABLE;
1659 }
1660
1661 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1662 si_is_zs_format_supported(format)) {
1663 retval |= PIPE_BIND_DEPTH_STENCIL;
1664 }
1665
1666 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
1667 si_is_vertex_format_supported(screen, format)) {
1668 retval |= PIPE_BIND_VERTEX_BUFFER;
1669 }
1670
1671 if (usage & PIPE_BIND_TRANSFER_READ)
1672 retval |= PIPE_BIND_TRANSFER_READ;
1673 if (usage & PIPE_BIND_TRANSFER_WRITE)
1674 retval |= PIPE_BIND_TRANSFER_WRITE;
1675
1676 return retval == usage;
1677 }
1678
1679 unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
1680 {
1681 unsigned tile_mode_index = 0;
1682
1683 if (stencil) {
1684 tile_mode_index = rtex->surface.stencil_tiling_index[level];
1685 } else {
1686 tile_mode_index = rtex->surface.tiling_index[level];
1687 }
1688 return tile_mode_index;
1689 }
1690
1691 /*
1692 * framebuffer handling
1693 */
1694
1695 static void si_initialize_color_surface(struct si_context *sctx,
1696 struct r600_surface *surf)
1697 {
1698 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1699 unsigned level = surf->base.u.tex.level;
1700 uint64_t offset = rtex->surface.level[level].offset;
1701 unsigned pitch, slice;
1702 unsigned color_info, color_attrib, color_pitch, color_view;
1703 unsigned tile_mode_index;
1704 unsigned format, swap, ntype, endian;
1705 const struct util_format_description *desc;
1706 int i;
1707 unsigned blend_clamp = 0, blend_bypass = 0;
1708 unsigned max_comp_size;
1709
1710 /* Layered rendering doesn't work with LINEAR_GENERAL.
1711 * (LINEAR_ALIGNED and others work) */
1712 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) {
1713 assert(surf->base.u.tex.first_layer == surf->base.u.tex.last_layer);
1714 offset += rtex->surface.level[level].slice_size *
1715 surf->base.u.tex.first_layer;
1716 color_view = 0;
1717 } else {
1718 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
1719 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
1720 }
1721
1722 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1723 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1724 if (slice) {
1725 slice = slice - 1;
1726 }
1727
1728 tile_mode_index = si_tile_mode_index(rtex, level, false);
1729
1730 desc = util_format_description(surf->base.format);
1731 for (i = 0; i < 4; i++) {
1732 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1733 break;
1734 }
1735 }
1736 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1737 ntype = V_028C70_NUMBER_FLOAT;
1738 } else {
1739 ntype = V_028C70_NUMBER_UNORM;
1740 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1741 ntype = V_028C70_NUMBER_SRGB;
1742 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1743 if (desc->channel[i].pure_integer) {
1744 ntype = V_028C70_NUMBER_SINT;
1745 } else {
1746 assert(desc->channel[i].normalized);
1747 ntype = V_028C70_NUMBER_SNORM;
1748 }
1749 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1750 if (desc->channel[i].pure_integer) {
1751 ntype = V_028C70_NUMBER_UINT;
1752 } else {
1753 assert(desc->channel[i].normalized);
1754 ntype = V_028C70_NUMBER_UNORM;
1755 }
1756 }
1757 }
1758
1759 format = si_translate_colorformat(surf->base.format);
1760 if (format == V_028C70_COLOR_INVALID) {
1761 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
1762 }
1763 assert(format != V_028C70_COLOR_INVALID);
1764 swap = r600_translate_colorswap(surf->base.format);
1765 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1766 endian = V_028C70_ENDIAN_NONE;
1767 } else {
1768 endian = si_colorformat_endian_swap(format);
1769 }
1770
1771 /* blend clamp should be set for all NORM/SRGB types */
1772 if (ntype == V_028C70_NUMBER_UNORM ||
1773 ntype == V_028C70_NUMBER_SNORM ||
1774 ntype == V_028C70_NUMBER_SRGB)
1775 blend_clamp = 1;
1776
1777 /* set blend bypass according to docs if SINT/UINT or
1778 8/24 COLOR variants */
1779 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1780 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1781 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1782 blend_clamp = 0;
1783 blend_bypass = 1;
1784 }
1785
1786 color_info = S_028C70_FORMAT(format) |
1787 S_028C70_COMP_SWAP(swap) |
1788 S_028C70_BLEND_CLAMP(blend_clamp) |
1789 S_028C70_BLEND_BYPASS(blend_bypass) |
1790 S_028C70_NUMBER_TYPE(ntype) |
1791 S_028C70_ENDIAN(endian);
1792
1793 color_pitch = S_028C64_TILE_MAX(pitch);
1794
1795 color_attrib = S_028C74_TILE_MODE_INDEX(tile_mode_index) |
1796 S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == UTIL_FORMAT_SWIZZLE_1);
1797
1798 if (rtex->resource.b.b.nr_samples > 1) {
1799 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1800
1801 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1802 S_028C74_NUM_FRAGMENTS(log_samples);
1803
1804 if (rtex->fmask.size) {
1805 color_info |= S_028C70_COMPRESSION(1);
1806 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
1807
1808 color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(rtex->fmask.tile_mode_index);
1809
1810 if (sctx->b.chip_class == SI) {
1811 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
1812 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1813 }
1814 if (sctx->b.chip_class >= CIK) {
1815 color_pitch |= S_028C64_FMASK_TILE_MAX(rtex->fmask.pitch / 8 - 1);
1816 }
1817 }
1818 }
1819
1820 offset += rtex->resource.gpu_address;
1821
1822 surf->cb_color_base = offset >> 8;
1823 surf->cb_color_pitch = color_pitch;
1824 surf->cb_color_slice = S_028C68_TILE_MAX(slice);
1825 surf->cb_color_view = color_view;
1826 surf->cb_color_info = color_info;
1827 surf->cb_color_attrib = color_attrib;
1828
1829 if (rtex->fmask.size) {
1830 surf->cb_color_fmask = (offset + rtex->fmask.offset) >> 8;
1831 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max);
1832 } else {
1833 /* This must be set for fast clear to work without FMASK. */
1834 surf->cb_color_fmask = surf->cb_color_base;
1835 surf->cb_color_fmask_slice = surf->cb_color_slice;
1836 surf->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
1837
1838 if (sctx->b.chip_class == SI) {
1839 unsigned bankh = util_logbase2(rtex->surface.bankh);
1840 surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
1841 }
1842
1843 if (sctx->b.chip_class >= CIK) {
1844 surf->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch);
1845 }
1846 }
1847
1848 /* Determine pixel shader export format */
1849 max_comp_size = si_colorformat_max_comp_size(format);
1850 if (ntype == V_028C70_NUMBER_SRGB ||
1851 ((ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM) &&
1852 max_comp_size <= 10) ||
1853 (ntype == V_028C70_NUMBER_FLOAT && max_comp_size <= 16)) {
1854 surf->export_16bpc = true;
1855 }
1856
1857 surf->color_initialized = true;
1858 }
1859
1860 static void si_init_depth_surface(struct si_context *sctx,
1861 struct r600_surface *surf)
1862 {
1863 struct si_screen *sscreen = sctx->screen;
1864 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1865 unsigned level = surf->base.u.tex.level;
1866 struct radeon_surf_level *levelinfo = &rtex->surface.level[level];
1867 unsigned format, tile_mode_index, array_mode;
1868 unsigned macro_aspect, tile_split, stile_split, bankh, bankw, nbanks, pipe_config;
1869 uint32_t z_info, s_info, db_depth_info;
1870 uint64_t z_offs, s_offs;
1871 uint32_t db_htile_data_base, db_htile_surface, pa_su_poly_offset_db_fmt_cntl = 0;
1872
1873 switch (sctx->framebuffer.state.zsbuf->texture->format) {
1874 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1875 case PIPE_FORMAT_X8Z24_UNORM:
1876 case PIPE_FORMAT_Z24X8_UNORM:
1877 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1878 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
1879 break;
1880 case PIPE_FORMAT_Z32_FLOAT:
1881 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1882 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
1883 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1884 break;
1885 case PIPE_FORMAT_Z16_UNORM:
1886 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
1887 break;
1888 default:
1889 assert(0);
1890 }
1891
1892 format = si_translate_dbformat(rtex->resource.b.b.format);
1893
1894 if (format == V_028040_Z_INVALID) {
1895 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
1896 }
1897 assert(format != V_028040_Z_INVALID);
1898
1899 s_offs = z_offs = rtex->resource.gpu_address;
1900 z_offs += rtex->surface.level[level].offset;
1901 s_offs += rtex->surface.stencil_level[level].offset;
1902
1903 db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
1904
1905 z_info = S_028040_FORMAT(format);
1906 if (rtex->resource.b.b.nr_samples > 1) {
1907 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
1908 }
1909
1910 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
1911 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
1912 else
1913 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
1914
1915 if (sctx->b.chip_class >= CIK) {
1916 switch (rtex->surface.level[level].mode) {
1917 case RADEON_SURF_MODE_2D:
1918 array_mode = V_02803C_ARRAY_2D_TILED_THIN1;
1919 break;
1920 case RADEON_SURF_MODE_1D:
1921 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1922 case RADEON_SURF_MODE_LINEAR:
1923 default:
1924 array_mode = V_02803C_ARRAY_1D_TILED_THIN1;
1925 break;
1926 }
1927 tile_split = rtex->surface.tile_split;
1928 stile_split = rtex->surface.stencil_tile_split;
1929 macro_aspect = rtex->surface.mtilea;
1930 bankw = rtex->surface.bankw;
1931 bankh = rtex->surface.bankh;
1932 tile_split = cik_tile_split(tile_split);
1933 stile_split = cik_tile_split(stile_split);
1934 macro_aspect = cik_macro_tile_aspect(macro_aspect);
1935 bankw = cik_bank_wh(bankw);
1936 bankh = cik_bank_wh(bankh);
1937 nbanks = si_num_banks(sscreen, rtex);
1938 tile_mode_index = si_tile_mode_index(rtex, level, false);
1939 pipe_config = cik_db_pipe_config(sscreen, tile_mode_index);
1940
1941 db_depth_info |= S_02803C_ARRAY_MODE(array_mode) |
1942 S_02803C_PIPE_CONFIG(pipe_config) |
1943 S_02803C_BANK_WIDTH(bankw) |
1944 S_02803C_BANK_HEIGHT(bankh) |
1945 S_02803C_MACRO_TILE_ASPECT(macro_aspect) |
1946 S_02803C_NUM_BANKS(nbanks);
1947 z_info |= S_028040_TILE_SPLIT(tile_split);
1948 s_info |= S_028044_TILE_SPLIT(stile_split);
1949 } else {
1950 tile_mode_index = si_tile_mode_index(rtex, level, false);
1951 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
1952 tile_mode_index = si_tile_mode_index(rtex, level, true);
1953 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
1954 }
1955
1956 /* HiZ aka depth buffer htile */
1957 /* use htile only for first level */
1958 if (rtex->htile_buffer && !level) {
1959 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
1960 S_028040_ALLOW_EXPCLEAR(1);
1961
1962 /* Use all of the htile_buffer for depth, because we don't
1963 * use HTILE for stencil because of FAST_STENCIL_DISABLE. */
1964 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
1965
1966 uint64_t va = rtex->htile_buffer->gpu_address;
1967 db_htile_data_base = va >> 8;
1968 db_htile_surface = S_028ABC_FULL_CACHE(1);
1969 } else {
1970 db_htile_data_base = 0;
1971 db_htile_surface = 0;
1972 }
1973
1974 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
1975
1976 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
1977 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
1978 surf->db_htile_data_base = db_htile_data_base;
1979 surf->db_depth_info = db_depth_info;
1980 surf->db_z_info = z_info;
1981 surf->db_stencil_info = s_info;
1982 surf->db_depth_base = z_offs >> 8;
1983 surf->db_stencil_base = s_offs >> 8;
1984 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
1985 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
1986 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
1987 levelinfo->nblk_y) / 64 - 1);
1988 surf->db_htile_surface = db_htile_surface;
1989 surf->pa_su_poly_offset_db_fmt_cntl = pa_su_poly_offset_db_fmt_cntl;
1990
1991 surf->depth_initialized = true;
1992 }
1993
1994 static void si_set_framebuffer_state(struct pipe_context *ctx,
1995 const struct pipe_framebuffer_state *state)
1996 {
1997 struct si_context *sctx = (struct si_context *)ctx;
1998 struct pipe_constant_buffer constbuf = {0};
1999 struct r600_surface *surf = NULL;
2000 struct r600_texture *rtex;
2001 bool old_cb0_is_integer = sctx->framebuffer.cb0_is_integer;
2002 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2003 int i;
2004
2005 /* Only flush TC when changing the framebuffer state, because
2006 * the only client not using TC that can change textures is
2007 * the framebuffer.
2008 *
2009 * Flush all CB and DB caches here because all buffers can be used
2010 * for write by both TC (with shader image stores) and CB/DB.
2011 */
2012 sctx->b.flags |= SI_CONTEXT_INV_TC_L1 |
2013 SI_CONTEXT_INV_TC_L2 |
2014 SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER;
2015
2016 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2017
2018 sctx->framebuffer.export_16bpc = 0;
2019 sctx->framebuffer.compressed_cb_mask = 0;
2020 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2021 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2022 sctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
2023 util_format_is_pure_integer(state->cbufs[0]->format);
2024
2025 if (sctx->framebuffer.cb0_is_integer != old_cb0_is_integer)
2026 sctx->db_render_state.dirty = true;
2027
2028 for (i = 0; i < state->nr_cbufs; i++) {
2029 if (!state->cbufs[i])
2030 continue;
2031
2032 surf = (struct r600_surface*)state->cbufs[i];
2033 rtex = (struct r600_texture*)surf->base.texture;
2034
2035 if (!surf->color_initialized) {
2036 si_initialize_color_surface(sctx, surf);
2037 }
2038
2039 if (surf->export_16bpc) {
2040 sctx->framebuffer.export_16bpc |= 1 << i;
2041 }
2042
2043 if (rtex->fmask.size && rtex->cmask.size) {
2044 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2045 }
2046 }
2047 /* Set the 16BPC export for possible dual-src blending. */
2048 if (i == 1 && surf && surf->export_16bpc) {
2049 sctx->framebuffer.export_16bpc |= 1 << 1;
2050 }
2051
2052 assert(!(sctx->framebuffer.export_16bpc & ~0xff));
2053
2054 if (state->zsbuf) {
2055 surf = (struct r600_surface*)state->zsbuf;
2056
2057 if (!surf->depth_initialized) {
2058 si_init_depth_surface(sctx, surf);
2059 }
2060 }
2061
2062 si_update_fb_rs_state(sctx);
2063 si_update_fb_blend_state(sctx);
2064
2065 sctx->framebuffer.atom.num_dw = state->nr_cbufs*15 + (8 - state->nr_cbufs)*3;
2066 sctx->framebuffer.atom.num_dw += state->zsbuf ? 26 : 4;
2067 sctx->framebuffer.atom.num_dw += 3; /* WINDOW_SCISSOR_BR */
2068 sctx->framebuffer.atom.num_dw += 18; /* MSAA sample locations */
2069 sctx->framebuffer.atom.dirty = true;
2070
2071 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2072 sctx->msaa_config.dirty = true;
2073 sctx->db_render_state.dirty = true;
2074
2075 /* Set sample locations as fragment shader constants. */
2076 switch (sctx->framebuffer.nr_samples) {
2077 case 1:
2078 constbuf.user_buffer = sctx->b.sample_locations_1x;
2079 break;
2080 case 2:
2081 constbuf.user_buffer = sctx->b.sample_locations_2x;
2082 break;
2083 case 4:
2084 constbuf.user_buffer = sctx->b.sample_locations_4x;
2085 break;
2086 case 8:
2087 constbuf.user_buffer = sctx->b.sample_locations_8x;
2088 break;
2089 case 16:
2090 constbuf.user_buffer = sctx->b.sample_locations_16x;
2091 break;
2092 default:
2093 assert(0);
2094 }
2095 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2096 ctx->set_constant_buffer(ctx, PIPE_SHADER_FRAGMENT,
2097 SI_DRIVER_STATE_CONST_BUF, &constbuf);
2098
2099 /* Smoothing (only possible with nr_samples == 1) uses the same
2100 * sample locations as the MSAA it simulates.
2101 *
2102 * Therefore, don't update the sample locations when
2103 * transitioning from no AA to smoothing-equivalent AA, and
2104 * vice versa.
2105 */
2106 if ((sctx->framebuffer.nr_samples != 1 ||
2107 old_nr_samples != SI_NUM_SMOOTH_AA_SAMPLES) &&
2108 (sctx->framebuffer.nr_samples != SI_NUM_SMOOTH_AA_SAMPLES ||
2109 old_nr_samples != 1))
2110 sctx->msaa_sample_locs.dirty = true;
2111 }
2112 }
2113
2114 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
2115 {
2116 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
2117 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2118 unsigned i, nr_cbufs = state->nr_cbufs;
2119 struct r600_texture *tex = NULL;
2120 struct r600_surface *cb = NULL;
2121
2122 /* Colorbuffers. */
2123 for (i = 0; i < nr_cbufs; i++) {
2124 cb = (struct r600_surface*)state->cbufs[i];
2125 if (!cb) {
2126 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2127 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2128 continue;
2129 }
2130
2131 tex = (struct r600_texture *)cb->base.texture;
2132 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
2133 &tex->resource, RADEON_USAGE_READWRITE,
2134 tex->surface.nsamples > 1 ?
2135 RADEON_PRIO_COLOR_BUFFER_MSAA :
2136 RADEON_PRIO_COLOR_BUFFER);
2137
2138 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2139 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
2140 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2141 RADEON_PRIO_COLOR_META);
2142 }
2143
2144 r600_write_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 13);
2145 radeon_emit(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
2146 radeon_emit(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
2147 radeon_emit(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
2148 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
2149 radeon_emit(cs, cb->cb_color_info | tex->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
2150 radeon_emit(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
2151 radeon_emit(cs, 0); /* R_028C78 unused */
2152 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
2153 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
2154 radeon_emit(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
2155 radeon_emit(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
2156 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
2157 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
2158 }
2159 /* set CB_COLOR1_INFO for possible dual-src blending */
2160 if (i == 1 && state->cbufs[0]) {
2161 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
2162 cb->cb_color_info | tex->cb_color_info);
2163 i++;
2164 }
2165 for (; i < 8 ; i++) {
2166 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
2167 }
2168
2169 /* ZS buffer. */
2170 if (state->zsbuf) {
2171 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
2172 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
2173
2174 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
2175 &rtex->resource, RADEON_USAGE_READWRITE,
2176 zb->base.texture->nr_samples > 1 ?
2177 RADEON_PRIO_DEPTH_BUFFER_MSAA :
2178 RADEON_PRIO_DEPTH_BUFFER);
2179
2180 if (zb->db_htile_data_base) {
2181 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
2182 rtex->htile_buffer, RADEON_USAGE_READWRITE,
2183 RADEON_PRIO_DEPTH_META);
2184 }
2185
2186 r600_write_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
2187 r600_write_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
2188
2189 r600_write_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
2190 radeon_emit(cs, zb->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
2191 radeon_emit(cs, zb->db_z_info | /* R_028040_DB_Z_INFO */
2192 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
2193 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
2194 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
2195 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
2196 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
2197 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
2198 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
2199 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
2200
2201 r600_write_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
2202 r600_write_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
2203 r600_write_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2204 zb->pa_su_poly_offset_db_fmt_cntl);
2205 } else {
2206 r600_write_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
2207 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
2208 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
2209 }
2210
2211 /* Framebuffer dimensions. */
2212 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2213 r600_write_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2214 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
2215 }
2216
2217 static void si_emit_msaa_sample_locs(struct r600_common_context *rctx,
2218 struct r600_atom *atom)
2219 {
2220 struct si_context *sctx = (struct si_context *)rctx;
2221 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
2222 unsigned nr_samples = sctx->framebuffer.nr_samples;
2223
2224 cayman_emit_msaa_sample_locs(cs, nr_samples > 1 ? nr_samples :
2225 SI_NUM_SMOOTH_AA_SAMPLES);
2226 }
2227
2228 const struct r600_atom si_atom_msaa_sample_locs = { si_emit_msaa_sample_locs, 18 }; /* number of CS dwords */
2229
2230 static void si_emit_msaa_config(struct r600_common_context *rctx, struct r600_atom *atom)
2231 {
2232 struct si_context *sctx = (struct si_context *)rctx;
2233 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
2234
2235 cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples,
2236 sctx->ps_iter_samples,
2237 sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0);
2238 }
2239
2240 const struct r600_atom si_atom_msaa_config = { si_emit_msaa_config, 10 }; /* number of CS dwords */
2241
2242 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
2243 {
2244 struct si_context *sctx = (struct si_context *)ctx;
2245
2246 if (sctx->ps_iter_samples == min_samples)
2247 return;
2248
2249 sctx->ps_iter_samples = min_samples;
2250
2251 if (sctx->framebuffer.nr_samples > 1)
2252 sctx->msaa_config.dirty = true;
2253 }
2254
2255 /*
2256 * Samplers
2257 */
2258
2259 static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx,
2260 struct pipe_resource *texture,
2261 const struct pipe_sampler_view *state)
2262 {
2263 struct si_context *sctx = (struct si_context*)ctx;
2264 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
2265 struct r600_texture *tmp = (struct r600_texture*)texture;
2266 const struct util_format_description *desc;
2267 unsigned format, num_format;
2268 uint32_t pitch = 0;
2269 unsigned char state_swizzle[4], swizzle[4];
2270 unsigned height, depth, width;
2271 enum pipe_format pipe_format = state->format;
2272 struct radeon_surf_level *surflevel;
2273 int first_non_void;
2274 uint64_t va;
2275
2276 if (view == NULL)
2277 return NULL;
2278
2279 /* initialize base object */
2280 view->base = *state;
2281 view->base.texture = NULL;
2282 view->base.reference.count = 1;
2283 view->base.context = ctx;
2284
2285 /* NULL resource, obey swizzle (only ZERO and ONE make sense). */
2286 if (!texture) {
2287 view->state[3] = S_008F1C_DST_SEL_X(si_map_swizzle(state->swizzle_r)) |
2288 S_008F1C_DST_SEL_Y(si_map_swizzle(state->swizzle_g)) |
2289 S_008F1C_DST_SEL_Z(si_map_swizzle(state->swizzle_b)) |
2290 S_008F1C_DST_SEL_W(si_map_swizzle(state->swizzle_a)) |
2291 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D);
2292 return &view->base;
2293 }
2294
2295 pipe_resource_reference(&view->base.texture, texture);
2296 view->resource = &tmp->resource;
2297
2298 /* Buffer resource. */
2299 if (texture->target == PIPE_BUFFER) {
2300 unsigned stride;
2301
2302 desc = util_format_description(state->format);
2303 first_non_void = util_format_get_first_non_void_channel(state->format);
2304 stride = desc->block.bits / 8;
2305 va = tmp->resource.gpu_address + state->u.buf.first_element*stride;
2306 format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
2307 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
2308
2309 view->state[4] = va;
2310 view->state[5] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
2311 S_008F04_STRIDE(stride);
2312 view->state[6] = state->u.buf.last_element + 1 - state->u.buf.first_element;
2313 view->state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2314 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2315 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2316 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2317 S_008F0C_NUM_FORMAT(num_format) |
2318 S_008F0C_DATA_FORMAT(format);
2319
2320 LIST_ADDTAIL(&view->list, &sctx->b.texture_buffers);
2321 return &view->base;
2322 }
2323
2324 state_swizzle[0] = state->swizzle_r;
2325 state_swizzle[1] = state->swizzle_g;
2326 state_swizzle[2] = state->swizzle_b;
2327 state_swizzle[3] = state->swizzle_a;
2328
2329 surflevel = tmp->surface.level;
2330
2331 /* Texturing with separate depth and stencil. */
2332 if (tmp->is_depth && !tmp->is_flushing_texture) {
2333 switch (pipe_format) {
2334 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2335 pipe_format = PIPE_FORMAT_Z32_FLOAT;
2336 break;
2337 case PIPE_FORMAT_X8Z24_UNORM:
2338 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2339 /* Z24 is always stored like this. */
2340 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
2341 break;
2342 case PIPE_FORMAT_X24S8_UINT:
2343 case PIPE_FORMAT_S8X24_UINT:
2344 case PIPE_FORMAT_X32_S8X24_UINT:
2345 pipe_format = PIPE_FORMAT_S8_UINT;
2346 surflevel = tmp->surface.stencil_level;
2347 break;
2348 default:;
2349 }
2350 }
2351
2352 desc = util_format_description(pipe_format);
2353
2354 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2355 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2356 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2357
2358 switch (pipe_format) {
2359 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2360 case PIPE_FORMAT_X24S8_UINT:
2361 case PIPE_FORMAT_X32_S8X24_UINT:
2362 case PIPE_FORMAT_X8Z24_UNORM:
2363 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
2364 break;
2365 default:
2366 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
2367 }
2368 } else {
2369 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2370 }
2371
2372 first_non_void = util_format_get_first_non_void_channel(pipe_format);
2373
2374 switch (pipe_format) {
2375 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2376 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2377 break;
2378 default:
2379 if (first_non_void < 0) {
2380 if (util_format_is_compressed(pipe_format)) {
2381 switch (pipe_format) {
2382 case PIPE_FORMAT_DXT1_SRGB:
2383 case PIPE_FORMAT_DXT1_SRGBA:
2384 case PIPE_FORMAT_DXT3_SRGBA:
2385 case PIPE_FORMAT_DXT5_SRGBA:
2386 case PIPE_FORMAT_BPTC_SRGBA:
2387 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2388 break;
2389 case PIPE_FORMAT_RGTC1_SNORM:
2390 case PIPE_FORMAT_LATC1_SNORM:
2391 case PIPE_FORMAT_RGTC2_SNORM:
2392 case PIPE_FORMAT_LATC2_SNORM:
2393 /* implies float, so use SNORM/UNORM to determine
2394 whether data is signed or not */
2395 case PIPE_FORMAT_BPTC_RGB_FLOAT:
2396 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2397 break;
2398 default:
2399 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2400 break;
2401 }
2402 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
2403 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2404 } else {
2405 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2406 }
2407 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
2408 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2409 } else {
2410 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2411
2412 switch (desc->channel[first_non_void].type) {
2413 case UTIL_FORMAT_TYPE_FLOAT:
2414 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2415 break;
2416 case UTIL_FORMAT_TYPE_SIGNED:
2417 if (desc->channel[first_non_void].normalized)
2418 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2419 else if (desc->channel[first_non_void].pure_integer)
2420 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
2421 else
2422 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
2423 break;
2424 case UTIL_FORMAT_TYPE_UNSIGNED:
2425 if (desc->channel[first_non_void].normalized)
2426 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2427 else if (desc->channel[first_non_void].pure_integer)
2428 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
2429 else
2430 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
2431 }
2432 }
2433 }
2434
2435 format = si_translate_texformat(ctx->screen, pipe_format, desc, first_non_void);
2436 if (format == ~0) {
2437 format = 0;
2438 }
2439
2440 /* not supported any more */
2441 //endian = si_colorformat_endian_swap(format);
2442
2443 width = surflevel[0].npix_x;
2444 height = surflevel[0].npix_y;
2445 depth = surflevel[0].npix_z;
2446 pitch = surflevel[0].nblk_x * util_format_get_blockwidth(pipe_format);
2447
2448 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
2449 height = 1;
2450 depth = texture->array_size;
2451 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
2452 depth = texture->array_size;
2453 } else if (texture->target == PIPE_TEXTURE_CUBE_ARRAY)
2454 depth = texture->array_size / 6;
2455
2456 va = tmp->resource.gpu_address + surflevel[0].offset;
2457 va += tmp->mipmap_shift * surflevel[texture->last_level].slice_size * tmp->surface.array_size;
2458
2459 view->state[0] = va >> 8;
2460 view->state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) |
2461 S_008F14_DATA_FORMAT(format) |
2462 S_008F14_NUM_FORMAT(num_format));
2463 view->state[2] = (S_008F18_WIDTH(width - 1) |
2464 S_008F18_HEIGHT(height - 1));
2465 view->state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2466 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2467 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2468 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2469 S_008F1C_BASE_LEVEL(texture->nr_samples > 1 ?
2470 0 : state->u.tex.first_level - tmp->mipmap_shift) |
2471 S_008F1C_LAST_LEVEL(texture->nr_samples > 1 ?
2472 util_logbase2(texture->nr_samples) :
2473 state->u.tex.last_level - tmp->mipmap_shift) |
2474 S_008F1C_TILING_INDEX(si_tile_mode_index(tmp, 0, false)) |
2475 S_008F1C_POW2_PAD(texture->last_level > 0) |
2476 S_008F1C_TYPE(si_tex_dim(texture->target, texture->nr_samples)));
2477 view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
2478 view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2479 S_008F24_LAST_ARRAY(state->u.tex.last_layer));
2480 view->state[6] = 0;
2481 view->state[7] = 0;
2482
2483 /* Initialize the sampler view for FMASK. */
2484 if (tmp->fmask.size) {
2485 uint64_t va = tmp->resource.gpu_address + tmp->fmask.offset;
2486 uint32_t fmask_format;
2487
2488 switch (texture->nr_samples) {
2489 case 2:
2490 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
2491 break;
2492 case 4:
2493 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
2494 break;
2495 case 8:
2496 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
2497 break;
2498 default:
2499 assert(0);
2500 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
2501 }
2502
2503 view->fmask_state[0] = va >> 8;
2504 view->fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
2505 S_008F14_DATA_FORMAT(fmask_format) |
2506 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT);
2507 view->fmask_state[2] = S_008F18_WIDTH(width - 1) |
2508 S_008F18_HEIGHT(height - 1);
2509 view->fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
2510 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
2511 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
2512 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
2513 S_008F1C_TILING_INDEX(tmp->fmask.tile_mode_index) |
2514 S_008F1C_TYPE(si_tex_dim(texture->target, 0));
2515 view->fmask_state[4] = S_008F20_DEPTH(depth - 1) |
2516 S_008F20_PITCH(tmp->fmask.pitch - 1);
2517 view->fmask_state[5] = S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2518 S_008F24_LAST_ARRAY(state->u.tex.last_layer);
2519 view->fmask_state[6] = 0;
2520 view->fmask_state[7] = 0;
2521 }
2522
2523 return &view->base;
2524 }
2525
2526 static void si_sampler_view_destroy(struct pipe_context *ctx,
2527 struct pipe_sampler_view *state)
2528 {
2529 struct si_sampler_view *view = (struct si_sampler_view *)state;
2530
2531 if (view->resource && view->resource->b.b.target == PIPE_BUFFER)
2532 LIST_DELINIT(&view->list);
2533
2534 pipe_resource_reference(&state->texture, NULL);
2535 FREE(view);
2536 }
2537
2538 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
2539 {
2540 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
2541 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
2542 (linear_filter &&
2543 (wrap == PIPE_TEX_WRAP_CLAMP ||
2544 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
2545 }
2546
2547 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
2548 {
2549 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
2550 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
2551
2552 return (state->border_color.ui[0] || state->border_color.ui[1] ||
2553 state->border_color.ui[2] || state->border_color.ui[3]) &&
2554 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
2555 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
2556 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
2557 }
2558
2559 static void *si_create_sampler_state(struct pipe_context *ctx,
2560 const struct pipe_sampler_state *state)
2561 {
2562 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
2563 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
2564 unsigned border_color_type;
2565
2566 if (rstate == NULL) {
2567 return NULL;
2568 }
2569
2570 if (sampler_state_needs_border_color(state))
2571 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
2572 else
2573 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
2574
2575 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
2576 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
2577 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
2578 r600_tex_aniso_filter(state->max_anisotropy) << 9 |
2579 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
2580 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
2581 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map));
2582 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
2583 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
2584 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
2585 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
2586 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter) | aniso_flag_offset) |
2587 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)));
2588 rstate->val[3] = S_008F3C_BORDER_COLOR_TYPE(border_color_type);
2589
2590 if (border_color_type == V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2591 memcpy(rstate->border_color, state->border_color.ui,
2592 sizeof(rstate->border_color));
2593 }
2594
2595 return rstate;
2596 }
2597
2598 /* Upload border colors and update the pointers in resource descriptors.
2599 * There can only be 4096 border colors per context.
2600 *
2601 * XXX: This is broken if the buffer gets reallocated.
2602 */
2603 static void si_set_border_colors(struct si_context *sctx, unsigned count,
2604 void **states)
2605 {
2606 struct si_sampler_state **rstates = (struct si_sampler_state **)states;
2607 uint32_t *border_color_table = NULL;
2608 int i, j;
2609
2610 for (i = 0; i < count; i++) {
2611 if (rstates[i] &&
2612 G_008F3C_BORDER_COLOR_TYPE(rstates[i]->val[3]) ==
2613 V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2614 if (!sctx->border_color_table ||
2615 ((sctx->border_color_offset + count - i) &
2616 C_008F3C_BORDER_COLOR_PTR)) {
2617 r600_resource_reference(&sctx->border_color_table, NULL);
2618 sctx->border_color_offset = 0;
2619
2620 sctx->border_color_table =
2621 si_resource_create_custom(&sctx->screen->b.b,
2622 PIPE_USAGE_DYNAMIC,
2623 4096 * 4 * 4);
2624 }
2625
2626 if (!border_color_table) {
2627 border_color_table =
2628 sctx->b.ws->buffer_map(sctx->border_color_table->cs_buf,
2629 sctx->b.rings.gfx.cs,
2630 PIPE_TRANSFER_WRITE |
2631 PIPE_TRANSFER_UNSYNCHRONIZED);
2632 }
2633
2634 for (j = 0; j < 4; j++) {
2635 border_color_table[4 * sctx->border_color_offset + j] =
2636 util_le32_to_cpu(rstates[i]->border_color[j]);
2637 }
2638
2639 rstates[i]->val[3] &= C_008F3C_BORDER_COLOR_PTR;
2640 rstates[i]->val[3] |= S_008F3C_BORDER_COLOR_PTR(sctx->border_color_offset++);
2641 }
2642 }
2643
2644 if (border_color_table) {
2645 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
2646
2647 uint64_t va_offset = sctx->border_color_table->gpu_address;
2648
2649 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, va_offset >> 8);
2650 if (sctx->b.chip_class >= CIK)
2651 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, va_offset >> 40);
2652 si_pm4_add_bo(pm4, sctx->border_color_table, RADEON_USAGE_READ,
2653 RADEON_PRIO_SHADER_DATA);
2654 si_pm4_set_state(sctx, ta_bordercolor_base, pm4);
2655 }
2656 }
2657
2658 static void si_bind_sampler_states(struct pipe_context *ctx, unsigned shader,
2659 unsigned start, unsigned count,
2660 void **states)
2661 {
2662 struct si_context *sctx = (struct si_context *)ctx;
2663
2664 if (!count || shader >= SI_NUM_SHADERS)
2665 return;
2666
2667 si_set_border_colors(sctx, count, states);
2668 si_set_sampler_descriptors(sctx, shader, start, count, states);
2669 }
2670
2671 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
2672 {
2673 struct si_context *sctx = (struct si_context *)ctx;
2674 struct si_state_sample_mask *state = CALLOC_STRUCT(si_state_sample_mask);
2675 struct si_pm4_state *pm4 = &state->pm4;
2676 uint16_t mask = sample_mask;
2677
2678 if (state == NULL)
2679 return;
2680
2681 state->sample_mask = mask;
2682 si_pm4_set_reg(pm4, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, mask | (mask << 16));
2683 si_pm4_set_reg(pm4, R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, mask | (mask << 16));
2684
2685 si_pm4_set_state(sctx, sample_mask, state);
2686 }
2687
2688 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
2689 {
2690 free(state);
2691 }
2692
2693 /*
2694 * Vertex elements & buffers
2695 */
2696
2697 static void *si_create_vertex_elements(struct pipe_context *ctx,
2698 unsigned count,
2699 const struct pipe_vertex_element *elements)
2700 {
2701 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
2702 int i;
2703
2704 assert(count < PIPE_MAX_ATTRIBS);
2705 if (!v)
2706 return NULL;
2707
2708 v->count = count;
2709 for (i = 0; i < count; ++i) {
2710 const struct util_format_description *desc;
2711 unsigned data_format, num_format;
2712 int first_non_void;
2713
2714 desc = util_format_description(elements[i].src_format);
2715 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
2716 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
2717 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
2718
2719 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2720 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2721 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2722 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2723 S_008F0C_NUM_FORMAT(num_format) |
2724 S_008F0C_DATA_FORMAT(data_format);
2725 v->format_size[i] = desc->block.bits / 8;
2726 }
2727 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
2728
2729 return v;
2730 }
2731
2732 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
2733 {
2734 struct si_context *sctx = (struct si_context *)ctx;
2735 struct si_vertex_element *v = (struct si_vertex_element*)state;
2736
2737 sctx->vertex_elements = v;
2738 sctx->vertex_buffers_dirty = true;
2739 }
2740
2741 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
2742 {
2743 struct si_context *sctx = (struct si_context *)ctx;
2744
2745 if (sctx->vertex_elements == state)
2746 sctx->vertex_elements = NULL;
2747 FREE(state);
2748 }
2749
2750 static void si_set_vertex_buffers(struct pipe_context *ctx,
2751 unsigned start_slot, unsigned count,
2752 const struct pipe_vertex_buffer *buffers)
2753 {
2754 struct si_context *sctx = (struct si_context *)ctx;
2755 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
2756 int i;
2757
2758 assert(start_slot + count <= Elements(sctx->vertex_buffer));
2759
2760 if (buffers) {
2761 for (i = 0; i < count; i++) {
2762 const struct pipe_vertex_buffer *src = buffers + i;
2763 struct pipe_vertex_buffer *dsti = dst + i;
2764
2765 pipe_resource_reference(&dsti->buffer, src->buffer);
2766 dsti->buffer_offset = src->buffer_offset;
2767 dsti->stride = src->stride;
2768 }
2769 } else {
2770 for (i = 0; i < count; i++) {
2771 pipe_resource_reference(&dst[i].buffer, NULL);
2772 }
2773 }
2774 sctx->vertex_buffers_dirty = true;
2775 }
2776
2777 static void si_set_index_buffer(struct pipe_context *ctx,
2778 const struct pipe_index_buffer *ib)
2779 {
2780 struct si_context *sctx = (struct si_context *)ctx;
2781
2782 if (ib) {
2783 pipe_resource_reference(&sctx->index_buffer.buffer, ib->buffer);
2784 memcpy(&sctx->index_buffer, ib, sizeof(*ib));
2785 } else {
2786 pipe_resource_reference(&sctx->index_buffer.buffer, NULL);
2787 }
2788 }
2789
2790 /*
2791 * Misc
2792 */
2793 static void si_set_polygon_stipple(struct pipe_context *ctx,
2794 const struct pipe_poly_stipple *state)
2795 {
2796 struct si_context *sctx = (struct si_context *)ctx;
2797 struct pipe_resource *tex;
2798 struct pipe_sampler_view *view;
2799 bool is_zero = true;
2800 bool is_one = true;
2801 int i;
2802
2803 /* The hardware obeys 0 and 1 swizzles in the descriptor even if
2804 * the resource is NULL/invalid. Take advantage of this fact and skip
2805 * texture allocation if the stipple pattern is constant.
2806 *
2807 * This is an optimization for the common case when stippling isn't
2808 * used but set_polygon_stipple is still called by st/mesa.
2809 */
2810 for (i = 0; i < Elements(state->stipple); i++) {
2811 is_zero = is_zero && state->stipple[i] == 0;
2812 is_one = is_one && state->stipple[i] == 0xffffffff;
2813 }
2814
2815 if (is_zero || is_one) {
2816 struct pipe_sampler_view templ = {{0}};
2817
2818 templ.swizzle_r = PIPE_SWIZZLE_ZERO;
2819 templ.swizzle_g = PIPE_SWIZZLE_ZERO;
2820 templ.swizzle_b = PIPE_SWIZZLE_ZERO;
2821 /* The pattern should be inverted in the texture. */
2822 templ.swizzle_a = is_zero ? PIPE_SWIZZLE_ONE : PIPE_SWIZZLE_ZERO;
2823
2824 view = ctx->create_sampler_view(ctx, NULL, &templ);
2825 } else {
2826 /* Create a new texture. */
2827 tex = util_pstipple_create_stipple_texture(ctx, state->stipple);
2828 if (!tex)
2829 return;
2830
2831 view = util_pstipple_create_sampler_view(ctx, tex);
2832 pipe_resource_reference(&tex, NULL);
2833 }
2834
2835 ctx->set_sampler_views(ctx, PIPE_SHADER_FRAGMENT,
2836 SI_POLY_STIPPLE_SAMPLER, 1, &view);
2837 pipe_sampler_view_reference(&view, NULL);
2838
2839 /* Bind the sampler state if needed. */
2840 if (!sctx->pstipple_sampler_state) {
2841 sctx->pstipple_sampler_state = util_pstipple_create_sampler(ctx);
2842 ctx->bind_sampler_states(ctx, PIPE_SHADER_FRAGMENT,
2843 SI_POLY_STIPPLE_SAMPLER, 1,
2844 &sctx->pstipple_sampler_state);
2845 }
2846 }
2847
2848 static void si_texture_barrier(struct pipe_context *ctx)
2849 {
2850 struct si_context *sctx = (struct si_context *)ctx;
2851
2852 sctx->b.flags |= SI_CONTEXT_INV_TC_L1 |
2853 SI_CONTEXT_INV_TC_L2 |
2854 SI_CONTEXT_FLUSH_AND_INV_CB;
2855 }
2856
2857 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
2858 {
2859 struct pipe_blend_state blend;
2860
2861 memset(&blend, 0, sizeof(blend));
2862 blend.independent_blend_enable = true;
2863 blend.rt[0].colormask = 0xf;
2864 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
2865 }
2866
2867 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
2868 bool include_draw_vbo)
2869 {
2870 si_need_cs_space((struct si_context*)ctx, num_dw, include_draw_vbo);
2871 }
2872
2873 void si_init_state_functions(struct si_context *sctx)
2874 {
2875 si_init_atom(&sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state, 0);
2876 si_init_atom(&sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state, 10);
2877 si_init_atom(&sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs, 6);
2878
2879 sctx->b.b.create_blend_state = si_create_blend_state;
2880 sctx->b.b.bind_blend_state = si_bind_blend_state;
2881 sctx->b.b.delete_blend_state = si_delete_blend_state;
2882 sctx->b.b.set_blend_color = si_set_blend_color;
2883
2884 sctx->b.b.create_rasterizer_state = si_create_rs_state;
2885 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
2886 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
2887
2888 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
2889 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
2890 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
2891
2892 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
2893 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
2894 sctx->custom_blend_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
2895 sctx->custom_blend_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
2896
2897 sctx->b.b.set_clip_state = si_set_clip_state;
2898 sctx->b.b.set_scissor_states = si_set_scissor_states;
2899 sctx->b.b.set_viewport_states = si_set_viewport_states;
2900 sctx->b.b.set_stencil_ref = si_set_pipe_stencil_ref;
2901
2902 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
2903 sctx->b.b.get_sample_position = cayman_get_sample_position;
2904
2905 sctx->b.b.create_sampler_state = si_create_sampler_state;
2906 sctx->b.b.bind_sampler_states = si_bind_sampler_states;
2907 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
2908
2909 sctx->b.b.create_sampler_view = si_create_sampler_view;
2910 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
2911
2912 sctx->b.b.set_sample_mask = si_set_sample_mask;
2913
2914 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
2915 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
2916 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
2917 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
2918 sctx->b.b.set_index_buffer = si_set_index_buffer;
2919
2920 sctx->b.b.texture_barrier = si_texture_barrier;
2921 sctx->b.b.set_polygon_stipple = si_set_polygon_stipple;
2922 sctx->b.b.set_min_samples = si_set_min_samples;
2923
2924 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
2925 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
2926
2927 sctx->b.b.draw_vbo = si_draw_vbo;
2928
2929 if (sctx->b.chip_class >= CIK) {
2930 sctx->b.dma_copy = cik_sdma_copy;
2931 } else {
2932 sctx->b.dma_copy = si_dma_copy;
2933 }
2934 }
2935
2936 static void
2937 si_write_harvested_raster_configs(struct si_context *sctx,
2938 struct si_pm4_state *pm4,
2939 unsigned raster_config)
2940 {
2941 unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1);
2942 unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1);
2943 unsigned rb_mask = sctx->screen->b.info.si_backend_enabled_mask;
2944 unsigned num_rb = sctx->screen->b.info.r600_num_backends;
2945 unsigned rb_per_pkr = num_rb / num_se / sh_per_se;
2946 unsigned rb_per_se = num_rb / num_se;
2947 unsigned se0_mask = (1 << rb_per_se) - 1;
2948 unsigned se1_mask = se0_mask << rb_per_se;
2949 unsigned se;
2950
2951 assert(num_se == 1 || num_se == 2);
2952 assert(sh_per_se == 1 || sh_per_se == 2);
2953 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
2954
2955 /* XXX: I can't figure out what the *_XSEL and *_YSEL
2956 * fields are for, so I'm leaving them as their default
2957 * values. */
2958
2959 se0_mask &= rb_mask;
2960 se1_mask &= rb_mask;
2961 if (num_se == 2 && (!se0_mask || !se1_mask)) {
2962 raster_config &= C_028350_SE_MAP;
2963
2964 if (!se0_mask) {
2965 raster_config |=
2966 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
2967 } else {
2968 raster_config |=
2969 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
2970 }
2971 }
2972
2973 for (se = 0; se < num_se; se++) {
2974 unsigned raster_config_se = raster_config;
2975 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
2976 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
2977
2978 pkr0_mask &= rb_mask;
2979 pkr1_mask &= rb_mask;
2980 if (sh_per_se == 2 && (!pkr0_mask || !pkr1_mask)) {
2981 raster_config_se &= C_028350_PKR_MAP;
2982
2983 if (!pkr0_mask) {
2984 raster_config_se |=
2985 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
2986 } else {
2987 raster_config_se |=
2988 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
2989 }
2990 }
2991
2992 if (rb_per_pkr == 2) {
2993 unsigned rb0_mask = 1 << (se * rb_per_se);
2994 unsigned rb1_mask = rb0_mask << 1;
2995
2996 rb0_mask &= rb_mask;
2997 rb1_mask &= rb_mask;
2998 if (!rb0_mask || !rb1_mask) {
2999 raster_config_se &= C_028350_RB_MAP_PKR0;
3000
3001 if (!rb0_mask) {
3002 raster_config_se |=
3003 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
3004 } else {
3005 raster_config_se |=
3006 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
3007 }
3008 }
3009
3010 if (sh_per_se == 2) {
3011 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
3012 rb1_mask = rb0_mask << 1;
3013 rb0_mask &= rb_mask;
3014 rb1_mask &= rb_mask;
3015 if (!rb0_mask || !rb1_mask) {
3016 raster_config_se &= C_028350_RB_MAP_PKR1;
3017
3018 if (!rb0_mask) {
3019 raster_config_se |=
3020 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
3021 } else {
3022 raster_config_se |=
3023 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
3024 }
3025 }
3026 }
3027 }
3028
3029 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3030 SE_INDEX(se) | SH_BROADCAST_WRITES |
3031 INSTANCE_BROADCAST_WRITES);
3032 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
3033 }
3034
3035 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3036 SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
3037 INSTANCE_BROADCAST_WRITES);
3038 }
3039
3040 void si_init_config(struct si_context *sctx)
3041 {
3042 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3043
3044 if (pm4 == NULL)
3045 return;
3046
3047 si_cmd_context_control(pm4);
3048
3049 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0);
3050 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0);
3051
3052 /* FIXME calculate these values somehow ??? */
3053 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, 0x80);
3054 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
3055 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
3056
3057 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0x0);
3058 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
3059 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0);
3060 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3061
3062 si_pm4_set_reg(pm4, R_028B60_VGT_GS_VERT_ITEMSIZE_1, 0);
3063 si_pm4_set_reg(pm4, R_028B64_VGT_GS_VERT_ITEMSIZE_2, 0);
3064 si_pm4_set_reg(pm4, R_028B68_VGT_GS_VERT_ITEMSIZE_3, 0);
3065 si_pm4_set_reg(pm4, R_028B90_VGT_GS_INSTANCE_CNT, 0);
3066
3067 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
3068 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0);
3069 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
3070 if (sctx->b.chip_class < CIK)
3071 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
3072 S_008A14_CLIP_VTX_REORDER_ENA(1));
3073
3074 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
3075 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
3076
3077 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
3078
3079 if (sctx->b.chip_class >= CIK) {
3080 switch (sctx->screen->b.family) {
3081 case CHIP_BONAIRE:
3082 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x16000012);
3083 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0);
3084 break;
3085 case CHIP_HAWAII:
3086 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x3a00161a);
3087 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x0000002e);
3088 break;
3089 case CHIP_KAVERI:
3090 /* XXX todo */
3091 case CHIP_KABINI:
3092 /* XXX todo */
3093 case CHIP_MULLINS:
3094 /* XXX todo */
3095 default:
3096 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0);
3097 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0);
3098 break;
3099 }
3100 } else {
3101 unsigned rb_mask = sctx->screen->b.info.si_backend_enabled_mask;
3102 unsigned num_rb = sctx->screen->b.info.r600_num_backends;
3103 unsigned raster_config;
3104
3105 switch (sctx->screen->b.family) {
3106 case CHIP_TAHITI:
3107 case CHIP_PITCAIRN:
3108 raster_config = 0x2a00126a;
3109 break;
3110 case CHIP_VERDE:
3111 raster_config = 0x0000124a;
3112 break;
3113 case CHIP_OLAND:
3114 raster_config = 0x00000082;
3115 break;
3116 case CHIP_HAINAN:
3117 raster_config = 0;
3118 break;
3119 default:
3120 fprintf(stderr,
3121 "radeonsi: Unknown GPU, using 0 for raster_config\n");
3122 raster_config = 0;
3123 break;
3124 }
3125
3126 /* Always use the default config when all backends are enabled
3127 * (or when we failed to determine the enabled backends).
3128 */
3129 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
3130 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
3131 raster_config);
3132 } else {
3133 si_write_harvested_raster_configs(sctx, pm4, raster_config);
3134 }
3135 }
3136
3137 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
3138 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
3139 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
3140 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
3141 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
3142 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
3143 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
3144
3145 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
3146 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
3147 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
3148 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
3149 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0, 0);
3150 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0, fui(1.0));
3151 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
3152 si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, fui(1.0));
3153 si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, fui(1.0));
3154 si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, fui(1.0));
3155 si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, fui(1.0));
3156 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, 0);
3157 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, 0);
3158 si_pm4_set_reg(pm4, R_028028_DB_STENCIL_CLEAR, 0);
3159 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
3160 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
3161 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
3162
3163 /* There is a hang if stencil is used and fast stencil is enabled
3164 * regardless of whether HTILE is depth-only or not.
3165 */
3166 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE,
3167 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3168 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE) |
3169 S_02800C_FAST_STENCIL_DISABLE(1));
3170
3171 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
3172 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
3173 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
3174
3175 if (sctx->b.chip_class >= CIK) {
3176 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
3177 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(0));
3178 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
3179 }
3180
3181 sctx->init_config = pm4;
3182 }