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radeonsi: allow using all CUs for tessellation and on-chip GS (v2)
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "si_shader.h"
29 #include "sid.h"
30 #include "radeon/r600_cs.h"
31
32 #include "util/u_dual_blend.h"
33 #include "util/u_format.h"
34 #include "util/u_format_s3tc.h"
35 #include "util/u_memory.h"
36 #include "util/u_pstipple.h"
37
38 /* Initialize an external atom (owned by ../radeon). */
39 static void
40 si_init_external_atom(struct si_context *sctx, struct r600_atom *atom,
41 struct r600_atom **list_elem)
42 {
43 atom->id = list_elem - sctx->atoms.array + 1;
44 *list_elem = atom;
45 }
46
47 /* Initialize an atom owned by radeonsi. */
48 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
49 struct r600_atom **list_elem,
50 void (*emit_func)(struct si_context *ctx, struct r600_atom *state))
51 {
52 atom->emit = (void*)emit_func;
53 atom->id = list_elem - sctx->atoms.array + 1; /* index+1 in the atom array */
54 *list_elem = atom;
55 }
56
57 unsigned si_array_mode(unsigned mode)
58 {
59 switch (mode) {
60 case RADEON_SURF_MODE_LINEAR_ALIGNED:
61 return V_009910_ARRAY_LINEAR_ALIGNED;
62 case RADEON_SURF_MODE_1D:
63 return V_009910_ARRAY_1D_TILED_THIN1;
64 case RADEON_SURF_MODE_2D:
65 return V_009910_ARRAY_2D_TILED_THIN1;
66 default:
67 case RADEON_SURF_MODE_LINEAR:
68 return V_009910_ARRAY_LINEAR_GENERAL;
69 }
70 }
71
72 uint32_t si_num_banks(struct si_screen *sscreen, struct r600_texture *tex)
73 {
74 if (sscreen->b.chip_class >= CIK &&
75 sscreen->b.info.cik_macrotile_mode_array_valid) {
76 unsigned index, tileb;
77
78 tileb = 8 * 8 * tex->surface.bpe;
79 tileb = MIN2(tex->surface.tile_split, tileb);
80
81 for (index = 0; tileb > 64; index++) {
82 tileb >>= 1;
83 }
84 assert(index < 16);
85
86 return (sscreen->b.info.cik_macrotile_mode_array[index] >> 6) & 0x3;
87 }
88
89 if (sscreen->b.chip_class == SI &&
90 sscreen->b.info.si_tile_mode_array_valid) {
91 /* Don't use stencil_tiling_index, because num_banks is always
92 * read from the depth mode. */
93 unsigned tile_mode_index = tex->surface.tiling_index[0];
94 assert(tile_mode_index < 32);
95
96 return G_009910_NUM_BANKS(sscreen->b.info.si_tile_mode_array[tile_mode_index]);
97 }
98
99 /* The old way. */
100 switch (sscreen->b.tiling_info.num_banks) {
101 case 2:
102 return V_02803C_ADDR_SURF_2_BANK;
103 case 4:
104 return V_02803C_ADDR_SURF_4_BANK;
105 case 8:
106 default:
107 return V_02803C_ADDR_SURF_8_BANK;
108 case 16:
109 return V_02803C_ADDR_SURF_16_BANK;
110 }
111 }
112
113 unsigned cik_tile_split(unsigned tile_split)
114 {
115 switch (tile_split) {
116 case 64:
117 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_64B;
118 break;
119 case 128:
120 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_128B;
121 break;
122 case 256:
123 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_256B;
124 break;
125 case 512:
126 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_512B;
127 break;
128 default:
129 case 1024:
130 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_1KB;
131 break;
132 case 2048:
133 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_2KB;
134 break;
135 case 4096:
136 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_4KB;
137 break;
138 }
139 return tile_split;
140 }
141
142 unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect)
143 {
144 switch (macro_tile_aspect) {
145 default:
146 case 1:
147 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_1;
148 break;
149 case 2:
150 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_2;
151 break;
152 case 4:
153 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_4;
154 break;
155 case 8:
156 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_8;
157 break;
158 }
159 return macro_tile_aspect;
160 }
161
162 unsigned cik_bank_wh(unsigned bankwh)
163 {
164 switch (bankwh) {
165 default:
166 case 1:
167 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_1;
168 break;
169 case 2:
170 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_2;
171 break;
172 case 4:
173 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_4;
174 break;
175 case 8:
176 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_8;
177 break;
178 }
179 return bankwh;
180 }
181
182 unsigned cik_db_pipe_config(struct si_screen *sscreen, unsigned tile_mode)
183 {
184 if (sscreen->b.info.si_tile_mode_array_valid) {
185 uint32_t gb_tile_mode = sscreen->b.info.si_tile_mode_array[tile_mode];
186
187 return G_009910_PIPE_CONFIG(gb_tile_mode);
188 }
189
190 /* This is probably broken for a lot of chips, but it's only used
191 * if the kernel cannot return the tile mode array for CIK. */
192 switch (sscreen->b.info.r600_num_tile_pipes) {
193 case 16:
194 return V_02803C_X_ADDR_SURF_P16_32X32_16X16;
195 case 8:
196 return V_02803C_X_ADDR_SURF_P8_32X32_16X16;
197 case 4:
198 default:
199 if (sscreen->b.info.r600_num_backends == 4)
200 return V_02803C_X_ADDR_SURF_P4_16X16;
201 else
202 return V_02803C_X_ADDR_SURF_P4_8X16;
203 case 2:
204 return V_02803C_ADDR_SURF_P2;
205 }
206 }
207
208 static unsigned si_map_swizzle(unsigned swizzle)
209 {
210 switch (swizzle) {
211 case UTIL_FORMAT_SWIZZLE_Y:
212 return V_008F0C_SQ_SEL_Y;
213 case UTIL_FORMAT_SWIZZLE_Z:
214 return V_008F0C_SQ_SEL_Z;
215 case UTIL_FORMAT_SWIZZLE_W:
216 return V_008F0C_SQ_SEL_W;
217 case UTIL_FORMAT_SWIZZLE_0:
218 return V_008F0C_SQ_SEL_0;
219 case UTIL_FORMAT_SWIZZLE_1:
220 return V_008F0C_SQ_SEL_1;
221 default: /* UTIL_FORMAT_SWIZZLE_X */
222 return V_008F0C_SQ_SEL_X;
223 }
224 }
225
226 static uint32_t S_FIXED(float value, uint32_t frac_bits)
227 {
228 return value * (1 << frac_bits);
229 }
230
231 /* 12.4 fixed-point */
232 static unsigned si_pack_float_12p4(float x)
233 {
234 return x <= 0 ? 0 :
235 x >= 4096 ? 0xffff : x * 16;
236 }
237
238 /*
239 * Inferred framebuffer and blender state.
240 *
241 * One of the reasons this must be derived from the framebuffer state is that:
242 * - The blend state mask is 0xf most of the time.
243 * - The COLOR1 format isn't INVALID because of possible dual-source blending,
244 * so COLOR1 is enabled pretty much all the time.
245 * So CB_TARGET_MASK is the only register that can disable COLOR1.
246 *
247 * Another reason is to avoid a hang with dual source blending.
248 */
249 static void si_emit_cb_target_mask(struct si_context *sctx, struct r600_atom *atom)
250 {
251 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
252 struct si_state_blend *blend = sctx->queued.named.blend;
253 uint32_t mask = 0, i;
254
255 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++)
256 if (sctx->framebuffer.state.cbufs[i])
257 mask |= 0xf << (4*i);
258
259 if (blend)
260 mask &= blend->cb_target_mask;
261
262 /* Avoid a hang that happens when dual source blending is enabled
263 * but there is not enough color outputs. This is undefined behavior,
264 * so disable color writes completely.
265 *
266 * Reproducible with Unigine Heaven 4.0 and drirc missing.
267 */
268 if (blend && blend->dual_src_blend &&
269 sctx->ps_shader.cso &&
270 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
271 mask = 0;
272
273 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, mask);
274 }
275
276 /*
277 * Blender functions
278 */
279
280 static uint32_t si_translate_blend_function(int blend_func)
281 {
282 switch (blend_func) {
283 case PIPE_BLEND_ADD:
284 return V_028780_COMB_DST_PLUS_SRC;
285 case PIPE_BLEND_SUBTRACT:
286 return V_028780_COMB_SRC_MINUS_DST;
287 case PIPE_BLEND_REVERSE_SUBTRACT:
288 return V_028780_COMB_DST_MINUS_SRC;
289 case PIPE_BLEND_MIN:
290 return V_028780_COMB_MIN_DST_SRC;
291 case PIPE_BLEND_MAX:
292 return V_028780_COMB_MAX_DST_SRC;
293 default:
294 R600_ERR("Unknown blend function %d\n", blend_func);
295 assert(0);
296 break;
297 }
298 return 0;
299 }
300
301 static uint32_t si_translate_blend_factor(int blend_fact)
302 {
303 switch (blend_fact) {
304 case PIPE_BLENDFACTOR_ONE:
305 return V_028780_BLEND_ONE;
306 case PIPE_BLENDFACTOR_SRC_COLOR:
307 return V_028780_BLEND_SRC_COLOR;
308 case PIPE_BLENDFACTOR_SRC_ALPHA:
309 return V_028780_BLEND_SRC_ALPHA;
310 case PIPE_BLENDFACTOR_DST_ALPHA:
311 return V_028780_BLEND_DST_ALPHA;
312 case PIPE_BLENDFACTOR_DST_COLOR:
313 return V_028780_BLEND_DST_COLOR;
314 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
315 return V_028780_BLEND_SRC_ALPHA_SATURATE;
316 case PIPE_BLENDFACTOR_CONST_COLOR:
317 return V_028780_BLEND_CONSTANT_COLOR;
318 case PIPE_BLENDFACTOR_CONST_ALPHA:
319 return V_028780_BLEND_CONSTANT_ALPHA;
320 case PIPE_BLENDFACTOR_ZERO:
321 return V_028780_BLEND_ZERO;
322 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
323 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
324 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
325 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
326 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
327 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
328 case PIPE_BLENDFACTOR_INV_DST_COLOR:
329 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
330 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
331 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
332 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
333 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
334 case PIPE_BLENDFACTOR_SRC1_COLOR:
335 return V_028780_BLEND_SRC1_COLOR;
336 case PIPE_BLENDFACTOR_SRC1_ALPHA:
337 return V_028780_BLEND_SRC1_ALPHA;
338 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
339 return V_028780_BLEND_INV_SRC1_COLOR;
340 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
341 return V_028780_BLEND_INV_SRC1_ALPHA;
342 default:
343 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
344 assert(0);
345 break;
346 }
347 return 0;
348 }
349
350 static uint32_t si_translate_blend_opt_function(int blend_func)
351 {
352 switch (blend_func) {
353 case PIPE_BLEND_ADD:
354 return V_028760_OPT_COMB_ADD;
355 case PIPE_BLEND_SUBTRACT:
356 return V_028760_OPT_COMB_SUBTRACT;
357 case PIPE_BLEND_REVERSE_SUBTRACT:
358 return V_028760_OPT_COMB_REVSUBTRACT;
359 case PIPE_BLEND_MIN:
360 return V_028760_OPT_COMB_MIN;
361 case PIPE_BLEND_MAX:
362 return V_028760_OPT_COMB_MAX;
363 default:
364 return V_028760_OPT_COMB_BLEND_DISABLED;
365 }
366 }
367
368 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
369 {
370 switch (blend_fact) {
371 case PIPE_BLENDFACTOR_ZERO:
372 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
373 case PIPE_BLENDFACTOR_ONE:
374 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
375 case PIPE_BLENDFACTOR_SRC_COLOR:
376 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
377 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
378 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
379 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
380 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
381 case PIPE_BLENDFACTOR_SRC_ALPHA:
382 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
383 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
384 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
385 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
386 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
387 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
388 default:
389 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
390 }
391 }
392
393 static void *si_create_blend_state_mode(struct pipe_context *ctx,
394 const struct pipe_blend_state *state,
395 unsigned mode)
396 {
397 struct si_context *sctx = (struct si_context*)ctx;
398 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
399 struct si_pm4_state *pm4 = &blend->pm4;
400
401 uint32_t color_control = 0;
402
403 if (!blend)
404 return NULL;
405
406 blend->alpha_to_coverage = state->alpha_to_coverage;
407 blend->alpha_to_one = state->alpha_to_one;
408 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
409
410 if (state->logicop_enable) {
411 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
412 } else {
413 color_control |= S_028808_ROP3(0xcc);
414 }
415
416 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
417 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
418 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
419 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
420 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
421 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
422
423 if (state->alpha_to_coverage)
424 blend->need_src_alpha_4bit |= 0xf;
425
426 blend->cb_target_mask = 0;
427 for (int i = 0; i < 8; i++) {
428 /* state->rt entries > 0 only written if independent blending */
429 const int j = state->independent_blend_enable ? i : 0;
430
431 unsigned eqRGB = state->rt[j].rgb_func;
432 unsigned srcRGB = state->rt[j].rgb_src_factor;
433 unsigned dstRGB = state->rt[j].rgb_dst_factor;
434 unsigned eqA = state->rt[j].alpha_func;
435 unsigned srcA = state->rt[j].alpha_src_factor;
436 unsigned dstA = state->rt[j].alpha_dst_factor;
437
438 unsigned blend_cntl = 0;
439
440 if (!state->rt[j].colormask)
441 continue;
442
443 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
444 blend->cb_target_mask |= state->rt[j].colormask << (4 * i);
445
446 if (!state->rt[j].blend_enable) {
447 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
448 continue;
449 }
450
451 blend_cntl |= S_028780_ENABLE(1);
452 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
453 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
454 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
455
456 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
457 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
458 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
459 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
460 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
461 }
462 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
463
464 blend->blend_enable_4bit |= 0xf << (i * 4);
465
466 /* This is only important for formats without alpha. */
467 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
468 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
469 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
470 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
471 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
472 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
473 blend->need_src_alpha_4bit |= 0xf << (i * 4);
474 }
475
476 if (blend->cb_target_mask) {
477 color_control |= S_028808_MODE(mode);
478 } else {
479 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
480 }
481
482 if (sctx->b.family == CHIP_STONEY) {
483 uint32_t sx_blend_opt_control = 0;
484
485 for (int i = 0; i < 8; i++) {
486 const int j = state->independent_blend_enable ? i : 0;
487
488 /* TODO: We can also set this if the surface doesn't contain RGB. */
489 if (!state->rt[j].blend_enable ||
490 !(state->rt[j].colormask & (PIPE_MASK_R | PIPE_MASK_G | PIPE_MASK_B)))
491 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (4 * i);
492
493 /* TODO: We can also set this if the surface doesn't contain alpha. */
494 if (!state->rt[j].blend_enable ||
495 !(state->rt[j].colormask & PIPE_MASK_A))
496 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (4 * i);
497
498 if (!state->rt[j].blend_enable) {
499 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
500 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
501 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED));
502 continue;
503 }
504
505 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
506 S_028760_COLOR_SRC_OPT(si_translate_blend_opt_factor(state->rt[j].rgb_src_factor, false)) |
507 S_028760_COLOR_DST_OPT(si_translate_blend_opt_factor(state->rt[j].rgb_dst_factor, false)) |
508 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(state->rt[j].rgb_func)) |
509 S_028760_ALPHA_SRC_OPT(si_translate_blend_opt_factor(state->rt[j].alpha_src_factor, true)) |
510 S_028760_ALPHA_DST_OPT(si_translate_blend_opt_factor(state->rt[j].alpha_dst_factor, true)) |
511 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(state->rt[j].alpha_func)));
512 }
513
514 si_pm4_set_reg(pm4, R_02875C_SX_BLEND_OPT_CONTROL, sx_blend_opt_control);
515
516 /* RB+ doesn't work with dual source blending */
517 if (blend->dual_src_blend)
518 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
519 }
520
521 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
522 return blend;
523 }
524
525 static void *si_create_blend_state(struct pipe_context *ctx,
526 const struct pipe_blend_state *state)
527 {
528 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
529 }
530
531 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
532 {
533 struct si_context *sctx = (struct si_context *)ctx;
534 si_pm4_bind_state(sctx, blend, (struct si_state_blend *)state);
535 si_mark_atom_dirty(sctx, &sctx->cb_target_mask);
536 }
537
538 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
539 {
540 struct si_context *sctx = (struct si_context *)ctx;
541 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
542 }
543
544 static void si_set_blend_color(struct pipe_context *ctx,
545 const struct pipe_blend_color *state)
546 {
547 struct si_context *sctx = (struct si_context *)ctx;
548
549 if (memcmp(&sctx->blend_color.state, state, sizeof(*state)) == 0)
550 return;
551
552 sctx->blend_color.state = *state;
553 si_mark_atom_dirty(sctx, &sctx->blend_color.atom);
554 }
555
556 static void si_emit_blend_color(struct si_context *sctx, struct r600_atom *atom)
557 {
558 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
559
560 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
561 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
562 }
563
564 /*
565 * Clipping, scissors and viewport
566 */
567
568 static void si_set_clip_state(struct pipe_context *ctx,
569 const struct pipe_clip_state *state)
570 {
571 struct si_context *sctx = (struct si_context *)ctx;
572 struct pipe_constant_buffer cb;
573
574 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
575 return;
576
577 sctx->clip_state.state = *state;
578 si_mark_atom_dirty(sctx, &sctx->clip_state.atom);
579
580 cb.buffer = NULL;
581 cb.user_buffer = state->ucp;
582 cb.buffer_offset = 0;
583 cb.buffer_size = 4*4*8;
584 ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, SI_DRIVER_STATE_CONST_BUF, &cb);
585 pipe_resource_reference(&cb.buffer, NULL);
586 }
587
588 static void si_emit_clip_state(struct si_context *sctx, struct r600_atom *atom)
589 {
590 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
591
592 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
593 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
594 }
595
596 #define SIX_BITS 0x3F
597
598 static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom)
599 {
600 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
601 struct tgsi_shader_info *info = si_get_vs_info(sctx);
602 unsigned window_space =
603 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
604 unsigned clipdist_mask =
605 info->writes_clipvertex ? SIX_BITS : info->clipdist_writemask;
606
607 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
608 S_02881C_USE_VTX_POINT_SIZE(info->writes_psize) |
609 S_02881C_USE_VTX_EDGE_FLAG(info->writes_edgeflag) |
610 S_02881C_USE_VTX_RENDER_TARGET_INDX(info->writes_layer) |
611 S_02881C_USE_VTX_VIEWPORT_INDX(info->writes_viewport_index) |
612 S_02881C_VS_OUT_CCDIST0_VEC_ENA((clipdist_mask & 0x0F) != 0) |
613 S_02881C_VS_OUT_CCDIST1_VEC_ENA((clipdist_mask & 0xF0) != 0) |
614 S_02881C_VS_OUT_MISC_VEC_ENA(info->writes_psize ||
615 info->writes_edgeflag ||
616 info->writes_layer ||
617 info->writes_viewport_index) |
618 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(1) |
619 (sctx->queued.named.rasterizer->clip_plane_enable &
620 clipdist_mask));
621 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
622 sctx->queued.named.rasterizer->pa_cl_clip_cntl |
623 (clipdist_mask ? 0 :
624 sctx->queued.named.rasterizer->clip_plane_enable & SIX_BITS) |
625 S_028810_CLIP_DISABLE(window_space));
626
627 /* reuse needs to be set off if we write oViewport */
628 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF,
629 S_028AB4_REUSE_OFF(info->writes_viewport_index));
630 }
631
632 static void si_set_scissor_states(struct pipe_context *ctx,
633 unsigned start_slot,
634 unsigned num_scissors,
635 const struct pipe_scissor_state *state)
636 {
637 struct si_context *sctx = (struct si_context *)ctx;
638 int i;
639
640 for (i = 0; i < num_scissors; i++)
641 sctx->scissors.states[start_slot + i] = state[i];
642
643 sctx->scissors.dirty_mask |= ((1 << num_scissors) - 1) << start_slot;
644 si_mark_atom_dirty(sctx, &sctx->scissors.atom);
645 }
646
647 static void si_emit_scissors(struct si_context *sctx, struct r600_atom *atom)
648 {
649 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
650 struct pipe_scissor_state *states = sctx->scissors.states;
651 unsigned mask = sctx->scissors.dirty_mask;
652
653 /* The simple case: Only 1 viewport is active. */
654 if (mask & 1 &&
655 !si_get_vs_info(sctx)->writes_viewport_index) {
656 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2);
657 radeon_emit(cs, S_028250_TL_X(states[0].minx) |
658 S_028250_TL_Y(states[0].miny) |
659 S_028250_WINDOW_OFFSET_DISABLE(1));
660 radeon_emit(cs, S_028254_BR_X(states[0].maxx) |
661 S_028254_BR_Y(states[0].maxy));
662 sctx->scissors.dirty_mask &= ~1; /* clear one bit */
663 return;
664 }
665
666 while (mask) {
667 int start, count, i;
668
669 u_bit_scan_consecutive_range(&mask, &start, &count);
670
671 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL +
672 start * 4 * 2, count * 2);
673 for (i = start; i < start+count; i++) {
674 radeon_emit(cs, S_028250_TL_X(states[i].minx) |
675 S_028250_TL_Y(states[i].miny) |
676 S_028250_WINDOW_OFFSET_DISABLE(1));
677 radeon_emit(cs, S_028254_BR_X(states[i].maxx) |
678 S_028254_BR_Y(states[i].maxy));
679 }
680 }
681 sctx->scissors.dirty_mask = 0;
682 }
683
684 static void si_set_viewport_states(struct pipe_context *ctx,
685 unsigned start_slot,
686 unsigned num_viewports,
687 const struct pipe_viewport_state *state)
688 {
689 struct si_context *sctx = (struct si_context *)ctx;
690 int i;
691
692 for (i = 0; i < num_viewports; i++)
693 sctx->viewports.states[start_slot + i] = state[i];
694
695 sctx->viewports.dirty_mask |= ((1 << num_viewports) - 1) << start_slot;
696 si_mark_atom_dirty(sctx, &sctx->viewports.atom);
697 }
698
699 static void si_emit_viewports(struct si_context *sctx, struct r600_atom *atom)
700 {
701 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
702 struct pipe_viewport_state *states = sctx->viewports.states;
703 unsigned mask = sctx->viewports.dirty_mask;
704
705 /* The simple case: Only 1 viewport is active. */
706 if (mask & 1 &&
707 !si_get_vs_info(sctx)->writes_viewport_index) {
708 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE, 6);
709 radeon_emit(cs, fui(states[0].scale[0]));
710 radeon_emit(cs, fui(states[0].translate[0]));
711 radeon_emit(cs, fui(states[0].scale[1]));
712 radeon_emit(cs, fui(states[0].translate[1]));
713 radeon_emit(cs, fui(states[0].scale[2]));
714 radeon_emit(cs, fui(states[0].translate[2]));
715 sctx->viewports.dirty_mask &= ~1; /* clear one bit */
716 return;
717 }
718
719 while (mask) {
720 int start, count, i;
721
722 u_bit_scan_consecutive_range(&mask, &start, &count);
723
724 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE +
725 start * 4 * 6, count * 6);
726 for (i = start; i < start+count; i++) {
727 radeon_emit(cs, fui(states[i].scale[0]));
728 radeon_emit(cs, fui(states[i].translate[0]));
729 radeon_emit(cs, fui(states[i].scale[1]));
730 radeon_emit(cs, fui(states[i].translate[1]));
731 radeon_emit(cs, fui(states[i].scale[2]));
732 radeon_emit(cs, fui(states[i].translate[2]));
733 }
734 }
735 sctx->viewports.dirty_mask = 0;
736 }
737
738 /*
739 * inferred state between framebuffer and rasterizer
740 */
741 static void si_update_poly_offset_state(struct si_context *sctx)
742 {
743 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
744
745 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf)
746 return;
747
748 switch (sctx->framebuffer.state.zsbuf->texture->format) {
749 case PIPE_FORMAT_Z16_UNORM:
750 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
751 break;
752 default: /* 24-bit */
753 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
754 break;
755 case PIPE_FORMAT_Z32_FLOAT:
756 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
757 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
758 break;
759 }
760 }
761
762 /*
763 * Rasterizer
764 */
765
766 static uint32_t si_translate_fill(uint32_t func)
767 {
768 switch(func) {
769 case PIPE_POLYGON_MODE_FILL:
770 return V_028814_X_DRAW_TRIANGLES;
771 case PIPE_POLYGON_MODE_LINE:
772 return V_028814_X_DRAW_LINES;
773 case PIPE_POLYGON_MODE_POINT:
774 return V_028814_X_DRAW_POINTS;
775 default:
776 assert(0);
777 return V_028814_X_DRAW_POINTS;
778 }
779 }
780
781 static void *si_create_rs_state(struct pipe_context *ctx,
782 const struct pipe_rasterizer_state *state)
783 {
784 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
785 struct si_pm4_state *pm4 = &rs->pm4;
786 unsigned tmp, i;
787 float psize_min, psize_max;
788
789 if (!rs) {
790 return NULL;
791 }
792
793 rs->two_side = state->light_twoside;
794 rs->multisample_enable = state->multisample;
795 rs->force_persample_interp = state->force_persample_interp;
796 rs->clip_plane_enable = state->clip_plane_enable;
797 rs->line_stipple_enable = state->line_stipple_enable;
798 rs->poly_stipple_enable = state->poly_stipple_enable;
799 rs->line_smooth = state->line_smooth;
800 rs->poly_smooth = state->poly_smooth;
801 rs->uses_poly_offset = state->offset_point || state->offset_line ||
802 state->offset_tri;
803 rs->clamp_fragment_color = state->clamp_fragment_color;
804 rs->flatshade = state->flatshade;
805 rs->sprite_coord_enable = state->sprite_coord_enable;
806 rs->rasterizer_discard = state->rasterizer_discard;
807 rs->pa_sc_line_stipple = state->line_stipple_enable ?
808 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
809 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
810 rs->pa_cl_clip_cntl =
811 S_028810_PS_UCP_MODE(3) |
812 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
813 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
814 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
815 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
816 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
817
818 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
819 S_0286D4_FLAT_SHADE_ENA(1) |
820 S_0286D4_PNT_SPRITE_ENA(1) |
821 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
822 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
823 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
824 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
825 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
826
827 /* point size 12.4 fixed point */
828 tmp = (unsigned)(state->point_size * 8.0);
829 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
830
831 if (state->point_size_per_vertex) {
832 psize_min = util_get_min_point_size(state);
833 psize_max = 8192;
834 } else {
835 /* Force the point size to be as if the vertex output was disabled. */
836 psize_min = state->point_size;
837 psize_max = state->point_size;
838 }
839 /* Divide by two, because 0.5 = 1 pixel. */
840 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
841 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
842 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
843
844 tmp = (unsigned)state->line_width * 8;
845 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
846 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
847 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
848 S_028A48_MSAA_ENABLE(state->multisample ||
849 state->poly_smooth ||
850 state->line_smooth) |
851 S_028A48_VPORT_SCISSOR_ENABLE(state->scissor));
852
853 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
854 S_028BE4_PIX_CENTER(state->half_pixel_center) |
855 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
856
857 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
858 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
859 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
860 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
861 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
862 S_028814_FACE(!state->front_ccw) |
863 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
864 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
865 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
866 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
867 state->fill_back != PIPE_POLYGON_MODE_FILL) |
868 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
869 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
870 si_pm4_set_reg(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0 +
871 SI_SGPR_VS_STATE_BITS * 4, state->clamp_vertex_color);
872
873 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
874 for (i = 0; i < 3; i++) {
875 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
876 float offset_units = state->offset_units;
877 float offset_scale = state->offset_scale * 16.0f;
878
879 switch (i) {
880 case 0: /* 16-bit zbuffer */
881 offset_units *= 4.0f;
882 break;
883 case 1: /* 24-bit zbuffer */
884 offset_units *= 2.0f;
885 break;
886 case 2: /* 32-bit zbuffer */
887 offset_units *= 1.0f;
888 break;
889 }
890
891 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
892 fui(offset_scale));
893 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
894 fui(offset_units));
895 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
896 fui(offset_scale));
897 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
898 fui(offset_units));
899 }
900
901 return rs;
902 }
903
904 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
905 {
906 struct si_context *sctx = (struct si_context *)ctx;
907 struct si_state_rasterizer *old_rs =
908 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
909 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
910
911 if (!state)
912 return;
913
914 if (sctx->framebuffer.nr_samples > 1 &&
915 (!old_rs || old_rs->multisample_enable != rs->multisample_enable))
916 si_mark_atom_dirty(sctx, &sctx->db_render_state);
917
918 si_pm4_bind_state(sctx, rasterizer, rs);
919 si_update_poly_offset_state(sctx);
920
921 si_mark_atom_dirty(sctx, &sctx->clip_regs);
922 }
923
924 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
925 {
926 struct si_context *sctx = (struct si_context *)ctx;
927
928 if (sctx->queued.named.rasterizer == state)
929 si_pm4_bind_state(sctx, poly_offset, NULL);
930 si_pm4_delete_state(sctx, rasterizer, (struct si_state_rasterizer *)state);
931 }
932
933 /*
934 * infeered state between dsa and stencil ref
935 */
936 static void si_emit_stencil_ref(struct si_context *sctx, struct r600_atom *atom)
937 {
938 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
939 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
940 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
941
942 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
943 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
944 S_028430_STENCILMASK(dsa->valuemask[0]) |
945 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
946 S_028430_STENCILOPVAL(1));
947 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
948 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
949 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
950 S_028434_STENCILOPVAL_BF(1));
951 }
952
953 static void si_set_stencil_ref(struct pipe_context *ctx,
954 const struct pipe_stencil_ref *state)
955 {
956 struct si_context *sctx = (struct si_context *)ctx;
957
958 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
959 return;
960
961 sctx->stencil_ref.state = *state;
962 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
963 }
964
965
966 /*
967 * DSA
968 */
969
970 static uint32_t si_translate_stencil_op(int s_op)
971 {
972 switch (s_op) {
973 case PIPE_STENCIL_OP_KEEP:
974 return V_02842C_STENCIL_KEEP;
975 case PIPE_STENCIL_OP_ZERO:
976 return V_02842C_STENCIL_ZERO;
977 case PIPE_STENCIL_OP_REPLACE:
978 return V_02842C_STENCIL_REPLACE_TEST;
979 case PIPE_STENCIL_OP_INCR:
980 return V_02842C_STENCIL_ADD_CLAMP;
981 case PIPE_STENCIL_OP_DECR:
982 return V_02842C_STENCIL_SUB_CLAMP;
983 case PIPE_STENCIL_OP_INCR_WRAP:
984 return V_02842C_STENCIL_ADD_WRAP;
985 case PIPE_STENCIL_OP_DECR_WRAP:
986 return V_02842C_STENCIL_SUB_WRAP;
987 case PIPE_STENCIL_OP_INVERT:
988 return V_02842C_STENCIL_INVERT;
989 default:
990 R600_ERR("Unknown stencil op %d", s_op);
991 assert(0);
992 break;
993 }
994 return 0;
995 }
996
997 static void *si_create_dsa_state(struct pipe_context *ctx,
998 const struct pipe_depth_stencil_alpha_state *state)
999 {
1000 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
1001 struct si_pm4_state *pm4 = &dsa->pm4;
1002 unsigned db_depth_control;
1003 uint32_t db_stencil_control = 0;
1004
1005 if (!dsa) {
1006 return NULL;
1007 }
1008
1009 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
1010 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
1011 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
1012 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
1013
1014 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
1015 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
1016 S_028800_ZFUNC(state->depth.func) |
1017 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
1018
1019 /* stencil */
1020 if (state->stencil[0].enabled) {
1021 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1022 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
1023 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
1024 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
1025 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
1026
1027 if (state->stencil[1].enabled) {
1028 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1029 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1030 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
1031 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
1032 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
1033 }
1034 }
1035
1036 /* alpha */
1037 if (state->alpha.enabled) {
1038 dsa->alpha_func = state->alpha.func;
1039
1040 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1041 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
1042 } else {
1043 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1044 }
1045
1046 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1047 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1048 if (state->depth.bounds_test) {
1049 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1050 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1051 }
1052
1053 return dsa;
1054 }
1055
1056 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1057 {
1058 struct si_context *sctx = (struct si_context *)ctx;
1059 struct si_state_dsa *dsa = state;
1060
1061 if (!state)
1062 return;
1063
1064 si_pm4_bind_state(sctx, dsa, dsa);
1065
1066 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1067 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1068 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1069 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1070 }
1071 }
1072
1073 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1074 {
1075 struct si_context *sctx = (struct si_context *)ctx;
1076 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1077 }
1078
1079 static void *si_create_db_flush_dsa(struct si_context *sctx)
1080 {
1081 struct pipe_depth_stencil_alpha_state dsa = {};
1082
1083 return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
1084 }
1085
1086 /* DB RENDER STATE */
1087
1088 static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
1089 {
1090 struct si_context *sctx = (struct si_context*)ctx;
1091
1092 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1093 }
1094
1095 static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
1096 {
1097 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1098 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1099 unsigned db_shader_control;
1100
1101 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1102
1103 /* DB_RENDER_CONTROL */
1104 if (sctx->dbcb_depth_copy_enabled ||
1105 sctx->dbcb_stencil_copy_enabled) {
1106 radeon_emit(cs,
1107 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1108 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1109 S_028000_COPY_CENTROID(1) |
1110 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
1111 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1112 radeon_emit(cs,
1113 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1114 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace));
1115 } else {
1116 radeon_emit(cs,
1117 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1118 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear));
1119 }
1120
1121 /* DB_COUNT_CONTROL (occlusion queries) */
1122 if (sctx->b.num_occlusion_queries > 0) {
1123 if (sctx->b.chip_class >= CIK) {
1124 radeon_emit(cs,
1125 S_028004_PERFECT_ZPASS_COUNTS(1) |
1126 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
1127 S_028004_ZPASS_ENABLE(1) |
1128 S_028004_SLICE_EVEN_ENABLE(1) |
1129 S_028004_SLICE_ODD_ENABLE(1));
1130 } else {
1131 radeon_emit(cs,
1132 S_028004_PERFECT_ZPASS_COUNTS(1) |
1133 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
1134 }
1135 } else {
1136 /* Disable occlusion queries. */
1137 if (sctx->b.chip_class >= CIK) {
1138 radeon_emit(cs, 0);
1139 } else {
1140 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
1141 }
1142 }
1143
1144 /* DB_RENDER_OVERRIDE2 */
1145 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
1146 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1147 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear));
1148
1149 db_shader_control = S_02880C_ALPHA_TO_MASK_DISABLE(sctx->framebuffer.cb0_is_integer) |
1150 sctx->ps_db_shader_control;
1151
1152 /* Bug workaround for smoothing (overrasterization) on SI. */
1153 if (sctx->b.chip_class == SI && sctx->smoothing_enabled)
1154 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1155 else
1156 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
1157
1158 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1159 if (sctx->framebuffer.nr_samples <= 1 || (rs && !rs->multisample_enable))
1160 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1161
1162 if (sctx->b.family == CHIP_STONEY &&
1163 sctx->screen->b.debug_flags & DBG_NO_RB_PLUS)
1164 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1165
1166 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
1167 db_shader_control);
1168 }
1169
1170 /*
1171 * format translation
1172 */
1173 static uint32_t si_translate_colorformat(enum pipe_format format)
1174 {
1175 const struct util_format_description *desc = util_format_description(format);
1176
1177 #define HAS_SIZE(x,y,z,w) \
1178 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1179 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1180
1181 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1182 return V_028C70_COLOR_10_11_11;
1183
1184 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1185 return V_028C70_COLOR_INVALID;
1186
1187 switch (desc->nr_channels) {
1188 case 1:
1189 switch (desc->channel[0].size) {
1190 case 8:
1191 return V_028C70_COLOR_8;
1192 case 16:
1193 return V_028C70_COLOR_16;
1194 case 32:
1195 return V_028C70_COLOR_32;
1196 }
1197 break;
1198 case 2:
1199 if (desc->channel[0].size == desc->channel[1].size) {
1200 switch (desc->channel[0].size) {
1201 case 8:
1202 return V_028C70_COLOR_8_8;
1203 case 16:
1204 return V_028C70_COLOR_16_16;
1205 case 32:
1206 return V_028C70_COLOR_32_32;
1207 }
1208 } else if (HAS_SIZE(8,24,0,0)) {
1209 return V_028C70_COLOR_24_8;
1210 } else if (HAS_SIZE(24,8,0,0)) {
1211 return V_028C70_COLOR_8_24;
1212 }
1213 break;
1214 case 3:
1215 if (HAS_SIZE(5,6,5,0)) {
1216 return V_028C70_COLOR_5_6_5;
1217 } else if (HAS_SIZE(32,8,24,0)) {
1218 return V_028C70_COLOR_X24_8_32_FLOAT;
1219 }
1220 break;
1221 case 4:
1222 if (desc->channel[0].size == desc->channel[1].size &&
1223 desc->channel[0].size == desc->channel[2].size &&
1224 desc->channel[0].size == desc->channel[3].size) {
1225 switch (desc->channel[0].size) {
1226 case 4:
1227 return V_028C70_COLOR_4_4_4_4;
1228 case 8:
1229 return V_028C70_COLOR_8_8_8_8;
1230 case 16:
1231 return V_028C70_COLOR_16_16_16_16;
1232 case 32:
1233 return V_028C70_COLOR_32_32_32_32;
1234 }
1235 } else if (HAS_SIZE(5,5,5,1)) {
1236 return V_028C70_COLOR_1_5_5_5;
1237 } else if (HAS_SIZE(10,10,10,2)) {
1238 return V_028C70_COLOR_2_10_10_10;
1239 }
1240 break;
1241 }
1242 return V_028C70_COLOR_INVALID;
1243 }
1244
1245 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1246 {
1247 if (SI_BIG_ENDIAN) {
1248 switch(colorformat) {
1249 /* 8-bit buffers. */
1250 case V_028C70_COLOR_8:
1251 return V_028C70_ENDIAN_NONE;
1252
1253 /* 16-bit buffers. */
1254 case V_028C70_COLOR_5_6_5:
1255 case V_028C70_COLOR_1_5_5_5:
1256 case V_028C70_COLOR_4_4_4_4:
1257 case V_028C70_COLOR_16:
1258 case V_028C70_COLOR_8_8:
1259 return V_028C70_ENDIAN_8IN16;
1260
1261 /* 32-bit buffers. */
1262 case V_028C70_COLOR_8_8_8_8:
1263 case V_028C70_COLOR_2_10_10_10:
1264 case V_028C70_COLOR_8_24:
1265 case V_028C70_COLOR_24_8:
1266 case V_028C70_COLOR_16_16:
1267 return V_028C70_ENDIAN_8IN32;
1268
1269 /* 64-bit buffers. */
1270 case V_028C70_COLOR_16_16_16_16:
1271 return V_028C70_ENDIAN_8IN16;
1272
1273 case V_028C70_COLOR_32_32:
1274 return V_028C70_ENDIAN_8IN32;
1275
1276 /* 128-bit buffers. */
1277 case V_028C70_COLOR_32_32_32_32:
1278 return V_028C70_ENDIAN_8IN32;
1279 default:
1280 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1281 }
1282 } else {
1283 return V_028C70_ENDIAN_NONE;
1284 }
1285 }
1286
1287 static uint32_t si_translate_dbformat(enum pipe_format format)
1288 {
1289 switch (format) {
1290 case PIPE_FORMAT_Z16_UNORM:
1291 return V_028040_Z_16;
1292 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1293 case PIPE_FORMAT_X8Z24_UNORM:
1294 case PIPE_FORMAT_Z24X8_UNORM:
1295 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1296 return V_028040_Z_24; /* deprecated on SI */
1297 case PIPE_FORMAT_Z32_FLOAT:
1298 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1299 return V_028040_Z_32_FLOAT;
1300 default:
1301 return V_028040_Z_INVALID;
1302 }
1303 }
1304
1305 /*
1306 * Texture translation
1307 */
1308
1309 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1310 enum pipe_format format,
1311 const struct util_format_description *desc,
1312 int first_non_void)
1313 {
1314 struct si_screen *sscreen = (struct si_screen*)screen;
1315 bool enable_compressed_formats = (sscreen->b.info.drm_major == 2 &&
1316 sscreen->b.info.drm_minor >= 31) ||
1317 sscreen->b.info.drm_major == 3;
1318 boolean uniform = TRUE;
1319 int i;
1320
1321 /* Colorspace (return non-RGB formats directly). */
1322 switch (desc->colorspace) {
1323 /* Depth stencil formats */
1324 case UTIL_FORMAT_COLORSPACE_ZS:
1325 switch (format) {
1326 case PIPE_FORMAT_Z16_UNORM:
1327 return V_008F14_IMG_DATA_FORMAT_16;
1328 case PIPE_FORMAT_X24S8_UINT:
1329 case PIPE_FORMAT_Z24X8_UNORM:
1330 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1331 return V_008F14_IMG_DATA_FORMAT_8_24;
1332 case PIPE_FORMAT_X8Z24_UNORM:
1333 case PIPE_FORMAT_S8X24_UINT:
1334 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1335 return V_008F14_IMG_DATA_FORMAT_24_8;
1336 case PIPE_FORMAT_S8_UINT:
1337 return V_008F14_IMG_DATA_FORMAT_8;
1338 case PIPE_FORMAT_Z32_FLOAT:
1339 return V_008F14_IMG_DATA_FORMAT_32;
1340 case PIPE_FORMAT_X32_S8X24_UINT:
1341 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1342 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1343 default:
1344 goto out_unknown;
1345 }
1346
1347 case UTIL_FORMAT_COLORSPACE_YUV:
1348 goto out_unknown; /* TODO */
1349
1350 case UTIL_FORMAT_COLORSPACE_SRGB:
1351 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1352 goto out_unknown;
1353 break;
1354
1355 default:
1356 break;
1357 }
1358
1359 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1360 if (!enable_compressed_formats)
1361 goto out_unknown;
1362
1363 switch (format) {
1364 case PIPE_FORMAT_RGTC1_SNORM:
1365 case PIPE_FORMAT_LATC1_SNORM:
1366 case PIPE_FORMAT_RGTC1_UNORM:
1367 case PIPE_FORMAT_LATC1_UNORM:
1368 return V_008F14_IMG_DATA_FORMAT_BC4;
1369 case PIPE_FORMAT_RGTC2_SNORM:
1370 case PIPE_FORMAT_LATC2_SNORM:
1371 case PIPE_FORMAT_RGTC2_UNORM:
1372 case PIPE_FORMAT_LATC2_UNORM:
1373 return V_008F14_IMG_DATA_FORMAT_BC5;
1374 default:
1375 goto out_unknown;
1376 }
1377 }
1378
1379 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1380 sscreen->b.family >= CHIP_STONEY) {
1381 switch (format) {
1382 case PIPE_FORMAT_ETC2_RGB8:
1383 case PIPE_FORMAT_ETC2_SRGB8:
1384 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1385 case PIPE_FORMAT_ETC2_RGB8A1:
1386 case PIPE_FORMAT_ETC2_SRGB8A1:
1387 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1388 case PIPE_FORMAT_ETC2_RGBA8:
1389 case PIPE_FORMAT_ETC2_SRGBA8:
1390 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1391 case PIPE_FORMAT_ETC2_R11_UNORM:
1392 case PIPE_FORMAT_ETC2_R11_SNORM:
1393 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1394 case PIPE_FORMAT_ETC2_RG11_UNORM:
1395 case PIPE_FORMAT_ETC2_RG11_SNORM:
1396 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1397 default:
1398 goto out_unknown;
1399 }
1400 }
1401
1402 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1403 if (!enable_compressed_formats)
1404 goto out_unknown;
1405
1406 switch (format) {
1407 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1408 case PIPE_FORMAT_BPTC_SRGBA:
1409 return V_008F14_IMG_DATA_FORMAT_BC7;
1410 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1411 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1412 return V_008F14_IMG_DATA_FORMAT_BC6;
1413 default:
1414 goto out_unknown;
1415 }
1416 }
1417
1418 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1419 switch (format) {
1420 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1421 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1422 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1423 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1424 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1425 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1426 default:
1427 goto out_unknown;
1428 }
1429 }
1430
1431 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1432 if (!enable_compressed_formats)
1433 goto out_unknown;
1434
1435 if (!util_format_s3tc_enabled) {
1436 goto out_unknown;
1437 }
1438
1439 switch (format) {
1440 case PIPE_FORMAT_DXT1_RGB:
1441 case PIPE_FORMAT_DXT1_RGBA:
1442 case PIPE_FORMAT_DXT1_SRGB:
1443 case PIPE_FORMAT_DXT1_SRGBA:
1444 return V_008F14_IMG_DATA_FORMAT_BC1;
1445 case PIPE_FORMAT_DXT3_RGBA:
1446 case PIPE_FORMAT_DXT3_SRGBA:
1447 return V_008F14_IMG_DATA_FORMAT_BC2;
1448 case PIPE_FORMAT_DXT5_RGBA:
1449 case PIPE_FORMAT_DXT5_SRGBA:
1450 return V_008F14_IMG_DATA_FORMAT_BC3;
1451 default:
1452 goto out_unknown;
1453 }
1454 }
1455
1456 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1457 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1458 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1459 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1460 }
1461
1462 /* R8G8Bx_SNORM - TODO CxV8U8 */
1463
1464 /* See whether the components are of the same size. */
1465 for (i = 1; i < desc->nr_channels; i++) {
1466 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1467 }
1468
1469 /* Non-uniform formats. */
1470 if (!uniform) {
1471 switch(desc->nr_channels) {
1472 case 3:
1473 if (desc->channel[0].size == 5 &&
1474 desc->channel[1].size == 6 &&
1475 desc->channel[2].size == 5) {
1476 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1477 }
1478 goto out_unknown;
1479 case 4:
1480 if (desc->channel[0].size == 5 &&
1481 desc->channel[1].size == 5 &&
1482 desc->channel[2].size == 5 &&
1483 desc->channel[3].size == 1) {
1484 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1485 }
1486 if (desc->channel[0].size == 10 &&
1487 desc->channel[1].size == 10 &&
1488 desc->channel[2].size == 10 &&
1489 desc->channel[3].size == 2) {
1490 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1491 }
1492 goto out_unknown;
1493 }
1494 goto out_unknown;
1495 }
1496
1497 if (first_non_void < 0 || first_non_void > 3)
1498 goto out_unknown;
1499
1500 /* uniform formats */
1501 switch (desc->channel[first_non_void].size) {
1502 case 4:
1503 switch (desc->nr_channels) {
1504 #if 0 /* Not supported for render targets */
1505 case 2:
1506 return V_008F14_IMG_DATA_FORMAT_4_4;
1507 #endif
1508 case 4:
1509 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1510 }
1511 break;
1512 case 8:
1513 switch (desc->nr_channels) {
1514 case 1:
1515 return V_008F14_IMG_DATA_FORMAT_8;
1516 case 2:
1517 return V_008F14_IMG_DATA_FORMAT_8_8;
1518 case 4:
1519 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1520 }
1521 break;
1522 case 16:
1523 switch (desc->nr_channels) {
1524 case 1:
1525 return V_008F14_IMG_DATA_FORMAT_16;
1526 case 2:
1527 return V_008F14_IMG_DATA_FORMAT_16_16;
1528 case 4:
1529 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1530 }
1531 break;
1532 case 32:
1533 switch (desc->nr_channels) {
1534 case 1:
1535 return V_008F14_IMG_DATA_FORMAT_32;
1536 case 2:
1537 return V_008F14_IMG_DATA_FORMAT_32_32;
1538 #if 0 /* Not supported for render targets */
1539 case 3:
1540 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1541 #endif
1542 case 4:
1543 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1544 }
1545 }
1546
1547 out_unknown:
1548 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1549 return ~0;
1550 }
1551
1552 static unsigned si_tex_wrap(unsigned wrap)
1553 {
1554 switch (wrap) {
1555 default:
1556 case PIPE_TEX_WRAP_REPEAT:
1557 return V_008F30_SQ_TEX_WRAP;
1558 case PIPE_TEX_WRAP_CLAMP:
1559 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1560 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1561 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1562 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1563 return V_008F30_SQ_TEX_CLAMP_BORDER;
1564 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1565 return V_008F30_SQ_TEX_MIRROR;
1566 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1567 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1568 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1569 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1570 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1571 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1572 }
1573 }
1574
1575 static unsigned si_tex_filter(unsigned filter)
1576 {
1577 switch (filter) {
1578 default:
1579 case PIPE_TEX_FILTER_NEAREST:
1580 return V_008F38_SQ_TEX_XY_FILTER_POINT;
1581 case PIPE_TEX_FILTER_LINEAR:
1582 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
1583 }
1584 }
1585
1586 static unsigned si_tex_mipfilter(unsigned filter)
1587 {
1588 switch (filter) {
1589 case PIPE_TEX_MIPFILTER_NEAREST:
1590 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1591 case PIPE_TEX_MIPFILTER_LINEAR:
1592 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1593 default:
1594 case PIPE_TEX_MIPFILTER_NONE:
1595 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1596 }
1597 }
1598
1599 static unsigned si_tex_compare(unsigned compare)
1600 {
1601 switch (compare) {
1602 default:
1603 case PIPE_FUNC_NEVER:
1604 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1605 case PIPE_FUNC_LESS:
1606 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1607 case PIPE_FUNC_EQUAL:
1608 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1609 case PIPE_FUNC_LEQUAL:
1610 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1611 case PIPE_FUNC_GREATER:
1612 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1613 case PIPE_FUNC_NOTEQUAL:
1614 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1615 case PIPE_FUNC_GEQUAL:
1616 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1617 case PIPE_FUNC_ALWAYS:
1618 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1619 }
1620 }
1621
1622 static unsigned si_tex_dim(unsigned res_target, unsigned view_target,
1623 unsigned nr_samples)
1624 {
1625 if (view_target == PIPE_TEXTURE_CUBE ||
1626 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1627 res_target = view_target;
1628
1629 switch (res_target) {
1630 default:
1631 case PIPE_TEXTURE_1D:
1632 return V_008F1C_SQ_RSRC_IMG_1D;
1633 case PIPE_TEXTURE_1D_ARRAY:
1634 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1635 case PIPE_TEXTURE_2D:
1636 case PIPE_TEXTURE_RECT:
1637 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1638 V_008F1C_SQ_RSRC_IMG_2D;
1639 case PIPE_TEXTURE_2D_ARRAY:
1640 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1641 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1642 case PIPE_TEXTURE_3D:
1643 return V_008F1C_SQ_RSRC_IMG_3D;
1644 case PIPE_TEXTURE_CUBE:
1645 case PIPE_TEXTURE_CUBE_ARRAY:
1646 return V_008F1C_SQ_RSRC_IMG_CUBE;
1647 }
1648 }
1649
1650 /*
1651 * Format support testing
1652 */
1653
1654 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1655 {
1656 return si_translate_texformat(screen, format, util_format_description(format),
1657 util_format_get_first_non_void_channel(format)) != ~0U;
1658 }
1659
1660 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1661 const struct util_format_description *desc,
1662 int first_non_void)
1663 {
1664 unsigned type = desc->channel[first_non_void].type;
1665 int i;
1666
1667 if (type == UTIL_FORMAT_TYPE_FIXED)
1668 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1669
1670 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1671 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1672
1673 if (desc->nr_channels == 4 &&
1674 desc->channel[0].size == 10 &&
1675 desc->channel[1].size == 10 &&
1676 desc->channel[2].size == 10 &&
1677 desc->channel[3].size == 2)
1678 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1679
1680 /* See whether the components are of the same size. */
1681 for (i = 0; i < desc->nr_channels; i++) {
1682 if (desc->channel[first_non_void].size != desc->channel[i].size)
1683 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1684 }
1685
1686 switch (desc->channel[first_non_void].size) {
1687 case 8:
1688 switch (desc->nr_channels) {
1689 case 1:
1690 return V_008F0C_BUF_DATA_FORMAT_8;
1691 case 2:
1692 return V_008F0C_BUF_DATA_FORMAT_8_8;
1693 case 3:
1694 case 4:
1695 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1696 }
1697 break;
1698 case 16:
1699 switch (desc->nr_channels) {
1700 case 1:
1701 return V_008F0C_BUF_DATA_FORMAT_16;
1702 case 2:
1703 return V_008F0C_BUF_DATA_FORMAT_16_16;
1704 case 3:
1705 case 4:
1706 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1707 }
1708 break;
1709 case 32:
1710 /* From the Southern Islands ISA documentation about MTBUF:
1711 * 'Memory reads of data in memory that is 32 or 64 bits do not
1712 * undergo any format conversion.'
1713 */
1714 if (type != UTIL_FORMAT_TYPE_FLOAT &&
1715 !desc->channel[first_non_void].pure_integer)
1716 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1717
1718 switch (desc->nr_channels) {
1719 case 1:
1720 return V_008F0C_BUF_DATA_FORMAT_32;
1721 case 2:
1722 return V_008F0C_BUF_DATA_FORMAT_32_32;
1723 case 3:
1724 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1725 case 4:
1726 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1727 }
1728 break;
1729 }
1730
1731 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1732 }
1733
1734 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1735 const struct util_format_description *desc,
1736 int first_non_void)
1737 {
1738 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1739 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1740
1741 switch (desc->channel[first_non_void].type) {
1742 case UTIL_FORMAT_TYPE_SIGNED:
1743 if (desc->channel[first_non_void].normalized)
1744 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1745 else if (desc->channel[first_non_void].pure_integer)
1746 return V_008F0C_BUF_NUM_FORMAT_SINT;
1747 else
1748 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1749 break;
1750 case UTIL_FORMAT_TYPE_UNSIGNED:
1751 if (desc->channel[first_non_void].normalized)
1752 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1753 else if (desc->channel[first_non_void].pure_integer)
1754 return V_008F0C_BUF_NUM_FORMAT_UINT;
1755 else
1756 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1757 break;
1758 case UTIL_FORMAT_TYPE_FLOAT:
1759 default:
1760 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1761 }
1762 }
1763
1764 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
1765 {
1766 const struct util_format_description *desc;
1767 int first_non_void;
1768 unsigned data_format;
1769
1770 desc = util_format_description(format);
1771 first_non_void = util_format_get_first_non_void_channel(format);
1772 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1773 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
1774 }
1775
1776 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1777 {
1778 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1779 r600_translate_colorswap(format) != ~0U;
1780 }
1781
1782 static bool si_is_zs_format_supported(enum pipe_format format)
1783 {
1784 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1785 }
1786
1787 boolean si_is_format_supported(struct pipe_screen *screen,
1788 enum pipe_format format,
1789 enum pipe_texture_target target,
1790 unsigned sample_count,
1791 unsigned usage)
1792 {
1793 unsigned retval = 0;
1794
1795 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1796 R600_ERR("r600: unsupported texture type %d\n", target);
1797 return FALSE;
1798 }
1799
1800 if (!util_format_is_supported(format, usage))
1801 return FALSE;
1802
1803 if (sample_count > 1) {
1804 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
1805 return FALSE;
1806
1807 switch (sample_count) {
1808 case 2:
1809 case 4:
1810 case 8:
1811 break;
1812 default:
1813 return FALSE;
1814 }
1815 }
1816
1817 if (usage & PIPE_BIND_SAMPLER_VIEW) {
1818 if (target == PIPE_BUFFER) {
1819 if (si_is_vertex_format_supported(screen, format))
1820 retval |= PIPE_BIND_SAMPLER_VIEW;
1821 } else {
1822 if (si_is_sampler_format_supported(screen, format))
1823 retval |= PIPE_BIND_SAMPLER_VIEW;
1824 }
1825 }
1826
1827 if ((usage & (PIPE_BIND_RENDER_TARGET |
1828 PIPE_BIND_DISPLAY_TARGET |
1829 PIPE_BIND_SCANOUT |
1830 PIPE_BIND_SHARED |
1831 PIPE_BIND_BLENDABLE)) &&
1832 si_is_colorbuffer_format_supported(format)) {
1833 retval |= usage &
1834 (PIPE_BIND_RENDER_TARGET |
1835 PIPE_BIND_DISPLAY_TARGET |
1836 PIPE_BIND_SCANOUT |
1837 PIPE_BIND_SHARED);
1838 if (!util_format_is_pure_integer(format) &&
1839 !util_format_is_depth_or_stencil(format))
1840 retval |= usage & PIPE_BIND_BLENDABLE;
1841 }
1842
1843 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1844 si_is_zs_format_supported(format)) {
1845 retval |= PIPE_BIND_DEPTH_STENCIL;
1846 }
1847
1848 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
1849 si_is_vertex_format_supported(screen, format)) {
1850 retval |= PIPE_BIND_VERTEX_BUFFER;
1851 }
1852
1853 if (usage & PIPE_BIND_TRANSFER_READ)
1854 retval |= PIPE_BIND_TRANSFER_READ;
1855 if (usage & PIPE_BIND_TRANSFER_WRITE)
1856 retval |= PIPE_BIND_TRANSFER_WRITE;
1857
1858 return retval == usage;
1859 }
1860
1861 unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
1862 {
1863 unsigned tile_mode_index = 0;
1864
1865 if (stencil) {
1866 tile_mode_index = rtex->surface.stencil_tiling_index[level];
1867 } else {
1868 tile_mode_index = rtex->surface.tiling_index[level];
1869 }
1870 return tile_mode_index;
1871 }
1872
1873 /*
1874 * framebuffer handling
1875 */
1876
1877 static void si_choose_spi_color_formats(struct r600_surface *surf,
1878 unsigned format, unsigned swap,
1879 unsigned ntype, bool is_depth)
1880 {
1881 /* Alpha is needed for alpha-to-coverage.
1882 * Blending may be with or without alpha.
1883 */
1884 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
1885 unsigned alpha = 0; /* exports alpha, but may not support blending */
1886 unsigned blend = 0; /* supports blending, but may not export alpha */
1887 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
1888
1889 /* Choose the SPI color formats. These are required values for Stoney/RB+.
1890 * Other chips have multiple choices, though they are not necessarily better.
1891 */
1892 switch (format) {
1893 case V_028C70_COLOR_5_6_5:
1894 case V_028C70_COLOR_1_5_5_5:
1895 case V_028C70_COLOR_5_5_5_1:
1896 case V_028C70_COLOR_4_4_4_4:
1897 case V_028C70_COLOR_10_11_11:
1898 case V_028C70_COLOR_11_11_10:
1899 case V_028C70_COLOR_8:
1900 case V_028C70_COLOR_8_8:
1901 case V_028C70_COLOR_8_8_8_8:
1902 case V_028C70_COLOR_10_10_10_2:
1903 case V_028C70_COLOR_2_10_10_10:
1904 if (ntype == V_028C70_NUMBER_UINT)
1905 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
1906 else if (ntype == V_028C70_NUMBER_SINT)
1907 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
1908 else
1909 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
1910 break;
1911
1912 case V_028C70_COLOR_16:
1913 case V_028C70_COLOR_16_16:
1914 case V_028C70_COLOR_16_16_16_16:
1915 if (ntype == V_028C70_NUMBER_UNORM ||
1916 ntype == V_028C70_NUMBER_SNORM) {
1917 /* UNORM16 and SNORM16 don't support blending */
1918 if (ntype == V_028C70_NUMBER_UNORM)
1919 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
1920 else
1921 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
1922
1923 /* Use 32 bits per channel for blending. */
1924 if (format == V_028C70_COLOR_16) {
1925 if (swap == V_028C70_SWAP_STD) { /* R */
1926 blend = V_028714_SPI_SHADER_32_R;
1927 blend_alpha = V_028714_SPI_SHADER_32_AR;
1928 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
1929 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
1930 else
1931 assert(0);
1932 } else if (format == V_028C70_COLOR_16_16) {
1933 if (swap == V_028C70_SWAP_STD) { /* RG */
1934 blend = V_028714_SPI_SHADER_32_GR;
1935 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
1936 } else if (swap == V_028C70_SWAP_ALT) /* RA */
1937 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
1938 else
1939 assert(0);
1940 } else /* 16_16_16_16 */
1941 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
1942 } else if (ntype == V_028C70_NUMBER_UINT)
1943 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
1944 else if (ntype == V_028C70_NUMBER_SINT)
1945 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
1946 else if (ntype == V_028C70_NUMBER_FLOAT)
1947 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
1948 else
1949 assert(0);
1950 break;
1951
1952 case V_028C70_COLOR_32:
1953 if (swap == V_028C70_SWAP_STD) { /* R */
1954 blend = normal = V_028714_SPI_SHADER_32_R;
1955 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
1956 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
1957 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
1958 else
1959 assert(0);
1960 break;
1961
1962 case V_028C70_COLOR_32_32:
1963 if (swap == V_028C70_SWAP_STD) { /* RG */
1964 blend = normal = V_028714_SPI_SHADER_32_GR;
1965 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
1966 } else if (swap == V_028C70_SWAP_ALT) /* RA */
1967 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
1968 else
1969 assert(0);
1970 break;
1971
1972 case V_028C70_COLOR_32_32_32_32:
1973 case V_028C70_COLOR_8_24:
1974 case V_028C70_COLOR_24_8:
1975 case V_028C70_COLOR_X24_8_32_FLOAT:
1976 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
1977 break;
1978
1979 default:
1980 assert(0);
1981 return;
1982 }
1983
1984 /* The DB->CB copy needs 32_ABGR. */
1985 if (is_depth)
1986 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
1987
1988 surf->spi_shader_col_format = normal;
1989 surf->spi_shader_col_format_alpha = alpha;
1990 surf->spi_shader_col_format_blend = blend;
1991 surf->spi_shader_col_format_blend_alpha = blend_alpha;
1992 }
1993
1994 static void si_initialize_color_surface(struct si_context *sctx,
1995 struct r600_surface *surf)
1996 {
1997 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1998 unsigned level = surf->base.u.tex.level;
1999 uint64_t offset = rtex->surface.level[level].offset;
2000 unsigned pitch, slice;
2001 unsigned color_info, color_attrib, color_pitch, color_view;
2002 unsigned tile_mode_index;
2003 unsigned format, swap, ntype, endian;
2004 const struct util_format_description *desc;
2005 int i;
2006 unsigned blend_clamp = 0, blend_bypass = 0;
2007
2008 /* Layered rendering doesn't work with LINEAR_GENERAL.
2009 * (LINEAR_ALIGNED and others work) */
2010 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) {
2011 assert(surf->base.u.tex.first_layer == surf->base.u.tex.last_layer);
2012 offset += rtex->surface.level[level].slice_size *
2013 surf->base.u.tex.first_layer;
2014 color_view = 0;
2015 } else {
2016 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2017 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
2018 }
2019
2020 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
2021 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
2022 if (slice) {
2023 slice = slice - 1;
2024 }
2025
2026 tile_mode_index = si_tile_mode_index(rtex, level, false);
2027
2028 desc = util_format_description(surf->base.format);
2029 for (i = 0; i < 4; i++) {
2030 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2031 break;
2032 }
2033 }
2034 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
2035 ntype = V_028C70_NUMBER_FLOAT;
2036 } else {
2037 ntype = V_028C70_NUMBER_UNORM;
2038 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2039 ntype = V_028C70_NUMBER_SRGB;
2040 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2041 if (desc->channel[i].pure_integer) {
2042 ntype = V_028C70_NUMBER_SINT;
2043 } else {
2044 assert(desc->channel[i].normalized);
2045 ntype = V_028C70_NUMBER_SNORM;
2046 }
2047 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2048 if (desc->channel[i].pure_integer) {
2049 ntype = V_028C70_NUMBER_UINT;
2050 } else {
2051 assert(desc->channel[i].normalized);
2052 ntype = V_028C70_NUMBER_UNORM;
2053 }
2054 }
2055 }
2056
2057 format = si_translate_colorformat(surf->base.format);
2058 if (format == V_028C70_COLOR_INVALID) {
2059 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2060 }
2061 assert(format != V_028C70_COLOR_INVALID);
2062 swap = r600_translate_colorswap(surf->base.format);
2063 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
2064 endian = V_028C70_ENDIAN_NONE;
2065 } else {
2066 endian = si_colorformat_endian_swap(format);
2067 }
2068
2069 /* blend clamp should be set for all NORM/SRGB types */
2070 if (ntype == V_028C70_NUMBER_UNORM ||
2071 ntype == V_028C70_NUMBER_SNORM ||
2072 ntype == V_028C70_NUMBER_SRGB)
2073 blend_clamp = 1;
2074
2075 /* set blend bypass according to docs if SINT/UINT or
2076 8/24 COLOR variants */
2077 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2078 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2079 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2080 blend_clamp = 0;
2081 blend_bypass = 1;
2082 }
2083
2084 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
2085 (format == V_028C70_COLOR_8 ||
2086 format == V_028C70_COLOR_8_8 ||
2087 format == V_028C70_COLOR_8_8_8_8))
2088 surf->color_is_int8 = true;
2089
2090 color_info = S_028C70_FORMAT(format) |
2091 S_028C70_COMP_SWAP(swap) |
2092 S_028C70_BLEND_CLAMP(blend_clamp) |
2093 S_028C70_BLEND_BYPASS(blend_bypass) |
2094 S_028C70_NUMBER_TYPE(ntype) |
2095 S_028C70_ENDIAN(endian);
2096
2097 color_pitch = S_028C64_TILE_MAX(pitch);
2098
2099 color_attrib = S_028C74_TILE_MODE_INDEX(tile_mode_index) |
2100 S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == UTIL_FORMAT_SWIZZLE_1);
2101
2102 if (rtex->resource.b.b.nr_samples > 1) {
2103 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
2104
2105 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2106 S_028C74_NUM_FRAGMENTS(log_samples);
2107
2108 if (rtex->fmask.size) {
2109 color_info |= S_028C70_COMPRESSION(1);
2110 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
2111
2112 color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(rtex->fmask.tile_mode_index);
2113
2114 if (sctx->b.chip_class == SI) {
2115 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2116 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2117 }
2118 if (sctx->b.chip_class >= CIK) {
2119 color_pitch |= S_028C64_FMASK_TILE_MAX(rtex->fmask.pitch_in_pixels / 8 - 1);
2120 }
2121 }
2122 }
2123
2124 offset += rtex->resource.gpu_address;
2125
2126 surf->cb_color_base = offset >> 8;
2127 surf->cb_color_pitch = color_pitch;
2128 surf->cb_color_slice = S_028C68_TILE_MAX(slice);
2129 surf->cb_color_view = color_view;
2130 surf->cb_color_info = color_info;
2131 surf->cb_color_attrib = color_attrib;
2132
2133 if (sctx->b.chip_class >= VI && rtex->dcc_buffer) {
2134 unsigned max_uncompressed_block_size = 2;
2135 uint64_t dcc_offset = rtex->surface.level[level].dcc_offset;
2136
2137 if (rtex->surface.nsamples > 1) {
2138 if (rtex->surface.bpe == 1)
2139 max_uncompressed_block_size = 0;
2140 else if (rtex->surface.bpe == 2)
2141 max_uncompressed_block_size = 1;
2142 }
2143
2144 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2145 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2146 surf->cb_dcc_base = (rtex->dcc_buffer->gpu_address + dcc_offset) >> 8;
2147 }
2148
2149 if (rtex->fmask.size) {
2150 surf->cb_color_fmask = (offset + rtex->fmask.offset) >> 8;
2151 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max);
2152 } else {
2153 /* This must be set for fast clear to work without FMASK. */
2154 surf->cb_color_fmask = surf->cb_color_base;
2155 surf->cb_color_fmask_slice = surf->cb_color_slice;
2156 surf->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
2157
2158 if (sctx->b.chip_class == SI) {
2159 unsigned bankh = util_logbase2(rtex->surface.bankh);
2160 surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2161 }
2162
2163 if (sctx->b.chip_class >= CIK) {
2164 surf->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch);
2165 }
2166 }
2167
2168 /* Determine pixel shader export format */
2169 si_choose_spi_color_formats(surf, format, swap, ntype, rtex->is_depth);
2170
2171 if (sctx->b.family == CHIP_STONEY &&
2172 !(sctx->screen->b.debug_flags & DBG_NO_RB_PLUS)) {
2173 switch (desc->channel[0].size) {
2174 case 32:
2175 if (desc->nr_channels == 1) {
2176 if (swap == V_0280A0_SWAP_STD)
2177 surf->sx_ps_downconvert = V_028754_SX_RT_EXPORT_32_R;
2178 else if (swap == V_0280A0_SWAP_ALT_REV)
2179 surf->sx_ps_downconvert = V_028754_SX_RT_EXPORT_32_A;
2180 }
2181 break;
2182 case 16:
2183 /* For 1-channel formats, use the superset thereof. */
2184 if (desc->nr_channels <= 2) {
2185 if (swap == V_0280A0_SWAP_STD ||
2186 swap == V_0280A0_SWAP_STD_REV)
2187 surf->sx_ps_downconvert = V_028754_SX_RT_EXPORT_16_16_GR;
2188 else
2189 surf->sx_ps_downconvert = V_028754_SX_RT_EXPORT_16_16_AR;
2190 }
2191 break;
2192 case 11:
2193 if (desc->nr_channels == 3) {
2194 surf->sx_ps_downconvert = V_028754_SX_RT_EXPORT_10_11_11;
2195 surf->sx_blend_opt_epsilon = V_028758_11BIT_FORMAT;
2196 }
2197 break;
2198 case 10:
2199 if (desc->nr_channels == 4) {
2200 surf->sx_ps_downconvert = V_028754_SX_RT_EXPORT_2_10_10_10;
2201 surf->sx_blend_opt_epsilon = V_028758_10BIT_FORMAT;
2202 }
2203 break;
2204 case 8:
2205 /* For 1 and 2-channel formats, use the superset thereof. */
2206 surf->sx_ps_downconvert = V_028754_SX_RT_EXPORT_8_8_8_8;
2207 surf->sx_blend_opt_epsilon = V_028758_8BIT_FORMAT;
2208 break;
2209 case 5:
2210 if (desc->nr_channels == 3) {
2211 surf->sx_ps_downconvert = V_028754_SX_RT_EXPORT_5_6_5;
2212 surf->sx_blend_opt_epsilon = V_028758_6BIT_FORMAT;
2213 } else if (desc->nr_channels == 4) {
2214 surf->sx_ps_downconvert = V_028754_SX_RT_EXPORT_1_5_5_5;
2215 surf->sx_blend_opt_epsilon = V_028758_5BIT_FORMAT;
2216 }
2217 break;
2218 case 4:
2219 /* For 1 nad 2-channel formats, use the superset thereof. */
2220 surf->sx_ps_downconvert = V_028754_SX_RT_EXPORT_4_4_4_4;
2221 surf->sx_blend_opt_epsilon = V_028758_4BIT_FORMAT;
2222 break;
2223 }
2224 }
2225
2226 surf->color_initialized = true;
2227 }
2228
2229 static void si_init_depth_surface(struct si_context *sctx,
2230 struct r600_surface *surf)
2231 {
2232 struct si_screen *sscreen = sctx->screen;
2233 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2234 unsigned level = surf->base.u.tex.level;
2235 struct radeon_surf_level *levelinfo = &rtex->surface.level[level];
2236 unsigned format, tile_mode_index, array_mode;
2237 unsigned macro_aspect, tile_split, stile_split, bankh, bankw, nbanks, pipe_config;
2238 uint32_t z_info, s_info, db_depth_info;
2239 uint64_t z_offs, s_offs;
2240 uint32_t db_htile_data_base, db_htile_surface, pa_su_poly_offset_db_fmt_cntl = 0;
2241
2242 switch (sctx->framebuffer.state.zsbuf->texture->format) {
2243 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2244 case PIPE_FORMAT_X8Z24_UNORM:
2245 case PIPE_FORMAT_Z24X8_UNORM:
2246 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
2247 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
2248 break;
2249 case PIPE_FORMAT_Z32_FLOAT:
2250 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2251 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
2252 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2253 break;
2254 case PIPE_FORMAT_Z16_UNORM:
2255 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
2256 break;
2257 default:
2258 assert(0);
2259 }
2260
2261 format = si_translate_dbformat(rtex->resource.b.b.format);
2262
2263 if (format == V_028040_Z_INVALID) {
2264 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
2265 }
2266 assert(format != V_028040_Z_INVALID);
2267
2268 s_offs = z_offs = rtex->resource.gpu_address;
2269 z_offs += rtex->surface.level[level].offset;
2270 s_offs += rtex->surface.stencil_level[level].offset;
2271
2272 db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
2273
2274 z_info = S_028040_FORMAT(format);
2275 if (rtex->resource.b.b.nr_samples > 1) {
2276 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
2277 }
2278
2279 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
2280 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
2281 else
2282 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
2283
2284 if (sctx->b.chip_class >= CIK) {
2285 switch (rtex->surface.level[level].mode) {
2286 case RADEON_SURF_MODE_2D:
2287 array_mode = V_02803C_ARRAY_2D_TILED_THIN1;
2288 break;
2289 case RADEON_SURF_MODE_1D:
2290 case RADEON_SURF_MODE_LINEAR_ALIGNED:
2291 case RADEON_SURF_MODE_LINEAR:
2292 default:
2293 array_mode = V_02803C_ARRAY_1D_TILED_THIN1;
2294 break;
2295 }
2296 tile_split = rtex->surface.tile_split;
2297 stile_split = rtex->surface.stencil_tile_split;
2298 macro_aspect = rtex->surface.mtilea;
2299 bankw = rtex->surface.bankw;
2300 bankh = rtex->surface.bankh;
2301 tile_split = cik_tile_split(tile_split);
2302 stile_split = cik_tile_split(stile_split);
2303 macro_aspect = cik_macro_tile_aspect(macro_aspect);
2304 bankw = cik_bank_wh(bankw);
2305 bankh = cik_bank_wh(bankh);
2306 nbanks = si_num_banks(sscreen, rtex);
2307 tile_mode_index = si_tile_mode_index(rtex, level, false);
2308 pipe_config = cik_db_pipe_config(sscreen, tile_mode_index);
2309
2310 db_depth_info |= S_02803C_ARRAY_MODE(array_mode) |
2311 S_02803C_PIPE_CONFIG(pipe_config) |
2312 S_02803C_BANK_WIDTH(bankw) |
2313 S_02803C_BANK_HEIGHT(bankh) |
2314 S_02803C_MACRO_TILE_ASPECT(macro_aspect) |
2315 S_02803C_NUM_BANKS(nbanks);
2316 z_info |= S_028040_TILE_SPLIT(tile_split);
2317 s_info |= S_028044_TILE_SPLIT(stile_split);
2318 } else {
2319 tile_mode_index = si_tile_mode_index(rtex, level, false);
2320 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2321 tile_mode_index = si_tile_mode_index(rtex, level, true);
2322 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2323 }
2324
2325 /* HiZ aka depth buffer htile */
2326 /* use htile only for first level */
2327 if (rtex->htile_buffer && !level) {
2328 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2329 S_028040_ALLOW_EXPCLEAR(1);
2330
2331 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
2332 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2333 else
2334 /* Use all of the htile_buffer for depth if there's no stencil. */
2335 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2336
2337 uint64_t va = rtex->htile_buffer->gpu_address;
2338 db_htile_data_base = va >> 8;
2339 db_htile_surface = S_028ABC_FULL_CACHE(1);
2340 } else {
2341 db_htile_data_base = 0;
2342 db_htile_surface = 0;
2343 }
2344
2345 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2346
2347 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2348 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2349 surf->db_htile_data_base = db_htile_data_base;
2350 surf->db_depth_info = db_depth_info;
2351 surf->db_z_info = z_info;
2352 surf->db_stencil_info = s_info;
2353 surf->db_depth_base = z_offs >> 8;
2354 surf->db_stencil_base = s_offs >> 8;
2355 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2356 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2357 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2358 levelinfo->nblk_y) / 64 - 1);
2359 surf->db_htile_surface = db_htile_surface;
2360 surf->pa_su_poly_offset_db_fmt_cntl = pa_su_poly_offset_db_fmt_cntl;
2361
2362 surf->depth_initialized = true;
2363 }
2364
2365 static void si_set_framebuffer_state(struct pipe_context *ctx,
2366 const struct pipe_framebuffer_state *state)
2367 {
2368 struct si_context *sctx = (struct si_context *)ctx;
2369 struct pipe_constant_buffer constbuf = {0};
2370 struct r600_surface *surf = NULL;
2371 struct r600_texture *rtex;
2372 bool old_cb0_is_integer = sctx->framebuffer.cb0_is_integer;
2373 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2374 int i;
2375
2376 /* Only flush TC when changing the framebuffer state, because
2377 * the only client not using TC that can change textures is
2378 * the framebuffer.
2379 *
2380 * Flush all CB and DB caches here because all buffers can be used
2381 * for write by both TC (with shader image stores) and CB/DB.
2382 */
2383 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
2384 SI_CONTEXT_INV_GLOBAL_L2 |
2385 SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER;
2386
2387 /* Take the maximum of the old and new count. If the new count is lower,
2388 * dirtying is needed to disable the unbound colorbuffers.
2389 */
2390 sctx->framebuffer.dirty_cbufs |=
2391 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2392 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2393
2394 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2395
2396 sctx->framebuffer.spi_shader_col_format = 0;
2397 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2398 sctx->framebuffer.spi_shader_col_format_blend = 0;
2399 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2400 sctx->framebuffer.color_is_int8 = 0;
2401
2402 sctx->framebuffer.compressed_cb_mask = 0;
2403 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2404 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2405 sctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
2406 util_format_is_pure_integer(state->cbufs[0]->format);
2407
2408 if (sctx->framebuffer.cb0_is_integer != old_cb0_is_integer)
2409 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2410
2411 for (i = 0; i < state->nr_cbufs; i++) {
2412 if (!state->cbufs[i])
2413 continue;
2414
2415 surf = (struct r600_surface*)state->cbufs[i];
2416 rtex = (struct r600_texture*)surf->base.texture;
2417
2418 if (!surf->color_initialized) {
2419 si_initialize_color_surface(sctx, surf);
2420 }
2421
2422 sctx->framebuffer.spi_shader_col_format |=
2423 surf->spi_shader_col_format << (i * 4);
2424 sctx->framebuffer.spi_shader_col_format_alpha |=
2425 surf->spi_shader_col_format_alpha << (i * 4);
2426 sctx->framebuffer.spi_shader_col_format_blend |=
2427 surf->spi_shader_col_format_blend << (i * 4);
2428 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2429 surf->spi_shader_col_format_blend_alpha << (i * 4);
2430
2431 if (surf->color_is_int8)
2432 sctx->framebuffer.color_is_int8 |= 1 << i;
2433
2434 if (rtex->fmask.size && rtex->cmask.size) {
2435 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2436 }
2437 r600_context_add_resource_size(ctx, surf->base.texture);
2438 }
2439 /* Set the second SPI format for possible dual-src blending. */
2440 if (i == 1 && surf) {
2441 sctx->framebuffer.spi_shader_col_format |=
2442 surf->spi_shader_col_format << (i * 4);
2443 sctx->framebuffer.spi_shader_col_format_alpha |=
2444 surf->spi_shader_col_format_alpha << (i * 4);
2445 sctx->framebuffer.spi_shader_col_format_blend |=
2446 surf->spi_shader_col_format_blend << (i * 4);
2447 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2448 surf->spi_shader_col_format_blend_alpha << (i * 4);
2449 }
2450
2451 if (state->zsbuf) {
2452 surf = (struct r600_surface*)state->zsbuf;
2453
2454 if (!surf->depth_initialized) {
2455 si_init_depth_surface(sctx, surf);
2456 }
2457 r600_context_add_resource_size(ctx, surf->base.texture);
2458 }
2459
2460 si_update_poly_offset_state(sctx);
2461 si_mark_atom_dirty(sctx, &sctx->cb_target_mask);
2462 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
2463
2464 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2465 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2466 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2467
2468 /* Set sample locations as fragment shader constants. */
2469 switch (sctx->framebuffer.nr_samples) {
2470 case 1:
2471 constbuf.user_buffer = sctx->b.sample_locations_1x;
2472 break;
2473 case 2:
2474 constbuf.user_buffer = sctx->b.sample_locations_2x;
2475 break;
2476 case 4:
2477 constbuf.user_buffer = sctx->b.sample_locations_4x;
2478 break;
2479 case 8:
2480 constbuf.user_buffer = sctx->b.sample_locations_8x;
2481 break;
2482 case 16:
2483 constbuf.user_buffer = sctx->b.sample_locations_16x;
2484 break;
2485 default:
2486 assert(0);
2487 }
2488 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2489 ctx->set_constant_buffer(ctx, PIPE_SHADER_FRAGMENT,
2490 SI_DRIVER_STATE_CONST_BUF, &constbuf);
2491
2492 /* Smoothing (only possible with nr_samples == 1) uses the same
2493 * sample locations as the MSAA it simulates.
2494 *
2495 * Therefore, don't update the sample locations when
2496 * transitioning from no AA to smoothing-equivalent AA, and
2497 * vice versa.
2498 */
2499 if ((sctx->framebuffer.nr_samples != 1 ||
2500 old_nr_samples != SI_NUM_SMOOTH_AA_SAMPLES) &&
2501 (sctx->framebuffer.nr_samples != SI_NUM_SMOOTH_AA_SAMPLES ||
2502 old_nr_samples != 1))
2503 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs);
2504 }
2505 }
2506
2507 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
2508 {
2509 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2510 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2511 unsigned i, nr_cbufs = state->nr_cbufs;
2512 struct r600_texture *tex = NULL;
2513 struct r600_surface *cb = NULL;
2514 uint32_t sx_ps_downconvert = 0;
2515 uint32_t sx_blend_opt_epsilon = 0;
2516
2517 /* Colorbuffers. */
2518 for (i = 0; i < nr_cbufs; i++) {
2519 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2520 continue;
2521
2522 cb = (struct r600_surface*)state->cbufs[i];
2523 if (!cb) {
2524 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2525 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2526 continue;
2527 }
2528
2529 tex = (struct r600_texture *)cb->base.texture;
2530 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2531 &tex->resource, RADEON_USAGE_READWRITE,
2532 tex->surface.nsamples > 1 ?
2533 RADEON_PRIO_COLOR_BUFFER_MSAA :
2534 RADEON_PRIO_COLOR_BUFFER);
2535
2536 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2537 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2538 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2539 RADEON_PRIO_CMASK);
2540 }
2541
2542 if (tex->dcc_buffer && tex->dcc_buffer != &tex->resource) {
2543 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2544 tex->dcc_buffer, RADEON_USAGE_READWRITE,
2545 RADEON_PRIO_DCC);
2546 }
2547
2548 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
2549 sctx->b.chip_class >= VI ? 14 : 13);
2550 radeon_emit(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
2551 radeon_emit(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
2552 radeon_emit(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
2553 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
2554 radeon_emit(cs, cb->cb_color_info | tex->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
2555 radeon_emit(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
2556 radeon_emit(cs, cb->cb_dcc_control); /* R_028C78_CB_COLOR0_DCC_CONTROL */
2557 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
2558 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
2559 radeon_emit(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
2560 radeon_emit(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
2561 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
2562 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
2563
2564 if (sctx->b.chip_class >= VI)
2565 radeon_emit(cs, cb->cb_dcc_base); /* R_028C94_CB_COLOR0_DCC_BASE */
2566
2567 sx_ps_downconvert |= cb->sx_ps_downconvert << (4 * i);
2568 sx_blend_opt_epsilon |= cb->sx_blend_opt_epsilon << (4 * i);
2569 }
2570 /* set CB_COLOR1_INFO for possible dual-src blending */
2571 if (i == 1 && state->cbufs[0] &&
2572 sctx->framebuffer.dirty_cbufs & (1 << 0)) {
2573 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
2574 cb->cb_color_info | tex->cb_color_info);
2575 sx_ps_downconvert |= cb->sx_ps_downconvert << (4 * i);
2576 sx_blend_opt_epsilon |= cb->sx_blend_opt_epsilon << (4 * i);
2577 i++;
2578 }
2579 for (; i < 8 ; i++)
2580 if (sctx->framebuffer.dirty_cbufs & (1 << i))
2581 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
2582
2583 if (sctx->b.family == CHIP_STONEY) {
2584 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 2);
2585 radeon_emit(cs, sx_ps_downconvert); /* R_028754_SX_PS_DOWNCONVERT */
2586 radeon_emit(cs, sx_blend_opt_epsilon); /* R_028758_SX_BLEND_OPT_EPSILON */
2587 }
2588
2589 /* ZS buffer. */
2590 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
2591 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
2592 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
2593
2594 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2595 &rtex->resource, RADEON_USAGE_READWRITE,
2596 zb->base.texture->nr_samples > 1 ?
2597 RADEON_PRIO_DEPTH_BUFFER_MSAA :
2598 RADEON_PRIO_DEPTH_BUFFER);
2599
2600 if (zb->db_htile_data_base) {
2601 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2602 rtex->htile_buffer, RADEON_USAGE_READWRITE,
2603 RADEON_PRIO_HTILE);
2604 }
2605
2606 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
2607 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
2608
2609 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
2610 radeon_emit(cs, zb->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
2611 radeon_emit(cs, zb->db_z_info | /* R_028040_DB_Z_INFO */
2612 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
2613 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
2614 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
2615 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
2616 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
2617 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
2618 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
2619 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
2620
2621 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
2622 radeon_emit(cs, rtex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
2623 radeon_emit(cs, fui(rtex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
2624
2625 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
2626 radeon_set_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2627 zb->pa_su_poly_offset_db_fmt_cntl);
2628 } else if (sctx->framebuffer.dirty_zsbuf) {
2629 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
2630 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
2631 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
2632 }
2633
2634 /* Framebuffer dimensions. */
2635 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2636 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2637 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
2638
2639 sctx->framebuffer.dirty_cbufs = 0;
2640 sctx->framebuffer.dirty_zsbuf = false;
2641 }
2642
2643 static void si_emit_msaa_sample_locs(struct si_context *sctx,
2644 struct r600_atom *atom)
2645 {
2646 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2647 unsigned nr_samples = sctx->framebuffer.nr_samples;
2648
2649 cayman_emit_msaa_sample_locs(cs, nr_samples > 1 ? nr_samples :
2650 SI_NUM_SMOOTH_AA_SAMPLES);
2651 }
2652
2653 static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom)
2654 {
2655 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2656
2657 cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples,
2658 sctx->ps_iter_samples,
2659 sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0);
2660 }
2661
2662
2663 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
2664 {
2665 struct si_context *sctx = (struct si_context *)ctx;
2666
2667 if (sctx->ps_iter_samples == min_samples)
2668 return;
2669
2670 sctx->ps_iter_samples = min_samples;
2671
2672 if (sctx->framebuffer.nr_samples > 1)
2673 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2674 }
2675
2676 /*
2677 * Samplers
2678 */
2679
2680 /**
2681 * Create a sampler view.
2682 *
2683 * @param ctx context
2684 * @param texture texture
2685 * @param state sampler view template
2686 * @param width0 width0 override (for compressed textures as int)
2687 * @param height0 height0 override (for compressed textures as int)
2688 * @param force_level set the base address to the level (for compressed textures)
2689 */
2690 struct pipe_sampler_view *
2691 si_create_sampler_view_custom(struct pipe_context *ctx,
2692 struct pipe_resource *texture,
2693 const struct pipe_sampler_view *state,
2694 unsigned width0, unsigned height0,
2695 unsigned force_level)
2696 {
2697 struct si_context *sctx = (struct si_context*)ctx;
2698 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
2699 struct r600_texture *tmp = (struct r600_texture*)texture;
2700 const struct util_format_description *desc;
2701 unsigned format, num_format, base_level, first_level, last_level;
2702 uint32_t pitch = 0;
2703 unsigned char state_swizzle[4], swizzle[4];
2704 unsigned height, depth, width;
2705 enum pipe_format pipe_format = state->format;
2706 struct radeon_surf_level *surflevel;
2707 int first_non_void;
2708 uint64_t va;
2709 unsigned last_layer = state->u.tex.last_layer;
2710
2711 if (!view)
2712 return NULL;
2713
2714 /* initialize base object */
2715 view->base = *state;
2716 view->base.texture = NULL;
2717 view->base.reference.count = 1;
2718 view->base.context = ctx;
2719
2720 /* NULL resource, obey swizzle (only ZERO and ONE make sense). */
2721 if (!texture) {
2722 view->state[3] = S_008F1C_DST_SEL_X(si_map_swizzle(state->swizzle_r)) |
2723 S_008F1C_DST_SEL_Y(si_map_swizzle(state->swizzle_g)) |
2724 S_008F1C_DST_SEL_Z(si_map_swizzle(state->swizzle_b)) |
2725 S_008F1C_DST_SEL_W(si_map_swizzle(state->swizzle_a)) |
2726 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D);
2727 return &view->base;
2728 }
2729
2730 pipe_resource_reference(&view->base.texture, texture);
2731 view->resource = &tmp->resource;
2732
2733 if (state->format == PIPE_FORMAT_X24S8_UINT ||
2734 state->format == PIPE_FORMAT_S8X24_UINT ||
2735 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
2736 state->format == PIPE_FORMAT_S8_UINT)
2737 view->is_stencil_sampler = true;
2738
2739 /* Buffer resource. */
2740 if (texture->target == PIPE_BUFFER) {
2741 unsigned stride, num_records;
2742
2743 desc = util_format_description(state->format);
2744 first_non_void = util_format_get_first_non_void_channel(state->format);
2745 stride = desc->block.bits / 8;
2746 va = tmp->resource.gpu_address + state->u.buf.first_element*stride;
2747 format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
2748 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
2749
2750 num_records = state->u.buf.last_element + 1 - state->u.buf.first_element;
2751 num_records = MIN2(num_records, texture->width0 / stride);
2752
2753 if (sctx->b.chip_class >= VI)
2754 num_records *= stride;
2755
2756 view->state[4] = va;
2757 view->state[5] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
2758 S_008F04_STRIDE(stride);
2759 view->state[6] = num_records;
2760 view->state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2761 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2762 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2763 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2764 S_008F0C_NUM_FORMAT(num_format) |
2765 S_008F0C_DATA_FORMAT(format);
2766
2767 LIST_ADDTAIL(&view->list, &sctx->b.texture_buffers);
2768 return &view->base;
2769 }
2770
2771 state_swizzle[0] = state->swizzle_r;
2772 state_swizzle[1] = state->swizzle_g;
2773 state_swizzle[2] = state->swizzle_b;
2774 state_swizzle[3] = state->swizzle_a;
2775
2776 surflevel = tmp->surface.level;
2777
2778 /* Texturing with separate depth and stencil. */
2779 if (tmp->is_depth && !tmp->is_flushing_texture) {
2780 switch (pipe_format) {
2781 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2782 pipe_format = PIPE_FORMAT_Z32_FLOAT;
2783 break;
2784 case PIPE_FORMAT_X8Z24_UNORM:
2785 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2786 /* Z24 is always stored like this. */
2787 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
2788 break;
2789 case PIPE_FORMAT_X24S8_UINT:
2790 case PIPE_FORMAT_S8X24_UINT:
2791 case PIPE_FORMAT_X32_S8X24_UINT:
2792 pipe_format = PIPE_FORMAT_S8_UINT;
2793 surflevel = tmp->surface.stencil_level;
2794 break;
2795 default:;
2796 }
2797 }
2798
2799 desc = util_format_description(pipe_format);
2800
2801 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2802 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2803 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2804
2805 switch (pipe_format) {
2806 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2807 case PIPE_FORMAT_X24S8_UINT:
2808 case PIPE_FORMAT_X32_S8X24_UINT:
2809 case PIPE_FORMAT_X8Z24_UNORM:
2810 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
2811 break;
2812 default:
2813 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
2814 }
2815 } else {
2816 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2817 }
2818
2819 first_non_void = util_format_get_first_non_void_channel(pipe_format);
2820
2821 switch (pipe_format) {
2822 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2823 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2824 break;
2825 default:
2826 if (first_non_void < 0) {
2827 if (util_format_is_compressed(pipe_format)) {
2828 switch (pipe_format) {
2829 case PIPE_FORMAT_DXT1_SRGB:
2830 case PIPE_FORMAT_DXT1_SRGBA:
2831 case PIPE_FORMAT_DXT3_SRGBA:
2832 case PIPE_FORMAT_DXT5_SRGBA:
2833 case PIPE_FORMAT_BPTC_SRGBA:
2834 case PIPE_FORMAT_ETC2_SRGB8:
2835 case PIPE_FORMAT_ETC2_SRGB8A1:
2836 case PIPE_FORMAT_ETC2_SRGBA8:
2837 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2838 break;
2839 case PIPE_FORMAT_RGTC1_SNORM:
2840 case PIPE_FORMAT_LATC1_SNORM:
2841 case PIPE_FORMAT_RGTC2_SNORM:
2842 case PIPE_FORMAT_LATC2_SNORM:
2843 case PIPE_FORMAT_ETC2_R11_SNORM:
2844 case PIPE_FORMAT_ETC2_RG11_SNORM:
2845 /* implies float, so use SNORM/UNORM to determine
2846 whether data is signed or not */
2847 case PIPE_FORMAT_BPTC_RGB_FLOAT:
2848 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2849 break;
2850 default:
2851 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2852 break;
2853 }
2854 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
2855 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2856 } else {
2857 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2858 }
2859 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
2860 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2861 } else {
2862 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2863
2864 switch (desc->channel[first_non_void].type) {
2865 case UTIL_FORMAT_TYPE_FLOAT:
2866 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2867 break;
2868 case UTIL_FORMAT_TYPE_SIGNED:
2869 if (desc->channel[first_non_void].normalized)
2870 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2871 else if (desc->channel[first_non_void].pure_integer)
2872 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
2873 else
2874 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
2875 break;
2876 case UTIL_FORMAT_TYPE_UNSIGNED:
2877 if (desc->channel[first_non_void].normalized)
2878 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2879 else if (desc->channel[first_non_void].pure_integer)
2880 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
2881 else
2882 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
2883 }
2884 }
2885 }
2886
2887 format = si_translate_texformat(ctx->screen, pipe_format, desc, first_non_void);
2888 if (format == ~0) {
2889 format = 0;
2890 }
2891
2892 base_level = 0;
2893 first_level = state->u.tex.first_level;
2894 last_level = state->u.tex.last_level;
2895 width = width0;
2896 height = height0;
2897 depth = texture->depth0;
2898
2899 if (force_level) {
2900 assert(force_level == first_level &&
2901 force_level == last_level);
2902 base_level = force_level;
2903 first_level = 0;
2904 last_level = 0;
2905 width = u_minify(width, force_level);
2906 height = u_minify(height, force_level);
2907 depth = u_minify(depth, force_level);
2908 }
2909
2910 pitch = surflevel[base_level].nblk_x * util_format_get_blockwidth(pipe_format);
2911
2912 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
2913 height = 1;
2914 depth = texture->array_size;
2915 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
2916 depth = texture->array_size;
2917 } else if (texture->target == PIPE_TEXTURE_CUBE_ARRAY)
2918 depth = texture->array_size / 6;
2919
2920 /* This is not needed if state trackers set last_layer correctly. */
2921 if (state->target == PIPE_TEXTURE_1D ||
2922 state->target == PIPE_TEXTURE_2D ||
2923 state->target == PIPE_TEXTURE_RECT ||
2924 state->target == PIPE_TEXTURE_CUBE)
2925 last_layer = state->u.tex.first_layer;
2926
2927 va = tmp->resource.gpu_address + surflevel[base_level].offset;
2928
2929 view->state[0] = va >> 8;
2930 view->state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) |
2931 S_008F14_DATA_FORMAT(format) |
2932 S_008F14_NUM_FORMAT(num_format));
2933 view->state[2] = (S_008F18_WIDTH(width - 1) |
2934 S_008F18_HEIGHT(height - 1));
2935 view->state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2936 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2937 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2938 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2939 S_008F1C_BASE_LEVEL(texture->nr_samples > 1 ?
2940 0 : first_level) |
2941 S_008F1C_LAST_LEVEL(texture->nr_samples > 1 ?
2942 util_logbase2(texture->nr_samples) :
2943 last_level) |
2944 S_008F1C_TILING_INDEX(si_tile_mode_index(tmp, base_level, false)) |
2945 S_008F1C_POW2_PAD(texture->last_level > 0) |
2946 S_008F1C_TYPE(si_tex_dim(texture->target, state->target,
2947 texture->nr_samples)));
2948 view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
2949 view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2950 S_008F24_LAST_ARRAY(last_layer));
2951
2952 if (tmp->dcc_buffer) {
2953 uint64_t dcc_offset = surflevel[base_level].dcc_offset;
2954 unsigned swap = r600_translate_colorswap(pipe_format);
2955
2956 view->state[6] = S_008F28_COMPRESSION_EN(1) | S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
2957 view->state[7] = (tmp->dcc_buffer->gpu_address + dcc_offset) >> 8;
2958 view->dcc_buffer = tmp->dcc_buffer;
2959 } else {
2960 view->state[6] = 0;
2961 view->state[7] = 0;
2962 }
2963
2964 /* Initialize the sampler view for FMASK. */
2965 if (tmp->fmask.size) {
2966 uint64_t va = tmp->resource.gpu_address + tmp->fmask.offset;
2967 uint32_t fmask_format;
2968
2969 switch (texture->nr_samples) {
2970 case 2:
2971 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
2972 break;
2973 case 4:
2974 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
2975 break;
2976 case 8:
2977 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
2978 break;
2979 default:
2980 assert(0);
2981 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
2982 }
2983
2984 view->fmask_state[0] = va >> 8;
2985 view->fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
2986 S_008F14_DATA_FORMAT(fmask_format) |
2987 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT);
2988 view->fmask_state[2] = S_008F18_WIDTH(width - 1) |
2989 S_008F18_HEIGHT(height - 1);
2990 view->fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
2991 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
2992 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
2993 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
2994 S_008F1C_TILING_INDEX(tmp->fmask.tile_mode_index) |
2995 S_008F1C_TYPE(si_tex_dim(texture->target,
2996 state->target, 0));
2997 view->fmask_state[4] = S_008F20_DEPTH(depth - 1) |
2998 S_008F20_PITCH(tmp->fmask.pitch_in_pixels - 1);
2999 view->fmask_state[5] = S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
3000 S_008F24_LAST_ARRAY(last_layer);
3001 view->fmask_state[6] = 0;
3002 view->fmask_state[7] = 0;
3003 }
3004
3005 return &view->base;
3006 }
3007
3008 static struct pipe_sampler_view *
3009 si_create_sampler_view(struct pipe_context *ctx,
3010 struct pipe_resource *texture,
3011 const struct pipe_sampler_view *state)
3012 {
3013 return si_create_sampler_view_custom(ctx, texture, state,
3014 texture ? texture->width0 : 0,
3015 texture ? texture->height0 : 0, 0);
3016 }
3017
3018 static void si_sampler_view_destroy(struct pipe_context *ctx,
3019 struct pipe_sampler_view *state)
3020 {
3021 struct si_sampler_view *view = (struct si_sampler_view *)state;
3022
3023 if (view->resource && view->resource->b.b.target == PIPE_BUFFER)
3024 LIST_DELINIT(&view->list);
3025
3026 pipe_resource_reference(&state->texture, NULL);
3027 FREE(view);
3028 }
3029
3030 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
3031 {
3032 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
3033 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
3034 (linear_filter &&
3035 (wrap == PIPE_TEX_WRAP_CLAMP ||
3036 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
3037 }
3038
3039 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
3040 {
3041 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
3042 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
3043
3044 return (state->border_color.ui[0] || state->border_color.ui[1] ||
3045 state->border_color.ui[2] || state->border_color.ui[3]) &&
3046 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
3047 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
3048 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
3049 }
3050
3051 static void *si_create_sampler_state(struct pipe_context *ctx,
3052 const struct pipe_sampler_state *state)
3053 {
3054 struct si_context *sctx = (struct si_context *)ctx;
3055 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
3056 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
3057 unsigned border_color_type, border_color_index = 0;
3058
3059 if (!rstate) {
3060 return NULL;
3061 }
3062
3063 if (!sampler_state_needs_border_color(state))
3064 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3065 else if (state->border_color.f[0] == 0 &&
3066 state->border_color.f[1] == 0 &&
3067 state->border_color.f[2] == 0 &&
3068 state->border_color.f[3] == 0)
3069 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3070 else if (state->border_color.f[0] == 0 &&
3071 state->border_color.f[1] == 0 &&
3072 state->border_color.f[2] == 0 &&
3073 state->border_color.f[3] == 1)
3074 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3075 else if (state->border_color.f[0] == 1 &&
3076 state->border_color.f[1] == 1 &&
3077 state->border_color.f[2] == 1 &&
3078 state->border_color.f[3] == 1)
3079 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3080 else {
3081 int i;
3082
3083 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
3084
3085 /* Check if the border has been uploaded already. */
3086 for (i = 0; i < sctx->border_color_count; i++)
3087 if (memcmp(&sctx->border_color_table[i], &state->border_color,
3088 sizeof(state->border_color)) == 0)
3089 break;
3090
3091 if (i >= SI_MAX_BORDER_COLORS) {
3092 /* Getting 4096 unique border colors is very unlikely. */
3093 fprintf(stderr, "radeonsi: The border color table is full. "
3094 "Any new border colors will be just black. "
3095 "Please file a bug.\n");
3096 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3097 } else {
3098 if (i == sctx->border_color_count) {
3099 /* Upload a new border color. */
3100 memcpy(&sctx->border_color_table[i], &state->border_color,
3101 sizeof(state->border_color));
3102 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
3103 &state->border_color,
3104 sizeof(state->border_color));
3105 sctx->border_color_count++;
3106 }
3107
3108 border_color_index = i;
3109 }
3110 }
3111
3112 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
3113 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
3114 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
3115 r600_tex_aniso_filter(state->max_anisotropy) << 9 |
3116 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
3117 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
3118 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map));
3119 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
3120 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
3121 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
3122 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
3123 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter) | aniso_flag_offset) |
3124 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)));
3125 rstate->val[3] = S_008F3C_BORDER_COLOR_PTR(border_color_index) |
3126 S_008F3C_BORDER_COLOR_TYPE(border_color_type);
3127 return rstate;
3128 }
3129
3130 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
3131 {
3132 struct si_context *sctx = (struct si_context *)ctx;
3133
3134 if (sctx->sample_mask.sample_mask == (uint16_t)sample_mask)
3135 return;
3136
3137 sctx->sample_mask.sample_mask = sample_mask;
3138 si_mark_atom_dirty(sctx, &sctx->sample_mask.atom);
3139 }
3140
3141 static void si_emit_sample_mask(struct si_context *sctx, struct r600_atom *atom)
3142 {
3143 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
3144 unsigned mask = sctx->sample_mask.sample_mask;
3145
3146 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3147 radeon_emit(cs, mask | (mask << 16));
3148 radeon_emit(cs, mask | (mask << 16));
3149 }
3150
3151 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
3152 {
3153 free(state);
3154 }
3155
3156 /*
3157 * Vertex elements & buffers
3158 */
3159
3160 static void *si_create_vertex_elements(struct pipe_context *ctx,
3161 unsigned count,
3162 const struct pipe_vertex_element *elements)
3163 {
3164 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
3165 int i;
3166
3167 assert(count < SI_MAX_ATTRIBS);
3168 if (!v)
3169 return NULL;
3170
3171 v->count = count;
3172 for (i = 0; i < count; ++i) {
3173 const struct util_format_description *desc;
3174 unsigned data_format, num_format;
3175 int first_non_void;
3176
3177 desc = util_format_description(elements[i].src_format);
3178 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
3179 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
3180 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
3181
3182 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3183 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3184 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3185 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
3186 S_008F0C_NUM_FORMAT(num_format) |
3187 S_008F0C_DATA_FORMAT(data_format);
3188 v->format_size[i] = desc->block.bits / 8;
3189 }
3190 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
3191
3192 return v;
3193 }
3194
3195 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
3196 {
3197 struct si_context *sctx = (struct si_context *)ctx;
3198 struct si_vertex_element *v = (struct si_vertex_element*)state;
3199
3200 sctx->vertex_elements = v;
3201 sctx->vertex_buffers_dirty = true;
3202 }
3203
3204 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
3205 {
3206 struct si_context *sctx = (struct si_context *)ctx;
3207
3208 if (sctx->vertex_elements == state)
3209 sctx->vertex_elements = NULL;
3210 FREE(state);
3211 }
3212
3213 static void si_set_vertex_buffers(struct pipe_context *ctx,
3214 unsigned start_slot, unsigned count,
3215 const struct pipe_vertex_buffer *buffers)
3216 {
3217 struct si_context *sctx = (struct si_context *)ctx;
3218 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
3219 int i;
3220
3221 assert(start_slot + count <= Elements(sctx->vertex_buffer));
3222
3223 if (buffers) {
3224 for (i = 0; i < count; i++) {
3225 const struct pipe_vertex_buffer *src = buffers + i;
3226 struct pipe_vertex_buffer *dsti = dst + i;
3227
3228 pipe_resource_reference(&dsti->buffer, src->buffer);
3229 dsti->buffer_offset = src->buffer_offset;
3230 dsti->stride = src->stride;
3231 r600_context_add_resource_size(ctx, src->buffer);
3232 }
3233 } else {
3234 for (i = 0; i < count; i++) {
3235 pipe_resource_reference(&dst[i].buffer, NULL);
3236 }
3237 }
3238 sctx->vertex_buffers_dirty = true;
3239 }
3240
3241 static void si_set_index_buffer(struct pipe_context *ctx,
3242 const struct pipe_index_buffer *ib)
3243 {
3244 struct si_context *sctx = (struct si_context *)ctx;
3245
3246 if (ib) {
3247 pipe_resource_reference(&sctx->index_buffer.buffer, ib->buffer);
3248 memcpy(&sctx->index_buffer, ib, sizeof(*ib));
3249 r600_context_add_resource_size(ctx, ib->buffer);
3250 } else {
3251 pipe_resource_reference(&sctx->index_buffer.buffer, NULL);
3252 }
3253 }
3254
3255 /*
3256 * Misc
3257 */
3258 static void si_set_polygon_stipple(struct pipe_context *ctx,
3259 const struct pipe_poly_stipple *state)
3260 {
3261 struct si_context *sctx = (struct si_context *)ctx;
3262 struct pipe_resource *tex;
3263 struct pipe_sampler_view *view;
3264 bool is_zero = true;
3265 bool is_one = true;
3266 int i;
3267
3268 /* The hardware obeys 0 and 1 swizzles in the descriptor even if
3269 * the resource is NULL/invalid. Take advantage of this fact and skip
3270 * texture allocation if the stipple pattern is constant.
3271 *
3272 * This is an optimization for the common case when stippling isn't
3273 * used but set_polygon_stipple is still called by st/mesa.
3274 */
3275 for (i = 0; i < Elements(state->stipple); i++) {
3276 is_zero = is_zero && state->stipple[i] == 0;
3277 is_one = is_one && state->stipple[i] == 0xffffffff;
3278 }
3279
3280 if (is_zero || is_one) {
3281 struct pipe_sampler_view templ = {{0}};
3282
3283 templ.swizzle_r = PIPE_SWIZZLE_ZERO;
3284 templ.swizzle_g = PIPE_SWIZZLE_ZERO;
3285 templ.swizzle_b = PIPE_SWIZZLE_ZERO;
3286 /* The pattern should be inverted in the texture. */
3287 templ.swizzle_a = is_zero ? PIPE_SWIZZLE_ONE : PIPE_SWIZZLE_ZERO;
3288
3289 view = ctx->create_sampler_view(ctx, NULL, &templ);
3290 } else {
3291 /* Create a new texture. */
3292 tex = util_pstipple_create_stipple_texture(ctx, state->stipple);
3293 if (!tex)
3294 return;
3295
3296 view = util_pstipple_create_sampler_view(ctx, tex);
3297 pipe_resource_reference(&tex, NULL);
3298 }
3299
3300 ctx->set_sampler_views(ctx, PIPE_SHADER_FRAGMENT,
3301 SI_POLY_STIPPLE_SAMPLER, 1, &view);
3302 pipe_sampler_view_reference(&view, NULL);
3303
3304 /* Bind the sampler state if needed. */
3305 if (!sctx->pstipple_sampler_state) {
3306 sctx->pstipple_sampler_state = util_pstipple_create_sampler(ctx);
3307 ctx->bind_sampler_states(ctx, PIPE_SHADER_FRAGMENT,
3308 SI_POLY_STIPPLE_SAMPLER, 1,
3309 &sctx->pstipple_sampler_state);
3310 }
3311 }
3312
3313 static void si_set_tess_state(struct pipe_context *ctx,
3314 const float default_outer_level[4],
3315 const float default_inner_level[2])
3316 {
3317 struct si_context *sctx = (struct si_context *)ctx;
3318 struct pipe_constant_buffer cb;
3319 float array[8];
3320
3321 memcpy(array, default_outer_level, sizeof(float) * 4);
3322 memcpy(array+4, default_inner_level, sizeof(float) * 2);
3323
3324 cb.buffer = NULL;
3325 cb.user_buffer = NULL;
3326 cb.buffer_size = sizeof(array);
3327
3328 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
3329 (void*)array, sizeof(array),
3330 &cb.buffer_offset);
3331
3332 ctx->set_constant_buffer(ctx, PIPE_SHADER_TESS_CTRL,
3333 SI_DRIVER_STATE_CONST_BUF, &cb);
3334 pipe_resource_reference(&cb.buffer, NULL);
3335 }
3336
3337 static void si_texture_barrier(struct pipe_context *ctx)
3338 {
3339 struct si_context *sctx = (struct si_context *)ctx;
3340
3341 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
3342 SI_CONTEXT_INV_GLOBAL_L2 |
3343 SI_CONTEXT_FLUSH_AND_INV_CB;
3344 }
3345
3346 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
3347 {
3348 struct pipe_blend_state blend;
3349
3350 memset(&blend, 0, sizeof(blend));
3351 blend.independent_blend_enable = true;
3352 blend.rt[0].colormask = 0xf;
3353 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
3354 }
3355
3356 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
3357 bool include_draw_vbo)
3358 {
3359 si_need_cs_space((struct si_context*)ctx);
3360 }
3361
3362 static void si_init_config(struct si_context *sctx);
3363
3364 void si_init_state_functions(struct si_context *sctx)
3365 {
3366 si_init_external_atom(sctx, &sctx->b.render_cond_atom, &sctx->atoms.s.render_cond);
3367 si_init_external_atom(sctx, &sctx->b.streamout.begin_atom, &sctx->atoms.s.streamout_begin);
3368 si_init_external_atom(sctx, &sctx->b.streamout.enable_atom, &sctx->atoms.s.streamout_enable);
3369
3370 si_init_atom(sctx, &sctx->cache_flush, &sctx->atoms.s.cache_flush, si_emit_cache_flush);
3371 si_init_atom(sctx, &sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state);
3372 si_init_atom(sctx, &sctx->msaa_sample_locs, &sctx->atoms.s.msaa_sample_locs, si_emit_msaa_sample_locs);
3373 si_init_atom(sctx, &sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state);
3374 si_init_atom(sctx, &sctx->msaa_config, &sctx->atoms.s.msaa_config, si_emit_msaa_config);
3375 si_init_atom(sctx, &sctx->sample_mask.atom, &sctx->atoms.s.sample_mask, si_emit_sample_mask);
3376 si_init_atom(sctx, &sctx->cb_target_mask, &sctx->atoms.s.cb_target_mask, si_emit_cb_target_mask);
3377 si_init_atom(sctx, &sctx->blend_color.atom, &sctx->atoms.s.blend_color, si_emit_blend_color);
3378 si_init_atom(sctx, &sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs);
3379 si_init_atom(sctx, &sctx->clip_state.atom, &sctx->atoms.s.clip_state, si_emit_clip_state);
3380 si_init_atom(sctx, &sctx->scissors.atom, &sctx->atoms.s.scissors, si_emit_scissors);
3381 si_init_atom(sctx, &sctx->viewports.atom, &sctx->atoms.s.viewports, si_emit_viewports);
3382 si_init_atom(sctx, &sctx->stencil_ref.atom, &sctx->atoms.s.stencil_ref, si_emit_stencil_ref);
3383
3384 sctx->b.b.create_blend_state = si_create_blend_state;
3385 sctx->b.b.bind_blend_state = si_bind_blend_state;
3386 sctx->b.b.delete_blend_state = si_delete_blend_state;
3387 sctx->b.b.set_blend_color = si_set_blend_color;
3388
3389 sctx->b.b.create_rasterizer_state = si_create_rs_state;
3390 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
3391 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
3392
3393 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
3394 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
3395 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
3396
3397 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
3398 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
3399 sctx->custom_blend_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
3400 sctx->custom_blend_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
3401
3402 sctx->b.b.set_clip_state = si_set_clip_state;
3403 sctx->b.b.set_scissor_states = si_set_scissor_states;
3404 sctx->b.b.set_viewport_states = si_set_viewport_states;
3405 sctx->b.b.set_stencil_ref = si_set_stencil_ref;
3406
3407 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
3408 sctx->b.b.get_sample_position = cayman_get_sample_position;
3409
3410 sctx->b.b.create_sampler_state = si_create_sampler_state;
3411 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
3412
3413 sctx->b.b.create_sampler_view = si_create_sampler_view;
3414 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
3415
3416 sctx->b.b.set_sample_mask = si_set_sample_mask;
3417
3418 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
3419 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
3420 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
3421 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
3422 sctx->b.b.set_index_buffer = si_set_index_buffer;
3423
3424 sctx->b.b.texture_barrier = si_texture_barrier;
3425 sctx->b.b.set_polygon_stipple = si_set_polygon_stipple;
3426 sctx->b.b.set_min_samples = si_set_min_samples;
3427 sctx->b.b.set_tess_state = si_set_tess_state;
3428
3429 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
3430 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
3431
3432 sctx->b.b.draw_vbo = si_draw_vbo;
3433
3434 if (sctx->b.chip_class >= CIK) {
3435 sctx->b.dma_copy = cik_sdma_copy;
3436 } else {
3437 sctx->b.dma_copy = si_dma_copy;
3438 }
3439
3440 si_init_config(sctx);
3441 }
3442
3443 static void
3444 si_write_harvested_raster_configs(struct si_context *sctx,
3445 struct si_pm4_state *pm4,
3446 unsigned raster_config,
3447 unsigned raster_config_1)
3448 {
3449 unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1);
3450 unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1);
3451 unsigned rb_mask = sctx->screen->b.info.si_backend_enabled_mask;
3452 unsigned num_rb = MIN2(sctx->screen->b.info.r600_num_backends, 16);
3453 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
3454 unsigned rb_per_se = num_rb / num_se;
3455 unsigned se_mask[4];
3456 unsigned se;
3457
3458 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
3459 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
3460 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
3461 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
3462
3463 assert(num_se == 1 || num_se == 2 || num_se == 4);
3464 assert(sh_per_se == 1 || sh_per_se == 2);
3465 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
3466
3467 /* XXX: I can't figure out what the *_XSEL and *_YSEL
3468 * fields are for, so I'm leaving them as their default
3469 * values. */
3470
3471 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
3472 (!se_mask[2] && !se_mask[3]))) {
3473 raster_config_1 &= C_028354_SE_PAIR_MAP;
3474
3475 if (!se_mask[0] && !se_mask[1]) {
3476 raster_config_1 |=
3477 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
3478 } else {
3479 raster_config_1 |=
3480 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
3481 }
3482 }
3483
3484 for (se = 0; se < num_se; se++) {
3485 unsigned raster_config_se = raster_config;
3486 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
3487 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
3488 int idx = (se / 2) * 2;
3489
3490 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
3491 raster_config_se &= C_028350_SE_MAP;
3492
3493 if (!se_mask[idx]) {
3494 raster_config_se |=
3495 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
3496 } else {
3497 raster_config_se |=
3498 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
3499 }
3500 }
3501
3502 pkr0_mask &= rb_mask;
3503 pkr1_mask &= rb_mask;
3504 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
3505 raster_config_se &= C_028350_PKR_MAP;
3506
3507 if (!pkr0_mask) {
3508 raster_config_se |=
3509 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
3510 } else {
3511 raster_config_se |=
3512 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
3513 }
3514 }
3515
3516 if (rb_per_se >= 2) {
3517 unsigned rb0_mask = 1 << (se * rb_per_se);
3518 unsigned rb1_mask = rb0_mask << 1;
3519
3520 rb0_mask &= rb_mask;
3521 rb1_mask &= rb_mask;
3522 if (!rb0_mask || !rb1_mask) {
3523 raster_config_se &= C_028350_RB_MAP_PKR0;
3524
3525 if (!rb0_mask) {
3526 raster_config_se |=
3527 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
3528 } else {
3529 raster_config_se |=
3530 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
3531 }
3532 }
3533
3534 if (rb_per_se > 2) {
3535 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
3536 rb1_mask = rb0_mask << 1;
3537 rb0_mask &= rb_mask;
3538 rb1_mask &= rb_mask;
3539 if (!rb0_mask || !rb1_mask) {
3540 raster_config_se &= C_028350_RB_MAP_PKR1;
3541
3542 if (!rb0_mask) {
3543 raster_config_se |=
3544 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
3545 } else {
3546 raster_config_se |=
3547 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
3548 }
3549 }
3550 }
3551 }
3552
3553 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
3554 if (sctx->b.chip_class < CIK)
3555 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3556 SE_INDEX(se) | SH_BROADCAST_WRITES |
3557 INSTANCE_BROADCAST_WRITES);
3558 else
3559 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
3560 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
3561 S_030800_INSTANCE_BROADCAST_WRITES(1));
3562 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
3563 if (sctx->b.chip_class >= CIK)
3564 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
3565 }
3566
3567 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
3568 if (sctx->b.chip_class < CIK)
3569 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3570 SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
3571 INSTANCE_BROADCAST_WRITES);
3572 else
3573 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
3574 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
3575 S_030800_INSTANCE_BROADCAST_WRITES(1));
3576 }
3577
3578 static void si_init_config(struct si_context *sctx)
3579 {
3580 struct si_screen *sscreen = sctx->screen;
3581 unsigned num_rb = MIN2(sctx->screen->b.info.r600_num_backends, 16);
3582 unsigned rb_mask = sctx->screen->b.info.si_backend_enabled_mask;
3583 unsigned raster_config, raster_config_1;
3584 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
3585 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3586 int i;
3587
3588 if (!pm4)
3589 return;
3590
3591 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
3592 si_pm4_cmd_add(pm4, 0x80000000);
3593 si_pm4_cmd_add(pm4, 0x80000000);
3594 si_pm4_cmd_end(pm4, false);
3595
3596 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
3597 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
3598
3599 /* FIXME calculate these values somehow ??? */
3600 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
3601 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
3602 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
3603
3604 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
3605 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3606
3607 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
3608 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
3609 if (sctx->b.chip_class < CIK)
3610 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
3611 S_008A14_CLIP_VTX_REORDER_ENA(1));
3612
3613 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
3614 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
3615
3616 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
3617
3618 for (i = 0; i < 16; i++) {
3619 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0);
3620 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0));
3621 }
3622
3623 switch (sctx->screen->b.family) {
3624 case CHIP_TAHITI:
3625 case CHIP_PITCAIRN:
3626 raster_config = 0x2a00126a;
3627 raster_config_1 = 0x00000000;
3628 break;
3629 case CHIP_VERDE:
3630 raster_config = 0x0000124a;
3631 raster_config_1 = 0x00000000;
3632 break;
3633 case CHIP_OLAND:
3634 raster_config = 0x00000082;
3635 raster_config_1 = 0x00000000;
3636 break;
3637 case CHIP_HAINAN:
3638 raster_config = 0x00000000;
3639 raster_config_1 = 0x00000000;
3640 break;
3641 case CHIP_BONAIRE:
3642 raster_config = 0x16000012;
3643 raster_config_1 = 0x00000000;
3644 break;
3645 case CHIP_HAWAII:
3646 raster_config = 0x3a00161a;
3647 raster_config_1 = 0x0000002e;
3648 break;
3649 case CHIP_FIJI:
3650 if (sscreen->b.info.cik_macrotile_mode_array[0] == 0x000000e8) {
3651 /* old kernels with old tiling config */
3652 raster_config = 0x16000012;
3653 raster_config_1 = 0x0000002a;
3654 } else {
3655 raster_config = 0x3a00161a;
3656 raster_config_1 = 0x0000002e;
3657 }
3658 break;
3659 case CHIP_TONGA:
3660 raster_config = 0x16000012;
3661 raster_config_1 = 0x0000002a;
3662 break;
3663 case CHIP_ICELAND:
3664 raster_config = 0x00000002;
3665 raster_config_1 = 0x00000000;
3666 break;
3667 case CHIP_CARRIZO:
3668 raster_config = 0x00000002;
3669 raster_config_1 = 0x00000000;
3670 break;
3671 case CHIP_KAVERI:
3672 /* KV should be 0x00000002, but that causes problems with radeon */
3673 raster_config = 0x00000000; /* 0x00000002 */
3674 raster_config_1 = 0x00000000;
3675 break;
3676 case CHIP_KABINI:
3677 case CHIP_MULLINS:
3678 case CHIP_STONEY:
3679 raster_config = 0x00000000;
3680 raster_config_1 = 0x00000000;
3681 break;
3682 default:
3683 fprintf(stderr,
3684 "radeonsi: Unknown GPU, using 0 for raster_config\n");
3685 raster_config = 0x00000000;
3686 raster_config_1 = 0x00000000;
3687 break;
3688 }
3689
3690 /* Always use the default config when all backends are enabled
3691 * (or when we failed to determine the enabled backends).
3692 */
3693 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
3694 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
3695 raster_config);
3696 if (sctx->b.chip_class >= CIK)
3697 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
3698 raster_config_1);
3699 } else {
3700 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
3701 }
3702
3703 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
3704 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
3705 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
3706 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
3707 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
3708 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
3709 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
3710
3711 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
3712 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
3713 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
3714 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
3715 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
3716 si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, fui(1.0));
3717 si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, fui(1.0));
3718 si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, fui(1.0));
3719 si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, fui(1.0));
3720 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
3721 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
3722 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
3723 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE,
3724 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3725 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
3726
3727 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
3728 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
3729 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
3730
3731 if (sctx->b.chip_class >= CIK) {
3732 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff));
3733 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
3734 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xffff));
3735 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
3736 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
3737 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(0));
3738 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
3739 }
3740
3741 if (sctx->b.chip_class >= VI) {
3742 si_pm4_set_reg(pm4, R_028424_CB_DCC_CONTROL,
3743 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
3744 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
3745 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
3746 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
3747 }
3748
3749 if (sctx->b.family == CHIP_STONEY)
3750 si_pm4_set_reg(pm4, R_028C40_PA_SC_SHADER_CONTROL, 0);
3751
3752 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
3753 if (sctx->b.chip_class >= CIK)
3754 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, border_color_va >> 40);
3755 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
3756 RADEON_PRIO_BORDER_COLORS);
3757
3758 si_pm4_upload_indirect_buffer(sctx, pm4);
3759 sctx->init_config = pm4;
3760 }