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gallium: change pipe_sampler_view::first_element/last_element -> offset/size
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "si_shader.h"
29 #include "sid.h"
30 #include "radeon/r600_cs.h"
31
32 #include "util/u_dual_blend.h"
33 #include "util/u_format.h"
34 #include "util/u_format_s3tc.h"
35 #include "util/u_memory.h"
36 #include "util/u_pstipple.h"
37 #include "util/u_resource.h"
38
39 /* Initialize an external atom (owned by ../radeon). */
40 static void
41 si_init_external_atom(struct si_context *sctx, struct r600_atom *atom,
42 struct r600_atom **list_elem)
43 {
44 atom->id = list_elem - sctx->atoms.array + 1;
45 *list_elem = atom;
46 }
47
48 /* Initialize an atom owned by radeonsi. */
49 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
50 struct r600_atom **list_elem,
51 void (*emit_func)(struct si_context *ctx, struct r600_atom *state))
52 {
53 atom->emit = (void*)emit_func;
54 atom->id = list_elem - sctx->atoms.array + 1; /* index+1 in the atom array */
55 *list_elem = atom;
56 }
57
58 static unsigned si_map_swizzle(unsigned swizzle)
59 {
60 switch (swizzle) {
61 case PIPE_SWIZZLE_Y:
62 return V_008F0C_SQ_SEL_Y;
63 case PIPE_SWIZZLE_Z:
64 return V_008F0C_SQ_SEL_Z;
65 case PIPE_SWIZZLE_W:
66 return V_008F0C_SQ_SEL_W;
67 case PIPE_SWIZZLE_0:
68 return V_008F0C_SQ_SEL_0;
69 case PIPE_SWIZZLE_1:
70 return V_008F0C_SQ_SEL_1;
71 default: /* PIPE_SWIZZLE_X */
72 return V_008F0C_SQ_SEL_X;
73 }
74 }
75
76 static uint32_t S_FIXED(float value, uint32_t frac_bits)
77 {
78 return value * (1 << frac_bits);
79 }
80
81 /* 12.4 fixed-point */
82 static unsigned si_pack_float_12p4(float x)
83 {
84 return x <= 0 ? 0 :
85 x >= 4096 ? 0xffff : x * 16;
86 }
87
88 /*
89 * Inferred framebuffer and blender state.
90 *
91 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
92 * if there is not enough PS outputs.
93 */
94 static void si_emit_cb_render_state(struct si_context *sctx, struct r600_atom *atom)
95 {
96 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
97 struct si_state_blend *blend = sctx->queued.named.blend;
98 uint32_t cb_target_mask, i;
99
100 /* CB_COLORn_INFO.FORMAT=INVALID disables empty colorbuffer slots. */
101 if (blend)
102 cb_target_mask = blend->cb_target_mask;
103 else
104 cb_target_mask = 0xffffffff;
105
106 /* Avoid a hang that happens when dual source blending is enabled
107 * but there is not enough color outputs. This is undefined behavior,
108 * so disable color writes completely.
109 *
110 * Reproducible with Unigine Heaven 4.0 and drirc missing.
111 */
112 if (blend && blend->dual_src_blend &&
113 sctx->ps_shader.cso &&
114 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
115 cb_target_mask = 0;
116
117 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, cb_target_mask);
118
119 /* STONEY-specific register settings. */
120 if (sctx->b.family == CHIP_STONEY) {
121 unsigned spi_shader_col_format =
122 sctx->ps_shader.cso ?
123 sctx->ps_shader.current->key.ps.epilog.spi_shader_col_format : 0;
124 unsigned sx_ps_downconvert = 0;
125 unsigned sx_blend_opt_epsilon = 0;
126 unsigned sx_blend_opt_control = 0;
127
128 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
129 struct r600_surface *surf =
130 (struct r600_surface*)sctx->framebuffer.state.cbufs[i];
131 unsigned format, swap, spi_format, colormask;
132 bool has_alpha, has_rgb;
133
134 if (!surf)
135 continue;
136
137 format = G_028C70_FORMAT(surf->cb_color_info);
138 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
139 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
140 colormask = (cb_target_mask >> (i * 4)) & 0xf;
141
142 /* Set if RGB and A are present. */
143 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
144
145 if (format == V_028C70_COLOR_8 ||
146 format == V_028C70_COLOR_16 ||
147 format == V_028C70_COLOR_32)
148 has_rgb = !has_alpha;
149 else
150 has_rgb = true;
151
152 /* Check the colormask and export format. */
153 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
154 has_rgb = false;
155 if (!(colormask & PIPE_MASK_A))
156 has_alpha = false;
157
158 if (spi_format == V_028714_SPI_SHADER_ZERO) {
159 has_rgb = false;
160 has_alpha = false;
161 }
162
163 /* Disable value checking for disabled channels. */
164 if (!has_rgb)
165 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
166 if (!has_alpha)
167 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
168
169 /* Enable down-conversion for 32bpp and smaller formats. */
170 switch (format) {
171 case V_028C70_COLOR_8:
172 case V_028C70_COLOR_8_8:
173 case V_028C70_COLOR_8_8_8_8:
174 /* For 1 and 2-channel formats, use the superset thereof. */
175 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
176 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
177 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
178 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
179 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
180 }
181 break;
182
183 case V_028C70_COLOR_5_6_5:
184 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
185 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
186 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
187 }
188 break;
189
190 case V_028C70_COLOR_1_5_5_5:
191 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
192 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
193 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
194 }
195 break;
196
197 case V_028C70_COLOR_4_4_4_4:
198 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
199 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
200 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
201 }
202 break;
203
204 case V_028C70_COLOR_32:
205 if (swap == V_0280A0_SWAP_STD &&
206 spi_format == V_028714_SPI_SHADER_32_R)
207 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
208 else if (swap == V_0280A0_SWAP_ALT_REV &&
209 spi_format == V_028714_SPI_SHADER_32_AR)
210 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
211 break;
212
213 case V_028C70_COLOR_16:
214 case V_028C70_COLOR_16_16:
215 /* For 1-channel formats, use the superset thereof. */
216 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
217 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
218 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
219 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
220 if (swap == V_0280A0_SWAP_STD ||
221 swap == V_0280A0_SWAP_STD_REV)
222 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
223 else
224 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
225 }
226 break;
227
228 case V_028C70_COLOR_10_11_11:
229 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
230 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
231 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
232 }
233 break;
234
235 case V_028C70_COLOR_2_10_10_10:
236 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
237 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
238 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
239 }
240 break;
241 }
242 }
243
244 if (sctx->screen->b.debug_flags & DBG_NO_RB_PLUS) {
245 sx_ps_downconvert = 0;
246 sx_blend_opt_epsilon = 0;
247 sx_blend_opt_control = 0;
248 }
249
250 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
251 radeon_emit(cs, sx_ps_downconvert); /* R_028754_SX_PS_DOWNCONVERT */
252 radeon_emit(cs, sx_blend_opt_epsilon); /* R_028758_SX_BLEND_OPT_EPSILON */
253 radeon_emit(cs, sx_blend_opt_control); /* R_02875C_SX_BLEND_OPT_CONTROL */
254 }
255 }
256
257 /*
258 * Blender functions
259 */
260
261 static uint32_t si_translate_blend_function(int blend_func)
262 {
263 switch (blend_func) {
264 case PIPE_BLEND_ADD:
265 return V_028780_COMB_DST_PLUS_SRC;
266 case PIPE_BLEND_SUBTRACT:
267 return V_028780_COMB_SRC_MINUS_DST;
268 case PIPE_BLEND_REVERSE_SUBTRACT:
269 return V_028780_COMB_DST_MINUS_SRC;
270 case PIPE_BLEND_MIN:
271 return V_028780_COMB_MIN_DST_SRC;
272 case PIPE_BLEND_MAX:
273 return V_028780_COMB_MAX_DST_SRC;
274 default:
275 R600_ERR("Unknown blend function %d\n", blend_func);
276 assert(0);
277 break;
278 }
279 return 0;
280 }
281
282 static uint32_t si_translate_blend_factor(int blend_fact)
283 {
284 switch (blend_fact) {
285 case PIPE_BLENDFACTOR_ONE:
286 return V_028780_BLEND_ONE;
287 case PIPE_BLENDFACTOR_SRC_COLOR:
288 return V_028780_BLEND_SRC_COLOR;
289 case PIPE_BLENDFACTOR_SRC_ALPHA:
290 return V_028780_BLEND_SRC_ALPHA;
291 case PIPE_BLENDFACTOR_DST_ALPHA:
292 return V_028780_BLEND_DST_ALPHA;
293 case PIPE_BLENDFACTOR_DST_COLOR:
294 return V_028780_BLEND_DST_COLOR;
295 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
296 return V_028780_BLEND_SRC_ALPHA_SATURATE;
297 case PIPE_BLENDFACTOR_CONST_COLOR:
298 return V_028780_BLEND_CONSTANT_COLOR;
299 case PIPE_BLENDFACTOR_CONST_ALPHA:
300 return V_028780_BLEND_CONSTANT_ALPHA;
301 case PIPE_BLENDFACTOR_ZERO:
302 return V_028780_BLEND_ZERO;
303 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
304 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
305 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
306 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
307 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
308 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
309 case PIPE_BLENDFACTOR_INV_DST_COLOR:
310 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
311 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
312 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
313 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
314 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
315 case PIPE_BLENDFACTOR_SRC1_COLOR:
316 return V_028780_BLEND_SRC1_COLOR;
317 case PIPE_BLENDFACTOR_SRC1_ALPHA:
318 return V_028780_BLEND_SRC1_ALPHA;
319 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
320 return V_028780_BLEND_INV_SRC1_COLOR;
321 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
322 return V_028780_BLEND_INV_SRC1_ALPHA;
323 default:
324 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
325 assert(0);
326 break;
327 }
328 return 0;
329 }
330
331 static uint32_t si_translate_blend_opt_function(int blend_func)
332 {
333 switch (blend_func) {
334 case PIPE_BLEND_ADD:
335 return V_028760_OPT_COMB_ADD;
336 case PIPE_BLEND_SUBTRACT:
337 return V_028760_OPT_COMB_SUBTRACT;
338 case PIPE_BLEND_REVERSE_SUBTRACT:
339 return V_028760_OPT_COMB_REVSUBTRACT;
340 case PIPE_BLEND_MIN:
341 return V_028760_OPT_COMB_MIN;
342 case PIPE_BLEND_MAX:
343 return V_028760_OPT_COMB_MAX;
344 default:
345 return V_028760_OPT_COMB_BLEND_DISABLED;
346 }
347 }
348
349 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
350 {
351 switch (blend_fact) {
352 case PIPE_BLENDFACTOR_ZERO:
353 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
354 case PIPE_BLENDFACTOR_ONE:
355 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
356 case PIPE_BLENDFACTOR_SRC_COLOR:
357 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
358 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
359 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
360 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
361 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
362 case PIPE_BLENDFACTOR_SRC_ALPHA:
363 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
364 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
365 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
366 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
367 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
368 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
369 default:
370 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
371 }
372 }
373
374 /**
375 * Get rid of DST in the blend factors by commuting the operands:
376 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
377 */
378 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
379 unsigned *dst_factor, unsigned expected_dst,
380 unsigned replacement_src)
381 {
382 if (*src_factor == expected_dst &&
383 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
384 *src_factor = PIPE_BLENDFACTOR_ZERO;
385 *dst_factor = replacement_src;
386
387 /* Commuting the operands requires reversing subtractions. */
388 if (*func == PIPE_BLEND_SUBTRACT)
389 *func = PIPE_BLEND_REVERSE_SUBTRACT;
390 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
391 *func = PIPE_BLEND_SUBTRACT;
392 }
393 }
394
395 static bool si_blend_factor_uses_dst(unsigned factor)
396 {
397 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
398 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
399 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
400 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
401 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
402 }
403
404 static void *si_create_blend_state_mode(struct pipe_context *ctx,
405 const struct pipe_blend_state *state,
406 unsigned mode)
407 {
408 struct si_context *sctx = (struct si_context*)ctx;
409 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
410 struct si_pm4_state *pm4 = &blend->pm4;
411 uint32_t sx_mrt_blend_opt[8] = {0};
412 uint32_t color_control = 0;
413
414 if (!blend)
415 return NULL;
416
417 blend->alpha_to_coverage = state->alpha_to_coverage;
418 blend->alpha_to_one = state->alpha_to_one;
419 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
420
421 if (state->logicop_enable) {
422 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
423 } else {
424 color_control |= S_028808_ROP3(0xcc);
425 }
426
427 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
428 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
429 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
430 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
431 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
432 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
433
434 if (state->alpha_to_coverage)
435 blend->need_src_alpha_4bit |= 0xf;
436
437 blend->cb_target_mask = 0;
438 for (int i = 0; i < 8; i++) {
439 /* state->rt entries > 0 only written if independent blending */
440 const int j = state->independent_blend_enable ? i : 0;
441
442 unsigned eqRGB = state->rt[j].rgb_func;
443 unsigned srcRGB = state->rt[j].rgb_src_factor;
444 unsigned dstRGB = state->rt[j].rgb_dst_factor;
445 unsigned eqA = state->rt[j].alpha_func;
446 unsigned srcA = state->rt[j].alpha_src_factor;
447 unsigned dstA = state->rt[j].alpha_dst_factor;
448
449 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
450 unsigned blend_cntl = 0;
451
452 sx_mrt_blend_opt[i] =
453 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
454 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
455
456 /* Only set dual source blending for MRT0 to avoid a hang. */
457 if (i >= 1 && blend->dual_src_blend)
458 continue;
459
460 /* Only addition and subtraction equations are supported with
461 * dual source blending.
462 */
463 if (blend->dual_src_blend &&
464 (eqRGB == PIPE_BLEND_MIN || eqRGB == PIPE_BLEND_MAX ||
465 eqA == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MAX)) {
466 assert(!"Unsupported equation for dual source blending");
467 continue;
468 }
469
470 if (!state->rt[j].colormask)
471 continue;
472
473 /* cb_render_state will disable unused ones */
474 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
475
476 if (!state->rt[j].blend_enable) {
477 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
478 continue;
479 }
480
481 /* Blending optimizations for Stoney.
482 * These transformations don't change the behavior.
483 *
484 * First, get rid of DST in the blend factors:
485 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
486 */
487 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
488 PIPE_BLENDFACTOR_DST_COLOR,
489 PIPE_BLENDFACTOR_SRC_COLOR);
490 si_blend_remove_dst(&eqA, &srcA, &dstA,
491 PIPE_BLENDFACTOR_DST_COLOR,
492 PIPE_BLENDFACTOR_SRC_COLOR);
493 si_blend_remove_dst(&eqA, &srcA, &dstA,
494 PIPE_BLENDFACTOR_DST_ALPHA,
495 PIPE_BLENDFACTOR_SRC_ALPHA);
496
497 /* Look up the ideal settings from tables. */
498 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
499 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
500 srcA_opt = si_translate_blend_opt_factor(srcA, true);
501 dstA_opt = si_translate_blend_opt_factor(dstA, true);
502
503 /* Handle interdependencies. */
504 if (si_blend_factor_uses_dst(srcRGB))
505 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
506 if (si_blend_factor_uses_dst(srcA))
507 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
508
509 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
510 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
511 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
512 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
513 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
514
515 /* Set the final value. */
516 sx_mrt_blend_opt[i] =
517 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
518 S_028760_COLOR_DST_OPT(dstRGB_opt) |
519 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
520 S_028760_ALPHA_SRC_OPT(srcA_opt) |
521 S_028760_ALPHA_DST_OPT(dstA_opt) |
522 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
523
524 /* Set blend state. */
525 blend_cntl |= S_028780_ENABLE(1);
526 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
527 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
528 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
529
530 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
531 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
532 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
533 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
534 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
535 }
536 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
537
538 blend->blend_enable_4bit |= 0xfu << (i * 4);
539
540 /* This is only important for formats without alpha. */
541 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
542 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
543 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
544 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
545 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
546 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
547 blend->need_src_alpha_4bit |= 0xfu << (i * 4);
548 }
549
550 if (blend->cb_target_mask) {
551 color_control |= S_028808_MODE(mode);
552 } else {
553 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
554 }
555
556 if (sctx->b.family == CHIP_STONEY) {
557 for (int i = 0; i < 8; i++)
558 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
559 sx_mrt_blend_opt[i]);
560
561 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
562 if (blend->dual_src_blend || state->logicop_enable ||
563 mode == V_028808_CB_RESOLVE)
564 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
565 }
566
567 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
568 return blend;
569 }
570
571 static void *si_create_blend_state(struct pipe_context *ctx,
572 const struct pipe_blend_state *state)
573 {
574 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
575 }
576
577 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
578 {
579 struct si_context *sctx = (struct si_context *)ctx;
580 si_pm4_bind_state(sctx, blend, (struct si_state_blend *)state);
581 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
582 sctx->do_update_shaders = true;
583 }
584
585 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
586 {
587 struct si_context *sctx = (struct si_context *)ctx;
588 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
589 }
590
591 static void si_set_blend_color(struct pipe_context *ctx,
592 const struct pipe_blend_color *state)
593 {
594 struct si_context *sctx = (struct si_context *)ctx;
595
596 if (memcmp(&sctx->blend_color.state, state, sizeof(*state)) == 0)
597 return;
598
599 sctx->blend_color.state = *state;
600 si_mark_atom_dirty(sctx, &sctx->blend_color.atom);
601 }
602
603 static void si_emit_blend_color(struct si_context *sctx, struct r600_atom *atom)
604 {
605 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
606
607 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
608 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
609 }
610
611 /*
612 * Clipping
613 */
614
615 static void si_set_clip_state(struct pipe_context *ctx,
616 const struct pipe_clip_state *state)
617 {
618 struct si_context *sctx = (struct si_context *)ctx;
619 struct pipe_constant_buffer cb;
620
621 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
622 return;
623
624 sctx->clip_state.state = *state;
625 si_mark_atom_dirty(sctx, &sctx->clip_state.atom);
626
627 cb.buffer = NULL;
628 cb.user_buffer = state->ucp;
629 cb.buffer_offset = 0;
630 cb.buffer_size = 4*4*8;
631 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
632 pipe_resource_reference(&cb.buffer, NULL);
633 }
634
635 static void si_emit_clip_state(struct si_context *sctx, struct r600_atom *atom)
636 {
637 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
638
639 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
640 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
641 }
642
643 #define SIX_BITS 0x3F
644
645 static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom)
646 {
647 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
648 struct tgsi_shader_info *info = si_get_vs_info(sctx);
649 unsigned window_space =
650 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
651 unsigned clipdist_mask =
652 info->writes_clipvertex ? SIX_BITS : info->clipdist_writemask;
653
654 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
655 S_02881C_USE_VTX_POINT_SIZE(info->writes_psize) |
656 S_02881C_USE_VTX_EDGE_FLAG(info->writes_edgeflag) |
657 S_02881C_USE_VTX_RENDER_TARGET_INDX(info->writes_layer) |
658 S_02881C_USE_VTX_VIEWPORT_INDX(info->writes_viewport_index) |
659 S_02881C_VS_OUT_CCDIST0_VEC_ENA((clipdist_mask & 0x0F) != 0) |
660 S_02881C_VS_OUT_CCDIST1_VEC_ENA((clipdist_mask & 0xF0) != 0) |
661 S_02881C_VS_OUT_MISC_VEC_ENA(info->writes_psize ||
662 info->writes_edgeflag ||
663 info->writes_layer ||
664 info->writes_viewport_index) |
665 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(1) |
666 (sctx->queued.named.rasterizer->clip_plane_enable &
667 clipdist_mask));
668 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
669 sctx->queued.named.rasterizer->pa_cl_clip_cntl |
670 (clipdist_mask ? 0 :
671 sctx->queued.named.rasterizer->clip_plane_enable & SIX_BITS) |
672 S_028810_CLIP_DISABLE(window_space));
673
674 /* reuse needs to be set off if we write oViewport */
675 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF,
676 S_028AB4_REUSE_OFF(info->writes_viewport_index));
677 }
678
679 /*
680 * inferred state between framebuffer and rasterizer
681 */
682 static void si_update_poly_offset_state(struct si_context *sctx)
683 {
684 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
685
686 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf)
687 return;
688
689 switch (sctx->framebuffer.state.zsbuf->texture->format) {
690 case PIPE_FORMAT_Z16_UNORM:
691 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
692 break;
693 default: /* 24-bit */
694 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
695 break;
696 case PIPE_FORMAT_Z32_FLOAT:
697 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
698 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
699 break;
700 }
701 }
702
703 /*
704 * Rasterizer
705 */
706
707 static uint32_t si_translate_fill(uint32_t func)
708 {
709 switch(func) {
710 case PIPE_POLYGON_MODE_FILL:
711 return V_028814_X_DRAW_TRIANGLES;
712 case PIPE_POLYGON_MODE_LINE:
713 return V_028814_X_DRAW_LINES;
714 case PIPE_POLYGON_MODE_POINT:
715 return V_028814_X_DRAW_POINTS;
716 default:
717 assert(0);
718 return V_028814_X_DRAW_POINTS;
719 }
720 }
721
722 static void *si_create_rs_state(struct pipe_context *ctx,
723 const struct pipe_rasterizer_state *state)
724 {
725 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
726 struct si_pm4_state *pm4 = &rs->pm4;
727 unsigned tmp, i;
728 float psize_min, psize_max;
729
730 if (!rs) {
731 return NULL;
732 }
733
734 rs->scissor_enable = state->scissor;
735 rs->two_side = state->light_twoside;
736 rs->multisample_enable = state->multisample;
737 rs->force_persample_interp = state->force_persample_interp;
738 rs->clip_plane_enable = state->clip_plane_enable;
739 rs->line_stipple_enable = state->line_stipple_enable;
740 rs->poly_stipple_enable = state->poly_stipple_enable;
741 rs->line_smooth = state->line_smooth;
742 rs->poly_smooth = state->poly_smooth;
743 rs->uses_poly_offset = state->offset_point || state->offset_line ||
744 state->offset_tri;
745 rs->clamp_fragment_color = state->clamp_fragment_color;
746 rs->flatshade = state->flatshade;
747 rs->sprite_coord_enable = state->sprite_coord_enable;
748 rs->rasterizer_discard = state->rasterizer_discard;
749 rs->pa_sc_line_stipple = state->line_stipple_enable ?
750 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
751 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
752 rs->pa_cl_clip_cntl =
753 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
754 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
755 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
756 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
757 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
758
759 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
760 S_0286D4_FLAT_SHADE_ENA(1) |
761 S_0286D4_PNT_SPRITE_ENA(1) |
762 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
763 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
764 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
765 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
766 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
767
768 /* point size 12.4 fixed point */
769 tmp = (unsigned)(state->point_size * 8.0);
770 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
771
772 if (state->point_size_per_vertex) {
773 psize_min = util_get_min_point_size(state);
774 psize_max = 8192;
775 } else {
776 /* Force the point size to be as if the vertex output was disabled. */
777 psize_min = state->point_size;
778 psize_max = state->point_size;
779 }
780 /* Divide by two, because 0.5 = 1 pixel. */
781 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
782 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
783 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
784
785 tmp = (unsigned)state->line_width * 8;
786 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
787 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
788 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
789 S_028A48_MSAA_ENABLE(state->multisample ||
790 state->poly_smooth ||
791 state->line_smooth) |
792 S_028A48_VPORT_SCISSOR_ENABLE(1));
793
794 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
795 S_028BE4_PIX_CENTER(state->half_pixel_center) |
796 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
797
798 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
799 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
800 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
801 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
802 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
803 S_028814_FACE(!state->front_ccw) |
804 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
805 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
806 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
807 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
808 state->fill_back != PIPE_POLYGON_MODE_FILL) |
809 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
810 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
811 si_pm4_set_reg(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0 +
812 SI_SGPR_VS_STATE_BITS * 4, state->clamp_vertex_color);
813
814 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
815 for (i = 0; i < 3; i++) {
816 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
817 float offset_units = state->offset_units;
818 float offset_scale = state->offset_scale * 16.0f;
819 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
820
821 if (!state->offset_units_unscaled) {
822 switch (i) {
823 case 0: /* 16-bit zbuffer */
824 offset_units *= 4.0f;
825 pa_su_poly_offset_db_fmt_cntl =
826 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
827 break;
828 case 1: /* 24-bit zbuffer */
829 offset_units *= 2.0f;
830 pa_su_poly_offset_db_fmt_cntl =
831 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
832 break;
833 case 2: /* 32-bit zbuffer */
834 offset_units *= 1.0f;
835 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
836 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
837 break;
838 }
839 }
840
841 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
842 fui(offset_scale));
843 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
844 fui(offset_units));
845 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
846 fui(offset_scale));
847 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
848 fui(offset_units));
849 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
850 pa_su_poly_offset_db_fmt_cntl);
851 }
852
853 return rs;
854 }
855
856 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
857 {
858 struct si_context *sctx = (struct si_context *)ctx;
859 struct si_state_rasterizer *old_rs =
860 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
861 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
862
863 if (!state)
864 return;
865
866 if (sctx->framebuffer.nr_samples > 1 &&
867 (!old_rs || old_rs->multisample_enable != rs->multisample_enable)) {
868 si_mark_atom_dirty(sctx, &sctx->db_render_state);
869
870 if (sctx->b.family >= CHIP_POLARIS10)
871 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
872 }
873
874 r600_set_scissor_enable(&sctx->b, rs->scissor_enable);
875
876 si_pm4_bind_state(sctx, rasterizer, rs);
877 si_update_poly_offset_state(sctx);
878
879 si_mark_atom_dirty(sctx, &sctx->clip_regs);
880 sctx->do_update_shaders = true;
881 }
882
883 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
884 {
885 struct si_context *sctx = (struct si_context *)ctx;
886
887 if (sctx->queued.named.rasterizer == state)
888 si_pm4_bind_state(sctx, poly_offset, NULL);
889 si_pm4_delete_state(sctx, rasterizer, (struct si_state_rasterizer *)state);
890 }
891
892 /*
893 * infeered state between dsa and stencil ref
894 */
895 static void si_emit_stencil_ref(struct si_context *sctx, struct r600_atom *atom)
896 {
897 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
898 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
899 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
900
901 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
902 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
903 S_028430_STENCILMASK(dsa->valuemask[0]) |
904 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
905 S_028430_STENCILOPVAL(1));
906 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
907 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
908 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
909 S_028434_STENCILOPVAL_BF(1));
910 }
911
912 static void si_set_stencil_ref(struct pipe_context *ctx,
913 const struct pipe_stencil_ref *state)
914 {
915 struct si_context *sctx = (struct si_context *)ctx;
916
917 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
918 return;
919
920 sctx->stencil_ref.state = *state;
921 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
922 }
923
924
925 /*
926 * DSA
927 */
928
929 static uint32_t si_translate_stencil_op(int s_op)
930 {
931 switch (s_op) {
932 case PIPE_STENCIL_OP_KEEP:
933 return V_02842C_STENCIL_KEEP;
934 case PIPE_STENCIL_OP_ZERO:
935 return V_02842C_STENCIL_ZERO;
936 case PIPE_STENCIL_OP_REPLACE:
937 return V_02842C_STENCIL_REPLACE_TEST;
938 case PIPE_STENCIL_OP_INCR:
939 return V_02842C_STENCIL_ADD_CLAMP;
940 case PIPE_STENCIL_OP_DECR:
941 return V_02842C_STENCIL_SUB_CLAMP;
942 case PIPE_STENCIL_OP_INCR_WRAP:
943 return V_02842C_STENCIL_ADD_WRAP;
944 case PIPE_STENCIL_OP_DECR_WRAP:
945 return V_02842C_STENCIL_SUB_WRAP;
946 case PIPE_STENCIL_OP_INVERT:
947 return V_02842C_STENCIL_INVERT;
948 default:
949 R600_ERR("Unknown stencil op %d", s_op);
950 assert(0);
951 break;
952 }
953 return 0;
954 }
955
956 static void *si_create_dsa_state(struct pipe_context *ctx,
957 const struct pipe_depth_stencil_alpha_state *state)
958 {
959 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
960 struct si_pm4_state *pm4 = &dsa->pm4;
961 unsigned db_depth_control;
962 uint32_t db_stencil_control = 0;
963
964 if (!dsa) {
965 return NULL;
966 }
967
968 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
969 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
970 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
971 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
972
973 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
974 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
975 S_028800_ZFUNC(state->depth.func) |
976 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
977
978 /* stencil */
979 if (state->stencil[0].enabled) {
980 db_depth_control |= S_028800_STENCIL_ENABLE(1);
981 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
982 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
983 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
984 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
985
986 if (state->stencil[1].enabled) {
987 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
988 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
989 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
990 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
991 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
992 }
993 }
994
995 /* alpha */
996 if (state->alpha.enabled) {
997 dsa->alpha_func = state->alpha.func;
998
999 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1000 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
1001 } else {
1002 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1003 }
1004
1005 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1006 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1007 if (state->depth.bounds_test) {
1008 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1009 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1010 }
1011
1012 return dsa;
1013 }
1014
1015 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1016 {
1017 struct si_context *sctx = (struct si_context *)ctx;
1018 struct si_state_dsa *dsa = state;
1019
1020 if (!state)
1021 return;
1022
1023 si_pm4_bind_state(sctx, dsa, dsa);
1024
1025 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1026 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1027 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1028 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1029 }
1030 sctx->do_update_shaders = true;
1031 }
1032
1033 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1034 {
1035 struct si_context *sctx = (struct si_context *)ctx;
1036 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1037 }
1038
1039 static void *si_create_db_flush_dsa(struct si_context *sctx)
1040 {
1041 struct pipe_depth_stencil_alpha_state dsa = {};
1042
1043 return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
1044 }
1045
1046 /* DB RENDER STATE */
1047
1048 static void si_set_active_query_state(struct pipe_context *ctx, boolean enable)
1049 {
1050 struct si_context *sctx = (struct si_context*)ctx;
1051
1052 /* Pipeline stat & streamout queries. */
1053 if (enable) {
1054 sctx->b.flags &= ~R600_CONTEXT_STOP_PIPELINE_STATS;
1055 sctx->b.flags |= R600_CONTEXT_START_PIPELINE_STATS;
1056 } else {
1057 sctx->b.flags &= ~R600_CONTEXT_START_PIPELINE_STATS;
1058 sctx->b.flags |= R600_CONTEXT_STOP_PIPELINE_STATS;
1059 }
1060
1061 /* Occlusion queries. */
1062 if (sctx->occlusion_queries_disabled != !enable) {
1063 sctx->occlusion_queries_disabled = !enable;
1064 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1065 }
1066 }
1067
1068 static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
1069 {
1070 struct si_context *sctx = (struct si_context*)ctx;
1071
1072 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1073 }
1074
1075 static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
1076 {
1077 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1078 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1079 unsigned db_shader_control;
1080
1081 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1082
1083 /* DB_RENDER_CONTROL */
1084 if (sctx->dbcb_depth_copy_enabled ||
1085 sctx->dbcb_stencil_copy_enabled) {
1086 radeon_emit(cs,
1087 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1088 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1089 S_028000_COPY_CENTROID(1) |
1090 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
1091 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1092 radeon_emit(cs,
1093 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1094 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace));
1095 } else {
1096 radeon_emit(cs,
1097 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1098 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear));
1099 }
1100
1101 /* DB_COUNT_CONTROL (occlusion queries) */
1102 if (sctx->b.num_occlusion_queries > 0 &&
1103 !sctx->occlusion_queries_disabled) {
1104 bool perfect = sctx->b.num_perfect_occlusion_queries > 0;
1105
1106 if (sctx->b.chip_class >= CIK) {
1107 radeon_emit(cs,
1108 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1109 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
1110 S_028004_ZPASS_ENABLE(1) |
1111 S_028004_SLICE_EVEN_ENABLE(1) |
1112 S_028004_SLICE_ODD_ENABLE(1));
1113 } else {
1114 radeon_emit(cs,
1115 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1116 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
1117 }
1118 } else {
1119 /* Disable occlusion queries. */
1120 if (sctx->b.chip_class >= CIK) {
1121 radeon_emit(cs, 0);
1122 } else {
1123 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
1124 }
1125 }
1126
1127 /* DB_RENDER_OVERRIDE2 */
1128 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
1129 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1130 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1131 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4));
1132
1133 db_shader_control = S_02880C_ALPHA_TO_MASK_DISABLE(sctx->framebuffer.cb0_is_integer) |
1134 sctx->ps_db_shader_control;
1135
1136 /* Bug workaround for smoothing (overrasterization) on SI. */
1137 if (sctx->b.chip_class == SI && sctx->smoothing_enabled) {
1138 db_shader_control &= C_02880C_Z_ORDER;
1139 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1140 }
1141
1142 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1143 if (sctx->framebuffer.nr_samples <= 1 || (rs && !rs->multisample_enable))
1144 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1145
1146 if (sctx->b.family == CHIP_STONEY &&
1147 sctx->screen->b.debug_flags & DBG_NO_RB_PLUS)
1148 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1149
1150 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
1151 db_shader_control);
1152 }
1153
1154 /*
1155 * format translation
1156 */
1157 static uint32_t si_translate_colorformat(enum pipe_format format)
1158 {
1159 const struct util_format_description *desc = util_format_description(format);
1160
1161 #define HAS_SIZE(x,y,z,w) \
1162 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1163 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1164
1165 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1166 return V_028C70_COLOR_10_11_11;
1167
1168 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1169 return V_028C70_COLOR_INVALID;
1170
1171 /* hw cannot support mixed formats (except depth/stencil, since
1172 * stencil is not written to). */
1173 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1174 return V_028C70_COLOR_INVALID;
1175
1176 switch (desc->nr_channels) {
1177 case 1:
1178 switch (desc->channel[0].size) {
1179 case 8:
1180 return V_028C70_COLOR_8;
1181 case 16:
1182 return V_028C70_COLOR_16;
1183 case 32:
1184 return V_028C70_COLOR_32;
1185 }
1186 break;
1187 case 2:
1188 if (desc->channel[0].size == desc->channel[1].size) {
1189 switch (desc->channel[0].size) {
1190 case 8:
1191 return V_028C70_COLOR_8_8;
1192 case 16:
1193 return V_028C70_COLOR_16_16;
1194 case 32:
1195 return V_028C70_COLOR_32_32;
1196 }
1197 } else if (HAS_SIZE(8,24,0,0)) {
1198 return V_028C70_COLOR_24_8;
1199 } else if (HAS_SIZE(24,8,0,0)) {
1200 return V_028C70_COLOR_8_24;
1201 }
1202 break;
1203 case 3:
1204 if (HAS_SIZE(5,6,5,0)) {
1205 return V_028C70_COLOR_5_6_5;
1206 } else if (HAS_SIZE(32,8,24,0)) {
1207 return V_028C70_COLOR_X24_8_32_FLOAT;
1208 }
1209 break;
1210 case 4:
1211 if (desc->channel[0].size == desc->channel[1].size &&
1212 desc->channel[0].size == desc->channel[2].size &&
1213 desc->channel[0].size == desc->channel[3].size) {
1214 switch (desc->channel[0].size) {
1215 case 4:
1216 return V_028C70_COLOR_4_4_4_4;
1217 case 8:
1218 return V_028C70_COLOR_8_8_8_8;
1219 case 16:
1220 return V_028C70_COLOR_16_16_16_16;
1221 case 32:
1222 return V_028C70_COLOR_32_32_32_32;
1223 }
1224 } else if (HAS_SIZE(5,5,5,1)) {
1225 return V_028C70_COLOR_1_5_5_5;
1226 } else if (HAS_SIZE(10,10,10,2)) {
1227 return V_028C70_COLOR_2_10_10_10;
1228 }
1229 break;
1230 }
1231 return V_028C70_COLOR_INVALID;
1232 }
1233
1234 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1235 {
1236 if (SI_BIG_ENDIAN) {
1237 switch(colorformat) {
1238 /* 8-bit buffers. */
1239 case V_028C70_COLOR_8:
1240 return V_028C70_ENDIAN_NONE;
1241
1242 /* 16-bit buffers. */
1243 case V_028C70_COLOR_5_6_5:
1244 case V_028C70_COLOR_1_5_5_5:
1245 case V_028C70_COLOR_4_4_4_4:
1246 case V_028C70_COLOR_16:
1247 case V_028C70_COLOR_8_8:
1248 return V_028C70_ENDIAN_8IN16;
1249
1250 /* 32-bit buffers. */
1251 case V_028C70_COLOR_8_8_8_8:
1252 case V_028C70_COLOR_2_10_10_10:
1253 case V_028C70_COLOR_8_24:
1254 case V_028C70_COLOR_24_8:
1255 case V_028C70_COLOR_16_16:
1256 return V_028C70_ENDIAN_8IN32;
1257
1258 /* 64-bit buffers. */
1259 case V_028C70_COLOR_16_16_16_16:
1260 return V_028C70_ENDIAN_8IN16;
1261
1262 case V_028C70_COLOR_32_32:
1263 return V_028C70_ENDIAN_8IN32;
1264
1265 /* 128-bit buffers. */
1266 case V_028C70_COLOR_32_32_32_32:
1267 return V_028C70_ENDIAN_8IN32;
1268 default:
1269 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1270 }
1271 } else {
1272 return V_028C70_ENDIAN_NONE;
1273 }
1274 }
1275
1276 static uint32_t si_translate_dbformat(enum pipe_format format)
1277 {
1278 switch (format) {
1279 case PIPE_FORMAT_Z16_UNORM:
1280 return V_028040_Z_16;
1281 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1282 case PIPE_FORMAT_X8Z24_UNORM:
1283 case PIPE_FORMAT_Z24X8_UNORM:
1284 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1285 return V_028040_Z_24; /* deprecated on SI */
1286 case PIPE_FORMAT_Z32_FLOAT:
1287 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1288 return V_028040_Z_32_FLOAT;
1289 default:
1290 return V_028040_Z_INVALID;
1291 }
1292 }
1293
1294 /*
1295 * Texture translation
1296 */
1297
1298 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1299 enum pipe_format format,
1300 const struct util_format_description *desc,
1301 int first_non_void)
1302 {
1303 struct si_screen *sscreen = (struct si_screen*)screen;
1304 bool enable_compressed_formats = (sscreen->b.info.drm_major == 2 &&
1305 sscreen->b.info.drm_minor >= 31) ||
1306 sscreen->b.info.drm_major == 3;
1307 bool uniform = true;
1308 int i;
1309
1310 /* Colorspace (return non-RGB formats directly). */
1311 switch (desc->colorspace) {
1312 /* Depth stencil formats */
1313 case UTIL_FORMAT_COLORSPACE_ZS:
1314 switch (format) {
1315 case PIPE_FORMAT_Z16_UNORM:
1316 return V_008F14_IMG_DATA_FORMAT_16;
1317 case PIPE_FORMAT_X24S8_UINT:
1318 case PIPE_FORMAT_Z24X8_UNORM:
1319 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1320 return V_008F14_IMG_DATA_FORMAT_8_24;
1321 case PIPE_FORMAT_X8Z24_UNORM:
1322 case PIPE_FORMAT_S8X24_UINT:
1323 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1324 return V_008F14_IMG_DATA_FORMAT_24_8;
1325 case PIPE_FORMAT_S8_UINT:
1326 return V_008F14_IMG_DATA_FORMAT_8;
1327 case PIPE_FORMAT_Z32_FLOAT:
1328 return V_008F14_IMG_DATA_FORMAT_32;
1329 case PIPE_FORMAT_X32_S8X24_UINT:
1330 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1331 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1332 default:
1333 goto out_unknown;
1334 }
1335
1336 case UTIL_FORMAT_COLORSPACE_YUV:
1337 goto out_unknown; /* TODO */
1338
1339 case UTIL_FORMAT_COLORSPACE_SRGB:
1340 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1341 goto out_unknown;
1342 break;
1343
1344 default:
1345 break;
1346 }
1347
1348 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1349 if (!enable_compressed_formats)
1350 goto out_unknown;
1351
1352 switch (format) {
1353 case PIPE_FORMAT_RGTC1_SNORM:
1354 case PIPE_FORMAT_LATC1_SNORM:
1355 case PIPE_FORMAT_RGTC1_UNORM:
1356 case PIPE_FORMAT_LATC1_UNORM:
1357 return V_008F14_IMG_DATA_FORMAT_BC4;
1358 case PIPE_FORMAT_RGTC2_SNORM:
1359 case PIPE_FORMAT_LATC2_SNORM:
1360 case PIPE_FORMAT_RGTC2_UNORM:
1361 case PIPE_FORMAT_LATC2_UNORM:
1362 return V_008F14_IMG_DATA_FORMAT_BC5;
1363 default:
1364 goto out_unknown;
1365 }
1366 }
1367
1368 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1369 sscreen->b.family == CHIP_STONEY) {
1370 switch (format) {
1371 case PIPE_FORMAT_ETC1_RGB8:
1372 case PIPE_FORMAT_ETC2_RGB8:
1373 case PIPE_FORMAT_ETC2_SRGB8:
1374 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1375 case PIPE_FORMAT_ETC2_RGB8A1:
1376 case PIPE_FORMAT_ETC2_SRGB8A1:
1377 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1378 case PIPE_FORMAT_ETC2_RGBA8:
1379 case PIPE_FORMAT_ETC2_SRGBA8:
1380 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1381 case PIPE_FORMAT_ETC2_R11_UNORM:
1382 case PIPE_FORMAT_ETC2_R11_SNORM:
1383 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1384 case PIPE_FORMAT_ETC2_RG11_UNORM:
1385 case PIPE_FORMAT_ETC2_RG11_SNORM:
1386 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1387 default:
1388 goto out_unknown;
1389 }
1390 }
1391
1392 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1393 if (!enable_compressed_formats)
1394 goto out_unknown;
1395
1396 switch (format) {
1397 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1398 case PIPE_FORMAT_BPTC_SRGBA:
1399 return V_008F14_IMG_DATA_FORMAT_BC7;
1400 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1401 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1402 return V_008F14_IMG_DATA_FORMAT_BC6;
1403 default:
1404 goto out_unknown;
1405 }
1406 }
1407
1408 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1409 switch (format) {
1410 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1411 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1412 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1413 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1414 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1415 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1416 default:
1417 goto out_unknown;
1418 }
1419 }
1420
1421 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1422 if (!enable_compressed_formats)
1423 goto out_unknown;
1424
1425 if (!util_format_s3tc_enabled) {
1426 goto out_unknown;
1427 }
1428
1429 switch (format) {
1430 case PIPE_FORMAT_DXT1_RGB:
1431 case PIPE_FORMAT_DXT1_RGBA:
1432 case PIPE_FORMAT_DXT1_SRGB:
1433 case PIPE_FORMAT_DXT1_SRGBA:
1434 return V_008F14_IMG_DATA_FORMAT_BC1;
1435 case PIPE_FORMAT_DXT3_RGBA:
1436 case PIPE_FORMAT_DXT3_SRGBA:
1437 return V_008F14_IMG_DATA_FORMAT_BC2;
1438 case PIPE_FORMAT_DXT5_RGBA:
1439 case PIPE_FORMAT_DXT5_SRGBA:
1440 return V_008F14_IMG_DATA_FORMAT_BC3;
1441 default:
1442 goto out_unknown;
1443 }
1444 }
1445
1446 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1447 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1448 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1449 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1450 }
1451
1452 /* R8G8Bx_SNORM - TODO CxV8U8 */
1453
1454 /* hw cannot support mixed formats (except depth/stencil, since only
1455 * depth is read).*/
1456 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1457 goto out_unknown;
1458
1459 /* See whether the components are of the same size. */
1460 for (i = 1; i < desc->nr_channels; i++) {
1461 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1462 }
1463
1464 /* Non-uniform formats. */
1465 if (!uniform) {
1466 switch(desc->nr_channels) {
1467 case 3:
1468 if (desc->channel[0].size == 5 &&
1469 desc->channel[1].size == 6 &&
1470 desc->channel[2].size == 5) {
1471 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1472 }
1473 goto out_unknown;
1474 case 4:
1475 if (desc->channel[0].size == 5 &&
1476 desc->channel[1].size == 5 &&
1477 desc->channel[2].size == 5 &&
1478 desc->channel[3].size == 1) {
1479 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1480 }
1481 if (desc->channel[0].size == 10 &&
1482 desc->channel[1].size == 10 &&
1483 desc->channel[2].size == 10 &&
1484 desc->channel[3].size == 2) {
1485 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1486 }
1487 goto out_unknown;
1488 }
1489 goto out_unknown;
1490 }
1491
1492 if (first_non_void < 0 || first_non_void > 3)
1493 goto out_unknown;
1494
1495 /* uniform formats */
1496 switch (desc->channel[first_non_void].size) {
1497 case 4:
1498 switch (desc->nr_channels) {
1499 #if 0 /* Not supported for render targets */
1500 case 2:
1501 return V_008F14_IMG_DATA_FORMAT_4_4;
1502 #endif
1503 case 4:
1504 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1505 }
1506 break;
1507 case 8:
1508 switch (desc->nr_channels) {
1509 case 1:
1510 return V_008F14_IMG_DATA_FORMAT_8;
1511 case 2:
1512 return V_008F14_IMG_DATA_FORMAT_8_8;
1513 case 4:
1514 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1515 }
1516 break;
1517 case 16:
1518 switch (desc->nr_channels) {
1519 case 1:
1520 return V_008F14_IMG_DATA_FORMAT_16;
1521 case 2:
1522 return V_008F14_IMG_DATA_FORMAT_16_16;
1523 case 4:
1524 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1525 }
1526 break;
1527 case 32:
1528 switch (desc->nr_channels) {
1529 case 1:
1530 return V_008F14_IMG_DATA_FORMAT_32;
1531 case 2:
1532 return V_008F14_IMG_DATA_FORMAT_32_32;
1533 #if 0 /* Not supported for render targets */
1534 case 3:
1535 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1536 #endif
1537 case 4:
1538 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1539 }
1540 }
1541
1542 out_unknown:
1543 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1544 return ~0;
1545 }
1546
1547 static unsigned si_tex_wrap(unsigned wrap)
1548 {
1549 switch (wrap) {
1550 default:
1551 case PIPE_TEX_WRAP_REPEAT:
1552 return V_008F30_SQ_TEX_WRAP;
1553 case PIPE_TEX_WRAP_CLAMP:
1554 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1555 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1556 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1557 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1558 return V_008F30_SQ_TEX_CLAMP_BORDER;
1559 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1560 return V_008F30_SQ_TEX_MIRROR;
1561 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1562 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1563 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1564 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1565 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1566 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1567 }
1568 }
1569
1570 static unsigned si_tex_mipfilter(unsigned filter)
1571 {
1572 switch (filter) {
1573 case PIPE_TEX_MIPFILTER_NEAREST:
1574 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1575 case PIPE_TEX_MIPFILTER_LINEAR:
1576 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1577 default:
1578 case PIPE_TEX_MIPFILTER_NONE:
1579 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1580 }
1581 }
1582
1583 static unsigned si_tex_compare(unsigned compare)
1584 {
1585 switch (compare) {
1586 default:
1587 case PIPE_FUNC_NEVER:
1588 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1589 case PIPE_FUNC_LESS:
1590 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1591 case PIPE_FUNC_EQUAL:
1592 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1593 case PIPE_FUNC_LEQUAL:
1594 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1595 case PIPE_FUNC_GREATER:
1596 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1597 case PIPE_FUNC_NOTEQUAL:
1598 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1599 case PIPE_FUNC_GEQUAL:
1600 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1601 case PIPE_FUNC_ALWAYS:
1602 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1603 }
1604 }
1605
1606 static unsigned si_tex_dim(unsigned res_target, unsigned view_target,
1607 unsigned nr_samples)
1608 {
1609 if (view_target == PIPE_TEXTURE_CUBE ||
1610 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1611 res_target = view_target;
1612
1613 switch (res_target) {
1614 default:
1615 case PIPE_TEXTURE_1D:
1616 return V_008F1C_SQ_RSRC_IMG_1D;
1617 case PIPE_TEXTURE_1D_ARRAY:
1618 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1619 case PIPE_TEXTURE_2D:
1620 case PIPE_TEXTURE_RECT:
1621 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1622 V_008F1C_SQ_RSRC_IMG_2D;
1623 case PIPE_TEXTURE_2D_ARRAY:
1624 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1625 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1626 case PIPE_TEXTURE_3D:
1627 return V_008F1C_SQ_RSRC_IMG_3D;
1628 case PIPE_TEXTURE_CUBE:
1629 case PIPE_TEXTURE_CUBE_ARRAY:
1630 return V_008F1C_SQ_RSRC_IMG_CUBE;
1631 }
1632 }
1633
1634 /*
1635 * Format support testing
1636 */
1637
1638 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1639 {
1640 return si_translate_texformat(screen, format, util_format_description(format),
1641 util_format_get_first_non_void_channel(format)) != ~0U;
1642 }
1643
1644 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1645 const struct util_format_description *desc,
1646 int first_non_void)
1647 {
1648 unsigned type;
1649 int i;
1650
1651 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1652 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1653
1654 assert(first_non_void >= 0);
1655 type = desc->channel[first_non_void].type;
1656
1657 if (type == UTIL_FORMAT_TYPE_FIXED)
1658 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1659
1660 if (desc->nr_channels == 4 &&
1661 desc->channel[0].size == 10 &&
1662 desc->channel[1].size == 10 &&
1663 desc->channel[2].size == 10 &&
1664 desc->channel[3].size == 2)
1665 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1666
1667 /* See whether the components are of the same size. */
1668 for (i = 0; i < desc->nr_channels; i++) {
1669 if (desc->channel[first_non_void].size != desc->channel[i].size)
1670 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1671 }
1672
1673 switch (desc->channel[first_non_void].size) {
1674 case 8:
1675 switch (desc->nr_channels) {
1676 case 1:
1677 return V_008F0C_BUF_DATA_FORMAT_8;
1678 case 2:
1679 return V_008F0C_BUF_DATA_FORMAT_8_8;
1680 case 3:
1681 case 4:
1682 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1683 }
1684 break;
1685 case 16:
1686 switch (desc->nr_channels) {
1687 case 1:
1688 return V_008F0C_BUF_DATA_FORMAT_16;
1689 case 2:
1690 return V_008F0C_BUF_DATA_FORMAT_16_16;
1691 case 3:
1692 case 4:
1693 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1694 }
1695 break;
1696 case 32:
1697 /* From the Southern Islands ISA documentation about MTBUF:
1698 * 'Memory reads of data in memory that is 32 or 64 bits do not
1699 * undergo any format conversion.'
1700 */
1701 if (type != UTIL_FORMAT_TYPE_FLOAT &&
1702 !desc->channel[first_non_void].pure_integer)
1703 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1704
1705 switch (desc->nr_channels) {
1706 case 1:
1707 return V_008F0C_BUF_DATA_FORMAT_32;
1708 case 2:
1709 return V_008F0C_BUF_DATA_FORMAT_32_32;
1710 case 3:
1711 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1712 case 4:
1713 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1714 }
1715 break;
1716 }
1717
1718 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1719 }
1720
1721 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1722 const struct util_format_description *desc,
1723 int first_non_void)
1724 {
1725 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1726 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1727
1728 assert(first_non_void >= 0);
1729
1730 switch (desc->channel[first_non_void].type) {
1731 case UTIL_FORMAT_TYPE_SIGNED:
1732 if (desc->channel[first_non_void].normalized)
1733 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1734 else if (desc->channel[first_non_void].pure_integer)
1735 return V_008F0C_BUF_NUM_FORMAT_SINT;
1736 else
1737 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1738 break;
1739 case UTIL_FORMAT_TYPE_UNSIGNED:
1740 if (desc->channel[first_non_void].normalized)
1741 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1742 else if (desc->channel[first_non_void].pure_integer)
1743 return V_008F0C_BUF_NUM_FORMAT_UINT;
1744 else
1745 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1746 break;
1747 case UTIL_FORMAT_TYPE_FLOAT:
1748 default:
1749 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1750 }
1751 }
1752
1753 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
1754 {
1755 const struct util_format_description *desc;
1756 int first_non_void;
1757 unsigned data_format;
1758
1759 desc = util_format_description(format);
1760 first_non_void = util_format_get_first_non_void_channel(format);
1761 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1762 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
1763 }
1764
1765 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1766 {
1767 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1768 r600_translate_colorswap(format, false) != ~0U;
1769 }
1770
1771 static bool si_is_zs_format_supported(enum pipe_format format)
1772 {
1773 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1774 }
1775
1776 static boolean si_is_format_supported(struct pipe_screen *screen,
1777 enum pipe_format format,
1778 enum pipe_texture_target target,
1779 unsigned sample_count,
1780 unsigned usage)
1781 {
1782 unsigned retval = 0;
1783
1784 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1785 R600_ERR("r600: unsupported texture type %d\n", target);
1786 return false;
1787 }
1788
1789 if (!util_format_is_supported(format, usage))
1790 return false;
1791
1792 if (sample_count > 1) {
1793 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
1794 return false;
1795
1796 if (usage & PIPE_BIND_SHADER_IMAGE)
1797 return false;
1798
1799 switch (sample_count) {
1800 case 2:
1801 case 4:
1802 case 8:
1803 break;
1804 case 16:
1805 if (format == PIPE_FORMAT_NONE)
1806 return true;
1807 else
1808 return false;
1809 default:
1810 return false;
1811 }
1812 }
1813
1814 if (usage & (PIPE_BIND_SAMPLER_VIEW |
1815 PIPE_BIND_SHADER_IMAGE)) {
1816 if (target == PIPE_BUFFER) {
1817 if (si_is_vertex_format_supported(screen, format))
1818 retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
1819 PIPE_BIND_SHADER_IMAGE);
1820 } else {
1821 if (si_is_sampler_format_supported(screen, format))
1822 retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
1823 PIPE_BIND_SHADER_IMAGE);
1824 }
1825 }
1826
1827 if ((usage & (PIPE_BIND_RENDER_TARGET |
1828 PIPE_BIND_DISPLAY_TARGET |
1829 PIPE_BIND_SCANOUT |
1830 PIPE_BIND_SHARED |
1831 PIPE_BIND_BLENDABLE)) &&
1832 si_is_colorbuffer_format_supported(format)) {
1833 retval |= usage &
1834 (PIPE_BIND_RENDER_TARGET |
1835 PIPE_BIND_DISPLAY_TARGET |
1836 PIPE_BIND_SCANOUT |
1837 PIPE_BIND_SHARED);
1838 if (!util_format_is_pure_integer(format) &&
1839 !util_format_is_depth_or_stencil(format))
1840 retval |= usage & PIPE_BIND_BLENDABLE;
1841 }
1842
1843 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1844 si_is_zs_format_supported(format)) {
1845 retval |= PIPE_BIND_DEPTH_STENCIL;
1846 }
1847
1848 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
1849 si_is_vertex_format_supported(screen, format)) {
1850 retval |= PIPE_BIND_VERTEX_BUFFER;
1851 }
1852
1853 if (usage & PIPE_BIND_TRANSFER_READ)
1854 retval |= PIPE_BIND_TRANSFER_READ;
1855 if (usage & PIPE_BIND_TRANSFER_WRITE)
1856 retval |= PIPE_BIND_TRANSFER_WRITE;
1857
1858 if ((usage & PIPE_BIND_LINEAR) &&
1859 !util_format_is_compressed(format) &&
1860 !(usage & PIPE_BIND_DEPTH_STENCIL))
1861 retval |= PIPE_BIND_LINEAR;
1862
1863 return retval == usage;
1864 }
1865
1866 /*
1867 * framebuffer handling
1868 */
1869
1870 static void si_choose_spi_color_formats(struct r600_surface *surf,
1871 unsigned format, unsigned swap,
1872 unsigned ntype, bool is_depth)
1873 {
1874 /* Alpha is needed for alpha-to-coverage.
1875 * Blending may be with or without alpha.
1876 */
1877 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
1878 unsigned alpha = 0; /* exports alpha, but may not support blending */
1879 unsigned blend = 0; /* supports blending, but may not export alpha */
1880 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
1881
1882 /* Choose the SPI color formats. These are required values for Stoney/RB+.
1883 * Other chips have multiple choices, though they are not necessarily better.
1884 */
1885 switch (format) {
1886 case V_028C70_COLOR_5_6_5:
1887 case V_028C70_COLOR_1_5_5_5:
1888 case V_028C70_COLOR_5_5_5_1:
1889 case V_028C70_COLOR_4_4_4_4:
1890 case V_028C70_COLOR_10_11_11:
1891 case V_028C70_COLOR_11_11_10:
1892 case V_028C70_COLOR_8:
1893 case V_028C70_COLOR_8_8:
1894 case V_028C70_COLOR_8_8_8_8:
1895 case V_028C70_COLOR_10_10_10_2:
1896 case V_028C70_COLOR_2_10_10_10:
1897 if (ntype == V_028C70_NUMBER_UINT)
1898 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
1899 else if (ntype == V_028C70_NUMBER_SINT)
1900 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
1901 else
1902 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
1903 break;
1904
1905 case V_028C70_COLOR_16:
1906 case V_028C70_COLOR_16_16:
1907 case V_028C70_COLOR_16_16_16_16:
1908 if (ntype == V_028C70_NUMBER_UNORM ||
1909 ntype == V_028C70_NUMBER_SNORM) {
1910 /* UNORM16 and SNORM16 don't support blending */
1911 if (ntype == V_028C70_NUMBER_UNORM)
1912 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
1913 else
1914 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
1915
1916 /* Use 32 bits per channel for blending. */
1917 if (format == V_028C70_COLOR_16) {
1918 if (swap == V_028C70_SWAP_STD) { /* R */
1919 blend = V_028714_SPI_SHADER_32_R;
1920 blend_alpha = V_028714_SPI_SHADER_32_AR;
1921 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
1922 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
1923 else
1924 assert(0);
1925 } else if (format == V_028C70_COLOR_16_16) {
1926 if (swap == V_028C70_SWAP_STD) { /* RG */
1927 blend = V_028714_SPI_SHADER_32_GR;
1928 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
1929 } else if (swap == V_028C70_SWAP_ALT) /* RA */
1930 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
1931 else
1932 assert(0);
1933 } else /* 16_16_16_16 */
1934 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
1935 } else if (ntype == V_028C70_NUMBER_UINT)
1936 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
1937 else if (ntype == V_028C70_NUMBER_SINT)
1938 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
1939 else if (ntype == V_028C70_NUMBER_FLOAT)
1940 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
1941 else
1942 assert(0);
1943 break;
1944
1945 case V_028C70_COLOR_32:
1946 if (swap == V_028C70_SWAP_STD) { /* R */
1947 blend = normal = V_028714_SPI_SHADER_32_R;
1948 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
1949 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
1950 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
1951 else
1952 assert(0);
1953 break;
1954
1955 case V_028C70_COLOR_32_32:
1956 if (swap == V_028C70_SWAP_STD) { /* RG */
1957 blend = normal = V_028714_SPI_SHADER_32_GR;
1958 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
1959 } else if (swap == V_028C70_SWAP_ALT) /* RA */
1960 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
1961 else
1962 assert(0);
1963 break;
1964
1965 case V_028C70_COLOR_32_32_32_32:
1966 case V_028C70_COLOR_8_24:
1967 case V_028C70_COLOR_24_8:
1968 case V_028C70_COLOR_X24_8_32_FLOAT:
1969 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
1970 break;
1971
1972 default:
1973 assert(0);
1974 return;
1975 }
1976
1977 /* The DB->CB copy needs 32_ABGR. */
1978 if (is_depth)
1979 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
1980
1981 surf->spi_shader_col_format = normal;
1982 surf->spi_shader_col_format_alpha = alpha;
1983 surf->spi_shader_col_format_blend = blend;
1984 surf->spi_shader_col_format_blend_alpha = blend_alpha;
1985 }
1986
1987 static void si_initialize_color_surface(struct si_context *sctx,
1988 struct r600_surface *surf)
1989 {
1990 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1991 unsigned color_info, color_attrib, color_view;
1992 unsigned format, swap, ntype, endian;
1993 const struct util_format_description *desc;
1994 int i;
1995 unsigned blend_clamp = 0, blend_bypass = 0;
1996
1997 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
1998 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
1999
2000 desc = util_format_description(surf->base.format);
2001 for (i = 0; i < 4; i++) {
2002 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2003 break;
2004 }
2005 }
2006 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
2007 ntype = V_028C70_NUMBER_FLOAT;
2008 } else {
2009 ntype = V_028C70_NUMBER_UNORM;
2010 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2011 ntype = V_028C70_NUMBER_SRGB;
2012 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2013 if (desc->channel[i].pure_integer) {
2014 ntype = V_028C70_NUMBER_SINT;
2015 } else {
2016 assert(desc->channel[i].normalized);
2017 ntype = V_028C70_NUMBER_SNORM;
2018 }
2019 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2020 if (desc->channel[i].pure_integer) {
2021 ntype = V_028C70_NUMBER_UINT;
2022 } else {
2023 assert(desc->channel[i].normalized);
2024 ntype = V_028C70_NUMBER_UNORM;
2025 }
2026 }
2027 }
2028
2029 format = si_translate_colorformat(surf->base.format);
2030 if (format == V_028C70_COLOR_INVALID) {
2031 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2032 }
2033 assert(format != V_028C70_COLOR_INVALID);
2034 swap = r600_translate_colorswap(surf->base.format, false);
2035 endian = si_colorformat_endian_swap(format);
2036
2037 /* blend clamp should be set for all NORM/SRGB types */
2038 if (ntype == V_028C70_NUMBER_UNORM ||
2039 ntype == V_028C70_NUMBER_SNORM ||
2040 ntype == V_028C70_NUMBER_SRGB)
2041 blend_clamp = 1;
2042
2043 /* set blend bypass according to docs if SINT/UINT or
2044 8/24 COLOR variants */
2045 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2046 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2047 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2048 blend_clamp = 0;
2049 blend_bypass = 1;
2050 }
2051
2052 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
2053 (format == V_028C70_COLOR_8 ||
2054 format == V_028C70_COLOR_8_8 ||
2055 format == V_028C70_COLOR_8_8_8_8))
2056 surf->color_is_int8 = true;
2057
2058 color_info = S_028C70_FORMAT(format) |
2059 S_028C70_COMP_SWAP(swap) |
2060 S_028C70_BLEND_CLAMP(blend_clamp) |
2061 S_028C70_BLEND_BYPASS(blend_bypass) |
2062 S_028C70_SIMPLE_FLOAT(1) |
2063 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2064 ntype != V_028C70_NUMBER_SNORM &&
2065 ntype != V_028C70_NUMBER_SRGB &&
2066 format != V_028C70_COLOR_8_24 &&
2067 format != V_028C70_COLOR_24_8) |
2068 S_028C70_NUMBER_TYPE(ntype) |
2069 S_028C70_ENDIAN(endian);
2070
2071 /* Intensity is implemented as Red, so treat it that way. */
2072 color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2073 util_format_is_intensity(surf->base.format));
2074
2075 if (rtex->resource.b.b.nr_samples > 1) {
2076 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
2077
2078 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2079 S_028C74_NUM_FRAGMENTS(log_samples);
2080
2081 if (rtex->fmask.size) {
2082 color_info |= S_028C70_COMPRESSION(1);
2083 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
2084
2085 if (sctx->b.chip_class == SI) {
2086 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2087 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2088 }
2089 }
2090 }
2091
2092 surf->cb_color_view = color_view;
2093 surf->cb_color_info = color_info;
2094 surf->cb_color_attrib = color_attrib;
2095
2096 if (sctx->b.chip_class >= VI) {
2097 unsigned max_uncompressed_block_size = 2;
2098
2099 if (rtex->surface.nsamples > 1) {
2100 if (rtex->surface.bpe == 1)
2101 max_uncompressed_block_size = 0;
2102 else if (rtex->surface.bpe == 2)
2103 max_uncompressed_block_size = 1;
2104 }
2105
2106 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2107 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2108 }
2109
2110 /* This must be set for fast clear to work without FMASK. */
2111 if (!rtex->fmask.size && sctx->b.chip_class == SI) {
2112 unsigned bankh = util_logbase2(rtex->surface.bankh);
2113 surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2114 }
2115
2116 /* Determine pixel shader export format */
2117 si_choose_spi_color_formats(surf, format, swap, ntype, rtex->is_depth);
2118
2119 surf->color_initialized = true;
2120 }
2121
2122 static void si_init_depth_surface(struct si_context *sctx,
2123 struct r600_surface *surf)
2124 {
2125 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2126 unsigned level = surf->base.u.tex.level;
2127 struct radeon_surf_level *levelinfo = &rtex->surface.level[level];
2128 unsigned format;
2129 uint32_t z_info, s_info, db_depth_info;
2130 uint64_t z_offs, s_offs;
2131 uint32_t db_htile_data_base, db_htile_surface;
2132
2133 format = si_translate_dbformat(rtex->resource.b.b.format);
2134
2135 if (format == V_028040_Z_INVALID) {
2136 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
2137 }
2138 assert(format != V_028040_Z_INVALID);
2139
2140 s_offs = z_offs = rtex->resource.gpu_address;
2141 z_offs += rtex->surface.level[level].offset;
2142 s_offs += rtex->surface.stencil_level[level].offset;
2143
2144 db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
2145
2146 z_info = S_028040_FORMAT(format);
2147 if (rtex->resource.b.b.nr_samples > 1) {
2148 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
2149 }
2150
2151 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
2152 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
2153 else
2154 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
2155
2156 if (sctx->b.chip_class >= CIK) {
2157 struct radeon_info *info = &sctx->screen->b.info;
2158 unsigned index = rtex->surface.tiling_index[level];
2159 unsigned stencil_index = rtex->surface.stencil_tiling_index[level];
2160 unsigned macro_index = rtex->surface.macro_tile_index;
2161 unsigned tile_mode = info->si_tile_mode_array[index];
2162 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2163 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2164
2165 db_depth_info |=
2166 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2167 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2168 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2169 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2170 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2171 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2172 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2173 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2174 } else {
2175 unsigned tile_mode_index = si_tile_mode_index(rtex, level, false);
2176 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2177 tile_mode_index = si_tile_mode_index(rtex, level, true);
2178 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2179 }
2180
2181 /* HiZ aka depth buffer htile */
2182 /* use htile only for first level */
2183 if (rtex->htile_buffer && !level) {
2184 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2185 S_028040_ALLOW_EXPCLEAR(1);
2186
2187 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
2188 /* Workaround: For a not yet understood reason, the
2189 * combination of MSAA, fast stencil clear and stencil
2190 * decompress messes with subsequent stencil buffer
2191 * uses. Problem was reproduced on Verde, Bonaire,
2192 * Tonga, and Carrizo.
2193 *
2194 * Disabling EXPCLEAR works around the problem.
2195 *
2196 * Check piglit's arb_texture_multisample-stencil-clear
2197 * test if you want to try changing this.
2198 */
2199 if (rtex->resource.b.b.nr_samples <= 1)
2200 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2201 } else
2202 /* Use all of the htile_buffer for depth if there's no stencil. */
2203 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2204
2205 uint64_t va = rtex->htile_buffer->gpu_address;
2206 db_htile_data_base = va >> 8;
2207 db_htile_surface = S_028ABC_FULL_CACHE(1);
2208 } else {
2209 db_htile_data_base = 0;
2210 db_htile_surface = 0;
2211 }
2212
2213 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2214
2215 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2216 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2217 surf->db_htile_data_base = db_htile_data_base;
2218 surf->db_depth_info = db_depth_info;
2219 surf->db_z_info = z_info;
2220 surf->db_stencil_info = s_info;
2221 surf->db_depth_base = z_offs >> 8;
2222 surf->db_stencil_base = s_offs >> 8;
2223 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2224 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2225 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2226 levelinfo->nblk_y) / 64 - 1);
2227 surf->db_htile_surface = db_htile_surface;
2228
2229 surf->depth_initialized = true;
2230 }
2231
2232 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
2233 {
2234 for (int i = 0; i < state->nr_cbufs; ++i) {
2235 struct r600_surface *surf = NULL;
2236 struct r600_texture *rtex;
2237
2238 if (!state->cbufs[i])
2239 continue;
2240 surf = (struct r600_surface*)state->cbufs[i];
2241 rtex = (struct r600_texture*)surf->base.texture;
2242
2243 p_atomic_dec(&rtex->framebuffers_bound);
2244 }
2245 }
2246
2247 static void si_set_framebuffer_state(struct pipe_context *ctx,
2248 const struct pipe_framebuffer_state *state)
2249 {
2250 struct si_context *sctx = (struct si_context *)ctx;
2251 struct pipe_constant_buffer constbuf = {0};
2252 struct r600_surface *surf = NULL;
2253 struct r600_texture *rtex;
2254 bool old_cb0_is_integer = sctx->framebuffer.cb0_is_integer;
2255 bool old_any_dst_linear = sctx->framebuffer.any_dst_linear;
2256 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2257 int i;
2258
2259 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
2260 if (!sctx->framebuffer.state.cbufs[i])
2261 continue;
2262
2263 rtex = (struct r600_texture*)sctx->framebuffer.state.cbufs[i]->texture;
2264 if (rtex->dcc_gather_statistics)
2265 vi_separate_dcc_stop_query(ctx, rtex);
2266 }
2267
2268 /* Only flush TC when changing the framebuffer state, because
2269 * the only client not using TC that can change textures is
2270 * the framebuffer.
2271 *
2272 * Flush all CB and DB caches here because all buffers can be used
2273 * for write by both TC (with shader image stores) and CB/DB.
2274 */
2275 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
2276 SI_CONTEXT_INV_GLOBAL_L2 |
2277 SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER |
2278 SI_CONTEXT_CS_PARTIAL_FLUSH;
2279
2280 /* Take the maximum of the old and new count. If the new count is lower,
2281 * dirtying is needed to disable the unbound colorbuffers.
2282 */
2283 sctx->framebuffer.dirty_cbufs |=
2284 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2285 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2286
2287 si_dec_framebuffer_counters(&sctx->framebuffer.state);
2288 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2289
2290 sctx->framebuffer.spi_shader_col_format = 0;
2291 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2292 sctx->framebuffer.spi_shader_col_format_blend = 0;
2293 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2294 sctx->framebuffer.color_is_int8 = 0;
2295
2296 sctx->framebuffer.compressed_cb_mask = 0;
2297 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2298 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2299 sctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
2300 util_format_is_pure_integer(state->cbufs[0]->format);
2301 sctx->framebuffer.any_dst_linear = false;
2302
2303 if (sctx->framebuffer.cb0_is_integer != old_cb0_is_integer)
2304 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2305
2306 for (i = 0; i < state->nr_cbufs; i++) {
2307 if (!state->cbufs[i])
2308 continue;
2309
2310 surf = (struct r600_surface*)state->cbufs[i];
2311 rtex = (struct r600_texture*)surf->base.texture;
2312
2313 if (!surf->color_initialized) {
2314 si_initialize_color_surface(sctx, surf);
2315 }
2316
2317 sctx->framebuffer.spi_shader_col_format |=
2318 surf->spi_shader_col_format << (i * 4);
2319 sctx->framebuffer.spi_shader_col_format_alpha |=
2320 surf->spi_shader_col_format_alpha << (i * 4);
2321 sctx->framebuffer.spi_shader_col_format_blend |=
2322 surf->spi_shader_col_format_blend << (i * 4);
2323 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2324 surf->spi_shader_col_format_blend_alpha << (i * 4);
2325
2326 if (surf->color_is_int8)
2327 sctx->framebuffer.color_is_int8 |= 1 << i;
2328
2329 if (rtex->fmask.size && rtex->cmask.size) {
2330 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2331 }
2332
2333 if (surf->level_info->mode == RADEON_SURF_MODE_LINEAR_ALIGNED)
2334 sctx->framebuffer.any_dst_linear = true;
2335
2336 r600_context_add_resource_size(ctx, surf->base.texture);
2337
2338 p_atomic_inc(&rtex->framebuffers_bound);
2339
2340 if (rtex->dcc_gather_statistics) {
2341 /* Dirty tracking must be enabled for DCC usage analysis. */
2342 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2343 vi_separate_dcc_start_query(ctx, rtex);
2344 }
2345 }
2346
2347 if (state->zsbuf) {
2348 surf = (struct r600_surface*)state->zsbuf;
2349
2350 if (!surf->depth_initialized) {
2351 si_init_depth_surface(sctx, surf);
2352 }
2353 r600_context_add_resource_size(ctx, surf->base.texture);
2354 }
2355
2356 si_update_poly_offset_state(sctx);
2357 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2358 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
2359
2360 if (sctx->framebuffer.any_dst_linear != old_any_dst_linear)
2361 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2362
2363 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2364 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2365 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2366
2367 /* Set sample locations as fragment shader constants. */
2368 switch (sctx->framebuffer.nr_samples) {
2369 case 1:
2370 constbuf.user_buffer = sctx->b.sample_locations_1x;
2371 break;
2372 case 2:
2373 constbuf.user_buffer = sctx->b.sample_locations_2x;
2374 break;
2375 case 4:
2376 constbuf.user_buffer = sctx->b.sample_locations_4x;
2377 break;
2378 case 8:
2379 constbuf.user_buffer = sctx->b.sample_locations_8x;
2380 break;
2381 case 16:
2382 constbuf.user_buffer = sctx->b.sample_locations_16x;
2383 break;
2384 default:
2385 R600_ERR("Requested an invalid number of samples %i.\n",
2386 sctx->framebuffer.nr_samples);
2387 assert(0);
2388 }
2389 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2390 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
2391
2392 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
2393 }
2394
2395 sctx->need_check_render_feedback = true;
2396 sctx->do_update_shaders = true;
2397 }
2398
2399 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
2400 {
2401 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2402 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2403 unsigned i, nr_cbufs = state->nr_cbufs;
2404 struct r600_texture *tex = NULL;
2405 struct r600_surface *cb = NULL;
2406 unsigned cb_color_info = 0;
2407
2408 /* Colorbuffers. */
2409 for (i = 0; i < nr_cbufs; i++) {
2410 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
2411 unsigned cb_color_base, cb_color_fmask, cb_color_attrib;
2412 unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
2413
2414 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2415 continue;
2416
2417 cb = (struct r600_surface*)state->cbufs[i];
2418 if (!cb) {
2419 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2420 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2421 continue;
2422 }
2423
2424 tex = (struct r600_texture *)cb->base.texture;
2425 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2426 &tex->resource, RADEON_USAGE_READWRITE,
2427 tex->surface.nsamples > 1 ?
2428 RADEON_PRIO_COLOR_BUFFER_MSAA :
2429 RADEON_PRIO_COLOR_BUFFER);
2430
2431 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2432 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2433 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2434 RADEON_PRIO_CMASK);
2435 }
2436
2437 if (tex->dcc_separate_buffer)
2438 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2439 tex->dcc_separate_buffer,
2440 RADEON_USAGE_READWRITE,
2441 RADEON_PRIO_DCC);
2442
2443 /* Compute mutable surface parameters. */
2444 pitch_tile_max = cb->level_info->nblk_x / 8 - 1;
2445 slice_tile_max = cb->level_info->nblk_x *
2446 cb->level_info->nblk_y / 64 - 1;
2447 tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false);
2448
2449 cb_color_base = (tex->resource.gpu_address + cb->level_info->offset) >> 8;
2450 cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
2451 cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
2452 cb_color_attrib = cb->cb_color_attrib |
2453 S_028C74_TILE_MODE_INDEX(tile_mode_index);
2454
2455 if (tex->fmask.size) {
2456 if (sctx->b.chip_class >= CIK)
2457 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->fmask.pitch_in_pixels / 8 - 1);
2458 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->fmask.tile_mode_index);
2459 cb_color_fmask = (tex->resource.gpu_address + tex->fmask.offset) >> 8;
2460 cb_color_fmask_slice = S_028C88_TILE_MAX(tex->fmask.slice_tile_max);
2461 } else {
2462 /* This must be set for fast clear to work without FMASK. */
2463 if (sctx->b.chip_class >= CIK)
2464 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
2465 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
2466 cb_color_fmask = cb_color_base;
2467 cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
2468 }
2469
2470 cb_color_info = cb->cb_color_info | tex->cb_color_info;
2471
2472 if (tex->dcc_offset && cb->level_info->dcc_enabled) {
2473 bool is_msaa_resolve_dst = state->cbufs[0] &&
2474 state->cbufs[0]->texture->nr_samples > 1 &&
2475 state->cbufs[1] == &cb->base &&
2476 state->cbufs[1]->texture->nr_samples <= 1;
2477
2478 if (!is_msaa_resolve_dst)
2479 cb_color_info |= S_028C70_DCC_ENABLE(1);
2480 }
2481
2482 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
2483 sctx->b.chip_class >= VI ? 14 : 13);
2484 radeon_emit(cs, cb_color_base); /* R_028C60_CB_COLOR0_BASE */
2485 radeon_emit(cs, cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
2486 radeon_emit(cs, cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
2487 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
2488 radeon_emit(cs, cb_color_info); /* R_028C70_CB_COLOR0_INFO */
2489 radeon_emit(cs, cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
2490 radeon_emit(cs, cb->cb_dcc_control); /* R_028C78_CB_COLOR0_DCC_CONTROL */
2491 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
2492 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
2493 radeon_emit(cs, cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
2494 radeon_emit(cs, cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
2495 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
2496 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
2497
2498 if (sctx->b.chip_class >= VI) /* R_028C94_CB_COLOR0_DCC_BASE */
2499 radeon_emit(cs, ((!tex->dcc_separate_buffer ? tex->resource.gpu_address : 0) +
2500 tex->dcc_offset +
2501 tex->surface.level[cb->base.u.tex.level].dcc_offset) >> 8);
2502 }
2503 for (; i < 8 ; i++)
2504 if (sctx->framebuffer.dirty_cbufs & (1 << i))
2505 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
2506
2507 /* ZS buffer. */
2508 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
2509 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
2510 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
2511
2512 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2513 &rtex->resource, RADEON_USAGE_READWRITE,
2514 zb->base.texture->nr_samples > 1 ?
2515 RADEON_PRIO_DEPTH_BUFFER_MSAA :
2516 RADEON_PRIO_DEPTH_BUFFER);
2517
2518 if (zb->db_htile_data_base) {
2519 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2520 rtex->htile_buffer, RADEON_USAGE_READWRITE,
2521 RADEON_PRIO_HTILE);
2522 }
2523
2524 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
2525 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
2526
2527 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
2528 radeon_emit(cs, zb->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
2529 radeon_emit(cs, zb->db_z_info | /* R_028040_DB_Z_INFO */
2530 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
2531 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
2532 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
2533 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
2534 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
2535 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
2536 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
2537 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
2538
2539 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
2540 radeon_emit(cs, rtex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
2541 radeon_emit(cs, fui(rtex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
2542
2543 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
2544 } else if (sctx->framebuffer.dirty_zsbuf) {
2545 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
2546 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
2547 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
2548 }
2549
2550 /* Framebuffer dimensions. */
2551 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2552 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2553 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
2554
2555 sctx->framebuffer.dirty_cbufs = 0;
2556 sctx->framebuffer.dirty_zsbuf = false;
2557 }
2558
2559 static void si_emit_msaa_sample_locs(struct si_context *sctx,
2560 struct r600_atom *atom)
2561 {
2562 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2563 unsigned nr_samples = sctx->framebuffer.nr_samples;
2564
2565 /* Smoothing (only possible with nr_samples == 1) uses the same
2566 * sample locations as the MSAA it simulates.
2567 */
2568 if (nr_samples <= 1 && sctx->smoothing_enabled)
2569 nr_samples = SI_NUM_SMOOTH_AA_SAMPLES;
2570
2571 /* On Polaris, the small primitive filter uses the sample locations
2572 * even when MSAA is off, so we need to make sure they're set to 0.
2573 */
2574 if ((nr_samples > 1 || sctx->b.family >= CHIP_POLARIS10) &&
2575 (nr_samples != sctx->msaa_sample_locs.nr_samples)) {
2576 sctx->msaa_sample_locs.nr_samples = nr_samples;
2577 cayman_emit_msaa_sample_locs(cs, nr_samples);
2578 }
2579
2580 if (sctx->b.family >= CHIP_POLARIS10) {
2581 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
2582 unsigned small_prim_filter_cntl =
2583 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
2584 S_028830_LINE_FILTER_DISABLE(1); /* line bug */
2585
2586 /* The alternative of setting sample locations to 0 would
2587 * require a DB flush to avoid Z errors, see
2588 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
2589 */
2590 if (sctx->framebuffer.nr_samples > 1 && rs && !rs->multisample_enable)
2591 small_prim_filter_cntl &= C_028830_SMALL_PRIM_FILTER_ENABLE;
2592
2593 radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
2594 small_prim_filter_cntl);
2595 }
2596 }
2597
2598 static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom)
2599 {
2600 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2601 unsigned num_tile_pipes = sctx->screen->b.info.num_tile_pipes;
2602 /* 33% faster rendering to linear color buffers */
2603 bool dst_is_linear = sctx->framebuffer.any_dst_linear;
2604 unsigned sc_mode_cntl_1 =
2605 S_028A4C_WALK_SIZE(dst_is_linear) |
2606 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear) |
2607 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
2608 /* always 1: */
2609 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
2610 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
2611 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
2612 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
2613 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
2614 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
2615
2616 cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples,
2617 sctx->ps_iter_samples,
2618 sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0,
2619 sc_mode_cntl_1);
2620 }
2621
2622 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
2623 {
2624 struct si_context *sctx = (struct si_context *)ctx;
2625
2626 if (sctx->ps_iter_samples == min_samples)
2627 return;
2628
2629 sctx->ps_iter_samples = min_samples;
2630 sctx->do_update_shaders = true;
2631
2632 if (sctx->framebuffer.nr_samples > 1)
2633 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2634 }
2635
2636 /*
2637 * Samplers
2638 */
2639
2640 /**
2641 * Build the sampler view descriptor for a buffer texture.
2642 * @param state 256-bit descriptor; only the high 128 bits are filled in
2643 */
2644 void
2645 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
2646 enum pipe_format format,
2647 unsigned offset, unsigned size,
2648 uint32_t *state)
2649 {
2650 const struct util_format_description *desc;
2651 int first_non_void;
2652 uint64_t va;
2653 unsigned stride;
2654 unsigned num_records;
2655 unsigned num_format, data_format;
2656
2657 desc = util_format_description(format);
2658 first_non_void = util_format_get_first_non_void_channel(format);
2659 stride = desc->block.bits / 8;
2660 va = buf->gpu_address + offset;
2661 num_format = si_translate_buffer_numformat(&screen->b.b, desc, first_non_void);
2662 data_format = si_translate_buffer_dataformat(&screen->b.b, desc, first_non_void);
2663
2664 num_records = size / stride;
2665 num_records = MIN2(num_records, buf->b.b.width0 / stride);
2666
2667 if (screen->b.chip_class >= VI)
2668 num_records *= stride;
2669
2670 state[4] = va;
2671 state[5] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
2672 S_008F04_STRIDE(stride);
2673 state[6] = num_records;
2674 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2675 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2676 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2677 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2678 S_008F0C_NUM_FORMAT(num_format) |
2679 S_008F0C_DATA_FORMAT(data_format);
2680 }
2681
2682 /**
2683 * Build the sampler view descriptor for a texture.
2684 */
2685 void
2686 si_make_texture_descriptor(struct si_screen *screen,
2687 struct r600_texture *tex,
2688 bool sampler,
2689 enum pipe_texture_target target,
2690 enum pipe_format pipe_format,
2691 const unsigned char state_swizzle[4],
2692 unsigned first_level, unsigned last_level,
2693 unsigned first_layer, unsigned last_layer,
2694 unsigned width, unsigned height, unsigned depth,
2695 uint32_t *state,
2696 uint32_t *fmask_state)
2697 {
2698 struct pipe_resource *res = &tex->resource.b.b;
2699 const struct util_format_description *desc;
2700 unsigned char swizzle[4];
2701 int first_non_void;
2702 unsigned num_format, data_format, type;
2703 uint64_t va;
2704
2705 desc = util_format_description(pipe_format);
2706
2707 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2708 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2709 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2710
2711 switch (pipe_format) {
2712 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2713 case PIPE_FORMAT_X24S8_UINT:
2714 case PIPE_FORMAT_X32_S8X24_UINT:
2715 case PIPE_FORMAT_X8Z24_UNORM:
2716 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
2717 break;
2718 default:
2719 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
2720 }
2721 } else {
2722 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2723 }
2724
2725 first_non_void = util_format_get_first_non_void_channel(pipe_format);
2726
2727 switch (pipe_format) {
2728 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2729 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2730 break;
2731 default:
2732 if (first_non_void < 0) {
2733 if (util_format_is_compressed(pipe_format)) {
2734 switch (pipe_format) {
2735 case PIPE_FORMAT_DXT1_SRGB:
2736 case PIPE_FORMAT_DXT1_SRGBA:
2737 case PIPE_FORMAT_DXT3_SRGBA:
2738 case PIPE_FORMAT_DXT5_SRGBA:
2739 case PIPE_FORMAT_BPTC_SRGBA:
2740 case PIPE_FORMAT_ETC2_SRGB8:
2741 case PIPE_FORMAT_ETC2_SRGB8A1:
2742 case PIPE_FORMAT_ETC2_SRGBA8:
2743 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2744 break;
2745 case PIPE_FORMAT_RGTC1_SNORM:
2746 case PIPE_FORMAT_LATC1_SNORM:
2747 case PIPE_FORMAT_RGTC2_SNORM:
2748 case PIPE_FORMAT_LATC2_SNORM:
2749 case PIPE_FORMAT_ETC2_R11_SNORM:
2750 case PIPE_FORMAT_ETC2_RG11_SNORM:
2751 /* implies float, so use SNORM/UNORM to determine
2752 whether data is signed or not */
2753 case PIPE_FORMAT_BPTC_RGB_FLOAT:
2754 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2755 break;
2756 default:
2757 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2758 break;
2759 }
2760 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
2761 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2762 } else {
2763 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2764 }
2765 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
2766 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2767 } else {
2768 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2769
2770 switch (desc->channel[first_non_void].type) {
2771 case UTIL_FORMAT_TYPE_FLOAT:
2772 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2773 break;
2774 case UTIL_FORMAT_TYPE_SIGNED:
2775 if (desc->channel[first_non_void].normalized)
2776 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2777 else if (desc->channel[first_non_void].pure_integer)
2778 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
2779 else
2780 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
2781 break;
2782 case UTIL_FORMAT_TYPE_UNSIGNED:
2783 if (desc->channel[first_non_void].normalized)
2784 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2785 else if (desc->channel[first_non_void].pure_integer)
2786 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
2787 else
2788 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
2789 }
2790 }
2791 }
2792
2793 data_format = si_translate_texformat(&screen->b.b, pipe_format, desc, first_non_void);
2794 if (data_format == ~0) {
2795 data_format = 0;
2796 }
2797
2798 if (!sampler &&
2799 (res->target == PIPE_TEXTURE_CUBE ||
2800 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
2801 res->target == PIPE_TEXTURE_3D)) {
2802 /* For the purpose of shader images, treat cube maps and 3D
2803 * textures as 2D arrays. For 3D textures, the address
2804 * calculations for mipmaps are different, so we rely on the
2805 * caller to effectively disable mipmaps.
2806 */
2807 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
2808
2809 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
2810 } else {
2811 type = si_tex_dim(res->target, target, res->nr_samples);
2812 }
2813
2814 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
2815 height = 1;
2816 depth = res->array_size;
2817 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
2818 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
2819 if (sampler || res->target != PIPE_TEXTURE_3D)
2820 depth = res->array_size;
2821 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
2822 depth = res->array_size / 6;
2823
2824 state[0] = 0;
2825 state[1] = (S_008F14_DATA_FORMAT(data_format) |
2826 S_008F14_NUM_FORMAT(num_format));
2827 state[2] = (S_008F18_WIDTH(width - 1) |
2828 S_008F18_HEIGHT(height - 1));
2829 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2830 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2831 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2832 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2833 S_008F1C_BASE_LEVEL(res->nr_samples > 1 ?
2834 0 : first_level) |
2835 S_008F1C_LAST_LEVEL(res->nr_samples > 1 ?
2836 util_logbase2(res->nr_samples) :
2837 last_level) |
2838 S_008F1C_POW2_PAD(res->last_level > 0) |
2839 S_008F1C_TYPE(type));
2840 state[4] = S_008F20_DEPTH(depth - 1);
2841 state[5] = (S_008F24_BASE_ARRAY(first_layer) |
2842 S_008F24_LAST_ARRAY(last_layer));
2843 state[6] = 0;
2844 state[7] = 0;
2845
2846 if (tex->dcc_offset) {
2847 unsigned swap = r600_translate_colorswap(pipe_format, false);
2848
2849 state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
2850 } else {
2851 /* The last dword is unused by hw. The shader uses it to clear
2852 * bits in the first dword of sampler state.
2853 */
2854 if (screen->b.chip_class <= CIK && res->nr_samples <= 1) {
2855 if (first_level == last_level)
2856 state[7] = C_008F30_MAX_ANISO_RATIO;
2857 else
2858 state[7] = 0xffffffff;
2859 }
2860 }
2861
2862 /* Initialize the sampler view for FMASK. */
2863 if (tex->fmask.size) {
2864 uint32_t fmask_format;
2865
2866 va = tex->resource.gpu_address + tex->fmask.offset;
2867
2868 switch (res->nr_samples) {
2869 case 2:
2870 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
2871 break;
2872 case 4:
2873 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
2874 break;
2875 case 8:
2876 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
2877 break;
2878 default:
2879 assert(0);
2880 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
2881 }
2882
2883 fmask_state[0] = va >> 8;
2884 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
2885 S_008F14_DATA_FORMAT(fmask_format) |
2886 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT);
2887 fmask_state[2] = S_008F18_WIDTH(width - 1) |
2888 S_008F18_HEIGHT(height - 1);
2889 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
2890 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
2891 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
2892 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
2893 S_008F1C_TILING_INDEX(tex->fmask.tile_mode_index) |
2894 S_008F1C_TYPE(si_tex_dim(res->target, target, 0));
2895 fmask_state[4] = S_008F20_DEPTH(depth - 1) |
2896 S_008F20_PITCH(tex->fmask.pitch_in_pixels - 1);
2897 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer) |
2898 S_008F24_LAST_ARRAY(last_layer);
2899 fmask_state[6] = 0;
2900 fmask_state[7] = 0;
2901 }
2902 }
2903
2904 /**
2905 * Create a sampler view.
2906 *
2907 * @param ctx context
2908 * @param texture texture
2909 * @param state sampler view template
2910 * @param width0 width0 override (for compressed textures as int)
2911 * @param height0 height0 override (for compressed textures as int)
2912 * @param force_level set the base address to the level (for compressed textures)
2913 */
2914 struct pipe_sampler_view *
2915 si_create_sampler_view_custom(struct pipe_context *ctx,
2916 struct pipe_resource *texture,
2917 const struct pipe_sampler_view *state,
2918 unsigned width0, unsigned height0,
2919 unsigned force_level)
2920 {
2921 struct si_context *sctx = (struct si_context*)ctx;
2922 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
2923 struct r600_texture *tmp = (struct r600_texture*)texture;
2924 unsigned base_level, first_level, last_level;
2925 unsigned char state_swizzle[4];
2926 unsigned height, depth, width;
2927 unsigned last_layer = state->u.tex.last_layer;
2928 enum pipe_format pipe_format;
2929 const struct radeon_surf_level *surflevel;
2930
2931 if (!view)
2932 return NULL;
2933
2934 /* initialize base object */
2935 view->base = *state;
2936 view->base.texture = NULL;
2937 view->base.reference.count = 1;
2938 view->base.context = ctx;
2939
2940 /* NULL resource, obey swizzle (only ZERO and ONE make sense). */
2941 if (!texture) {
2942 view->state[3] = S_008F1C_DST_SEL_X(si_map_swizzle(state->swizzle_r)) |
2943 S_008F1C_DST_SEL_Y(si_map_swizzle(state->swizzle_g)) |
2944 S_008F1C_DST_SEL_Z(si_map_swizzle(state->swizzle_b)) |
2945 S_008F1C_DST_SEL_W(si_map_swizzle(state->swizzle_a)) |
2946 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D);
2947 return &view->base;
2948 }
2949
2950 pipe_resource_reference(&view->base.texture, texture);
2951
2952 if (state->format == PIPE_FORMAT_X24S8_UINT ||
2953 state->format == PIPE_FORMAT_S8X24_UINT ||
2954 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
2955 state->format == PIPE_FORMAT_S8_UINT)
2956 view->is_stencil_sampler = true;
2957
2958 /* Buffer resource. */
2959 if (texture->target == PIPE_BUFFER) {
2960 si_make_buffer_descriptor(sctx->screen,
2961 (struct r600_resource *)texture,
2962 state->format,
2963 state->u.buf.offset,
2964 state->u.buf.size,
2965 view->state);
2966
2967 LIST_ADDTAIL(&view->list, &sctx->b.texture_buffers);
2968 return &view->base;
2969 }
2970
2971 state_swizzle[0] = state->swizzle_r;
2972 state_swizzle[1] = state->swizzle_g;
2973 state_swizzle[2] = state->swizzle_b;
2974 state_swizzle[3] = state->swizzle_a;
2975
2976 base_level = 0;
2977 first_level = state->u.tex.first_level;
2978 last_level = state->u.tex.last_level;
2979 width = width0;
2980 height = height0;
2981 depth = texture->depth0;
2982
2983 if (force_level) {
2984 assert(force_level == first_level &&
2985 force_level == last_level);
2986 base_level = force_level;
2987 first_level = 0;
2988 last_level = 0;
2989 width = u_minify(width, force_level);
2990 height = u_minify(height, force_level);
2991 depth = u_minify(depth, force_level);
2992 }
2993
2994 /* This is not needed if state trackers set last_layer correctly. */
2995 if (state->target == PIPE_TEXTURE_1D ||
2996 state->target == PIPE_TEXTURE_2D ||
2997 state->target == PIPE_TEXTURE_RECT ||
2998 state->target == PIPE_TEXTURE_CUBE)
2999 last_layer = state->u.tex.first_layer;
3000
3001 /* Texturing with separate depth and stencil. */
3002 pipe_format = state->format;
3003
3004 /* Depth/stencil texturing sometimes needs separate texture. */
3005 if (tmp->is_depth && !r600_can_sample_zs(tmp, view->is_stencil_sampler)) {
3006 if (!tmp->flushed_depth_texture &&
3007 !r600_init_flushed_depth_texture(ctx, texture, NULL)) {
3008 pipe_resource_reference(&view->base.texture, NULL);
3009 FREE(view);
3010 return NULL;
3011 }
3012
3013 assert(tmp->flushed_depth_texture);
3014
3015 /* Override format for the case where the flushed texture
3016 * contains only Z or only S.
3017 */
3018 if (tmp->flushed_depth_texture->resource.b.b.format != tmp->resource.b.b.format)
3019 pipe_format = tmp->flushed_depth_texture->resource.b.b.format;
3020
3021 tmp = tmp->flushed_depth_texture;
3022 }
3023
3024 surflevel = tmp->surface.level;
3025
3026 if (tmp->db_compatible) {
3027 switch (pipe_format) {
3028 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
3029 pipe_format = PIPE_FORMAT_Z32_FLOAT;
3030 break;
3031 case PIPE_FORMAT_X8Z24_UNORM:
3032 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3033 /* Z24 is always stored like this for DB
3034 * compatibility.
3035 */
3036 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
3037 break;
3038 case PIPE_FORMAT_X24S8_UINT:
3039 case PIPE_FORMAT_S8X24_UINT:
3040 case PIPE_FORMAT_X32_S8X24_UINT:
3041 pipe_format = PIPE_FORMAT_S8_UINT;
3042 surflevel = tmp->surface.stencil_level;
3043 break;
3044 default:;
3045 }
3046 }
3047
3048 si_make_texture_descriptor(sctx->screen, tmp, true,
3049 state->target, pipe_format, state_swizzle,
3050 first_level, last_level,
3051 state->u.tex.first_layer, last_layer,
3052 width, height, depth,
3053 view->state, view->fmask_state);
3054
3055 view->base_level_info = &surflevel[base_level];
3056 view->base_level = base_level;
3057 view->block_width = util_format_get_blockwidth(pipe_format);
3058 return &view->base;
3059 }
3060
3061 static struct pipe_sampler_view *
3062 si_create_sampler_view(struct pipe_context *ctx,
3063 struct pipe_resource *texture,
3064 const struct pipe_sampler_view *state)
3065 {
3066 return si_create_sampler_view_custom(ctx, texture, state,
3067 texture ? texture->width0 : 0,
3068 texture ? texture->height0 : 0, 0);
3069 }
3070
3071 static void si_sampler_view_destroy(struct pipe_context *ctx,
3072 struct pipe_sampler_view *state)
3073 {
3074 struct si_sampler_view *view = (struct si_sampler_view *)state;
3075
3076 if (state->texture && state->texture->target == PIPE_BUFFER)
3077 LIST_DELINIT(&view->list);
3078
3079 pipe_resource_reference(&state->texture, NULL);
3080 FREE(view);
3081 }
3082
3083 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
3084 {
3085 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
3086 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
3087 (linear_filter &&
3088 (wrap == PIPE_TEX_WRAP_CLAMP ||
3089 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
3090 }
3091
3092 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
3093 {
3094 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
3095 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
3096
3097 return (state->border_color.ui[0] || state->border_color.ui[1] ||
3098 state->border_color.ui[2] || state->border_color.ui[3]) &&
3099 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
3100 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
3101 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
3102 }
3103
3104 static void *si_create_sampler_state(struct pipe_context *ctx,
3105 const struct pipe_sampler_state *state)
3106 {
3107 struct si_context *sctx = (struct si_context *)ctx;
3108 struct r600_common_screen *rscreen = sctx->b.screen;
3109 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
3110 unsigned border_color_type, border_color_index = 0;
3111 unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
3112 : state->max_anisotropy;
3113 unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso);
3114
3115 if (!rstate) {
3116 return NULL;
3117 }
3118
3119 if (!sampler_state_needs_border_color(state))
3120 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3121 else if (state->border_color.f[0] == 0 &&
3122 state->border_color.f[1] == 0 &&
3123 state->border_color.f[2] == 0 &&
3124 state->border_color.f[3] == 0)
3125 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3126 else if (state->border_color.f[0] == 0 &&
3127 state->border_color.f[1] == 0 &&
3128 state->border_color.f[2] == 0 &&
3129 state->border_color.f[3] == 1)
3130 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3131 else if (state->border_color.f[0] == 1 &&
3132 state->border_color.f[1] == 1 &&
3133 state->border_color.f[2] == 1 &&
3134 state->border_color.f[3] == 1)
3135 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3136 else {
3137 int i;
3138
3139 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
3140
3141 /* Check if the border has been uploaded already. */
3142 for (i = 0; i < sctx->border_color_count; i++)
3143 if (memcmp(&sctx->border_color_table[i], &state->border_color,
3144 sizeof(state->border_color)) == 0)
3145 break;
3146
3147 if (i >= SI_MAX_BORDER_COLORS) {
3148 /* Getting 4096 unique border colors is very unlikely. */
3149 fprintf(stderr, "radeonsi: The border color table is full. "
3150 "Any new border colors will be just black. "
3151 "Please file a bug.\n");
3152 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3153 } else {
3154 if (i == sctx->border_color_count) {
3155 /* Upload a new border color. */
3156 memcpy(&sctx->border_color_table[i], &state->border_color,
3157 sizeof(state->border_color));
3158 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
3159 &state->border_color,
3160 sizeof(state->border_color));
3161 sctx->border_color_count++;
3162 }
3163
3164 border_color_index = i;
3165 }
3166 }
3167
3168 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
3169 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
3170 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
3171 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3172 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
3173 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
3174 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
3175 S_008F30_COMPAT_MODE(sctx->b.chip_class >= VI));
3176 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
3177 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
3178 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
3179 S_008F38_XY_MAG_FILTER(eg_tex_filter(state->mag_img_filter, max_aniso)) |
3180 S_008F38_XY_MIN_FILTER(eg_tex_filter(state->min_img_filter, max_aniso)) |
3181 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
3182 S_008F38_MIP_POINT_PRECLAMP(1) |
3183 S_008F38_DISABLE_LSB_CEIL(1) |
3184 S_008F38_FILTER_PREC_FIX(1) |
3185 S_008F38_ANISO_OVERRIDE(sctx->b.chip_class >= VI));
3186 rstate->val[3] = S_008F3C_BORDER_COLOR_PTR(border_color_index) |
3187 S_008F3C_BORDER_COLOR_TYPE(border_color_type);
3188 return rstate;
3189 }
3190
3191 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
3192 {
3193 struct si_context *sctx = (struct si_context *)ctx;
3194
3195 if (sctx->sample_mask.sample_mask == (uint16_t)sample_mask)
3196 return;
3197
3198 sctx->sample_mask.sample_mask = sample_mask;
3199 si_mark_atom_dirty(sctx, &sctx->sample_mask.atom);
3200 }
3201
3202 static void si_emit_sample_mask(struct si_context *sctx, struct r600_atom *atom)
3203 {
3204 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
3205 unsigned mask = sctx->sample_mask.sample_mask;
3206
3207 /* Needed for line and polygon smoothing as well as for the Polaris
3208 * small primitive filter. We expect the state tracker to take care of
3209 * this for us.
3210 */
3211 assert(mask == 0xffff || sctx->framebuffer.nr_samples > 1 ||
3212 (mask & 1 && sctx->blitter->running));
3213
3214 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3215 radeon_emit(cs, mask | (mask << 16));
3216 radeon_emit(cs, mask | (mask << 16));
3217 }
3218
3219 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
3220 {
3221 free(state);
3222 }
3223
3224 /*
3225 * Vertex elements & buffers
3226 */
3227
3228 static void *si_create_vertex_elements(struct pipe_context *ctx,
3229 unsigned count,
3230 const struct pipe_vertex_element *elements)
3231 {
3232 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
3233 int i;
3234
3235 assert(count <= SI_MAX_ATTRIBS);
3236 if (!v)
3237 return NULL;
3238
3239 v->count = count;
3240 for (i = 0; i < count; ++i) {
3241 const struct util_format_description *desc;
3242 unsigned data_format, num_format;
3243 int first_non_void;
3244
3245 desc = util_format_description(elements[i].src_format);
3246 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
3247 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
3248 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
3249
3250 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3251 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3252 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3253 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
3254 S_008F0C_NUM_FORMAT(num_format) |
3255 S_008F0C_DATA_FORMAT(data_format);
3256 v->format_size[i] = desc->block.bits / 8;
3257 }
3258 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
3259
3260 return v;
3261 }
3262
3263 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
3264 {
3265 struct si_context *sctx = (struct si_context *)ctx;
3266 struct si_vertex_element *v = (struct si_vertex_element*)state;
3267
3268 sctx->vertex_elements = v;
3269 sctx->vertex_buffers_dirty = true;
3270 sctx->do_update_shaders = true;
3271 }
3272
3273 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
3274 {
3275 struct si_context *sctx = (struct si_context *)ctx;
3276
3277 if (sctx->vertex_elements == state)
3278 sctx->vertex_elements = NULL;
3279 FREE(state);
3280 }
3281
3282 static void si_set_vertex_buffers(struct pipe_context *ctx,
3283 unsigned start_slot, unsigned count,
3284 const struct pipe_vertex_buffer *buffers)
3285 {
3286 struct si_context *sctx = (struct si_context *)ctx;
3287 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
3288 int i;
3289
3290 assert(start_slot + count <= ARRAY_SIZE(sctx->vertex_buffer));
3291
3292 if (buffers) {
3293 for (i = 0; i < count; i++) {
3294 const struct pipe_vertex_buffer *src = buffers + i;
3295 struct pipe_vertex_buffer *dsti = dst + i;
3296
3297 pipe_resource_reference(&dsti->buffer, src->buffer);
3298 dsti->buffer_offset = src->buffer_offset;
3299 dsti->stride = src->stride;
3300 r600_context_add_resource_size(ctx, src->buffer);
3301 }
3302 } else {
3303 for (i = 0; i < count; i++) {
3304 pipe_resource_reference(&dst[i].buffer, NULL);
3305 }
3306 }
3307 sctx->vertex_buffers_dirty = true;
3308 }
3309
3310 static void si_set_index_buffer(struct pipe_context *ctx,
3311 const struct pipe_index_buffer *ib)
3312 {
3313 struct si_context *sctx = (struct si_context *)ctx;
3314
3315 if (ib) {
3316 pipe_resource_reference(&sctx->index_buffer.buffer, ib->buffer);
3317 memcpy(&sctx->index_buffer, ib, sizeof(*ib));
3318 r600_context_add_resource_size(ctx, ib->buffer);
3319 } else {
3320 pipe_resource_reference(&sctx->index_buffer.buffer, NULL);
3321 }
3322 }
3323
3324 /*
3325 * Misc
3326 */
3327
3328 static void si_set_tess_state(struct pipe_context *ctx,
3329 const float default_outer_level[4],
3330 const float default_inner_level[2])
3331 {
3332 struct si_context *sctx = (struct si_context *)ctx;
3333 struct pipe_constant_buffer cb;
3334 float array[8];
3335
3336 memcpy(array, default_outer_level, sizeof(float) * 4);
3337 memcpy(array+4, default_inner_level, sizeof(float) * 2);
3338
3339 cb.buffer = NULL;
3340 cb.user_buffer = NULL;
3341 cb.buffer_size = sizeof(array);
3342
3343 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
3344 (void*)array, sizeof(array),
3345 &cb.buffer_offset);
3346
3347 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
3348 pipe_resource_reference(&cb.buffer, NULL);
3349 }
3350
3351 static void si_texture_barrier(struct pipe_context *ctx)
3352 {
3353 struct si_context *sctx = (struct si_context *)ctx;
3354
3355 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
3356 SI_CONTEXT_INV_GLOBAL_L2 |
3357 SI_CONTEXT_FLUSH_AND_INV_CB |
3358 SI_CONTEXT_CS_PARTIAL_FLUSH;
3359 }
3360
3361 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
3362 {
3363 struct si_context *sctx = (struct si_context *)ctx;
3364
3365 /* Subsequent commands must wait for all shader invocations to
3366 * complete. */
3367 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
3368 SI_CONTEXT_CS_PARTIAL_FLUSH;
3369
3370 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
3371 sctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 |
3372 SI_CONTEXT_INV_VMEM_L1;
3373
3374 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
3375 PIPE_BARRIER_SHADER_BUFFER |
3376 PIPE_BARRIER_TEXTURE |
3377 PIPE_BARRIER_IMAGE |
3378 PIPE_BARRIER_STREAMOUT_BUFFER |
3379 PIPE_BARRIER_GLOBAL_BUFFER)) {
3380 /* As far as I can tell, L1 contents are written back to L2
3381 * automatically at end of shader, but the contents of other
3382 * L1 caches might still be stale. */
3383 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
3384 }
3385
3386 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
3387 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
3388
3389 /* Indices are read through TC L2 since VI. */
3390 if (sctx->screen->b.chip_class <= CIK)
3391 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
3392 }
3393
3394 if (flags & PIPE_BARRIER_FRAMEBUFFER)
3395 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER;
3396
3397 if (flags & (PIPE_BARRIER_MAPPED_BUFFER |
3398 PIPE_BARRIER_FRAMEBUFFER |
3399 PIPE_BARRIER_INDIRECT_BUFFER)) {
3400 /* Not sure if INV_GLOBAL_L2 is the best thing here.
3401 *
3402 * We need to make sure that TC L1 & L2 are written back to
3403 * memory, because neither CPU accesses nor CB fetches consider
3404 * TC, but there's no need to invalidate any TC cache lines. */
3405 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
3406 }
3407 }
3408
3409 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
3410 {
3411 struct pipe_blend_state blend;
3412
3413 memset(&blend, 0, sizeof(blend));
3414 blend.independent_blend_enable = true;
3415 blend.rt[0].colormask = 0xf;
3416 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
3417 }
3418
3419 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
3420 bool include_draw_vbo)
3421 {
3422 si_need_cs_space((struct si_context*)ctx);
3423 }
3424
3425 static void si_init_config(struct si_context *sctx);
3426
3427 void si_init_state_functions(struct si_context *sctx)
3428 {
3429 si_init_external_atom(sctx, &sctx->b.render_cond_atom, &sctx->atoms.s.render_cond);
3430 si_init_external_atom(sctx, &sctx->b.streamout.begin_atom, &sctx->atoms.s.streamout_begin);
3431 si_init_external_atom(sctx, &sctx->b.streamout.enable_atom, &sctx->atoms.s.streamout_enable);
3432 si_init_external_atom(sctx, &sctx->b.scissors.atom, &sctx->atoms.s.scissors);
3433 si_init_external_atom(sctx, &sctx->b.viewports.atom, &sctx->atoms.s.viewports);
3434
3435 si_init_atom(sctx, &sctx->cache_flush, &sctx->atoms.s.cache_flush, si_emit_cache_flush);
3436 si_init_atom(sctx, &sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state);
3437 si_init_atom(sctx, &sctx->msaa_sample_locs.atom, &sctx->atoms.s.msaa_sample_locs, si_emit_msaa_sample_locs);
3438 si_init_atom(sctx, &sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state);
3439 si_init_atom(sctx, &sctx->msaa_config, &sctx->atoms.s.msaa_config, si_emit_msaa_config);
3440 si_init_atom(sctx, &sctx->sample_mask.atom, &sctx->atoms.s.sample_mask, si_emit_sample_mask);
3441 si_init_atom(sctx, &sctx->cb_render_state, &sctx->atoms.s.cb_render_state, si_emit_cb_render_state);
3442 si_init_atom(sctx, &sctx->blend_color.atom, &sctx->atoms.s.blend_color, si_emit_blend_color);
3443 si_init_atom(sctx, &sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs);
3444 si_init_atom(sctx, &sctx->clip_state.atom, &sctx->atoms.s.clip_state, si_emit_clip_state);
3445 si_init_atom(sctx, &sctx->stencil_ref.atom, &sctx->atoms.s.stencil_ref, si_emit_stencil_ref);
3446
3447 sctx->b.b.create_blend_state = si_create_blend_state;
3448 sctx->b.b.bind_blend_state = si_bind_blend_state;
3449 sctx->b.b.delete_blend_state = si_delete_blend_state;
3450 sctx->b.b.set_blend_color = si_set_blend_color;
3451
3452 sctx->b.b.create_rasterizer_state = si_create_rs_state;
3453 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
3454 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
3455
3456 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
3457 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
3458 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
3459
3460 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
3461 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
3462 sctx->custom_blend_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
3463 sctx->custom_blend_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
3464 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
3465
3466 sctx->b.b.set_clip_state = si_set_clip_state;
3467 sctx->b.b.set_stencil_ref = si_set_stencil_ref;
3468
3469 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
3470 sctx->b.b.get_sample_position = cayman_get_sample_position;
3471
3472 sctx->b.b.create_sampler_state = si_create_sampler_state;
3473 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
3474
3475 sctx->b.b.create_sampler_view = si_create_sampler_view;
3476 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
3477
3478 sctx->b.b.set_sample_mask = si_set_sample_mask;
3479
3480 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
3481 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
3482 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
3483 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
3484 sctx->b.b.set_index_buffer = si_set_index_buffer;
3485
3486 sctx->b.b.texture_barrier = si_texture_barrier;
3487 sctx->b.b.memory_barrier = si_memory_barrier;
3488 sctx->b.b.set_min_samples = si_set_min_samples;
3489 sctx->b.b.set_tess_state = si_set_tess_state;
3490
3491 sctx->b.b.set_active_query_state = si_set_active_query_state;
3492 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
3493 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
3494
3495 sctx->b.b.draw_vbo = si_draw_vbo;
3496
3497 si_init_config(sctx);
3498 }
3499
3500 static uint32_t si_get_bo_metadata_word1(struct r600_common_screen *rscreen)
3501 {
3502 return (ATI_VENDOR_ID << 16) | rscreen->info.pci_id;
3503 }
3504
3505 static void si_query_opaque_metadata(struct r600_common_screen *rscreen,
3506 struct r600_texture *rtex,
3507 struct radeon_bo_metadata *md)
3508 {
3509 struct si_screen *sscreen = (struct si_screen*)rscreen;
3510 struct pipe_resource *res = &rtex->resource.b.b;
3511 static const unsigned char swizzle[] = {
3512 PIPE_SWIZZLE_X,
3513 PIPE_SWIZZLE_Y,
3514 PIPE_SWIZZLE_Z,
3515 PIPE_SWIZZLE_W
3516 };
3517 uint32_t desc[8], i;
3518 bool is_array = util_resource_is_array_texture(res);
3519
3520 /* DRM 2.x.x doesn't support this. */
3521 if (rscreen->info.drm_major != 3)
3522 return;
3523
3524 assert(rtex->dcc_separate_buffer == NULL);
3525 assert(rtex->fmask.size == 0);
3526
3527 /* Metadata image format format version 1:
3528 * [0] = 1 (metadata format identifier)
3529 * [1] = (VENDOR_ID << 16) | PCI_ID
3530 * [2:9] = image descriptor for the whole resource
3531 * [2] is always 0, because the base address is cleared
3532 * [9] is the DCC offset bits [39:8] from the beginning of
3533 * the buffer
3534 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
3535 */
3536
3537 md->metadata[0] = 1; /* metadata image format version 1 */
3538
3539 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
3540 md->metadata[1] = si_get_bo_metadata_word1(rscreen);
3541
3542 si_make_texture_descriptor(sscreen, rtex, true,
3543 res->target, res->format,
3544 swizzle, 0, res->last_level, 0,
3545 is_array ? res->array_size - 1 : 0,
3546 res->width0, res->height0, res->depth0,
3547 desc, NULL);
3548
3549 si_set_mutable_tex_desc_fields(rtex, &rtex->surface.level[0], 0, 0,
3550 rtex->surface.blk_w, false, desc);
3551
3552 /* Clear the base address and set the relative DCC offset. */
3553 desc[0] = 0;
3554 desc[1] &= C_008F14_BASE_ADDRESS_HI;
3555 desc[7] = rtex->dcc_offset >> 8;
3556
3557 /* Dwords [2:9] contain the image descriptor. */
3558 memcpy(&md->metadata[2], desc, sizeof(desc));
3559
3560 /* Dwords [10:..] contain the mipmap level offsets. */
3561 for (i = 0; i <= res->last_level; i++)
3562 md->metadata[10+i] = rtex->surface.level[i].offset >> 8;
3563
3564 md->size_metadata = (11 + res->last_level) * 4;
3565 }
3566
3567 static void si_apply_opaque_metadata(struct r600_common_screen *rscreen,
3568 struct r600_texture *rtex,
3569 struct radeon_bo_metadata *md)
3570 {
3571 uint32_t *desc = &md->metadata[2];
3572
3573 if (rscreen->chip_class < VI)
3574 return;
3575
3576 /* Return if DCC is enabled. The texture should be set up with it
3577 * already.
3578 */
3579 if (md->size_metadata >= 11 * 4 &&
3580 md->metadata[0] != 0 &&
3581 md->metadata[1] == si_get_bo_metadata_word1(rscreen) &&
3582 G_008F28_COMPRESSION_EN(desc[6])) {
3583 assert(rtex->dcc_offset == ((uint64_t)desc[7] << 8));
3584 return;
3585 }
3586
3587 /* Disable DCC. These are always set by texture_from_handle and must
3588 * be cleared here.
3589 */
3590 rtex->dcc_offset = 0;
3591 }
3592
3593 void si_init_screen_state_functions(struct si_screen *sscreen)
3594 {
3595 sscreen->b.b.is_format_supported = si_is_format_supported;
3596 sscreen->b.query_opaque_metadata = si_query_opaque_metadata;
3597 sscreen->b.apply_opaque_metadata = si_apply_opaque_metadata;
3598 }
3599
3600 static void
3601 si_write_harvested_raster_configs(struct si_context *sctx,
3602 struct si_pm4_state *pm4,
3603 unsigned raster_config,
3604 unsigned raster_config_1)
3605 {
3606 unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1);
3607 unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1);
3608 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
3609 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
3610 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
3611 unsigned rb_per_se = num_rb / num_se;
3612 unsigned se_mask[4];
3613 unsigned se;
3614
3615 se_mask[0] = ((1 << rb_per_se) - 1);
3616 se_mask[1] = (se_mask[0] << rb_per_se);
3617 se_mask[2] = (se_mask[1] << rb_per_se);
3618 se_mask[3] = (se_mask[2] << rb_per_se);
3619
3620 se_mask[0] &= rb_mask;
3621 se_mask[1] &= rb_mask;
3622 se_mask[2] &= rb_mask;
3623 se_mask[3] &= rb_mask;
3624
3625 assert(num_se == 1 || num_se == 2 || num_se == 4);
3626 assert(sh_per_se == 1 || sh_per_se == 2);
3627 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
3628
3629 /* XXX: I can't figure out what the *_XSEL and *_YSEL
3630 * fields are for, so I'm leaving them as their default
3631 * values. */
3632
3633 for (se = 0; se < num_se; se++) {
3634 unsigned raster_config_se = raster_config;
3635 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
3636 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
3637 int idx = (se / 2) * 2;
3638
3639 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
3640 raster_config_se &= C_028350_SE_MAP;
3641
3642 if (!se_mask[idx]) {
3643 raster_config_se |=
3644 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
3645 } else {
3646 raster_config_se |=
3647 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
3648 }
3649 }
3650
3651 pkr0_mask &= rb_mask;
3652 pkr1_mask &= rb_mask;
3653 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
3654 raster_config_se &= C_028350_PKR_MAP;
3655
3656 if (!pkr0_mask) {
3657 raster_config_se |=
3658 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
3659 } else {
3660 raster_config_se |=
3661 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
3662 }
3663 }
3664
3665 if (rb_per_se >= 2) {
3666 unsigned rb0_mask = 1 << (se * rb_per_se);
3667 unsigned rb1_mask = rb0_mask << 1;
3668
3669 rb0_mask &= rb_mask;
3670 rb1_mask &= rb_mask;
3671 if (!rb0_mask || !rb1_mask) {
3672 raster_config_se &= C_028350_RB_MAP_PKR0;
3673
3674 if (!rb0_mask) {
3675 raster_config_se |=
3676 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
3677 } else {
3678 raster_config_se |=
3679 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
3680 }
3681 }
3682
3683 if (rb_per_se > 2) {
3684 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
3685 rb1_mask = rb0_mask << 1;
3686 rb0_mask &= rb_mask;
3687 rb1_mask &= rb_mask;
3688 if (!rb0_mask || !rb1_mask) {
3689 raster_config_se &= C_028350_RB_MAP_PKR1;
3690
3691 if (!rb0_mask) {
3692 raster_config_se |=
3693 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
3694 } else {
3695 raster_config_se |=
3696 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
3697 }
3698 }
3699 }
3700 }
3701
3702 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
3703 if (sctx->b.chip_class < CIK)
3704 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3705 SE_INDEX(se) | SH_BROADCAST_WRITES |
3706 INSTANCE_BROADCAST_WRITES);
3707 else
3708 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
3709 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
3710 S_030800_INSTANCE_BROADCAST_WRITES(1));
3711 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
3712 }
3713
3714 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
3715 if (sctx->b.chip_class < CIK)
3716 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3717 SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
3718 INSTANCE_BROADCAST_WRITES);
3719 else {
3720 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
3721 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
3722 S_030800_INSTANCE_BROADCAST_WRITES(1));
3723
3724 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
3725 (!se_mask[2] && !se_mask[3]))) {
3726 raster_config_1 &= C_028354_SE_PAIR_MAP;
3727
3728 if (!se_mask[0] && !se_mask[1]) {
3729 raster_config_1 |=
3730 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
3731 } else {
3732 raster_config_1 |=
3733 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
3734 }
3735 }
3736
3737 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
3738 }
3739 }
3740
3741 static void si_init_config(struct si_context *sctx)
3742 {
3743 struct si_screen *sscreen = sctx->screen;
3744 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
3745 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
3746 unsigned raster_config, raster_config_1;
3747 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
3748 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3749 int i;
3750
3751 if (!pm4)
3752 return;
3753
3754 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
3755 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
3756 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
3757 si_pm4_cmd_end(pm4, false);
3758
3759 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
3760 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
3761
3762 /* FIXME calculate these values somehow ??? */
3763 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
3764 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
3765 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
3766
3767 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
3768 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3769
3770 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
3771 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
3772 if (sctx->b.chip_class < CIK)
3773 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
3774 S_008A14_CLIP_VTX_REORDER_ENA(1));
3775
3776 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
3777 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
3778
3779 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
3780
3781 for (i = 0; i < 16; i++) {
3782 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0);
3783 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0));
3784 }
3785
3786 switch (sctx->screen->b.family) {
3787 case CHIP_TAHITI:
3788 case CHIP_PITCAIRN:
3789 raster_config = 0x2a00126a;
3790 raster_config_1 = 0x00000000;
3791 break;
3792 case CHIP_VERDE:
3793 raster_config = 0x0000124a;
3794 raster_config_1 = 0x00000000;
3795 break;
3796 case CHIP_OLAND:
3797 raster_config = 0x00000082;
3798 raster_config_1 = 0x00000000;
3799 break;
3800 case CHIP_HAINAN:
3801 raster_config = 0x00000000;
3802 raster_config_1 = 0x00000000;
3803 break;
3804 case CHIP_BONAIRE:
3805 raster_config = 0x16000012;
3806 raster_config_1 = 0x00000000;
3807 break;
3808 case CHIP_HAWAII:
3809 raster_config = 0x3a00161a;
3810 raster_config_1 = 0x0000002e;
3811 break;
3812 case CHIP_FIJI:
3813 if (sscreen->b.info.cik_macrotile_mode_array[0] == 0x000000e8) {
3814 /* old kernels with old tiling config */
3815 raster_config = 0x16000012;
3816 raster_config_1 = 0x0000002a;
3817 } else {
3818 raster_config = 0x3a00161a;
3819 raster_config_1 = 0x0000002e;
3820 }
3821 break;
3822 case CHIP_POLARIS10:
3823 raster_config = 0x16000012;
3824 raster_config_1 = 0x0000002a;
3825 break;
3826 case CHIP_POLARIS11:
3827 raster_config = 0x16000012;
3828 raster_config_1 = 0x00000000;
3829 break;
3830 case CHIP_TONGA:
3831 raster_config = 0x16000012;
3832 raster_config_1 = 0x0000002a;
3833 break;
3834 case CHIP_ICELAND:
3835 if (num_rb == 1)
3836 raster_config = 0x00000000;
3837 else
3838 raster_config = 0x00000002;
3839 raster_config_1 = 0x00000000;
3840 break;
3841 case CHIP_CARRIZO:
3842 raster_config = 0x00000002;
3843 raster_config_1 = 0x00000000;
3844 break;
3845 case CHIP_KAVERI:
3846 /* KV should be 0x00000002, but that causes problems with radeon */
3847 raster_config = 0x00000000; /* 0x00000002 */
3848 raster_config_1 = 0x00000000;
3849 break;
3850 case CHIP_KABINI:
3851 case CHIP_MULLINS:
3852 case CHIP_STONEY:
3853 raster_config = 0x00000000;
3854 raster_config_1 = 0x00000000;
3855 break;
3856 default:
3857 fprintf(stderr,
3858 "radeonsi: Unknown GPU, using 0 for raster_config\n");
3859 raster_config = 0x00000000;
3860 raster_config_1 = 0x00000000;
3861 break;
3862 }
3863
3864 /* Always use the default config when all backends are enabled
3865 * (or when we failed to determine the enabled backends).
3866 */
3867 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
3868 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
3869 raster_config);
3870 if (sctx->b.chip_class >= CIK)
3871 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
3872 raster_config_1);
3873 } else {
3874 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
3875 }
3876
3877 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
3878 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
3879 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
3880 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
3881 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
3882 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
3883 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
3884
3885 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
3886 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
3887 S_028230_ER_TRI(0xA) |
3888 S_028230_ER_POINT(0xA) |
3889 S_028230_ER_RECT(0xA) |
3890 /* Required by DX10_DIAMOND_TEST_ENA: */
3891 S_028230_ER_LINE_LR(0x1A) |
3892 S_028230_ER_LINE_RL(0x26) |
3893 S_028230_ER_LINE_TB(0xA) |
3894 S_028230_ER_LINE_BT(0xA));
3895 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
3896 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
3897 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
3898 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
3899 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
3900 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
3901 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE,
3902 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3903 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
3904
3905 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
3906 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
3907 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
3908
3909 if (sctx->b.chip_class >= CIK) {
3910 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff));
3911 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
3912 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xffff));
3913 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
3914
3915 if (sscreen->b.info.num_good_compute_units /
3916 (sscreen->b.info.max_se * sscreen->b.info.max_sh_per_se) <= 4) {
3917 /* Too few available compute units per SH. Disallowing
3918 * VS to run on CU0 could hurt us more than late VS
3919 * allocation would help.
3920 *
3921 * LATE_ALLOC_VS = 2 is the highest safe number.
3922 */
3923 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
3924 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
3925 } else {
3926 /* Set LATE_ALLOC_VS == 31. It should be less than
3927 * the number of scratch waves. Limitations:
3928 * - VS can't execute on CU0.
3929 * - If HS writes outputs to LDS, LS can't execute on CU0.
3930 */
3931 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xfffe));
3932 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
3933 }
3934
3935 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
3936 }
3937
3938 if (sctx->b.chip_class >= VI) {
3939 unsigned vgt_tess_distribution;
3940
3941 si_pm4_set_reg(pm4, R_028424_CB_DCC_CONTROL,
3942 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
3943 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
3944 if (sctx->b.family < CHIP_POLARIS10)
3945 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
3946 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
3947
3948 vgt_tess_distribution =
3949 S_028B50_ACCUM_ISOLINE(32) |
3950 S_028B50_ACCUM_TRI(11) |
3951 S_028B50_ACCUM_QUAD(11) |
3952 S_028B50_DONUT_SPLIT(16);
3953
3954 /* Testing with Unigine Heaven extreme tesselation yielded best results
3955 * with TRAP_SPLIT = 3.
3956 */
3957 if (sctx->b.family == CHIP_FIJI ||
3958 sctx->b.family >= CHIP_POLARIS10)
3959 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
3960
3961 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution);
3962 } else {
3963 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
3964 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
3965 }
3966
3967 if (sctx->b.family == CHIP_STONEY)
3968 si_pm4_set_reg(pm4, R_028C40_PA_SC_SHADER_CONTROL, 0);
3969
3970 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
3971 if (sctx->b.chip_class >= CIK)
3972 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, border_color_va >> 40);
3973 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
3974 RADEON_PRIO_BORDER_COLORS);
3975
3976 si_pm4_upload_indirect_buffer(sctx, pm4);
3977 sctx->init_config = pm4;
3978 }