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radeonsi: enable ARB_shader_clock
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "sid.h"
29 #include "gfx9d.h"
30 #include "radeon/r600_cs.h"
31 #include "radeon/r600_query.h"
32
33 #include "util/u_dual_blend.h"
34 #include "util/u_format.h"
35 #include "util/u_format_s3tc.h"
36 #include "util/u_memory.h"
37 #include "util/u_resource.h"
38 #include "util/u_upload_mgr.h"
39
40 /* Initialize an external atom (owned by ../radeon). */
41 static void
42 si_init_external_atom(struct si_context *sctx, struct r600_atom *atom,
43 struct r600_atom **list_elem)
44 {
45 atom->id = list_elem - sctx->atoms.array;
46 *list_elem = atom;
47 }
48
49 /* Initialize an atom owned by radeonsi. */
50 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
51 struct r600_atom **list_elem,
52 void (*emit_func)(struct si_context *ctx, struct r600_atom *state))
53 {
54 atom->emit = (void*)emit_func;
55 atom->id = list_elem - sctx->atoms.array;
56 *list_elem = atom;
57 }
58
59 static unsigned si_map_swizzle(unsigned swizzle)
60 {
61 switch (swizzle) {
62 case PIPE_SWIZZLE_Y:
63 return V_008F0C_SQ_SEL_Y;
64 case PIPE_SWIZZLE_Z:
65 return V_008F0C_SQ_SEL_Z;
66 case PIPE_SWIZZLE_W:
67 return V_008F0C_SQ_SEL_W;
68 case PIPE_SWIZZLE_0:
69 return V_008F0C_SQ_SEL_0;
70 case PIPE_SWIZZLE_1:
71 return V_008F0C_SQ_SEL_1;
72 default: /* PIPE_SWIZZLE_X */
73 return V_008F0C_SQ_SEL_X;
74 }
75 }
76
77 static uint32_t S_FIXED(float value, uint32_t frac_bits)
78 {
79 return value * (1 << frac_bits);
80 }
81
82 /* 12.4 fixed-point */
83 static unsigned si_pack_float_12p4(float x)
84 {
85 return x <= 0 ? 0 :
86 x >= 4096 ? 0xffff : x * 16;
87 }
88
89 /*
90 * Inferred framebuffer and blender state.
91 *
92 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
93 * if there is not enough PS outputs.
94 */
95 static void si_emit_cb_render_state(struct si_context *sctx, struct r600_atom *atom)
96 {
97 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
98 struct si_state_blend *blend = sctx->queued.named.blend;
99 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
100 * but you never know. */
101 uint32_t cb_target_mask = sctx->framebuffer.colorbuf_enabled_4bit;
102 unsigned i;
103
104 if (blend)
105 cb_target_mask &= blend->cb_target_mask;
106
107 /* Avoid a hang that happens when dual source blending is enabled
108 * but there is not enough color outputs. This is undefined behavior,
109 * so disable color writes completely.
110 *
111 * Reproducible with Unigine Heaven 4.0 and drirc missing.
112 */
113 if (blend && blend->dual_src_blend &&
114 sctx->ps_shader.cso &&
115 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
116 cb_target_mask = 0;
117
118 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, cb_target_mask);
119
120 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
121 * I think we don't have to do anything between IBs.
122 */
123 if (sctx->b.chip_class >= GFX9 &&
124 sctx->last_cb_target_mask != cb_target_mask) {
125 sctx->last_cb_target_mask = cb_target_mask;
126
127 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
128 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
129 }
130
131 /* RB+ register settings. */
132 if (sctx->screen->b.rbplus_allowed) {
133 unsigned spi_shader_col_format =
134 sctx->ps_shader.cso ?
135 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format : 0;
136 unsigned sx_ps_downconvert = 0;
137 unsigned sx_blend_opt_epsilon = 0;
138 unsigned sx_blend_opt_control = 0;
139
140 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
141 struct r600_surface *surf =
142 (struct r600_surface*)sctx->framebuffer.state.cbufs[i];
143 unsigned format, swap, spi_format, colormask;
144 bool has_alpha, has_rgb;
145
146 if (!surf)
147 continue;
148
149 format = G_028C70_FORMAT(surf->cb_color_info);
150 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
151 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
152 colormask = (cb_target_mask >> (i * 4)) & 0xf;
153
154 /* Set if RGB and A are present. */
155 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
156
157 if (format == V_028C70_COLOR_8 ||
158 format == V_028C70_COLOR_16 ||
159 format == V_028C70_COLOR_32)
160 has_rgb = !has_alpha;
161 else
162 has_rgb = true;
163
164 /* Check the colormask and export format. */
165 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
166 has_rgb = false;
167 if (!(colormask & PIPE_MASK_A))
168 has_alpha = false;
169
170 if (spi_format == V_028714_SPI_SHADER_ZERO) {
171 has_rgb = false;
172 has_alpha = false;
173 }
174
175 /* Disable value checking for disabled channels. */
176 if (!has_rgb)
177 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
178 if (!has_alpha)
179 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
180
181 /* Enable down-conversion for 32bpp and smaller formats. */
182 switch (format) {
183 case V_028C70_COLOR_8:
184 case V_028C70_COLOR_8_8:
185 case V_028C70_COLOR_8_8_8_8:
186 /* For 1 and 2-channel formats, use the superset thereof. */
187 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
188 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
189 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
190 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
191 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
192 }
193 break;
194
195 case V_028C70_COLOR_5_6_5:
196 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
197 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
198 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
199 }
200 break;
201
202 case V_028C70_COLOR_1_5_5_5:
203 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
204 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
205 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
206 }
207 break;
208
209 case V_028C70_COLOR_4_4_4_4:
210 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
211 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
212 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
213 }
214 break;
215
216 case V_028C70_COLOR_32:
217 if (swap == V_0280A0_SWAP_STD &&
218 spi_format == V_028714_SPI_SHADER_32_R)
219 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
220 else if (swap == V_0280A0_SWAP_ALT_REV &&
221 spi_format == V_028714_SPI_SHADER_32_AR)
222 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
223 break;
224
225 case V_028C70_COLOR_16:
226 case V_028C70_COLOR_16_16:
227 /* For 1-channel formats, use the superset thereof. */
228 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
229 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
230 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
231 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
232 if (swap == V_0280A0_SWAP_STD ||
233 swap == V_0280A0_SWAP_STD_REV)
234 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
235 else
236 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
237 }
238 break;
239
240 case V_028C70_COLOR_10_11_11:
241 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
242 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
243 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
244 }
245 break;
246
247 case V_028C70_COLOR_2_10_10_10:
248 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
249 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
250 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
251 }
252 break;
253 }
254 }
255
256 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
257 radeon_emit(cs, sx_ps_downconvert); /* R_028754_SX_PS_DOWNCONVERT */
258 radeon_emit(cs, sx_blend_opt_epsilon); /* R_028758_SX_BLEND_OPT_EPSILON */
259 radeon_emit(cs, sx_blend_opt_control); /* R_02875C_SX_BLEND_OPT_CONTROL */
260 } else if (sctx->screen->b.has_rbplus) {
261 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
262 radeon_emit(cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
263 radeon_emit(cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
264 radeon_emit(cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
265 }
266 }
267
268 /*
269 * Blender functions
270 */
271
272 static uint32_t si_translate_blend_function(int blend_func)
273 {
274 switch (blend_func) {
275 case PIPE_BLEND_ADD:
276 return V_028780_COMB_DST_PLUS_SRC;
277 case PIPE_BLEND_SUBTRACT:
278 return V_028780_COMB_SRC_MINUS_DST;
279 case PIPE_BLEND_REVERSE_SUBTRACT:
280 return V_028780_COMB_DST_MINUS_SRC;
281 case PIPE_BLEND_MIN:
282 return V_028780_COMB_MIN_DST_SRC;
283 case PIPE_BLEND_MAX:
284 return V_028780_COMB_MAX_DST_SRC;
285 default:
286 R600_ERR("Unknown blend function %d\n", blend_func);
287 assert(0);
288 break;
289 }
290 return 0;
291 }
292
293 static uint32_t si_translate_blend_factor(int blend_fact)
294 {
295 switch (blend_fact) {
296 case PIPE_BLENDFACTOR_ONE:
297 return V_028780_BLEND_ONE;
298 case PIPE_BLENDFACTOR_SRC_COLOR:
299 return V_028780_BLEND_SRC_COLOR;
300 case PIPE_BLENDFACTOR_SRC_ALPHA:
301 return V_028780_BLEND_SRC_ALPHA;
302 case PIPE_BLENDFACTOR_DST_ALPHA:
303 return V_028780_BLEND_DST_ALPHA;
304 case PIPE_BLENDFACTOR_DST_COLOR:
305 return V_028780_BLEND_DST_COLOR;
306 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
307 return V_028780_BLEND_SRC_ALPHA_SATURATE;
308 case PIPE_BLENDFACTOR_CONST_COLOR:
309 return V_028780_BLEND_CONSTANT_COLOR;
310 case PIPE_BLENDFACTOR_CONST_ALPHA:
311 return V_028780_BLEND_CONSTANT_ALPHA;
312 case PIPE_BLENDFACTOR_ZERO:
313 return V_028780_BLEND_ZERO;
314 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
315 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
316 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
317 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
318 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
319 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
320 case PIPE_BLENDFACTOR_INV_DST_COLOR:
321 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
322 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
323 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
324 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
325 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
326 case PIPE_BLENDFACTOR_SRC1_COLOR:
327 return V_028780_BLEND_SRC1_COLOR;
328 case PIPE_BLENDFACTOR_SRC1_ALPHA:
329 return V_028780_BLEND_SRC1_ALPHA;
330 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
331 return V_028780_BLEND_INV_SRC1_COLOR;
332 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
333 return V_028780_BLEND_INV_SRC1_ALPHA;
334 default:
335 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
336 assert(0);
337 break;
338 }
339 return 0;
340 }
341
342 static uint32_t si_translate_blend_opt_function(int blend_func)
343 {
344 switch (blend_func) {
345 case PIPE_BLEND_ADD:
346 return V_028760_OPT_COMB_ADD;
347 case PIPE_BLEND_SUBTRACT:
348 return V_028760_OPT_COMB_SUBTRACT;
349 case PIPE_BLEND_REVERSE_SUBTRACT:
350 return V_028760_OPT_COMB_REVSUBTRACT;
351 case PIPE_BLEND_MIN:
352 return V_028760_OPT_COMB_MIN;
353 case PIPE_BLEND_MAX:
354 return V_028760_OPT_COMB_MAX;
355 default:
356 return V_028760_OPT_COMB_BLEND_DISABLED;
357 }
358 }
359
360 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
361 {
362 switch (blend_fact) {
363 case PIPE_BLENDFACTOR_ZERO:
364 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
365 case PIPE_BLENDFACTOR_ONE:
366 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
367 case PIPE_BLENDFACTOR_SRC_COLOR:
368 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
369 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
370 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
371 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
372 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
373 case PIPE_BLENDFACTOR_SRC_ALPHA:
374 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
375 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
376 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
377 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
378 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
379 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
380 default:
381 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
382 }
383 }
384
385 /**
386 * Get rid of DST in the blend factors by commuting the operands:
387 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
388 */
389 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
390 unsigned *dst_factor, unsigned expected_dst,
391 unsigned replacement_src)
392 {
393 if (*src_factor == expected_dst &&
394 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
395 *src_factor = PIPE_BLENDFACTOR_ZERO;
396 *dst_factor = replacement_src;
397
398 /* Commuting the operands requires reversing subtractions. */
399 if (*func == PIPE_BLEND_SUBTRACT)
400 *func = PIPE_BLEND_REVERSE_SUBTRACT;
401 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
402 *func = PIPE_BLEND_SUBTRACT;
403 }
404 }
405
406 static bool si_blend_factor_uses_dst(unsigned factor)
407 {
408 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
409 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
410 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
411 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
412 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
413 }
414
415 static void *si_create_blend_state_mode(struct pipe_context *ctx,
416 const struct pipe_blend_state *state,
417 unsigned mode)
418 {
419 struct si_context *sctx = (struct si_context*)ctx;
420 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
421 struct si_pm4_state *pm4 = &blend->pm4;
422 uint32_t sx_mrt_blend_opt[8] = {0};
423 uint32_t color_control = 0;
424
425 if (!blend)
426 return NULL;
427
428 blend->alpha_to_coverage = state->alpha_to_coverage;
429 blend->alpha_to_one = state->alpha_to_one;
430 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
431
432 if (state->logicop_enable) {
433 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
434 } else {
435 color_control |= S_028808_ROP3(0xcc);
436 }
437
438 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
439 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
440 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
441 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
442 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
443 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
444
445 if (state->alpha_to_coverage)
446 blend->need_src_alpha_4bit |= 0xf;
447
448 blend->cb_target_mask = 0;
449 for (int i = 0; i < 8; i++) {
450 /* state->rt entries > 0 only written if independent blending */
451 const int j = state->independent_blend_enable ? i : 0;
452
453 unsigned eqRGB = state->rt[j].rgb_func;
454 unsigned srcRGB = state->rt[j].rgb_src_factor;
455 unsigned dstRGB = state->rt[j].rgb_dst_factor;
456 unsigned eqA = state->rt[j].alpha_func;
457 unsigned srcA = state->rt[j].alpha_src_factor;
458 unsigned dstA = state->rt[j].alpha_dst_factor;
459
460 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
461 unsigned blend_cntl = 0;
462
463 sx_mrt_blend_opt[i] =
464 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
465 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
466
467 /* Only set dual source blending for MRT0 to avoid a hang. */
468 if (i >= 1 && blend->dual_src_blend) {
469 /* Vulkan does this for dual source blending. */
470 if (i == 1)
471 blend_cntl |= S_028780_ENABLE(1);
472
473 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
474 continue;
475 }
476
477 /* Only addition and subtraction equations are supported with
478 * dual source blending.
479 */
480 if (blend->dual_src_blend &&
481 (eqRGB == PIPE_BLEND_MIN || eqRGB == PIPE_BLEND_MAX ||
482 eqA == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MAX)) {
483 assert(!"Unsupported equation for dual source blending");
484 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
485 continue;
486 }
487
488 /* cb_render_state will disable unused ones */
489 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
490
491 if (!state->rt[j].colormask || !state->rt[j].blend_enable) {
492 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
493 continue;
494 }
495
496 /* Blending optimizations for RB+.
497 * These transformations don't change the behavior.
498 *
499 * First, get rid of DST in the blend factors:
500 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
501 */
502 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
503 PIPE_BLENDFACTOR_DST_COLOR,
504 PIPE_BLENDFACTOR_SRC_COLOR);
505 si_blend_remove_dst(&eqA, &srcA, &dstA,
506 PIPE_BLENDFACTOR_DST_COLOR,
507 PIPE_BLENDFACTOR_SRC_COLOR);
508 si_blend_remove_dst(&eqA, &srcA, &dstA,
509 PIPE_BLENDFACTOR_DST_ALPHA,
510 PIPE_BLENDFACTOR_SRC_ALPHA);
511
512 /* Look up the ideal settings from tables. */
513 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
514 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
515 srcA_opt = si_translate_blend_opt_factor(srcA, true);
516 dstA_opt = si_translate_blend_opt_factor(dstA, true);
517
518 /* Handle interdependencies. */
519 if (si_blend_factor_uses_dst(srcRGB))
520 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
521 if (si_blend_factor_uses_dst(srcA))
522 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
523
524 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
525 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
526 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
527 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
528 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
529
530 /* Set the final value. */
531 sx_mrt_blend_opt[i] =
532 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
533 S_028760_COLOR_DST_OPT(dstRGB_opt) |
534 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
535 S_028760_ALPHA_SRC_OPT(srcA_opt) |
536 S_028760_ALPHA_DST_OPT(dstA_opt) |
537 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
538
539 /* Set blend state. */
540 blend_cntl |= S_028780_ENABLE(1);
541 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
542 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
543 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
544
545 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
546 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
547 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
548 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
549 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
550 }
551 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
552
553 blend->blend_enable_4bit |= 0xfu << (i * 4);
554
555 /* This is only important for formats without alpha. */
556 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
557 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
558 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
559 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
560 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
561 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
562 blend->need_src_alpha_4bit |= 0xfu << (i * 4);
563 }
564
565 if (blend->cb_target_mask) {
566 color_control |= S_028808_MODE(mode);
567 } else {
568 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
569 }
570
571 if (sctx->screen->b.has_rbplus) {
572 /* Disable RB+ blend optimizations for dual source blending.
573 * Vulkan does this.
574 */
575 if (blend->dual_src_blend) {
576 for (int i = 0; i < 8; i++) {
577 sx_mrt_blend_opt[i] =
578 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
579 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
580 }
581 }
582
583 for (int i = 0; i < 8; i++)
584 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
585 sx_mrt_blend_opt[i]);
586
587 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
588 if (blend->dual_src_blend || state->logicop_enable ||
589 mode == V_028808_CB_RESOLVE)
590 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
591 }
592
593 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
594 return blend;
595 }
596
597 static void *si_create_blend_state(struct pipe_context *ctx,
598 const struct pipe_blend_state *state)
599 {
600 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
601 }
602
603 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
604 {
605 struct si_context *sctx = (struct si_context *)ctx;
606 si_pm4_bind_state(sctx, blend, (struct si_state_blend *)state);
607 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
608 sctx->do_update_shaders = true;
609 }
610
611 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
612 {
613 struct si_context *sctx = (struct si_context *)ctx;
614 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
615 }
616
617 static void si_set_blend_color(struct pipe_context *ctx,
618 const struct pipe_blend_color *state)
619 {
620 struct si_context *sctx = (struct si_context *)ctx;
621
622 if (memcmp(&sctx->blend_color.state, state, sizeof(*state)) == 0)
623 return;
624
625 sctx->blend_color.state = *state;
626 si_mark_atom_dirty(sctx, &sctx->blend_color.atom);
627 }
628
629 static void si_emit_blend_color(struct si_context *sctx, struct r600_atom *atom)
630 {
631 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
632
633 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
634 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
635 }
636
637 /*
638 * Clipping
639 */
640
641 static void si_set_clip_state(struct pipe_context *ctx,
642 const struct pipe_clip_state *state)
643 {
644 struct si_context *sctx = (struct si_context *)ctx;
645 struct pipe_constant_buffer cb;
646
647 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
648 return;
649
650 sctx->clip_state.state = *state;
651 si_mark_atom_dirty(sctx, &sctx->clip_state.atom);
652
653 cb.buffer = NULL;
654 cb.user_buffer = state->ucp;
655 cb.buffer_offset = 0;
656 cb.buffer_size = 4*4*8;
657 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
658 pipe_resource_reference(&cb.buffer, NULL);
659 }
660
661 static void si_emit_clip_state(struct si_context *sctx, struct r600_atom *atom)
662 {
663 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
664
665 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
666 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
667 }
668
669 #define SIX_BITS 0x3F
670
671 static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom)
672 {
673 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
674 struct si_shader *vs = si_get_vs_state(sctx);
675 struct tgsi_shader_info *info = si_get_vs_info(sctx);
676 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
677 unsigned window_space =
678 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
679 unsigned clipdist_mask =
680 info->writes_clipvertex ? SIX_BITS : info->clipdist_writemask;
681 unsigned ucp_mask = clipdist_mask ? 0 : rs->clip_plane_enable & SIX_BITS;
682 unsigned culldist_mask = info->culldist_writemask << info->num_written_clipdistance;
683 unsigned total_mask;
684 bool misc_vec_ena;
685
686 if (vs->key.opt.hw_vs.clip_disable) {
687 assert(!info->culldist_writemask);
688 clipdist_mask = 0;
689 culldist_mask = 0;
690 }
691 total_mask = clipdist_mask | culldist_mask;
692
693 /* Clip distances on points have no effect, so need to be implemented
694 * as cull distances. This applies for the clipvertex case as well.
695 *
696 * Setting this for primitives other than points should have no adverse
697 * effects.
698 */
699 clipdist_mask &= rs->clip_plane_enable;
700 culldist_mask |= clipdist_mask;
701
702 misc_vec_ena = info->writes_psize || info->writes_edgeflag ||
703 info->writes_layer || info->writes_viewport_index;
704
705 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
706 S_02881C_USE_VTX_POINT_SIZE(info->writes_psize) |
707 S_02881C_USE_VTX_EDGE_FLAG(info->writes_edgeflag) |
708 S_02881C_USE_VTX_RENDER_TARGET_INDX(info->writes_layer) |
709 S_02881C_USE_VTX_VIEWPORT_INDX(info->writes_viewport_index) |
710 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0F) != 0) |
711 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xF0) != 0) |
712 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
713 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
714 clipdist_mask | (culldist_mask << 8));
715 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
716 rs->pa_cl_clip_cntl |
717 ucp_mask |
718 S_028810_CLIP_DISABLE(window_space));
719
720 /* reuse needs to be set off if we write oViewport */
721 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF,
722 S_028AB4_REUSE_OFF(info->writes_viewport_index));
723 }
724
725 /*
726 * inferred state between framebuffer and rasterizer
727 */
728 static void si_update_poly_offset_state(struct si_context *sctx)
729 {
730 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
731
732 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf) {
733 si_pm4_bind_state(sctx, poly_offset, NULL);
734 return;
735 }
736
737 /* Use the user format, not db_render_format, so that the polygon
738 * offset behaves as expected by applications.
739 */
740 switch (sctx->framebuffer.state.zsbuf->texture->format) {
741 case PIPE_FORMAT_Z16_UNORM:
742 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
743 break;
744 default: /* 24-bit */
745 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
746 break;
747 case PIPE_FORMAT_Z32_FLOAT:
748 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
749 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
750 break;
751 }
752 }
753
754 /*
755 * Rasterizer
756 */
757
758 static uint32_t si_translate_fill(uint32_t func)
759 {
760 switch(func) {
761 case PIPE_POLYGON_MODE_FILL:
762 return V_028814_X_DRAW_TRIANGLES;
763 case PIPE_POLYGON_MODE_LINE:
764 return V_028814_X_DRAW_LINES;
765 case PIPE_POLYGON_MODE_POINT:
766 return V_028814_X_DRAW_POINTS;
767 default:
768 assert(0);
769 return V_028814_X_DRAW_POINTS;
770 }
771 }
772
773 static void *si_create_rs_state(struct pipe_context *ctx,
774 const struct pipe_rasterizer_state *state)
775 {
776 struct si_screen *sscreen = ((struct si_context *)ctx)->screen;
777 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
778 struct si_pm4_state *pm4 = &rs->pm4;
779 unsigned tmp, i;
780 float psize_min, psize_max;
781
782 if (!rs) {
783 return NULL;
784 }
785
786 rs->scissor_enable = state->scissor;
787 rs->clip_halfz = state->clip_halfz;
788 rs->two_side = state->light_twoside;
789 rs->multisample_enable = state->multisample;
790 rs->force_persample_interp = state->force_persample_interp;
791 rs->clip_plane_enable = state->clip_plane_enable;
792 rs->line_stipple_enable = state->line_stipple_enable;
793 rs->poly_stipple_enable = state->poly_stipple_enable;
794 rs->line_smooth = state->line_smooth;
795 rs->poly_smooth = state->poly_smooth;
796 rs->uses_poly_offset = state->offset_point || state->offset_line ||
797 state->offset_tri;
798 rs->clamp_fragment_color = state->clamp_fragment_color;
799 rs->flatshade = state->flatshade;
800 rs->sprite_coord_enable = state->sprite_coord_enable;
801 rs->rasterizer_discard = state->rasterizer_discard;
802 rs->pa_sc_line_stipple = state->line_stipple_enable ?
803 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
804 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
805 rs->pa_cl_clip_cntl =
806 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
807 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
808 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
809 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
810 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
811
812 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
813 S_0286D4_FLAT_SHADE_ENA(1) |
814 S_0286D4_PNT_SPRITE_ENA(1) |
815 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
816 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
817 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
818 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
819 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
820
821 /* point size 12.4 fixed point */
822 tmp = (unsigned)(state->point_size * 8.0);
823 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
824
825 if (state->point_size_per_vertex) {
826 psize_min = util_get_min_point_size(state);
827 psize_max = 8192;
828 } else {
829 /* Force the point size to be as if the vertex output was disabled. */
830 psize_min = state->point_size;
831 psize_max = state->point_size;
832 }
833 /* Divide by two, because 0.5 = 1 pixel. */
834 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
835 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
836 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
837
838 tmp = (unsigned)state->line_width * 8;
839 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
840 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
841 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
842 S_028A48_MSAA_ENABLE(state->multisample ||
843 state->poly_smooth ||
844 state->line_smooth) |
845 S_028A48_VPORT_SCISSOR_ENABLE(1) |
846 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen->b.chip_class >= GFX9));
847
848 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
849 S_028BE4_PIX_CENTER(state->half_pixel_center) |
850 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
851
852 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
853 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
854 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
855 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
856 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
857 S_028814_FACE(!state->front_ccw) |
858 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
859 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
860 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
861 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
862 state->fill_back != PIPE_POLYGON_MODE_FILL) |
863 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
864 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
865 si_pm4_set_reg(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0 +
866 SI_SGPR_VS_STATE_BITS * 4, state->clamp_vertex_color);
867
868 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
869 for (i = 0; i < 3; i++) {
870 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
871 float offset_units = state->offset_units;
872 float offset_scale = state->offset_scale * 16.0f;
873 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
874
875 if (!state->offset_units_unscaled) {
876 switch (i) {
877 case 0: /* 16-bit zbuffer */
878 offset_units *= 4.0f;
879 pa_su_poly_offset_db_fmt_cntl =
880 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
881 break;
882 case 1: /* 24-bit zbuffer */
883 offset_units *= 2.0f;
884 pa_su_poly_offset_db_fmt_cntl =
885 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
886 break;
887 case 2: /* 32-bit zbuffer */
888 offset_units *= 1.0f;
889 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
890 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
891 break;
892 }
893 }
894
895 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
896 fui(offset_scale));
897 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
898 fui(offset_units));
899 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
900 fui(offset_scale));
901 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
902 fui(offset_units));
903 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
904 pa_su_poly_offset_db_fmt_cntl);
905 }
906
907 return rs;
908 }
909
910 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
911 {
912 struct si_context *sctx = (struct si_context *)ctx;
913 struct si_state_rasterizer *old_rs =
914 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
915 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
916
917 if (!state)
918 return;
919
920 if (!old_rs || old_rs->multisample_enable != rs->multisample_enable) {
921 si_mark_atom_dirty(sctx, &sctx->db_render_state);
922
923 /* Update the small primitive filter workaround if necessary. */
924 if (sctx->b.family >= CHIP_POLARIS10 &&
925 sctx->framebuffer.nr_samples > 1)
926 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
927 }
928
929 r600_viewport_set_rast_deps(&sctx->b, rs->scissor_enable, rs->clip_halfz);
930
931 si_pm4_bind_state(sctx, rasterizer, rs);
932 si_update_poly_offset_state(sctx);
933
934 si_mark_atom_dirty(sctx, &sctx->clip_regs);
935 sctx->ia_multi_vgt_param_key.u.line_stipple_enabled =
936 rs->line_stipple_enable;
937 sctx->do_update_shaders = true;
938 }
939
940 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
941 {
942 struct si_context *sctx = (struct si_context *)ctx;
943
944 if (sctx->queued.named.rasterizer == state)
945 si_pm4_bind_state(sctx, poly_offset, NULL);
946 si_pm4_delete_state(sctx, rasterizer, (struct si_state_rasterizer *)state);
947 }
948
949 /*
950 * infeered state between dsa and stencil ref
951 */
952 static void si_emit_stencil_ref(struct si_context *sctx, struct r600_atom *atom)
953 {
954 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
955 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
956 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
957
958 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
959 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
960 S_028430_STENCILMASK(dsa->valuemask[0]) |
961 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
962 S_028430_STENCILOPVAL(1));
963 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
964 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
965 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
966 S_028434_STENCILOPVAL_BF(1));
967 }
968
969 static void si_set_stencil_ref(struct pipe_context *ctx,
970 const struct pipe_stencil_ref *state)
971 {
972 struct si_context *sctx = (struct si_context *)ctx;
973
974 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
975 return;
976
977 sctx->stencil_ref.state = *state;
978 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
979 }
980
981
982 /*
983 * DSA
984 */
985
986 static uint32_t si_translate_stencil_op(int s_op)
987 {
988 switch (s_op) {
989 case PIPE_STENCIL_OP_KEEP:
990 return V_02842C_STENCIL_KEEP;
991 case PIPE_STENCIL_OP_ZERO:
992 return V_02842C_STENCIL_ZERO;
993 case PIPE_STENCIL_OP_REPLACE:
994 return V_02842C_STENCIL_REPLACE_TEST;
995 case PIPE_STENCIL_OP_INCR:
996 return V_02842C_STENCIL_ADD_CLAMP;
997 case PIPE_STENCIL_OP_DECR:
998 return V_02842C_STENCIL_SUB_CLAMP;
999 case PIPE_STENCIL_OP_INCR_WRAP:
1000 return V_02842C_STENCIL_ADD_WRAP;
1001 case PIPE_STENCIL_OP_DECR_WRAP:
1002 return V_02842C_STENCIL_SUB_WRAP;
1003 case PIPE_STENCIL_OP_INVERT:
1004 return V_02842C_STENCIL_INVERT;
1005 default:
1006 R600_ERR("Unknown stencil op %d", s_op);
1007 assert(0);
1008 break;
1009 }
1010 return 0;
1011 }
1012
1013 static void *si_create_dsa_state(struct pipe_context *ctx,
1014 const struct pipe_depth_stencil_alpha_state *state)
1015 {
1016 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
1017 struct si_pm4_state *pm4 = &dsa->pm4;
1018 unsigned db_depth_control;
1019 uint32_t db_stencil_control = 0;
1020
1021 if (!dsa) {
1022 return NULL;
1023 }
1024
1025 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
1026 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
1027 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
1028 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
1029
1030 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
1031 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
1032 S_028800_ZFUNC(state->depth.func) |
1033 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
1034
1035 /* stencil */
1036 if (state->stencil[0].enabled) {
1037 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1038 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
1039 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
1040 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
1041 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
1042
1043 if (state->stencil[1].enabled) {
1044 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1045 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1046 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
1047 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
1048 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
1049 }
1050 }
1051
1052 /* alpha */
1053 if (state->alpha.enabled) {
1054 dsa->alpha_func = state->alpha.func;
1055
1056 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1057 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
1058 } else {
1059 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1060 }
1061
1062 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1063 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1064 if (state->depth.bounds_test) {
1065 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1066 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1067 }
1068
1069 return dsa;
1070 }
1071
1072 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1073 {
1074 struct si_context *sctx = (struct si_context *)ctx;
1075 struct si_state_dsa *dsa = state;
1076
1077 if (!state)
1078 return;
1079
1080 si_pm4_bind_state(sctx, dsa, dsa);
1081
1082 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1083 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1084 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1085 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1086 }
1087 sctx->do_update_shaders = true;
1088 }
1089
1090 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1091 {
1092 struct si_context *sctx = (struct si_context *)ctx;
1093 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1094 }
1095
1096 static void *si_create_db_flush_dsa(struct si_context *sctx)
1097 {
1098 struct pipe_depth_stencil_alpha_state dsa = {};
1099
1100 return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
1101 }
1102
1103 /* DB RENDER STATE */
1104
1105 static void si_set_active_query_state(struct pipe_context *ctx, boolean enable)
1106 {
1107 struct si_context *sctx = (struct si_context*)ctx;
1108
1109 /* Pipeline stat & streamout queries. */
1110 if (enable) {
1111 sctx->b.flags &= ~R600_CONTEXT_STOP_PIPELINE_STATS;
1112 sctx->b.flags |= R600_CONTEXT_START_PIPELINE_STATS;
1113 } else {
1114 sctx->b.flags &= ~R600_CONTEXT_START_PIPELINE_STATS;
1115 sctx->b.flags |= R600_CONTEXT_STOP_PIPELINE_STATS;
1116 }
1117
1118 /* Occlusion queries. */
1119 if (sctx->occlusion_queries_disabled != !enable) {
1120 sctx->occlusion_queries_disabled = !enable;
1121 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1122 }
1123 }
1124
1125 static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
1126 {
1127 struct si_context *sctx = (struct si_context*)ctx;
1128
1129 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1130 }
1131
1132 static void si_save_qbo_state(struct pipe_context *ctx, struct r600_qbo_state *st)
1133 {
1134 struct si_context *sctx = (struct si_context*)ctx;
1135
1136 st->saved_compute = sctx->cs_shader_state.program;
1137
1138 si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1139 si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
1140 }
1141
1142 static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
1143 {
1144 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1145 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1146 unsigned db_shader_control;
1147
1148 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1149
1150 /* DB_RENDER_CONTROL */
1151 if (sctx->dbcb_depth_copy_enabled ||
1152 sctx->dbcb_stencil_copy_enabled) {
1153 radeon_emit(cs,
1154 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1155 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1156 S_028000_COPY_CENTROID(1) |
1157 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
1158 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1159 radeon_emit(cs,
1160 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1161 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace));
1162 } else {
1163 radeon_emit(cs,
1164 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1165 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear));
1166 }
1167
1168 /* DB_COUNT_CONTROL (occlusion queries) */
1169 if (sctx->b.num_occlusion_queries > 0 &&
1170 !sctx->occlusion_queries_disabled) {
1171 bool perfect = sctx->b.num_perfect_occlusion_queries > 0;
1172
1173 if (sctx->b.chip_class >= CIK) {
1174 radeon_emit(cs,
1175 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1176 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
1177 S_028004_ZPASS_ENABLE(1) |
1178 S_028004_SLICE_EVEN_ENABLE(1) |
1179 S_028004_SLICE_ODD_ENABLE(1));
1180 } else {
1181 radeon_emit(cs,
1182 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1183 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
1184 }
1185 } else {
1186 /* Disable occlusion queries. */
1187 if (sctx->b.chip_class >= CIK) {
1188 radeon_emit(cs, 0);
1189 } else {
1190 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
1191 }
1192 }
1193
1194 /* DB_RENDER_OVERRIDE2 */
1195 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
1196 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1197 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1198 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4));
1199
1200 db_shader_control = sctx->ps_db_shader_control;
1201
1202 /* Bug workaround for smoothing (overrasterization) on SI. */
1203 if (sctx->b.chip_class == SI && sctx->smoothing_enabled) {
1204 db_shader_control &= C_02880C_Z_ORDER;
1205 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1206 }
1207
1208 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1209 if (!rs || !rs->multisample_enable)
1210 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1211
1212 if (sctx->screen->b.has_rbplus &&
1213 !sctx->screen->b.rbplus_allowed)
1214 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1215
1216 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
1217 db_shader_control);
1218 }
1219
1220 /*
1221 * format translation
1222 */
1223 static uint32_t si_translate_colorformat(enum pipe_format format)
1224 {
1225 const struct util_format_description *desc = util_format_description(format);
1226
1227 #define HAS_SIZE(x,y,z,w) \
1228 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1229 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1230
1231 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1232 return V_028C70_COLOR_10_11_11;
1233
1234 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1235 return V_028C70_COLOR_INVALID;
1236
1237 /* hw cannot support mixed formats (except depth/stencil, since
1238 * stencil is not written to). */
1239 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1240 return V_028C70_COLOR_INVALID;
1241
1242 switch (desc->nr_channels) {
1243 case 1:
1244 switch (desc->channel[0].size) {
1245 case 8:
1246 return V_028C70_COLOR_8;
1247 case 16:
1248 return V_028C70_COLOR_16;
1249 case 32:
1250 return V_028C70_COLOR_32;
1251 }
1252 break;
1253 case 2:
1254 if (desc->channel[0].size == desc->channel[1].size) {
1255 switch (desc->channel[0].size) {
1256 case 8:
1257 return V_028C70_COLOR_8_8;
1258 case 16:
1259 return V_028C70_COLOR_16_16;
1260 case 32:
1261 return V_028C70_COLOR_32_32;
1262 }
1263 } else if (HAS_SIZE(8,24,0,0)) {
1264 return V_028C70_COLOR_24_8;
1265 } else if (HAS_SIZE(24,8,0,0)) {
1266 return V_028C70_COLOR_8_24;
1267 }
1268 break;
1269 case 3:
1270 if (HAS_SIZE(5,6,5,0)) {
1271 return V_028C70_COLOR_5_6_5;
1272 } else if (HAS_SIZE(32,8,24,0)) {
1273 return V_028C70_COLOR_X24_8_32_FLOAT;
1274 }
1275 break;
1276 case 4:
1277 if (desc->channel[0].size == desc->channel[1].size &&
1278 desc->channel[0].size == desc->channel[2].size &&
1279 desc->channel[0].size == desc->channel[3].size) {
1280 switch (desc->channel[0].size) {
1281 case 4:
1282 return V_028C70_COLOR_4_4_4_4;
1283 case 8:
1284 return V_028C70_COLOR_8_8_8_8;
1285 case 16:
1286 return V_028C70_COLOR_16_16_16_16;
1287 case 32:
1288 return V_028C70_COLOR_32_32_32_32;
1289 }
1290 } else if (HAS_SIZE(5,5,5,1)) {
1291 return V_028C70_COLOR_1_5_5_5;
1292 } else if (HAS_SIZE(10,10,10,2)) {
1293 return V_028C70_COLOR_2_10_10_10;
1294 }
1295 break;
1296 }
1297 return V_028C70_COLOR_INVALID;
1298 }
1299
1300 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1301 {
1302 if (SI_BIG_ENDIAN) {
1303 switch(colorformat) {
1304 /* 8-bit buffers. */
1305 case V_028C70_COLOR_8:
1306 return V_028C70_ENDIAN_NONE;
1307
1308 /* 16-bit buffers. */
1309 case V_028C70_COLOR_5_6_5:
1310 case V_028C70_COLOR_1_5_5_5:
1311 case V_028C70_COLOR_4_4_4_4:
1312 case V_028C70_COLOR_16:
1313 case V_028C70_COLOR_8_8:
1314 return V_028C70_ENDIAN_8IN16;
1315
1316 /* 32-bit buffers. */
1317 case V_028C70_COLOR_8_8_8_8:
1318 case V_028C70_COLOR_2_10_10_10:
1319 case V_028C70_COLOR_8_24:
1320 case V_028C70_COLOR_24_8:
1321 case V_028C70_COLOR_16_16:
1322 return V_028C70_ENDIAN_8IN32;
1323
1324 /* 64-bit buffers. */
1325 case V_028C70_COLOR_16_16_16_16:
1326 return V_028C70_ENDIAN_8IN16;
1327
1328 case V_028C70_COLOR_32_32:
1329 return V_028C70_ENDIAN_8IN32;
1330
1331 /* 128-bit buffers. */
1332 case V_028C70_COLOR_32_32_32_32:
1333 return V_028C70_ENDIAN_8IN32;
1334 default:
1335 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1336 }
1337 } else {
1338 return V_028C70_ENDIAN_NONE;
1339 }
1340 }
1341
1342 static uint32_t si_translate_dbformat(enum pipe_format format)
1343 {
1344 switch (format) {
1345 case PIPE_FORMAT_Z16_UNORM:
1346 return V_028040_Z_16;
1347 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1348 case PIPE_FORMAT_X8Z24_UNORM:
1349 case PIPE_FORMAT_Z24X8_UNORM:
1350 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1351 return V_028040_Z_24; /* deprecated on SI */
1352 case PIPE_FORMAT_Z32_FLOAT:
1353 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1354 return V_028040_Z_32_FLOAT;
1355 default:
1356 return V_028040_Z_INVALID;
1357 }
1358 }
1359
1360 /*
1361 * Texture translation
1362 */
1363
1364 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1365 enum pipe_format format,
1366 const struct util_format_description *desc,
1367 int first_non_void)
1368 {
1369 struct si_screen *sscreen = (struct si_screen*)screen;
1370 bool enable_compressed_formats = (sscreen->b.info.drm_major == 2 &&
1371 sscreen->b.info.drm_minor >= 31) ||
1372 sscreen->b.info.drm_major == 3;
1373 bool uniform = true;
1374 int i;
1375
1376 /* Colorspace (return non-RGB formats directly). */
1377 switch (desc->colorspace) {
1378 /* Depth stencil formats */
1379 case UTIL_FORMAT_COLORSPACE_ZS:
1380 switch (format) {
1381 case PIPE_FORMAT_Z16_UNORM:
1382 return V_008F14_IMG_DATA_FORMAT_16;
1383 case PIPE_FORMAT_X24S8_UINT:
1384 case PIPE_FORMAT_S8X24_UINT:
1385 /*
1386 * Implemented as an 8_8_8_8 data format to fix texture
1387 * gathers in stencil sampling. This affects at least
1388 * GL45-CTS.texture_cube_map_array.sampling on VI.
1389 */
1390 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1391 case PIPE_FORMAT_Z24X8_UNORM:
1392 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1393 return V_008F14_IMG_DATA_FORMAT_8_24;
1394 case PIPE_FORMAT_X8Z24_UNORM:
1395 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1396 return V_008F14_IMG_DATA_FORMAT_24_8;
1397 case PIPE_FORMAT_S8_UINT:
1398 return V_008F14_IMG_DATA_FORMAT_8;
1399 case PIPE_FORMAT_Z32_FLOAT:
1400 return V_008F14_IMG_DATA_FORMAT_32;
1401 case PIPE_FORMAT_X32_S8X24_UINT:
1402 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1403 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1404 default:
1405 goto out_unknown;
1406 }
1407
1408 case UTIL_FORMAT_COLORSPACE_YUV:
1409 goto out_unknown; /* TODO */
1410
1411 case UTIL_FORMAT_COLORSPACE_SRGB:
1412 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1413 goto out_unknown;
1414 break;
1415
1416 default:
1417 break;
1418 }
1419
1420 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1421 if (!enable_compressed_formats)
1422 goto out_unknown;
1423
1424 switch (format) {
1425 case PIPE_FORMAT_RGTC1_SNORM:
1426 case PIPE_FORMAT_LATC1_SNORM:
1427 case PIPE_FORMAT_RGTC1_UNORM:
1428 case PIPE_FORMAT_LATC1_UNORM:
1429 return V_008F14_IMG_DATA_FORMAT_BC4;
1430 case PIPE_FORMAT_RGTC2_SNORM:
1431 case PIPE_FORMAT_LATC2_SNORM:
1432 case PIPE_FORMAT_RGTC2_UNORM:
1433 case PIPE_FORMAT_LATC2_UNORM:
1434 return V_008F14_IMG_DATA_FORMAT_BC5;
1435 default:
1436 goto out_unknown;
1437 }
1438 }
1439
1440 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1441 (sscreen->b.family == CHIP_STONEY ||
1442 sscreen->b.chip_class >= GFX9)) {
1443 switch (format) {
1444 case PIPE_FORMAT_ETC1_RGB8:
1445 case PIPE_FORMAT_ETC2_RGB8:
1446 case PIPE_FORMAT_ETC2_SRGB8:
1447 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1448 case PIPE_FORMAT_ETC2_RGB8A1:
1449 case PIPE_FORMAT_ETC2_SRGB8A1:
1450 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1451 case PIPE_FORMAT_ETC2_RGBA8:
1452 case PIPE_FORMAT_ETC2_SRGBA8:
1453 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1454 case PIPE_FORMAT_ETC2_R11_UNORM:
1455 case PIPE_FORMAT_ETC2_R11_SNORM:
1456 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1457 case PIPE_FORMAT_ETC2_RG11_UNORM:
1458 case PIPE_FORMAT_ETC2_RG11_SNORM:
1459 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1460 default:
1461 goto out_unknown;
1462 }
1463 }
1464
1465 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1466 if (!enable_compressed_formats)
1467 goto out_unknown;
1468
1469 switch (format) {
1470 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1471 case PIPE_FORMAT_BPTC_SRGBA:
1472 return V_008F14_IMG_DATA_FORMAT_BC7;
1473 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1474 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1475 return V_008F14_IMG_DATA_FORMAT_BC6;
1476 default:
1477 goto out_unknown;
1478 }
1479 }
1480
1481 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1482 switch (format) {
1483 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1484 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1485 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1486 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1487 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1488 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1489 default:
1490 goto out_unknown;
1491 }
1492 }
1493
1494 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1495 if (!enable_compressed_formats)
1496 goto out_unknown;
1497
1498 if (!util_format_s3tc_enabled) {
1499 goto out_unknown;
1500 }
1501
1502 switch (format) {
1503 case PIPE_FORMAT_DXT1_RGB:
1504 case PIPE_FORMAT_DXT1_RGBA:
1505 case PIPE_FORMAT_DXT1_SRGB:
1506 case PIPE_FORMAT_DXT1_SRGBA:
1507 return V_008F14_IMG_DATA_FORMAT_BC1;
1508 case PIPE_FORMAT_DXT3_RGBA:
1509 case PIPE_FORMAT_DXT3_SRGBA:
1510 return V_008F14_IMG_DATA_FORMAT_BC2;
1511 case PIPE_FORMAT_DXT5_RGBA:
1512 case PIPE_FORMAT_DXT5_SRGBA:
1513 return V_008F14_IMG_DATA_FORMAT_BC3;
1514 default:
1515 goto out_unknown;
1516 }
1517 }
1518
1519 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1520 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1521 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1522 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1523 }
1524
1525 /* R8G8Bx_SNORM - TODO CxV8U8 */
1526
1527 /* hw cannot support mixed formats (except depth/stencil, since only
1528 * depth is read).*/
1529 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1530 goto out_unknown;
1531
1532 /* See whether the components are of the same size. */
1533 for (i = 1; i < desc->nr_channels; i++) {
1534 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1535 }
1536
1537 /* Non-uniform formats. */
1538 if (!uniform) {
1539 switch(desc->nr_channels) {
1540 case 3:
1541 if (desc->channel[0].size == 5 &&
1542 desc->channel[1].size == 6 &&
1543 desc->channel[2].size == 5) {
1544 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1545 }
1546 goto out_unknown;
1547 case 4:
1548 if (desc->channel[0].size == 5 &&
1549 desc->channel[1].size == 5 &&
1550 desc->channel[2].size == 5 &&
1551 desc->channel[3].size == 1) {
1552 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1553 }
1554 if (desc->channel[0].size == 10 &&
1555 desc->channel[1].size == 10 &&
1556 desc->channel[2].size == 10 &&
1557 desc->channel[3].size == 2) {
1558 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1559 }
1560 goto out_unknown;
1561 }
1562 goto out_unknown;
1563 }
1564
1565 if (first_non_void < 0 || first_non_void > 3)
1566 goto out_unknown;
1567
1568 /* uniform formats */
1569 switch (desc->channel[first_non_void].size) {
1570 case 4:
1571 switch (desc->nr_channels) {
1572 #if 0 /* Not supported for render targets */
1573 case 2:
1574 return V_008F14_IMG_DATA_FORMAT_4_4;
1575 #endif
1576 case 4:
1577 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1578 }
1579 break;
1580 case 8:
1581 switch (desc->nr_channels) {
1582 case 1:
1583 return V_008F14_IMG_DATA_FORMAT_8;
1584 case 2:
1585 return V_008F14_IMG_DATA_FORMAT_8_8;
1586 case 4:
1587 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1588 }
1589 break;
1590 case 16:
1591 switch (desc->nr_channels) {
1592 case 1:
1593 return V_008F14_IMG_DATA_FORMAT_16;
1594 case 2:
1595 return V_008F14_IMG_DATA_FORMAT_16_16;
1596 case 4:
1597 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1598 }
1599 break;
1600 case 32:
1601 switch (desc->nr_channels) {
1602 case 1:
1603 return V_008F14_IMG_DATA_FORMAT_32;
1604 case 2:
1605 return V_008F14_IMG_DATA_FORMAT_32_32;
1606 #if 0 /* Not supported for render targets */
1607 case 3:
1608 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1609 #endif
1610 case 4:
1611 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1612 }
1613 }
1614
1615 out_unknown:
1616 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1617 return ~0;
1618 }
1619
1620 static unsigned si_tex_wrap(unsigned wrap)
1621 {
1622 switch (wrap) {
1623 default:
1624 case PIPE_TEX_WRAP_REPEAT:
1625 return V_008F30_SQ_TEX_WRAP;
1626 case PIPE_TEX_WRAP_CLAMP:
1627 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1628 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1629 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1630 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1631 return V_008F30_SQ_TEX_CLAMP_BORDER;
1632 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1633 return V_008F30_SQ_TEX_MIRROR;
1634 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1635 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1636 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1637 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1638 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1639 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1640 }
1641 }
1642
1643 static unsigned si_tex_mipfilter(unsigned filter)
1644 {
1645 switch (filter) {
1646 case PIPE_TEX_MIPFILTER_NEAREST:
1647 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1648 case PIPE_TEX_MIPFILTER_LINEAR:
1649 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1650 default:
1651 case PIPE_TEX_MIPFILTER_NONE:
1652 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1653 }
1654 }
1655
1656 static unsigned si_tex_compare(unsigned compare)
1657 {
1658 switch (compare) {
1659 default:
1660 case PIPE_FUNC_NEVER:
1661 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1662 case PIPE_FUNC_LESS:
1663 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1664 case PIPE_FUNC_EQUAL:
1665 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1666 case PIPE_FUNC_LEQUAL:
1667 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1668 case PIPE_FUNC_GREATER:
1669 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1670 case PIPE_FUNC_NOTEQUAL:
1671 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1672 case PIPE_FUNC_GEQUAL:
1673 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1674 case PIPE_FUNC_ALWAYS:
1675 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1676 }
1677 }
1678
1679 static unsigned si_tex_dim(struct si_screen *sscreen, struct r600_texture *rtex,
1680 unsigned view_target, unsigned nr_samples)
1681 {
1682 unsigned res_target = rtex->resource.b.b.target;
1683
1684 if (view_target == PIPE_TEXTURE_CUBE ||
1685 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1686 res_target = view_target;
1687 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1688 else if (res_target == PIPE_TEXTURE_CUBE ||
1689 res_target == PIPE_TEXTURE_CUBE_ARRAY)
1690 res_target = PIPE_TEXTURE_2D_ARRAY;
1691
1692 /* GFX9 allocates 1D textures as 2D. */
1693 if ((res_target == PIPE_TEXTURE_1D ||
1694 res_target == PIPE_TEXTURE_1D_ARRAY) &&
1695 sscreen->b.chip_class >= GFX9 &&
1696 rtex->surface.u.gfx9.resource_type == RADEON_RESOURCE_2D) {
1697 if (res_target == PIPE_TEXTURE_1D)
1698 res_target = PIPE_TEXTURE_2D;
1699 else
1700 res_target = PIPE_TEXTURE_2D_ARRAY;
1701 }
1702
1703 switch (res_target) {
1704 default:
1705 case PIPE_TEXTURE_1D:
1706 return V_008F1C_SQ_RSRC_IMG_1D;
1707 case PIPE_TEXTURE_1D_ARRAY:
1708 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1709 case PIPE_TEXTURE_2D:
1710 case PIPE_TEXTURE_RECT:
1711 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1712 V_008F1C_SQ_RSRC_IMG_2D;
1713 case PIPE_TEXTURE_2D_ARRAY:
1714 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1715 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1716 case PIPE_TEXTURE_3D:
1717 return V_008F1C_SQ_RSRC_IMG_3D;
1718 case PIPE_TEXTURE_CUBE:
1719 case PIPE_TEXTURE_CUBE_ARRAY:
1720 return V_008F1C_SQ_RSRC_IMG_CUBE;
1721 }
1722 }
1723
1724 /*
1725 * Format support testing
1726 */
1727
1728 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1729 {
1730 return si_translate_texformat(screen, format, util_format_description(format),
1731 util_format_get_first_non_void_channel(format)) != ~0U;
1732 }
1733
1734 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1735 const struct util_format_description *desc,
1736 int first_non_void)
1737 {
1738 int i;
1739
1740 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1741 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1742
1743 assert(first_non_void >= 0);
1744
1745 if (desc->nr_channels == 4 &&
1746 desc->channel[0].size == 10 &&
1747 desc->channel[1].size == 10 &&
1748 desc->channel[2].size == 10 &&
1749 desc->channel[3].size == 2)
1750 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1751
1752 /* See whether the components are of the same size. */
1753 for (i = 0; i < desc->nr_channels; i++) {
1754 if (desc->channel[first_non_void].size != desc->channel[i].size)
1755 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1756 }
1757
1758 switch (desc->channel[first_non_void].size) {
1759 case 8:
1760 switch (desc->nr_channels) {
1761 case 1:
1762 case 3: /* 3 loads */
1763 return V_008F0C_BUF_DATA_FORMAT_8;
1764 case 2:
1765 return V_008F0C_BUF_DATA_FORMAT_8_8;
1766 case 4:
1767 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1768 }
1769 break;
1770 case 16:
1771 switch (desc->nr_channels) {
1772 case 1:
1773 case 3: /* 3 loads */
1774 return V_008F0C_BUF_DATA_FORMAT_16;
1775 case 2:
1776 return V_008F0C_BUF_DATA_FORMAT_16_16;
1777 case 4:
1778 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1779 }
1780 break;
1781 case 32:
1782 switch (desc->nr_channels) {
1783 case 1:
1784 return V_008F0C_BUF_DATA_FORMAT_32;
1785 case 2:
1786 return V_008F0C_BUF_DATA_FORMAT_32_32;
1787 case 3:
1788 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1789 case 4:
1790 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1791 }
1792 break;
1793 case 64:
1794 /* Legacy double formats. */
1795 switch (desc->nr_channels) {
1796 case 1: /* 1 load */
1797 return V_008F0C_BUF_DATA_FORMAT_32_32;
1798 case 2: /* 1 load */
1799 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1800 case 3: /* 3 loads */
1801 return V_008F0C_BUF_DATA_FORMAT_32_32;
1802 case 4: /* 2 loads */
1803 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1804 }
1805 break;
1806 }
1807
1808 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1809 }
1810
1811 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1812 const struct util_format_description *desc,
1813 int first_non_void)
1814 {
1815 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1816 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1817
1818 assert(first_non_void >= 0);
1819
1820 switch (desc->channel[first_non_void].type) {
1821 case UTIL_FORMAT_TYPE_SIGNED:
1822 case UTIL_FORMAT_TYPE_FIXED:
1823 if (desc->channel[first_non_void].size >= 32 ||
1824 desc->channel[first_non_void].pure_integer)
1825 return V_008F0C_BUF_NUM_FORMAT_SINT;
1826 else if (desc->channel[first_non_void].normalized)
1827 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1828 else
1829 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1830 break;
1831 case UTIL_FORMAT_TYPE_UNSIGNED:
1832 if (desc->channel[first_non_void].size >= 32 ||
1833 desc->channel[first_non_void].pure_integer)
1834 return V_008F0C_BUF_NUM_FORMAT_UINT;
1835 else if (desc->channel[first_non_void].normalized)
1836 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1837 else
1838 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1839 break;
1840 case UTIL_FORMAT_TYPE_FLOAT:
1841 default:
1842 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1843 }
1844 }
1845
1846 static unsigned si_is_vertex_format_supported(struct pipe_screen *screen,
1847 enum pipe_format format,
1848 unsigned usage)
1849 {
1850 const struct util_format_description *desc;
1851 int first_non_void;
1852 unsigned data_format;
1853
1854 assert((usage & ~(PIPE_BIND_SHADER_IMAGE |
1855 PIPE_BIND_SAMPLER_VIEW |
1856 PIPE_BIND_VERTEX_BUFFER)) == 0);
1857
1858 desc = util_format_description(format);
1859
1860 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
1861 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
1862 * for read-only access (with caveats surrounding bounds checks), but
1863 * obviously fails for write access which we have to implement for
1864 * shader images. Luckily, OpenGL doesn't expect this to be supported
1865 * anyway, and so the only impact is on PBO uploads / downloads, which
1866 * shouldn't be expected to be fast for GL_RGB anyway.
1867 */
1868 if (desc->block.bits == 3 * 8 ||
1869 desc->block.bits == 3 * 16) {
1870 if (usage & (PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW)) {
1871 usage &= ~(PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW);
1872 if (!usage)
1873 return 0;
1874 }
1875 }
1876
1877 first_non_void = util_format_get_first_non_void_channel(format);
1878 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1879 if (data_format == V_008F0C_BUF_DATA_FORMAT_INVALID)
1880 return 0;
1881
1882 return usage;
1883 }
1884
1885 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1886 {
1887 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1888 r600_translate_colorswap(format, false) != ~0U;
1889 }
1890
1891 static bool si_is_zs_format_supported(enum pipe_format format)
1892 {
1893 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1894 }
1895
1896 static boolean si_is_format_supported(struct pipe_screen *screen,
1897 enum pipe_format format,
1898 enum pipe_texture_target target,
1899 unsigned sample_count,
1900 unsigned usage)
1901 {
1902 unsigned retval = 0;
1903
1904 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1905 R600_ERR("r600: unsupported texture type %d\n", target);
1906 return false;
1907 }
1908
1909 if (!util_format_is_supported(format, usage))
1910 return false;
1911
1912 if (sample_count > 1) {
1913 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
1914 return false;
1915
1916 if (usage & PIPE_BIND_SHADER_IMAGE)
1917 return false;
1918
1919 switch (sample_count) {
1920 case 2:
1921 case 4:
1922 case 8:
1923 break;
1924 case 16:
1925 if (format == PIPE_FORMAT_NONE)
1926 return true;
1927 else
1928 return false;
1929 default:
1930 return false;
1931 }
1932 }
1933
1934 if (usage & (PIPE_BIND_SAMPLER_VIEW |
1935 PIPE_BIND_SHADER_IMAGE)) {
1936 if (target == PIPE_BUFFER) {
1937 retval |= si_is_vertex_format_supported(
1938 screen, format, usage & (PIPE_BIND_SAMPLER_VIEW |
1939 PIPE_BIND_SHADER_IMAGE));
1940 } else {
1941 if (si_is_sampler_format_supported(screen, format))
1942 retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
1943 PIPE_BIND_SHADER_IMAGE);
1944 }
1945 }
1946
1947 if ((usage & (PIPE_BIND_RENDER_TARGET |
1948 PIPE_BIND_DISPLAY_TARGET |
1949 PIPE_BIND_SCANOUT |
1950 PIPE_BIND_SHARED |
1951 PIPE_BIND_BLENDABLE)) &&
1952 si_is_colorbuffer_format_supported(format)) {
1953 retval |= usage &
1954 (PIPE_BIND_RENDER_TARGET |
1955 PIPE_BIND_DISPLAY_TARGET |
1956 PIPE_BIND_SCANOUT |
1957 PIPE_BIND_SHARED);
1958 if (!util_format_is_pure_integer(format) &&
1959 !util_format_is_depth_or_stencil(format))
1960 retval |= usage & PIPE_BIND_BLENDABLE;
1961 }
1962
1963 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1964 si_is_zs_format_supported(format)) {
1965 retval |= PIPE_BIND_DEPTH_STENCIL;
1966 }
1967
1968 if (usage & PIPE_BIND_VERTEX_BUFFER) {
1969 retval |= si_is_vertex_format_supported(screen, format,
1970 PIPE_BIND_VERTEX_BUFFER);
1971 }
1972
1973 if ((usage & PIPE_BIND_LINEAR) &&
1974 !util_format_is_compressed(format) &&
1975 !(usage & PIPE_BIND_DEPTH_STENCIL))
1976 retval |= PIPE_BIND_LINEAR;
1977
1978 return retval == usage;
1979 }
1980
1981 /*
1982 * framebuffer handling
1983 */
1984
1985 static void si_choose_spi_color_formats(struct r600_surface *surf,
1986 unsigned format, unsigned swap,
1987 unsigned ntype, bool is_depth)
1988 {
1989 /* Alpha is needed for alpha-to-coverage.
1990 * Blending may be with or without alpha.
1991 */
1992 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
1993 unsigned alpha = 0; /* exports alpha, but may not support blending */
1994 unsigned blend = 0; /* supports blending, but may not export alpha */
1995 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
1996
1997 /* Choose the SPI color formats. These are required values for RB+.
1998 * Other chips have multiple choices, though they are not necessarily better.
1999 */
2000 switch (format) {
2001 case V_028C70_COLOR_5_6_5:
2002 case V_028C70_COLOR_1_5_5_5:
2003 case V_028C70_COLOR_5_5_5_1:
2004 case V_028C70_COLOR_4_4_4_4:
2005 case V_028C70_COLOR_10_11_11:
2006 case V_028C70_COLOR_11_11_10:
2007 case V_028C70_COLOR_8:
2008 case V_028C70_COLOR_8_8:
2009 case V_028C70_COLOR_8_8_8_8:
2010 case V_028C70_COLOR_10_10_10_2:
2011 case V_028C70_COLOR_2_10_10_10:
2012 if (ntype == V_028C70_NUMBER_UINT)
2013 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2014 else if (ntype == V_028C70_NUMBER_SINT)
2015 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2016 else
2017 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2018 break;
2019
2020 case V_028C70_COLOR_16:
2021 case V_028C70_COLOR_16_16:
2022 case V_028C70_COLOR_16_16_16_16:
2023 if (ntype == V_028C70_NUMBER_UNORM ||
2024 ntype == V_028C70_NUMBER_SNORM) {
2025 /* UNORM16 and SNORM16 don't support blending */
2026 if (ntype == V_028C70_NUMBER_UNORM)
2027 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
2028 else
2029 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
2030
2031 /* Use 32 bits per channel for blending. */
2032 if (format == V_028C70_COLOR_16) {
2033 if (swap == V_028C70_SWAP_STD) { /* R */
2034 blend = V_028714_SPI_SHADER_32_R;
2035 blend_alpha = V_028714_SPI_SHADER_32_AR;
2036 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2037 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2038 else
2039 assert(0);
2040 } else if (format == V_028C70_COLOR_16_16) {
2041 if (swap == V_028C70_SWAP_STD) { /* RG */
2042 blend = V_028714_SPI_SHADER_32_GR;
2043 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2044 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2045 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2046 else
2047 assert(0);
2048 } else /* 16_16_16_16 */
2049 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2050 } else if (ntype == V_028C70_NUMBER_UINT)
2051 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2052 else if (ntype == V_028C70_NUMBER_SINT)
2053 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2054 else if (ntype == V_028C70_NUMBER_FLOAT)
2055 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2056 else
2057 assert(0);
2058 break;
2059
2060 case V_028C70_COLOR_32:
2061 if (swap == V_028C70_SWAP_STD) { /* R */
2062 blend = normal = V_028714_SPI_SHADER_32_R;
2063 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
2064 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2065 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2066 else
2067 assert(0);
2068 break;
2069
2070 case V_028C70_COLOR_32_32:
2071 if (swap == V_028C70_SWAP_STD) { /* RG */
2072 blend = normal = V_028714_SPI_SHADER_32_GR;
2073 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2074 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2075 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2076 else
2077 assert(0);
2078 break;
2079
2080 case V_028C70_COLOR_32_32_32_32:
2081 case V_028C70_COLOR_8_24:
2082 case V_028C70_COLOR_24_8:
2083 case V_028C70_COLOR_X24_8_32_FLOAT:
2084 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2085 break;
2086
2087 default:
2088 assert(0);
2089 return;
2090 }
2091
2092 /* The DB->CB copy needs 32_ABGR. */
2093 if (is_depth)
2094 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2095
2096 surf->spi_shader_col_format = normal;
2097 surf->spi_shader_col_format_alpha = alpha;
2098 surf->spi_shader_col_format_blend = blend;
2099 surf->spi_shader_col_format_blend_alpha = blend_alpha;
2100 }
2101
2102 static void si_initialize_color_surface(struct si_context *sctx,
2103 struct r600_surface *surf)
2104 {
2105 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2106 unsigned color_info, color_attrib, color_view;
2107 unsigned format, swap, ntype, endian;
2108 const struct util_format_description *desc;
2109 int i;
2110 unsigned blend_clamp = 0, blend_bypass = 0;
2111
2112 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2113 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
2114
2115 desc = util_format_description(surf->base.format);
2116 for (i = 0; i < 4; i++) {
2117 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2118 break;
2119 }
2120 }
2121 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
2122 ntype = V_028C70_NUMBER_FLOAT;
2123 } else {
2124 ntype = V_028C70_NUMBER_UNORM;
2125 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2126 ntype = V_028C70_NUMBER_SRGB;
2127 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2128 if (desc->channel[i].pure_integer) {
2129 ntype = V_028C70_NUMBER_SINT;
2130 } else {
2131 assert(desc->channel[i].normalized);
2132 ntype = V_028C70_NUMBER_SNORM;
2133 }
2134 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2135 if (desc->channel[i].pure_integer) {
2136 ntype = V_028C70_NUMBER_UINT;
2137 } else {
2138 assert(desc->channel[i].normalized);
2139 ntype = V_028C70_NUMBER_UNORM;
2140 }
2141 }
2142 }
2143
2144 format = si_translate_colorformat(surf->base.format);
2145 if (format == V_028C70_COLOR_INVALID) {
2146 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2147 }
2148 assert(format != V_028C70_COLOR_INVALID);
2149 swap = r600_translate_colorswap(surf->base.format, false);
2150 endian = si_colorformat_endian_swap(format);
2151
2152 /* blend clamp should be set for all NORM/SRGB types */
2153 if (ntype == V_028C70_NUMBER_UNORM ||
2154 ntype == V_028C70_NUMBER_SNORM ||
2155 ntype == V_028C70_NUMBER_SRGB)
2156 blend_clamp = 1;
2157
2158 /* set blend bypass according to docs if SINT/UINT or
2159 8/24 COLOR variants */
2160 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2161 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2162 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2163 blend_clamp = 0;
2164 blend_bypass = 1;
2165 }
2166
2167 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) {
2168 if (format == V_028C70_COLOR_8 ||
2169 format == V_028C70_COLOR_8_8 ||
2170 format == V_028C70_COLOR_8_8_8_8)
2171 surf->color_is_int8 = true;
2172 else if (format == V_028C70_COLOR_10_10_10_2 ||
2173 format == V_028C70_COLOR_2_10_10_10)
2174 surf->color_is_int10 = true;
2175 }
2176
2177 color_info = S_028C70_FORMAT(format) |
2178 S_028C70_COMP_SWAP(swap) |
2179 S_028C70_BLEND_CLAMP(blend_clamp) |
2180 S_028C70_BLEND_BYPASS(blend_bypass) |
2181 S_028C70_SIMPLE_FLOAT(1) |
2182 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2183 ntype != V_028C70_NUMBER_SNORM &&
2184 ntype != V_028C70_NUMBER_SRGB &&
2185 format != V_028C70_COLOR_8_24 &&
2186 format != V_028C70_COLOR_24_8) |
2187 S_028C70_NUMBER_TYPE(ntype) |
2188 S_028C70_ENDIAN(endian);
2189
2190 /* Intensity is implemented as Red, so treat it that way. */
2191 color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2192 util_format_is_intensity(surf->base.format));
2193
2194 if (rtex->resource.b.b.nr_samples > 1) {
2195 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
2196
2197 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2198 S_028C74_NUM_FRAGMENTS(log_samples);
2199
2200 if (rtex->fmask.size) {
2201 /* TODO: fix FMASK on GFX9: */
2202 color_info |= S_028C70_COMPRESSION(sctx->b.chip_class <= VI);
2203 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
2204
2205 if (sctx->b.chip_class == SI) {
2206 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2207 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2208 }
2209 }
2210 }
2211
2212 surf->cb_color_view = color_view;
2213 surf->cb_color_info = color_info;
2214 surf->cb_color_attrib = color_attrib;
2215
2216 if (sctx->b.chip_class >= VI) {
2217 unsigned max_uncompressed_block_size = 2;
2218
2219 if (rtex->resource.b.b.nr_samples > 1) {
2220 if (rtex->surface.bpe == 1)
2221 max_uncompressed_block_size = 0;
2222 else if (rtex->surface.bpe == 2)
2223 max_uncompressed_block_size = 1;
2224 }
2225
2226 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2227 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2228 }
2229
2230 /* This must be set for fast clear to work without FMASK. */
2231 if (!rtex->fmask.size && sctx->b.chip_class == SI) {
2232 unsigned bankh = util_logbase2(rtex->surface.u.legacy.bankh);
2233 surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2234 }
2235
2236 if (sctx->b.chip_class >= GFX9) {
2237 unsigned mip0_depth = util_max_layer(&rtex->resource.b.b, 0);
2238
2239 surf->cb_color_view |= S_028C6C_MIP_LEVEL(surf->base.u.tex.level);
2240 surf->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
2241 S_028C74_RESOURCE_TYPE(rtex->surface.u.gfx9.resource_type);
2242 surf->cb_color_attrib2 = S_028C68_MIP0_WIDTH(surf->width0 - 1) |
2243 S_028C68_MIP0_HEIGHT(surf->height0 - 1) |
2244 S_028C68_MAX_MIP(rtex->resource.b.b.last_level);
2245 }
2246
2247 /* Determine pixel shader export format */
2248 si_choose_spi_color_formats(surf, format, swap, ntype, rtex->is_depth);
2249
2250 surf->color_initialized = true;
2251 }
2252
2253 static void si_init_depth_surface(struct si_context *sctx,
2254 struct r600_surface *surf)
2255 {
2256 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2257 unsigned level = surf->base.u.tex.level;
2258 unsigned format, stencil_format;
2259 uint32_t z_info, s_info;
2260
2261 format = si_translate_dbformat(rtex->db_render_format);
2262 stencil_format = rtex->surface.flags & RADEON_SURF_SBUFFER ?
2263 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
2264
2265 assert(format != V_028040_Z_INVALID);
2266 if (format == V_028040_Z_INVALID)
2267 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
2268
2269 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2270 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2271 surf->db_htile_data_base = 0;
2272 surf->db_htile_surface = 0;
2273
2274 if (sctx->b.chip_class >= GFX9) {
2275 assert(rtex->surface.u.gfx9.surf_offset == 0);
2276 surf->db_depth_base = rtex->resource.gpu_address >> 8;
2277 surf->db_stencil_base = (rtex->resource.gpu_address +
2278 rtex->surface.u.gfx9.stencil_offset) >> 8;
2279 z_info = S_028038_FORMAT(format) |
2280 S_028038_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples)) |
2281 S_028038_SW_MODE(rtex->surface.u.gfx9.surf.swizzle_mode) |
2282 S_028038_MAXMIP(rtex->resource.b.b.last_level);
2283 s_info = S_02803C_FORMAT(stencil_format) |
2284 S_02803C_SW_MODE(rtex->surface.u.gfx9.stencil.swizzle_mode);
2285 surf->db_z_info2 = S_028068_EPITCH(rtex->surface.u.gfx9.surf.epitch);
2286 surf->db_stencil_info2 = S_02806C_EPITCH(rtex->surface.u.gfx9.stencil.epitch);
2287 surf->db_depth_view |= S_028008_MIPID(level);
2288 surf->db_depth_size = S_02801C_X_MAX(rtex->resource.b.b.width0 - 1) |
2289 S_02801C_Y_MAX(rtex->resource.b.b.height0 - 1);
2290
2291 /* Only use HTILE for the first level. */
2292 if (rtex->htile_buffer && !level) {
2293 z_info |= S_028038_TILE_SURFACE_ENABLE(1) |
2294 S_028038_ALLOW_EXPCLEAR(1);
2295
2296 if (rtex->tc_compatible_htile) {
2297 unsigned max_zplanes = 4;
2298
2299 if (rtex->db_render_format == PIPE_FORMAT_Z16_UNORM &&
2300 rtex->resource.b.b.nr_samples > 1)
2301 max_zplanes = 2;
2302
2303 z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1) |
2304 S_028038_ITERATE_FLUSH(1);
2305 s_info |= S_02803C_ITERATE_FLUSH(1);
2306 }
2307
2308 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
2309 /* Stencil buffer workaround ported from the SI-CI-VI code.
2310 * See that for explanation.
2311 */
2312 s_info |= S_02803C_ALLOW_EXPCLEAR(rtex->resource.b.b.nr_samples <= 1);
2313 } else {
2314 /* Use all HTILE for depth if there's no stencil. */
2315 s_info |= S_02803C_TILE_STENCIL_DISABLE(1);
2316 }
2317
2318 surf->db_htile_data_base = rtex->htile_buffer->gpu_address >> 8;
2319 surf->db_htile_surface = S_028ABC_FULL_CACHE(1) |
2320 S_028ABC_PIPE_ALIGNED(rtex->surface.u.gfx9.htile.pipe_aligned) |
2321 S_028ABC_RB_ALIGNED(rtex->surface.u.gfx9.htile.rb_aligned);
2322 }
2323 } else {
2324 /* SI-CI-VI */
2325 struct legacy_surf_level *levelinfo = &rtex->surface.u.legacy.level[level];
2326
2327 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2328
2329 surf->db_depth_base = (rtex->resource.gpu_address +
2330 rtex->surface.u.legacy.level[level].offset) >> 8;
2331 surf->db_stencil_base = (rtex->resource.gpu_address +
2332 rtex->surface.u.legacy.stencil_level[level].offset) >> 8;
2333
2334 z_info = S_028040_FORMAT(format) |
2335 S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
2336 s_info = S_028044_FORMAT(stencil_format);
2337 surf->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!rtex->tc_compatible_htile);
2338
2339 if (sctx->b.chip_class >= CIK) {
2340 struct radeon_info *info = &sctx->screen->b.info;
2341 unsigned index = rtex->surface.u.legacy.tiling_index[level];
2342 unsigned stencil_index = rtex->surface.u.legacy.stencil_tiling_index[level];
2343 unsigned macro_index = rtex->surface.u.legacy.macro_tile_index;
2344 unsigned tile_mode = info->si_tile_mode_array[index];
2345 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2346 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2347
2348 surf->db_depth_info |=
2349 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2350 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2351 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2352 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2353 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2354 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2355 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2356 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2357 } else {
2358 unsigned tile_mode_index = si_tile_mode_index(rtex, level, false);
2359 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2360 tile_mode_index = si_tile_mode_index(rtex, level, true);
2361 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2362 }
2363
2364 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2365 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2366 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2367 levelinfo->nblk_y) / 64 - 1);
2368
2369 /* Only use HTILE for the first level. */
2370 if (rtex->htile_buffer && !level) {
2371 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2372 S_028040_ALLOW_EXPCLEAR(1);
2373
2374 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
2375 /* Workaround: For a not yet understood reason, the
2376 * combination of MSAA, fast stencil clear and stencil
2377 * decompress messes with subsequent stencil buffer
2378 * uses. Problem was reproduced on Verde, Bonaire,
2379 * Tonga, and Carrizo.
2380 *
2381 * Disabling EXPCLEAR works around the problem.
2382 *
2383 * Check piglit's arb_texture_multisample-stencil-clear
2384 * test if you want to try changing this.
2385 */
2386 if (rtex->resource.b.b.nr_samples <= 1)
2387 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2388 } else if (!rtex->tc_compatible_htile) {
2389 /* Use all of the htile_buffer for depth if there's no stencil.
2390 * This must not be set when TC-compatible HTILE is enabled
2391 * due to a hw bug.
2392 */
2393 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2394 }
2395
2396 surf->db_htile_data_base = rtex->htile_buffer->gpu_address >> 8;
2397 surf->db_htile_surface = S_028ABC_FULL_CACHE(1);
2398
2399 if (rtex->tc_compatible_htile) {
2400 surf->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
2401
2402 if (rtex->resource.b.b.nr_samples <= 1)
2403 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2404 else if (rtex->resource.b.b.nr_samples <= 4)
2405 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2406 else
2407 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2408 }
2409 }
2410 }
2411
2412 surf->db_z_info = z_info;
2413 surf->db_stencil_info = s_info;
2414
2415 surf->depth_initialized = true;
2416 }
2417
2418 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
2419 {
2420 for (int i = 0; i < state->nr_cbufs; ++i) {
2421 struct r600_surface *surf = NULL;
2422 struct r600_texture *rtex;
2423
2424 if (!state->cbufs[i])
2425 continue;
2426 surf = (struct r600_surface*)state->cbufs[i];
2427 rtex = (struct r600_texture*)surf->base.texture;
2428
2429 p_atomic_dec(&rtex->framebuffers_bound);
2430 }
2431 }
2432
2433 static void si_set_framebuffer_state(struct pipe_context *ctx,
2434 const struct pipe_framebuffer_state *state)
2435 {
2436 struct si_context *sctx = (struct si_context *)ctx;
2437 struct pipe_constant_buffer constbuf = {0};
2438 struct r600_surface *surf = NULL;
2439 struct r600_texture *rtex;
2440 bool old_any_dst_linear = sctx->framebuffer.any_dst_linear;
2441 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2442 int i;
2443
2444 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
2445 if (!sctx->framebuffer.state.cbufs[i])
2446 continue;
2447
2448 rtex = (struct r600_texture*)sctx->framebuffer.state.cbufs[i]->texture;
2449 if (rtex->dcc_gather_statistics)
2450 vi_separate_dcc_stop_query(ctx, rtex);
2451 }
2452
2453 /* Only flush TC when changing the framebuffer state, because
2454 * the only client not using TC that can change textures is
2455 * the framebuffer.
2456 *
2457 * Flush all CB and DB caches here because all buffers can be used
2458 * for write by both TC (with shader image stores) and CB/DB.
2459 */
2460 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
2461 SI_CONTEXT_INV_GLOBAL_L2 |
2462 SI_CONTEXT_FLUSH_AND_INV_CB |
2463 SI_CONTEXT_FLUSH_AND_INV_DB |
2464 SI_CONTEXT_CS_PARTIAL_FLUSH;
2465
2466 /* Take the maximum of the old and new count. If the new count is lower,
2467 * dirtying is needed to disable the unbound colorbuffers.
2468 */
2469 sctx->framebuffer.dirty_cbufs |=
2470 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2471 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2472
2473 si_dec_framebuffer_counters(&sctx->framebuffer.state);
2474 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2475
2476 sctx->framebuffer.colorbuf_enabled_4bit = 0;
2477 sctx->framebuffer.spi_shader_col_format = 0;
2478 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2479 sctx->framebuffer.spi_shader_col_format_blend = 0;
2480 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2481 sctx->framebuffer.color_is_int8 = 0;
2482 sctx->framebuffer.color_is_int10 = 0;
2483
2484 sctx->framebuffer.compressed_cb_mask = 0;
2485 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2486 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2487 sctx->framebuffer.any_dst_linear = false;
2488
2489 for (i = 0; i < state->nr_cbufs; i++) {
2490 if (!state->cbufs[i])
2491 continue;
2492
2493 surf = (struct r600_surface*)state->cbufs[i];
2494 rtex = (struct r600_texture*)surf->base.texture;
2495
2496 if (!surf->color_initialized) {
2497 si_initialize_color_surface(sctx, surf);
2498 }
2499
2500 sctx->framebuffer.colorbuf_enabled_4bit |= 0xf << (i * 4);
2501 sctx->framebuffer.spi_shader_col_format |=
2502 surf->spi_shader_col_format << (i * 4);
2503 sctx->framebuffer.spi_shader_col_format_alpha |=
2504 surf->spi_shader_col_format_alpha << (i * 4);
2505 sctx->framebuffer.spi_shader_col_format_blend |=
2506 surf->spi_shader_col_format_blend << (i * 4);
2507 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2508 surf->spi_shader_col_format_blend_alpha << (i * 4);
2509
2510 if (surf->color_is_int8)
2511 sctx->framebuffer.color_is_int8 |= 1 << i;
2512 if (surf->color_is_int10)
2513 sctx->framebuffer.color_is_int10 |= 1 << i;
2514
2515 if (rtex->fmask.size) {
2516 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2517 }
2518
2519 if (rtex->surface.is_linear)
2520 sctx->framebuffer.any_dst_linear = true;
2521
2522 r600_context_add_resource_size(ctx, surf->base.texture);
2523
2524 p_atomic_inc(&rtex->framebuffers_bound);
2525
2526 if (rtex->dcc_gather_statistics) {
2527 /* Dirty tracking must be enabled for DCC usage analysis. */
2528 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2529 vi_separate_dcc_start_query(ctx, rtex);
2530 }
2531 }
2532
2533 if (state->zsbuf) {
2534 surf = (struct r600_surface*)state->zsbuf;
2535 rtex = (struct r600_texture*)surf->base.texture;
2536
2537 if (!surf->depth_initialized) {
2538 si_init_depth_surface(sctx, surf);
2539 }
2540 r600_context_add_resource_size(ctx, surf->base.texture);
2541 }
2542
2543 si_update_poly_offset_state(sctx);
2544 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2545 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
2546
2547 if (sctx->framebuffer.any_dst_linear != old_any_dst_linear)
2548 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2549
2550 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2551 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2552 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2553
2554 /* Set sample locations as fragment shader constants. */
2555 switch (sctx->framebuffer.nr_samples) {
2556 case 1:
2557 constbuf.user_buffer = sctx->b.sample_locations_1x;
2558 break;
2559 case 2:
2560 constbuf.user_buffer = sctx->b.sample_locations_2x;
2561 break;
2562 case 4:
2563 constbuf.user_buffer = sctx->b.sample_locations_4x;
2564 break;
2565 case 8:
2566 constbuf.user_buffer = sctx->b.sample_locations_8x;
2567 break;
2568 case 16:
2569 constbuf.user_buffer = sctx->b.sample_locations_16x;
2570 break;
2571 default:
2572 R600_ERR("Requested an invalid number of samples %i.\n",
2573 sctx->framebuffer.nr_samples);
2574 assert(0);
2575 }
2576 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2577 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
2578
2579 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
2580 }
2581
2582 sctx->need_check_render_feedback = true;
2583 sctx->do_update_shaders = true;
2584 sctx->framebuffer.do_update_surf_dirtiness = true;
2585 }
2586
2587 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
2588 {
2589 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2590 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2591 unsigned i, nr_cbufs = state->nr_cbufs;
2592 struct r600_texture *tex = NULL;
2593 struct r600_surface *cb = NULL;
2594 unsigned cb_color_info = 0;
2595
2596 /* Colorbuffers. */
2597 for (i = 0; i < nr_cbufs; i++) {
2598 uint64_t cb_color_base, cb_color_fmask, cb_dcc_base;
2599 unsigned cb_color_attrib;
2600
2601 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2602 continue;
2603
2604 cb = (struct r600_surface*)state->cbufs[i];
2605 if (!cb) {
2606 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2607 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2608 continue;
2609 }
2610
2611 tex = (struct r600_texture *)cb->base.texture;
2612 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2613 &tex->resource, RADEON_USAGE_READWRITE,
2614 tex->resource.b.b.nr_samples > 1 ?
2615 RADEON_PRIO_COLOR_BUFFER_MSAA :
2616 RADEON_PRIO_COLOR_BUFFER);
2617
2618 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2619 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2620 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2621 RADEON_PRIO_CMASK);
2622 }
2623
2624 if (tex->dcc_separate_buffer)
2625 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2626 tex->dcc_separate_buffer,
2627 RADEON_USAGE_READWRITE,
2628 RADEON_PRIO_DCC);
2629
2630 /* Compute mutable surface parameters. */
2631 cb_color_base = tex->resource.gpu_address >> 8;
2632 cb_color_fmask = cb_color_base;
2633 cb_dcc_base = 0;
2634 cb_color_info = cb->cb_color_info | tex->cb_color_info;
2635 cb_color_attrib = cb->cb_color_attrib;
2636
2637 if (tex->fmask.size)
2638 cb_color_fmask = (tex->resource.gpu_address + tex->fmask.offset) >> 8;
2639
2640 /* Set up DCC. */
2641 if (vi_dcc_enabled(tex, cb->base.u.tex.level)) {
2642 bool is_msaa_resolve_dst = state->cbufs[0] &&
2643 state->cbufs[0]->texture->nr_samples > 1 &&
2644 state->cbufs[1] == &cb->base &&
2645 state->cbufs[1]->texture->nr_samples <= 1;
2646
2647 if (!is_msaa_resolve_dst)
2648 cb_color_info |= S_028C70_DCC_ENABLE(1);
2649
2650 cb_dcc_base = ((!tex->dcc_separate_buffer ? tex->resource.gpu_address : 0) +
2651 tex->dcc_offset) >> 8;
2652 }
2653
2654 if (sctx->b.chip_class >= GFX9) {
2655 struct gfx9_surf_meta_flags meta;
2656
2657 if (tex->dcc_offset)
2658 meta = tex->surface.u.gfx9.dcc;
2659 else
2660 meta = tex->surface.u.gfx9.cmask;
2661
2662 /* Set mutable surface parameters. */
2663 cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
2664 cb_color_attrib |= S_028C74_COLOR_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
2665 S_028C74_FMASK_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
2666 S_028C74_RB_ALIGNED(meta.rb_aligned) |
2667 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
2668
2669 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 15);
2670 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
2671 radeon_emit(cs, cb_color_base >> 32); /* CB_COLOR0_BASE_EXT */
2672 radeon_emit(cs, cb->cb_color_attrib2); /* CB_COLOR0_ATTRIB2 */
2673 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
2674 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
2675 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
2676 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
2677 radeon_emit(cs, tex->cmask.base_address_reg); /* CB_COLOR0_CMASK */
2678 radeon_emit(cs, tex->cmask.base_address_reg >> 32); /* CB_COLOR0_CMASK_BASE_EXT */
2679 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
2680 radeon_emit(cs, cb_color_fmask >> 32); /* CB_COLOR0_FMASK_BASE_EXT */
2681 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
2682 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
2683 radeon_emit(cs, cb_dcc_base); /* CB_COLOR0_DCC_BASE */
2684 radeon_emit(cs, cb_dcc_base >> 32); /* CB_COLOR0_DCC_BASE_EXT */
2685
2686 radeon_set_context_reg(cs, R_0287A0_CB_MRT0_EPITCH + i * 4,
2687 S_0287A0_EPITCH(tex->surface.u.gfx9.surf.epitch));
2688 } else {
2689 /* Compute mutable surface parameters (SI-CI-VI). */
2690 const struct legacy_surf_level *level_info =
2691 &tex->surface.u.legacy.level[cb->base.u.tex.level];
2692 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
2693 unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
2694
2695 cb_color_base += level_info->offset >> 8;
2696 if (cb_dcc_base)
2697 cb_dcc_base += level_info->dcc_offset >> 8;
2698
2699 pitch_tile_max = level_info->nblk_x / 8 - 1;
2700 slice_tile_max = level_info->nblk_x *
2701 level_info->nblk_y / 64 - 1;
2702 tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false);
2703
2704 cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
2705 cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
2706 cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
2707
2708 if (tex->fmask.size) {
2709 if (sctx->b.chip_class >= CIK)
2710 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->fmask.pitch_in_pixels / 8 - 1);
2711 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->fmask.tile_mode_index);
2712 cb_color_fmask_slice = S_028C88_TILE_MAX(tex->fmask.slice_tile_max);
2713 } else {
2714 /* This must be set for fast clear to work without FMASK. */
2715 if (sctx->b.chip_class >= CIK)
2716 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
2717 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
2718 cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
2719 }
2720
2721 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
2722 sctx->b.chip_class >= VI ? 14 : 13);
2723 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
2724 radeon_emit(cs, cb_color_pitch); /* CB_COLOR0_PITCH */
2725 radeon_emit(cs, cb_color_slice); /* CB_COLOR0_SLICE */
2726 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
2727 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
2728 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
2729 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
2730 radeon_emit(cs, tex->cmask.base_address_reg); /* CB_COLOR0_CMASK */
2731 radeon_emit(cs, tex->cmask.slice_tile_max); /* CB_COLOR0_CMASK_SLICE */
2732 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
2733 radeon_emit(cs, cb_color_fmask_slice); /* CB_COLOR0_FMASK_SLICE */
2734 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
2735 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
2736
2737 if (sctx->b.chip_class >= VI) /* R_028C94_CB_COLOR0_DCC_BASE */
2738 radeon_emit(cs, cb_dcc_base);
2739 }
2740 }
2741 for (; i < 8 ; i++)
2742 if (sctx->framebuffer.dirty_cbufs & (1 << i))
2743 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
2744
2745 /* ZS buffer. */
2746 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
2747 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
2748 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
2749
2750 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2751 &rtex->resource, RADEON_USAGE_READWRITE,
2752 zb->base.texture->nr_samples > 1 ?
2753 RADEON_PRIO_DEPTH_BUFFER_MSAA :
2754 RADEON_PRIO_DEPTH_BUFFER);
2755
2756 if (zb->db_htile_data_base) {
2757 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2758 rtex->htile_buffer, RADEON_USAGE_READWRITE,
2759 RADEON_PRIO_HTILE);
2760 }
2761
2762 if (sctx->b.chip_class >= GFX9) {
2763 radeon_set_context_reg_seq(cs, R_028014_DB_HTILE_DATA_BASE, 3);
2764 radeon_emit(cs, zb->db_htile_data_base); /* DB_HTILE_DATA_BASE */
2765 radeon_emit(cs, zb->db_htile_data_base >> 32); /* DB_HTILE_DATA_BASE_HI */
2766 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
2767
2768 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 10);
2769 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
2770 S_028038_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
2771 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
2772 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
2773 radeon_emit(cs, zb->db_depth_base >> 32); /* DB_Z_READ_BASE_HI */
2774 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
2775 radeon_emit(cs, zb->db_stencil_base >> 32); /* DB_STENCIL_READ_BASE_HI */
2776 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
2777 radeon_emit(cs, zb->db_depth_base >> 32); /* DB_Z_WRITE_BASE_HI */
2778 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
2779 radeon_emit(cs, zb->db_stencil_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
2780
2781 radeon_set_context_reg_seq(cs, R_028068_DB_Z_INFO2, 2);
2782 radeon_emit(cs, zb->db_z_info2); /* DB_Z_INFO2 */
2783 radeon_emit(cs, zb->db_stencil_info2); /* DB_STENCIL_INFO2 */
2784 } else {
2785 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
2786
2787 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
2788 radeon_emit(cs, zb->db_depth_info); /* DB_DEPTH_INFO */
2789 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
2790 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
2791 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
2792 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
2793 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
2794 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
2795 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
2796 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
2797 radeon_emit(cs, zb->db_depth_slice); /* DB_DEPTH_SLICE */
2798 }
2799
2800 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
2801 radeon_emit(cs, rtex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
2802 radeon_emit(cs, fui(rtex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
2803
2804 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
2805 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
2806 } else if (sctx->framebuffer.dirty_zsbuf) {
2807 if (sctx->b.chip_class >= GFX9)
2808 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 2);
2809 else
2810 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
2811
2812 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
2813 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
2814 }
2815
2816 /* Framebuffer dimensions. */
2817 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2818 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2819 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
2820
2821 if (sctx->b.chip_class >= GFX9) {
2822 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2823 radeon_emit(cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
2824 }
2825
2826 sctx->framebuffer.dirty_cbufs = 0;
2827 sctx->framebuffer.dirty_zsbuf = false;
2828 }
2829
2830 static void si_emit_msaa_sample_locs(struct si_context *sctx,
2831 struct r600_atom *atom)
2832 {
2833 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2834 unsigned nr_samples = sctx->framebuffer.nr_samples;
2835
2836 /* Smoothing (only possible with nr_samples == 1) uses the same
2837 * sample locations as the MSAA it simulates.
2838 */
2839 if (nr_samples <= 1 && sctx->smoothing_enabled)
2840 nr_samples = SI_NUM_SMOOTH_AA_SAMPLES;
2841
2842 /* On Polaris, the small primitive filter uses the sample locations
2843 * even when MSAA is off, so we need to make sure they're set to 0.
2844 */
2845 if (sctx->b.family >= CHIP_POLARIS10)
2846 nr_samples = MAX2(nr_samples, 1);
2847
2848 if (nr_samples >= 1 &&
2849 (nr_samples != sctx->msaa_sample_locs.nr_samples)) {
2850 sctx->msaa_sample_locs.nr_samples = nr_samples;
2851 cayman_emit_msaa_sample_locs(cs, nr_samples);
2852 }
2853
2854 if (sctx->b.family >= CHIP_POLARIS10) {
2855 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
2856 unsigned small_prim_filter_cntl =
2857 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
2858 S_028830_LINE_FILTER_DISABLE(sctx->b.chip_class == VI); /* line bug */
2859
2860 /* The alternative of setting sample locations to 0 would
2861 * require a DB flush to avoid Z errors, see
2862 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
2863 */
2864 if (sctx->framebuffer.nr_samples > 1 && rs && !rs->multisample_enable)
2865 small_prim_filter_cntl &= C_028830_SMALL_PRIM_FILTER_ENABLE;
2866
2867 radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
2868 small_prim_filter_cntl);
2869 }
2870 }
2871
2872 static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom)
2873 {
2874 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2875 unsigned num_tile_pipes = sctx->screen->b.info.num_tile_pipes;
2876 /* 33% faster rendering to linear color buffers */
2877 bool dst_is_linear = sctx->framebuffer.any_dst_linear;
2878 unsigned sc_mode_cntl_1 =
2879 S_028A4C_WALK_SIZE(dst_is_linear) |
2880 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear) |
2881 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
2882 /* always 1: */
2883 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
2884 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
2885 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
2886 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
2887 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
2888 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
2889
2890 cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples,
2891 sctx->ps_iter_samples,
2892 sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0,
2893 sc_mode_cntl_1);
2894
2895 /* GFX9: Flush DFSM when the AA mode changes. */
2896 if (sctx->b.chip_class >= GFX9) {
2897 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2898 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
2899 }
2900 }
2901
2902 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
2903 {
2904 struct si_context *sctx = (struct si_context *)ctx;
2905
2906 if (sctx->ps_iter_samples == min_samples)
2907 return;
2908
2909 sctx->ps_iter_samples = min_samples;
2910 sctx->do_update_shaders = true;
2911
2912 if (sctx->framebuffer.nr_samples > 1)
2913 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2914 }
2915
2916 /*
2917 * Samplers
2918 */
2919
2920 /**
2921 * Build the sampler view descriptor for a buffer texture.
2922 * @param state 256-bit descriptor; only the high 128 bits are filled in
2923 */
2924 void
2925 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
2926 enum pipe_format format,
2927 unsigned offset, unsigned size,
2928 uint32_t *state)
2929 {
2930 const struct util_format_description *desc;
2931 int first_non_void;
2932 unsigned stride;
2933 unsigned num_records;
2934 unsigned num_format, data_format;
2935
2936 desc = util_format_description(format);
2937 first_non_void = util_format_get_first_non_void_channel(format);
2938 stride = desc->block.bits / 8;
2939 num_format = si_translate_buffer_numformat(&screen->b.b, desc, first_non_void);
2940 data_format = si_translate_buffer_dataformat(&screen->b.b, desc, first_non_void);
2941
2942 num_records = size / stride;
2943 num_records = MIN2(num_records, (buf->b.b.width0 - offset) / stride);
2944
2945 if (screen->b.chip_class == VI)
2946 num_records *= stride;
2947
2948 state[4] = 0;
2949 state[5] = S_008F04_STRIDE(stride);
2950 state[6] = num_records;
2951 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2952 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2953 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2954 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2955 S_008F0C_NUM_FORMAT(num_format) |
2956 S_008F0C_DATA_FORMAT(data_format);
2957 }
2958
2959 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle[4])
2960 {
2961 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
2962
2963 if (swizzle[3] == PIPE_SWIZZLE_X) {
2964 /* For the pre-defined border color values (white, opaque
2965 * black, transparent black), the only thing that matters is
2966 * that the alpha channel winds up in the correct place
2967 * (because the RGB channels are all the same) so either of
2968 * these enumerations will work.
2969 */
2970 if (swizzle[2] == PIPE_SWIZZLE_Y)
2971 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
2972 else
2973 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
2974 } else if (swizzle[0] == PIPE_SWIZZLE_X) {
2975 if (swizzle[1] == PIPE_SWIZZLE_Y)
2976 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
2977 else
2978 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
2979 } else if (swizzle[1] == PIPE_SWIZZLE_X) {
2980 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
2981 } else if (swizzle[2] == PIPE_SWIZZLE_X) {
2982 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
2983 }
2984
2985 return bc_swizzle;
2986 }
2987
2988 /**
2989 * Build the sampler view descriptor for a texture.
2990 */
2991 void
2992 si_make_texture_descriptor(struct si_screen *screen,
2993 struct r600_texture *tex,
2994 bool sampler,
2995 enum pipe_texture_target target,
2996 enum pipe_format pipe_format,
2997 const unsigned char state_swizzle[4],
2998 unsigned first_level, unsigned last_level,
2999 unsigned first_layer, unsigned last_layer,
3000 unsigned width, unsigned height, unsigned depth,
3001 uint32_t *state,
3002 uint32_t *fmask_state)
3003 {
3004 struct pipe_resource *res = &tex->resource.b.b;
3005 const struct util_format_description *base_desc, *desc;
3006 unsigned char swizzle[4];
3007 int first_non_void;
3008 unsigned num_format, data_format, type;
3009 uint64_t va;
3010
3011 desc = util_format_description(pipe_format);
3012 base_desc = util_format_description(res->format);
3013
3014 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
3015 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
3016 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
3017 const unsigned char swizzle_wwww[4] = {3, 3, 3, 3};
3018
3019 switch (pipe_format) {
3020 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3021 case PIPE_FORMAT_X32_S8X24_UINT:
3022 case PIPE_FORMAT_X8Z24_UNORM:
3023 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3024 break;
3025 case PIPE_FORMAT_X24S8_UINT:
3026 /*
3027 * X24S8 is implemented as an 8_8_8_8 data format, to
3028 * fix texture gathers. This affects at least
3029 * GL45-CTS.texture_cube_map_array.sampling on VI.
3030 */
3031 util_format_compose_swizzles(swizzle_wwww, state_swizzle, swizzle);
3032 break;
3033 default:
3034 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
3035 }
3036 } else {
3037 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
3038 }
3039
3040 first_non_void = util_format_get_first_non_void_channel(pipe_format);
3041
3042 switch (pipe_format) {
3043 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3044 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3045 break;
3046 default:
3047 if (first_non_void < 0) {
3048 if (util_format_is_compressed(pipe_format)) {
3049 switch (pipe_format) {
3050 case PIPE_FORMAT_DXT1_SRGB:
3051 case PIPE_FORMAT_DXT1_SRGBA:
3052 case PIPE_FORMAT_DXT3_SRGBA:
3053 case PIPE_FORMAT_DXT5_SRGBA:
3054 case PIPE_FORMAT_BPTC_SRGBA:
3055 case PIPE_FORMAT_ETC2_SRGB8:
3056 case PIPE_FORMAT_ETC2_SRGB8A1:
3057 case PIPE_FORMAT_ETC2_SRGBA8:
3058 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3059 break;
3060 case PIPE_FORMAT_RGTC1_SNORM:
3061 case PIPE_FORMAT_LATC1_SNORM:
3062 case PIPE_FORMAT_RGTC2_SNORM:
3063 case PIPE_FORMAT_LATC2_SNORM:
3064 case PIPE_FORMAT_ETC2_R11_SNORM:
3065 case PIPE_FORMAT_ETC2_RG11_SNORM:
3066 /* implies float, so use SNORM/UNORM to determine
3067 whether data is signed or not */
3068 case PIPE_FORMAT_BPTC_RGB_FLOAT:
3069 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3070 break;
3071 default:
3072 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3073 break;
3074 }
3075 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
3076 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3077 } else {
3078 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3079 }
3080 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
3081 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3082 } else {
3083 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3084
3085 switch (desc->channel[first_non_void].type) {
3086 case UTIL_FORMAT_TYPE_FLOAT:
3087 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3088 break;
3089 case UTIL_FORMAT_TYPE_SIGNED:
3090 if (desc->channel[first_non_void].normalized)
3091 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3092 else if (desc->channel[first_non_void].pure_integer)
3093 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
3094 else
3095 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
3096 break;
3097 case UTIL_FORMAT_TYPE_UNSIGNED:
3098 if (desc->channel[first_non_void].normalized)
3099 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3100 else if (desc->channel[first_non_void].pure_integer)
3101 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3102 else
3103 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
3104 }
3105 }
3106 }
3107
3108 data_format = si_translate_texformat(&screen->b.b, pipe_format, desc, first_non_void);
3109 if (data_format == ~0) {
3110 data_format = 0;
3111 }
3112
3113 /* Enable clamping for UNORM depth formats promoted to Z32F. */
3114 if (screen->b.chip_class >= GFX9 &&
3115 util_format_has_depth(desc) &&
3116 num_format == V_008F14_IMG_NUM_FORMAT_FLOAT &&
3117 util_get_depth_format_type(base_desc) != UTIL_FORMAT_TYPE_FLOAT) {
3118 /* NUM_FORMAT=FLOAT and DATA_FORMAT=24_8 means "clamp to [0,1]". */
3119 data_format = V_008F14_IMG_DATA_FORMAT_24_8;
3120 }
3121
3122 if (!sampler &&
3123 (res->target == PIPE_TEXTURE_CUBE ||
3124 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
3125 res->target == PIPE_TEXTURE_3D)) {
3126 /* For the purpose of shader images, treat cube maps and 3D
3127 * textures as 2D arrays. For 3D textures, the address
3128 * calculations for mipmaps are different, so we rely on the
3129 * caller to effectively disable mipmaps.
3130 */
3131 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
3132
3133 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
3134 } else {
3135 type = si_tex_dim(screen, tex, target, res->nr_samples);
3136 }
3137
3138 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
3139 height = 1;
3140 depth = res->array_size;
3141 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
3142 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
3143 if (sampler || res->target != PIPE_TEXTURE_3D)
3144 depth = res->array_size;
3145 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
3146 depth = res->array_size / 6;
3147
3148 state[0] = 0;
3149 state[1] = (S_008F14_DATA_FORMAT_GFX6(data_format) |
3150 S_008F14_NUM_FORMAT_GFX6(num_format));
3151 state[2] = (S_008F18_WIDTH(width - 1) |
3152 S_008F18_HEIGHT(height - 1) |
3153 S_008F18_PERF_MOD(4));
3154 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
3155 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
3156 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
3157 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
3158 S_008F1C_BASE_LEVEL(res->nr_samples > 1 ?
3159 0 : first_level) |
3160 S_008F1C_LAST_LEVEL(res->nr_samples > 1 ?
3161 util_logbase2(res->nr_samples) :
3162 last_level) |
3163 S_008F1C_TYPE(type));
3164 state[4] = 0;
3165 state[5] = S_008F24_BASE_ARRAY(first_layer);
3166 state[6] = 0;
3167 state[7] = 0;
3168
3169 if (screen->b.chip_class >= GFX9) {
3170 unsigned bc_swizzle = gfx9_border_color_swizzle(desc->swizzle);
3171
3172 /* Depth is the the last accessible layer on Gfx9.
3173 * The hw doesn't need to know the total number of layers.
3174 */
3175 if (type == V_008F1C_SQ_RSRC_IMG_3D)
3176 state[4] |= S_008F20_DEPTH(depth - 1);
3177 else
3178 state[4] |= S_008F20_DEPTH(last_layer);
3179
3180 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
3181 state[5] |= S_008F24_MAX_MIP(res->nr_samples > 1 ?
3182 util_logbase2(res->nr_samples) :
3183 tex->resource.b.b.last_level);
3184 } else {
3185 state[3] |= S_008F1C_POW2_PAD(res->last_level > 0);
3186 state[4] |= S_008F20_DEPTH(depth - 1);
3187 state[5] |= S_008F24_LAST_ARRAY(last_layer);
3188 }
3189
3190 if (tex->dcc_offset) {
3191 unsigned swap = r600_translate_colorswap(pipe_format, false);
3192
3193 state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
3194 } else {
3195 /* The last dword is unused by hw. The shader uses it to clear
3196 * bits in the first dword of sampler state.
3197 */
3198 if (screen->b.chip_class <= CIK && res->nr_samples <= 1) {
3199 if (first_level == last_level)
3200 state[7] = C_008F30_MAX_ANISO_RATIO;
3201 else
3202 state[7] = 0xffffffff;
3203 }
3204 }
3205
3206 /* Initialize the sampler view for FMASK. */
3207 if (tex->fmask.size) {
3208 uint32_t data_format, num_format;
3209
3210 va = tex->resource.gpu_address + tex->fmask.offset;
3211
3212 if (screen->b.chip_class >= GFX9) {
3213 data_format = V_008F14_IMG_DATA_FORMAT_FMASK;
3214 switch (res->nr_samples) {
3215 case 2:
3216 num_format = V_008F14_IMG_FMASK_8_2_2;
3217 break;
3218 case 4:
3219 num_format = V_008F14_IMG_FMASK_8_4_4;
3220 break;
3221 case 8:
3222 num_format = V_008F14_IMG_FMASK_32_8_8;
3223 break;
3224 default:
3225 assert(0);
3226 }
3227 } else {
3228 switch (res->nr_samples) {
3229 case 2:
3230 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
3231 break;
3232 case 4:
3233 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
3234 break;
3235 case 8:
3236 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
3237 break;
3238 default:
3239 assert(0);
3240 }
3241 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3242 }
3243
3244 fmask_state[0] = va >> 8;
3245 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
3246 S_008F14_DATA_FORMAT_GFX6(data_format) |
3247 S_008F14_NUM_FORMAT_GFX6(num_format);
3248 fmask_state[2] = S_008F18_WIDTH(width - 1) |
3249 S_008F18_HEIGHT(height - 1);
3250 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
3251 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
3252 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
3253 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
3254 S_008F1C_TYPE(si_tex_dim(screen, tex, target, 0));
3255 fmask_state[4] = 0;
3256 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
3257 fmask_state[6] = 0;
3258 fmask_state[7] = 0;
3259
3260 if (screen->b.chip_class >= GFX9) {
3261 fmask_state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode);
3262 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
3263 S_008F20_PITCH_GFX9(tex->surface.u.gfx9.fmask.epitch);
3264 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned) |
3265 S_008F24_META_RB_ALIGNED(tex->surface.u.gfx9.cmask.rb_aligned);
3266 } else {
3267 fmask_state[3] |= S_008F1C_TILING_INDEX(tex->fmask.tile_mode_index);
3268 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
3269 S_008F20_PITCH_GFX6(tex->fmask.pitch_in_pixels - 1);
3270 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
3271 }
3272 }
3273 }
3274
3275 /**
3276 * Create a sampler view.
3277 *
3278 * @param ctx context
3279 * @param texture texture
3280 * @param state sampler view template
3281 * @param width0 width0 override (for compressed textures as int)
3282 * @param height0 height0 override (for compressed textures as int)
3283 * @param force_level set the base address to the level (for compressed textures)
3284 */
3285 struct pipe_sampler_view *
3286 si_create_sampler_view_custom(struct pipe_context *ctx,
3287 struct pipe_resource *texture,
3288 const struct pipe_sampler_view *state,
3289 unsigned width0, unsigned height0,
3290 unsigned force_level)
3291 {
3292 struct si_context *sctx = (struct si_context*)ctx;
3293 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
3294 struct r600_texture *tmp = (struct r600_texture*)texture;
3295 unsigned base_level, first_level, last_level;
3296 unsigned char state_swizzle[4];
3297 unsigned height, depth, width;
3298 unsigned last_layer = state->u.tex.last_layer;
3299 enum pipe_format pipe_format;
3300 const struct legacy_surf_level *surflevel;
3301
3302 if (!view)
3303 return NULL;
3304
3305 /* initialize base object */
3306 view->base = *state;
3307 view->base.texture = NULL;
3308 view->base.reference.count = 1;
3309 view->base.context = ctx;
3310
3311 assert(texture);
3312 pipe_resource_reference(&view->base.texture, texture);
3313
3314 if (state->format == PIPE_FORMAT_X24S8_UINT ||
3315 state->format == PIPE_FORMAT_S8X24_UINT ||
3316 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
3317 state->format == PIPE_FORMAT_S8_UINT)
3318 view->is_stencil_sampler = true;
3319
3320 /* Buffer resource. */
3321 if (texture->target == PIPE_BUFFER) {
3322 si_make_buffer_descriptor(sctx->screen,
3323 (struct r600_resource *)texture,
3324 state->format,
3325 state->u.buf.offset,
3326 state->u.buf.size,
3327 view->state);
3328 return &view->base;
3329 }
3330
3331 state_swizzle[0] = state->swizzle_r;
3332 state_swizzle[1] = state->swizzle_g;
3333 state_swizzle[2] = state->swizzle_b;
3334 state_swizzle[3] = state->swizzle_a;
3335
3336 base_level = 0;
3337 first_level = state->u.tex.first_level;
3338 last_level = state->u.tex.last_level;
3339 width = width0;
3340 height = height0;
3341 depth = texture->depth0;
3342
3343 if (sctx->b.chip_class <= VI && force_level) {
3344 assert(force_level == first_level &&
3345 force_level == last_level);
3346 base_level = force_level;
3347 first_level = 0;
3348 last_level = 0;
3349 width = u_minify(width, force_level);
3350 height = u_minify(height, force_level);
3351 depth = u_minify(depth, force_level);
3352 }
3353
3354 /* This is not needed if state trackers set last_layer correctly. */
3355 if (state->target == PIPE_TEXTURE_1D ||
3356 state->target == PIPE_TEXTURE_2D ||
3357 state->target == PIPE_TEXTURE_RECT ||
3358 state->target == PIPE_TEXTURE_CUBE)
3359 last_layer = state->u.tex.first_layer;
3360
3361 /* Texturing with separate depth and stencil. */
3362 pipe_format = state->format;
3363
3364 /* Depth/stencil texturing sometimes needs separate texture. */
3365 if (tmp->is_depth && !r600_can_sample_zs(tmp, view->is_stencil_sampler)) {
3366 if (!tmp->flushed_depth_texture &&
3367 !r600_init_flushed_depth_texture(ctx, texture, NULL)) {
3368 pipe_resource_reference(&view->base.texture, NULL);
3369 FREE(view);
3370 return NULL;
3371 }
3372
3373 assert(tmp->flushed_depth_texture);
3374
3375 /* Override format for the case where the flushed texture
3376 * contains only Z or only S.
3377 */
3378 if (tmp->flushed_depth_texture->resource.b.b.format != tmp->resource.b.b.format)
3379 pipe_format = tmp->flushed_depth_texture->resource.b.b.format;
3380
3381 tmp = tmp->flushed_depth_texture;
3382 }
3383
3384 surflevel = tmp->surface.u.legacy.level;
3385
3386 if (tmp->db_compatible) {
3387 if (!view->is_stencil_sampler)
3388 pipe_format = tmp->db_render_format;
3389
3390 switch (pipe_format) {
3391 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
3392 pipe_format = PIPE_FORMAT_Z32_FLOAT;
3393 break;
3394 case PIPE_FORMAT_X8Z24_UNORM:
3395 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3396 /* Z24 is always stored like this for DB
3397 * compatibility.
3398 */
3399 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
3400 break;
3401 case PIPE_FORMAT_X24S8_UINT:
3402 case PIPE_FORMAT_S8X24_UINT:
3403 case PIPE_FORMAT_X32_S8X24_UINT:
3404 pipe_format = PIPE_FORMAT_S8_UINT;
3405 surflevel = tmp->surface.u.legacy.stencil_level;
3406 break;
3407 default:;
3408 }
3409 }
3410
3411 vi_disable_dcc_if_incompatible_format(&sctx->b, texture,
3412 state->u.tex.first_level,
3413 state->format);
3414
3415 si_make_texture_descriptor(sctx->screen, tmp, true,
3416 state->target, pipe_format, state_swizzle,
3417 first_level, last_level,
3418 state->u.tex.first_layer, last_layer,
3419 width, height, depth,
3420 view->state, view->fmask_state);
3421
3422 view->base_level_info = &surflevel[base_level];
3423 view->base_level = base_level;
3424 view->block_width = util_format_get_blockwidth(pipe_format);
3425 return &view->base;
3426 }
3427
3428 static struct pipe_sampler_view *
3429 si_create_sampler_view(struct pipe_context *ctx,
3430 struct pipe_resource *texture,
3431 const struct pipe_sampler_view *state)
3432 {
3433 return si_create_sampler_view_custom(ctx, texture, state,
3434 texture ? texture->width0 : 0,
3435 texture ? texture->height0 : 0, 0);
3436 }
3437
3438 static void si_sampler_view_destroy(struct pipe_context *ctx,
3439 struct pipe_sampler_view *state)
3440 {
3441 struct si_sampler_view *view = (struct si_sampler_view *)state;
3442
3443 pipe_resource_reference(&state->texture, NULL);
3444 FREE(view);
3445 }
3446
3447 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
3448 {
3449 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
3450 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
3451 (linear_filter &&
3452 (wrap == PIPE_TEX_WRAP_CLAMP ||
3453 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
3454 }
3455
3456 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
3457 {
3458 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
3459 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
3460
3461 return (state->border_color.ui[0] || state->border_color.ui[1] ||
3462 state->border_color.ui[2] || state->border_color.ui[3]) &&
3463 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
3464 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
3465 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
3466 }
3467
3468 static void *si_create_sampler_state(struct pipe_context *ctx,
3469 const struct pipe_sampler_state *state)
3470 {
3471 struct si_context *sctx = (struct si_context *)ctx;
3472 struct r600_common_screen *rscreen = sctx->b.screen;
3473 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
3474 unsigned border_color_type, border_color_index = 0;
3475 unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
3476 : state->max_anisotropy;
3477 unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso);
3478
3479 if (!rstate) {
3480 return NULL;
3481 }
3482
3483 if (!sampler_state_needs_border_color(state))
3484 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3485 else if (state->border_color.f[0] == 0 &&
3486 state->border_color.f[1] == 0 &&
3487 state->border_color.f[2] == 0 &&
3488 state->border_color.f[3] == 0)
3489 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3490 else if (state->border_color.f[0] == 0 &&
3491 state->border_color.f[1] == 0 &&
3492 state->border_color.f[2] == 0 &&
3493 state->border_color.f[3] == 1)
3494 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3495 else if (state->border_color.f[0] == 1 &&
3496 state->border_color.f[1] == 1 &&
3497 state->border_color.f[2] == 1 &&
3498 state->border_color.f[3] == 1)
3499 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3500 else {
3501 int i;
3502
3503 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
3504
3505 /* Check if the border has been uploaded already. */
3506 for (i = 0; i < sctx->border_color_count; i++)
3507 if (memcmp(&sctx->border_color_table[i], &state->border_color,
3508 sizeof(state->border_color)) == 0)
3509 break;
3510
3511 if (i >= SI_MAX_BORDER_COLORS) {
3512 /* Getting 4096 unique border colors is very unlikely. */
3513 fprintf(stderr, "radeonsi: The border color table is full. "
3514 "Any new border colors will be just black. "
3515 "Please file a bug.\n");
3516 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3517 } else {
3518 if (i == sctx->border_color_count) {
3519 /* Upload a new border color. */
3520 memcpy(&sctx->border_color_table[i], &state->border_color,
3521 sizeof(state->border_color));
3522 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
3523 &state->border_color,
3524 sizeof(state->border_color));
3525 sctx->border_color_count++;
3526 }
3527
3528 border_color_index = i;
3529 }
3530 }
3531
3532 #ifdef DEBUG
3533 rstate->magic = SI_SAMPLER_STATE_MAGIC;
3534 #endif
3535 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
3536 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
3537 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
3538 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3539 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
3540 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
3541 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
3542 S_008F30_ANISO_BIAS(max_aniso_ratio) |
3543 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
3544 S_008F30_COMPAT_MODE(sctx->b.chip_class >= VI));
3545 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
3546 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)) |
3547 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
3548 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
3549 S_008F38_XY_MAG_FILTER(eg_tex_filter(state->mag_img_filter, max_aniso)) |
3550 S_008F38_XY_MIN_FILTER(eg_tex_filter(state->min_img_filter, max_aniso)) |
3551 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
3552 S_008F38_MIP_POINT_PRECLAMP(1) |
3553 S_008F38_DISABLE_LSB_CEIL(sctx->b.chip_class <= VI) |
3554 S_008F38_FILTER_PREC_FIX(1) |
3555 S_008F38_ANISO_OVERRIDE(sctx->b.chip_class >= VI));
3556 rstate->val[3] = S_008F3C_BORDER_COLOR_PTR(border_color_index) |
3557 S_008F3C_BORDER_COLOR_TYPE(border_color_type);
3558 return rstate;
3559 }
3560
3561 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
3562 {
3563 struct si_context *sctx = (struct si_context *)ctx;
3564
3565 if (sctx->sample_mask.sample_mask == (uint16_t)sample_mask)
3566 return;
3567
3568 sctx->sample_mask.sample_mask = sample_mask;
3569 si_mark_atom_dirty(sctx, &sctx->sample_mask.atom);
3570 }
3571
3572 static void si_emit_sample_mask(struct si_context *sctx, struct r600_atom *atom)
3573 {
3574 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
3575 unsigned mask = sctx->sample_mask.sample_mask;
3576
3577 /* Needed for line and polygon smoothing as well as for the Polaris
3578 * small primitive filter. We expect the state tracker to take care of
3579 * this for us.
3580 */
3581 assert(mask == 0xffff || sctx->framebuffer.nr_samples > 1 ||
3582 (mask & 1 && sctx->blitter->running));
3583
3584 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3585 radeon_emit(cs, mask | (mask << 16));
3586 radeon_emit(cs, mask | (mask << 16));
3587 }
3588
3589 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
3590 {
3591 #ifdef DEBUG
3592 struct si_sampler_state *s = state;
3593
3594 assert(s->magic == SI_SAMPLER_STATE_MAGIC);
3595 s->magic = 0;
3596 #endif
3597 free(state);
3598 }
3599
3600 /*
3601 * Vertex elements & buffers
3602 */
3603
3604 static void *si_create_vertex_elements(struct pipe_context *ctx,
3605 unsigned count,
3606 const struct pipe_vertex_element *elements)
3607 {
3608 struct si_screen *sscreen = (struct si_screen*)ctx->screen;
3609 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
3610 bool used[SI_NUM_VERTEX_BUFFERS] = {};
3611 int i;
3612
3613 assert(count <= SI_MAX_ATTRIBS);
3614 if (!v)
3615 return NULL;
3616
3617 v->count = count;
3618 v->desc_list_byte_size = align(count * 16, SI_CPDMA_ALIGNMENT);
3619
3620 for (i = 0; i < count; ++i) {
3621 const struct util_format_description *desc;
3622 const struct util_format_channel_description *channel;
3623 unsigned data_format, num_format;
3624 int first_non_void;
3625 unsigned vbo_index = elements[i].vertex_buffer_index;
3626 unsigned char swizzle[4];
3627
3628 if (vbo_index >= SI_NUM_VERTEX_BUFFERS) {
3629 FREE(v);
3630 return NULL;
3631 }
3632
3633 if (!used[vbo_index]) {
3634 v->first_vb_use_mask |= 1 << i;
3635 used[vbo_index] = true;
3636 }
3637
3638 desc = util_format_description(elements[i].src_format);
3639 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
3640 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
3641 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
3642 channel = first_non_void >= 0 ? &desc->channel[first_non_void] : NULL;
3643 memcpy(swizzle, desc->swizzle, sizeof(swizzle));
3644
3645 v->format_size[i] = desc->block.bits / 8;
3646
3647 /* The hardware always treats the 2-bit alpha channel as
3648 * unsigned, so a shader workaround is needed. The affected
3649 * chips are VI and older except Stoney (GFX8.1).
3650 */
3651 if (data_format == V_008F0C_BUF_DATA_FORMAT_2_10_10_10 &&
3652 sscreen->b.chip_class <= VI &&
3653 sscreen->b.family != CHIP_STONEY) {
3654 if (num_format == V_008F0C_BUF_NUM_FORMAT_SNORM) {
3655 v->fix_fetch[i] = SI_FIX_FETCH_A2_SNORM;
3656 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SSCALED) {
3657 v->fix_fetch[i] = SI_FIX_FETCH_A2_SSCALED;
3658 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SINT) {
3659 /* This isn't actually used in OpenGL. */
3660 v->fix_fetch[i] = SI_FIX_FETCH_A2_SINT;
3661 }
3662 } else if (channel && channel->type == UTIL_FORMAT_TYPE_FIXED) {
3663 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
3664 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_FIXED;
3665 else
3666 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_FIXED;
3667 } else if (channel && channel->size == 32 && !channel->pure_integer) {
3668 if (channel->type == UTIL_FORMAT_TYPE_SIGNED) {
3669 if (channel->normalized) {
3670 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
3671 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_SNORM;
3672 else
3673 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SNORM;
3674 } else {
3675 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SSCALED;
3676 }
3677 } else if (channel->type == UTIL_FORMAT_TYPE_UNSIGNED) {
3678 if (channel->normalized) {
3679 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
3680 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_UNORM;
3681 else
3682 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_UNORM;
3683 } else {
3684 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_USCALED;
3685 }
3686 }
3687 } else if (channel && channel->size == 64 &&
3688 channel->type == UTIL_FORMAT_TYPE_FLOAT) {
3689 switch (desc->nr_channels) {
3690 case 1:
3691 case 2:
3692 v->fix_fetch[i] = SI_FIX_FETCH_RG_64_FLOAT;
3693 swizzle[0] = PIPE_SWIZZLE_X;
3694 swizzle[1] = PIPE_SWIZZLE_Y;
3695 swizzle[2] = desc->nr_channels == 2 ? PIPE_SWIZZLE_Z : PIPE_SWIZZLE_0;
3696 swizzle[3] = desc->nr_channels == 2 ? PIPE_SWIZZLE_W : PIPE_SWIZZLE_0;
3697 break;
3698 case 3:
3699 v->fix_fetch[i] = SI_FIX_FETCH_RGB_64_FLOAT;
3700 swizzle[0] = PIPE_SWIZZLE_X; /* 3 loads */
3701 swizzle[1] = PIPE_SWIZZLE_Y;
3702 swizzle[2] = PIPE_SWIZZLE_0;
3703 swizzle[3] = PIPE_SWIZZLE_0;
3704 break;
3705 case 4:
3706 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_64_FLOAT;
3707 swizzle[0] = PIPE_SWIZZLE_X; /* 2 loads */
3708 swizzle[1] = PIPE_SWIZZLE_Y;
3709 swizzle[2] = PIPE_SWIZZLE_Z;
3710 swizzle[3] = PIPE_SWIZZLE_W;
3711 break;
3712 default:
3713 assert(0);
3714 }
3715 } else if (channel && desc->nr_channels == 3) {
3716 assert(desc->swizzle[0] == PIPE_SWIZZLE_X);
3717
3718 if (channel->size == 8) {
3719 if (channel->pure_integer)
3720 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8_INT;
3721 else
3722 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8;
3723 } else if (channel->size == 16) {
3724 if (channel->pure_integer)
3725 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16_INT;
3726 else
3727 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16;
3728 }
3729 }
3730
3731 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
3732 S_008F0C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
3733 S_008F0C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
3734 S_008F0C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
3735 S_008F0C_NUM_FORMAT(num_format) |
3736 S_008F0C_DATA_FORMAT(data_format);
3737 }
3738 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
3739
3740 return v;
3741 }
3742
3743 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
3744 {
3745 struct si_context *sctx = (struct si_context *)ctx;
3746 struct si_vertex_element *v = (struct si_vertex_element*)state;
3747
3748 sctx->vertex_elements = v;
3749 sctx->vertex_buffers_dirty = true;
3750 sctx->do_update_shaders = true;
3751 }
3752
3753 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
3754 {
3755 struct si_context *sctx = (struct si_context *)ctx;
3756
3757 if (sctx->vertex_elements == state)
3758 sctx->vertex_elements = NULL;
3759 FREE(state);
3760 }
3761
3762 static void si_set_vertex_buffers(struct pipe_context *ctx,
3763 unsigned start_slot, unsigned count,
3764 const struct pipe_vertex_buffer *buffers)
3765 {
3766 struct si_context *sctx = (struct si_context *)ctx;
3767 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
3768 int i;
3769
3770 assert(start_slot + count <= ARRAY_SIZE(sctx->vertex_buffer));
3771
3772 if (buffers) {
3773 for (i = 0; i < count; i++) {
3774 const struct pipe_vertex_buffer *src = buffers + i;
3775 struct pipe_vertex_buffer *dsti = dst + i;
3776
3777 if (unlikely(src->user_buffer)) {
3778 /* Zero-stride attribs only. */
3779 assert(src->stride == 0);
3780
3781 /* Assume that the user_buffer comes from
3782 * gl_current_attrib, which implies it has
3783 * 4 * 8 bytes (for dvec4 attributes).
3784 *
3785 * Use const_uploader to upload into VRAM directly.
3786 */
3787 u_upload_data(sctx->b.b.const_uploader, 0, 32, 32,
3788 src->user_buffer,
3789 &dsti->buffer_offset,
3790 &dsti->buffer);
3791 dsti->stride = 0;
3792 } else {
3793 struct pipe_resource *buf = src->buffer;
3794
3795 pipe_resource_reference(&dsti->buffer, buf);
3796 dsti->buffer_offset = src->buffer_offset;
3797 dsti->stride = src->stride;
3798 r600_context_add_resource_size(ctx, buf);
3799 if (buf)
3800 r600_resource(buf)->bind_history |= PIPE_BIND_VERTEX_BUFFER;
3801 }
3802 }
3803 } else {
3804 for (i = 0; i < count; i++) {
3805 pipe_resource_reference(&dst[i].buffer, NULL);
3806 }
3807 }
3808 sctx->vertex_buffers_dirty = true;
3809 }
3810
3811 static void si_set_index_buffer(struct pipe_context *ctx,
3812 const struct pipe_index_buffer *ib)
3813 {
3814 struct si_context *sctx = (struct si_context *)ctx;
3815
3816 if (ib) {
3817 struct pipe_resource *buf = ib->buffer;
3818
3819 pipe_resource_reference(&sctx->index_buffer.buffer, buf);
3820 memcpy(&sctx->index_buffer, ib, sizeof(*ib));
3821 r600_context_add_resource_size(ctx, buf);
3822 if (buf)
3823 r600_resource(buf)->bind_history |= PIPE_BIND_INDEX_BUFFER;
3824 } else {
3825 pipe_resource_reference(&sctx->index_buffer.buffer, NULL);
3826 }
3827 }
3828
3829 /*
3830 * Misc
3831 */
3832
3833 static void si_set_tess_state(struct pipe_context *ctx,
3834 const float default_outer_level[4],
3835 const float default_inner_level[2])
3836 {
3837 struct si_context *sctx = (struct si_context *)ctx;
3838 struct pipe_constant_buffer cb;
3839 float array[8];
3840
3841 memcpy(array, default_outer_level, sizeof(float) * 4);
3842 memcpy(array+4, default_inner_level, sizeof(float) * 2);
3843
3844 cb.buffer = NULL;
3845 cb.user_buffer = NULL;
3846 cb.buffer_size = sizeof(array);
3847
3848 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
3849 (void*)array, sizeof(array),
3850 &cb.buffer_offset);
3851
3852 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
3853 pipe_resource_reference(&cb.buffer, NULL);
3854 }
3855
3856 static void si_texture_barrier(struct pipe_context *ctx, unsigned flags)
3857 {
3858 struct si_context *sctx = (struct si_context *)ctx;
3859
3860 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
3861 SI_CONTEXT_INV_GLOBAL_L2 |
3862 SI_CONTEXT_FLUSH_AND_INV_CB;
3863 sctx->framebuffer.do_update_surf_dirtiness = true;
3864 }
3865
3866 /* This only ensures coherency for shader image/buffer stores. */
3867 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
3868 {
3869 struct si_context *sctx = (struct si_context *)ctx;
3870
3871 /* Subsequent commands must wait for all shader invocations to
3872 * complete. */
3873 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
3874 SI_CONTEXT_CS_PARTIAL_FLUSH;
3875
3876 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
3877 sctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 |
3878 SI_CONTEXT_INV_VMEM_L1;
3879
3880 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
3881 PIPE_BARRIER_SHADER_BUFFER |
3882 PIPE_BARRIER_TEXTURE |
3883 PIPE_BARRIER_IMAGE |
3884 PIPE_BARRIER_STREAMOUT_BUFFER |
3885 PIPE_BARRIER_GLOBAL_BUFFER)) {
3886 /* As far as I can tell, L1 contents are written back to L2
3887 * automatically at end of shader, but the contents of other
3888 * L1 caches might still be stale. */
3889 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
3890 }
3891
3892 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
3893 /* Indices are read through TC L2 since VI.
3894 * L1 isn't used.
3895 */
3896 if (sctx->screen->b.chip_class <= CIK)
3897 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
3898 }
3899
3900 if (flags & PIPE_BARRIER_FRAMEBUFFER)
3901 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_CB |
3902 SI_CONTEXT_FLUSH_AND_INV_DB;
3903
3904 if (flags & (PIPE_BARRIER_FRAMEBUFFER |
3905 PIPE_BARRIER_INDIRECT_BUFFER))
3906 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
3907 }
3908
3909 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
3910 {
3911 struct pipe_blend_state blend;
3912
3913 memset(&blend, 0, sizeof(blend));
3914 blend.independent_blend_enable = true;
3915 blend.rt[0].colormask = 0xf;
3916 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
3917 }
3918
3919 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
3920 bool include_draw_vbo)
3921 {
3922 si_need_cs_space((struct si_context*)ctx);
3923 }
3924
3925 static void si_init_config(struct si_context *sctx);
3926
3927 void si_init_state_functions(struct si_context *sctx)
3928 {
3929 si_init_external_atom(sctx, &sctx->b.render_cond_atom, &sctx->atoms.s.render_cond);
3930 si_init_external_atom(sctx, &sctx->b.streamout.begin_atom, &sctx->atoms.s.streamout_begin);
3931 si_init_external_atom(sctx, &sctx->b.streamout.enable_atom, &sctx->atoms.s.streamout_enable);
3932 si_init_external_atom(sctx, &sctx->b.scissors.atom, &sctx->atoms.s.scissors);
3933 si_init_external_atom(sctx, &sctx->b.viewports.atom, &sctx->atoms.s.viewports);
3934
3935 si_init_atom(sctx, &sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state);
3936 si_init_atom(sctx, &sctx->msaa_sample_locs.atom, &sctx->atoms.s.msaa_sample_locs, si_emit_msaa_sample_locs);
3937 si_init_atom(sctx, &sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state);
3938 si_init_atom(sctx, &sctx->msaa_config, &sctx->atoms.s.msaa_config, si_emit_msaa_config);
3939 si_init_atom(sctx, &sctx->sample_mask.atom, &sctx->atoms.s.sample_mask, si_emit_sample_mask);
3940 si_init_atom(sctx, &sctx->cb_render_state, &sctx->atoms.s.cb_render_state, si_emit_cb_render_state);
3941 si_init_atom(sctx, &sctx->blend_color.atom, &sctx->atoms.s.blend_color, si_emit_blend_color);
3942 si_init_atom(sctx, &sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs);
3943 si_init_atom(sctx, &sctx->clip_state.atom, &sctx->atoms.s.clip_state, si_emit_clip_state);
3944 si_init_atom(sctx, &sctx->stencil_ref.atom, &sctx->atoms.s.stencil_ref, si_emit_stencil_ref);
3945
3946 sctx->b.b.create_blend_state = si_create_blend_state;
3947 sctx->b.b.bind_blend_state = si_bind_blend_state;
3948 sctx->b.b.delete_blend_state = si_delete_blend_state;
3949 sctx->b.b.set_blend_color = si_set_blend_color;
3950
3951 sctx->b.b.create_rasterizer_state = si_create_rs_state;
3952 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
3953 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
3954
3955 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
3956 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
3957 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
3958
3959 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
3960 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
3961 sctx->custom_blend_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
3962 sctx->custom_blend_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
3963 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
3964
3965 sctx->b.b.set_clip_state = si_set_clip_state;
3966 sctx->b.b.set_stencil_ref = si_set_stencil_ref;
3967
3968 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
3969 sctx->b.b.get_sample_position = cayman_get_sample_position;
3970
3971 sctx->b.b.create_sampler_state = si_create_sampler_state;
3972 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
3973
3974 sctx->b.b.create_sampler_view = si_create_sampler_view;
3975 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
3976
3977 sctx->b.b.set_sample_mask = si_set_sample_mask;
3978
3979 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
3980 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
3981 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
3982 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
3983 sctx->b.b.set_index_buffer = si_set_index_buffer;
3984
3985 sctx->b.b.texture_barrier = si_texture_barrier;
3986 sctx->b.b.memory_barrier = si_memory_barrier;
3987 sctx->b.b.set_min_samples = si_set_min_samples;
3988 sctx->b.b.set_tess_state = si_set_tess_state;
3989
3990 sctx->b.b.set_active_query_state = si_set_active_query_state;
3991 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
3992 sctx->b.save_qbo_state = si_save_qbo_state;
3993 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
3994
3995 sctx->b.b.draw_vbo = si_draw_vbo;
3996
3997 si_init_config(sctx);
3998 }
3999
4000 static uint32_t si_get_bo_metadata_word1(struct r600_common_screen *rscreen)
4001 {
4002 return (ATI_VENDOR_ID << 16) | rscreen->info.pci_id;
4003 }
4004
4005 static void si_query_opaque_metadata(struct r600_common_screen *rscreen,
4006 struct r600_texture *rtex,
4007 struct radeon_bo_metadata *md)
4008 {
4009 struct si_screen *sscreen = (struct si_screen*)rscreen;
4010 struct pipe_resource *res = &rtex->resource.b.b;
4011 static const unsigned char swizzle[] = {
4012 PIPE_SWIZZLE_X,
4013 PIPE_SWIZZLE_Y,
4014 PIPE_SWIZZLE_Z,
4015 PIPE_SWIZZLE_W
4016 };
4017 uint32_t desc[8], i;
4018 bool is_array = util_resource_is_array_texture(res);
4019
4020 /* DRM 2.x.x doesn't support this. */
4021 if (rscreen->info.drm_major != 3)
4022 return;
4023
4024 assert(rtex->dcc_separate_buffer == NULL);
4025 assert(rtex->fmask.size == 0);
4026
4027 /* Metadata image format format version 1:
4028 * [0] = 1 (metadata format identifier)
4029 * [1] = (VENDOR_ID << 16) | PCI_ID
4030 * [2:9] = image descriptor for the whole resource
4031 * [2] is always 0, because the base address is cleared
4032 * [9] is the DCC offset bits [39:8] from the beginning of
4033 * the buffer
4034 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
4035 */
4036
4037 md->metadata[0] = 1; /* metadata image format version 1 */
4038
4039 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
4040 md->metadata[1] = si_get_bo_metadata_word1(rscreen);
4041
4042 si_make_texture_descriptor(sscreen, rtex, true,
4043 res->target, res->format,
4044 swizzle, 0, res->last_level, 0,
4045 is_array ? res->array_size - 1 : 0,
4046 res->width0, res->height0, res->depth0,
4047 desc, NULL);
4048
4049 si_set_mutable_tex_desc_fields(sscreen, rtex, &rtex->surface.u.legacy.level[0],
4050 0, 0, rtex->surface.blk_w, false, desc);
4051
4052 /* Clear the base address and set the relative DCC offset. */
4053 desc[0] = 0;
4054 desc[1] &= C_008F14_BASE_ADDRESS_HI;
4055 desc[7] = rtex->dcc_offset >> 8;
4056
4057 /* Dwords [2:9] contain the image descriptor. */
4058 memcpy(&md->metadata[2], desc, sizeof(desc));
4059 md->size_metadata = 10 * 4;
4060
4061 /* Dwords [10:..] contain the mipmap level offsets. */
4062 if (rscreen->chip_class <= VI) {
4063 for (i = 0; i <= res->last_level; i++)
4064 md->metadata[10+i] = rtex->surface.u.legacy.level[i].offset >> 8;
4065
4066 md->size_metadata += (1 + res->last_level) * 4;
4067 }
4068 }
4069
4070 static void si_apply_opaque_metadata(struct r600_common_screen *rscreen,
4071 struct r600_texture *rtex,
4072 struct radeon_bo_metadata *md)
4073 {
4074 uint32_t *desc = &md->metadata[2];
4075
4076 if (rscreen->chip_class < VI)
4077 return;
4078
4079 /* Return if DCC is enabled. The texture should be set up with it
4080 * already.
4081 */
4082 if (md->size_metadata >= 11 * 4 &&
4083 md->metadata[0] != 0 &&
4084 md->metadata[1] == si_get_bo_metadata_word1(rscreen) &&
4085 G_008F28_COMPRESSION_EN(desc[6])) {
4086 assert(rtex->dcc_offset == ((uint64_t)desc[7] << 8));
4087 return;
4088 }
4089
4090 /* Disable DCC. These are always set by texture_from_handle and must
4091 * be cleared here.
4092 */
4093 rtex->dcc_offset = 0;
4094 }
4095
4096 void si_init_screen_state_functions(struct si_screen *sscreen)
4097 {
4098 sscreen->b.b.is_format_supported = si_is_format_supported;
4099 sscreen->b.query_opaque_metadata = si_query_opaque_metadata;
4100 sscreen->b.apply_opaque_metadata = si_apply_opaque_metadata;
4101 }
4102
4103 static void
4104 si_write_harvested_raster_configs(struct si_context *sctx,
4105 struct si_pm4_state *pm4,
4106 unsigned raster_config,
4107 unsigned raster_config_1)
4108 {
4109 unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1);
4110 unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1);
4111 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
4112 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
4113 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
4114 unsigned rb_per_se = num_rb / num_se;
4115 unsigned se_mask[4];
4116 unsigned se;
4117
4118 se_mask[0] = ((1 << rb_per_se) - 1);
4119 se_mask[1] = (se_mask[0] << rb_per_se);
4120 se_mask[2] = (se_mask[1] << rb_per_se);
4121 se_mask[3] = (se_mask[2] << rb_per_se);
4122
4123 se_mask[0] &= rb_mask;
4124 se_mask[1] &= rb_mask;
4125 se_mask[2] &= rb_mask;
4126 se_mask[3] &= rb_mask;
4127
4128 assert(num_se == 1 || num_se == 2 || num_se == 4);
4129 assert(sh_per_se == 1 || sh_per_se == 2);
4130 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
4131
4132 /* XXX: I can't figure out what the *_XSEL and *_YSEL
4133 * fields are for, so I'm leaving them as their default
4134 * values. */
4135
4136 for (se = 0; se < num_se; se++) {
4137 unsigned raster_config_se = raster_config;
4138 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
4139 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
4140 int idx = (se / 2) * 2;
4141
4142 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
4143 raster_config_se &= C_028350_SE_MAP;
4144
4145 if (!se_mask[idx]) {
4146 raster_config_se |=
4147 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
4148 } else {
4149 raster_config_se |=
4150 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
4151 }
4152 }
4153
4154 pkr0_mask &= rb_mask;
4155 pkr1_mask &= rb_mask;
4156 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
4157 raster_config_se &= C_028350_PKR_MAP;
4158
4159 if (!pkr0_mask) {
4160 raster_config_se |=
4161 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
4162 } else {
4163 raster_config_se |=
4164 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
4165 }
4166 }
4167
4168 if (rb_per_se >= 2) {
4169 unsigned rb0_mask = 1 << (se * rb_per_se);
4170 unsigned rb1_mask = rb0_mask << 1;
4171
4172 rb0_mask &= rb_mask;
4173 rb1_mask &= rb_mask;
4174 if (!rb0_mask || !rb1_mask) {
4175 raster_config_se &= C_028350_RB_MAP_PKR0;
4176
4177 if (!rb0_mask) {
4178 raster_config_se |=
4179 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
4180 } else {
4181 raster_config_se |=
4182 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
4183 }
4184 }
4185
4186 if (rb_per_se > 2) {
4187 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
4188 rb1_mask = rb0_mask << 1;
4189 rb0_mask &= rb_mask;
4190 rb1_mask &= rb_mask;
4191 if (!rb0_mask || !rb1_mask) {
4192 raster_config_se &= C_028350_RB_MAP_PKR1;
4193
4194 if (!rb0_mask) {
4195 raster_config_se |=
4196 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
4197 } else {
4198 raster_config_se |=
4199 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
4200 }
4201 }
4202 }
4203 }
4204
4205 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
4206 if (sctx->b.chip_class < CIK)
4207 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
4208 SE_INDEX(se) | SH_BROADCAST_WRITES |
4209 INSTANCE_BROADCAST_WRITES);
4210 else
4211 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
4212 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
4213 S_030800_INSTANCE_BROADCAST_WRITES(1));
4214 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
4215 }
4216
4217 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
4218 if (sctx->b.chip_class < CIK)
4219 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
4220 SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
4221 INSTANCE_BROADCAST_WRITES);
4222 else {
4223 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
4224 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
4225 S_030800_INSTANCE_BROADCAST_WRITES(1));
4226
4227 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
4228 (!se_mask[2] && !se_mask[3]))) {
4229 raster_config_1 &= C_028354_SE_PAIR_MAP;
4230
4231 if (!se_mask[0] && !se_mask[1]) {
4232 raster_config_1 |=
4233 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
4234 } else {
4235 raster_config_1 |=
4236 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
4237 }
4238 }
4239
4240 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
4241 }
4242 }
4243
4244 static void si_init_config(struct si_context *sctx)
4245 {
4246 struct si_screen *sscreen = sctx->screen;
4247 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
4248 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
4249 unsigned raster_config, raster_config_1;
4250 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
4251 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
4252
4253 if (!pm4)
4254 return;
4255
4256 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
4257 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
4258 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
4259 si_pm4_cmd_end(pm4, false);
4260
4261 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
4262 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
4263
4264 /* FIXME calculate these values somehow ??? */
4265 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
4266 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
4267 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
4268
4269 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
4270 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
4271
4272 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
4273 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
4274 if (sctx->b.chip_class < CIK)
4275 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
4276 S_008A14_CLIP_VTX_REORDER_ENA(1));
4277
4278 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
4279 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
4280
4281 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
4282
4283 switch (sctx->screen->b.family) {
4284 case CHIP_TAHITI:
4285 case CHIP_PITCAIRN:
4286 raster_config = 0x2a00126a;
4287 raster_config_1 = 0x00000000;
4288 break;
4289 case CHIP_VERDE:
4290 raster_config = 0x0000124a;
4291 raster_config_1 = 0x00000000;
4292 break;
4293 case CHIP_OLAND:
4294 raster_config = 0x00000082;
4295 raster_config_1 = 0x00000000;
4296 break;
4297 case CHIP_HAINAN:
4298 raster_config = 0x00000000;
4299 raster_config_1 = 0x00000000;
4300 break;
4301 case CHIP_BONAIRE:
4302 raster_config = 0x16000012;
4303 raster_config_1 = 0x00000000;
4304 break;
4305 case CHIP_HAWAII:
4306 raster_config = 0x3a00161a;
4307 raster_config_1 = 0x0000002e;
4308 break;
4309 case CHIP_FIJI:
4310 if (sscreen->b.info.cik_macrotile_mode_array[0] == 0x000000e8) {
4311 /* old kernels with old tiling config */
4312 raster_config = 0x16000012;
4313 raster_config_1 = 0x0000002a;
4314 } else {
4315 raster_config = 0x3a00161a;
4316 raster_config_1 = 0x0000002e;
4317 }
4318 break;
4319 case CHIP_POLARIS10:
4320 raster_config = 0x16000012;
4321 raster_config_1 = 0x0000002a;
4322 break;
4323 case CHIP_POLARIS11:
4324 case CHIP_POLARIS12:
4325 raster_config = 0x16000012;
4326 raster_config_1 = 0x00000000;
4327 break;
4328 case CHIP_TONGA:
4329 raster_config = 0x16000012;
4330 raster_config_1 = 0x0000002a;
4331 break;
4332 case CHIP_ICELAND:
4333 if (num_rb == 1)
4334 raster_config = 0x00000000;
4335 else
4336 raster_config = 0x00000002;
4337 raster_config_1 = 0x00000000;
4338 break;
4339 case CHIP_CARRIZO:
4340 raster_config = 0x00000002;
4341 raster_config_1 = 0x00000000;
4342 break;
4343 case CHIP_KAVERI:
4344 /* KV should be 0x00000002, but that causes problems with radeon */
4345 raster_config = 0x00000000; /* 0x00000002 */
4346 raster_config_1 = 0x00000000;
4347 break;
4348 case CHIP_KABINI:
4349 case CHIP_MULLINS:
4350 case CHIP_STONEY:
4351 raster_config = 0x00000000;
4352 raster_config_1 = 0x00000000;
4353 break;
4354 default:
4355 if (sctx->b.chip_class <= VI) {
4356 fprintf(stderr,
4357 "radeonsi: Unknown GPU, using 0 for raster_config\n");
4358 raster_config = 0x00000000;
4359 raster_config_1 = 0x00000000;
4360 }
4361 break;
4362 }
4363
4364 if (sctx->b.chip_class <= VI) {
4365 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
4366 /* Always use the default config when all backends are enabled
4367 * (or when we failed to determine the enabled backends).
4368 */
4369 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
4370 raster_config);
4371 if (sctx->b.chip_class >= CIK)
4372 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
4373 raster_config_1);
4374 } else {
4375 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
4376 }
4377 }
4378
4379 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
4380 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
4381 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
4382 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
4383 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
4384 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
4385 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
4386
4387 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
4388 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
4389 S_028230_ER_TRI(0xA) |
4390 S_028230_ER_POINT(0xA) |
4391 S_028230_ER_RECT(0xA) |
4392 /* Required by DX10_DIAMOND_TEST_ENA: */
4393 S_028230_ER_LINE_LR(0x1A) |
4394 S_028230_ER_LINE_RL(0x26) |
4395 S_028230_ER_LINE_TB(0xA) |
4396 S_028230_ER_LINE_BT(0xA));
4397 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
4398 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
4399 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
4400 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
4401 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
4402 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
4403 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 0);
4404
4405 if (sctx->b.chip_class >= GFX9) {
4406 si_pm4_set_reg(pm4, R_030920_VGT_MAX_VTX_INDX, ~0);
4407 si_pm4_set_reg(pm4, R_030924_VGT_MIN_VTX_INDX, 0);
4408 si_pm4_set_reg(pm4, R_030928_VGT_INDX_OFFSET, 0);
4409 } else {
4410 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
4411 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
4412 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
4413 }
4414
4415 if (sctx->b.chip_class >= CIK) {
4416 /* If this is 0, Bonaire can hang even if GS isn't being used.
4417 * Other chips are unaffected. These are suboptimal values,
4418 * but we don't use on-chip GS.
4419 */
4420 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
4421 S_028A44_ES_VERTS_PER_SUBGRP(64) |
4422 S_028A44_GS_PRIMS_PER_SUBGRP(4));
4423
4424 if (sctx->b.chip_class >= GFX9) {
4425 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, S_00B41C_CU_EN(0xffff));
4426 } else {
4427 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff));
4428 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
4429 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xffff));
4430 }
4431 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
4432
4433 if (sscreen->b.info.num_good_compute_units /
4434 (sscreen->b.info.max_se * sscreen->b.info.max_sh_per_se) <= 4) {
4435 /* Too few available compute units per SH. Disallowing
4436 * VS to run on CU0 could hurt us more than late VS
4437 * allocation would help.
4438 *
4439 * LATE_ALLOC_VS = 2 is the highest safe number.
4440 */
4441 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
4442 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
4443 } else {
4444 /* Set LATE_ALLOC_VS == 31. It should be less than
4445 * the number of scratch waves. Limitations:
4446 * - VS can't execute on CU0.
4447 * - If HS writes outputs to LDS, LS can't execute on CU0.
4448 */
4449 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xfffe));
4450 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
4451 }
4452
4453 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
4454 }
4455
4456 if (sctx->b.chip_class >= VI) {
4457 unsigned vgt_tess_distribution;
4458
4459 si_pm4_set_reg(pm4, R_028424_CB_DCC_CONTROL,
4460 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
4461 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
4462 if (sctx->b.family < CHIP_POLARIS10)
4463 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
4464 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
4465
4466 vgt_tess_distribution =
4467 S_028B50_ACCUM_ISOLINE(32) |
4468 S_028B50_ACCUM_TRI(11) |
4469 S_028B50_ACCUM_QUAD(11) |
4470 S_028B50_DONUT_SPLIT(16);
4471
4472 /* Testing with Unigine Heaven extreme tesselation yielded best results
4473 * with TRAP_SPLIT = 3.
4474 */
4475 if (sctx->b.family == CHIP_FIJI ||
4476 sctx->b.family >= CHIP_POLARIS10)
4477 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
4478
4479 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution);
4480 } else {
4481 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
4482 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
4483 }
4484
4485 if (sctx->screen->b.has_rbplus)
4486 si_pm4_set_reg(pm4, R_028C40_PA_SC_SHADER_CONTROL, 0);
4487
4488 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
4489 if (sctx->b.chip_class >= CIK)
4490 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, border_color_va >> 40);
4491 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
4492 RADEON_PRIO_BORDER_COLORS);
4493
4494 if (sctx->b.chip_class >= GFX9) {
4495 si_pm4_set_reg(pm4, R_028060_DB_DFSM_CONTROL, 0);
4496 si_pm4_set_reg(pm4, R_028064_DB_RENDER_FILTER, 0);
4497 /* TODO: We can use this to disable RBs for rendering to GART: */
4498 si_pm4_set_reg(pm4, R_02835C_PA_SC_TILE_STEERING_OVERRIDE, 0);
4499 si_pm4_set_reg(pm4, R_02883C_PA_SU_OVER_RASTERIZATION_CNTL, 0);
4500 /* TODO: Enable the binner: */
4501 si_pm4_set_reg(pm4, R_028C44_PA_SC_BINNER_CNTL_0,
4502 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC));
4503 si_pm4_set_reg(pm4, R_028C48_PA_SC_BINNER_CNTL_1, 0);
4504 si_pm4_set_reg(pm4, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
4505 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
4506 si_pm4_set_reg(pm4, R_030968_VGT_INSTANCE_BASE_ID, 0);
4507 }
4508
4509 si_pm4_upload_indirect_buffer(sctx, pm4);
4510 sctx->init_config = pm4;
4511 }