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radeonsi: Only scan pixel shaders for TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "util/u_memory.h"
28 #include "util/u_framebuffer.h"
29 #include "util/u_blitter.h"
30 #include "util/u_helpers.h"
31 #include "util/u_math.h"
32 #include "util/u_pack_color.h"
33 #include "util/u_upload_mgr.h"
34 #include "util/u_format_s3tc.h"
35 #include "tgsi/tgsi_parse.h"
36 #include "tgsi/tgsi_scan.h"
37 #include "radeonsi_pipe.h"
38 #include "radeonsi_shader.h"
39 #include "si_state.h"
40 #include "../radeon/r600_cs.h"
41 #include "sid.h"
42
43 static uint32_t cik_num_banks(uint32_t nbanks)
44 {
45 switch (nbanks) {
46 case 2:
47 return V_02803C_ADDR_SURF_2_BANK;
48 case 4:
49 return V_02803C_ADDR_SURF_4_BANK;
50 case 8:
51 default:
52 return V_02803C_ADDR_SURF_8_BANK;
53 case 16:
54 return V_02803C_ADDR_SURF_16_BANK;
55 }
56 }
57
58
59 static unsigned cik_tile_split(unsigned tile_split)
60 {
61 switch (tile_split) {
62 case 64:
63 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_64B;
64 break;
65 case 128:
66 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_128B;
67 break;
68 case 256:
69 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_256B;
70 break;
71 case 512:
72 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_512B;
73 break;
74 default:
75 case 1024:
76 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_1KB;
77 break;
78 case 2048:
79 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_2KB;
80 break;
81 case 4096:
82 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_4KB;
83 break;
84 }
85 return tile_split;
86 }
87
88 static unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect)
89 {
90 switch (macro_tile_aspect) {
91 default:
92 case 1:
93 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_1;
94 break;
95 case 2:
96 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_2;
97 break;
98 case 4:
99 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_4;
100 break;
101 case 8:
102 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_8;
103 break;
104 }
105 return macro_tile_aspect;
106 }
107
108 static unsigned cik_bank_wh(unsigned bankwh)
109 {
110 switch (bankwh) {
111 default:
112 case 1:
113 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_1;
114 break;
115 case 2:
116 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_2;
117 break;
118 case 4:
119 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_4;
120 break;
121 case 8:
122 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_8;
123 break;
124 }
125 return bankwh;
126 }
127
128 static unsigned cik_db_pipe_config(unsigned tile_pipes,
129 unsigned num_rbs)
130 {
131 unsigned pipe_config;
132
133 switch (tile_pipes) {
134 case 8:
135 pipe_config = V_02803C_X_ADDR_SURF_P8_32X32_16X16;
136 break;
137 case 4:
138 default:
139 if (num_rbs == 4)
140 pipe_config = V_02803C_X_ADDR_SURF_P4_16X16;
141 else
142 pipe_config = V_02803C_X_ADDR_SURF_P4_8X16;
143 break;
144 case 2:
145 pipe_config = V_02803C_ADDR_SURF_P2;
146 break;
147 }
148 return pipe_config;
149 }
150
151 /*
152 * inferred framebuffer and blender state
153 */
154 static void si_update_fb_blend_state(struct r600_context *rctx)
155 {
156 struct si_pm4_state *pm4;
157 struct si_state_blend *blend = rctx->queued.named.blend;
158 uint32_t mask;
159
160 if (blend == NULL)
161 return;
162
163 pm4 = si_pm4_alloc_state(rctx);
164 if (pm4 == NULL)
165 return;
166
167 mask = (1ULL << ((unsigned)rctx->framebuffer.nr_cbufs * 4)) - 1;
168 mask &= blend->cb_target_mask;
169 si_pm4_set_reg(pm4, R_028238_CB_TARGET_MASK, mask);
170
171 si_pm4_set_state(rctx, fb_blend, pm4);
172 }
173
174 /*
175 * Blender functions
176 */
177
178 static uint32_t si_translate_blend_function(int blend_func)
179 {
180 switch (blend_func) {
181 case PIPE_BLEND_ADD:
182 return V_028780_COMB_DST_PLUS_SRC;
183 case PIPE_BLEND_SUBTRACT:
184 return V_028780_COMB_SRC_MINUS_DST;
185 case PIPE_BLEND_REVERSE_SUBTRACT:
186 return V_028780_COMB_DST_MINUS_SRC;
187 case PIPE_BLEND_MIN:
188 return V_028780_COMB_MIN_DST_SRC;
189 case PIPE_BLEND_MAX:
190 return V_028780_COMB_MAX_DST_SRC;
191 default:
192 R600_ERR("Unknown blend function %d\n", blend_func);
193 assert(0);
194 break;
195 }
196 return 0;
197 }
198
199 static uint32_t si_translate_blend_factor(int blend_fact)
200 {
201 switch (blend_fact) {
202 case PIPE_BLENDFACTOR_ONE:
203 return V_028780_BLEND_ONE;
204 case PIPE_BLENDFACTOR_SRC_COLOR:
205 return V_028780_BLEND_SRC_COLOR;
206 case PIPE_BLENDFACTOR_SRC_ALPHA:
207 return V_028780_BLEND_SRC_ALPHA;
208 case PIPE_BLENDFACTOR_DST_ALPHA:
209 return V_028780_BLEND_DST_ALPHA;
210 case PIPE_BLENDFACTOR_DST_COLOR:
211 return V_028780_BLEND_DST_COLOR;
212 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
213 return V_028780_BLEND_SRC_ALPHA_SATURATE;
214 case PIPE_BLENDFACTOR_CONST_COLOR:
215 return V_028780_BLEND_CONSTANT_COLOR;
216 case PIPE_BLENDFACTOR_CONST_ALPHA:
217 return V_028780_BLEND_CONSTANT_ALPHA;
218 case PIPE_BLENDFACTOR_ZERO:
219 return V_028780_BLEND_ZERO;
220 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
221 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
222 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
223 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
224 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
225 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
226 case PIPE_BLENDFACTOR_INV_DST_COLOR:
227 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
228 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
229 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
230 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
231 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
232 case PIPE_BLENDFACTOR_SRC1_COLOR:
233 return V_028780_BLEND_SRC1_COLOR;
234 case PIPE_BLENDFACTOR_SRC1_ALPHA:
235 return V_028780_BLEND_SRC1_ALPHA;
236 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
237 return V_028780_BLEND_INV_SRC1_COLOR;
238 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
239 return V_028780_BLEND_INV_SRC1_ALPHA;
240 default:
241 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
242 assert(0);
243 break;
244 }
245 return 0;
246 }
247
248 static void *si_create_blend_state_mode(struct pipe_context *ctx,
249 const struct pipe_blend_state *state,
250 unsigned mode)
251 {
252 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
253 struct si_pm4_state *pm4 = &blend->pm4;
254
255 uint32_t color_control = 0;
256
257 if (blend == NULL)
258 return NULL;
259
260 blend->alpha_to_one = state->alpha_to_one;
261
262 if (state->logicop_enable) {
263 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
264 } else {
265 color_control |= S_028808_ROP3(0xcc);
266 }
267
268 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
269 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
270 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
271 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
272 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
273 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
274
275 blend->cb_target_mask = 0;
276 for (int i = 0; i < 8; i++) {
277 /* state->rt entries > 0 only written if independent blending */
278 const int j = state->independent_blend_enable ? i : 0;
279
280 unsigned eqRGB = state->rt[j].rgb_func;
281 unsigned srcRGB = state->rt[j].rgb_src_factor;
282 unsigned dstRGB = state->rt[j].rgb_dst_factor;
283 unsigned eqA = state->rt[j].alpha_func;
284 unsigned srcA = state->rt[j].alpha_src_factor;
285 unsigned dstA = state->rt[j].alpha_dst_factor;
286
287 unsigned blend_cntl = 0;
288
289 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
290 blend->cb_target_mask |= state->rt[j].colormask << (4 * i);
291
292 if (!state->rt[j].blend_enable) {
293 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
294 continue;
295 }
296
297 blend_cntl |= S_028780_ENABLE(1);
298 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
299 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
300 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
301
302 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
303 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
304 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
305 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
306 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
307 }
308 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
309 }
310
311 if (blend->cb_target_mask) {
312 color_control |= S_028808_MODE(mode);
313 } else {
314 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
315 }
316 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
317
318 return blend;
319 }
320
321 static void *si_create_blend_state(struct pipe_context *ctx,
322 const struct pipe_blend_state *state)
323 {
324 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
325 }
326
327 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
328 {
329 struct r600_context *rctx = (struct r600_context *)ctx;
330 si_pm4_bind_state(rctx, blend, (struct si_state_blend *)state);
331 si_update_fb_blend_state(rctx);
332 }
333
334 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
335 {
336 struct r600_context *rctx = (struct r600_context *)ctx;
337 si_pm4_delete_state(rctx, blend, (struct si_state_blend *)state);
338 }
339
340 static void si_set_blend_color(struct pipe_context *ctx,
341 const struct pipe_blend_color *state)
342 {
343 struct r600_context *rctx = (struct r600_context *)ctx;
344 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
345
346 if (pm4 == NULL)
347 return;
348
349 si_pm4_set_reg(pm4, R_028414_CB_BLEND_RED, fui(state->color[0]));
350 si_pm4_set_reg(pm4, R_028418_CB_BLEND_GREEN, fui(state->color[1]));
351 si_pm4_set_reg(pm4, R_02841C_CB_BLEND_BLUE, fui(state->color[2]));
352 si_pm4_set_reg(pm4, R_028420_CB_BLEND_ALPHA, fui(state->color[3]));
353
354 si_pm4_set_state(rctx, blend_color, pm4);
355 }
356
357 /*
358 * Clipping, scissors and viewport
359 */
360
361 static void si_set_clip_state(struct pipe_context *ctx,
362 const struct pipe_clip_state *state)
363 {
364 struct r600_context *rctx = (struct r600_context *)ctx;
365 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
366 struct pipe_constant_buffer cb;
367
368 if (pm4 == NULL)
369 return;
370
371 for (int i = 0; i < 6; i++) {
372 si_pm4_set_reg(pm4, R_0285BC_PA_CL_UCP_0_X + i * 16,
373 fui(state->ucp[i][0]));
374 si_pm4_set_reg(pm4, R_0285C0_PA_CL_UCP_0_Y + i * 16,
375 fui(state->ucp[i][1]));
376 si_pm4_set_reg(pm4, R_0285C4_PA_CL_UCP_0_Z + i * 16,
377 fui(state->ucp[i][2]));
378 si_pm4_set_reg(pm4, R_0285C8_PA_CL_UCP_0_W + i * 16,
379 fui(state->ucp[i][3]));
380 }
381
382 cb.buffer = NULL;
383 cb.user_buffer = state->ucp;
384 cb.buffer_offset = 0;
385 cb.buffer_size = 4*4*8;
386 ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, NUM_PIPE_CONST_BUFFERS, &cb);
387 pipe_resource_reference(&cb.buffer, NULL);
388
389 si_pm4_set_state(rctx, clip, pm4);
390 }
391
392 static void si_set_scissor_states(struct pipe_context *ctx,
393 unsigned start_slot,
394 unsigned num_scissors,
395 const struct pipe_scissor_state *state)
396 {
397 struct r600_context *rctx = (struct r600_context *)ctx;
398 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
399 uint32_t tl, br;
400
401 if (pm4 == NULL)
402 return;
403
404 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny);
405 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
406 si_pm4_set_reg(pm4, R_028210_PA_SC_CLIPRECT_0_TL, tl);
407 si_pm4_set_reg(pm4, R_028214_PA_SC_CLIPRECT_0_BR, br);
408 si_pm4_set_reg(pm4, R_028218_PA_SC_CLIPRECT_1_TL, tl);
409 si_pm4_set_reg(pm4, R_02821C_PA_SC_CLIPRECT_1_BR, br);
410 si_pm4_set_reg(pm4, R_028220_PA_SC_CLIPRECT_2_TL, tl);
411 si_pm4_set_reg(pm4, R_028224_PA_SC_CLIPRECT_2_BR, br);
412 si_pm4_set_reg(pm4, R_028228_PA_SC_CLIPRECT_3_TL, tl);
413 si_pm4_set_reg(pm4, R_02822C_PA_SC_CLIPRECT_3_BR, br);
414
415 si_pm4_set_state(rctx, scissor, pm4);
416 }
417
418 static void si_set_viewport_states(struct pipe_context *ctx,
419 unsigned start_slot,
420 unsigned num_viewports,
421 const struct pipe_viewport_state *state)
422 {
423 struct r600_context *rctx = (struct r600_context *)ctx;
424 struct si_state_viewport *viewport = CALLOC_STRUCT(si_state_viewport);
425 struct si_pm4_state *pm4 = &viewport->pm4;
426
427 if (viewport == NULL)
428 return;
429
430 viewport->viewport = *state;
431 si_pm4_set_reg(pm4, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
432 si_pm4_set_reg(pm4, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
433 si_pm4_set_reg(pm4, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
434 si_pm4_set_reg(pm4, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
435 si_pm4_set_reg(pm4, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
436 si_pm4_set_reg(pm4, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
437
438 si_pm4_set_state(rctx, viewport, viewport);
439 }
440
441 /*
442 * inferred state between framebuffer and rasterizer
443 */
444 static void si_update_fb_rs_state(struct r600_context *rctx)
445 {
446 struct si_state_rasterizer *rs = rctx->queued.named.rasterizer;
447 struct si_pm4_state *pm4;
448 unsigned offset_db_fmt_cntl = 0, depth;
449 float offset_units;
450
451 if (!rs || !rctx->framebuffer.zsbuf)
452 return;
453
454 offset_units = rctx->queued.named.rasterizer->offset_units;
455 switch (rctx->framebuffer.zsbuf->texture->format) {
456 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
457 case PIPE_FORMAT_X8Z24_UNORM:
458 case PIPE_FORMAT_Z24X8_UNORM:
459 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
460 depth = -24;
461 offset_units *= 2.0f;
462 break;
463 case PIPE_FORMAT_Z32_FLOAT:
464 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
465 depth = -23;
466 offset_units *= 1.0f;
467 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
468 break;
469 case PIPE_FORMAT_Z16_UNORM:
470 depth = -16;
471 offset_units *= 4.0f;
472 break;
473 default:
474 return;
475 }
476
477 pm4 = si_pm4_alloc_state(rctx);
478
479 if (pm4 == NULL)
480 return;
481
482 /* FIXME some of those reg can be computed with cso */
483 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
484 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
485 fui(rctx->queued.named.rasterizer->offset_scale));
486 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units));
487 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
488 fui(rctx->queued.named.rasterizer->offset_scale));
489 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units));
490 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, offset_db_fmt_cntl);
491
492 si_pm4_set_state(rctx, fb_rs, pm4);
493 }
494
495 /*
496 * Rasterizer
497 */
498
499 static uint32_t si_translate_fill(uint32_t func)
500 {
501 switch(func) {
502 case PIPE_POLYGON_MODE_FILL:
503 return V_028814_X_DRAW_TRIANGLES;
504 case PIPE_POLYGON_MODE_LINE:
505 return V_028814_X_DRAW_LINES;
506 case PIPE_POLYGON_MODE_POINT:
507 return V_028814_X_DRAW_POINTS;
508 default:
509 assert(0);
510 return V_028814_X_DRAW_POINTS;
511 }
512 }
513
514 static void *si_create_rs_state(struct pipe_context *ctx,
515 const struct pipe_rasterizer_state *state)
516 {
517 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
518 struct si_pm4_state *pm4 = &rs->pm4;
519 unsigned tmp;
520 unsigned prov_vtx = 1, polygon_dual_mode;
521 unsigned clip_rule;
522 float psize_min, psize_max;
523
524 if (rs == NULL) {
525 return NULL;
526 }
527
528 rs->two_side = state->light_twoside;
529 rs->multisample_enable = state->multisample;
530 rs->clip_plane_enable = state->clip_plane_enable;
531 rs->line_stipple_enable = state->line_stipple_enable;
532
533 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
534 state->fill_back != PIPE_POLYGON_MODE_FILL);
535
536 if (state->flatshade_first)
537 prov_vtx = 0;
538
539 rs->flatshade = state->flatshade;
540 rs->sprite_coord_enable = state->sprite_coord_enable;
541 rs->pa_sc_line_stipple = state->line_stipple_enable ?
542 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
543 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
544 rs->pa_su_sc_mode_cntl =
545 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
546 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
547 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
548 S_028814_FACE(!state->front_ccw) |
549 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
550 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
551 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
552 S_028814_POLY_MODE(polygon_dual_mode) |
553 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
554 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back));
555 rs->pa_cl_clip_cntl =
556 S_028810_PS_UCP_MODE(3) |
557 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
558 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
559 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
560 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
561
562 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
563
564 /* offset */
565 rs->offset_units = state->offset_units;
566 rs->offset_scale = state->offset_scale * 12.0f;
567
568 tmp = S_0286D4_FLAT_SHADE_ENA(1);
569 if (state->sprite_coord_enable) {
570 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
571 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
572 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
573 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
574 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1);
575 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
576 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
577 }
578 }
579 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
580
581 /* point size 12.4 fixed point */
582 tmp = (unsigned)(state->point_size * 8.0);
583 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
584
585 if (state->point_size_per_vertex) {
586 psize_min = util_get_min_point_size(state);
587 psize_max = 8192;
588 } else {
589 /* Force the point size to be as if the vertex output was disabled. */
590 psize_min = state->point_size;
591 psize_max = state->point_size;
592 }
593 /* Divide by two, because 0.5 = 1 pixel. */
594 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
595 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
596 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
597
598 tmp = (unsigned)state->line_width * 8;
599 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
600 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
601 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
602 S_028A48_MSAA_ENABLE(state->multisample));
603
604 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
605 S_028BE4_PIX_CENTER(state->half_pixel_center) |
606 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
607
608 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
609 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule);
610
611 return rs;
612 }
613
614 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
615 {
616 struct r600_context *rctx = (struct r600_context *)ctx;
617 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
618
619 if (state == NULL)
620 return;
621
622 // TODO
623 rctx->sprite_coord_enable = rs->sprite_coord_enable;
624 rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
625 rctx->pa_su_sc_mode_cntl = rs->pa_su_sc_mode_cntl;
626
627 si_pm4_bind_state(rctx, rasterizer, rs);
628 si_update_fb_rs_state(rctx);
629 }
630
631 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
632 {
633 struct r600_context *rctx = (struct r600_context *)ctx;
634 si_pm4_delete_state(rctx, rasterizer, (struct si_state_rasterizer *)state);
635 }
636
637 /*
638 * infeered state between dsa and stencil ref
639 */
640 static void si_update_dsa_stencil_ref(struct r600_context *rctx)
641 {
642 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
643 struct pipe_stencil_ref *ref = &rctx->stencil_ref;
644 struct si_state_dsa *dsa = rctx->queued.named.dsa;
645
646 if (pm4 == NULL)
647 return;
648
649 si_pm4_set_reg(pm4, R_028430_DB_STENCILREFMASK,
650 S_028430_STENCILTESTVAL(ref->ref_value[0]) |
651 S_028430_STENCILMASK(dsa->valuemask[0]) |
652 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
653 S_028430_STENCILOPVAL(1));
654 si_pm4_set_reg(pm4, R_028434_DB_STENCILREFMASK_BF,
655 S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
656 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
657 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
658 S_028434_STENCILOPVAL_BF(1));
659
660 si_pm4_set_state(rctx, dsa_stencil_ref, pm4);
661 }
662
663 static void si_set_pipe_stencil_ref(struct pipe_context *ctx,
664 const struct pipe_stencil_ref *state)
665 {
666 struct r600_context *rctx = (struct r600_context *)ctx;
667 rctx->stencil_ref = *state;
668 si_update_dsa_stencil_ref(rctx);
669 }
670
671
672 /*
673 * DSA
674 */
675
676 static uint32_t si_translate_stencil_op(int s_op)
677 {
678 switch (s_op) {
679 case PIPE_STENCIL_OP_KEEP:
680 return V_02842C_STENCIL_KEEP;
681 case PIPE_STENCIL_OP_ZERO:
682 return V_02842C_STENCIL_ZERO;
683 case PIPE_STENCIL_OP_REPLACE:
684 return V_02842C_STENCIL_REPLACE_TEST;
685 case PIPE_STENCIL_OP_INCR:
686 return V_02842C_STENCIL_ADD_CLAMP;
687 case PIPE_STENCIL_OP_DECR:
688 return V_02842C_STENCIL_SUB_CLAMP;
689 case PIPE_STENCIL_OP_INCR_WRAP:
690 return V_02842C_STENCIL_ADD_WRAP;
691 case PIPE_STENCIL_OP_DECR_WRAP:
692 return V_02842C_STENCIL_SUB_WRAP;
693 case PIPE_STENCIL_OP_INVERT:
694 return V_02842C_STENCIL_INVERT;
695 default:
696 R600_ERR("Unknown stencil op %d", s_op);
697 assert(0);
698 break;
699 }
700 return 0;
701 }
702
703 static void *si_create_dsa_state(struct pipe_context *ctx,
704 const struct pipe_depth_stencil_alpha_state *state)
705 {
706 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
707 struct si_pm4_state *pm4 = &dsa->pm4;
708 unsigned db_depth_control;
709 unsigned db_render_control;
710 uint32_t db_stencil_control = 0;
711
712 if (dsa == NULL) {
713 return NULL;
714 }
715
716 dsa->valuemask[0] = state->stencil[0].valuemask;
717 dsa->valuemask[1] = state->stencil[1].valuemask;
718 dsa->writemask[0] = state->stencil[0].writemask;
719 dsa->writemask[1] = state->stencil[1].writemask;
720
721 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
722 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
723 S_028800_ZFUNC(state->depth.func);
724
725 /* stencil */
726 if (state->stencil[0].enabled) {
727 db_depth_control |= S_028800_STENCIL_ENABLE(1);
728 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
729 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
730 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
731 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
732
733 if (state->stencil[1].enabled) {
734 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
735 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
736 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
737 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
738 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
739 }
740 }
741
742 /* alpha */
743 if (state->alpha.enabled) {
744 dsa->alpha_func = state->alpha.func;
745 dsa->alpha_ref = state->alpha.ref_value;
746
747 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
748 SI_SGPR_ALPHA_REF * 4, fui(dsa->alpha_ref));
749 } else {
750 dsa->alpha_func = PIPE_FUNC_ALWAYS;
751 }
752
753 /* misc */
754 db_render_control = 0;
755 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
756 si_pm4_set_reg(pm4, R_028000_DB_RENDER_CONTROL, db_render_control);
757 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
758
759 return dsa;
760 }
761
762 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
763 {
764 struct r600_context *rctx = (struct r600_context *)ctx;
765 struct si_state_dsa *dsa = state;
766
767 if (state == NULL)
768 return;
769
770 si_pm4_bind_state(rctx, dsa, dsa);
771 si_update_dsa_stencil_ref(rctx);
772 }
773
774 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
775 {
776 struct r600_context *rctx = (struct r600_context *)ctx;
777 si_pm4_delete_state(rctx, dsa, (struct si_state_dsa *)state);
778 }
779
780 static void *si_create_db_flush_dsa(struct r600_context *rctx, bool copy_depth,
781 bool copy_stencil, int sample)
782 {
783 struct pipe_depth_stencil_alpha_state dsa;
784 struct si_state_dsa *state;
785
786 memset(&dsa, 0, sizeof(dsa));
787
788 state = rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa);
789 if (copy_depth || copy_stencil) {
790 si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL,
791 S_028000_DEPTH_COPY(copy_depth) |
792 S_028000_STENCIL_COPY(copy_stencil) |
793 S_028000_COPY_CENTROID(1) |
794 S_028000_COPY_SAMPLE(sample));
795 } else {
796 si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL,
797 S_028000_DEPTH_COMPRESS_DISABLE(1) |
798 S_028000_STENCIL_COMPRESS_DISABLE(1));
799 }
800
801 return state;
802 }
803
804 /*
805 * format translation
806 */
807 static uint32_t si_translate_colorformat(enum pipe_format format)
808 {
809 const struct util_format_description *desc = util_format_description(format);
810
811 #define HAS_SIZE(x,y,z,w) \
812 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
813 desc->channel[2].size == (z) && desc->channel[3].size == (w))
814
815 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
816 return V_028C70_COLOR_10_11_11;
817
818 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
819 return V_028C70_COLOR_INVALID;
820
821 switch (desc->nr_channels) {
822 case 1:
823 switch (desc->channel[0].size) {
824 case 8:
825 return V_028C70_COLOR_8;
826 case 16:
827 return V_028C70_COLOR_16;
828 case 32:
829 return V_028C70_COLOR_32;
830 }
831 break;
832 case 2:
833 if (desc->channel[0].size == desc->channel[1].size) {
834 switch (desc->channel[0].size) {
835 case 8:
836 return V_028C70_COLOR_8_8;
837 case 16:
838 return V_028C70_COLOR_16_16;
839 case 32:
840 return V_028C70_COLOR_32_32;
841 }
842 } else if (HAS_SIZE(8,24,0,0)) {
843 return V_028C70_COLOR_24_8;
844 } else if (HAS_SIZE(24,8,0,0)) {
845 return V_028C70_COLOR_8_24;
846 }
847 break;
848 case 3:
849 if (HAS_SIZE(5,6,5,0)) {
850 return V_028C70_COLOR_5_6_5;
851 } else if (HAS_SIZE(32,8,24,0)) {
852 return V_028C70_COLOR_X24_8_32_FLOAT;
853 }
854 break;
855 case 4:
856 if (desc->channel[0].size == desc->channel[1].size &&
857 desc->channel[0].size == desc->channel[2].size &&
858 desc->channel[0].size == desc->channel[3].size) {
859 switch (desc->channel[0].size) {
860 case 4:
861 return V_028C70_COLOR_4_4_4_4;
862 case 8:
863 return V_028C70_COLOR_8_8_8_8;
864 case 16:
865 return V_028C70_COLOR_16_16_16_16;
866 case 32:
867 return V_028C70_COLOR_32_32_32_32;
868 }
869 } else if (HAS_SIZE(5,5,5,1)) {
870 return V_028C70_COLOR_1_5_5_5;
871 } else if (HAS_SIZE(10,10,10,2)) {
872 return V_028C70_COLOR_2_10_10_10;
873 }
874 break;
875 }
876 return V_028C70_COLOR_INVALID;
877 }
878
879 static uint32_t si_translate_colorswap(enum pipe_format format)
880 {
881 const struct util_format_description *desc = util_format_description(format);
882
883 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == UTIL_FORMAT_SWIZZLE_##swz)
884
885 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
886 return V_028C70_SWAP_STD;
887
888 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
889 return ~0;
890
891 switch (desc->nr_channels) {
892 case 1:
893 if (HAS_SWIZZLE(0,X))
894 return V_028C70_SWAP_STD; /* X___ */
895 else if (HAS_SWIZZLE(3,X))
896 return V_028C70_SWAP_ALT_REV; /* ___X */
897 break;
898 case 2:
899 if ((HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,Y)) ||
900 (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,NONE)) ||
901 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,Y)))
902 return V_028C70_SWAP_STD; /* XY__ */
903 else if ((HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,X)) ||
904 (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,NONE)) ||
905 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,X)))
906 return V_028C70_SWAP_STD_REV; /* YX__ */
907 else if (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(3,Y))
908 return V_028C70_SWAP_ALT; /* X__Y */
909 break;
910 case 3:
911 if (HAS_SWIZZLE(0,X))
912 return V_028C70_SWAP_STD; /* XYZ */
913 else if (HAS_SWIZZLE(0,Z))
914 return V_028C70_SWAP_STD_REV; /* ZYX */
915 break;
916 case 4:
917 /* check the middle channels, the 1st and 4th channel can be NONE */
918 if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,Z))
919 return V_028C70_SWAP_STD; /* XYZW */
920 else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,Y))
921 return V_028C70_SWAP_STD_REV; /* WZYX */
922 else if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,X))
923 return V_028C70_SWAP_ALT; /* ZYXW */
924 else if (HAS_SWIZZLE(1,X) && HAS_SWIZZLE(2,Y))
925 return V_028C70_SWAP_ALT_REV; /* WXYZ */
926 break;
927 }
928 return ~0U;
929 }
930
931 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
932 {
933 if (R600_BIG_ENDIAN) {
934 switch(colorformat) {
935 /* 8-bit buffers. */
936 case V_028C70_COLOR_8:
937 return V_028C70_ENDIAN_NONE;
938
939 /* 16-bit buffers. */
940 case V_028C70_COLOR_5_6_5:
941 case V_028C70_COLOR_1_5_5_5:
942 case V_028C70_COLOR_4_4_4_4:
943 case V_028C70_COLOR_16:
944 case V_028C70_COLOR_8_8:
945 return V_028C70_ENDIAN_8IN16;
946
947 /* 32-bit buffers. */
948 case V_028C70_COLOR_8_8_8_8:
949 case V_028C70_COLOR_2_10_10_10:
950 case V_028C70_COLOR_8_24:
951 case V_028C70_COLOR_24_8:
952 case V_028C70_COLOR_16_16:
953 return V_028C70_ENDIAN_8IN32;
954
955 /* 64-bit buffers. */
956 case V_028C70_COLOR_16_16_16_16:
957 return V_028C70_ENDIAN_8IN16;
958
959 case V_028C70_COLOR_32_32:
960 return V_028C70_ENDIAN_8IN32;
961
962 /* 128-bit buffers. */
963 case V_028C70_COLOR_32_32_32_32:
964 return V_028C70_ENDIAN_8IN32;
965 default:
966 return V_028C70_ENDIAN_NONE; /* Unsupported. */
967 }
968 } else {
969 return V_028C70_ENDIAN_NONE;
970 }
971 }
972
973 /* Returns the size in bits of the widest component of a CB format */
974 static unsigned si_colorformat_max_comp_size(uint32_t colorformat)
975 {
976 switch(colorformat) {
977 case V_028C70_COLOR_4_4_4_4:
978 return 4;
979
980 case V_028C70_COLOR_1_5_5_5:
981 case V_028C70_COLOR_5_5_5_1:
982 return 5;
983
984 case V_028C70_COLOR_5_6_5:
985 return 6;
986
987 case V_028C70_COLOR_8:
988 case V_028C70_COLOR_8_8:
989 case V_028C70_COLOR_8_8_8_8:
990 return 8;
991
992 case V_028C70_COLOR_10_10_10_2:
993 case V_028C70_COLOR_2_10_10_10:
994 return 10;
995
996 case V_028C70_COLOR_10_11_11:
997 case V_028C70_COLOR_11_11_10:
998 return 11;
999
1000 case V_028C70_COLOR_16:
1001 case V_028C70_COLOR_16_16:
1002 case V_028C70_COLOR_16_16_16_16:
1003 return 16;
1004
1005 case V_028C70_COLOR_8_24:
1006 case V_028C70_COLOR_24_8:
1007 return 24;
1008
1009 case V_028C70_COLOR_32:
1010 case V_028C70_COLOR_32_32:
1011 case V_028C70_COLOR_32_32_32_32:
1012 case V_028C70_COLOR_X24_8_32_FLOAT:
1013 return 32;
1014 }
1015
1016 assert(!"Unknown maximum component size");
1017 return 0;
1018 }
1019
1020 static uint32_t si_translate_dbformat(enum pipe_format format)
1021 {
1022 switch (format) {
1023 case PIPE_FORMAT_Z16_UNORM:
1024 return V_028040_Z_16;
1025 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1026 case PIPE_FORMAT_X8Z24_UNORM:
1027 case PIPE_FORMAT_Z24X8_UNORM:
1028 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1029 return V_028040_Z_24; /* deprecated on SI */
1030 case PIPE_FORMAT_Z32_FLOAT:
1031 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1032 return V_028040_Z_32_FLOAT;
1033 default:
1034 return V_028040_Z_INVALID;
1035 }
1036 }
1037
1038 /*
1039 * Texture translation
1040 */
1041
1042 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1043 enum pipe_format format,
1044 const struct util_format_description *desc,
1045 int first_non_void)
1046 {
1047 struct r600_screen *rscreen = (struct r600_screen*)screen;
1048 bool enable_s3tc = rscreen->b.info.drm_minor >= 31;
1049 boolean uniform = TRUE;
1050 int i;
1051
1052 /* Colorspace (return non-RGB formats directly). */
1053 switch (desc->colorspace) {
1054 /* Depth stencil formats */
1055 case UTIL_FORMAT_COLORSPACE_ZS:
1056 switch (format) {
1057 case PIPE_FORMAT_Z16_UNORM:
1058 return V_008F14_IMG_DATA_FORMAT_16;
1059 case PIPE_FORMAT_X24S8_UINT:
1060 case PIPE_FORMAT_Z24X8_UNORM:
1061 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1062 return V_008F14_IMG_DATA_FORMAT_8_24;
1063 case PIPE_FORMAT_X8Z24_UNORM:
1064 case PIPE_FORMAT_S8X24_UINT:
1065 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1066 return V_008F14_IMG_DATA_FORMAT_24_8;
1067 case PIPE_FORMAT_S8_UINT:
1068 return V_008F14_IMG_DATA_FORMAT_8;
1069 case PIPE_FORMAT_Z32_FLOAT:
1070 return V_008F14_IMG_DATA_FORMAT_32;
1071 case PIPE_FORMAT_X32_S8X24_UINT:
1072 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1073 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1074 default:
1075 goto out_unknown;
1076 }
1077
1078 case UTIL_FORMAT_COLORSPACE_YUV:
1079 goto out_unknown; /* TODO */
1080
1081 case UTIL_FORMAT_COLORSPACE_SRGB:
1082 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1083 goto out_unknown;
1084 break;
1085
1086 default:
1087 break;
1088 }
1089
1090 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1091 if (!enable_s3tc)
1092 goto out_unknown;
1093
1094 switch (format) {
1095 case PIPE_FORMAT_RGTC1_SNORM:
1096 case PIPE_FORMAT_LATC1_SNORM:
1097 case PIPE_FORMAT_RGTC1_UNORM:
1098 case PIPE_FORMAT_LATC1_UNORM:
1099 return V_008F14_IMG_DATA_FORMAT_BC4;
1100 case PIPE_FORMAT_RGTC2_SNORM:
1101 case PIPE_FORMAT_LATC2_SNORM:
1102 case PIPE_FORMAT_RGTC2_UNORM:
1103 case PIPE_FORMAT_LATC2_UNORM:
1104 return V_008F14_IMG_DATA_FORMAT_BC5;
1105 default:
1106 goto out_unknown;
1107 }
1108 }
1109
1110 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1111
1112 if (!enable_s3tc)
1113 goto out_unknown;
1114
1115 if (!util_format_s3tc_enabled) {
1116 goto out_unknown;
1117 }
1118
1119 switch (format) {
1120 case PIPE_FORMAT_DXT1_RGB:
1121 case PIPE_FORMAT_DXT1_RGBA:
1122 case PIPE_FORMAT_DXT1_SRGB:
1123 case PIPE_FORMAT_DXT1_SRGBA:
1124 return V_008F14_IMG_DATA_FORMAT_BC1;
1125 case PIPE_FORMAT_DXT3_RGBA:
1126 case PIPE_FORMAT_DXT3_SRGBA:
1127 return V_008F14_IMG_DATA_FORMAT_BC2;
1128 case PIPE_FORMAT_DXT5_RGBA:
1129 case PIPE_FORMAT_DXT5_SRGBA:
1130 return V_008F14_IMG_DATA_FORMAT_BC3;
1131 default:
1132 goto out_unknown;
1133 }
1134 }
1135
1136 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1137 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1138 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1139 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1140 }
1141
1142 /* R8G8Bx_SNORM - TODO CxV8U8 */
1143
1144 /* See whether the components are of the same size. */
1145 for (i = 1; i < desc->nr_channels; i++) {
1146 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1147 }
1148
1149 /* Non-uniform formats. */
1150 if (!uniform) {
1151 switch(desc->nr_channels) {
1152 case 3:
1153 if (desc->channel[0].size == 5 &&
1154 desc->channel[1].size == 6 &&
1155 desc->channel[2].size == 5) {
1156 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1157 }
1158 goto out_unknown;
1159 case 4:
1160 if (desc->channel[0].size == 5 &&
1161 desc->channel[1].size == 5 &&
1162 desc->channel[2].size == 5 &&
1163 desc->channel[3].size == 1) {
1164 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1165 }
1166 if (desc->channel[0].size == 10 &&
1167 desc->channel[1].size == 10 &&
1168 desc->channel[2].size == 10 &&
1169 desc->channel[3].size == 2) {
1170 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1171 }
1172 goto out_unknown;
1173 }
1174 goto out_unknown;
1175 }
1176
1177 if (first_non_void < 0 || first_non_void > 3)
1178 goto out_unknown;
1179
1180 /* uniform formats */
1181 switch (desc->channel[first_non_void].size) {
1182 case 4:
1183 switch (desc->nr_channels) {
1184 #if 0 /* Not supported for render targets */
1185 case 2:
1186 return V_008F14_IMG_DATA_FORMAT_4_4;
1187 #endif
1188 case 4:
1189 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1190 }
1191 break;
1192 case 8:
1193 switch (desc->nr_channels) {
1194 case 1:
1195 return V_008F14_IMG_DATA_FORMAT_8;
1196 case 2:
1197 return V_008F14_IMG_DATA_FORMAT_8_8;
1198 case 4:
1199 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1200 }
1201 break;
1202 case 16:
1203 switch (desc->nr_channels) {
1204 case 1:
1205 return V_008F14_IMG_DATA_FORMAT_16;
1206 case 2:
1207 return V_008F14_IMG_DATA_FORMAT_16_16;
1208 case 4:
1209 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1210 }
1211 break;
1212 case 32:
1213 switch (desc->nr_channels) {
1214 case 1:
1215 return V_008F14_IMG_DATA_FORMAT_32;
1216 case 2:
1217 return V_008F14_IMG_DATA_FORMAT_32_32;
1218 #if 0 /* Not supported for render targets */
1219 case 3:
1220 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1221 #endif
1222 case 4:
1223 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1224 }
1225 }
1226
1227 out_unknown:
1228 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1229 return ~0;
1230 }
1231
1232 static unsigned si_tex_wrap(unsigned wrap)
1233 {
1234 switch (wrap) {
1235 default:
1236 case PIPE_TEX_WRAP_REPEAT:
1237 return V_008F30_SQ_TEX_WRAP;
1238 case PIPE_TEX_WRAP_CLAMP:
1239 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1240 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1241 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1242 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1243 return V_008F30_SQ_TEX_CLAMP_BORDER;
1244 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1245 return V_008F30_SQ_TEX_MIRROR;
1246 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1247 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1248 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1249 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1250 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1251 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1252 }
1253 }
1254
1255 static unsigned si_tex_filter(unsigned filter)
1256 {
1257 switch (filter) {
1258 default:
1259 case PIPE_TEX_FILTER_NEAREST:
1260 return V_008F38_SQ_TEX_XY_FILTER_POINT;
1261 case PIPE_TEX_FILTER_LINEAR:
1262 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
1263 }
1264 }
1265
1266 static unsigned si_tex_mipfilter(unsigned filter)
1267 {
1268 switch (filter) {
1269 case PIPE_TEX_MIPFILTER_NEAREST:
1270 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1271 case PIPE_TEX_MIPFILTER_LINEAR:
1272 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1273 default:
1274 case PIPE_TEX_MIPFILTER_NONE:
1275 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1276 }
1277 }
1278
1279 static unsigned si_tex_compare(unsigned compare)
1280 {
1281 switch (compare) {
1282 default:
1283 case PIPE_FUNC_NEVER:
1284 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1285 case PIPE_FUNC_LESS:
1286 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1287 case PIPE_FUNC_EQUAL:
1288 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1289 case PIPE_FUNC_LEQUAL:
1290 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1291 case PIPE_FUNC_GREATER:
1292 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1293 case PIPE_FUNC_NOTEQUAL:
1294 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1295 case PIPE_FUNC_GEQUAL:
1296 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1297 case PIPE_FUNC_ALWAYS:
1298 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1299 }
1300 }
1301
1302 static unsigned si_tex_dim(unsigned dim, unsigned nr_samples)
1303 {
1304 switch (dim) {
1305 default:
1306 case PIPE_TEXTURE_1D:
1307 return V_008F1C_SQ_RSRC_IMG_1D;
1308 case PIPE_TEXTURE_1D_ARRAY:
1309 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1310 case PIPE_TEXTURE_2D:
1311 case PIPE_TEXTURE_RECT:
1312 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1313 V_008F1C_SQ_RSRC_IMG_2D;
1314 case PIPE_TEXTURE_2D_ARRAY:
1315 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1316 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1317 case PIPE_TEXTURE_3D:
1318 return V_008F1C_SQ_RSRC_IMG_3D;
1319 case PIPE_TEXTURE_CUBE:
1320 return V_008F1C_SQ_RSRC_IMG_CUBE;
1321 }
1322 }
1323
1324 /*
1325 * Format support testing
1326 */
1327
1328 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1329 {
1330 return si_translate_texformat(screen, format, util_format_description(format),
1331 util_format_get_first_non_void_channel(format)) != ~0U;
1332 }
1333
1334 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1335 const struct util_format_description *desc,
1336 int first_non_void)
1337 {
1338 unsigned type = desc->channel[first_non_void].type;
1339 int i;
1340
1341 if (type == UTIL_FORMAT_TYPE_FIXED)
1342 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1343
1344 if (desc->nr_channels == 4 &&
1345 desc->channel[0].size == 10 &&
1346 desc->channel[1].size == 10 &&
1347 desc->channel[2].size == 10 &&
1348 desc->channel[3].size == 2)
1349 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1350
1351 /* See whether the components are of the same size. */
1352 for (i = 0; i < desc->nr_channels; i++) {
1353 if (desc->channel[first_non_void].size != desc->channel[i].size)
1354 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1355 }
1356
1357 switch (desc->channel[first_non_void].size) {
1358 case 8:
1359 switch (desc->nr_channels) {
1360 case 1:
1361 return V_008F0C_BUF_DATA_FORMAT_8;
1362 case 2:
1363 return V_008F0C_BUF_DATA_FORMAT_8_8;
1364 case 3:
1365 case 4:
1366 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1367 }
1368 break;
1369 case 16:
1370 switch (desc->nr_channels) {
1371 case 1:
1372 return V_008F0C_BUF_DATA_FORMAT_16;
1373 case 2:
1374 return V_008F0C_BUF_DATA_FORMAT_16_16;
1375 case 3:
1376 case 4:
1377 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1378 }
1379 break;
1380 case 32:
1381 /* From the Southern Islands ISA documentation about MTBUF:
1382 * 'Memory reads of data in memory that is 32 or 64 bits do not
1383 * undergo any format conversion.'
1384 */
1385 if (type != UTIL_FORMAT_TYPE_FLOAT &&
1386 !desc->channel[first_non_void].pure_integer)
1387 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1388
1389 switch (desc->nr_channels) {
1390 case 1:
1391 return V_008F0C_BUF_DATA_FORMAT_32;
1392 case 2:
1393 return V_008F0C_BUF_DATA_FORMAT_32_32;
1394 case 3:
1395 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1396 case 4:
1397 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1398 }
1399 break;
1400 }
1401
1402 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1403 }
1404
1405 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1406 const struct util_format_description *desc,
1407 int first_non_void)
1408 {
1409 switch (desc->channel[first_non_void].type) {
1410 case UTIL_FORMAT_TYPE_SIGNED:
1411 if (desc->channel[first_non_void].normalized)
1412 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1413 else if (desc->channel[first_non_void].pure_integer)
1414 return V_008F0C_BUF_NUM_FORMAT_SINT;
1415 else
1416 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1417 break;
1418 case UTIL_FORMAT_TYPE_UNSIGNED:
1419 if (desc->channel[first_non_void].normalized)
1420 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1421 else if (desc->channel[first_non_void].pure_integer)
1422 return V_008F0C_BUF_NUM_FORMAT_UINT;
1423 else
1424 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1425 break;
1426 case UTIL_FORMAT_TYPE_FLOAT:
1427 default:
1428 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1429 }
1430 }
1431
1432 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
1433 {
1434 const struct util_format_description *desc;
1435 int first_non_void;
1436 unsigned data_format;
1437
1438 desc = util_format_description(format);
1439 first_non_void = util_format_get_first_non_void_channel(format);
1440 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1441 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
1442 }
1443
1444 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1445 {
1446 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1447 si_translate_colorswap(format) != ~0U;
1448 }
1449
1450 static bool si_is_zs_format_supported(enum pipe_format format)
1451 {
1452 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1453 }
1454
1455 boolean si_is_format_supported(struct pipe_screen *screen,
1456 enum pipe_format format,
1457 enum pipe_texture_target target,
1458 unsigned sample_count,
1459 unsigned usage)
1460 {
1461 struct r600_screen *rscreen = (struct r600_screen *)screen;
1462 unsigned retval = 0;
1463
1464 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1465 R600_ERR("r600: unsupported texture type %d\n", target);
1466 return FALSE;
1467 }
1468
1469 if (!util_format_is_supported(format, usage))
1470 return FALSE;
1471
1472 if (sample_count > 1) {
1473 if (HAVE_LLVM < 0x0304)
1474 return FALSE;
1475
1476 /* 2D tiling on CIK is supported since DRM 2.35.0 */
1477 if (rscreen->b.chip_class >= CIK && rscreen->b.info.drm_minor < 35)
1478 return FALSE;
1479
1480 switch (sample_count) {
1481 case 2:
1482 case 4:
1483 case 8:
1484 break;
1485 default:
1486 return FALSE;
1487 }
1488 }
1489
1490 if (usage & PIPE_BIND_SAMPLER_VIEW) {
1491 if (target == PIPE_BUFFER) {
1492 if (si_is_vertex_format_supported(screen, format))
1493 retval |= PIPE_BIND_SAMPLER_VIEW;
1494 } else {
1495 if (si_is_sampler_format_supported(screen, format))
1496 retval |= PIPE_BIND_SAMPLER_VIEW;
1497 }
1498 }
1499
1500 if ((usage & (PIPE_BIND_RENDER_TARGET |
1501 PIPE_BIND_DISPLAY_TARGET |
1502 PIPE_BIND_SCANOUT |
1503 PIPE_BIND_SHARED)) &&
1504 si_is_colorbuffer_format_supported(format)) {
1505 retval |= usage &
1506 (PIPE_BIND_RENDER_TARGET |
1507 PIPE_BIND_DISPLAY_TARGET |
1508 PIPE_BIND_SCANOUT |
1509 PIPE_BIND_SHARED);
1510 }
1511
1512 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1513 si_is_zs_format_supported(format)) {
1514 retval |= PIPE_BIND_DEPTH_STENCIL;
1515 }
1516
1517 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
1518 si_is_vertex_format_supported(screen, format)) {
1519 retval |= PIPE_BIND_VERTEX_BUFFER;
1520 }
1521
1522 if (usage & PIPE_BIND_TRANSFER_READ)
1523 retval |= PIPE_BIND_TRANSFER_READ;
1524 if (usage & PIPE_BIND_TRANSFER_WRITE)
1525 retval |= PIPE_BIND_TRANSFER_WRITE;
1526
1527 return retval == usage;
1528 }
1529
1530 static unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
1531 {
1532 unsigned tile_mode_index = 0;
1533
1534 if (stencil) {
1535 tile_mode_index = rtex->surface.stencil_tiling_index[level];
1536 } else {
1537 tile_mode_index = rtex->surface.tiling_index[level];
1538 }
1539 return tile_mode_index;
1540 }
1541
1542 /*
1543 * framebuffer handling
1544 */
1545
1546 static void si_cb(struct r600_context *rctx, struct si_pm4_state *pm4,
1547 const struct pipe_framebuffer_state *state, int cb)
1548 {
1549 struct r600_texture *rtex;
1550 struct r600_surface *surf;
1551 unsigned level = state->cbufs[cb]->u.tex.level;
1552 unsigned pitch, slice;
1553 unsigned color_info, color_attrib, color_pitch, color_view;
1554 unsigned tile_mode_index;
1555 unsigned format, swap, ntype, endian;
1556 uint64_t offset;
1557 const struct util_format_description *desc;
1558 int i;
1559 unsigned blend_clamp = 0, blend_bypass = 0;
1560 unsigned max_comp_size;
1561
1562 surf = (struct r600_surface *)state->cbufs[cb];
1563 rtex = (struct r600_texture*)state->cbufs[cb]->texture;
1564
1565 offset = rtex->surface.level[level].offset;
1566
1567 /* Layered rendering doesn't work with LINEAR_GENERAL.
1568 * (LINEAR_ALIGNED and others work) */
1569 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) {
1570 assert(state->cbufs[cb]->u.tex.first_layer == state->cbufs[cb]->u.tex.last_layer);
1571 offset += rtex->surface.level[level].slice_size *
1572 state->cbufs[cb]->u.tex.first_layer;
1573 color_view = 0;
1574 } else {
1575 color_view = S_028C6C_SLICE_START(state->cbufs[cb]->u.tex.first_layer) |
1576 S_028C6C_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer);
1577 }
1578
1579 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1580 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1581 if (slice) {
1582 slice = slice - 1;
1583 }
1584
1585 tile_mode_index = si_tile_mode_index(rtex, level, false);
1586
1587 desc = util_format_description(surf->base.format);
1588 for (i = 0; i < 4; i++) {
1589 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1590 break;
1591 }
1592 }
1593 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1594 ntype = V_028C70_NUMBER_FLOAT;
1595 } else {
1596 ntype = V_028C70_NUMBER_UNORM;
1597 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1598 ntype = V_028C70_NUMBER_SRGB;
1599 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1600 if (desc->channel[i].pure_integer) {
1601 ntype = V_028C70_NUMBER_SINT;
1602 } else {
1603 assert(desc->channel[i].normalized);
1604 ntype = V_028C70_NUMBER_SNORM;
1605 }
1606 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1607 if (desc->channel[i].pure_integer) {
1608 ntype = V_028C70_NUMBER_UINT;
1609 } else {
1610 assert(desc->channel[i].normalized);
1611 ntype = V_028C70_NUMBER_UNORM;
1612 }
1613 }
1614 }
1615
1616 format = si_translate_colorformat(surf->base.format);
1617 if (format == V_028C70_COLOR_INVALID) {
1618 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
1619 }
1620 assert(format != V_028C70_COLOR_INVALID);
1621 swap = si_translate_colorswap(surf->base.format);
1622 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1623 endian = V_028C70_ENDIAN_NONE;
1624 } else {
1625 endian = si_colorformat_endian_swap(format);
1626 }
1627
1628 /* blend clamp should be set for all NORM/SRGB types */
1629 if (ntype == V_028C70_NUMBER_UNORM ||
1630 ntype == V_028C70_NUMBER_SNORM ||
1631 ntype == V_028C70_NUMBER_SRGB)
1632 blend_clamp = 1;
1633
1634 /* set blend bypass according to docs if SINT/UINT or
1635 8/24 COLOR variants */
1636 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1637 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1638 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1639 blend_clamp = 0;
1640 blend_bypass = 1;
1641 }
1642
1643 color_info = S_028C70_FORMAT(format) |
1644 S_028C70_COMP_SWAP(swap) |
1645 S_028C70_BLEND_CLAMP(blend_clamp) |
1646 S_028C70_BLEND_BYPASS(blend_bypass) |
1647 S_028C70_NUMBER_TYPE(ntype) |
1648 S_028C70_ENDIAN(endian);
1649
1650 color_pitch = S_028C64_TILE_MAX(pitch);
1651
1652 color_attrib = S_028C74_TILE_MODE_INDEX(tile_mode_index) |
1653 S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == UTIL_FORMAT_SWIZZLE_1);
1654
1655 if (rtex->resource.b.b.nr_samples > 1) {
1656 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1657
1658 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1659 S_028C74_NUM_FRAGMENTS(log_samples);
1660
1661 if (rtex->fmask.size) {
1662 color_info |= S_028C70_COMPRESSION(1);
1663 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
1664
1665 color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(rtex->fmask.tile_mode_index);
1666
1667 if (rctx->b.chip_class == SI) {
1668 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
1669 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1670 }
1671 if (rctx->b.chip_class >= CIK) {
1672 color_pitch |= S_028C64_FMASK_TILE_MAX(rtex->fmask.pitch / 8 - 1);
1673 }
1674 }
1675 }
1676
1677 if (rtex->cmask.size) {
1678 color_info |= S_028C70_FAST_CLEAR(1);
1679 }
1680
1681 offset += r600_resource_va(rctx->b.b.screen, state->cbufs[cb]->texture);
1682 offset >>= 8;
1683
1684 si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE);
1685 si_pm4_set_reg(pm4, R_028C60_CB_COLOR0_BASE + cb * 0x3C, offset);
1686 si_pm4_set_reg(pm4, R_028C64_CB_COLOR0_PITCH + cb * 0x3C, color_pitch);
1687 si_pm4_set_reg(pm4, R_028C68_CB_COLOR0_SLICE + cb * 0x3C, S_028C68_TILE_MAX(slice));
1688 si_pm4_set_reg(pm4, R_028C6C_CB_COLOR0_VIEW + cb * 0x3C, color_view);
1689 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + cb * 0x3C, color_info);
1690 si_pm4_set_reg(pm4, R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C, color_attrib);
1691
1692 if (rtex->cmask.size) {
1693 si_pm4_set_reg(pm4, R_028C7C_CB_COLOR0_CMASK + cb * 0x3C,
1694 offset + (rtex->cmask.offset >> 8));
1695 si_pm4_set_reg(pm4, R_028C80_CB_COLOR0_CMASK_SLICE + cb * 0x3C,
1696 S_028C80_TILE_MAX(rtex->cmask.slice_tile_max));
1697 }
1698 if (rtex->fmask.size) {
1699 si_pm4_set_reg(pm4, R_028C84_CB_COLOR0_FMASK + cb * 0x3C,
1700 offset + (rtex->fmask.offset >> 8));
1701 si_pm4_set_reg(pm4, R_028C88_CB_COLOR0_FMASK_SLICE + cb * 0x3C,
1702 S_028C88_TILE_MAX(rtex->fmask.slice_tile_max));
1703 }
1704
1705 /* set CB_COLOR1_INFO for possible dual-src blending */
1706 if (state->nr_cbufs == 1) {
1707 assert(cb == 0);
1708 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + 1 * 0x3C, color_info);
1709 }
1710
1711 /* Determine pixel shader export format */
1712 max_comp_size = si_colorformat_max_comp_size(format);
1713 if (ntype == V_028C70_NUMBER_SRGB ||
1714 ((ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM) &&
1715 max_comp_size <= 10) ||
1716 (ntype == V_028C70_NUMBER_FLOAT && max_comp_size <= 16)) {
1717 rctx->export_16bpc |= 1 << cb;
1718 /* set SPI_SHADER_COL_FORMAT for possible dual-src blending */
1719 if (state->nr_cbufs == 1)
1720 rctx->export_16bpc |= 1 << 1;
1721 }
1722 }
1723
1724 static void si_db(struct r600_context *rctx, struct si_pm4_state *pm4,
1725 const struct pipe_framebuffer_state *state)
1726 {
1727 struct r600_screen *rscreen = rctx->screen;
1728 struct r600_texture *rtex;
1729 struct r600_surface *surf;
1730 unsigned level, pitch, slice, format, tile_mode_index, array_mode;
1731 unsigned macro_aspect, tile_split, stile_split, bankh, bankw, nbanks, pipe_config;
1732 uint32_t z_info, s_info, db_depth_info;
1733 uint64_t z_offs, s_offs;
1734 uint32_t db_htile_data_base, db_htile_surface;
1735
1736 if (state->zsbuf == NULL) {
1737 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, S_028040_FORMAT(V_028040_Z_INVALID));
1738 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, S_028044_FORMAT(V_028044_STENCIL_INVALID));
1739 return;
1740 }
1741
1742 surf = (struct r600_surface *)state->zsbuf;
1743 level = surf->base.u.tex.level;
1744 rtex = (struct r600_texture*)surf->base.texture;
1745
1746 format = si_translate_dbformat(rtex->resource.b.b.format);
1747
1748 if (format == V_028040_Z_INVALID) {
1749 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
1750 }
1751 assert(format != V_028040_Z_INVALID);
1752
1753 s_offs = z_offs = r600_resource_va(rctx->b.b.screen, surf->base.texture);
1754 z_offs += rtex->surface.level[level].offset;
1755 s_offs += rtex->surface.stencil_level[level].offset;
1756
1757 z_offs >>= 8;
1758 s_offs >>= 8;
1759
1760 pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
1761 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1762 if (slice) {
1763 slice = slice - 1;
1764 }
1765
1766 db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
1767
1768 z_info = S_028040_FORMAT(format);
1769 if (rtex->resource.b.b.nr_samples > 1) {
1770 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
1771 }
1772
1773 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
1774 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
1775 else
1776 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
1777
1778 if (rctx->b.chip_class >= CIK) {
1779 switch (rtex->surface.level[level].mode) {
1780 case RADEON_SURF_MODE_2D:
1781 array_mode = V_02803C_ARRAY_2D_TILED_THIN1;
1782 break;
1783 case RADEON_SURF_MODE_1D:
1784 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1785 case RADEON_SURF_MODE_LINEAR:
1786 default:
1787 array_mode = V_02803C_ARRAY_1D_TILED_THIN1;
1788 break;
1789 }
1790 tile_split = rtex->surface.tile_split;
1791 stile_split = rtex->surface.stencil_tile_split;
1792 macro_aspect = rtex->surface.mtilea;
1793 bankw = rtex->surface.bankw;
1794 bankh = rtex->surface.bankh;
1795 tile_split = cik_tile_split(tile_split);
1796 stile_split = cik_tile_split(stile_split);
1797 macro_aspect = cik_macro_tile_aspect(macro_aspect);
1798 bankw = cik_bank_wh(bankw);
1799 bankh = cik_bank_wh(bankh);
1800 nbanks = cik_num_banks(rscreen->b.tiling_info.num_banks);
1801 pipe_config = cik_db_pipe_config(rscreen->b.info.r600_num_tile_pipes,
1802 rscreen->b.info.r600_num_backends);
1803
1804 db_depth_info |= S_02803C_ARRAY_MODE(array_mode) |
1805 S_02803C_PIPE_CONFIG(pipe_config) |
1806 S_02803C_BANK_WIDTH(bankw) |
1807 S_02803C_BANK_HEIGHT(bankh) |
1808 S_02803C_MACRO_TILE_ASPECT(macro_aspect) |
1809 S_02803C_NUM_BANKS(nbanks);
1810 z_info |= S_028040_TILE_SPLIT(tile_split);
1811 s_info |= S_028044_TILE_SPLIT(stile_split);
1812 } else {
1813 tile_mode_index = si_tile_mode_index(rtex, level, false);
1814 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
1815 tile_mode_index = si_tile_mode_index(rtex, level, true);
1816 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
1817 }
1818
1819 /* HiZ aka depth buffer htile */
1820 /* use htile only for first level */
1821 if (rtex->htile_buffer && !level) {
1822 z_info |= S_028040_TILE_SURFACE_ENABLE(1);
1823
1824 /* This is optimal for the clear value of 1.0 and using
1825 * the LESS and LEQUAL test functions. Set this to 0
1826 * for the opposite case. This can only be changed when
1827 * clearing. */
1828 z_info |= S_028040_ZRANGE_PRECISION(1);
1829
1830 uint64_t va = r600_resource_va(&rctx->screen->b.b, &rtex->htile_buffer->b.b);
1831 db_htile_data_base = va >> 8;
1832 db_htile_surface = S_028ABC_FULL_CACHE(1);
1833
1834 si_pm4_add_bo(pm4, rtex->htile_buffer, RADEON_USAGE_READWRITE);
1835 } else {
1836 db_htile_data_base = 0;
1837 db_htile_surface = 0;
1838 }
1839
1840 si_pm4_set_reg(pm4, R_028008_DB_DEPTH_VIEW,
1841 S_028008_SLICE_START(state->zsbuf->u.tex.first_layer) |
1842 S_028008_SLICE_MAX(state->zsbuf->u.tex.last_layer));
1843 si_pm4_set_reg(pm4, R_028014_DB_HTILE_DATA_BASE, db_htile_data_base);
1844
1845 si_pm4_set_reg(pm4, R_02803C_DB_DEPTH_INFO, db_depth_info);
1846 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, z_info);
1847 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, s_info);
1848
1849 si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE);
1850 si_pm4_set_reg(pm4, R_028048_DB_Z_READ_BASE, z_offs);
1851 si_pm4_set_reg(pm4, R_02804C_DB_STENCIL_READ_BASE, s_offs);
1852 si_pm4_set_reg(pm4, R_028050_DB_Z_WRITE_BASE, z_offs);
1853 si_pm4_set_reg(pm4, R_028054_DB_STENCIL_WRITE_BASE, s_offs);
1854
1855 si_pm4_set_reg(pm4, R_028058_DB_DEPTH_SIZE, S_028058_PITCH_TILE_MAX(pitch));
1856 si_pm4_set_reg(pm4, R_02805C_DB_DEPTH_SLICE, S_02805C_SLICE_TILE_MAX(slice));
1857
1858 si_pm4_set_reg(pm4, R_028ABC_DB_HTILE_SURFACE, db_htile_surface);
1859 }
1860
1861 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1862 (((s0x) & 0xf) | (((s0y) & 0xf) << 4) | \
1863 (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) | \
1864 (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) | \
1865 (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
1866
1867 /* 2xMSAA
1868 * There are two locations (-4, 4), (4, -4). */
1869 static uint32_t sample_locs_2x[] = {
1870 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1871 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1872 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1873 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1874 };
1875 static unsigned max_dist_2x = 4;
1876 /* 4xMSAA
1877 * There are 4 locations: (-2, -2), (2, 2), (-6, 6), (6, -6). */
1878 static uint32_t sample_locs_4x[] = {
1879 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1880 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1881 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1882 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1883 };
1884 static unsigned max_dist_4x = 6;
1885 /* Cayman/SI 8xMSAA */
1886 static uint32_t cm_sample_locs_8x[] = {
1887 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1888 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1889 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1890 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1891 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1892 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1893 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1894 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1895 };
1896 static unsigned cm_max_dist_8x = 8;
1897 /* Cayman/SI 16xMSAA */
1898 static uint32_t cm_sample_locs_16x[] = {
1899 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1900 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1901 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1902 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1903 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1904 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1905 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1906 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1907 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1908 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1909 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1910 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1911 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1912 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1913 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1914 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1915 };
1916 static unsigned cm_max_dist_16x = 8;
1917
1918 static void si_get_sample_position(struct pipe_context *ctx,
1919 unsigned sample_count,
1920 unsigned sample_index,
1921 float *out_value)
1922 {
1923 int offset, index;
1924 struct {
1925 int idx:4;
1926 } val;
1927 switch (sample_count) {
1928 case 1:
1929 default:
1930 out_value[0] = out_value[1] = 0.5;
1931 break;
1932 case 2:
1933 offset = 4 * (sample_index * 2);
1934 val.idx = (sample_locs_2x[0] >> offset) & 0xf;
1935 out_value[0] = (float)(val.idx + 8) / 16.0f;
1936 val.idx = (sample_locs_2x[0] >> (offset + 4)) & 0xf;
1937 out_value[1] = (float)(val.idx + 8) / 16.0f;
1938 break;
1939 case 4:
1940 offset = 4 * (sample_index * 2);
1941 val.idx = (sample_locs_4x[0] >> offset) & 0xf;
1942 out_value[0] = (float)(val.idx + 8) / 16.0f;
1943 val.idx = (sample_locs_4x[0] >> (offset + 4)) & 0xf;
1944 out_value[1] = (float)(val.idx + 8) / 16.0f;
1945 break;
1946 case 8:
1947 offset = 4 * (sample_index % 4 * 2);
1948 index = (sample_index / 4) * 4;
1949 val.idx = (cm_sample_locs_8x[index] >> offset) & 0xf;
1950 out_value[0] = (float)(val.idx + 8) / 16.0f;
1951 val.idx = (cm_sample_locs_8x[index] >> (offset + 4)) & 0xf;
1952 out_value[1] = (float)(val.idx + 8) / 16.0f;
1953 break;
1954 case 16:
1955 offset = 4 * (sample_index % 4 * 2);
1956 index = (sample_index / 4) * 4;
1957 val.idx = (cm_sample_locs_16x[index] >> offset) & 0xf;
1958 out_value[0] = (float)(val.idx + 8) / 16.0f;
1959 val.idx = (cm_sample_locs_16x[index] >> (offset + 4)) & 0xf;
1960 out_value[1] = (float)(val.idx + 8) / 16.0f;
1961 break;
1962 }
1963 }
1964
1965 static void si_set_msaa_state(struct r600_context *rctx, struct si_pm4_state *pm4, int nr_samples)
1966 {
1967 unsigned max_dist = 0;
1968
1969 switch (nr_samples) {
1970 default:
1971 nr_samples = 0;
1972 break;
1973 case 2:
1974 si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_2x[0]);
1975 si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_2x[1]);
1976 si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_2x[2]);
1977 si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_2x[3]);
1978 max_dist = max_dist_2x;
1979 break;
1980 case 4:
1981 si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_4x[0]);
1982 si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_4x[1]);
1983 si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_4x[2]);
1984 si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_4x[3]);
1985 max_dist = max_dist_4x;
1986 break;
1987 case 8:
1988 si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, cm_sample_locs_8x[0]);
1989 si_pm4_set_reg(pm4, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, cm_sample_locs_8x[4]);
1990 si_pm4_set_reg(pm4, R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2, 0);
1991 si_pm4_set_reg(pm4, R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3, 0);
1992 si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, cm_sample_locs_8x[1]);
1993 si_pm4_set_reg(pm4, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, cm_sample_locs_8x[5]);
1994 si_pm4_set_reg(pm4, R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2, 0);
1995 si_pm4_set_reg(pm4, R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3, 0);
1996 si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, cm_sample_locs_8x[2]);
1997 si_pm4_set_reg(pm4, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, cm_sample_locs_8x[6]);
1998 si_pm4_set_reg(pm4, R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2, 0);
1999 si_pm4_set_reg(pm4, R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3, 0);
2000 si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, cm_sample_locs_8x[3]);
2001 si_pm4_set_reg(pm4, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, cm_sample_locs_8x[7]);
2002 max_dist = cm_max_dist_8x;
2003 break;
2004 case 16:
2005 si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, cm_sample_locs_16x[0]);
2006 si_pm4_set_reg(pm4, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, cm_sample_locs_16x[4]);
2007 si_pm4_set_reg(pm4, R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2, cm_sample_locs_16x[8]);
2008 si_pm4_set_reg(pm4, R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3, cm_sample_locs_16x[12]);
2009 si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, cm_sample_locs_16x[1]);
2010 si_pm4_set_reg(pm4, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, cm_sample_locs_16x[5]);
2011 si_pm4_set_reg(pm4, R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2, cm_sample_locs_16x[9]);
2012 si_pm4_set_reg(pm4, R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3, cm_sample_locs_16x[13]);
2013 si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, cm_sample_locs_16x[2]);
2014 si_pm4_set_reg(pm4, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, cm_sample_locs_16x[6]);
2015 si_pm4_set_reg(pm4, R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2, cm_sample_locs_16x[10]);
2016 si_pm4_set_reg(pm4, R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3, cm_sample_locs_16x[14]);
2017 si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, cm_sample_locs_16x[3]);
2018 si_pm4_set_reg(pm4, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, cm_sample_locs_16x[7]);
2019 si_pm4_set_reg(pm4, R_028C30_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2, cm_sample_locs_16x[11]);
2020 si_pm4_set_reg(pm4, R_028C34_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3, cm_sample_locs_16x[15]);
2021 max_dist = cm_max_dist_16x;
2022 break;
2023 }
2024
2025 if (nr_samples > 1) {
2026 unsigned log_samples = util_logbase2(nr_samples);
2027
2028 si_pm4_set_reg(pm4, R_028BDC_PA_SC_LINE_CNTL,
2029 S_028BDC_LAST_PIXEL(1) |
2030 S_028BDC_EXPAND_LINE_WIDTH(1));
2031 si_pm4_set_reg(pm4, R_028BE0_PA_SC_AA_CONFIG,
2032 S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
2033 S_028BE0_MAX_SAMPLE_DIST(max_dist) |
2034 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples));
2035
2036 si_pm4_set_reg(pm4, R_028804_DB_EQAA,
2037 S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
2038 S_028804_PS_ITER_SAMPLES(log_samples) |
2039 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
2040 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples) |
2041 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
2042 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
2043 } else {
2044 si_pm4_set_reg(pm4, R_028BDC_PA_SC_LINE_CNTL, S_028BDC_LAST_PIXEL(1));
2045 si_pm4_set_reg(pm4, R_028BE0_PA_SC_AA_CONFIG, 0);
2046
2047 si_pm4_set_reg(pm4, R_028804_DB_EQAA,
2048 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
2049 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
2050 }
2051 }
2052
2053 static void si_set_framebuffer_state(struct pipe_context *ctx,
2054 const struct pipe_framebuffer_state *state)
2055 {
2056 struct r600_context *rctx = (struct r600_context *)ctx;
2057 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
2058 uint32_t tl, br;
2059 int tl_x, tl_y, br_x, br_y, nr_samples, i;
2060
2061 if (pm4 == NULL)
2062 return;
2063
2064 if (rctx->framebuffer.nr_cbufs) {
2065 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB |
2066 R600_CONTEXT_FLUSH_AND_INV_CB_META;
2067 }
2068 if (rctx->framebuffer.zsbuf) {
2069 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB |
2070 R600_CONTEXT_FLUSH_AND_INV_DB_META;
2071 }
2072
2073 util_copy_framebuffer_state(&rctx->framebuffer, state);
2074
2075 /* build states */
2076 rctx->export_16bpc = 0;
2077 rctx->fb_compressed_cb_mask = 0;
2078 for (i = 0; i < state->nr_cbufs; i++) {
2079 struct r600_texture *rtex =
2080 (struct r600_texture*)state->cbufs[i]->texture;
2081
2082 si_cb(rctx, pm4, state, i);
2083
2084 if (rtex->fmask.size || rtex->cmask.size) {
2085 rctx->fb_compressed_cb_mask |= 1 << i;
2086 }
2087 }
2088 for (; i < 8; i++) {
2089 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2090 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2091 }
2092
2093 assert(!(rctx->export_16bpc & ~0xff));
2094 si_db(rctx, pm4, state);
2095
2096 tl_x = 0;
2097 tl_y = 0;
2098 br_x = state->width;
2099 br_y = state->height;
2100
2101 tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
2102 br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
2103
2104 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, tl);
2105 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR, br);
2106 si_pm4_set_reg(pm4, R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl);
2107 si_pm4_set_reg(pm4, R_028254_PA_SC_VPORT_SCISSOR_0_BR, br);
2108 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, tl);
2109 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR, br);
2110 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, tl);
2111 si_pm4_set_reg(pm4, R_028208_PA_SC_WINDOW_SCISSOR_BR, br);
2112
2113 if (state->nr_cbufs)
2114 nr_samples = state->cbufs[0]->texture->nr_samples;
2115 else if (state->zsbuf)
2116 nr_samples = state->zsbuf->texture->nr_samples;
2117 else
2118 nr_samples = 0;
2119
2120 si_set_msaa_state(rctx, pm4, nr_samples);
2121 rctx->fb_log_samples = util_logbase2(nr_samples);
2122 rctx->fb_cb0_is_integer = state->nr_cbufs &&
2123 util_format_is_pure_integer(state->cbufs[0]->format);
2124
2125 si_pm4_set_state(rctx, framebuffer, pm4);
2126 si_update_fb_rs_state(rctx);
2127 si_update_fb_blend_state(rctx);
2128 }
2129
2130 /*
2131 * shaders
2132 */
2133
2134 /* Compute the key for the hw shader variant */
2135 static INLINE void si_shader_selector_key(struct pipe_context *ctx,
2136 struct si_pipe_shader_selector *sel,
2137 union si_shader_key *key)
2138 {
2139 struct r600_context *rctx = (struct r600_context *)ctx;
2140 memset(key, 0, sizeof(*key));
2141
2142 if (sel->type == PIPE_SHADER_VERTEX) {
2143 unsigned i;
2144 if (!rctx->vertex_elements)
2145 return;
2146
2147 for (i = 0; i < rctx->vertex_elements->count; ++i)
2148 key->vs.instance_divisors[i] = rctx->vertex_elements->elements[i].instance_divisor;
2149
2150 if (rctx->queued.named.rasterizer->clip_plane_enable & 0xf0)
2151 key->vs.ucps_enabled |= 0x2;
2152 if (rctx->queued.named.rasterizer->clip_plane_enable & 0xf)
2153 key->vs.ucps_enabled |= 0x1;
2154 } else if (sel->type == PIPE_SHADER_FRAGMENT) {
2155 if (sel->fs_write_all)
2156 key->ps.nr_cbufs = rctx->framebuffer.nr_cbufs;
2157 key->ps.export_16bpc = rctx->export_16bpc;
2158
2159 if (rctx->queued.named.rasterizer) {
2160 key->ps.color_two_side = rctx->queued.named.rasterizer->two_side;
2161 key->ps.flatshade = rctx->queued.named.rasterizer->flatshade;
2162
2163 if (rctx->queued.named.blend) {
2164 key->ps.alpha_to_one = rctx->queued.named.blend->alpha_to_one &&
2165 rctx->queued.named.rasterizer->multisample_enable &&
2166 !rctx->fb_cb0_is_integer;
2167 }
2168 }
2169 if (rctx->queued.named.dsa) {
2170 key->ps.alpha_func = rctx->queued.named.dsa->alpha_func;
2171
2172 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
2173 if (rctx->framebuffer.nr_cbufs &&
2174 rctx->framebuffer.cbufs[0] &&
2175 util_format_is_pure_integer(rctx->framebuffer.cbufs[0]->texture->format))
2176 key->ps.alpha_func = PIPE_FUNC_ALWAYS;
2177 } else {
2178 key->ps.alpha_func = PIPE_FUNC_ALWAYS;
2179 }
2180 }
2181 }
2182
2183 /* Select the hw shader variant depending on the current state.
2184 * (*dirty) is set to 1 if current variant was changed */
2185 int si_shader_select(struct pipe_context *ctx,
2186 struct si_pipe_shader_selector *sel,
2187 unsigned *dirty)
2188 {
2189 union si_shader_key key;
2190 struct si_pipe_shader * shader = NULL;
2191 int r;
2192
2193 si_shader_selector_key(ctx, sel, &key);
2194
2195 /* Check if we don't need to change anything.
2196 * This path is also used for most shaders that don't need multiple
2197 * variants, it will cost just a computation of the key and this
2198 * test. */
2199 if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
2200 return 0;
2201 }
2202
2203 /* lookup if we have other variants in the list */
2204 if (sel->num_shaders > 1) {
2205 struct si_pipe_shader *p = sel->current, *c = p->next_variant;
2206
2207 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
2208 p = c;
2209 c = c->next_variant;
2210 }
2211
2212 if (c) {
2213 p->next_variant = c->next_variant;
2214 shader = c;
2215 }
2216 }
2217
2218 if (unlikely(!shader)) {
2219 shader = CALLOC(1, sizeof(struct si_pipe_shader));
2220 shader->selector = sel;
2221 shader->key = key;
2222
2223 r = si_pipe_shader_create(ctx, shader);
2224 if (unlikely(r)) {
2225 R600_ERR("Failed to build shader variant (type=%u) %d\n",
2226 sel->type, r);
2227 sel->current = NULL;
2228 FREE(shader);
2229 return r;
2230 }
2231 sel->num_shaders++;
2232 }
2233
2234 if (dirty)
2235 *dirty = 1;
2236
2237 shader->next_variant = sel->current;
2238 sel->current = shader;
2239
2240 return 0;
2241 }
2242
2243 static void *si_create_shader_state(struct pipe_context *ctx,
2244 const struct pipe_shader_state *state,
2245 unsigned pipe_shader_type)
2246 {
2247 struct si_pipe_shader_selector *sel = CALLOC_STRUCT(si_pipe_shader_selector);
2248 int r;
2249
2250 sel->type = pipe_shader_type;
2251 sel->tokens = tgsi_dup_tokens(state->tokens);
2252 sel->so = state->stream_output;
2253
2254 if (pipe_shader_type == PIPE_SHADER_FRAGMENT) {
2255 struct tgsi_shader_info info;
2256
2257 tgsi_scan_shader(state->tokens, &info);
2258 sel->fs_write_all = info.color0_writes_all_cbufs;
2259 }
2260
2261 r = si_shader_select(ctx, sel, NULL);
2262 if (r) {
2263 free(sel);
2264 return NULL;
2265 }
2266
2267 return sel;
2268 }
2269
2270 static void *si_create_fs_state(struct pipe_context *ctx,
2271 const struct pipe_shader_state *state)
2272 {
2273 return si_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
2274 }
2275
2276 static void *si_create_vs_state(struct pipe_context *ctx,
2277 const struct pipe_shader_state *state)
2278 {
2279 return si_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
2280 }
2281
2282 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
2283 {
2284 struct r600_context *rctx = (struct r600_context *)ctx;
2285 struct si_pipe_shader_selector *sel = state;
2286
2287 if (rctx->vs_shader == sel)
2288 return;
2289
2290 if (!sel || !sel->current)
2291 return;
2292
2293 rctx->vs_shader = sel;
2294 si_pm4_bind_state(rctx, vs, sel->current->pm4);
2295 rctx->b.streamout.stride_in_dw = sel->so.stride;
2296 rctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE;
2297 }
2298
2299 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
2300 {
2301 struct r600_context *rctx = (struct r600_context *)ctx;
2302 struct si_pipe_shader_selector *sel = state;
2303
2304 if (rctx->ps_shader == sel)
2305 return;
2306
2307 if (!sel || !sel->current)
2308 sel = rctx->dummy_pixel_shader;
2309
2310 rctx->ps_shader = sel;
2311 si_pm4_bind_state(rctx, ps, sel->current->pm4);
2312 rctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE;
2313 }
2314
2315 static void si_delete_shader_selector(struct pipe_context *ctx,
2316 struct si_pipe_shader_selector *sel)
2317 {
2318 struct r600_context *rctx = (struct r600_context *)ctx;
2319 struct si_pipe_shader *p = sel->current, *c;
2320
2321 while (p) {
2322 c = p->next_variant;
2323 si_pm4_delete_state(rctx, vs, p->pm4);
2324 si_pipe_shader_destroy(ctx, p);
2325 free(p);
2326 p = c;
2327 }
2328
2329 free(sel->tokens);
2330 free(sel);
2331 }
2332
2333 static void si_delete_vs_shader(struct pipe_context *ctx, void *state)
2334 {
2335 struct r600_context *rctx = (struct r600_context *)ctx;
2336 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state;
2337
2338 if (rctx->vs_shader == sel) {
2339 rctx->vs_shader = NULL;
2340 }
2341
2342 si_delete_shader_selector(ctx, sel);
2343 }
2344
2345 static void si_delete_ps_shader(struct pipe_context *ctx, void *state)
2346 {
2347 struct r600_context *rctx = (struct r600_context *)ctx;
2348 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state;
2349
2350 if (rctx->ps_shader == sel) {
2351 rctx->ps_shader = NULL;
2352 }
2353
2354 si_delete_shader_selector(ctx, sel);
2355 }
2356
2357 /*
2358 * Samplers
2359 */
2360
2361 static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx,
2362 struct pipe_resource *texture,
2363 const struct pipe_sampler_view *state)
2364 {
2365 struct si_pipe_sampler_view *view = CALLOC_STRUCT(si_pipe_sampler_view);
2366 struct r600_texture *tmp = (struct r600_texture*)texture;
2367 const struct util_format_description *desc;
2368 unsigned format, num_format;
2369 uint32_t pitch = 0;
2370 unsigned char state_swizzle[4], swizzle[4];
2371 unsigned height, depth, width;
2372 enum pipe_format pipe_format = state->format;
2373 struct radeon_surface_level *surflevel;
2374 int first_non_void;
2375 uint64_t va;
2376
2377 if (view == NULL)
2378 return NULL;
2379
2380 /* initialize base object */
2381 view->base = *state;
2382 view->base.texture = NULL;
2383 pipe_resource_reference(&view->base.texture, texture);
2384 view->base.reference.count = 1;
2385 view->base.context = ctx;
2386 view->resource = &tmp->resource;
2387
2388 /* Buffer resource. */
2389 if (texture->target == PIPE_BUFFER) {
2390 unsigned stride;
2391
2392 desc = util_format_description(state->format);
2393 first_non_void = util_format_get_first_non_void_channel(state->format);
2394 stride = desc->block.bits / 8;
2395 va = r600_resource_va(ctx->screen, texture) + state->u.buf.first_element*stride;
2396 format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
2397 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
2398
2399 view->state[0] = va;
2400 view->state[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
2401 S_008F04_STRIDE(stride);
2402 view->state[2] = state->u.buf.last_element + 1 - state->u.buf.first_element;
2403 view->state[3] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2404 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2405 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2406 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2407 S_008F0C_NUM_FORMAT(num_format) |
2408 S_008F0C_DATA_FORMAT(format);
2409 return &view->base;
2410 }
2411
2412 state_swizzle[0] = state->swizzle_r;
2413 state_swizzle[1] = state->swizzle_g;
2414 state_swizzle[2] = state->swizzle_b;
2415 state_swizzle[3] = state->swizzle_a;
2416
2417 surflevel = tmp->surface.level;
2418
2419 /* Texturing with separate depth and stencil. */
2420 if (tmp->is_depth && !tmp->is_flushing_texture) {
2421 switch (pipe_format) {
2422 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2423 pipe_format = PIPE_FORMAT_Z32_FLOAT;
2424 break;
2425 case PIPE_FORMAT_X8Z24_UNORM:
2426 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2427 /* Z24 is always stored like this. */
2428 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
2429 break;
2430 case PIPE_FORMAT_X24S8_UINT:
2431 case PIPE_FORMAT_S8X24_UINT:
2432 case PIPE_FORMAT_X32_S8X24_UINT:
2433 pipe_format = PIPE_FORMAT_S8_UINT;
2434 surflevel = tmp->surface.stencil_level;
2435 break;
2436 default:;
2437 }
2438 }
2439
2440 desc = util_format_description(pipe_format);
2441
2442 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2443 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2444 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2445
2446 switch (pipe_format) {
2447 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2448 case PIPE_FORMAT_X24S8_UINT:
2449 case PIPE_FORMAT_X32_S8X24_UINT:
2450 case PIPE_FORMAT_X8Z24_UNORM:
2451 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
2452 break;
2453 default:
2454 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
2455 }
2456 } else {
2457 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2458 }
2459
2460 first_non_void = util_format_get_first_non_void_channel(pipe_format);
2461
2462 switch (pipe_format) {
2463 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2464 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2465 break;
2466 default:
2467 if (first_non_void < 0) {
2468 if (util_format_is_compressed(pipe_format)) {
2469 switch (pipe_format) {
2470 case PIPE_FORMAT_DXT1_SRGB:
2471 case PIPE_FORMAT_DXT1_SRGBA:
2472 case PIPE_FORMAT_DXT3_SRGBA:
2473 case PIPE_FORMAT_DXT5_SRGBA:
2474 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2475 break;
2476 case PIPE_FORMAT_RGTC1_SNORM:
2477 case PIPE_FORMAT_LATC1_SNORM:
2478 case PIPE_FORMAT_RGTC2_SNORM:
2479 case PIPE_FORMAT_LATC2_SNORM:
2480 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2481 break;
2482 default:
2483 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2484 break;
2485 }
2486 } else {
2487 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2488 }
2489 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
2490 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2491 } else {
2492 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2493
2494 switch (desc->channel[first_non_void].type) {
2495 case UTIL_FORMAT_TYPE_FLOAT:
2496 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2497 break;
2498 case UTIL_FORMAT_TYPE_SIGNED:
2499 if (desc->channel[first_non_void].normalized)
2500 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2501 else if (desc->channel[first_non_void].pure_integer)
2502 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
2503 else
2504 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
2505 break;
2506 case UTIL_FORMAT_TYPE_UNSIGNED:
2507 if (desc->channel[first_non_void].normalized)
2508 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2509 else if (desc->channel[first_non_void].pure_integer)
2510 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
2511 else
2512 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
2513 }
2514 }
2515 }
2516
2517 format = si_translate_texformat(ctx->screen, pipe_format, desc, first_non_void);
2518 if (format == ~0) {
2519 format = 0;
2520 }
2521
2522 /* not supported any more */
2523 //endian = si_colorformat_endian_swap(format);
2524
2525 width = surflevel[0].npix_x;
2526 height = surflevel[0].npix_y;
2527 depth = surflevel[0].npix_z;
2528 pitch = surflevel[0].nblk_x * util_format_get_blockwidth(pipe_format);
2529
2530 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
2531 height = 1;
2532 depth = texture->array_size;
2533 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
2534 depth = texture->array_size;
2535 }
2536
2537 va = r600_resource_va(ctx->screen, texture);
2538 va += surflevel[0].offset;
2539 va += tmp->mipmap_shift * surflevel[texture->last_level].slice_size;
2540 view->state[0] = va >> 8;
2541 view->state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) |
2542 S_008F14_DATA_FORMAT(format) |
2543 S_008F14_NUM_FORMAT(num_format));
2544 view->state[2] = (S_008F18_WIDTH(width - 1) |
2545 S_008F18_HEIGHT(height - 1));
2546 view->state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2547 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2548 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2549 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2550 S_008F1C_BASE_LEVEL(texture->nr_samples > 1 ?
2551 0 : state->u.tex.first_level - tmp->mipmap_shift) |
2552 S_008F1C_LAST_LEVEL(texture->nr_samples > 1 ?
2553 util_logbase2(texture->nr_samples) :
2554 state->u.tex.last_level - tmp->mipmap_shift) |
2555 S_008F1C_TILING_INDEX(si_tile_mode_index(tmp, 0, false)) |
2556 S_008F1C_POW2_PAD(texture->last_level > 0) |
2557 S_008F1C_TYPE(si_tex_dim(texture->target, texture->nr_samples)));
2558 view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
2559 view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2560 S_008F24_LAST_ARRAY(state->u.tex.last_layer));
2561 view->state[6] = 0;
2562 view->state[7] = 0;
2563
2564 /* Initialize the sampler view for FMASK. */
2565 if (tmp->fmask.size) {
2566 uint64_t va = r600_resource_va(ctx->screen, texture) + tmp->fmask.offset;
2567 uint32_t fmask_format;
2568
2569 switch (texture->nr_samples) {
2570 case 2:
2571 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
2572 break;
2573 case 4:
2574 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
2575 break;
2576 case 8:
2577 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
2578 break;
2579 default:
2580 assert(0);
2581 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
2582 }
2583
2584 view->fmask_state[0] = va >> 8;
2585 view->fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
2586 S_008F14_DATA_FORMAT(fmask_format) |
2587 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT);
2588 view->fmask_state[2] = S_008F18_WIDTH(width - 1) |
2589 S_008F18_HEIGHT(height - 1);
2590 view->fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
2591 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
2592 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
2593 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
2594 S_008F1C_TILING_INDEX(tmp->fmask.tile_mode_index) |
2595 S_008F1C_TYPE(si_tex_dim(texture->target, 0));
2596 view->fmask_state[4] = S_008F20_DEPTH(depth - 1) |
2597 S_008F20_PITCH(tmp->fmask.pitch - 1);
2598 view->fmask_state[5] = S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2599 S_008F24_LAST_ARRAY(state->u.tex.last_layer);
2600 view->fmask_state[6] = 0;
2601 view->fmask_state[7] = 0;
2602 }
2603
2604 return &view->base;
2605 }
2606
2607 static void si_sampler_view_destroy(struct pipe_context *ctx,
2608 struct pipe_sampler_view *state)
2609 {
2610 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
2611
2612 pipe_resource_reference(&state->texture, NULL);
2613 FREE(resource);
2614 }
2615
2616 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
2617 {
2618 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
2619 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
2620 (linear_filter &&
2621 (wrap == PIPE_TEX_WRAP_CLAMP ||
2622 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
2623 }
2624
2625 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
2626 {
2627 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
2628 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
2629
2630 return (state->border_color.ui[0] || state->border_color.ui[1] ||
2631 state->border_color.ui[2] || state->border_color.ui[3]) &&
2632 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
2633 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
2634 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
2635 }
2636
2637 static void *si_create_sampler_state(struct pipe_context *ctx,
2638 const struct pipe_sampler_state *state)
2639 {
2640 struct si_pipe_sampler_state *rstate = CALLOC_STRUCT(si_pipe_sampler_state);
2641 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
2642 unsigned border_color_type;
2643
2644 if (rstate == NULL) {
2645 return NULL;
2646 }
2647
2648 if (sampler_state_needs_border_color(state))
2649 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
2650 else
2651 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
2652
2653 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
2654 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
2655 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
2656 (state->max_anisotropy & 0x7) << 9 | /* XXX */
2657 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
2658 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
2659 aniso_flag_offset << 16 | /* XXX */
2660 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map));
2661 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
2662 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
2663 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
2664 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter)) |
2665 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter)) |
2666 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)));
2667 rstate->val[3] = S_008F3C_BORDER_COLOR_TYPE(border_color_type);
2668
2669 if (border_color_type == V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2670 memcpy(rstate->border_color, state->border_color.ui,
2671 sizeof(rstate->border_color));
2672 }
2673
2674 return rstate;
2675 }
2676
2677 /* XXX consider moving this function to si_descriptors.c for gcc to inline
2678 * the si_set_sampler_view calls. LTO might help too. */
2679 static void si_set_sampler_views(struct pipe_context *ctx,
2680 unsigned shader, unsigned start,
2681 unsigned count,
2682 struct pipe_sampler_view **views)
2683 {
2684 struct r600_context *rctx = (struct r600_context *)ctx;
2685 struct r600_textures_info *samplers = &rctx->samplers[shader];
2686 struct si_pipe_sampler_view **rviews = (struct si_pipe_sampler_view **)views;
2687 int i;
2688
2689 if (shader != PIPE_SHADER_VERTEX && shader != PIPE_SHADER_FRAGMENT)
2690 return;
2691
2692 assert(start == 0);
2693
2694 for (i = 0; i < count; i++) {
2695 if (!views[i]) {
2696 samplers->depth_texture_mask &= ~(1 << i);
2697 samplers->compressed_colortex_mask &= ~(1 << i);
2698 si_set_sampler_view(rctx, shader, i, NULL, NULL);
2699 si_set_sampler_view(rctx, shader, FMASK_TEX_OFFSET + i,
2700 NULL, NULL);
2701 continue;
2702 }
2703
2704 si_set_sampler_view(rctx, shader, i, views[i], rviews[i]->state);
2705
2706 if (views[i]->texture->target != PIPE_BUFFER) {
2707 struct r600_texture *rtex =
2708 (struct r600_texture*)views[i]->texture;
2709
2710 if (rtex->is_depth && !rtex->is_flushing_texture) {
2711 samplers->depth_texture_mask |= 1 << i;
2712 } else {
2713 samplers->depth_texture_mask &= ~(1 << i);
2714 }
2715 if (rtex->cmask.size || rtex->fmask.size) {
2716 samplers->compressed_colortex_mask |= 1 << i;
2717 } else {
2718 samplers->compressed_colortex_mask &= ~(1 << i);
2719 }
2720
2721 if (rtex->fmask.size) {
2722 si_set_sampler_view(rctx, shader, FMASK_TEX_OFFSET + i,
2723 views[i], rviews[i]->fmask_state);
2724 } else {
2725 si_set_sampler_view(rctx, shader, FMASK_TEX_OFFSET + i,
2726 NULL, NULL);
2727 }
2728 }
2729 }
2730 for (; i < samplers->n_views; i++) {
2731 samplers->depth_texture_mask &= ~(1 << i);
2732 samplers->compressed_colortex_mask &= ~(1 << i);
2733 si_set_sampler_view(rctx, shader, i, NULL, NULL);
2734 si_set_sampler_view(rctx, shader, FMASK_TEX_OFFSET + i,
2735 NULL, NULL);
2736 }
2737
2738 samplers->n_views = count;
2739 rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE;
2740 }
2741
2742 static struct si_pm4_state *si_set_sampler_states(struct r600_context *rctx, unsigned count,
2743 void **states,
2744 struct r600_textures_info *samplers,
2745 unsigned user_data_reg)
2746 {
2747 struct si_pipe_sampler_state **rstates = (struct si_pipe_sampler_state **)states;
2748 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
2749 uint32_t *border_color_table = NULL;
2750 int i, j;
2751
2752 if (!count)
2753 goto out;
2754
2755 rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE;
2756
2757 si_pm4_sh_data_begin(pm4);
2758 for (i = 0; i < count; i++) {
2759 if (rstates[i] &&
2760 G_008F3C_BORDER_COLOR_TYPE(rstates[i]->val[3]) ==
2761 V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2762 if (!rctx->border_color_table ||
2763 ((rctx->border_color_offset + count - i) &
2764 C_008F3C_BORDER_COLOR_PTR)) {
2765 r600_resource_reference(&rctx->border_color_table, NULL);
2766 rctx->border_color_offset = 0;
2767
2768 rctx->border_color_table =
2769 r600_resource_create_custom(&rctx->screen->b.b,
2770 PIPE_USAGE_STAGING,
2771 4096 * 4 * 4);
2772 }
2773
2774 if (!border_color_table) {
2775 border_color_table =
2776 rctx->b.ws->buffer_map(rctx->border_color_table->cs_buf,
2777 rctx->b.rings.gfx.cs,
2778 PIPE_TRANSFER_WRITE |
2779 PIPE_TRANSFER_UNSYNCHRONIZED);
2780 }
2781
2782 for (j = 0; j < 4; j++) {
2783 border_color_table[4 * rctx->border_color_offset + j] =
2784 util_le32_to_cpu(rstates[i]->border_color[j]);
2785 }
2786
2787 rstates[i]->val[3] &= C_008F3C_BORDER_COLOR_PTR;
2788 rstates[i]->val[3] |= S_008F3C_BORDER_COLOR_PTR(rctx->border_color_offset++);
2789 }
2790
2791 for (j = 0; j < Elements(rstates[i]->val); ++j) {
2792 si_pm4_sh_data_add(pm4, rstates[i] ? rstates[i]->val[j] : 0);
2793 }
2794 }
2795 si_pm4_sh_data_end(pm4, user_data_reg, SI_SGPR_SAMPLER);
2796
2797 if (border_color_table) {
2798 uint64_t va_offset =
2799 r600_resource_va(&rctx->screen->b.b,
2800 (void*)rctx->border_color_table);
2801
2802 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, va_offset >> 8);
2803 if (rctx->b.chip_class >= CIK)
2804 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, va_offset >> 40);
2805 rctx->b.ws->buffer_unmap(rctx->border_color_table->cs_buf);
2806 si_pm4_add_bo(pm4, rctx->border_color_table, RADEON_USAGE_READ);
2807 }
2808
2809 memcpy(samplers->samplers, states, sizeof(void*) * count);
2810
2811 out:
2812 samplers->n_samplers = count;
2813 return pm4;
2814 }
2815
2816 static void si_bind_vs_sampler_states(struct pipe_context *ctx, unsigned count, void **states)
2817 {
2818 struct r600_context *rctx = (struct r600_context *)ctx;
2819 struct si_pm4_state *pm4;
2820
2821 pm4 = si_set_sampler_states(rctx, count, states, &rctx->samplers[PIPE_SHADER_VERTEX],
2822 R_00B130_SPI_SHADER_USER_DATA_VS_0);
2823 si_pm4_set_state(rctx, vs_sampler, pm4);
2824 }
2825
2826 static void si_bind_ps_sampler_states(struct pipe_context *ctx, unsigned count, void **states)
2827 {
2828 struct r600_context *rctx = (struct r600_context *)ctx;
2829 struct si_pm4_state *pm4;
2830
2831 pm4 = si_set_sampler_states(rctx, count, states, &rctx->samplers[PIPE_SHADER_FRAGMENT],
2832 R_00B030_SPI_SHADER_USER_DATA_PS_0);
2833 si_pm4_set_state(rctx, ps_sampler, pm4);
2834 }
2835
2836
2837 static void si_bind_sampler_states(struct pipe_context *ctx, unsigned shader,
2838 unsigned start, unsigned count,
2839 void **states)
2840 {
2841 assert(start == 0);
2842
2843 switch (shader) {
2844 case PIPE_SHADER_VERTEX:
2845 si_bind_vs_sampler_states(ctx, count, states);
2846 break;
2847 case PIPE_SHADER_FRAGMENT:
2848 si_bind_ps_sampler_states(ctx, count, states);
2849 break;
2850 default:
2851 ;
2852 }
2853 }
2854
2855
2856
2857 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
2858 {
2859 struct r600_context *rctx = (struct r600_context *)ctx;
2860 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
2861 uint16_t mask = sample_mask;
2862
2863 if (pm4 == NULL)
2864 return;
2865
2866 si_pm4_set_reg(pm4, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, mask | (mask << 16));
2867 si_pm4_set_reg(pm4, R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, mask | (mask << 16));
2868
2869 si_pm4_set_state(rctx, sample_mask, pm4);
2870 }
2871
2872 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
2873 {
2874 free(state);
2875 }
2876
2877 /*
2878 * Vertex elements & buffers
2879 */
2880
2881 static void *si_create_vertex_elements(struct pipe_context *ctx,
2882 unsigned count,
2883 const struct pipe_vertex_element *elements)
2884 {
2885 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
2886 int i;
2887
2888 assert(count < PIPE_MAX_ATTRIBS);
2889 if (!v)
2890 return NULL;
2891
2892 v->count = count;
2893 for (i = 0; i < count; ++i) {
2894 const struct util_format_description *desc;
2895 unsigned data_format, num_format;
2896 int first_non_void;
2897
2898 desc = util_format_description(elements[i].src_format);
2899 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
2900 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
2901 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
2902
2903 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2904 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2905 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2906 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2907 S_008F0C_NUM_FORMAT(num_format) |
2908 S_008F0C_DATA_FORMAT(data_format);
2909 }
2910 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
2911
2912 return v;
2913 }
2914
2915 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
2916 {
2917 struct r600_context *rctx = (struct r600_context *)ctx;
2918 struct si_vertex_element *v = (struct si_vertex_element*)state;
2919
2920 rctx->vertex_elements = v;
2921 }
2922
2923 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
2924 {
2925 struct r600_context *rctx = (struct r600_context *)ctx;
2926
2927 if (rctx->vertex_elements == state)
2928 rctx->vertex_elements = NULL;
2929 FREE(state);
2930 }
2931
2932 static void si_set_vertex_buffers(struct pipe_context *ctx, unsigned start_slot, unsigned count,
2933 const struct pipe_vertex_buffer *buffers)
2934 {
2935 struct r600_context *rctx = (struct r600_context *)ctx;
2936
2937 util_set_vertex_buffers_count(rctx->vertex_buffer, &rctx->nr_vertex_buffers, buffers, start_slot, count);
2938 }
2939
2940 static void si_set_index_buffer(struct pipe_context *ctx,
2941 const struct pipe_index_buffer *ib)
2942 {
2943 struct r600_context *rctx = (struct r600_context *)ctx;
2944
2945 if (ib) {
2946 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
2947 memcpy(&rctx->index_buffer, ib, sizeof(*ib));
2948 } else {
2949 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
2950 }
2951 }
2952
2953 /*
2954 * Misc
2955 */
2956 static void si_set_polygon_stipple(struct pipe_context *ctx,
2957 const struct pipe_poly_stipple *state)
2958 {
2959 }
2960
2961 static void si_texture_barrier(struct pipe_context *ctx)
2962 {
2963 struct r600_context *rctx = (struct r600_context *)ctx;
2964
2965 rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE |
2966 R600_CONTEXT_FLUSH_AND_INV_CB;
2967 }
2968
2969 static void *si_create_blend_custom(struct r600_context *rctx, unsigned mode)
2970 {
2971 struct pipe_blend_state blend;
2972
2973 memset(&blend, 0, sizeof(blend));
2974 blend.independent_blend_enable = true;
2975 blend.rt[0].colormask = 0xf;
2976 return si_create_blend_state_mode(&rctx->b.b, &blend, mode);
2977 }
2978
2979 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
2980 struct pipe_resource *texture,
2981 const struct pipe_surface *surf_tmpl)
2982 {
2983 struct r600_texture *rtex = (struct r600_texture*)texture;
2984 struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
2985 unsigned level = surf_tmpl->u.tex.level;
2986
2987 if (surface == NULL)
2988 return NULL;
2989
2990 assert(surf_tmpl->u.tex.first_layer <= util_max_layer(texture, surf_tmpl->u.tex.level));
2991 assert(surf_tmpl->u.tex.last_layer <= util_max_layer(texture, surf_tmpl->u.tex.level));
2992
2993 pipe_reference_init(&surface->base.reference, 1);
2994 pipe_resource_reference(&surface->base.texture, texture);
2995 surface->base.context = pipe;
2996 surface->base.format = surf_tmpl->format;
2997 surface->base.width = rtex->surface.level[level].npix_x;
2998 surface->base.height = rtex->surface.level[level].npix_y;
2999 surface->base.texture = texture;
3000 surface->base.u.tex.first_layer = surf_tmpl->u.tex.first_layer;
3001 surface->base.u.tex.last_layer = surf_tmpl->u.tex.last_layer;
3002 surface->base.u.tex.level = level;
3003
3004 return &surface->base;
3005 }
3006
3007 static void r600_surface_destroy(struct pipe_context *pipe,
3008 struct pipe_surface *surface)
3009 {
3010 pipe_resource_reference(&surface->texture, NULL);
3011 FREE(surface);
3012 }
3013
3014 static boolean si_dma_copy(struct pipe_context *ctx,
3015 struct pipe_resource *dst,
3016 unsigned dst_level,
3017 unsigned dst_x, unsigned dst_y, unsigned dst_z,
3018 struct pipe_resource *src,
3019 unsigned src_level,
3020 const struct pipe_box *src_box)
3021 {
3022 /* XXX implement this or share evergreen_dma_blit with r600g */
3023 return FALSE;
3024 }
3025
3026 void si_init_state_functions(struct r600_context *rctx)
3027 {
3028 int i;
3029
3030 rctx->b.b.create_blend_state = si_create_blend_state;
3031 rctx->b.b.bind_blend_state = si_bind_blend_state;
3032 rctx->b.b.delete_blend_state = si_delete_blend_state;
3033 rctx->b.b.set_blend_color = si_set_blend_color;
3034
3035 rctx->b.b.create_rasterizer_state = si_create_rs_state;
3036 rctx->b.b.bind_rasterizer_state = si_bind_rs_state;
3037 rctx->b.b.delete_rasterizer_state = si_delete_rs_state;
3038
3039 rctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
3040 rctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
3041 rctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
3042
3043 for (i = 0; i < 8; i++) {
3044 rctx->custom_dsa_flush_depth_stencil[i] = si_create_db_flush_dsa(rctx, true, true, i);
3045 rctx->custom_dsa_flush_depth[i] = si_create_db_flush_dsa(rctx, true, false, i);
3046 rctx->custom_dsa_flush_stencil[i] = si_create_db_flush_dsa(rctx, false, true, i);
3047 }
3048 rctx->custom_dsa_flush_inplace = si_create_db_flush_dsa(rctx, false, false, 0);
3049 rctx->custom_blend_resolve = si_create_blend_custom(rctx, V_028808_CB_RESOLVE);
3050 rctx->custom_blend_decompress = si_create_blend_custom(rctx, V_028808_CB_FMASK_DECOMPRESS);
3051
3052 rctx->b.b.set_clip_state = si_set_clip_state;
3053 rctx->b.b.set_scissor_states = si_set_scissor_states;
3054 rctx->b.b.set_viewport_states = si_set_viewport_states;
3055 rctx->b.b.set_stencil_ref = si_set_pipe_stencil_ref;
3056
3057 rctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
3058 rctx->b.b.get_sample_position = si_get_sample_position;
3059
3060 rctx->b.b.create_vs_state = si_create_vs_state;
3061 rctx->b.b.create_fs_state = si_create_fs_state;
3062 rctx->b.b.bind_vs_state = si_bind_vs_shader;
3063 rctx->b.b.bind_fs_state = si_bind_ps_shader;
3064 rctx->b.b.delete_vs_state = si_delete_vs_shader;
3065 rctx->b.b.delete_fs_state = si_delete_ps_shader;
3066
3067 rctx->b.b.create_sampler_state = si_create_sampler_state;
3068 rctx->b.b.bind_sampler_states = si_bind_sampler_states;
3069 rctx->b.b.delete_sampler_state = si_delete_sampler_state;
3070
3071 rctx->b.b.create_sampler_view = si_create_sampler_view;
3072 rctx->b.b.set_sampler_views = si_set_sampler_views;
3073 rctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
3074
3075 rctx->b.b.set_sample_mask = si_set_sample_mask;
3076
3077 rctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
3078 rctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
3079 rctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
3080 rctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
3081 rctx->b.b.set_index_buffer = si_set_index_buffer;
3082
3083 rctx->b.b.texture_barrier = si_texture_barrier;
3084 rctx->b.b.set_polygon_stipple = si_set_polygon_stipple;
3085 rctx->b.b.create_surface = r600_create_surface;
3086 rctx->b.b.surface_destroy = r600_surface_destroy;
3087 rctx->b.dma_copy = si_dma_copy;
3088
3089 rctx->b.b.draw_vbo = si_draw_vbo;
3090 }
3091
3092 void si_init_config(struct r600_context *rctx)
3093 {
3094 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
3095
3096 if (pm4 == NULL)
3097 return;
3098
3099 si_cmd_context_control(pm4);
3100
3101 si_pm4_set_reg(pm4, R_028A4C_PA_SC_MODE_CNTL_1, 0x0);
3102
3103 si_pm4_set_reg(pm4, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0);
3104 si_pm4_set_reg(pm4, R_028A14_VGT_HOS_CNTL, 0x0);
3105 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0);
3106 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0);
3107 si_pm4_set_reg(pm4, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0);
3108 si_pm4_set_reg(pm4, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0);
3109 si_pm4_set_reg(pm4, R_028A28_VGT_GROUP_FIRST_DECR, 0x0);
3110 si_pm4_set_reg(pm4, R_028A2C_VGT_GROUP_DECR, 0x0);
3111 si_pm4_set_reg(pm4, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0);
3112 si_pm4_set_reg(pm4, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0);
3113 si_pm4_set_reg(pm4, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0);
3114 si_pm4_set_reg(pm4, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0);
3115 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, 0x0);
3116 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0x0);
3117 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
3118 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3119 si_pm4_set_reg(pm4, R_028B94_VGT_STRMOUT_CONFIG, 0x0);
3120 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
3121 if (rctx->b.chip_class == SI) {
3122 si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM,
3123 S_028AA8_SWITCH_ON_EOP(1) |
3124 S_028AA8_PARTIAL_VS_WAVE_ON(1) |
3125 S_028AA8_PRIMGROUP_SIZE(63));
3126 }
3127 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0x00000000);
3128 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
3129 if (rctx->b.chip_class < CIK)
3130 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
3131 S_008A14_CLIP_VTX_REORDER_ENA(1));
3132
3133 si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, 0);
3134 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
3135 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
3136
3137 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
3138
3139 if (rctx->b.chip_class >= CIK) {
3140 switch (rctx->screen->b.family) {
3141 case CHIP_BONAIRE:
3142 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x16000012);
3143 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000);
3144 break;
3145 case CHIP_HAWAII:
3146 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x3a00161a);
3147 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x0000002e);
3148 break;
3149 case CHIP_KAVERI:
3150 /* XXX todo */
3151 case CHIP_KABINI:
3152 /* XXX todo */
3153 default:
3154 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
3155 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000);
3156 break;
3157 }
3158 } else {
3159 switch (rctx->screen->b.family) {
3160 case CHIP_TAHITI:
3161 case CHIP_PITCAIRN:
3162 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x2a00126a);
3163 break;
3164 case CHIP_VERDE:
3165 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x0000124a);
3166 break;
3167 case CHIP_OLAND:
3168 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000082);
3169 break;
3170 case CHIP_HAINAN:
3171 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
3172 break;
3173 default:
3174 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
3175 break;
3176 }
3177 }
3178
3179 si_pm4_set_reg(pm4, R_028200_PA_SC_WINDOW_OFFSET, 0x00000000);
3180 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
3181 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000);
3182 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000);
3183 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
3184 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0x00000000);
3185 si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000);
3186 si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000);
3187 si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000);
3188 si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000);
3189 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, 0x00000000);
3190 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, 0x00000000);
3191 si_pm4_set_reg(pm4, R_028028_DB_STENCIL_CLEAR, 0x00000000);
3192 si_pm4_set_reg(pm4, R_02802C_DB_DEPTH_CLEAR, 0x3F800000);
3193 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
3194 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
3195 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
3196 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE,
3197 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3198 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
3199 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
3200 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
3201
3202 if (rctx->b.chip_class >= CIK) {
3203 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
3204 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(0));
3205 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
3206 }
3207
3208 si_pm4_set_state(rctx, init, pm4);
3209 }