2 * Copyright 2012 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "si_build_pm4.h"
29 #include "util/u_dual_blend.h"
30 #include "util/u_format.h"
31 #include "util/u_format_s3tc.h"
32 #include "util/u_memory.h"
33 #include "util/u_resource.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/fast_idiv_by_const.h"
37 static unsigned si_map_swizzle(unsigned swizzle
)
41 return V_008F0C_SQ_SEL_Y
;
43 return V_008F0C_SQ_SEL_Z
;
45 return V_008F0C_SQ_SEL_W
;
47 return V_008F0C_SQ_SEL_0
;
49 return V_008F0C_SQ_SEL_1
;
50 default: /* PIPE_SWIZZLE_X */
51 return V_008F0C_SQ_SEL_X
;
55 /* 12.4 fixed-point */
56 static unsigned si_pack_float_12p4(float x
)
59 x
>= 4096 ? 0xffff : x
* 16;
63 * Inferred framebuffer and blender state.
65 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
66 * if there is not enough PS outputs.
68 static void si_emit_cb_render_state(struct si_context
*sctx
)
70 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
71 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
72 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
73 * but you never know. */
74 uint32_t cb_target_mask
= sctx
->framebuffer
.colorbuf_enabled_4bit
;
78 cb_target_mask
&= blend
->cb_target_mask
;
80 /* Avoid a hang that happens when dual source blending is enabled
81 * but there is not enough color outputs. This is undefined behavior,
82 * so disable color writes completely.
84 * Reproducible with Unigine Heaven 4.0 and drirc missing.
86 if (blend
&& blend
->dual_src_blend
&&
87 sctx
->ps_shader
.cso
&&
88 (sctx
->ps_shader
.cso
->info
.colors_written
& 0x3) != 0x3)
91 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
92 * I think we don't have to do anything between IBs.
94 if (sctx
->screen
->dfsm_allowed
&&
95 sctx
->last_cb_target_mask
!= cb_target_mask
) {
96 sctx
->last_cb_target_mask
= cb_target_mask
;
98 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
99 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
102 unsigned initial_cdw
= cs
->current
.cdw
;
103 radeon_opt_set_context_reg(sctx
, R_028238_CB_TARGET_MASK
,
104 SI_TRACKED_CB_TARGET_MASK
, cb_target_mask
);
106 if (sctx
->chip_class
>= VI
) {
107 /* DCC MSAA workaround for blending.
108 * Alternatively, we can set CB_COLORi_DCC_CONTROL.OVERWRITE_-
109 * COMBINER_DISABLE, but that would be more complicated.
111 bool oc_disable
= (sctx
->chip_class
== VI
||
112 sctx
->chip_class
== GFX9
) &&
114 blend
->blend_enable_4bit
& cb_target_mask
&&
115 sctx
->framebuffer
.nr_samples
>= 2;
116 unsigned watermark
= sctx
->framebuffer
.dcc_overwrite_combiner_watermark
;
118 radeon_opt_set_context_reg(
119 sctx
, R_028424_CB_DCC_CONTROL
,
120 SI_TRACKED_CB_DCC_CONTROL
,
121 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
122 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark
) |
123 S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable
) |
124 S_028424_DISABLE_CONSTANT_ENCODE_REG(sctx
->screen
->has_dcc_constant_encode
));
127 /* RB+ register settings. */
128 if (sctx
->screen
->rbplus_allowed
) {
129 unsigned spi_shader_col_format
=
130 sctx
->ps_shader
.cso
?
131 sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.spi_shader_col_format
: 0;
132 unsigned sx_ps_downconvert
= 0;
133 unsigned sx_blend_opt_epsilon
= 0;
134 unsigned sx_blend_opt_control
= 0;
136 for (i
= 0; i
< sctx
->framebuffer
.state
.nr_cbufs
; i
++) {
137 struct si_surface
*surf
=
138 (struct si_surface
*)sctx
->framebuffer
.state
.cbufs
[i
];
139 unsigned format
, swap
, spi_format
, colormask
;
140 bool has_alpha
, has_rgb
;
145 format
= G_028C70_FORMAT(surf
->cb_color_info
);
146 swap
= G_028C70_COMP_SWAP(surf
->cb_color_info
);
147 spi_format
= (spi_shader_col_format
>> (i
* 4)) & 0xf;
148 colormask
= (cb_target_mask
>> (i
* 4)) & 0xf;
150 /* Set if RGB and A are present. */
151 has_alpha
= !G_028C74_FORCE_DST_ALPHA_1(surf
->cb_color_attrib
);
153 if (format
== V_028C70_COLOR_8
||
154 format
== V_028C70_COLOR_16
||
155 format
== V_028C70_COLOR_32
)
156 has_rgb
= !has_alpha
;
160 /* Check the colormask and export format. */
161 if (!(colormask
& (PIPE_MASK_RGBA
& ~PIPE_MASK_A
)))
163 if (!(colormask
& PIPE_MASK_A
))
166 if (spi_format
== V_028714_SPI_SHADER_ZERO
) {
171 /* Disable value checking for disabled channels. */
173 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
175 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
177 /* Enable down-conversion for 32bpp and smaller formats. */
179 case V_028C70_COLOR_8
:
180 case V_028C70_COLOR_8_8
:
181 case V_028C70_COLOR_8_8_8_8
:
182 /* For 1 and 2-channel formats, use the superset thereof. */
183 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
||
184 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
185 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
186 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_8_8_8_8
<< (i
* 4);
187 sx_blend_opt_epsilon
|= V_028758_8BIT_FORMAT
<< (i
* 4);
191 case V_028C70_COLOR_5_6_5
:
192 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
193 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_5_6_5
<< (i
* 4);
194 sx_blend_opt_epsilon
|= V_028758_6BIT_FORMAT
<< (i
* 4);
198 case V_028C70_COLOR_1_5_5_5
:
199 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
200 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_1_5_5_5
<< (i
* 4);
201 sx_blend_opt_epsilon
|= V_028758_5BIT_FORMAT
<< (i
* 4);
205 case V_028C70_COLOR_4_4_4_4
:
206 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
207 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_4_4_4_4
<< (i
* 4);
208 sx_blend_opt_epsilon
|= V_028758_4BIT_FORMAT
<< (i
* 4);
212 case V_028C70_COLOR_32
:
213 if (swap
== V_028C70_SWAP_STD
&&
214 spi_format
== V_028714_SPI_SHADER_32_R
)
215 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_R
<< (i
* 4);
216 else if (swap
== V_028C70_SWAP_ALT_REV
&&
217 spi_format
== V_028714_SPI_SHADER_32_AR
)
218 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_A
<< (i
* 4);
221 case V_028C70_COLOR_16
:
222 case V_028C70_COLOR_16_16
:
223 /* For 1-channel formats, use the superset thereof. */
224 if (spi_format
== V_028714_SPI_SHADER_UNORM16_ABGR
||
225 spi_format
== V_028714_SPI_SHADER_SNORM16_ABGR
||
226 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
227 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
228 if (swap
== V_028C70_SWAP_STD
||
229 swap
== V_028C70_SWAP_STD_REV
)
230 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_GR
<< (i
* 4);
232 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_AR
<< (i
* 4);
236 case V_028C70_COLOR_10_11_11
:
237 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
238 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_10_11_11
<< (i
* 4);
239 sx_blend_opt_epsilon
|= V_028758_11BIT_FORMAT
<< (i
* 4);
243 case V_028C70_COLOR_2_10_10_10
:
244 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
245 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_2_10_10_10
<< (i
* 4);
246 sx_blend_opt_epsilon
|= V_028758_10BIT_FORMAT
<< (i
* 4);
252 /* SX_PS_DOWNCONVERT, SX_BLEND_OPT_EPSILON, SX_BLEND_OPT_CONTROL */
253 radeon_opt_set_context_reg3(sctx
, R_028754_SX_PS_DOWNCONVERT
,
254 SI_TRACKED_SX_PS_DOWNCONVERT
,
255 sx_ps_downconvert
, sx_blend_opt_epsilon
,
256 sx_blend_opt_control
);
258 if (initial_cdw
!= cs
->current
.cdw
)
259 sctx
->context_roll_counter
++;
266 static uint32_t si_translate_blend_function(int blend_func
)
268 switch (blend_func
) {
270 return V_028780_COMB_DST_PLUS_SRC
;
271 case PIPE_BLEND_SUBTRACT
:
272 return V_028780_COMB_SRC_MINUS_DST
;
273 case PIPE_BLEND_REVERSE_SUBTRACT
:
274 return V_028780_COMB_DST_MINUS_SRC
;
276 return V_028780_COMB_MIN_DST_SRC
;
278 return V_028780_COMB_MAX_DST_SRC
;
280 PRINT_ERR("Unknown blend function %d\n", blend_func
);
287 static uint32_t si_translate_blend_factor(int blend_fact
)
289 switch (blend_fact
) {
290 case PIPE_BLENDFACTOR_ONE
:
291 return V_028780_BLEND_ONE
;
292 case PIPE_BLENDFACTOR_SRC_COLOR
:
293 return V_028780_BLEND_SRC_COLOR
;
294 case PIPE_BLENDFACTOR_SRC_ALPHA
:
295 return V_028780_BLEND_SRC_ALPHA
;
296 case PIPE_BLENDFACTOR_DST_ALPHA
:
297 return V_028780_BLEND_DST_ALPHA
;
298 case PIPE_BLENDFACTOR_DST_COLOR
:
299 return V_028780_BLEND_DST_COLOR
;
300 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
301 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
302 case PIPE_BLENDFACTOR_CONST_COLOR
:
303 return V_028780_BLEND_CONSTANT_COLOR
;
304 case PIPE_BLENDFACTOR_CONST_ALPHA
:
305 return V_028780_BLEND_CONSTANT_ALPHA
;
306 case PIPE_BLENDFACTOR_ZERO
:
307 return V_028780_BLEND_ZERO
;
308 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
309 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
310 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
311 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
312 case PIPE_BLENDFACTOR_INV_DST_ALPHA
:
313 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
314 case PIPE_BLENDFACTOR_INV_DST_COLOR
:
315 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
316 case PIPE_BLENDFACTOR_INV_CONST_COLOR
:
317 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR
;
318 case PIPE_BLENDFACTOR_INV_CONST_ALPHA
:
319 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA
;
320 case PIPE_BLENDFACTOR_SRC1_COLOR
:
321 return V_028780_BLEND_SRC1_COLOR
;
322 case PIPE_BLENDFACTOR_SRC1_ALPHA
:
323 return V_028780_BLEND_SRC1_ALPHA
;
324 case PIPE_BLENDFACTOR_INV_SRC1_COLOR
:
325 return V_028780_BLEND_INV_SRC1_COLOR
;
326 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA
:
327 return V_028780_BLEND_INV_SRC1_ALPHA
;
329 PRINT_ERR("Bad blend factor %d not supported!\n", blend_fact
);
336 static uint32_t si_translate_blend_opt_function(int blend_func
)
338 switch (blend_func
) {
340 return V_028760_OPT_COMB_ADD
;
341 case PIPE_BLEND_SUBTRACT
:
342 return V_028760_OPT_COMB_SUBTRACT
;
343 case PIPE_BLEND_REVERSE_SUBTRACT
:
344 return V_028760_OPT_COMB_REVSUBTRACT
;
346 return V_028760_OPT_COMB_MIN
;
348 return V_028760_OPT_COMB_MAX
;
350 return V_028760_OPT_COMB_BLEND_DISABLED
;
354 static uint32_t si_translate_blend_opt_factor(int blend_fact
, bool is_alpha
)
356 switch (blend_fact
) {
357 case PIPE_BLENDFACTOR_ZERO
:
358 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL
;
359 case PIPE_BLENDFACTOR_ONE
:
360 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
;
361 case PIPE_BLENDFACTOR_SRC_COLOR
:
362 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
363 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0
;
364 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
365 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
366 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1
;
367 case PIPE_BLENDFACTOR_SRC_ALPHA
:
368 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
;
369 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
370 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
;
371 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
372 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
373 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
375 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
379 static void si_blend_check_commutativity(struct si_screen
*sscreen
,
380 struct si_state_blend
*blend
,
381 enum pipe_blend_func func
,
382 enum pipe_blendfactor src
,
383 enum pipe_blendfactor dst
,
386 /* Src factor is allowed when it does not depend on Dst */
387 static const uint32_t src_allowed
=
388 (1u << PIPE_BLENDFACTOR_ONE
) |
389 (1u << PIPE_BLENDFACTOR_SRC_COLOR
) |
390 (1u << PIPE_BLENDFACTOR_SRC_ALPHA
) |
391 (1u << PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
) |
392 (1u << PIPE_BLENDFACTOR_CONST_COLOR
) |
393 (1u << PIPE_BLENDFACTOR_CONST_ALPHA
) |
394 (1u << PIPE_BLENDFACTOR_SRC1_COLOR
) |
395 (1u << PIPE_BLENDFACTOR_SRC1_ALPHA
) |
396 (1u << PIPE_BLENDFACTOR_ZERO
) |
397 (1u << PIPE_BLENDFACTOR_INV_SRC_COLOR
) |
398 (1u << PIPE_BLENDFACTOR_INV_SRC_ALPHA
) |
399 (1u << PIPE_BLENDFACTOR_INV_CONST_COLOR
) |
400 (1u << PIPE_BLENDFACTOR_INV_CONST_ALPHA
) |
401 (1u << PIPE_BLENDFACTOR_INV_SRC1_COLOR
) |
402 (1u << PIPE_BLENDFACTOR_INV_SRC1_ALPHA
);
404 if (dst
== PIPE_BLENDFACTOR_ONE
&&
405 (src_allowed
& (1u << src
))) {
406 /* Addition is commutative, but floating point addition isn't
407 * associative: subtle changes can be introduced via different
410 * Out-of-order is also non-deterministic, which means that
411 * this breaks OpenGL invariance requirements. So only enable
412 * out-of-order additive blending if explicitly allowed by a
415 if (func
== PIPE_BLEND_MAX
|| func
== PIPE_BLEND_MIN
||
416 (func
== PIPE_BLEND_ADD
&& sscreen
->commutative_blend_add
))
417 blend
->commutative_4bit
|= chanmask
;
422 * Get rid of DST in the blend factors by commuting the operands:
423 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
425 static void si_blend_remove_dst(unsigned *func
, unsigned *src_factor
,
426 unsigned *dst_factor
, unsigned expected_dst
,
427 unsigned replacement_src
)
429 if (*src_factor
== expected_dst
&&
430 *dst_factor
== PIPE_BLENDFACTOR_ZERO
) {
431 *src_factor
= PIPE_BLENDFACTOR_ZERO
;
432 *dst_factor
= replacement_src
;
434 /* Commuting the operands requires reversing subtractions. */
435 if (*func
== PIPE_BLEND_SUBTRACT
)
436 *func
= PIPE_BLEND_REVERSE_SUBTRACT
;
437 else if (*func
== PIPE_BLEND_REVERSE_SUBTRACT
)
438 *func
= PIPE_BLEND_SUBTRACT
;
442 static bool si_blend_factor_uses_dst(unsigned factor
)
444 return factor
== PIPE_BLENDFACTOR_DST_COLOR
||
445 factor
== PIPE_BLENDFACTOR_DST_ALPHA
||
446 factor
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
447 factor
== PIPE_BLENDFACTOR_INV_DST_ALPHA
||
448 factor
== PIPE_BLENDFACTOR_INV_DST_COLOR
;
451 static void *si_create_blend_state_mode(struct pipe_context
*ctx
,
452 const struct pipe_blend_state
*state
,
455 struct si_context
*sctx
= (struct si_context
*)ctx
;
456 struct si_state_blend
*blend
= CALLOC_STRUCT(si_state_blend
);
457 struct si_pm4_state
*pm4
= &blend
->pm4
;
458 uint32_t sx_mrt_blend_opt
[8] = {0};
459 uint32_t color_control
= 0;
464 blend
->alpha_to_coverage
= state
->alpha_to_coverage
;
465 blend
->alpha_to_one
= state
->alpha_to_one
;
466 blend
->dual_src_blend
= util_blend_state_is_dual(state
, 0);
467 blend
->logicop_enable
= state
->logicop_enable
;
469 if (state
->logicop_enable
) {
470 color_control
|= S_028808_ROP3(state
->logicop_func
| (state
->logicop_func
<< 4));
472 color_control
|= S_028808_ROP3(0xcc);
475 si_pm4_set_reg(pm4
, R_028B70_DB_ALPHA_TO_MASK
,
476 S_028B70_ALPHA_TO_MASK_ENABLE(state
->alpha_to_coverage
) |
477 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
478 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
479 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
480 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
482 if (state
->alpha_to_coverage
)
483 blend
->need_src_alpha_4bit
|= 0xf;
485 blend
->cb_target_mask
= 0;
486 blend
->cb_target_enabled_4bit
= 0;
488 for (int i
= 0; i
< 8; i
++) {
489 /* state->rt entries > 0 only written if independent blending */
490 const int j
= state
->independent_blend_enable
? i
: 0;
492 unsigned eqRGB
= state
->rt
[j
].rgb_func
;
493 unsigned srcRGB
= state
->rt
[j
].rgb_src_factor
;
494 unsigned dstRGB
= state
->rt
[j
].rgb_dst_factor
;
495 unsigned eqA
= state
->rt
[j
].alpha_func
;
496 unsigned srcA
= state
->rt
[j
].alpha_src_factor
;
497 unsigned dstA
= state
->rt
[j
].alpha_dst_factor
;
499 unsigned srcRGB_opt
, dstRGB_opt
, srcA_opt
, dstA_opt
;
500 unsigned blend_cntl
= 0;
502 sx_mrt_blend_opt
[i
] =
503 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) |
504 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
506 /* Only set dual source blending for MRT0 to avoid a hang. */
507 if (i
>= 1 && blend
->dual_src_blend
) {
508 /* Vulkan does this for dual source blending. */
510 blend_cntl
|= S_028780_ENABLE(1);
512 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
516 /* Only addition and subtraction equations are supported with
517 * dual source blending.
519 if (blend
->dual_src_blend
&&
520 (eqRGB
== PIPE_BLEND_MIN
|| eqRGB
== PIPE_BLEND_MAX
||
521 eqA
== PIPE_BLEND_MIN
|| eqA
== PIPE_BLEND_MAX
)) {
522 assert(!"Unsupported equation for dual source blending");
523 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
527 /* cb_render_state will disable unused ones */
528 blend
->cb_target_mask
|= (unsigned)state
->rt
[j
].colormask
<< (4 * i
);
529 if (state
->rt
[j
].colormask
)
530 blend
->cb_target_enabled_4bit
|= 0xf << (4 * i
);
532 if (!state
->rt
[j
].colormask
|| !state
->rt
[j
].blend_enable
) {
533 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
537 si_blend_check_commutativity(sctx
->screen
, blend
,
538 eqRGB
, srcRGB
, dstRGB
, 0x7 << (4 * i
));
539 si_blend_check_commutativity(sctx
->screen
, blend
,
540 eqA
, srcA
, dstA
, 0x8 << (4 * i
));
542 /* Blending optimizations for RB+.
543 * These transformations don't change the behavior.
545 * First, get rid of DST in the blend factors:
546 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
548 si_blend_remove_dst(&eqRGB
, &srcRGB
, &dstRGB
,
549 PIPE_BLENDFACTOR_DST_COLOR
,
550 PIPE_BLENDFACTOR_SRC_COLOR
);
551 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
552 PIPE_BLENDFACTOR_DST_COLOR
,
553 PIPE_BLENDFACTOR_SRC_COLOR
);
554 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
555 PIPE_BLENDFACTOR_DST_ALPHA
,
556 PIPE_BLENDFACTOR_SRC_ALPHA
);
558 /* Look up the ideal settings from tables. */
559 srcRGB_opt
= si_translate_blend_opt_factor(srcRGB
, false);
560 dstRGB_opt
= si_translate_blend_opt_factor(dstRGB
, false);
561 srcA_opt
= si_translate_blend_opt_factor(srcA
, true);
562 dstA_opt
= si_translate_blend_opt_factor(dstA
, true);
564 /* Handle interdependencies. */
565 if (si_blend_factor_uses_dst(srcRGB
))
566 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
567 if (si_blend_factor_uses_dst(srcA
))
568 dstA_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
570 if (srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
&&
571 (dstRGB
== PIPE_BLENDFACTOR_ZERO
||
572 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
573 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
))
574 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
576 /* Set the final value. */
577 sx_mrt_blend_opt
[i
] =
578 S_028760_COLOR_SRC_OPT(srcRGB_opt
) |
579 S_028760_COLOR_DST_OPT(dstRGB_opt
) |
580 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB
)) |
581 S_028760_ALPHA_SRC_OPT(srcA_opt
) |
582 S_028760_ALPHA_DST_OPT(dstA_opt
) |
583 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA
));
585 /* Set blend state. */
586 blend_cntl
|= S_028780_ENABLE(1);
587 blend_cntl
|= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB
));
588 blend_cntl
|= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB
));
589 blend_cntl
|= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB
));
591 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
592 blend_cntl
|= S_028780_SEPARATE_ALPHA_BLEND(1);
593 blend_cntl
|= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA
));
594 blend_cntl
|= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA
));
595 blend_cntl
|= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA
));
597 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
599 blend
->blend_enable_4bit
|= 0xfu
<< (i
* 4);
601 /* This is only important for formats without alpha. */
602 if (srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
603 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
604 srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
605 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
606 srcRGB
== PIPE_BLENDFACTOR_INV_SRC_ALPHA
||
607 dstRGB
== PIPE_BLENDFACTOR_INV_SRC_ALPHA
)
608 blend
->need_src_alpha_4bit
|= 0xfu
<< (i
* 4);
611 if (blend
->cb_target_mask
) {
612 color_control
|= S_028808_MODE(mode
);
614 color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
617 if (sctx
->screen
->rbplus_allowed
) {
618 /* Disable RB+ blend optimizations for dual source blending.
621 if (blend
->dual_src_blend
) {
622 for (int i
= 0; i
< 8; i
++) {
623 sx_mrt_blend_opt
[i
] =
624 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE
) |
625 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE
);
629 for (int i
= 0; i
< 8; i
++)
630 si_pm4_set_reg(pm4
, R_028760_SX_MRT0_BLEND_OPT
+ i
* 4,
631 sx_mrt_blend_opt
[i
]);
633 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
634 if (blend
->dual_src_blend
|| state
->logicop_enable
||
635 mode
== V_028808_CB_RESOLVE
)
636 color_control
|= S_028808_DISABLE_DUAL_QUAD(1);
639 si_pm4_set_reg(pm4
, R_028808_CB_COLOR_CONTROL
, color_control
);
643 static void *si_create_blend_state(struct pipe_context
*ctx
,
644 const struct pipe_blend_state
*state
)
646 return si_create_blend_state_mode(ctx
, state
, V_028808_CB_NORMAL
);
649 static void si_bind_blend_state(struct pipe_context
*ctx
, void *state
)
651 struct si_context
*sctx
= (struct si_context
*)ctx
;
652 struct si_state_blend
*old_blend
= sctx
->queued
.named
.blend
;
653 struct si_state_blend
*blend
= (struct si_state_blend
*)state
;
658 si_pm4_bind_state(sctx
, blend
, state
);
661 old_blend
->cb_target_mask
!= blend
->cb_target_mask
||
662 old_blend
->dual_src_blend
!= blend
->dual_src_blend
||
663 (old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
&&
664 sctx
->framebuffer
.nr_samples
>= 2 &&
665 sctx
->screen
->dcc_msaa_allowed
))
666 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
669 old_blend
->cb_target_mask
!= blend
->cb_target_mask
||
670 old_blend
->alpha_to_coverage
!= blend
->alpha_to_coverage
||
671 old_blend
->alpha_to_one
!= blend
->alpha_to_one
||
672 old_blend
->dual_src_blend
!= blend
->dual_src_blend
||
673 old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
||
674 old_blend
->need_src_alpha_4bit
!= blend
->need_src_alpha_4bit
)
675 sctx
->do_update_shaders
= true;
677 if (sctx
->screen
->dpbb_allowed
&&
679 old_blend
->alpha_to_coverage
!= blend
->alpha_to_coverage
||
680 old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
||
681 old_blend
->cb_target_enabled_4bit
!= blend
->cb_target_enabled_4bit
))
682 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
684 if (sctx
->screen
->has_out_of_order_rast
&&
686 (old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
||
687 old_blend
->cb_target_enabled_4bit
!= blend
->cb_target_enabled_4bit
||
688 old_blend
->commutative_4bit
!= blend
->commutative_4bit
||
689 old_blend
->logicop_enable
!= blend
->logicop_enable
)))
690 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
693 static void si_delete_blend_state(struct pipe_context
*ctx
, void *state
)
695 struct si_context
*sctx
= (struct si_context
*)ctx
;
696 si_pm4_delete_state(sctx
, blend
, (struct si_state_blend
*)state
);
699 static void si_set_blend_color(struct pipe_context
*ctx
,
700 const struct pipe_blend_color
*state
)
702 struct si_context
*sctx
= (struct si_context
*)ctx
;
703 static const struct pipe_blend_color zeros
;
705 sctx
->blend_color
.state
= *state
;
706 sctx
->blend_color
.any_nonzeros
= memcmp(state
, &zeros
, sizeof(*state
)) != 0;
707 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.blend_color
);
710 static void si_emit_blend_color(struct si_context
*sctx
)
712 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
714 radeon_set_context_reg_seq(cs
, R_028414_CB_BLEND_RED
, 4);
715 radeon_emit_array(cs
, (uint32_t*)sctx
->blend_color
.state
.color
, 4);
722 static void si_set_clip_state(struct pipe_context
*ctx
,
723 const struct pipe_clip_state
*state
)
725 struct si_context
*sctx
= (struct si_context
*)ctx
;
726 struct pipe_constant_buffer cb
;
727 static const struct pipe_clip_state zeros
;
729 if (memcmp(&sctx
->clip_state
.state
, state
, sizeof(*state
)) == 0)
732 sctx
->clip_state
.state
= *state
;
733 sctx
->clip_state
.any_nonzeros
= memcmp(state
, &zeros
, sizeof(*state
)) != 0;
734 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_state
);
737 cb
.user_buffer
= state
->ucp
;
738 cb
.buffer_offset
= 0;
739 cb
.buffer_size
= 4*4*8;
740 si_set_rw_buffer(sctx
, SI_VS_CONST_CLIP_PLANES
, &cb
);
741 pipe_resource_reference(&cb
.buffer
, NULL
);
744 static void si_emit_clip_state(struct si_context
*sctx
)
746 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
748 radeon_set_context_reg_seq(cs
, R_0285BC_PA_CL_UCP_0_X
, 6*4);
749 radeon_emit_array(cs
, (uint32_t*)sctx
->clip_state
.state
.ucp
, 6*4);
752 static void si_emit_clip_regs(struct si_context
*sctx
)
754 struct si_shader
*vs
= si_get_vs_state(sctx
);
755 struct si_shader_selector
*vs_sel
= vs
->selector
;
756 struct tgsi_shader_info
*info
= &vs_sel
->info
;
757 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
758 unsigned window_space
=
759 info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
760 unsigned clipdist_mask
= vs_sel
->clipdist_mask
;
761 unsigned ucp_mask
= clipdist_mask
? 0 : rs
->clip_plane_enable
& SIX_BITS
;
762 unsigned culldist_mask
= vs_sel
->culldist_mask
;
765 if (vs
->key
.opt
.clip_disable
) {
766 assert(!info
->culldist_writemask
);
770 total_mask
= clipdist_mask
| culldist_mask
;
772 /* Clip distances on points have no effect, so need to be implemented
773 * as cull distances. This applies for the clipvertex case as well.
775 * Setting this for primitives other than points should have no adverse
778 clipdist_mask
&= rs
->clip_plane_enable
;
779 culldist_mask
|= clipdist_mask
;
781 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
782 radeon_opt_set_context_reg(sctx
, R_02881C_PA_CL_VS_OUT_CNTL
,
783 SI_TRACKED_PA_CL_VS_OUT_CNTL
,
784 vs_sel
->pa_cl_vs_out_cntl
|
785 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0F) != 0) |
786 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xF0) != 0) |
787 clipdist_mask
| (culldist_mask
<< 8));
788 radeon_opt_set_context_reg(sctx
, R_028810_PA_CL_CLIP_CNTL
,
789 SI_TRACKED_PA_CL_CLIP_CNTL
,
790 rs
->pa_cl_clip_cntl
|
792 S_028810_CLIP_DISABLE(window_space
));
794 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
795 sctx
->context_roll_counter
++;
799 * inferred state between framebuffer and rasterizer
801 static void si_update_poly_offset_state(struct si_context
*sctx
)
803 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
805 if (!rs
|| !rs
->uses_poly_offset
|| !sctx
->framebuffer
.state
.zsbuf
) {
806 si_pm4_bind_state(sctx
, poly_offset
, NULL
);
810 /* Use the user format, not db_render_format, so that the polygon
811 * offset behaves as expected by applications.
813 switch (sctx
->framebuffer
.state
.zsbuf
->texture
->format
) {
814 case PIPE_FORMAT_Z16_UNORM
:
815 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[0]);
817 default: /* 24-bit */
818 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[1]);
820 case PIPE_FORMAT_Z32_FLOAT
:
821 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
822 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[2]);
831 static uint32_t si_translate_fill(uint32_t func
)
834 case PIPE_POLYGON_MODE_FILL
:
835 return V_028814_X_DRAW_TRIANGLES
;
836 case PIPE_POLYGON_MODE_LINE
:
837 return V_028814_X_DRAW_LINES
;
838 case PIPE_POLYGON_MODE_POINT
:
839 return V_028814_X_DRAW_POINTS
;
842 return V_028814_X_DRAW_POINTS
;
846 static void *si_create_rs_state(struct pipe_context
*ctx
,
847 const struct pipe_rasterizer_state
*state
)
849 struct si_screen
*sscreen
= ((struct si_context
*)ctx
)->screen
;
850 struct si_state_rasterizer
*rs
= CALLOC_STRUCT(si_state_rasterizer
);
851 struct si_pm4_state
*pm4
= &rs
->pm4
;
853 float psize_min
, psize_max
;
859 rs
->scissor_enable
= state
->scissor
;
860 rs
->clip_halfz
= state
->clip_halfz
;
861 rs
->two_side
= state
->light_twoside
;
862 rs
->multisample_enable
= state
->multisample
;
863 rs
->force_persample_interp
= state
->force_persample_interp
;
864 rs
->clip_plane_enable
= state
->clip_plane_enable
;
865 rs
->half_pixel_center
= state
->half_pixel_center
;
866 rs
->line_stipple_enable
= state
->line_stipple_enable
;
867 rs
->poly_stipple_enable
= state
->poly_stipple_enable
;
868 rs
->line_smooth
= state
->line_smooth
;
869 rs
->line_width
= state
->line_width
;
870 rs
->poly_smooth
= state
->poly_smooth
;
871 rs
->uses_poly_offset
= state
->offset_point
|| state
->offset_line
||
873 rs
->clamp_fragment_color
= state
->clamp_fragment_color
;
874 rs
->clamp_vertex_color
= state
->clamp_vertex_color
;
875 rs
->flatshade
= state
->flatshade
;
876 rs
->sprite_coord_enable
= state
->sprite_coord_enable
;
877 rs
->rasterizer_discard
= state
->rasterizer_discard
;
878 rs
->pa_sc_line_stipple
= state
->line_stipple_enable
?
879 S_028A0C_LINE_PATTERN(state
->line_stipple_pattern
) |
880 S_028A0C_REPEAT_COUNT(state
->line_stipple_factor
) : 0;
881 rs
->pa_cl_clip_cntl
=
882 S_028810_DX_CLIP_SPACE_DEF(state
->clip_halfz
) |
883 S_028810_ZCLIP_NEAR_DISABLE(!state
->depth_clip_near
) |
884 S_028810_ZCLIP_FAR_DISABLE(!state
->depth_clip_far
) |
885 S_028810_DX_RASTERIZATION_KILL(state
->rasterizer_discard
) |
886 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
888 si_pm4_set_reg(pm4
, R_0286D4_SPI_INTERP_CONTROL_0
,
889 S_0286D4_FLAT_SHADE_ENA(1) |
890 S_0286D4_PNT_SPRITE_ENA(state
->point_quad_rasterization
) |
891 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S
) |
892 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T
) |
893 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0
) |
894 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1
) |
895 S_0286D4_PNT_SPRITE_TOP_1(state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
));
897 /* point size 12.4 fixed point */
898 tmp
= (unsigned)(state
->point_size
* 8.0);
899 si_pm4_set_reg(pm4
, R_028A00_PA_SU_POINT_SIZE
, S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
));
901 if (state
->point_size_per_vertex
) {
902 psize_min
= util_get_min_point_size(state
);
903 psize_max
= SI_MAX_POINT_SIZE
;
905 /* Force the point size to be as if the vertex output was disabled. */
906 psize_min
= state
->point_size
;
907 psize_max
= state
->point_size
;
909 rs
->max_point_size
= psize_max
;
911 /* Divide by two, because 0.5 = 1 pixel. */
912 si_pm4_set_reg(pm4
, R_028A04_PA_SU_POINT_MINMAX
,
913 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min
/2)) |
914 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max
/2)));
916 si_pm4_set_reg(pm4
, R_028A08_PA_SU_LINE_CNTL
,
917 S_028A08_WIDTH(si_pack_float_12p4(state
->line_width
/2)));
918 si_pm4_set_reg(pm4
, R_028A48_PA_SC_MODE_CNTL_0
,
919 S_028A48_LINE_STIPPLE_ENABLE(state
->line_stipple_enable
) |
920 S_028A48_MSAA_ENABLE(state
->multisample
||
921 state
->poly_smooth
||
922 state
->line_smooth
) |
923 S_028A48_VPORT_SCISSOR_ENABLE(1) |
924 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen
->info
.chip_class
>= GFX9
));
926 si_pm4_set_reg(pm4
, R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, fui(state
->offset_clamp
));
927 si_pm4_set_reg(pm4
, R_028814_PA_SU_SC_MODE_CNTL
,
928 S_028814_PROVOKING_VTX_LAST(!state
->flatshade_first
) |
929 S_028814_CULL_FRONT((state
->cull_face
& PIPE_FACE_FRONT
) ? 1 : 0) |
930 S_028814_CULL_BACK((state
->cull_face
& PIPE_FACE_BACK
) ? 1 : 0) |
931 S_028814_FACE(!state
->front_ccw
) |
932 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state
, state
->fill_front
)) |
933 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state
, state
->fill_back
)) |
934 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_point
|| state
->offset_line
) |
935 S_028814_POLY_MODE(state
->fill_front
!= PIPE_POLYGON_MODE_FILL
||
936 state
->fill_back
!= PIPE_POLYGON_MODE_FILL
) |
937 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state
->fill_front
)) |
938 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state
->fill_back
)));
940 if (!rs
->uses_poly_offset
)
943 rs
->pm4_poly_offset
= CALLOC(3, sizeof(struct si_pm4_state
));
944 if (!rs
->pm4_poly_offset
) {
949 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
950 for (i
= 0; i
< 3; i
++) {
951 struct si_pm4_state
*pm4
= &rs
->pm4_poly_offset
[i
];
952 float offset_units
= state
->offset_units
;
953 float offset_scale
= state
->offset_scale
* 16.0f
;
954 uint32_t pa_su_poly_offset_db_fmt_cntl
= 0;
956 if (!state
->offset_units_unscaled
) {
958 case 0: /* 16-bit zbuffer */
959 offset_units
*= 4.0f
;
960 pa_su_poly_offset_db_fmt_cntl
=
961 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
963 case 1: /* 24-bit zbuffer */
964 offset_units
*= 2.0f
;
965 pa_su_poly_offset_db_fmt_cntl
=
966 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
968 case 2: /* 32-bit zbuffer */
969 offset_units
*= 1.0f
;
970 pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
971 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
976 si_pm4_set_reg(pm4
, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE
,
978 si_pm4_set_reg(pm4
, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET
,
980 si_pm4_set_reg(pm4
, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE
,
982 si_pm4_set_reg(pm4
, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET
,
984 si_pm4_set_reg(pm4
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
985 pa_su_poly_offset_db_fmt_cntl
);
991 static void si_bind_rs_state(struct pipe_context
*ctx
, void *state
)
993 struct si_context
*sctx
= (struct si_context
*)ctx
;
994 struct si_state_rasterizer
*old_rs
=
995 (struct si_state_rasterizer
*)sctx
->queued
.named
.rasterizer
;
996 struct si_state_rasterizer
*rs
= (struct si_state_rasterizer
*)state
;
1001 if (!old_rs
|| old_rs
->multisample_enable
!= rs
->multisample_enable
) {
1002 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
1004 /* Update the small primitive filter workaround if necessary. */
1005 if (sctx
->screen
->has_msaa_sample_loc_bug
&&
1006 sctx
->framebuffer
.nr_samples
> 1)
1007 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_sample_locs
);
1010 sctx
->current_vs_state
&= C_VS_STATE_CLAMP_VERTEX_COLOR
;
1011 sctx
->current_vs_state
|= S_VS_STATE_CLAMP_VERTEX_COLOR(rs
->clamp_vertex_color
);
1013 si_pm4_bind_state(sctx
, rasterizer
, rs
);
1014 si_update_poly_offset_state(sctx
);
1017 old_rs
->scissor_enable
!= rs
->scissor_enable
) {
1018 sctx
->scissors
.dirty_mask
= (1 << SI_MAX_VIEWPORTS
) - 1;
1019 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.scissors
);
1023 old_rs
->line_width
!= rs
->line_width
||
1024 old_rs
->max_point_size
!= rs
->max_point_size
||
1025 old_rs
->half_pixel_center
!= rs
->half_pixel_center
)
1026 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.guardband
);
1029 old_rs
->clip_halfz
!= rs
->clip_halfz
) {
1030 sctx
->viewports
.depth_range_dirty_mask
= (1 << SI_MAX_VIEWPORTS
) - 1;
1031 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.viewports
);
1035 old_rs
->clip_plane_enable
!= rs
->clip_plane_enable
||
1036 old_rs
->pa_cl_clip_cntl
!= rs
->pa_cl_clip_cntl
)
1037 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_regs
);
1039 sctx
->ia_multi_vgt_param_key
.u
.line_stipple_enabled
=
1040 rs
->line_stipple_enable
;
1043 old_rs
->clip_plane_enable
!= rs
->clip_plane_enable
||
1044 old_rs
->rasterizer_discard
!= rs
->rasterizer_discard
||
1045 old_rs
->sprite_coord_enable
!= rs
->sprite_coord_enable
||
1046 old_rs
->flatshade
!= rs
->flatshade
||
1047 old_rs
->two_side
!= rs
->two_side
||
1048 old_rs
->multisample_enable
!= rs
->multisample_enable
||
1049 old_rs
->poly_stipple_enable
!= rs
->poly_stipple_enable
||
1050 old_rs
->poly_smooth
!= rs
->poly_smooth
||
1051 old_rs
->line_smooth
!= rs
->line_smooth
||
1052 old_rs
->clamp_fragment_color
!= rs
->clamp_fragment_color
||
1053 old_rs
->force_persample_interp
!= rs
->force_persample_interp
)
1054 sctx
->do_update_shaders
= true;
1057 static void si_delete_rs_state(struct pipe_context
*ctx
, void *state
)
1059 struct si_context
*sctx
= (struct si_context
*)ctx
;
1060 struct si_state_rasterizer
*rs
= (struct si_state_rasterizer
*)state
;
1062 if (sctx
->queued
.named
.rasterizer
== state
)
1063 si_pm4_bind_state(sctx
, poly_offset
, NULL
);
1065 FREE(rs
->pm4_poly_offset
);
1066 si_pm4_delete_state(sctx
, rasterizer
, rs
);
1070 * infeered state between dsa and stencil ref
1072 static void si_emit_stencil_ref(struct si_context
*sctx
)
1074 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
1075 struct pipe_stencil_ref
*ref
= &sctx
->stencil_ref
.state
;
1076 struct si_dsa_stencil_ref_part
*dsa
= &sctx
->stencil_ref
.dsa_part
;
1078 radeon_set_context_reg_seq(cs
, R_028430_DB_STENCILREFMASK
, 2);
1079 radeon_emit(cs
, S_028430_STENCILTESTVAL(ref
->ref_value
[0]) |
1080 S_028430_STENCILMASK(dsa
->valuemask
[0]) |
1081 S_028430_STENCILWRITEMASK(dsa
->writemask
[0]) |
1082 S_028430_STENCILOPVAL(1));
1083 radeon_emit(cs
, S_028434_STENCILTESTVAL_BF(ref
->ref_value
[1]) |
1084 S_028434_STENCILMASK_BF(dsa
->valuemask
[1]) |
1085 S_028434_STENCILWRITEMASK_BF(dsa
->writemask
[1]) |
1086 S_028434_STENCILOPVAL_BF(1));
1089 static void si_set_stencil_ref(struct pipe_context
*ctx
,
1090 const struct pipe_stencil_ref
*state
)
1092 struct si_context
*sctx
= (struct si_context
*)ctx
;
1094 if (memcmp(&sctx
->stencil_ref
.state
, state
, sizeof(*state
)) == 0)
1097 sctx
->stencil_ref
.state
= *state
;
1098 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.stencil_ref
);
1106 static uint32_t si_translate_stencil_op(int s_op
)
1109 case PIPE_STENCIL_OP_KEEP
:
1110 return V_02842C_STENCIL_KEEP
;
1111 case PIPE_STENCIL_OP_ZERO
:
1112 return V_02842C_STENCIL_ZERO
;
1113 case PIPE_STENCIL_OP_REPLACE
:
1114 return V_02842C_STENCIL_REPLACE_TEST
;
1115 case PIPE_STENCIL_OP_INCR
:
1116 return V_02842C_STENCIL_ADD_CLAMP
;
1117 case PIPE_STENCIL_OP_DECR
:
1118 return V_02842C_STENCIL_SUB_CLAMP
;
1119 case PIPE_STENCIL_OP_INCR_WRAP
:
1120 return V_02842C_STENCIL_ADD_WRAP
;
1121 case PIPE_STENCIL_OP_DECR_WRAP
:
1122 return V_02842C_STENCIL_SUB_WRAP
;
1123 case PIPE_STENCIL_OP_INVERT
:
1124 return V_02842C_STENCIL_INVERT
;
1126 PRINT_ERR("Unknown stencil op %d", s_op
);
1133 static bool si_dsa_writes_stencil(const struct pipe_stencil_state
*s
)
1135 return s
->enabled
&& s
->writemask
&&
1136 (s
->fail_op
!= PIPE_STENCIL_OP_KEEP
||
1137 s
->zfail_op
!= PIPE_STENCIL_OP_KEEP
||
1138 s
->zpass_op
!= PIPE_STENCIL_OP_KEEP
);
1141 static bool si_order_invariant_stencil_op(enum pipe_stencil_op op
)
1143 /* REPLACE is normally order invariant, except when the stencil
1144 * reference value is written by the fragment shader. Tracking this
1145 * interaction does not seem worth the effort, so be conservative. */
1146 return op
!= PIPE_STENCIL_OP_INCR
&&
1147 op
!= PIPE_STENCIL_OP_DECR
&&
1148 op
!= PIPE_STENCIL_OP_REPLACE
;
1151 /* Compute whether, assuming Z writes are disabled, this stencil state is order
1152 * invariant in the sense that the set of passing fragments as well as the
1153 * final stencil buffer result does not depend on the order of fragments. */
1154 static bool si_order_invariant_stencil_state(const struct pipe_stencil_state
*state
)
1156 return !state
->enabled
|| !state
->writemask
||
1157 /* The following assumes that Z writes are disabled. */
1158 (state
->func
== PIPE_FUNC_ALWAYS
&&
1159 si_order_invariant_stencil_op(state
->zpass_op
) &&
1160 si_order_invariant_stencil_op(state
->zfail_op
)) ||
1161 (state
->func
== PIPE_FUNC_NEVER
&&
1162 si_order_invariant_stencil_op(state
->fail_op
));
1165 static void *si_create_dsa_state(struct pipe_context
*ctx
,
1166 const struct pipe_depth_stencil_alpha_state
*state
)
1168 struct si_context
*sctx
= (struct si_context
*)ctx
;
1169 struct si_state_dsa
*dsa
= CALLOC_STRUCT(si_state_dsa
);
1170 struct si_pm4_state
*pm4
= &dsa
->pm4
;
1171 unsigned db_depth_control
;
1172 uint32_t db_stencil_control
= 0;
1178 dsa
->stencil_ref
.valuemask
[0] = state
->stencil
[0].valuemask
;
1179 dsa
->stencil_ref
.valuemask
[1] = state
->stencil
[1].valuemask
;
1180 dsa
->stencil_ref
.writemask
[0] = state
->stencil
[0].writemask
;
1181 dsa
->stencil_ref
.writemask
[1] = state
->stencil
[1].writemask
;
1183 db_depth_control
= S_028800_Z_ENABLE(state
->depth
.enabled
) |
1184 S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
1185 S_028800_ZFUNC(state
->depth
.func
) |
1186 S_028800_DEPTH_BOUNDS_ENABLE(state
->depth
.bounds_test
);
1189 if (state
->stencil
[0].enabled
) {
1190 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
1191 db_depth_control
|= S_028800_STENCILFUNC(state
->stencil
[0].func
);
1192 db_stencil_control
|= S_02842C_STENCILFAIL(si_translate_stencil_op(state
->stencil
[0].fail_op
));
1193 db_stencil_control
|= S_02842C_STENCILZPASS(si_translate_stencil_op(state
->stencil
[0].zpass_op
));
1194 db_stencil_control
|= S_02842C_STENCILZFAIL(si_translate_stencil_op(state
->stencil
[0].zfail_op
));
1196 if (state
->stencil
[1].enabled
) {
1197 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
1198 db_depth_control
|= S_028800_STENCILFUNC_BF(state
->stencil
[1].func
);
1199 db_stencil_control
|= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state
->stencil
[1].fail_op
));
1200 db_stencil_control
|= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state
->stencil
[1].zpass_op
));
1201 db_stencil_control
|= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state
->stencil
[1].zfail_op
));
1206 if (state
->alpha
.enabled
) {
1207 dsa
->alpha_func
= state
->alpha
.func
;
1209 si_pm4_set_reg(pm4
, R_00B030_SPI_SHADER_USER_DATA_PS_0
+
1210 SI_SGPR_ALPHA_REF
* 4, fui(state
->alpha
.ref_value
));
1212 dsa
->alpha_func
= PIPE_FUNC_ALWAYS
;
1215 si_pm4_set_reg(pm4
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
1216 if (state
->stencil
[0].enabled
)
1217 si_pm4_set_reg(pm4
, R_02842C_DB_STENCIL_CONTROL
, db_stencil_control
);
1218 if (state
->depth
.bounds_test
) {
1219 si_pm4_set_reg(pm4
, R_028020_DB_DEPTH_BOUNDS_MIN
, fui(state
->depth
.bounds_min
));
1220 si_pm4_set_reg(pm4
, R_028024_DB_DEPTH_BOUNDS_MAX
, fui(state
->depth
.bounds_max
));
1223 dsa
->depth_enabled
= state
->depth
.enabled
;
1224 dsa
->depth_write_enabled
= state
->depth
.enabled
&&
1225 state
->depth
.writemask
;
1226 dsa
->stencil_enabled
= state
->stencil
[0].enabled
;
1227 dsa
->stencil_write_enabled
= state
->stencil
[0].enabled
&&
1228 (si_dsa_writes_stencil(&state
->stencil
[0]) ||
1229 si_dsa_writes_stencil(&state
->stencil
[1]));
1230 dsa
->db_can_write
= dsa
->depth_write_enabled
||
1231 dsa
->stencil_write_enabled
;
1233 bool zfunc_is_ordered
=
1234 state
->depth
.func
== PIPE_FUNC_NEVER
||
1235 state
->depth
.func
== PIPE_FUNC_LESS
||
1236 state
->depth
.func
== PIPE_FUNC_LEQUAL
||
1237 state
->depth
.func
== PIPE_FUNC_GREATER
||
1238 state
->depth
.func
== PIPE_FUNC_GEQUAL
;
1240 bool nozwrite_and_order_invariant_stencil
=
1241 !dsa
->db_can_write
||
1242 (!dsa
->depth_write_enabled
&&
1243 si_order_invariant_stencil_state(&state
->stencil
[0]) &&
1244 si_order_invariant_stencil_state(&state
->stencil
[1]));
1246 dsa
->order_invariance
[1].zs
=
1247 nozwrite_and_order_invariant_stencil
||
1248 (!dsa
->stencil_write_enabled
&& zfunc_is_ordered
);
1249 dsa
->order_invariance
[0].zs
= !dsa
->depth_write_enabled
|| zfunc_is_ordered
;
1251 dsa
->order_invariance
[1].pass_set
=
1252 nozwrite_and_order_invariant_stencil
||
1253 (!dsa
->stencil_write_enabled
&&
1254 (state
->depth
.func
== PIPE_FUNC_ALWAYS
||
1255 state
->depth
.func
== PIPE_FUNC_NEVER
));
1256 dsa
->order_invariance
[0].pass_set
=
1257 !dsa
->depth_write_enabled
||
1258 (state
->depth
.func
== PIPE_FUNC_ALWAYS
||
1259 state
->depth
.func
== PIPE_FUNC_NEVER
);
1261 dsa
->order_invariance
[1].pass_last
=
1262 sctx
->screen
->assume_no_z_fights
&&
1263 !dsa
->stencil_write_enabled
&&
1264 dsa
->depth_write_enabled
&& zfunc_is_ordered
;
1265 dsa
->order_invariance
[0].pass_last
=
1266 sctx
->screen
->assume_no_z_fights
&&
1267 dsa
->depth_write_enabled
&& zfunc_is_ordered
;
1272 static void si_bind_dsa_state(struct pipe_context
*ctx
, void *state
)
1274 struct si_context
*sctx
= (struct si_context
*)ctx
;
1275 struct si_state_dsa
*old_dsa
= sctx
->queued
.named
.dsa
;
1276 struct si_state_dsa
*dsa
= state
;
1281 si_pm4_bind_state(sctx
, dsa
, dsa
);
1283 if (memcmp(&dsa
->stencil_ref
, &sctx
->stencil_ref
.dsa_part
,
1284 sizeof(struct si_dsa_stencil_ref_part
)) != 0) {
1285 sctx
->stencil_ref
.dsa_part
= dsa
->stencil_ref
;
1286 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.stencil_ref
);
1289 if (!old_dsa
|| old_dsa
->alpha_func
!= dsa
->alpha_func
)
1290 sctx
->do_update_shaders
= true;
1292 if (sctx
->screen
->dpbb_allowed
&&
1294 (old_dsa
->depth_enabled
!= dsa
->depth_enabled
||
1295 old_dsa
->stencil_enabled
!= dsa
->stencil_enabled
||
1296 old_dsa
->db_can_write
!= dsa
->db_can_write
)))
1297 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
1299 if (sctx
->screen
->has_out_of_order_rast
&&
1301 memcmp(old_dsa
->order_invariance
, dsa
->order_invariance
,
1302 sizeof(old_dsa
->order_invariance
))))
1303 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
1306 static void si_delete_dsa_state(struct pipe_context
*ctx
, void *state
)
1308 struct si_context
*sctx
= (struct si_context
*)ctx
;
1309 si_pm4_delete_state(sctx
, dsa
, (struct si_state_dsa
*)state
);
1312 static void *si_create_db_flush_dsa(struct si_context
*sctx
)
1314 struct pipe_depth_stencil_alpha_state dsa
= {};
1316 return sctx
->b
.create_depth_stencil_alpha_state(&sctx
->b
, &dsa
);
1319 /* DB RENDER STATE */
1321 static void si_set_active_query_state(struct pipe_context
*ctx
, boolean enable
)
1323 struct si_context
*sctx
= (struct si_context
*)ctx
;
1325 /* Pipeline stat & streamout queries. */
1327 sctx
->flags
&= ~SI_CONTEXT_STOP_PIPELINE_STATS
;
1328 sctx
->flags
|= SI_CONTEXT_START_PIPELINE_STATS
;
1330 sctx
->flags
&= ~SI_CONTEXT_START_PIPELINE_STATS
;
1331 sctx
->flags
|= SI_CONTEXT_STOP_PIPELINE_STATS
;
1334 /* Occlusion queries. */
1335 if (sctx
->occlusion_queries_disabled
!= !enable
) {
1336 sctx
->occlusion_queries_disabled
= !enable
;
1337 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
1341 void si_set_occlusion_query_state(struct si_context
*sctx
,
1342 bool old_perfect_enable
)
1344 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
1346 bool perfect_enable
= sctx
->num_perfect_occlusion_queries
!= 0;
1348 if (perfect_enable
!= old_perfect_enable
)
1349 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
1352 void si_save_qbo_state(struct si_context
*sctx
, struct si_qbo_state
*st
)
1354 st
->saved_compute
= sctx
->cs_shader_state
.program
;
1356 si_get_pipe_constant_buffer(sctx
, PIPE_SHADER_COMPUTE
, 0, &st
->saved_const0
);
1357 si_get_shader_buffers(sctx
, PIPE_SHADER_COMPUTE
, 0, 3, st
->saved_ssbo
);
1360 static void si_emit_db_render_state(struct si_context
*sctx
)
1362 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
1363 unsigned db_shader_control
, db_render_control
, db_count_control
;
1364 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1366 /* DB_RENDER_CONTROL */
1367 if (sctx
->dbcb_depth_copy_enabled
||
1368 sctx
->dbcb_stencil_copy_enabled
) {
1370 S_028000_DEPTH_COPY(sctx
->dbcb_depth_copy_enabled
) |
1371 S_028000_STENCIL_COPY(sctx
->dbcb_stencil_copy_enabled
) |
1372 S_028000_COPY_CENTROID(1) |
1373 S_028000_COPY_SAMPLE(sctx
->dbcb_copy_sample
);
1374 } else if (sctx
->db_flush_depth_inplace
|| sctx
->db_flush_stencil_inplace
) {
1376 S_028000_DEPTH_COMPRESS_DISABLE(sctx
->db_flush_depth_inplace
) |
1377 S_028000_STENCIL_COMPRESS_DISABLE(sctx
->db_flush_stencil_inplace
);
1380 S_028000_DEPTH_CLEAR_ENABLE(sctx
->db_depth_clear
) |
1381 S_028000_STENCIL_CLEAR_ENABLE(sctx
->db_stencil_clear
);
1384 /* DB_COUNT_CONTROL (occlusion queries) */
1385 if (sctx
->num_occlusion_queries
> 0 &&
1386 !sctx
->occlusion_queries_disabled
) {
1387 bool perfect
= sctx
->num_perfect_occlusion_queries
> 0;
1389 if (sctx
->chip_class
>= CIK
) {
1390 unsigned log_sample_rate
= sctx
->framebuffer
.log_samples
;
1392 /* Stoney doesn't increment occlusion query counters
1393 * if the sample rate is 16x. Use 8x sample rate instead.
1395 if (sctx
->family
== CHIP_STONEY
)
1396 log_sample_rate
= MIN2(log_sample_rate
, 3);
1399 S_028004_PERFECT_ZPASS_COUNTS(perfect
) |
1400 S_028004_SAMPLE_RATE(log_sample_rate
) |
1401 S_028004_ZPASS_ENABLE(1) |
1402 S_028004_SLICE_EVEN_ENABLE(1) |
1403 S_028004_SLICE_ODD_ENABLE(1);
1406 S_028004_PERFECT_ZPASS_COUNTS(perfect
) |
1407 S_028004_SAMPLE_RATE(sctx
->framebuffer
.log_samples
);
1410 /* Disable occlusion queries. */
1411 if (sctx
->chip_class
>= CIK
) {
1412 db_count_control
= 0;
1414 db_count_control
= S_028004_ZPASS_INCREMENT_DISABLE(1);
1418 radeon_opt_set_context_reg2(sctx
, R_028000_DB_RENDER_CONTROL
,
1419 SI_TRACKED_DB_RENDER_CONTROL
, db_render_control
,
1422 /* DB_RENDER_OVERRIDE2 */
1423 radeon_opt_set_context_reg(sctx
, R_028010_DB_RENDER_OVERRIDE2
,
1424 SI_TRACKED_DB_RENDER_OVERRIDE2
,
1425 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx
->db_depth_disable_expclear
) |
1426 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx
->db_stencil_disable_expclear
) |
1427 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx
->framebuffer
.nr_samples
>= 4));
1429 db_shader_control
= sctx
->ps_db_shader_control
;
1431 /* Bug workaround for smoothing (overrasterization) on SI. */
1432 if (sctx
->chip_class
== SI
&& sctx
->smoothing_enabled
) {
1433 db_shader_control
&= C_02880C_Z_ORDER
;
1434 db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
);
1437 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1438 if (!rs
->multisample_enable
)
1439 db_shader_control
&= C_02880C_MASK_EXPORT_ENABLE
;
1441 if (sctx
->screen
->has_rbplus
&&
1442 !sctx
->screen
->rbplus_allowed
)
1443 db_shader_control
|= S_02880C_DUAL_QUAD_DISABLE(1);
1445 radeon_opt_set_context_reg(sctx
, R_02880C_DB_SHADER_CONTROL
,
1446 SI_TRACKED_DB_SHADER_CONTROL
, db_shader_control
);
1448 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
1449 sctx
->context_roll_counter
++;
1453 * format translation
1455 static uint32_t si_translate_colorformat(enum pipe_format format
)
1457 const struct util_format_description
*desc
= util_format_description(format
);
1459 return V_028C70_COLOR_INVALID
;
1461 #define HAS_SIZE(x,y,z,w) \
1462 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1463 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1465 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
1466 return V_028C70_COLOR_10_11_11
;
1468 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
1469 return V_028C70_COLOR_INVALID
;
1471 /* hw cannot support mixed formats (except depth/stencil, since
1472 * stencil is not written to). */
1473 if (desc
->is_mixed
&& desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
)
1474 return V_028C70_COLOR_INVALID
;
1476 switch (desc
->nr_channels
) {
1478 switch (desc
->channel
[0].size
) {
1480 return V_028C70_COLOR_8
;
1482 return V_028C70_COLOR_16
;
1484 return V_028C70_COLOR_32
;
1488 if (desc
->channel
[0].size
== desc
->channel
[1].size
) {
1489 switch (desc
->channel
[0].size
) {
1491 return V_028C70_COLOR_8_8
;
1493 return V_028C70_COLOR_16_16
;
1495 return V_028C70_COLOR_32_32
;
1497 } else if (HAS_SIZE(8,24,0,0)) {
1498 return V_028C70_COLOR_24_8
;
1499 } else if (HAS_SIZE(24,8,0,0)) {
1500 return V_028C70_COLOR_8_24
;
1504 if (HAS_SIZE(5,6,5,0)) {
1505 return V_028C70_COLOR_5_6_5
;
1506 } else if (HAS_SIZE(32,8,24,0)) {
1507 return V_028C70_COLOR_X24_8_32_FLOAT
;
1511 if (desc
->channel
[0].size
== desc
->channel
[1].size
&&
1512 desc
->channel
[0].size
== desc
->channel
[2].size
&&
1513 desc
->channel
[0].size
== desc
->channel
[3].size
) {
1514 switch (desc
->channel
[0].size
) {
1516 return V_028C70_COLOR_4_4_4_4
;
1518 return V_028C70_COLOR_8_8_8_8
;
1520 return V_028C70_COLOR_16_16_16_16
;
1522 return V_028C70_COLOR_32_32_32_32
;
1524 } else if (HAS_SIZE(5,5,5,1)) {
1525 return V_028C70_COLOR_1_5_5_5
;
1526 } else if (HAS_SIZE(1,5,5,5)) {
1527 return V_028C70_COLOR_5_5_5_1
;
1528 } else if (HAS_SIZE(10,10,10,2)) {
1529 return V_028C70_COLOR_2_10_10_10
;
1533 return V_028C70_COLOR_INVALID
;
1536 static uint32_t si_colorformat_endian_swap(uint32_t colorformat
)
1538 if (SI_BIG_ENDIAN
) {
1539 switch(colorformat
) {
1540 /* 8-bit buffers. */
1541 case V_028C70_COLOR_8
:
1542 return V_028C70_ENDIAN_NONE
;
1544 /* 16-bit buffers. */
1545 case V_028C70_COLOR_5_6_5
:
1546 case V_028C70_COLOR_1_5_5_5
:
1547 case V_028C70_COLOR_4_4_4_4
:
1548 case V_028C70_COLOR_16
:
1549 case V_028C70_COLOR_8_8
:
1550 return V_028C70_ENDIAN_8IN16
;
1552 /* 32-bit buffers. */
1553 case V_028C70_COLOR_8_8_8_8
:
1554 case V_028C70_COLOR_2_10_10_10
:
1555 case V_028C70_COLOR_8_24
:
1556 case V_028C70_COLOR_24_8
:
1557 case V_028C70_COLOR_16_16
:
1558 return V_028C70_ENDIAN_8IN32
;
1560 /* 64-bit buffers. */
1561 case V_028C70_COLOR_16_16_16_16
:
1562 return V_028C70_ENDIAN_8IN16
;
1564 case V_028C70_COLOR_32_32
:
1565 return V_028C70_ENDIAN_8IN32
;
1567 /* 128-bit buffers. */
1568 case V_028C70_COLOR_32_32_32_32
:
1569 return V_028C70_ENDIAN_8IN32
;
1571 return V_028C70_ENDIAN_NONE
; /* Unsupported. */
1574 return V_028C70_ENDIAN_NONE
;
1578 static uint32_t si_translate_dbformat(enum pipe_format format
)
1581 case PIPE_FORMAT_Z16_UNORM
:
1582 return V_028040_Z_16
;
1583 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1584 case PIPE_FORMAT_X8Z24_UNORM
:
1585 case PIPE_FORMAT_Z24X8_UNORM
:
1586 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1587 return V_028040_Z_24
; /* deprecated on SI */
1588 case PIPE_FORMAT_Z32_FLOAT
:
1589 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1590 return V_028040_Z_32_FLOAT
;
1592 return V_028040_Z_INVALID
;
1597 * Texture translation
1600 static uint32_t si_translate_texformat(struct pipe_screen
*screen
,
1601 enum pipe_format format
,
1602 const struct util_format_description
*desc
,
1605 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1606 bool uniform
= true;
1609 /* Colorspace (return non-RGB formats directly). */
1610 switch (desc
->colorspace
) {
1611 /* Depth stencil formats */
1612 case UTIL_FORMAT_COLORSPACE_ZS
:
1614 case PIPE_FORMAT_Z16_UNORM
:
1615 return V_008F14_IMG_DATA_FORMAT_16
;
1616 case PIPE_FORMAT_X24S8_UINT
:
1617 case PIPE_FORMAT_S8X24_UINT
:
1619 * Implemented as an 8_8_8_8 data format to fix texture
1620 * gathers in stencil sampling. This affects at least
1621 * GL45-CTS.texture_cube_map_array.sampling on VI.
1623 if (sscreen
->info
.chip_class
<= VI
)
1624 return V_008F14_IMG_DATA_FORMAT_8_8_8_8
;
1626 if (format
== PIPE_FORMAT_X24S8_UINT
)
1627 return V_008F14_IMG_DATA_FORMAT_8_24
;
1629 return V_008F14_IMG_DATA_FORMAT_24_8
;
1630 case PIPE_FORMAT_Z24X8_UNORM
:
1631 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1632 return V_008F14_IMG_DATA_FORMAT_8_24
;
1633 case PIPE_FORMAT_X8Z24_UNORM
:
1634 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1635 return V_008F14_IMG_DATA_FORMAT_24_8
;
1636 case PIPE_FORMAT_S8_UINT
:
1637 return V_008F14_IMG_DATA_FORMAT_8
;
1638 case PIPE_FORMAT_Z32_FLOAT
:
1639 return V_008F14_IMG_DATA_FORMAT_32
;
1640 case PIPE_FORMAT_X32_S8X24_UINT
:
1641 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1642 return V_008F14_IMG_DATA_FORMAT_X24_8_32
;
1647 case UTIL_FORMAT_COLORSPACE_YUV
:
1648 goto out_unknown
; /* TODO */
1650 case UTIL_FORMAT_COLORSPACE_SRGB
:
1651 if (desc
->nr_channels
!= 4 && desc
->nr_channels
!= 1)
1659 if (desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
) {
1660 if (!sscreen
->info
.has_format_bc1_through_bc7
)
1664 case PIPE_FORMAT_RGTC1_SNORM
:
1665 case PIPE_FORMAT_LATC1_SNORM
:
1666 case PIPE_FORMAT_RGTC1_UNORM
:
1667 case PIPE_FORMAT_LATC1_UNORM
:
1668 return V_008F14_IMG_DATA_FORMAT_BC4
;
1669 case PIPE_FORMAT_RGTC2_SNORM
:
1670 case PIPE_FORMAT_LATC2_SNORM
:
1671 case PIPE_FORMAT_RGTC2_UNORM
:
1672 case PIPE_FORMAT_LATC2_UNORM
:
1673 return V_008F14_IMG_DATA_FORMAT_BC5
;
1679 if (desc
->layout
== UTIL_FORMAT_LAYOUT_ETC
&&
1680 (sscreen
->info
.family
== CHIP_STONEY
||
1681 sscreen
->info
.family
== CHIP_VEGA10
||
1682 sscreen
->info
.family
== CHIP_RAVEN
)) {
1684 case PIPE_FORMAT_ETC1_RGB8
:
1685 case PIPE_FORMAT_ETC2_RGB8
:
1686 case PIPE_FORMAT_ETC2_SRGB8
:
1687 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB
;
1688 case PIPE_FORMAT_ETC2_RGB8A1
:
1689 case PIPE_FORMAT_ETC2_SRGB8A1
:
1690 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1
;
1691 case PIPE_FORMAT_ETC2_RGBA8
:
1692 case PIPE_FORMAT_ETC2_SRGBA8
:
1693 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA
;
1694 case PIPE_FORMAT_ETC2_R11_UNORM
:
1695 case PIPE_FORMAT_ETC2_R11_SNORM
:
1696 return V_008F14_IMG_DATA_FORMAT_ETC2_R
;
1697 case PIPE_FORMAT_ETC2_RG11_UNORM
:
1698 case PIPE_FORMAT_ETC2_RG11_SNORM
:
1699 return V_008F14_IMG_DATA_FORMAT_ETC2_RG
;
1705 if (desc
->layout
== UTIL_FORMAT_LAYOUT_BPTC
) {
1706 if (!sscreen
->info
.has_format_bc1_through_bc7
)
1710 case PIPE_FORMAT_BPTC_RGBA_UNORM
:
1711 case PIPE_FORMAT_BPTC_SRGBA
:
1712 return V_008F14_IMG_DATA_FORMAT_BC7
;
1713 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
1714 case PIPE_FORMAT_BPTC_RGB_UFLOAT
:
1715 return V_008F14_IMG_DATA_FORMAT_BC6
;
1721 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
1723 case PIPE_FORMAT_R8G8_B8G8_UNORM
:
1724 case PIPE_FORMAT_G8R8_B8R8_UNORM
:
1725 return V_008F14_IMG_DATA_FORMAT_GB_GR
;
1726 case PIPE_FORMAT_G8R8_G8B8_UNORM
:
1727 case PIPE_FORMAT_R8G8_R8B8_UNORM
:
1728 return V_008F14_IMG_DATA_FORMAT_BG_RG
;
1734 if (desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
1735 if (!sscreen
->info
.has_format_bc1_through_bc7
)
1739 case PIPE_FORMAT_DXT1_RGB
:
1740 case PIPE_FORMAT_DXT1_RGBA
:
1741 case PIPE_FORMAT_DXT1_SRGB
:
1742 case PIPE_FORMAT_DXT1_SRGBA
:
1743 return V_008F14_IMG_DATA_FORMAT_BC1
;
1744 case PIPE_FORMAT_DXT3_RGBA
:
1745 case PIPE_FORMAT_DXT3_SRGBA
:
1746 return V_008F14_IMG_DATA_FORMAT_BC2
;
1747 case PIPE_FORMAT_DXT5_RGBA
:
1748 case PIPE_FORMAT_DXT5_SRGBA
:
1749 return V_008F14_IMG_DATA_FORMAT_BC3
;
1755 if (format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
1756 return V_008F14_IMG_DATA_FORMAT_5_9_9_9
;
1757 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
1758 return V_008F14_IMG_DATA_FORMAT_10_11_11
;
1761 /* R8G8Bx_SNORM - TODO CxV8U8 */
1763 /* hw cannot support mixed formats (except depth/stencil, since only
1765 if (desc
->is_mixed
&& desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
)
1768 /* See whether the components are of the same size. */
1769 for (i
= 1; i
< desc
->nr_channels
; i
++) {
1770 uniform
= uniform
&& desc
->channel
[0].size
== desc
->channel
[i
].size
;
1773 /* Non-uniform formats. */
1775 switch(desc
->nr_channels
) {
1777 if (desc
->channel
[0].size
== 5 &&
1778 desc
->channel
[1].size
== 6 &&
1779 desc
->channel
[2].size
== 5) {
1780 return V_008F14_IMG_DATA_FORMAT_5_6_5
;
1784 if (desc
->channel
[0].size
== 5 &&
1785 desc
->channel
[1].size
== 5 &&
1786 desc
->channel
[2].size
== 5 &&
1787 desc
->channel
[3].size
== 1) {
1788 return V_008F14_IMG_DATA_FORMAT_1_5_5_5
;
1790 if (desc
->channel
[0].size
== 1 &&
1791 desc
->channel
[1].size
== 5 &&
1792 desc
->channel
[2].size
== 5 &&
1793 desc
->channel
[3].size
== 5) {
1794 return V_008F14_IMG_DATA_FORMAT_5_5_5_1
;
1796 if (desc
->channel
[0].size
== 10 &&
1797 desc
->channel
[1].size
== 10 &&
1798 desc
->channel
[2].size
== 10 &&
1799 desc
->channel
[3].size
== 2) {
1800 return V_008F14_IMG_DATA_FORMAT_2_10_10_10
;
1807 if (first_non_void
< 0 || first_non_void
> 3)
1810 /* uniform formats */
1811 switch (desc
->channel
[first_non_void
].size
) {
1813 switch (desc
->nr_channels
) {
1814 #if 0 /* Not supported for render targets */
1816 return V_008F14_IMG_DATA_FORMAT_4_4
;
1819 return V_008F14_IMG_DATA_FORMAT_4_4_4_4
;
1823 switch (desc
->nr_channels
) {
1825 return V_008F14_IMG_DATA_FORMAT_8
;
1827 return V_008F14_IMG_DATA_FORMAT_8_8
;
1829 return V_008F14_IMG_DATA_FORMAT_8_8_8_8
;
1833 switch (desc
->nr_channels
) {
1835 return V_008F14_IMG_DATA_FORMAT_16
;
1837 return V_008F14_IMG_DATA_FORMAT_16_16
;
1839 return V_008F14_IMG_DATA_FORMAT_16_16_16_16
;
1843 switch (desc
->nr_channels
) {
1845 return V_008F14_IMG_DATA_FORMAT_32
;
1847 return V_008F14_IMG_DATA_FORMAT_32_32
;
1848 #if 0 /* Not supported for render targets */
1850 return V_008F14_IMG_DATA_FORMAT_32_32_32
;
1853 return V_008F14_IMG_DATA_FORMAT_32_32_32_32
;
1861 static unsigned si_tex_wrap(unsigned wrap
)
1865 case PIPE_TEX_WRAP_REPEAT
:
1866 return V_008F30_SQ_TEX_WRAP
;
1867 case PIPE_TEX_WRAP_CLAMP
:
1868 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER
;
1869 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
1870 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL
;
1871 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
1872 return V_008F30_SQ_TEX_CLAMP_BORDER
;
1873 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
1874 return V_008F30_SQ_TEX_MIRROR
;
1875 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
1876 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
1877 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
1878 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
1879 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
1880 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER
;
1884 static unsigned si_tex_mipfilter(unsigned filter
)
1887 case PIPE_TEX_MIPFILTER_NEAREST
:
1888 return V_008F38_SQ_TEX_Z_FILTER_POINT
;
1889 case PIPE_TEX_MIPFILTER_LINEAR
:
1890 return V_008F38_SQ_TEX_Z_FILTER_LINEAR
;
1892 case PIPE_TEX_MIPFILTER_NONE
:
1893 return V_008F38_SQ_TEX_Z_FILTER_NONE
;
1897 static unsigned si_tex_compare(unsigned compare
)
1901 case PIPE_FUNC_NEVER
:
1902 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
1903 case PIPE_FUNC_LESS
:
1904 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS
;
1905 case PIPE_FUNC_EQUAL
:
1906 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL
;
1907 case PIPE_FUNC_LEQUAL
:
1908 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
1909 case PIPE_FUNC_GREATER
:
1910 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER
;
1911 case PIPE_FUNC_NOTEQUAL
:
1912 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
1913 case PIPE_FUNC_GEQUAL
:
1914 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
1915 case PIPE_FUNC_ALWAYS
:
1916 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
1920 static unsigned si_tex_dim(struct si_screen
*sscreen
, struct si_texture
*tex
,
1921 unsigned view_target
, unsigned nr_samples
)
1923 unsigned res_target
= tex
->buffer
.b
.b
.target
;
1925 if (view_target
== PIPE_TEXTURE_CUBE
||
1926 view_target
== PIPE_TEXTURE_CUBE_ARRAY
)
1927 res_target
= view_target
;
1928 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1929 else if (res_target
== PIPE_TEXTURE_CUBE
||
1930 res_target
== PIPE_TEXTURE_CUBE_ARRAY
)
1931 res_target
= PIPE_TEXTURE_2D_ARRAY
;
1933 /* GFX9 allocates 1D textures as 2D. */
1934 if ((res_target
== PIPE_TEXTURE_1D
||
1935 res_target
== PIPE_TEXTURE_1D_ARRAY
) &&
1936 sscreen
->info
.chip_class
>= GFX9
&&
1937 tex
->surface
.u
.gfx9
.resource_type
== RADEON_RESOURCE_2D
) {
1938 if (res_target
== PIPE_TEXTURE_1D
)
1939 res_target
= PIPE_TEXTURE_2D
;
1941 res_target
= PIPE_TEXTURE_2D_ARRAY
;
1944 switch (res_target
) {
1946 case PIPE_TEXTURE_1D
:
1947 return V_008F1C_SQ_RSRC_IMG_1D
;
1948 case PIPE_TEXTURE_1D_ARRAY
:
1949 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY
;
1950 case PIPE_TEXTURE_2D
:
1951 case PIPE_TEXTURE_RECT
:
1952 return nr_samples
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA
:
1953 V_008F1C_SQ_RSRC_IMG_2D
;
1954 case PIPE_TEXTURE_2D_ARRAY
:
1955 return nr_samples
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
:
1956 V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
1957 case PIPE_TEXTURE_3D
:
1958 return V_008F1C_SQ_RSRC_IMG_3D
;
1959 case PIPE_TEXTURE_CUBE
:
1960 case PIPE_TEXTURE_CUBE_ARRAY
:
1961 return V_008F1C_SQ_RSRC_IMG_CUBE
;
1966 * Format support testing
1969 static bool si_is_sampler_format_supported(struct pipe_screen
*screen
, enum pipe_format format
)
1971 const struct util_format_description
*desc
= util_format_description(format
);
1975 return si_translate_texformat(screen
, format
, desc
,
1976 util_format_get_first_non_void_channel(format
)) != ~0U;
1979 static uint32_t si_translate_buffer_dataformat(struct pipe_screen
*screen
,
1980 const struct util_format_description
*desc
,
1985 if (desc
->format
== PIPE_FORMAT_R11G11B10_FLOAT
)
1986 return V_008F0C_BUF_DATA_FORMAT_10_11_11
;
1988 assert(first_non_void
>= 0);
1990 if (desc
->nr_channels
== 4 &&
1991 desc
->channel
[0].size
== 10 &&
1992 desc
->channel
[1].size
== 10 &&
1993 desc
->channel
[2].size
== 10 &&
1994 desc
->channel
[3].size
== 2)
1995 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10
;
1997 /* See whether the components are of the same size. */
1998 for (i
= 0; i
< desc
->nr_channels
; i
++) {
1999 if (desc
->channel
[first_non_void
].size
!= desc
->channel
[i
].size
)
2000 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
2003 switch (desc
->channel
[first_non_void
].size
) {
2005 switch (desc
->nr_channels
) {
2007 case 3: /* 3 loads */
2008 return V_008F0C_BUF_DATA_FORMAT_8
;
2010 return V_008F0C_BUF_DATA_FORMAT_8_8
;
2012 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8
;
2016 switch (desc
->nr_channels
) {
2018 case 3: /* 3 loads */
2019 return V_008F0C_BUF_DATA_FORMAT_16
;
2021 return V_008F0C_BUF_DATA_FORMAT_16_16
;
2023 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16
;
2027 switch (desc
->nr_channels
) {
2029 return V_008F0C_BUF_DATA_FORMAT_32
;
2031 return V_008F0C_BUF_DATA_FORMAT_32_32
;
2033 return V_008F0C_BUF_DATA_FORMAT_32_32_32
;
2035 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
2039 /* Legacy double formats. */
2040 switch (desc
->nr_channels
) {
2041 case 1: /* 1 load */
2042 return V_008F0C_BUF_DATA_FORMAT_32_32
;
2043 case 2: /* 1 load */
2044 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
2045 case 3: /* 3 loads */
2046 return V_008F0C_BUF_DATA_FORMAT_32_32
;
2047 case 4: /* 2 loads */
2048 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
2053 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
2056 static uint32_t si_translate_buffer_numformat(struct pipe_screen
*screen
,
2057 const struct util_format_description
*desc
,
2060 if (desc
->format
== PIPE_FORMAT_R11G11B10_FLOAT
)
2061 return V_008F0C_BUF_NUM_FORMAT_FLOAT
;
2063 assert(first_non_void
>= 0);
2065 switch (desc
->channel
[first_non_void
].type
) {
2066 case UTIL_FORMAT_TYPE_SIGNED
:
2067 case UTIL_FORMAT_TYPE_FIXED
:
2068 if (desc
->channel
[first_non_void
].size
>= 32 ||
2069 desc
->channel
[first_non_void
].pure_integer
)
2070 return V_008F0C_BUF_NUM_FORMAT_SINT
;
2071 else if (desc
->channel
[first_non_void
].normalized
)
2072 return V_008F0C_BUF_NUM_FORMAT_SNORM
;
2074 return V_008F0C_BUF_NUM_FORMAT_SSCALED
;
2076 case UTIL_FORMAT_TYPE_UNSIGNED
:
2077 if (desc
->channel
[first_non_void
].size
>= 32 ||
2078 desc
->channel
[first_non_void
].pure_integer
)
2079 return V_008F0C_BUF_NUM_FORMAT_UINT
;
2080 else if (desc
->channel
[first_non_void
].normalized
)
2081 return V_008F0C_BUF_NUM_FORMAT_UNORM
;
2083 return V_008F0C_BUF_NUM_FORMAT_USCALED
;
2085 case UTIL_FORMAT_TYPE_FLOAT
:
2087 return V_008F0C_BUF_NUM_FORMAT_FLOAT
;
2091 static unsigned si_is_vertex_format_supported(struct pipe_screen
*screen
,
2092 enum pipe_format format
,
2095 const struct util_format_description
*desc
;
2097 unsigned data_format
;
2099 assert((usage
& ~(PIPE_BIND_SHADER_IMAGE
|
2100 PIPE_BIND_SAMPLER_VIEW
|
2101 PIPE_BIND_VERTEX_BUFFER
)) == 0);
2103 desc
= util_format_description(format
);
2107 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
2108 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
2109 * for read-only access (with caveats surrounding bounds checks), but
2110 * obviously fails for write access which we have to implement for
2111 * shader images. Luckily, OpenGL doesn't expect this to be supported
2112 * anyway, and so the only impact is on PBO uploads / downloads, which
2113 * shouldn't be expected to be fast for GL_RGB anyway.
2115 if (desc
->block
.bits
== 3 * 8 ||
2116 desc
->block
.bits
== 3 * 16) {
2117 if (usage
& (PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SAMPLER_VIEW
)) {
2118 usage
&= ~(PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SAMPLER_VIEW
);
2124 first_non_void
= util_format_get_first_non_void_channel(format
);
2125 data_format
= si_translate_buffer_dataformat(screen
, desc
, first_non_void
);
2126 if (data_format
== V_008F0C_BUF_DATA_FORMAT_INVALID
)
2132 static bool si_is_colorbuffer_format_supported(enum pipe_format format
)
2134 return si_translate_colorformat(format
) != V_028C70_COLOR_INVALID
&&
2135 si_translate_colorswap(format
, false) != ~0U;
2138 static bool si_is_zs_format_supported(enum pipe_format format
)
2140 return si_translate_dbformat(format
) != V_028040_Z_INVALID
;
2143 static boolean
si_is_format_supported(struct pipe_screen
*screen
,
2144 enum pipe_format format
,
2145 enum pipe_texture_target target
,
2146 unsigned sample_count
,
2147 unsigned storage_sample_count
,
2150 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2151 unsigned retval
= 0;
2153 if (target
>= PIPE_MAX_TEXTURE_TYPES
) {
2154 PRINT_ERR("radeonsi: unsupported texture type %d\n", target
);
2158 if (MAX2(1, sample_count
) < MAX2(1, storage_sample_count
))
2161 if (sample_count
> 1) {
2162 if (!screen
->get_param(screen
, PIPE_CAP_TEXTURE_MULTISAMPLE
))
2165 if (usage
& PIPE_BIND_SHADER_IMAGE
)
2168 /* Only power-of-two sample counts are supported. */
2169 if (!util_is_power_of_two_or_zero(sample_count
) ||
2170 !util_is_power_of_two_or_zero(storage_sample_count
))
2173 /* MSAA support without framebuffer attachments. */
2174 if (format
== PIPE_FORMAT_NONE
&& sample_count
<= 16)
2177 if (!sscreen
->info
.has_eqaa_surface_allocator
||
2178 util_format_is_depth_or_stencil(format
)) {
2179 /* Color without EQAA or depth/stencil. */
2180 if (sample_count
> 8 ||
2181 sample_count
!= storage_sample_count
)
2184 /* Color with EQAA. */
2185 if (sample_count
> 16 ||
2186 storage_sample_count
> 8)
2191 if (usage
& (PIPE_BIND_SAMPLER_VIEW
|
2192 PIPE_BIND_SHADER_IMAGE
)) {
2193 if (target
== PIPE_BUFFER
) {
2194 retval
|= si_is_vertex_format_supported(
2195 screen
, format
, usage
& (PIPE_BIND_SAMPLER_VIEW
|
2196 PIPE_BIND_SHADER_IMAGE
));
2198 if (si_is_sampler_format_supported(screen
, format
))
2199 retval
|= usage
& (PIPE_BIND_SAMPLER_VIEW
|
2200 PIPE_BIND_SHADER_IMAGE
);
2204 if ((usage
& (PIPE_BIND_RENDER_TARGET
|
2205 PIPE_BIND_DISPLAY_TARGET
|
2208 PIPE_BIND_BLENDABLE
)) &&
2209 si_is_colorbuffer_format_supported(format
)) {
2211 (PIPE_BIND_RENDER_TARGET
|
2212 PIPE_BIND_DISPLAY_TARGET
|
2215 if (!util_format_is_pure_integer(format
) &&
2216 !util_format_is_depth_or_stencil(format
))
2217 retval
|= usage
& PIPE_BIND_BLENDABLE
;
2220 if ((usage
& PIPE_BIND_DEPTH_STENCIL
) &&
2221 si_is_zs_format_supported(format
)) {
2222 retval
|= PIPE_BIND_DEPTH_STENCIL
;
2225 if (usage
& PIPE_BIND_VERTEX_BUFFER
) {
2226 retval
|= si_is_vertex_format_supported(screen
, format
,
2227 PIPE_BIND_VERTEX_BUFFER
);
2230 if ((usage
& PIPE_BIND_LINEAR
) &&
2231 !util_format_is_compressed(format
) &&
2232 !(usage
& PIPE_BIND_DEPTH_STENCIL
))
2233 retval
|= PIPE_BIND_LINEAR
;
2235 return retval
== usage
;
2239 * framebuffer handling
2242 static void si_choose_spi_color_formats(struct si_surface
*surf
,
2243 unsigned format
, unsigned swap
,
2244 unsigned ntype
, bool is_depth
)
2246 /* Alpha is needed for alpha-to-coverage.
2247 * Blending may be with or without alpha.
2249 unsigned normal
= 0; /* most optimal, may not support blending or export alpha */
2250 unsigned alpha
= 0; /* exports alpha, but may not support blending */
2251 unsigned blend
= 0; /* supports blending, but may not export alpha */
2252 unsigned blend_alpha
= 0; /* least optimal, supports blending and exports alpha */
2254 /* Choose the SPI color formats. These are required values for RB+.
2255 * Other chips have multiple choices, though they are not necessarily better.
2258 case V_028C70_COLOR_5_6_5
:
2259 case V_028C70_COLOR_1_5_5_5
:
2260 case V_028C70_COLOR_5_5_5_1
:
2261 case V_028C70_COLOR_4_4_4_4
:
2262 case V_028C70_COLOR_10_11_11
:
2263 case V_028C70_COLOR_11_11_10
:
2264 case V_028C70_COLOR_8
:
2265 case V_028C70_COLOR_8_8
:
2266 case V_028C70_COLOR_8_8_8_8
:
2267 case V_028C70_COLOR_10_10_10_2
:
2268 case V_028C70_COLOR_2_10_10_10
:
2269 if (ntype
== V_028C70_NUMBER_UINT
)
2270 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
2271 else if (ntype
== V_028C70_NUMBER_SINT
)
2272 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
2274 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
2277 case V_028C70_COLOR_16
:
2278 case V_028C70_COLOR_16_16
:
2279 case V_028C70_COLOR_16_16_16_16
:
2280 if (ntype
== V_028C70_NUMBER_UNORM
||
2281 ntype
== V_028C70_NUMBER_SNORM
) {
2282 /* UNORM16 and SNORM16 don't support blending */
2283 if (ntype
== V_028C70_NUMBER_UNORM
)
2284 normal
= alpha
= V_028714_SPI_SHADER_UNORM16_ABGR
;
2286 normal
= alpha
= V_028714_SPI_SHADER_SNORM16_ABGR
;
2288 /* Use 32 bits per channel for blending. */
2289 if (format
== V_028C70_COLOR_16
) {
2290 if (swap
== V_028C70_SWAP_STD
) { /* R */
2291 blend
= V_028714_SPI_SHADER_32_R
;
2292 blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2293 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
2294 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2297 } else if (format
== V_028C70_COLOR_16_16
) {
2298 if (swap
== V_028C70_SWAP_STD
) { /* RG */
2299 blend
= V_028714_SPI_SHADER_32_GR
;
2300 blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2301 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
2302 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2305 } else /* 16_16_16_16 */
2306 blend
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2307 } else if (ntype
== V_028C70_NUMBER_UINT
)
2308 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
2309 else if (ntype
== V_028C70_NUMBER_SINT
)
2310 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
2311 else if (ntype
== V_028C70_NUMBER_FLOAT
)
2312 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
2317 case V_028C70_COLOR_32
:
2318 if (swap
== V_028C70_SWAP_STD
) { /* R */
2319 blend
= normal
= V_028714_SPI_SHADER_32_R
;
2320 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2321 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
2322 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
2327 case V_028C70_COLOR_32_32
:
2328 if (swap
== V_028C70_SWAP_STD
) { /* RG */
2329 blend
= normal
= V_028714_SPI_SHADER_32_GR
;
2330 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2331 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
2332 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
2337 case V_028C70_COLOR_32_32_32_32
:
2338 case V_028C70_COLOR_8_24
:
2339 case V_028C70_COLOR_24_8
:
2340 case V_028C70_COLOR_X24_8_32_FLOAT
:
2341 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
2349 /* The DB->CB copy needs 32_ABGR. */
2351 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
2353 surf
->spi_shader_col_format
= normal
;
2354 surf
->spi_shader_col_format_alpha
= alpha
;
2355 surf
->spi_shader_col_format_blend
= blend
;
2356 surf
->spi_shader_col_format_blend_alpha
= blend_alpha
;
2359 static void si_initialize_color_surface(struct si_context
*sctx
,
2360 struct si_surface
*surf
)
2362 struct si_texture
*tex
= (struct si_texture
*)surf
->base
.texture
;
2363 unsigned color_info
, color_attrib
;
2364 unsigned format
, swap
, ntype
, endian
;
2365 const struct util_format_description
*desc
;
2367 unsigned blend_clamp
= 0, blend_bypass
= 0;
2369 desc
= util_format_description(surf
->base
.format
);
2370 for (firstchan
= 0; firstchan
< 4; firstchan
++) {
2371 if (desc
->channel
[firstchan
].type
!= UTIL_FORMAT_TYPE_VOID
) {
2375 if (firstchan
== 4 || desc
->channel
[firstchan
].type
== UTIL_FORMAT_TYPE_FLOAT
) {
2376 ntype
= V_028C70_NUMBER_FLOAT
;
2378 ntype
= V_028C70_NUMBER_UNORM
;
2379 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
2380 ntype
= V_028C70_NUMBER_SRGB
;
2381 else if (desc
->channel
[firstchan
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2382 if (desc
->channel
[firstchan
].pure_integer
) {
2383 ntype
= V_028C70_NUMBER_SINT
;
2385 assert(desc
->channel
[firstchan
].normalized
);
2386 ntype
= V_028C70_NUMBER_SNORM
;
2388 } else if (desc
->channel
[firstchan
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
2389 if (desc
->channel
[firstchan
].pure_integer
) {
2390 ntype
= V_028C70_NUMBER_UINT
;
2392 assert(desc
->channel
[firstchan
].normalized
);
2393 ntype
= V_028C70_NUMBER_UNORM
;
2398 format
= si_translate_colorformat(surf
->base
.format
);
2399 if (format
== V_028C70_COLOR_INVALID
) {
2400 PRINT_ERR("Invalid CB format: %d, disabling CB.\n", surf
->base
.format
);
2402 assert(format
!= V_028C70_COLOR_INVALID
);
2403 swap
= si_translate_colorswap(surf
->base
.format
, false);
2404 endian
= si_colorformat_endian_swap(format
);
2406 /* blend clamp should be set for all NORM/SRGB types */
2407 if (ntype
== V_028C70_NUMBER_UNORM
||
2408 ntype
== V_028C70_NUMBER_SNORM
||
2409 ntype
== V_028C70_NUMBER_SRGB
)
2412 /* set blend bypass according to docs if SINT/UINT or
2413 8/24 COLOR variants */
2414 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
2415 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
2416 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
2421 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
) {
2422 if (format
== V_028C70_COLOR_8
||
2423 format
== V_028C70_COLOR_8_8
||
2424 format
== V_028C70_COLOR_8_8_8_8
)
2425 surf
->color_is_int8
= true;
2426 else if (format
== V_028C70_COLOR_10_10_10_2
||
2427 format
== V_028C70_COLOR_2_10_10_10
)
2428 surf
->color_is_int10
= true;
2431 color_info
= S_028C70_FORMAT(format
) |
2432 S_028C70_COMP_SWAP(swap
) |
2433 S_028C70_BLEND_CLAMP(blend_clamp
) |
2434 S_028C70_BLEND_BYPASS(blend_bypass
) |
2435 S_028C70_SIMPLE_FLOAT(1) |
2436 S_028C70_ROUND_MODE(ntype
!= V_028C70_NUMBER_UNORM
&&
2437 ntype
!= V_028C70_NUMBER_SNORM
&&
2438 ntype
!= V_028C70_NUMBER_SRGB
&&
2439 format
!= V_028C70_COLOR_8_24
&&
2440 format
!= V_028C70_COLOR_24_8
) |
2441 S_028C70_NUMBER_TYPE(ntype
) |
2442 S_028C70_ENDIAN(endian
);
2444 /* Intensity is implemented as Red, so treat it that way. */
2445 color_attrib
= S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] == PIPE_SWIZZLE_1
||
2446 util_format_is_intensity(surf
->base
.format
));
2448 if (tex
->buffer
.b
.b
.nr_samples
> 1) {
2449 unsigned log_samples
= util_logbase2(tex
->buffer
.b
.b
.nr_samples
);
2450 unsigned log_fragments
= util_logbase2(tex
->buffer
.b
.b
.nr_storage_samples
);
2452 color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
2453 S_028C74_NUM_FRAGMENTS(log_fragments
);
2455 if (tex
->surface
.fmask_size
) {
2456 color_info
|= S_028C70_COMPRESSION(1);
2457 unsigned fmask_bankh
= util_logbase2(tex
->surface
.u
.legacy
.fmask
.bankh
);
2459 if (sctx
->chip_class
== SI
) {
2460 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2461 color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh
);
2466 if (sctx
->chip_class
>= VI
) {
2467 unsigned max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_256B
;
2468 unsigned min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_32B
;
2470 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2471 64 for APU because all of our APUs to date use DIMMs which have
2472 a request granularity size of 64B while all other chips have a
2474 if (!sctx
->screen
->info
.has_dedicated_vram
)
2475 min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_64B
;
2477 if (tex
->buffer
.b
.b
.nr_storage_samples
> 1) {
2478 if (tex
->surface
.bpe
== 1)
2479 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_64B
;
2480 else if (tex
->surface
.bpe
== 2)
2481 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_128B
;
2484 surf
->cb_dcc_control
= S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size
) |
2485 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size
) |
2486 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2489 /* This must be set for fast clear to work without FMASK. */
2490 if (!tex
->surface
.fmask_size
&& sctx
->chip_class
== SI
) {
2491 unsigned bankh
= util_logbase2(tex
->surface
.u
.legacy
.bankh
);
2492 color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(bankh
);
2495 unsigned color_view
= S_028C6C_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
2496 S_028C6C_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
2498 if (sctx
->chip_class
>= GFX9
) {
2499 unsigned mip0_depth
= util_max_layer(&tex
->buffer
.b
.b
, 0);
2501 color_view
|= S_028C6C_MIP_LEVEL(surf
->base
.u
.tex
.level
);
2502 color_attrib
|= S_028C74_MIP0_DEPTH(mip0_depth
) |
2503 S_028C74_RESOURCE_TYPE(tex
->surface
.u
.gfx9
.resource_type
);
2504 surf
->cb_color_attrib2
= S_028C68_MIP0_WIDTH(surf
->width0
- 1) |
2505 S_028C68_MIP0_HEIGHT(surf
->height0
- 1) |
2506 S_028C68_MAX_MIP(tex
->buffer
.b
.b
.last_level
);
2509 surf
->cb_color_view
= color_view
;
2510 surf
->cb_color_info
= color_info
;
2511 surf
->cb_color_attrib
= color_attrib
;
2513 /* Determine pixel shader export format */
2514 si_choose_spi_color_formats(surf
, format
, swap
, ntype
, tex
->is_depth
);
2516 surf
->color_initialized
= true;
2519 static void si_init_depth_surface(struct si_context
*sctx
,
2520 struct si_surface
*surf
)
2522 struct si_texture
*tex
= (struct si_texture
*)surf
->base
.texture
;
2523 unsigned level
= surf
->base
.u
.tex
.level
;
2524 unsigned format
, stencil_format
;
2525 uint32_t z_info
, s_info
;
2527 format
= si_translate_dbformat(tex
->db_render_format
);
2528 stencil_format
= tex
->surface
.has_stencil
?
2529 V_028044_STENCIL_8
: V_028044_STENCIL_INVALID
;
2531 assert(format
!= V_028040_Z_INVALID
);
2532 if (format
== V_028040_Z_INVALID
)
2533 PRINT_ERR("Invalid DB format: %d, disabling DB.\n", tex
->buffer
.b
.b
.format
);
2535 surf
->db_depth_view
= S_028008_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
2536 S_028008_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
2537 surf
->db_htile_data_base
= 0;
2538 surf
->db_htile_surface
= 0;
2540 if (sctx
->chip_class
>= GFX9
) {
2541 assert(tex
->surface
.u
.gfx9
.surf_offset
== 0);
2542 surf
->db_depth_base
= tex
->buffer
.gpu_address
>> 8;
2543 surf
->db_stencil_base
= (tex
->buffer
.gpu_address
+
2544 tex
->surface
.u
.gfx9
.stencil_offset
) >> 8;
2545 z_info
= S_028038_FORMAT(format
) |
2546 S_028038_NUM_SAMPLES(util_logbase2(tex
->buffer
.b
.b
.nr_samples
)) |
2547 S_028038_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
2548 S_028038_MAXMIP(tex
->buffer
.b
.b
.last_level
);
2549 s_info
= S_02803C_FORMAT(stencil_format
) |
2550 S_02803C_SW_MODE(tex
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
2551 surf
->db_z_info2
= S_028068_EPITCH(tex
->surface
.u
.gfx9
.surf
.epitch
);
2552 surf
->db_stencil_info2
= S_02806C_EPITCH(tex
->surface
.u
.gfx9
.stencil
.epitch
);
2553 surf
->db_depth_view
|= S_028008_MIPID(level
);
2554 surf
->db_depth_size
= S_02801C_X_MAX(tex
->buffer
.b
.b
.width0
- 1) |
2555 S_02801C_Y_MAX(tex
->buffer
.b
.b
.height0
- 1);
2557 if (si_htile_enabled(tex
, level
)) {
2558 z_info
|= S_028038_TILE_SURFACE_ENABLE(1) |
2559 S_028038_ALLOW_EXPCLEAR(1);
2561 if (tex
->tc_compatible_htile
) {
2562 unsigned max_zplanes
= 4;
2564 if (tex
->db_render_format
== PIPE_FORMAT_Z16_UNORM
&&
2565 tex
->buffer
.b
.b
.nr_samples
> 1)
2568 z_info
|= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes
+ 1) |
2569 S_028038_ITERATE_FLUSH(1);
2570 s_info
|= S_02803C_ITERATE_FLUSH(1);
2573 if (tex
->surface
.has_stencil
) {
2574 /* Stencil buffer workaround ported from the SI-CI-VI code.
2575 * See that for explanation.
2577 s_info
|= S_02803C_ALLOW_EXPCLEAR(tex
->buffer
.b
.b
.nr_samples
<= 1);
2579 /* Use all HTILE for depth if there's no stencil. */
2580 s_info
|= S_02803C_TILE_STENCIL_DISABLE(1);
2583 surf
->db_htile_data_base
= (tex
->buffer
.gpu_address
+
2584 tex
->htile_offset
) >> 8;
2585 surf
->db_htile_surface
= S_028ABC_FULL_CACHE(1) |
2586 S_028ABC_PIPE_ALIGNED(tex
->surface
.u
.gfx9
.htile
.pipe_aligned
) |
2587 S_028ABC_RB_ALIGNED(tex
->surface
.u
.gfx9
.htile
.rb_aligned
);
2591 struct legacy_surf_level
*levelinfo
= &tex
->surface
.u
.legacy
.level
[level
];
2593 assert(levelinfo
->nblk_x
% 8 == 0 && levelinfo
->nblk_y
% 8 == 0);
2595 surf
->db_depth_base
= (tex
->buffer
.gpu_address
+
2596 tex
->surface
.u
.legacy
.level
[level
].offset
) >> 8;
2597 surf
->db_stencil_base
= (tex
->buffer
.gpu_address
+
2598 tex
->surface
.u
.legacy
.stencil_level
[level
].offset
) >> 8;
2600 z_info
= S_028040_FORMAT(format
) |
2601 S_028040_NUM_SAMPLES(util_logbase2(tex
->buffer
.b
.b
.nr_samples
));
2602 s_info
= S_028044_FORMAT(stencil_format
);
2603 surf
->db_depth_info
= S_02803C_ADDR5_SWIZZLE_MASK(!tex
->tc_compatible_htile
);
2605 if (sctx
->chip_class
>= CIK
) {
2606 struct radeon_info
*info
= &sctx
->screen
->info
;
2607 unsigned index
= tex
->surface
.u
.legacy
.tiling_index
[level
];
2608 unsigned stencil_index
= tex
->surface
.u
.legacy
.stencil_tiling_index
[level
];
2609 unsigned macro_index
= tex
->surface
.u
.legacy
.macro_tile_index
;
2610 unsigned tile_mode
= info
->si_tile_mode_array
[index
];
2611 unsigned stencil_tile_mode
= info
->si_tile_mode_array
[stencil_index
];
2612 unsigned macro_mode
= info
->cik_macrotile_mode_array
[macro_index
];
2614 surf
->db_depth_info
|=
2615 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode
)) |
2616 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode
)) |
2617 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode
)) |
2618 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode
)) |
2619 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode
)) |
2620 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode
));
2621 z_info
|= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode
));
2622 s_info
|= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode
));
2624 unsigned tile_mode_index
= si_tile_mode_index(tex
, level
, false);
2625 z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
2626 tile_mode_index
= si_tile_mode_index(tex
, level
, true);
2627 s_info
|= S_028044_TILE_MODE_INDEX(tile_mode_index
);
2630 surf
->db_depth_size
= S_028058_PITCH_TILE_MAX((levelinfo
->nblk_x
/ 8) - 1) |
2631 S_028058_HEIGHT_TILE_MAX((levelinfo
->nblk_y
/ 8) - 1);
2632 surf
->db_depth_slice
= S_02805C_SLICE_TILE_MAX((levelinfo
->nblk_x
*
2633 levelinfo
->nblk_y
) / 64 - 1);
2635 if (si_htile_enabled(tex
, level
)) {
2636 z_info
|= S_028040_TILE_SURFACE_ENABLE(1) |
2637 S_028040_ALLOW_EXPCLEAR(1);
2639 if (tex
->surface
.has_stencil
) {
2640 /* Workaround: For a not yet understood reason, the
2641 * combination of MSAA, fast stencil clear and stencil
2642 * decompress messes with subsequent stencil buffer
2643 * uses. Problem was reproduced on Verde, Bonaire,
2644 * Tonga, and Carrizo.
2646 * Disabling EXPCLEAR works around the problem.
2648 * Check piglit's arb_texture_multisample-stencil-clear
2649 * test if you want to try changing this.
2651 if (tex
->buffer
.b
.b
.nr_samples
<= 1)
2652 s_info
|= S_028044_ALLOW_EXPCLEAR(1);
2653 } else if (!tex
->tc_compatible_htile
) {
2654 /* Use all of the htile_buffer for depth if there's no stencil.
2655 * This must not be set when TC-compatible HTILE is enabled
2658 s_info
|= S_028044_TILE_STENCIL_DISABLE(1);
2661 surf
->db_htile_data_base
= (tex
->buffer
.gpu_address
+
2662 tex
->htile_offset
) >> 8;
2663 surf
->db_htile_surface
= S_028ABC_FULL_CACHE(1);
2665 if (tex
->tc_compatible_htile
) {
2666 surf
->db_htile_surface
|= S_028ABC_TC_COMPATIBLE(1);
2668 /* 0 = full compression. N = only compress up to N-1 Z planes. */
2669 if (tex
->buffer
.b
.b
.nr_samples
<= 1)
2670 z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2671 else if (tex
->buffer
.b
.b
.nr_samples
<= 4)
2672 z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2674 z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2679 surf
->db_z_info
= z_info
;
2680 surf
->db_stencil_info
= s_info
;
2682 surf
->depth_initialized
= true;
2685 void si_update_fb_dirtiness_after_rendering(struct si_context
*sctx
)
2687 if (sctx
->decompression_enabled
)
2690 if (sctx
->framebuffer
.state
.zsbuf
) {
2691 struct pipe_surface
*surf
= sctx
->framebuffer
.state
.zsbuf
;
2692 struct si_texture
*tex
= (struct si_texture
*)surf
->texture
;
2694 tex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2696 if (tex
->surface
.has_stencil
)
2697 tex
->stencil_dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2700 unsigned compressed_cb_mask
= sctx
->framebuffer
.compressed_cb_mask
;
2701 while (compressed_cb_mask
) {
2702 unsigned i
= u_bit_scan(&compressed_cb_mask
);
2703 struct pipe_surface
*surf
= sctx
->framebuffer
.state
.cbufs
[i
];
2704 struct si_texture
*tex
= (struct si_texture
*)surf
->texture
;
2706 if (tex
->surface
.fmask_size
)
2707 tex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2708 if (tex
->dcc_gather_statistics
)
2709 tex
->separate_dcc_dirty
= true;
2713 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state
*state
)
2715 for (int i
= 0; i
< state
->nr_cbufs
; ++i
) {
2716 struct si_surface
*surf
= NULL
;
2717 struct si_texture
*tex
;
2719 if (!state
->cbufs
[i
])
2721 surf
= (struct si_surface
*)state
->cbufs
[i
];
2722 tex
= (struct si_texture
*)surf
->base
.texture
;
2724 p_atomic_dec(&tex
->framebuffers_bound
);
2728 static void si_set_framebuffer_state(struct pipe_context
*ctx
,
2729 const struct pipe_framebuffer_state
*state
)
2731 struct si_context
*sctx
= (struct si_context
*)ctx
;
2732 struct si_surface
*surf
= NULL
;
2733 struct si_texture
*tex
;
2734 bool old_any_dst_linear
= sctx
->framebuffer
.any_dst_linear
;
2735 unsigned old_nr_samples
= sctx
->framebuffer
.nr_samples
;
2736 unsigned old_colorbuf_enabled_4bit
= sctx
->framebuffer
.colorbuf_enabled_4bit
;
2737 bool old_has_zsbuf
= !!sctx
->framebuffer
.state
.zsbuf
;
2738 bool old_has_stencil
=
2740 ((struct si_texture
*)sctx
->framebuffer
.state
.zsbuf
->texture
)->surface
.has_stencil
;
2741 bool unbound
= false;
2744 /* Reject zero-sized framebuffers due to a hw bug on SI that occurs
2745 * when PA_SU_HARDWARE_SCREEN_OFFSET != 0 and any_scissor.BR_X/Y <= 0.
2746 * We could implement the full workaround here, but it's a useless case.
2748 if ((!state
->width
|| !state
->height
) && (state
->nr_cbufs
|| state
->zsbuf
)) {
2749 unreachable("the framebuffer shouldn't have zero area");
2753 si_update_fb_dirtiness_after_rendering(sctx
);
2755 for (i
= 0; i
< sctx
->framebuffer
.state
.nr_cbufs
; i
++) {
2756 if (!sctx
->framebuffer
.state
.cbufs
[i
])
2759 tex
= (struct si_texture
*)sctx
->framebuffer
.state
.cbufs
[i
]->texture
;
2760 if (tex
->dcc_gather_statistics
)
2761 vi_separate_dcc_stop_query(sctx
, tex
);
2764 /* Disable DCC if the formats are incompatible. */
2765 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
2766 if (!state
->cbufs
[i
])
2769 surf
= (struct si_surface
*)state
->cbufs
[i
];
2770 tex
= (struct si_texture
*)surf
->base
.texture
;
2772 if (!surf
->dcc_incompatible
)
2775 /* Since the DCC decompression calls back into set_framebuffer-
2776 * _state, we need to unbind the framebuffer, so that
2777 * vi_separate_dcc_stop_query isn't called twice with the same
2781 util_copy_framebuffer_state(&sctx
->framebuffer
.state
, NULL
);
2785 if (vi_dcc_enabled(tex
, surf
->base
.u
.tex
.level
))
2786 if (!si_texture_disable_dcc(sctx
, tex
))
2787 si_decompress_dcc(sctx
, tex
);
2789 surf
->dcc_incompatible
= false;
2792 /* Only flush TC when changing the framebuffer state, because
2793 * the only client not using TC that can change textures is
2796 * Wait for compute shaders because of possible transitions:
2797 * - FB write -> shader read
2798 * - shader write -> FB read
2800 * DB caches are flushed on demand (using si_decompress_textures).
2802 * When MSAA is enabled, CB and TC caches are flushed on demand
2803 * (after FMASK decompression). Shader write -> FB read transitions
2804 * cannot happen for MSAA textures, because MSAA shader images are
2807 * Only flush and wait for CB if there is actually a bound color buffer.
2809 if (sctx
->framebuffer
.uncompressed_cb_mask
)
2810 si_make_CB_shader_coherent(sctx
, sctx
->framebuffer
.nr_samples
,
2811 sctx
->framebuffer
.CB_has_shader_readable_metadata
);
2813 sctx
->flags
|= SI_CONTEXT_CS_PARTIAL_FLUSH
;
2815 /* u_blitter doesn't invoke depth decompression when it does multiple
2816 * blits in a row, but the only case when it matters for DB is when
2817 * doing generate_mipmap. So here we flush DB manually between
2818 * individual generate_mipmap blits.
2819 * Note that lower mipmap levels aren't compressed.
2821 if (sctx
->generate_mipmap_for_depth
) {
2822 si_make_DB_shader_coherent(sctx
, 1, false,
2823 sctx
->framebuffer
.DB_has_shader_readable_metadata
);
2824 } else if (sctx
->chip_class
== GFX9
) {
2825 /* It appears that DB metadata "leaks" in a sequence of:
2827 * - DCC decompress for shader image writes (with DB disabled)
2828 * - render with DEPTH_BEFORE_SHADER=1
2829 * Flushing DB metadata works around the problem.
2831 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_DB_META
;
2834 /* Take the maximum of the old and new count. If the new count is lower,
2835 * dirtying is needed to disable the unbound colorbuffers.
2837 sctx
->framebuffer
.dirty_cbufs
|=
2838 (1 << MAX2(sctx
->framebuffer
.state
.nr_cbufs
, state
->nr_cbufs
)) - 1;
2839 sctx
->framebuffer
.dirty_zsbuf
|= sctx
->framebuffer
.state
.zsbuf
!= state
->zsbuf
;
2841 si_dec_framebuffer_counters(&sctx
->framebuffer
.state
);
2842 util_copy_framebuffer_state(&sctx
->framebuffer
.state
, state
);
2844 sctx
->framebuffer
.colorbuf_enabled_4bit
= 0;
2845 sctx
->framebuffer
.spi_shader_col_format
= 0;
2846 sctx
->framebuffer
.spi_shader_col_format_alpha
= 0;
2847 sctx
->framebuffer
.spi_shader_col_format_blend
= 0;
2848 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
= 0;
2849 sctx
->framebuffer
.color_is_int8
= 0;
2850 sctx
->framebuffer
.color_is_int10
= 0;
2852 sctx
->framebuffer
.compressed_cb_mask
= 0;
2853 sctx
->framebuffer
.uncompressed_cb_mask
= 0;
2854 sctx
->framebuffer
.nr_samples
= util_framebuffer_get_num_samples(state
);
2855 sctx
->framebuffer
.nr_color_samples
= sctx
->framebuffer
.nr_samples
;
2856 sctx
->framebuffer
.log_samples
= util_logbase2(sctx
->framebuffer
.nr_samples
);
2857 sctx
->framebuffer
.any_dst_linear
= false;
2858 sctx
->framebuffer
.CB_has_shader_readable_metadata
= false;
2859 sctx
->framebuffer
.DB_has_shader_readable_metadata
= false;
2860 unsigned num_bpp64_colorbufs
= 0;
2862 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
2863 if (!state
->cbufs
[i
])
2866 surf
= (struct si_surface
*)state
->cbufs
[i
];
2867 tex
= (struct si_texture
*)surf
->base
.texture
;
2869 if (!surf
->color_initialized
) {
2870 si_initialize_color_surface(sctx
, surf
);
2873 sctx
->framebuffer
.colorbuf_enabled_4bit
|= 0xf << (i
* 4);
2874 sctx
->framebuffer
.spi_shader_col_format
|=
2875 surf
->spi_shader_col_format
<< (i
* 4);
2876 sctx
->framebuffer
.spi_shader_col_format_alpha
|=
2877 surf
->spi_shader_col_format_alpha
<< (i
* 4);
2878 sctx
->framebuffer
.spi_shader_col_format_blend
|=
2879 surf
->spi_shader_col_format_blend
<< (i
* 4);
2880 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
|=
2881 surf
->spi_shader_col_format_blend_alpha
<< (i
* 4);
2883 if (surf
->color_is_int8
)
2884 sctx
->framebuffer
.color_is_int8
|= 1 << i
;
2885 if (surf
->color_is_int10
)
2886 sctx
->framebuffer
.color_is_int10
|= 1 << i
;
2888 if (tex
->surface
.fmask_size
)
2889 sctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
2891 sctx
->framebuffer
.uncompressed_cb_mask
|= 1 << i
;
2893 /* Don't update nr_color_samples for non-AA buffers.
2894 * (e.g. destination of MSAA resolve)
2896 if (tex
->buffer
.b
.b
.nr_samples
>= 2 &&
2897 tex
->buffer
.b
.b
.nr_storage_samples
< tex
->buffer
.b
.b
.nr_samples
) {
2898 sctx
->framebuffer
.nr_color_samples
=
2899 MIN2(sctx
->framebuffer
.nr_color_samples
,
2900 tex
->buffer
.b
.b
.nr_storage_samples
);
2901 sctx
->framebuffer
.nr_color_samples
=
2902 MAX2(1, sctx
->framebuffer
.nr_color_samples
);
2905 if (tex
->surface
.is_linear
)
2906 sctx
->framebuffer
.any_dst_linear
= true;
2907 if (tex
->surface
.bpe
>= 8)
2908 num_bpp64_colorbufs
++;
2910 if (vi_dcc_enabled(tex
, surf
->base
.u
.tex
.level
))
2911 sctx
->framebuffer
.CB_has_shader_readable_metadata
= true;
2913 si_context_add_resource_size(sctx
, surf
->base
.texture
);
2915 p_atomic_inc(&tex
->framebuffers_bound
);
2917 if (tex
->dcc_gather_statistics
) {
2918 /* Dirty tracking must be enabled for DCC usage analysis. */
2919 sctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
2920 vi_separate_dcc_start_query(sctx
, tex
);
2924 /* For optimal DCC performance. */
2925 if (sctx
->chip_class
== VI
)
2926 sctx
->framebuffer
.dcc_overwrite_combiner_watermark
= 4;
2927 else if (num_bpp64_colorbufs
>= 5)
2928 sctx
->framebuffer
.dcc_overwrite_combiner_watermark
= 8;
2930 sctx
->framebuffer
.dcc_overwrite_combiner_watermark
= 6;
2932 struct si_texture
*zstex
= NULL
;
2935 surf
= (struct si_surface
*)state
->zsbuf
;
2936 zstex
= (struct si_texture
*)surf
->base
.texture
;
2938 if (!surf
->depth_initialized
) {
2939 si_init_depth_surface(sctx
, surf
);
2942 if (vi_tc_compat_htile_enabled(zstex
, surf
->base
.u
.tex
.level
))
2943 sctx
->framebuffer
.DB_has_shader_readable_metadata
= true;
2945 si_context_add_resource_size(sctx
, surf
->base
.texture
);
2948 si_update_ps_colorbuf0_slot(sctx
);
2949 si_update_poly_offset_state(sctx
);
2950 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
2951 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.framebuffer
);
2953 if (sctx
->screen
->dpbb_allowed
)
2954 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
2956 if (sctx
->framebuffer
.any_dst_linear
!= old_any_dst_linear
)
2957 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
2959 if (sctx
->screen
->has_out_of_order_rast
&&
2960 (sctx
->framebuffer
.colorbuf_enabled_4bit
!= old_colorbuf_enabled_4bit
||
2961 !!sctx
->framebuffer
.state
.zsbuf
!= old_has_zsbuf
||
2962 (zstex
&& zstex
->surface
.has_stencil
!= old_has_stencil
)))
2963 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
2965 if (sctx
->framebuffer
.nr_samples
!= old_nr_samples
) {
2966 struct pipe_constant_buffer constbuf
= {0};
2968 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
2969 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
2971 constbuf
.buffer
= sctx
->sample_pos_buffer
;
2973 /* Set sample locations as fragment shader constants. */
2974 switch (sctx
->framebuffer
.nr_samples
) {
2976 constbuf
.buffer_offset
= 0;
2979 constbuf
.buffer_offset
= (ubyte
*)sctx
->sample_positions
.x2
-
2980 (ubyte
*)sctx
->sample_positions
.x1
;
2983 constbuf
.buffer_offset
= (ubyte
*)sctx
->sample_positions
.x4
-
2984 (ubyte
*)sctx
->sample_positions
.x1
;
2987 constbuf
.buffer_offset
= (ubyte
*)sctx
->sample_positions
.x8
-
2988 (ubyte
*)sctx
->sample_positions
.x1
;
2991 constbuf
.buffer_offset
= (ubyte
*)sctx
->sample_positions
.x16
-
2992 (ubyte
*)sctx
->sample_positions
.x1
;
2995 PRINT_ERR("Requested an invalid number of samples %i.\n",
2996 sctx
->framebuffer
.nr_samples
);
2999 constbuf
.buffer_size
= sctx
->framebuffer
.nr_samples
* 2 * 4;
3000 si_set_rw_buffer(sctx
, SI_PS_CONST_SAMPLE_POSITIONS
, &constbuf
);
3002 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_sample_locs
);
3005 sctx
->do_update_shaders
= true;
3007 if (!sctx
->decompression_enabled
) {
3008 /* Prevent textures decompression when the framebuffer state
3009 * changes come from the decompression passes themselves.
3011 sctx
->need_check_render_feedback
= true;
3015 static void si_emit_framebuffer_state(struct si_context
*sctx
)
3017 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
3018 struct pipe_framebuffer_state
*state
= &sctx
->framebuffer
.state
;
3019 unsigned i
, nr_cbufs
= state
->nr_cbufs
;
3020 struct si_texture
*tex
= NULL
;
3021 struct si_surface
*cb
= NULL
;
3022 unsigned cb_color_info
= 0;
3025 for (i
= 0; i
< nr_cbufs
; i
++) {
3026 uint64_t cb_color_base
, cb_color_fmask
, cb_color_cmask
, cb_dcc_base
;
3027 unsigned cb_color_attrib
;
3029 if (!(sctx
->framebuffer
.dirty_cbufs
& (1 << i
)))
3032 cb
= (struct si_surface
*)state
->cbufs
[i
];
3034 radeon_set_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
3035 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
3039 tex
= (struct si_texture
*)cb
->base
.texture
;
3040 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
3041 &tex
->buffer
, RADEON_USAGE_READWRITE
,
3042 tex
->buffer
.b
.b
.nr_samples
> 1 ?
3043 RADEON_PRIO_COLOR_BUFFER_MSAA
:
3044 RADEON_PRIO_COLOR_BUFFER
);
3046 if (tex
->cmask_buffer
&& tex
->cmask_buffer
!= &tex
->buffer
) {
3047 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
3048 tex
->cmask_buffer
, RADEON_USAGE_READWRITE
,
3049 RADEON_PRIO_SEPARATE_META
);
3052 if (tex
->dcc_separate_buffer
)
3053 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
3054 tex
->dcc_separate_buffer
,
3055 RADEON_USAGE_READWRITE
,
3056 RADEON_PRIO_SEPARATE_META
);
3058 /* Compute mutable surface parameters. */
3059 cb_color_base
= tex
->buffer
.gpu_address
>> 8;
3061 cb_color_cmask
= tex
->cmask_base_address_reg
;
3063 cb_color_info
= cb
->cb_color_info
| tex
->cb_color_info
;
3064 cb_color_attrib
= cb
->cb_color_attrib
;
3066 if (cb
->base
.u
.tex
.level
> 0)
3067 cb_color_info
&= C_028C70_FAST_CLEAR
;
3069 if (tex
->surface
.fmask_size
) {
3070 cb_color_fmask
= (tex
->buffer
.gpu_address
+ tex
->fmask_offset
) >> 8;
3071 cb_color_fmask
|= tex
->surface
.fmask_tile_swizzle
;
3075 if (vi_dcc_enabled(tex
, cb
->base
.u
.tex
.level
)) {
3076 bool is_msaa_resolve_dst
= state
->cbufs
[0] &&
3077 state
->cbufs
[0]->texture
->nr_samples
> 1 &&
3078 state
->cbufs
[1] == &cb
->base
&&
3079 state
->cbufs
[1]->texture
->nr_samples
<= 1;
3081 if (!is_msaa_resolve_dst
)
3082 cb_color_info
|= S_028C70_DCC_ENABLE(1);
3084 cb_dcc_base
= ((!tex
->dcc_separate_buffer
? tex
->buffer
.gpu_address
: 0) +
3085 tex
->dcc_offset
) >> 8;
3086 cb_dcc_base
|= tex
->surface
.tile_swizzle
;
3089 if (sctx
->chip_class
>= GFX9
) {
3090 struct gfx9_surf_meta_flags meta
;
3092 if (tex
->dcc_offset
)
3093 meta
= tex
->surface
.u
.gfx9
.dcc
;
3095 meta
= tex
->surface
.u
.gfx9
.cmask
;
3097 /* Set mutable surface parameters. */
3098 cb_color_base
+= tex
->surface
.u
.gfx9
.surf_offset
>> 8;
3099 cb_color_base
|= tex
->surface
.tile_swizzle
;
3100 if (!tex
->surface
.fmask_size
)
3101 cb_color_fmask
= cb_color_base
;
3102 if (cb
->base
.u
.tex
.level
> 0)
3103 cb_color_cmask
= cb_color_base
;
3104 cb_color_attrib
|= S_028C74_COLOR_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
3105 S_028C74_FMASK_SW_MODE(tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
) |
3106 S_028C74_RB_ALIGNED(meta
.rb_aligned
) |
3107 S_028C74_PIPE_ALIGNED(meta
.pipe_aligned
);
3109 radeon_set_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C, 15);
3110 radeon_emit(cs
, cb_color_base
); /* CB_COLOR0_BASE */
3111 radeon_emit(cs
, S_028C64_BASE_256B(cb_color_base
>> 32)); /* CB_COLOR0_BASE_EXT */
3112 radeon_emit(cs
, cb
->cb_color_attrib2
); /* CB_COLOR0_ATTRIB2 */
3113 radeon_emit(cs
, cb
->cb_color_view
); /* CB_COLOR0_VIEW */
3114 radeon_emit(cs
, cb_color_info
); /* CB_COLOR0_INFO */
3115 radeon_emit(cs
, cb_color_attrib
); /* CB_COLOR0_ATTRIB */
3116 radeon_emit(cs
, cb
->cb_dcc_control
); /* CB_COLOR0_DCC_CONTROL */
3117 radeon_emit(cs
, cb_color_cmask
); /* CB_COLOR0_CMASK */
3118 radeon_emit(cs
, S_028C80_BASE_256B(cb_color_cmask
>> 32)); /* CB_COLOR0_CMASK_BASE_EXT */
3119 radeon_emit(cs
, cb_color_fmask
); /* CB_COLOR0_FMASK */
3120 radeon_emit(cs
, S_028C88_BASE_256B(cb_color_fmask
>> 32)); /* CB_COLOR0_FMASK_BASE_EXT */
3121 radeon_emit(cs
, tex
->color_clear_value
[0]); /* CB_COLOR0_CLEAR_WORD0 */
3122 radeon_emit(cs
, tex
->color_clear_value
[1]); /* CB_COLOR0_CLEAR_WORD1 */
3123 radeon_emit(cs
, cb_dcc_base
); /* CB_COLOR0_DCC_BASE */
3124 radeon_emit(cs
, S_028C98_BASE_256B(cb_dcc_base
>> 32)); /* CB_COLOR0_DCC_BASE_EXT */
3126 radeon_set_context_reg(cs
, R_0287A0_CB_MRT0_EPITCH
+ i
* 4,
3127 S_0287A0_EPITCH(tex
->surface
.u
.gfx9
.surf
.epitch
));
3129 /* Compute mutable surface parameters (SI-CI-VI). */
3130 const struct legacy_surf_level
*level_info
=
3131 &tex
->surface
.u
.legacy
.level
[cb
->base
.u
.tex
.level
];
3132 unsigned pitch_tile_max
, slice_tile_max
, tile_mode_index
;
3133 unsigned cb_color_pitch
, cb_color_slice
, cb_color_fmask_slice
;
3135 cb_color_base
+= level_info
->offset
>> 8;
3136 /* Only macrotiled modes can set tile swizzle. */
3137 if (level_info
->mode
== RADEON_SURF_MODE_2D
)
3138 cb_color_base
|= tex
->surface
.tile_swizzle
;
3140 if (!tex
->surface
.fmask_size
)
3141 cb_color_fmask
= cb_color_base
;
3142 if (cb
->base
.u
.tex
.level
> 0)
3143 cb_color_cmask
= cb_color_base
;
3145 cb_dcc_base
+= level_info
->dcc_offset
>> 8;
3147 pitch_tile_max
= level_info
->nblk_x
/ 8 - 1;
3148 slice_tile_max
= level_info
->nblk_x
*
3149 level_info
->nblk_y
/ 64 - 1;
3150 tile_mode_index
= si_tile_mode_index(tex
, cb
->base
.u
.tex
.level
, false);
3152 cb_color_attrib
|= S_028C74_TILE_MODE_INDEX(tile_mode_index
);
3153 cb_color_pitch
= S_028C64_TILE_MAX(pitch_tile_max
);
3154 cb_color_slice
= S_028C68_TILE_MAX(slice_tile_max
);
3156 if (tex
->surface
.fmask_size
) {
3157 if (sctx
->chip_class
>= CIK
)
3158 cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(tex
->surface
.u
.legacy
.fmask
.pitch_in_pixels
/ 8 - 1);
3159 cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tex
->surface
.u
.legacy
.fmask
.tiling_index
);
3160 cb_color_fmask_slice
= S_028C88_TILE_MAX(tex
->surface
.u
.legacy
.fmask
.slice_tile_max
);
3162 /* This must be set for fast clear to work without FMASK. */
3163 if (sctx
->chip_class
>= CIK
)
3164 cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(pitch_tile_max
);
3165 cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index
);
3166 cb_color_fmask_slice
= S_028C88_TILE_MAX(slice_tile_max
);
3169 radeon_set_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C,
3170 sctx
->chip_class
>= VI
? 14 : 13);
3171 radeon_emit(cs
, cb_color_base
); /* CB_COLOR0_BASE */
3172 radeon_emit(cs
, cb_color_pitch
); /* CB_COLOR0_PITCH */
3173 radeon_emit(cs
, cb_color_slice
); /* CB_COLOR0_SLICE */
3174 radeon_emit(cs
, cb
->cb_color_view
); /* CB_COLOR0_VIEW */
3175 radeon_emit(cs
, cb_color_info
); /* CB_COLOR0_INFO */
3176 radeon_emit(cs
, cb_color_attrib
); /* CB_COLOR0_ATTRIB */
3177 radeon_emit(cs
, cb
->cb_dcc_control
); /* CB_COLOR0_DCC_CONTROL */
3178 radeon_emit(cs
, cb_color_cmask
); /* CB_COLOR0_CMASK */
3179 radeon_emit(cs
, tex
->surface
.u
.legacy
.cmask_slice_tile_max
); /* CB_COLOR0_CMASK_SLICE */
3180 radeon_emit(cs
, cb_color_fmask
); /* CB_COLOR0_FMASK */
3181 radeon_emit(cs
, cb_color_fmask_slice
); /* CB_COLOR0_FMASK_SLICE */
3182 radeon_emit(cs
, tex
->color_clear_value
[0]); /* CB_COLOR0_CLEAR_WORD0 */
3183 radeon_emit(cs
, tex
->color_clear_value
[1]); /* CB_COLOR0_CLEAR_WORD1 */
3185 if (sctx
->chip_class
>= VI
) /* R_028C94_CB_COLOR0_DCC_BASE */
3186 radeon_emit(cs
, cb_dcc_base
);
3190 if (sctx
->framebuffer
.dirty_cbufs
& (1 << i
))
3191 radeon_set_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C, 0);
3194 if (state
->zsbuf
&& sctx
->framebuffer
.dirty_zsbuf
) {
3195 struct si_surface
*zb
= (struct si_surface
*)state
->zsbuf
;
3196 struct si_texture
*tex
= (struct si_texture
*)zb
->base
.texture
;
3198 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
3199 &tex
->buffer
, RADEON_USAGE_READWRITE
,
3200 zb
->base
.texture
->nr_samples
> 1 ?
3201 RADEON_PRIO_DEPTH_BUFFER_MSAA
:
3202 RADEON_PRIO_DEPTH_BUFFER
);
3204 if (sctx
->chip_class
>= GFX9
) {
3205 radeon_set_context_reg_seq(cs
, R_028014_DB_HTILE_DATA_BASE
, 3);
3206 radeon_emit(cs
, zb
->db_htile_data_base
); /* DB_HTILE_DATA_BASE */
3207 radeon_emit(cs
, S_028018_BASE_HI(zb
->db_htile_data_base
>> 32)); /* DB_HTILE_DATA_BASE_HI */
3208 radeon_emit(cs
, zb
->db_depth_size
); /* DB_DEPTH_SIZE */
3210 radeon_set_context_reg_seq(cs
, R_028038_DB_Z_INFO
, 10);
3211 radeon_emit(cs
, zb
->db_z_info
| /* DB_Z_INFO */
3212 S_028038_ZRANGE_PRECISION(tex
->depth_clear_value
!= 0));
3213 radeon_emit(cs
, zb
->db_stencil_info
); /* DB_STENCIL_INFO */
3214 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_READ_BASE */
3215 radeon_emit(cs
, S_028044_BASE_HI(zb
->db_depth_base
>> 32)); /* DB_Z_READ_BASE_HI */
3216 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_READ_BASE */
3217 radeon_emit(cs
, S_02804C_BASE_HI(zb
->db_stencil_base
>> 32)); /* DB_STENCIL_READ_BASE_HI */
3218 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_WRITE_BASE */
3219 radeon_emit(cs
, S_028054_BASE_HI(zb
->db_depth_base
>> 32)); /* DB_Z_WRITE_BASE_HI */
3220 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_WRITE_BASE */
3221 radeon_emit(cs
, S_02805C_BASE_HI(zb
->db_stencil_base
>> 32)); /* DB_STENCIL_WRITE_BASE_HI */
3223 radeon_set_context_reg_seq(cs
, R_028068_DB_Z_INFO2
, 2);
3224 radeon_emit(cs
, zb
->db_z_info2
); /* DB_Z_INFO2 */
3225 radeon_emit(cs
, zb
->db_stencil_info2
); /* DB_STENCIL_INFO2 */
3227 radeon_set_context_reg(cs
, R_028014_DB_HTILE_DATA_BASE
, zb
->db_htile_data_base
);
3229 radeon_set_context_reg_seq(cs
, R_02803C_DB_DEPTH_INFO
, 9);
3230 radeon_emit(cs
, zb
->db_depth_info
); /* DB_DEPTH_INFO */
3231 radeon_emit(cs
, zb
->db_z_info
| /* DB_Z_INFO */
3232 S_028040_ZRANGE_PRECISION(tex
->depth_clear_value
!= 0));
3233 radeon_emit(cs
, zb
->db_stencil_info
); /* DB_STENCIL_INFO */
3234 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_READ_BASE */
3235 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_READ_BASE */
3236 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_WRITE_BASE */
3237 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_WRITE_BASE */
3238 radeon_emit(cs
, zb
->db_depth_size
); /* DB_DEPTH_SIZE */
3239 radeon_emit(cs
, zb
->db_depth_slice
); /* DB_DEPTH_SLICE */
3242 radeon_set_context_reg_seq(cs
, R_028028_DB_STENCIL_CLEAR
, 2);
3243 radeon_emit(cs
, tex
->stencil_clear_value
); /* R_028028_DB_STENCIL_CLEAR */
3244 radeon_emit(cs
, fui(tex
->depth_clear_value
)); /* R_02802C_DB_DEPTH_CLEAR */
3246 radeon_set_context_reg(cs
, R_028008_DB_DEPTH_VIEW
, zb
->db_depth_view
);
3247 radeon_set_context_reg(cs
, R_028ABC_DB_HTILE_SURFACE
, zb
->db_htile_surface
);
3248 } else if (sctx
->framebuffer
.dirty_zsbuf
) {
3249 if (sctx
->chip_class
>= GFX9
)
3250 radeon_set_context_reg_seq(cs
, R_028038_DB_Z_INFO
, 2);
3252 radeon_set_context_reg_seq(cs
, R_028040_DB_Z_INFO
, 2);
3254 radeon_emit(cs
, S_028040_FORMAT(V_028040_Z_INVALID
)); /* DB_Z_INFO */
3255 radeon_emit(cs
, S_028044_FORMAT(V_028044_STENCIL_INVALID
)); /* DB_STENCIL_INFO */
3258 /* Framebuffer dimensions. */
3259 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
3260 radeon_set_context_reg(cs
, R_028208_PA_SC_WINDOW_SCISSOR_BR
,
3261 S_028208_BR_X(state
->width
) | S_028208_BR_Y(state
->height
));
3263 if (sctx
->screen
->dfsm_allowed
) {
3264 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3265 radeon_emit(cs
, EVENT_TYPE(V_028A90_BREAK_BATCH
) | EVENT_INDEX(0));
3268 sctx
->framebuffer
.dirty_cbufs
= 0;
3269 sctx
->framebuffer
.dirty_zsbuf
= false;
3272 static void si_emit_msaa_sample_locs(struct si_context
*sctx
)
3274 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
3275 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
3276 unsigned nr_samples
= sctx
->framebuffer
.nr_samples
;
3277 bool has_msaa_sample_loc_bug
= sctx
->screen
->has_msaa_sample_loc_bug
;
3279 /* Smoothing (only possible with nr_samples == 1) uses the same
3280 * sample locations as the MSAA it simulates.
3282 if (nr_samples
<= 1 && sctx
->smoothing_enabled
)
3283 nr_samples
= SI_NUM_SMOOTH_AA_SAMPLES
;
3285 /* On Polaris, the small primitive filter uses the sample locations
3286 * even when MSAA is off, so we need to make sure they're set to 0.
3288 if ((nr_samples
>= 2 || has_msaa_sample_loc_bug
) &&
3289 nr_samples
!= sctx
->sample_locs_num_samples
) {
3290 sctx
->sample_locs_num_samples
= nr_samples
;
3291 si_emit_sample_locations(cs
, nr_samples
);
3294 if (sctx
->family
>= CHIP_POLARIS10
) {
3295 unsigned small_prim_filter_cntl
=
3296 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
3298 S_028830_LINE_FILTER_DISABLE(sctx
->family
<= CHIP_POLARIS12
);
3300 /* The alternative of setting sample locations to 0 would
3301 * require a DB flush to avoid Z errors, see
3302 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
3304 if (has_msaa_sample_loc_bug
&&
3305 sctx
->framebuffer
.nr_samples
> 1 &&
3306 !rs
->multisample_enable
)
3307 small_prim_filter_cntl
&= C_028830_SMALL_PRIM_FILTER_ENABLE
;
3309 radeon_opt_set_context_reg(sctx
,
3310 R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL
,
3311 SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL
,
3312 small_prim_filter_cntl
);
3315 /* The exclusion bits can be set to improve rasterization efficiency
3316 * if no sample lies on the pixel boundary (-8 sample offset).
3318 bool exclusion
= sctx
->chip_class
>= CIK
&&
3319 (!rs
->multisample_enable
|| nr_samples
!= 16);
3320 radeon_opt_set_context_reg(sctx
, R_02882C_PA_SU_PRIM_FILTER_CNTL
,
3321 SI_TRACKED_PA_SU_PRIM_FILTER_CNTL
,
3322 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion
) |
3323 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion
));
3326 static bool si_out_of_order_rasterization(struct si_context
*sctx
)
3328 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
3329 struct si_state_dsa
*dsa
= sctx
->queued
.named
.dsa
;
3331 if (!sctx
->screen
->has_out_of_order_rast
)
3334 unsigned colormask
= sctx
->framebuffer
.colorbuf_enabled_4bit
;
3337 colormask
&= blend
->cb_target_enabled_4bit
;
3342 /* Conservative: No logic op. */
3343 if (colormask
&& blend
->logicop_enable
)
3346 struct si_dsa_order_invariance dsa_order_invariant
= {
3347 .zs
= true, .pass_set
= true, .pass_last
= false
3350 if (sctx
->framebuffer
.state
.zsbuf
) {
3351 struct si_texture
*zstex
=
3352 (struct si_texture
*)sctx
->framebuffer
.state
.zsbuf
->texture
;
3353 bool has_stencil
= zstex
->surface
.has_stencil
;
3354 dsa_order_invariant
= dsa
->order_invariance
[has_stencil
];
3355 if (!dsa_order_invariant
.zs
)
3358 /* The set of PS invocations is always order invariant,
3359 * except when early Z/S tests are requested. */
3360 if (sctx
->ps_shader
.cso
&&
3361 sctx
->ps_shader
.cso
->info
.writes_memory
&&
3362 sctx
->ps_shader
.cso
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
] &&
3363 !dsa_order_invariant
.pass_set
)
3366 if (sctx
->num_perfect_occlusion_queries
!= 0 &&
3367 !dsa_order_invariant
.pass_set
)
3374 unsigned blendmask
= colormask
& blend
->blend_enable_4bit
;
3377 /* Only commutative blending. */
3378 if (blendmask
& ~blend
->commutative_4bit
)
3381 if (!dsa_order_invariant
.pass_set
)
3385 if (colormask
& ~blendmask
) {
3386 if (!dsa_order_invariant
.pass_last
)
3393 static void si_emit_msaa_config(struct si_context
*sctx
)
3395 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
3396 unsigned num_tile_pipes
= sctx
->screen
->info
.num_tile_pipes
;
3397 /* 33% faster rendering to linear color buffers */
3398 bool dst_is_linear
= sctx
->framebuffer
.any_dst_linear
;
3399 bool out_of_order_rast
= si_out_of_order_rasterization(sctx
);
3400 unsigned sc_mode_cntl_1
=
3401 S_028A4C_WALK_SIZE(dst_is_linear
) |
3402 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear
) |
3403 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes
== 2 ? 2 : 3) |
3404 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast
) |
3405 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
3407 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
3408 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
3409 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
3410 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
3411 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
3412 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
3413 unsigned db_eqaa
= S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3414 S_028804_INCOHERENT_EQAA_READS(1) |
3415 S_028804_INTERPOLATE_COMP_Z(1) |
3416 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
3417 unsigned coverage_samples
, color_samples
, z_samples
;
3419 /* S: Coverage samples (up to 16x):
3420 * - Scan conversion samples (PA_SC_AA_CONFIG.MSAA_NUM_SAMPLES)
3421 * - CB FMASK samples (CB_COLORi_ATTRIB.NUM_SAMPLES)
3423 * Z: Z/S samples (up to 8x, must be <= coverage samples and >= color samples):
3424 * - Value seen by DB (DB_Z_INFO.NUM_SAMPLES)
3425 * - Value seen by CB, must be correct even if Z/S is unbound (DB_EQAA.MAX_ANCHOR_SAMPLES)
3426 * # Missing samples are derived from Z planes if Z is compressed (up to 16x quality), or
3427 * # from the closest defined sample if Z is uncompressed (same quality as the number of
3430 * F: Color samples (up to 8x, must be <= coverage samples):
3431 * - CB color samples (CB_COLORi_ATTRIB.NUM_FRAGMENTS)
3432 * - PS iter samples (DB_EQAA.PS_ITER_SAMPLES)
3434 * Can be anything between coverage and color samples:
3435 * - SampleMaskIn samples (PA_SC_AA_CONFIG.MSAA_EXPOSED_SAMPLES)
3436 * - SampleMaskOut samples (DB_EQAA.MASK_EXPORT_NUM_SAMPLES)
3437 * - Alpha-to-coverage samples (DB_EQAA.ALPHA_TO_MASK_NUM_SAMPLES)
3438 * - Occlusion query samples (DB_COUNT_CONTROL.SAMPLE_RATE)
3439 * # All are currently set the same as coverage samples.
3441 * If color samples < coverage samples, FMASK has a higher bpp to store an "unknown"
3442 * flag for undefined color samples. A shader-based resolve must handle unknowns
3443 * or mask them out with AND. Unknowns can also be guessed from neighbors via
3444 * an edge-detect shader-based resolve, which is required to make "color samples = 1"
3445 * useful. The CB resolve always drops unknowns.
3447 * Sensible AA configurations:
3448 * EQAA 16s 8z 8f - might look the same as 16x MSAA if Z is compressed
3449 * EQAA 16s 8z 4f - might look the same as 16x MSAA if Z is compressed
3450 * EQAA 16s 4z 4f - might look the same as 16x MSAA if Z is compressed
3451 * EQAA 8s 8z 8f = 8x MSAA
3452 * EQAA 8s 8z 4f - might look the same as 8x MSAA
3453 * EQAA 8s 8z 2f - might look the same as 8x MSAA with low-density geometry
3454 * EQAA 8s 4z 4f - might look the same as 8x MSAA if Z is compressed
3455 * EQAA 8s 4z 2f - might look the same as 8x MSAA with low-density geometry if Z is compressed
3456 * EQAA 4s 4z 4f = 4x MSAA
3457 * EQAA 4s 4z 2f - might look the same as 4x MSAA with low-density geometry
3458 * EQAA 2s 2z 2f = 2x MSAA
3460 if (sctx
->framebuffer
.nr_samples
> 1) {
3461 coverage_samples
= sctx
->framebuffer
.nr_samples
;
3462 color_samples
= sctx
->framebuffer
.nr_color_samples
;
3464 if (sctx
->framebuffer
.state
.zsbuf
) {
3465 z_samples
= sctx
->framebuffer
.state
.zsbuf
->texture
->nr_samples
;
3466 z_samples
= MAX2(1, z_samples
);
3468 z_samples
= coverage_samples
;
3470 } else if (sctx
->smoothing_enabled
) {
3471 coverage_samples
= color_samples
= z_samples
= SI_NUM_SMOOTH_AA_SAMPLES
;
3473 coverage_samples
= color_samples
= z_samples
= 1;
3476 /* Required by OpenGL line rasterization.
3478 * TODO: We should also enable perpendicular endcaps for AA lines,
3479 * but that requires implementing line stippling in the pixel
3480 * shader. SC can only do line stippling with axis-aligned
3483 unsigned sc_line_cntl
= S_028BDC_DX10_DIAMOND_TEST_ENA(1);
3484 unsigned sc_aa_config
= 0;
3486 if (coverage_samples
> 1) {
3487 /* distance from the pixel center, indexed by log2(nr_samples) */
3488 static unsigned max_dist
[] = {
3495 unsigned log_samples
= util_logbase2(coverage_samples
);
3496 unsigned log_z_samples
= util_logbase2(z_samples
);
3497 unsigned ps_iter_samples
= si_get_ps_iter_samples(sctx
);
3498 unsigned log_ps_iter_samples
= util_logbase2(ps_iter_samples
);
3500 sc_line_cntl
|= S_028BDC_EXPAND_LINE_WIDTH(1);
3501 sc_aa_config
= S_028BE0_MSAA_NUM_SAMPLES(log_samples
) |
3502 S_028BE0_MAX_SAMPLE_DIST(max_dist
[log_samples
]) |
3503 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples
);
3505 if (sctx
->framebuffer
.nr_samples
> 1) {
3506 db_eqaa
|= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples
) |
3507 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples
) |
3508 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples
) |
3509 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples
);
3510 sc_mode_cntl_1
|= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples
> 1);
3511 } else if (sctx
->smoothing_enabled
) {
3512 db_eqaa
|= S_028804_OVERRASTERIZATION_AMOUNT(log_samples
);
3516 unsigned initial_cdw
= cs
->current
.cdw
;
3518 /* R_028BDC_PA_SC_LINE_CNTL, R_028BE0_PA_SC_AA_CONFIG */
3519 radeon_opt_set_context_reg2(sctx
, R_028BDC_PA_SC_LINE_CNTL
,
3520 SI_TRACKED_PA_SC_LINE_CNTL
, sc_line_cntl
,
3522 /* R_028804_DB_EQAA */
3523 radeon_opt_set_context_reg(sctx
, R_028804_DB_EQAA
, SI_TRACKED_DB_EQAA
,
3525 /* R_028A4C_PA_SC_MODE_CNTL_1 */
3526 radeon_opt_set_context_reg(sctx
, R_028A4C_PA_SC_MODE_CNTL_1
,
3527 SI_TRACKED_PA_SC_MODE_CNTL_1
, sc_mode_cntl_1
);
3529 if (initial_cdw
!= cs
->current
.cdw
) {
3530 sctx
->context_roll_counter
++;
3532 /* GFX9: Flush DFSM when the AA mode changes. */
3533 if (sctx
->screen
->dfsm_allowed
) {
3534 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3535 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
3540 void si_update_ps_iter_samples(struct si_context
*sctx
)
3542 if (sctx
->framebuffer
.nr_samples
> 1)
3543 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
3544 if (sctx
->screen
->dpbb_allowed
)
3545 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
3548 static void si_set_min_samples(struct pipe_context
*ctx
, unsigned min_samples
)
3550 struct si_context
*sctx
= (struct si_context
*)ctx
;
3552 /* The hardware can only do sample shading with 2^n samples. */
3553 min_samples
= util_next_power_of_two(min_samples
);
3555 if (sctx
->ps_iter_samples
== min_samples
)
3558 sctx
->ps_iter_samples
= min_samples
;
3559 sctx
->do_update_shaders
= true;
3561 si_update_ps_iter_samples(sctx
);
3569 * Build the sampler view descriptor for a buffer texture.
3570 * @param state 256-bit descriptor; only the high 128 bits are filled in
3573 si_make_buffer_descriptor(struct si_screen
*screen
, struct si_resource
*buf
,
3574 enum pipe_format format
,
3575 unsigned offset
, unsigned size
,
3578 const struct util_format_description
*desc
;
3581 unsigned num_records
;
3582 unsigned num_format
, data_format
;
3584 desc
= util_format_description(format
);
3585 first_non_void
= util_format_get_first_non_void_channel(format
);
3586 stride
= desc
->block
.bits
/ 8;
3587 num_format
= si_translate_buffer_numformat(&screen
->b
, desc
, first_non_void
);
3588 data_format
= si_translate_buffer_dataformat(&screen
->b
, desc
, first_non_void
);
3590 num_records
= size
/ stride
;
3591 num_records
= MIN2(num_records
, (buf
->b
.b
.width0
- offset
) / stride
);
3593 /* The NUM_RECORDS field has a different meaning depending on the chip,
3594 * instruction type, STRIDE, and SWIZZLE_ENABLE.
3597 * - If STRIDE == 0, it's in byte units.
3598 * - If STRIDE != 0, it's in units of STRIDE, used with inst.IDXEN.
3601 * - For SMEM and STRIDE == 0, it's in byte units.
3602 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3603 * - For VMEM and STRIDE == 0 or SWIZZLE_ENABLE == 0, it's in byte units.
3604 * - For VMEM and STRIDE != 0 and SWIZZLE_ENABLE == 1, it's in units of STRIDE.
3605 * NOTE: There is incompatibility between VMEM and SMEM opcodes due to SWIZZLE_-
3606 * ENABLE. The workaround is to set STRIDE = 0 if SWIZZLE_ENABLE == 0 when
3607 * using SMEM. This can be done in the shader by clearing STRIDE with s_and.
3608 * That way the same descriptor can be used by both SMEM and VMEM.
3611 * - For SMEM and STRIDE == 0, it's in byte units.
3612 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3613 * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
3614 * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
3616 if (screen
->info
.chip_class
>= GFX9
&& HAVE_LLVM
< 0x0800)
3617 /* When vindex == 0, LLVM < 8.0 sets IDXEN = 0, thus changing units
3618 * from STRIDE to bytes. This works around it by setting
3619 * NUM_RECORDS to at least the size of one element, so that
3620 * the first element is readable when IDXEN == 0.
3622 num_records
= num_records
? MAX2(num_records
, stride
) : 0;
3623 else if (screen
->info
.chip_class
== VI
)
3624 num_records
*= stride
;
3627 state
[5] = S_008F04_STRIDE(stride
);
3628 state
[6] = num_records
;
3629 state
[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc
->swizzle
[0])) |
3630 S_008F0C_DST_SEL_Y(si_map_swizzle(desc
->swizzle
[1])) |
3631 S_008F0C_DST_SEL_Z(si_map_swizzle(desc
->swizzle
[2])) |
3632 S_008F0C_DST_SEL_W(si_map_swizzle(desc
->swizzle
[3])) |
3633 S_008F0C_NUM_FORMAT(num_format
) |
3634 S_008F0C_DATA_FORMAT(data_format
);
3637 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle
[4])
3639 unsigned bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
3641 if (swizzle
[3] == PIPE_SWIZZLE_X
) {
3642 /* For the pre-defined border color values (white, opaque
3643 * black, transparent black), the only thing that matters is
3644 * that the alpha channel winds up in the correct place
3645 * (because the RGB channels are all the same) so either of
3646 * these enumerations will work.
3648 if (swizzle
[2] == PIPE_SWIZZLE_Y
)
3649 bc_swizzle
= V_008F20_BC_SWIZZLE_WZYX
;
3651 bc_swizzle
= V_008F20_BC_SWIZZLE_WXYZ
;
3652 } else if (swizzle
[0] == PIPE_SWIZZLE_X
) {
3653 if (swizzle
[1] == PIPE_SWIZZLE_Y
)
3654 bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
3656 bc_swizzle
= V_008F20_BC_SWIZZLE_XWYZ
;
3657 } else if (swizzle
[1] == PIPE_SWIZZLE_X
) {
3658 bc_swizzle
= V_008F20_BC_SWIZZLE_YXWZ
;
3659 } else if (swizzle
[2] == PIPE_SWIZZLE_X
) {
3660 bc_swizzle
= V_008F20_BC_SWIZZLE_ZYXW
;
3667 * Build the sampler view descriptor for a texture.
3670 si_make_texture_descriptor(struct si_screen
*screen
,
3671 struct si_texture
*tex
,
3673 enum pipe_texture_target target
,
3674 enum pipe_format pipe_format
,
3675 const unsigned char state_swizzle
[4],
3676 unsigned first_level
, unsigned last_level
,
3677 unsigned first_layer
, unsigned last_layer
,
3678 unsigned width
, unsigned height
, unsigned depth
,
3680 uint32_t *fmask_state
)
3682 struct pipe_resource
*res
= &tex
->buffer
.b
.b
;
3683 const struct util_format_description
*desc
;
3684 unsigned char swizzle
[4];
3686 unsigned num_format
, data_format
, type
, num_samples
;
3689 desc
= util_format_description(pipe_format
);
3691 num_samples
= desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
?
3692 MAX2(1, res
->nr_samples
) :
3693 MAX2(1, res
->nr_storage_samples
);
3695 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
) {
3696 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
3697 const unsigned char swizzle_yyyy
[4] = {1, 1, 1, 1};
3698 const unsigned char swizzle_wwww
[4] = {3, 3, 3, 3};
3700 switch (pipe_format
) {
3701 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
3702 case PIPE_FORMAT_X32_S8X24_UINT
:
3703 case PIPE_FORMAT_X8Z24_UNORM
:
3704 util_format_compose_swizzles(swizzle_yyyy
, state_swizzle
, swizzle
);
3706 case PIPE_FORMAT_X24S8_UINT
:
3708 * X24S8 is implemented as an 8_8_8_8 data format, to
3709 * fix texture gathers. This affects at least
3710 * GL45-CTS.texture_cube_map_array.sampling on VI.
3712 if (screen
->info
.chip_class
<= VI
)
3713 util_format_compose_swizzles(swizzle_wwww
, state_swizzle
, swizzle
);
3715 util_format_compose_swizzles(swizzle_yyyy
, state_swizzle
, swizzle
);
3718 util_format_compose_swizzles(swizzle_xxxx
, state_swizzle
, swizzle
);
3721 util_format_compose_swizzles(desc
->swizzle
, state_swizzle
, swizzle
);
3724 first_non_void
= util_format_get_first_non_void_channel(pipe_format
);
3726 switch (pipe_format
) {
3727 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
3728 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3731 if (first_non_void
< 0) {
3732 if (util_format_is_compressed(pipe_format
)) {
3733 switch (pipe_format
) {
3734 case PIPE_FORMAT_DXT1_SRGB
:
3735 case PIPE_FORMAT_DXT1_SRGBA
:
3736 case PIPE_FORMAT_DXT3_SRGBA
:
3737 case PIPE_FORMAT_DXT5_SRGBA
:
3738 case PIPE_FORMAT_BPTC_SRGBA
:
3739 case PIPE_FORMAT_ETC2_SRGB8
:
3740 case PIPE_FORMAT_ETC2_SRGB8A1
:
3741 case PIPE_FORMAT_ETC2_SRGBA8
:
3742 num_format
= V_008F14_IMG_NUM_FORMAT_SRGB
;
3744 case PIPE_FORMAT_RGTC1_SNORM
:
3745 case PIPE_FORMAT_LATC1_SNORM
:
3746 case PIPE_FORMAT_RGTC2_SNORM
:
3747 case PIPE_FORMAT_LATC2_SNORM
:
3748 case PIPE_FORMAT_ETC2_R11_SNORM
:
3749 case PIPE_FORMAT_ETC2_RG11_SNORM
:
3750 /* implies float, so use SNORM/UNORM to determine
3751 whether data is signed or not */
3752 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
3753 num_format
= V_008F14_IMG_NUM_FORMAT_SNORM
;
3756 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3759 } else if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
3760 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3762 num_format
= V_008F14_IMG_NUM_FORMAT_FLOAT
;
3764 } else if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
) {
3765 num_format
= V_008F14_IMG_NUM_FORMAT_SRGB
;
3767 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3769 switch (desc
->channel
[first_non_void
].type
) {
3770 case UTIL_FORMAT_TYPE_FLOAT
:
3771 num_format
= V_008F14_IMG_NUM_FORMAT_FLOAT
;
3773 case UTIL_FORMAT_TYPE_SIGNED
:
3774 if (desc
->channel
[first_non_void
].normalized
)
3775 num_format
= V_008F14_IMG_NUM_FORMAT_SNORM
;
3776 else if (desc
->channel
[first_non_void
].pure_integer
)
3777 num_format
= V_008F14_IMG_NUM_FORMAT_SINT
;
3779 num_format
= V_008F14_IMG_NUM_FORMAT_SSCALED
;
3781 case UTIL_FORMAT_TYPE_UNSIGNED
:
3782 if (desc
->channel
[first_non_void
].normalized
)
3783 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3784 else if (desc
->channel
[first_non_void
].pure_integer
)
3785 num_format
= V_008F14_IMG_NUM_FORMAT_UINT
;
3787 num_format
= V_008F14_IMG_NUM_FORMAT_USCALED
;
3792 data_format
= si_translate_texformat(&screen
->b
, pipe_format
, desc
, first_non_void
);
3793 if (data_format
== ~0) {
3797 /* S8 with Z32 HTILE needs a special format. */
3798 if (screen
->info
.chip_class
>= GFX9
&&
3799 pipe_format
== PIPE_FORMAT_S8_UINT
&&
3800 tex
->tc_compatible_htile
)
3801 data_format
= V_008F14_IMG_DATA_FORMAT_S8_32
;
3804 (res
->target
== PIPE_TEXTURE_CUBE
||
3805 res
->target
== PIPE_TEXTURE_CUBE_ARRAY
||
3806 (screen
->info
.chip_class
<= VI
&&
3807 res
->target
== PIPE_TEXTURE_3D
))) {
3808 /* For the purpose of shader images, treat cube maps and 3D
3809 * textures as 2D arrays. For 3D textures, the address
3810 * calculations for mipmaps are different, so we rely on the
3811 * caller to effectively disable mipmaps.
3813 type
= V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
3815 assert(res
->target
!= PIPE_TEXTURE_3D
|| (first_level
== 0 && last_level
== 0));
3817 type
= si_tex_dim(screen
, tex
, target
, num_samples
);
3820 if (type
== V_008F1C_SQ_RSRC_IMG_1D_ARRAY
) {
3822 depth
= res
->array_size
;
3823 } else if (type
== V_008F1C_SQ_RSRC_IMG_2D_ARRAY
||
3824 type
== V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
) {
3825 if (sampler
|| res
->target
!= PIPE_TEXTURE_3D
)
3826 depth
= res
->array_size
;
3827 } else if (type
== V_008F1C_SQ_RSRC_IMG_CUBE
)
3828 depth
= res
->array_size
/ 6;
3831 state
[1] = (S_008F14_DATA_FORMAT_GFX6(data_format
) |
3832 S_008F14_NUM_FORMAT_GFX6(num_format
));
3833 state
[2] = (S_008F18_WIDTH(width
- 1) |
3834 S_008F18_HEIGHT(height
- 1) |
3835 S_008F18_PERF_MOD(4));
3836 state
[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle
[0])) |
3837 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle
[1])) |
3838 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle
[2])) |
3839 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle
[3])) |
3840 S_008F1C_BASE_LEVEL(num_samples
> 1 ? 0 : first_level
) |
3841 S_008F1C_LAST_LEVEL(num_samples
> 1 ?
3842 util_logbase2(num_samples
) :
3844 S_008F1C_TYPE(type
));
3846 state
[5] = S_008F24_BASE_ARRAY(first_layer
);
3850 if (screen
->info
.chip_class
>= GFX9
) {
3851 unsigned bc_swizzle
= gfx9_border_color_swizzle(desc
->swizzle
);
3853 /* Depth is the the last accessible layer on Gfx9.
3854 * The hw doesn't need to know the total number of layers.
3856 if (type
== V_008F1C_SQ_RSRC_IMG_3D
)
3857 state
[4] |= S_008F20_DEPTH(depth
- 1);
3859 state
[4] |= S_008F20_DEPTH(last_layer
);
3861 state
[4] |= S_008F20_BC_SWIZZLE(bc_swizzle
);
3862 state
[5] |= S_008F24_MAX_MIP(num_samples
> 1 ?
3863 util_logbase2(num_samples
) :
3864 tex
->buffer
.b
.b
.last_level
);
3866 state
[3] |= S_008F1C_POW2_PAD(res
->last_level
> 0);
3867 state
[4] |= S_008F20_DEPTH(depth
- 1);
3868 state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
3871 if (tex
->dcc_offset
) {
3872 state
[6] = S_008F28_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(pipe_format
));
3874 /* The last dword is unused by hw. The shader uses it to clear
3875 * bits in the first dword of sampler state.
3877 if (screen
->info
.chip_class
<= CIK
&& res
->nr_samples
<= 1) {
3878 if (first_level
== last_level
)
3879 state
[7] = C_008F30_MAX_ANISO_RATIO
;
3881 state
[7] = 0xffffffff;
3885 /* Initialize the sampler view for FMASK. */
3886 if (tex
->surface
.fmask_size
) {
3887 uint32_t data_format
, num_format
;
3889 va
= tex
->buffer
.gpu_address
+ tex
->fmask_offset
;
3891 #define FMASK(s,f) (((unsigned)(MAX2(1, s)) * 16) + (MAX2(1, f)))
3892 if (screen
->info
.chip_class
>= GFX9
) {
3893 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK
;
3894 switch (FMASK(res
->nr_samples
, res
->nr_storage_samples
)) {
3896 num_format
= V_008F14_IMG_FMASK_8_2_1
;
3899 num_format
= V_008F14_IMG_FMASK_8_2_2
;
3902 num_format
= V_008F14_IMG_FMASK_8_4_1
;
3905 num_format
= V_008F14_IMG_FMASK_8_4_2
;
3908 num_format
= V_008F14_IMG_FMASK_8_4_4
;
3911 num_format
= V_008F14_IMG_FMASK_8_8_1
;
3914 num_format
= V_008F14_IMG_FMASK_16_8_2
;
3917 num_format
= V_008F14_IMG_FMASK_32_8_4
;
3920 num_format
= V_008F14_IMG_FMASK_32_8_8
;
3923 num_format
= V_008F14_IMG_FMASK_16_16_1
;
3926 num_format
= V_008F14_IMG_FMASK_32_16_2
;
3929 num_format
= V_008F14_IMG_FMASK_64_16_4
;
3932 num_format
= V_008F14_IMG_FMASK_64_16_8
;
3935 unreachable("invalid nr_samples");
3938 switch (FMASK(res
->nr_samples
, res
->nr_storage_samples
)) {
3940 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F1
;
3943 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2
;
3946 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F1
;
3949 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F2
;
3952 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4
;
3955 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S8_F1
;
3958 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK16_S8_F2
;
3961 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F4
;
3964 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8
;
3967 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK16_S16_F1
;
3970 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S16_F2
;
3973 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F4
;
3976 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F8
;
3979 unreachable("invalid nr_samples");
3981 num_format
= V_008F14_IMG_NUM_FORMAT_UINT
;
3985 fmask_state
[0] = (va
>> 8) | tex
->surface
.fmask_tile_swizzle
;
3986 fmask_state
[1] = S_008F14_BASE_ADDRESS_HI(va
>> 40) |
3987 S_008F14_DATA_FORMAT_GFX6(data_format
) |
3988 S_008F14_NUM_FORMAT_GFX6(num_format
);
3989 fmask_state
[2] = S_008F18_WIDTH(width
- 1) |
3990 S_008F18_HEIGHT(height
- 1);
3991 fmask_state
[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X
) |
3992 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X
) |
3993 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X
) |
3994 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X
) |
3995 S_008F1C_TYPE(si_tex_dim(screen
, tex
, target
, 0));
3997 fmask_state
[5] = S_008F24_BASE_ARRAY(first_layer
);
4001 if (screen
->info
.chip_class
>= GFX9
) {
4002 fmask_state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
);
4003 fmask_state
[4] |= S_008F20_DEPTH(last_layer
) |
4004 S_008F20_PITCH_GFX9(tex
->surface
.u
.gfx9
.fmask
.epitch
);
4005 fmask_state
[5] |= S_008F24_META_PIPE_ALIGNED(tex
->surface
.u
.gfx9
.cmask
.pipe_aligned
) |
4006 S_008F24_META_RB_ALIGNED(tex
->surface
.u
.gfx9
.cmask
.rb_aligned
);
4008 fmask_state
[3] |= S_008F1C_TILING_INDEX(tex
->surface
.u
.legacy
.fmask
.tiling_index
);
4009 fmask_state
[4] |= S_008F20_DEPTH(depth
- 1) |
4010 S_008F20_PITCH_GFX6(tex
->surface
.u
.legacy
.fmask
.pitch_in_pixels
- 1);
4011 fmask_state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
4017 * Create a sampler view.
4019 * @param ctx context
4020 * @param texture texture
4021 * @param state sampler view template
4022 * @param width0 width0 override (for compressed textures as int)
4023 * @param height0 height0 override (for compressed textures as int)
4024 * @param force_level set the base address to the level (for compressed textures)
4026 struct pipe_sampler_view
*
4027 si_create_sampler_view_custom(struct pipe_context
*ctx
,
4028 struct pipe_resource
*texture
,
4029 const struct pipe_sampler_view
*state
,
4030 unsigned width0
, unsigned height0
,
4031 unsigned force_level
)
4033 struct si_context
*sctx
= (struct si_context
*)ctx
;
4034 struct si_sampler_view
*view
= CALLOC_STRUCT(si_sampler_view
);
4035 struct si_texture
*tex
= (struct si_texture
*)texture
;
4036 unsigned base_level
, first_level
, last_level
;
4037 unsigned char state_swizzle
[4];
4038 unsigned height
, depth
, width
;
4039 unsigned last_layer
= state
->u
.tex
.last_layer
;
4040 enum pipe_format pipe_format
;
4041 const struct legacy_surf_level
*surflevel
;
4046 /* initialize base object */
4047 view
->base
= *state
;
4048 view
->base
.texture
= NULL
;
4049 view
->base
.reference
.count
= 1;
4050 view
->base
.context
= ctx
;
4053 pipe_resource_reference(&view
->base
.texture
, texture
);
4055 if (state
->format
== PIPE_FORMAT_X24S8_UINT
||
4056 state
->format
== PIPE_FORMAT_S8X24_UINT
||
4057 state
->format
== PIPE_FORMAT_X32_S8X24_UINT
||
4058 state
->format
== PIPE_FORMAT_S8_UINT
)
4059 view
->is_stencil_sampler
= true;
4061 /* Buffer resource. */
4062 if (texture
->target
== PIPE_BUFFER
) {
4063 si_make_buffer_descriptor(sctx
->screen
,
4064 si_resource(texture
),
4066 state
->u
.buf
.offset
,
4072 state_swizzle
[0] = state
->swizzle_r
;
4073 state_swizzle
[1] = state
->swizzle_g
;
4074 state_swizzle
[2] = state
->swizzle_b
;
4075 state_swizzle
[3] = state
->swizzle_a
;
4078 first_level
= state
->u
.tex
.first_level
;
4079 last_level
= state
->u
.tex
.last_level
;
4082 depth
= texture
->depth0
;
4084 if (sctx
->chip_class
<= VI
&& force_level
) {
4085 assert(force_level
== first_level
&&
4086 force_level
== last_level
);
4087 base_level
= force_level
;
4090 width
= u_minify(width
, force_level
);
4091 height
= u_minify(height
, force_level
);
4092 depth
= u_minify(depth
, force_level
);
4095 /* This is not needed if state trackers set last_layer correctly. */
4096 if (state
->target
== PIPE_TEXTURE_1D
||
4097 state
->target
== PIPE_TEXTURE_2D
||
4098 state
->target
== PIPE_TEXTURE_RECT
||
4099 state
->target
== PIPE_TEXTURE_CUBE
)
4100 last_layer
= state
->u
.tex
.first_layer
;
4102 /* Texturing with separate depth and stencil. */
4103 pipe_format
= state
->format
;
4105 /* Depth/stencil texturing sometimes needs separate texture. */
4106 if (tex
->is_depth
&& !si_can_sample_zs(tex
, view
->is_stencil_sampler
)) {
4107 if (!tex
->flushed_depth_texture
&&
4108 !si_init_flushed_depth_texture(ctx
, texture
, NULL
)) {
4109 pipe_resource_reference(&view
->base
.texture
, NULL
);
4114 assert(tex
->flushed_depth_texture
);
4116 /* Override format for the case where the flushed texture
4117 * contains only Z or only S.
4119 if (tex
->flushed_depth_texture
->buffer
.b
.b
.format
!= tex
->buffer
.b
.b
.format
)
4120 pipe_format
= tex
->flushed_depth_texture
->buffer
.b
.b
.format
;
4122 tex
= tex
->flushed_depth_texture
;
4125 surflevel
= tex
->surface
.u
.legacy
.level
;
4127 if (tex
->db_compatible
) {
4128 if (!view
->is_stencil_sampler
)
4129 pipe_format
= tex
->db_render_format
;
4131 switch (pipe_format
) {
4132 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
4133 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
4135 case PIPE_FORMAT_X8Z24_UNORM
:
4136 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
4137 /* Z24 is always stored like this for DB
4140 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
4142 case PIPE_FORMAT_X24S8_UINT
:
4143 case PIPE_FORMAT_S8X24_UINT
:
4144 case PIPE_FORMAT_X32_S8X24_UINT
:
4145 pipe_format
= PIPE_FORMAT_S8_UINT
;
4146 surflevel
= tex
->surface
.u
.legacy
.stencil_level
;
4152 view
->dcc_incompatible
=
4153 vi_dcc_formats_are_incompatible(texture
,
4154 state
->u
.tex
.first_level
,
4157 si_make_texture_descriptor(sctx
->screen
, tex
, true,
4158 state
->target
, pipe_format
, state_swizzle
,
4159 first_level
, last_level
,
4160 state
->u
.tex
.first_layer
, last_layer
,
4161 width
, height
, depth
,
4162 view
->state
, view
->fmask_state
);
4164 unsigned num_format
= G_008F14_NUM_FORMAT_GFX6(view
->state
[1]);
4166 num_format
== V_008F14_IMG_NUM_FORMAT_USCALED
||
4167 num_format
== V_008F14_IMG_NUM_FORMAT_SSCALED
||
4168 num_format
== V_008F14_IMG_NUM_FORMAT_UINT
||
4169 num_format
== V_008F14_IMG_NUM_FORMAT_SINT
;
4170 view
->base_level_info
= &surflevel
[base_level
];
4171 view
->base_level
= base_level
;
4172 view
->block_width
= util_format_get_blockwidth(pipe_format
);
4176 static struct pipe_sampler_view
*
4177 si_create_sampler_view(struct pipe_context
*ctx
,
4178 struct pipe_resource
*texture
,
4179 const struct pipe_sampler_view
*state
)
4181 return si_create_sampler_view_custom(ctx
, texture
, state
,
4182 texture
? texture
->width0
: 0,
4183 texture
? texture
->height0
: 0, 0);
4186 static void si_sampler_view_destroy(struct pipe_context
*ctx
,
4187 struct pipe_sampler_view
*state
)
4189 struct si_sampler_view
*view
= (struct si_sampler_view
*)state
;
4191 pipe_resource_reference(&state
->texture
, NULL
);
4195 static bool wrap_mode_uses_border_color(unsigned wrap
, bool linear_filter
)
4197 return wrap
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
||
4198 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
||
4200 (wrap
== PIPE_TEX_WRAP_CLAMP
||
4201 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP
));
4204 static uint32_t si_translate_border_color(struct si_context
*sctx
,
4205 const struct pipe_sampler_state
*state
,
4206 const union pipe_color_union
*color
,
4209 bool linear_filter
= state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
||
4210 state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
;
4212 if (!wrap_mode_uses_border_color(state
->wrap_s
, linear_filter
) &&
4213 !wrap_mode_uses_border_color(state
->wrap_t
, linear_filter
) &&
4214 !wrap_mode_uses_border_color(state
->wrap_r
, linear_filter
))
4215 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
);
4217 #define simple_border_types(elt) \
4219 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4220 color->elt[2] == 0 && color->elt[3] == 0) \
4221 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK); \
4222 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4223 color->elt[2] == 0 && color->elt[3] == 1) \
4224 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK); \
4225 if (color->elt[0] == 1 && color->elt[1] == 1 && \
4226 color->elt[2] == 1 && color->elt[3] == 1) \
4227 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE); \
4231 simple_border_types(ui
);
4233 simple_border_types(f
);
4235 #undef simple_border_types
4239 /* Check if the border has been uploaded already. */
4240 for (i
= 0; i
< sctx
->border_color_count
; i
++)
4241 if (memcmp(&sctx
->border_color_table
[i
], color
,
4242 sizeof(*color
)) == 0)
4245 if (i
>= SI_MAX_BORDER_COLORS
) {
4246 /* Getting 4096 unique border colors is very unlikely. */
4247 fprintf(stderr
, "radeonsi: The border color table is full. "
4248 "Any new border colors will be just black. "
4249 "Please file a bug.\n");
4250 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
);
4253 if (i
== sctx
->border_color_count
) {
4254 /* Upload a new border color. */
4255 memcpy(&sctx
->border_color_table
[i
], color
,
4257 util_memcpy_cpu_to_le32(&sctx
->border_color_map
[i
],
4258 color
, sizeof(*color
));
4259 sctx
->border_color_count
++;
4262 return S_008F3C_BORDER_COLOR_PTR(i
) |
4263 S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER
);
4266 static inline int S_FIXED(float value
, unsigned frac_bits
)
4268 return value
* (1 << frac_bits
);
4271 static inline unsigned si_tex_filter(unsigned filter
, unsigned max_aniso
)
4273 if (filter
== PIPE_TEX_FILTER_LINEAR
)
4274 return max_aniso
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
4275 : V_008F38_SQ_TEX_XY_FILTER_BILINEAR
;
4277 return max_aniso
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
4278 : V_008F38_SQ_TEX_XY_FILTER_POINT
;
4281 static inline unsigned si_tex_aniso_filter(unsigned filter
)
4294 static void *si_create_sampler_state(struct pipe_context
*ctx
,
4295 const struct pipe_sampler_state
*state
)
4297 struct si_context
*sctx
= (struct si_context
*)ctx
;
4298 struct si_screen
*sscreen
= sctx
->screen
;
4299 struct si_sampler_state
*rstate
= CALLOC_STRUCT(si_sampler_state
);
4300 unsigned max_aniso
= sscreen
->force_aniso
>= 0 ? sscreen
->force_aniso
4301 : state
->max_anisotropy
;
4302 unsigned max_aniso_ratio
= si_tex_aniso_filter(max_aniso
);
4303 union pipe_color_union clamped_border_color
;
4310 rstate
->magic
= SI_SAMPLER_STATE_MAGIC
;
4312 rstate
->val
[0] = (S_008F30_CLAMP_X(si_tex_wrap(state
->wrap_s
)) |
4313 S_008F30_CLAMP_Y(si_tex_wrap(state
->wrap_t
)) |
4314 S_008F30_CLAMP_Z(si_tex_wrap(state
->wrap_r
)) |
4315 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio
) |
4316 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state
->compare_func
)) |
4317 S_008F30_FORCE_UNNORMALIZED(!state
->normalized_coords
) |
4318 S_008F30_ANISO_THRESHOLD(max_aniso_ratio
>> 1) |
4319 S_008F30_ANISO_BIAS(max_aniso_ratio
) |
4320 S_008F30_DISABLE_CUBE_WRAP(!state
->seamless_cube_map
) |
4321 S_008F30_COMPAT_MODE(sctx
->chip_class
>= VI
));
4322 rstate
->val
[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 8)) |
4323 S_008F34_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 8)) |
4324 S_008F34_PERF_MIP(max_aniso_ratio
? max_aniso_ratio
+ 6 : 0));
4325 rstate
->val
[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 8)) |
4326 S_008F38_XY_MAG_FILTER(si_tex_filter(state
->mag_img_filter
, max_aniso
)) |
4327 S_008F38_XY_MIN_FILTER(si_tex_filter(state
->min_img_filter
, max_aniso
)) |
4328 S_008F38_MIP_FILTER(si_tex_mipfilter(state
->min_mip_filter
)) |
4329 S_008F38_MIP_POINT_PRECLAMP(0) |
4330 S_008F38_DISABLE_LSB_CEIL(sctx
->chip_class
<= VI
) |
4331 S_008F38_FILTER_PREC_FIX(1) |
4332 S_008F38_ANISO_OVERRIDE(sctx
->chip_class
>= VI
));
4333 rstate
->val
[3] = si_translate_border_color(sctx
, state
, &state
->border_color
, false);
4335 /* Create sampler resource for integer textures. */
4336 memcpy(rstate
->integer_val
, rstate
->val
, sizeof(rstate
->val
));
4337 rstate
->integer_val
[3] = si_translate_border_color(sctx
, state
, &state
->border_color
, true);
4339 /* Create sampler resource for upgraded depth textures. */
4340 memcpy(rstate
->upgraded_depth_val
, rstate
->val
, sizeof(rstate
->val
));
4342 for (unsigned i
= 0; i
< 4; ++i
) {
4343 /* Use channel 0 on purpose, so that we can use OPAQUE_WHITE
4344 * when the border color is 1.0. */
4345 clamped_border_color
.f
[i
] = CLAMP(state
->border_color
.f
[0], 0, 1);
4348 if (memcmp(&state
->border_color
, &clamped_border_color
, sizeof(clamped_border_color
)) == 0)
4349 rstate
->upgraded_depth_val
[3] |= S_008F3C_UPGRADED_DEPTH(1);
4351 rstate
->upgraded_depth_val
[3] =
4352 si_translate_border_color(sctx
, state
, &clamped_border_color
, false) |
4353 S_008F3C_UPGRADED_DEPTH(1);
4358 static void si_set_sample_mask(struct pipe_context
*ctx
, unsigned sample_mask
)
4360 struct si_context
*sctx
= (struct si_context
*)ctx
;
4362 if (sctx
->sample_mask
== (uint16_t)sample_mask
)
4365 sctx
->sample_mask
= sample_mask
;
4366 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.sample_mask
);
4369 static void si_emit_sample_mask(struct si_context
*sctx
)
4371 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
4372 unsigned mask
= sctx
->sample_mask
;
4374 /* Needed for line and polygon smoothing as well as for the Polaris
4375 * small primitive filter. We expect the state tracker to take care of
4378 assert(mask
== 0xffff || sctx
->framebuffer
.nr_samples
> 1 ||
4379 (mask
& 1 && sctx
->blitter
->running
));
4381 radeon_set_context_reg_seq(cs
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
4382 radeon_emit(cs
, mask
| (mask
<< 16));
4383 radeon_emit(cs
, mask
| (mask
<< 16));
4386 static void si_delete_sampler_state(struct pipe_context
*ctx
, void *state
)
4389 struct si_sampler_state
*s
= state
;
4391 assert(s
->magic
== SI_SAMPLER_STATE_MAGIC
);
4398 * Vertex elements & buffers
4401 struct util_fast_udiv_info32
{
4402 unsigned multiplier
; /* the "magic number" multiplier */
4403 unsigned pre_shift
; /* shift for the dividend before multiplying */
4404 unsigned post_shift
; /* shift for the dividend after multiplying */
4405 int increment
; /* 0 or 1; if set then increment the numerator, using one of
4406 the two strategies */
4409 static struct util_fast_udiv_info32
4410 util_compute_fast_udiv_info32(uint32_t D
, unsigned num_bits
)
4412 struct util_fast_udiv_info info
=
4413 util_compute_fast_udiv_info(D
, num_bits
, 32);
4415 struct util_fast_udiv_info32 result
= {
4424 static void *si_create_vertex_elements(struct pipe_context
*ctx
,
4426 const struct pipe_vertex_element
*elements
)
4428 struct si_screen
*sscreen
= (struct si_screen
*)ctx
->screen
;
4429 struct si_vertex_elements
*v
= CALLOC_STRUCT(si_vertex_elements
);
4430 bool used
[SI_NUM_VERTEX_BUFFERS
] = {};
4431 struct util_fast_udiv_info32 divisor_factors
[SI_MAX_ATTRIBS
] = {};
4432 STATIC_ASSERT(sizeof(struct util_fast_udiv_info32
) == 16);
4433 STATIC_ASSERT(sizeof(divisor_factors
[0].multiplier
) == 4);
4434 STATIC_ASSERT(sizeof(divisor_factors
[0].pre_shift
) == 4);
4435 STATIC_ASSERT(sizeof(divisor_factors
[0].post_shift
) == 4);
4436 STATIC_ASSERT(sizeof(divisor_factors
[0].increment
) == 4);
4439 assert(count
<= SI_MAX_ATTRIBS
);
4444 v
->desc_list_byte_size
= align(count
* 16, SI_CPDMA_ALIGNMENT
);
4446 for (i
= 0; i
< count
; ++i
) {
4447 const struct util_format_description
*desc
;
4448 const struct util_format_channel_description
*channel
;
4449 unsigned data_format
, num_format
;
4451 unsigned vbo_index
= elements
[i
].vertex_buffer_index
;
4452 unsigned char swizzle
[4];
4454 if (vbo_index
>= SI_NUM_VERTEX_BUFFERS
) {
4459 unsigned instance_divisor
= elements
[i
].instance_divisor
;
4460 if (instance_divisor
) {
4461 v
->uses_instance_divisors
= true;
4463 if (instance_divisor
== 1) {
4464 v
->instance_divisor_is_one
|= 1u << i
;
4466 v
->instance_divisor_is_fetched
|= 1u << i
;
4467 divisor_factors
[i
] =
4468 util_compute_fast_udiv_info32(instance_divisor
, 32);
4472 if (!used
[vbo_index
]) {
4473 v
->first_vb_use_mask
|= 1 << i
;
4474 used
[vbo_index
] = true;
4477 desc
= util_format_description(elements
[i
].src_format
);
4478 first_non_void
= util_format_get_first_non_void_channel(elements
[i
].src_format
);
4479 data_format
= si_translate_buffer_dataformat(ctx
->screen
, desc
, first_non_void
);
4480 num_format
= si_translate_buffer_numformat(ctx
->screen
, desc
, first_non_void
);
4481 channel
= first_non_void
>= 0 ? &desc
->channel
[first_non_void
] : NULL
;
4482 memcpy(swizzle
, desc
->swizzle
, sizeof(swizzle
));
4484 v
->format_size
[i
] = desc
->block
.bits
/ 8;
4485 v
->src_offset
[i
] = elements
[i
].src_offset
;
4486 v
->vertex_buffer_index
[i
] = vbo_index
;
4488 /* The hardware always treats the 2-bit alpha channel as
4489 * unsigned, so a shader workaround is needed. The affected
4490 * chips are VI and older except Stoney (GFX8.1).
4492 if (data_format
== V_008F0C_BUF_DATA_FORMAT_2_10_10_10
&&
4493 sscreen
->info
.chip_class
<= VI
&&
4494 sscreen
->info
.family
!= CHIP_STONEY
) {
4495 if (num_format
== V_008F0C_BUF_NUM_FORMAT_SNORM
) {
4496 v
->fix_fetch
[i
] = SI_FIX_FETCH_A2_SNORM
;
4497 } else if (num_format
== V_008F0C_BUF_NUM_FORMAT_SSCALED
) {
4498 v
->fix_fetch
[i
] = SI_FIX_FETCH_A2_SSCALED
;
4499 } else if (num_format
== V_008F0C_BUF_NUM_FORMAT_SINT
) {
4500 /* This isn't actually used in OpenGL. */
4501 v
->fix_fetch
[i
] = SI_FIX_FETCH_A2_SINT
;
4503 } else if (channel
&& channel
->type
== UTIL_FORMAT_TYPE_FIXED
) {
4504 if (desc
->swizzle
[3] == PIPE_SWIZZLE_1
)
4505 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBX_32_FIXED
;
4507 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_32_FIXED
;
4508 } else if (channel
&& channel
->size
== 32 && !channel
->pure_integer
) {
4509 if (channel
->type
== UTIL_FORMAT_TYPE_SIGNED
) {
4510 if (channel
->normalized
) {
4511 if (desc
->swizzle
[3] == PIPE_SWIZZLE_1
)
4512 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBX_32_SNORM
;
4514 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_32_SNORM
;
4516 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_32_SSCALED
;
4518 } else if (channel
->type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
4519 if (channel
->normalized
) {
4520 if (desc
->swizzle
[3] == PIPE_SWIZZLE_1
)
4521 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBX_32_UNORM
;
4523 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_32_UNORM
;
4525 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_32_USCALED
;
4528 } else if (channel
&& channel
->size
== 64 &&
4529 channel
->type
== UTIL_FORMAT_TYPE_FLOAT
) {
4530 switch (desc
->nr_channels
) {
4533 v
->fix_fetch
[i
] = SI_FIX_FETCH_RG_64_FLOAT
;
4534 swizzle
[0] = PIPE_SWIZZLE_X
;
4535 swizzle
[1] = PIPE_SWIZZLE_Y
;
4536 swizzle
[2] = desc
->nr_channels
== 2 ? PIPE_SWIZZLE_Z
: PIPE_SWIZZLE_0
;
4537 swizzle
[3] = desc
->nr_channels
== 2 ? PIPE_SWIZZLE_W
: PIPE_SWIZZLE_0
;
4540 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGB_64_FLOAT
;
4541 swizzle
[0] = PIPE_SWIZZLE_X
; /* 3 loads */
4542 swizzle
[1] = PIPE_SWIZZLE_Y
;
4543 swizzle
[2] = PIPE_SWIZZLE_0
;
4544 swizzle
[3] = PIPE_SWIZZLE_0
;
4547 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_64_FLOAT
;
4548 swizzle
[0] = PIPE_SWIZZLE_X
; /* 2 loads */
4549 swizzle
[1] = PIPE_SWIZZLE_Y
;
4550 swizzle
[2] = PIPE_SWIZZLE_Z
;
4551 swizzle
[3] = PIPE_SWIZZLE_W
;
4556 } else if (channel
&& desc
->nr_channels
== 3) {
4557 assert(desc
->swizzle
[0] == PIPE_SWIZZLE_X
);
4559 if (channel
->size
== 8) {
4560 if (channel
->pure_integer
)
4561 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGB_8_INT
;
4563 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGB_8
;
4564 } else if (channel
->size
== 16) {
4565 if (channel
->pure_integer
)
4566 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGB_16_INT
;
4568 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGB_16
;
4572 v
->rsrc_word3
[i
] = S_008F0C_DST_SEL_X(si_map_swizzle(swizzle
[0])) |
4573 S_008F0C_DST_SEL_Y(si_map_swizzle(swizzle
[1])) |
4574 S_008F0C_DST_SEL_Z(si_map_swizzle(swizzle
[2])) |
4575 S_008F0C_DST_SEL_W(si_map_swizzle(swizzle
[3])) |
4576 S_008F0C_NUM_FORMAT(num_format
) |
4577 S_008F0C_DATA_FORMAT(data_format
);
4580 if (v
->instance_divisor_is_fetched
) {
4581 unsigned num_divisors
= util_last_bit(v
->instance_divisor_is_fetched
);
4583 v
->instance_divisor_factor_buffer
=
4584 (struct si_resource
*)
4585 pipe_buffer_create(&sscreen
->b
, 0, PIPE_USAGE_DEFAULT
,
4586 num_divisors
* sizeof(divisor_factors
[0]));
4587 if (!v
->instance_divisor_factor_buffer
) {
4591 void *map
= sscreen
->ws
->buffer_map(v
->instance_divisor_factor_buffer
->buf
,
4592 NULL
, PIPE_TRANSFER_WRITE
);
4593 memcpy(map
, divisor_factors
, num_divisors
* sizeof(divisor_factors
[0]));
4598 static void si_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
4600 struct si_context
*sctx
= (struct si_context
*)ctx
;
4601 struct si_vertex_elements
*old
= sctx
->vertex_elements
;
4602 struct si_vertex_elements
*v
= (struct si_vertex_elements
*)state
;
4604 sctx
->vertex_elements
= v
;
4605 sctx
->vertex_buffers_dirty
= true;
4609 old
->count
!= v
->count
||
4610 old
->uses_instance_divisors
!= v
->uses_instance_divisors
||
4611 v
->uses_instance_divisors
|| /* we don't check which divisors changed */
4612 memcmp(old
->fix_fetch
, v
->fix_fetch
, sizeof(v
->fix_fetch
[0]) * v
->count
)))
4613 sctx
->do_update_shaders
= true;
4615 if (v
&& v
->instance_divisor_is_fetched
) {
4616 struct pipe_constant_buffer cb
;
4618 cb
.buffer
= &v
->instance_divisor_factor_buffer
->b
.b
;
4619 cb
.user_buffer
= NULL
;
4620 cb
.buffer_offset
= 0;
4621 cb
.buffer_size
= 0xffffffff;
4622 si_set_rw_buffer(sctx
, SI_VS_CONST_INSTANCE_DIVISORS
, &cb
);
4626 static void si_delete_vertex_element(struct pipe_context
*ctx
, void *state
)
4628 struct si_context
*sctx
= (struct si_context
*)ctx
;
4629 struct si_vertex_elements
*v
= (struct si_vertex_elements
*)state
;
4631 if (sctx
->vertex_elements
== state
)
4632 sctx
->vertex_elements
= NULL
;
4633 si_resource_reference(&v
->instance_divisor_factor_buffer
, NULL
);
4637 static void si_set_vertex_buffers(struct pipe_context
*ctx
,
4638 unsigned start_slot
, unsigned count
,
4639 const struct pipe_vertex_buffer
*buffers
)
4641 struct si_context
*sctx
= (struct si_context
*)ctx
;
4642 struct pipe_vertex_buffer
*dst
= sctx
->vertex_buffer
+ start_slot
;
4645 assert(start_slot
+ count
<= ARRAY_SIZE(sctx
->vertex_buffer
));
4648 for (i
= 0; i
< count
; i
++) {
4649 const struct pipe_vertex_buffer
*src
= buffers
+ i
;
4650 struct pipe_vertex_buffer
*dsti
= dst
+ i
;
4651 struct pipe_resource
*buf
= src
->buffer
.resource
;
4653 pipe_resource_reference(&dsti
->buffer
.resource
, buf
);
4654 dsti
->buffer_offset
= src
->buffer_offset
;
4655 dsti
->stride
= src
->stride
;
4656 si_context_add_resource_size(sctx
, buf
);
4658 si_resource(buf
)->bind_history
|= PIPE_BIND_VERTEX_BUFFER
;
4661 for (i
= 0; i
< count
; i
++) {
4662 pipe_resource_reference(&dst
[i
].buffer
.resource
, NULL
);
4665 sctx
->vertex_buffers_dirty
= true;
4672 static void si_set_tess_state(struct pipe_context
*ctx
,
4673 const float default_outer_level
[4],
4674 const float default_inner_level
[2])
4676 struct si_context
*sctx
= (struct si_context
*)ctx
;
4677 struct pipe_constant_buffer cb
;
4680 memcpy(array
, default_outer_level
, sizeof(float) * 4);
4681 memcpy(array
+4, default_inner_level
, sizeof(float) * 2);
4684 cb
.user_buffer
= NULL
;
4685 cb
.buffer_size
= sizeof(array
);
4687 si_upload_const_buffer(sctx
, (struct si_resource
**)&cb
.buffer
,
4688 (void*)array
, sizeof(array
),
4691 si_set_rw_buffer(sctx
, SI_HS_CONST_DEFAULT_TESS_LEVELS
, &cb
);
4692 pipe_resource_reference(&cb
.buffer
, NULL
);
4695 static void si_texture_barrier(struct pipe_context
*ctx
, unsigned flags
)
4697 struct si_context
*sctx
= (struct si_context
*)ctx
;
4699 si_update_fb_dirtiness_after_rendering(sctx
);
4701 /* Multisample surfaces are flushed in si_decompress_textures. */
4702 if (sctx
->framebuffer
.uncompressed_cb_mask
)
4703 si_make_CB_shader_coherent(sctx
, sctx
->framebuffer
.nr_samples
,
4704 sctx
->framebuffer
.CB_has_shader_readable_metadata
);
4707 /* This only ensures coherency for shader image/buffer stores. */
4708 static void si_memory_barrier(struct pipe_context
*ctx
, unsigned flags
)
4710 struct si_context
*sctx
= (struct si_context
*)ctx
;
4712 /* Subsequent commands must wait for all shader invocations to
4714 sctx
->flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
|
4715 SI_CONTEXT_CS_PARTIAL_FLUSH
;
4717 if (flags
& PIPE_BARRIER_CONSTANT_BUFFER
)
4718 sctx
->flags
|= SI_CONTEXT_INV_SMEM_L1
|
4719 SI_CONTEXT_INV_VMEM_L1
;
4721 if (flags
& (PIPE_BARRIER_VERTEX_BUFFER
|
4722 PIPE_BARRIER_SHADER_BUFFER
|
4723 PIPE_BARRIER_TEXTURE
|
4724 PIPE_BARRIER_IMAGE
|
4725 PIPE_BARRIER_STREAMOUT_BUFFER
|
4726 PIPE_BARRIER_GLOBAL_BUFFER
)) {
4727 /* As far as I can tell, L1 contents are written back to L2
4728 * automatically at end of shader, but the contents of other
4729 * L1 caches might still be stale. */
4730 sctx
->flags
|= SI_CONTEXT_INV_VMEM_L1
;
4733 if (flags
& PIPE_BARRIER_INDEX_BUFFER
) {
4734 /* Indices are read through TC L2 since VI.
4737 if (sctx
->screen
->info
.chip_class
<= CIK
)
4738 sctx
->flags
|= SI_CONTEXT_WRITEBACK_GLOBAL_L2
;
4741 /* MSAA color, any depth and any stencil are flushed in
4742 * si_decompress_textures when needed.
4744 if (flags
& PIPE_BARRIER_FRAMEBUFFER
&&
4745 sctx
->framebuffer
.uncompressed_cb_mask
) {
4746 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_CB
;
4748 if (sctx
->chip_class
<= VI
)
4749 sctx
->flags
|= SI_CONTEXT_WRITEBACK_GLOBAL_L2
;
4752 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
4753 if (sctx
->screen
->info
.chip_class
<= VI
&&
4754 flags
& PIPE_BARRIER_INDIRECT_BUFFER
)
4755 sctx
->flags
|= SI_CONTEXT_WRITEBACK_GLOBAL_L2
;
4758 static void *si_create_blend_custom(struct si_context
*sctx
, unsigned mode
)
4760 struct pipe_blend_state blend
;
4762 memset(&blend
, 0, sizeof(blend
));
4763 blend
.independent_blend_enable
= true;
4764 blend
.rt
[0].colormask
= 0xf;
4765 return si_create_blend_state_mode(&sctx
->b
, &blend
, mode
);
4768 static void si_init_config(struct si_context
*sctx
);
4770 void si_init_state_functions(struct si_context
*sctx
)
4772 sctx
->atoms
.s
.framebuffer
.emit
= si_emit_framebuffer_state
;
4773 sctx
->atoms
.s
.msaa_sample_locs
.emit
= si_emit_msaa_sample_locs
;
4774 sctx
->atoms
.s
.db_render_state
.emit
= si_emit_db_render_state
;
4775 sctx
->atoms
.s
.dpbb_state
.emit
= si_emit_dpbb_state
;
4776 sctx
->atoms
.s
.msaa_config
.emit
= si_emit_msaa_config
;
4777 sctx
->atoms
.s
.sample_mask
.emit
= si_emit_sample_mask
;
4778 sctx
->atoms
.s
.cb_render_state
.emit
= si_emit_cb_render_state
;
4779 sctx
->atoms
.s
.blend_color
.emit
= si_emit_blend_color
;
4780 sctx
->atoms
.s
.clip_regs
.emit
= si_emit_clip_regs
;
4781 sctx
->atoms
.s
.clip_state
.emit
= si_emit_clip_state
;
4782 sctx
->atoms
.s
.stencil_ref
.emit
= si_emit_stencil_ref
;
4784 sctx
->b
.create_blend_state
= si_create_blend_state
;
4785 sctx
->b
.bind_blend_state
= si_bind_blend_state
;
4786 sctx
->b
.delete_blend_state
= si_delete_blend_state
;
4787 sctx
->b
.set_blend_color
= si_set_blend_color
;
4789 sctx
->b
.create_rasterizer_state
= si_create_rs_state
;
4790 sctx
->b
.bind_rasterizer_state
= si_bind_rs_state
;
4791 sctx
->b
.delete_rasterizer_state
= si_delete_rs_state
;
4793 sctx
->b
.create_depth_stencil_alpha_state
= si_create_dsa_state
;
4794 sctx
->b
.bind_depth_stencil_alpha_state
= si_bind_dsa_state
;
4795 sctx
->b
.delete_depth_stencil_alpha_state
= si_delete_dsa_state
;
4797 sctx
->custom_dsa_flush
= si_create_db_flush_dsa(sctx
);
4798 sctx
->custom_blend_resolve
= si_create_blend_custom(sctx
, V_028808_CB_RESOLVE
);
4799 sctx
->custom_blend_fmask_decompress
= si_create_blend_custom(sctx
, V_028808_CB_FMASK_DECOMPRESS
);
4800 sctx
->custom_blend_eliminate_fastclear
= si_create_blend_custom(sctx
, V_028808_CB_ELIMINATE_FAST_CLEAR
);
4801 sctx
->custom_blend_dcc_decompress
= si_create_blend_custom(sctx
, V_028808_CB_DCC_DECOMPRESS
);
4803 sctx
->b
.set_clip_state
= si_set_clip_state
;
4804 sctx
->b
.set_stencil_ref
= si_set_stencil_ref
;
4806 sctx
->b
.set_framebuffer_state
= si_set_framebuffer_state
;
4808 sctx
->b
.create_sampler_state
= si_create_sampler_state
;
4809 sctx
->b
.delete_sampler_state
= si_delete_sampler_state
;
4811 sctx
->b
.create_sampler_view
= si_create_sampler_view
;
4812 sctx
->b
.sampler_view_destroy
= si_sampler_view_destroy
;
4814 sctx
->b
.set_sample_mask
= si_set_sample_mask
;
4816 sctx
->b
.create_vertex_elements_state
= si_create_vertex_elements
;
4817 sctx
->b
.bind_vertex_elements_state
= si_bind_vertex_elements
;
4818 sctx
->b
.delete_vertex_elements_state
= si_delete_vertex_element
;
4819 sctx
->b
.set_vertex_buffers
= si_set_vertex_buffers
;
4821 sctx
->b
.texture_barrier
= si_texture_barrier
;
4822 sctx
->b
.memory_barrier
= si_memory_barrier
;
4823 sctx
->b
.set_min_samples
= si_set_min_samples
;
4824 sctx
->b
.set_tess_state
= si_set_tess_state
;
4826 sctx
->b
.set_active_query_state
= si_set_active_query_state
;
4828 si_init_config(sctx
);
4831 void si_init_screen_state_functions(struct si_screen
*sscreen
)
4833 sscreen
->b
.is_format_supported
= si_is_format_supported
;
4836 static void si_set_grbm_gfx_index(struct si_context
*sctx
,
4837 struct si_pm4_state
*pm4
, unsigned value
)
4839 unsigned reg
= sctx
->chip_class
>= CIK
? R_030800_GRBM_GFX_INDEX
:
4840 R_00802C_GRBM_GFX_INDEX
;
4841 si_pm4_set_reg(pm4
, reg
, value
);
4844 static void si_set_grbm_gfx_index_se(struct si_context
*sctx
,
4845 struct si_pm4_state
*pm4
, unsigned se
)
4847 assert(se
== ~0 || se
< sctx
->screen
->info
.max_se
);
4848 si_set_grbm_gfx_index(sctx
, pm4
,
4849 (se
== ~0 ? S_030800_SE_BROADCAST_WRITES(1) :
4850 S_030800_SE_INDEX(se
)) |
4851 S_030800_SH_BROADCAST_WRITES(1) |
4852 S_030800_INSTANCE_BROADCAST_WRITES(1));
4856 si_write_harvested_raster_configs(struct si_context
*sctx
,
4857 struct si_pm4_state
*pm4
,
4858 unsigned raster_config
,
4859 unsigned raster_config_1
)
4861 unsigned num_se
= MAX2(sctx
->screen
->info
.max_se
, 1);
4862 unsigned raster_config_se
[4];
4865 ac_get_harvested_configs(&sctx
->screen
->info
,
4870 for (se
= 0; se
< num_se
; se
++) {
4871 si_set_grbm_gfx_index_se(sctx
, pm4
, se
);
4872 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
, raster_config_se
[se
]);
4874 si_set_grbm_gfx_index(sctx
, pm4
, ~0);
4876 if (sctx
->chip_class
>= CIK
) {
4877 si_pm4_set_reg(pm4
, R_028354_PA_SC_RASTER_CONFIG_1
, raster_config_1
);
4881 static void si_set_raster_config(struct si_context
*sctx
, struct si_pm4_state
*pm4
)
4883 struct si_screen
*sscreen
= sctx
->screen
;
4884 unsigned num_rb
= MIN2(sscreen
->info
.num_render_backends
, 16);
4885 unsigned rb_mask
= sscreen
->info
.enabled_rb_mask
;
4886 unsigned raster_config
= sscreen
->pa_sc_raster_config
;
4887 unsigned raster_config_1
= sscreen
->pa_sc_raster_config_1
;
4889 if (!rb_mask
|| util_bitcount(rb_mask
) >= num_rb
) {
4890 /* Always use the default config when all backends are enabled
4891 * (or when we failed to determine the enabled backends).
4893 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
,
4895 if (sctx
->chip_class
>= CIK
)
4896 si_pm4_set_reg(pm4
, R_028354_PA_SC_RASTER_CONFIG_1
,
4899 si_write_harvested_raster_configs(sctx
, pm4
, raster_config
, raster_config_1
);
4903 static void si_init_config(struct si_context
*sctx
)
4905 struct si_screen
*sscreen
= sctx
->screen
;
4906 uint64_t border_color_va
= sctx
->border_color_buffer
->gpu_address
;
4907 bool has_clear_state
= sscreen
->has_clear_state
;
4908 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
4910 /* SI, radeon kernel disabled CLEAR_STATE. */
4911 assert(has_clear_state
|| sscreen
->info
.chip_class
== SI
||
4912 sscreen
->info
.drm_major
!= 3);
4917 si_pm4_cmd_begin(pm4
, PKT3_CONTEXT_CONTROL
);
4918 si_pm4_cmd_add(pm4
, CONTEXT_CONTROL_LOAD_ENABLE(1));
4919 si_pm4_cmd_add(pm4
, CONTEXT_CONTROL_SHADOW_ENABLE(1));
4920 si_pm4_cmd_end(pm4
, false);
4922 if (has_clear_state
) {
4923 si_pm4_cmd_begin(pm4
, PKT3_CLEAR_STATE
);
4924 si_pm4_cmd_add(pm4
, 0);
4925 si_pm4_cmd_end(pm4
, false);
4928 if (sctx
->chip_class
<= VI
)
4929 si_set_raster_config(sctx
, pm4
);
4931 si_pm4_set_reg(pm4
, R_028A18_VGT_HOS_MAX_TESS_LEVEL
, fui(64));
4932 if (!has_clear_state
)
4933 si_pm4_set_reg(pm4
, R_028A1C_VGT_HOS_MIN_TESS_LEVEL
, fui(0));
4935 /* FIXME calculate these values somehow ??? */
4936 if (sctx
->chip_class
<= VI
) {
4937 si_pm4_set_reg(pm4
, R_028A54_VGT_GS_PER_ES
, SI_GS_PER_ES
);
4938 si_pm4_set_reg(pm4
, R_028A58_VGT_ES_PER_GS
, 0x40);
4941 if (!has_clear_state
) {
4942 si_pm4_set_reg(pm4
, R_028A5C_VGT_GS_PER_VS
, 0x2);
4943 si_pm4_set_reg(pm4
, R_028A8C_VGT_PRIMITIVEID_RESET
, 0x0);
4944 si_pm4_set_reg(pm4
, R_028B98_VGT_STRMOUT_BUFFER_CONFIG
, 0x0);
4947 si_pm4_set_reg(pm4
, R_028AA0_VGT_INSTANCE_STEP_RATE_0
, 1);
4948 if (!has_clear_state
)
4949 si_pm4_set_reg(pm4
, R_028AB8_VGT_VTX_CNT_EN
, 0x0);
4950 if (sctx
->chip_class
< CIK
)
4951 si_pm4_set_reg(pm4
, R_008A14_PA_CL_ENHANCE
, S_008A14_NUM_CLIP_SEQ(3) |
4952 S_008A14_CLIP_VTX_REORDER_ENA(1));
4954 /* CLEAR_STATE doesn't clear these correctly on certain generations.
4955 * I don't know why. Deduced by trial and error.
4957 if (sctx
->chip_class
<= CIK
) {
4958 si_pm4_set_reg(pm4
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
4959 si_pm4_set_reg(pm4
, R_028204_PA_SC_WINDOW_SCISSOR_TL
, S_028204_WINDOW_OFFSET_DISABLE(1));
4960 si_pm4_set_reg(pm4
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, S_028240_WINDOW_OFFSET_DISABLE(1));
4961 si_pm4_set_reg(pm4
, R_028244_PA_SC_GENERIC_SCISSOR_BR
,
4962 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
4963 si_pm4_set_reg(pm4
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 0);
4964 si_pm4_set_reg(pm4
, R_028034_PA_SC_SCREEN_SCISSOR_BR
,
4965 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
4968 if (!has_clear_state
) {
4969 si_pm4_set_reg(pm4
, R_028230_PA_SC_EDGERULE
,
4970 S_028230_ER_TRI(0xA) |
4971 S_028230_ER_POINT(0xA) |
4972 S_028230_ER_RECT(0xA) |
4973 /* Required by DX10_DIAMOND_TEST_ENA: */
4974 S_028230_ER_LINE_LR(0x1A) |
4975 S_028230_ER_LINE_RL(0x26) |
4976 S_028230_ER_LINE_TB(0xA) |
4977 S_028230_ER_LINE_BT(0xA));
4978 si_pm4_set_reg(pm4
, R_028820_PA_CL_NANINF_CNTL
, 0);
4979 si_pm4_set_reg(pm4
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 0x0);
4980 si_pm4_set_reg(pm4
, R_028AC4_DB_SRESULTS_COMPARE_STATE1
, 0x0);
4981 si_pm4_set_reg(pm4
, R_028AC8_DB_PRELOAD_CONTROL
, 0x0);
4982 si_pm4_set_reg(pm4
, R_02800C_DB_RENDER_OVERRIDE
, 0);
4985 if (sctx
->chip_class
>= GFX9
) {
4986 si_pm4_set_reg(pm4
, R_030920_VGT_MAX_VTX_INDX
, ~0);
4987 si_pm4_set_reg(pm4
, R_030924_VGT_MIN_VTX_INDX
, 0);
4988 si_pm4_set_reg(pm4
, R_030928_VGT_INDX_OFFSET
, 0);
4990 /* These registers, when written, also overwrite the CLEAR_STATE
4991 * context, so we can't rely on CLEAR_STATE setting them.
4992 * It would be an issue if there was another UMD changing them.
4994 si_pm4_set_reg(pm4
, R_028400_VGT_MAX_VTX_INDX
, ~0);
4995 si_pm4_set_reg(pm4
, R_028404_VGT_MIN_VTX_INDX
, 0);
4996 si_pm4_set_reg(pm4
, R_028408_VGT_INDX_OFFSET
, 0);
4999 if (sctx
->chip_class
>= CIK
) {
5000 if (sctx
->chip_class
>= GFX9
) {
5001 si_pm4_set_reg(pm4
, R_00B41C_SPI_SHADER_PGM_RSRC3_HS
,
5002 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
5004 si_pm4_set_reg(pm4
, R_00B51C_SPI_SHADER_PGM_RSRC3_LS
,
5005 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
5006 si_pm4_set_reg(pm4
, R_00B41C_SPI_SHADER_PGM_RSRC3_HS
,
5007 S_00B41C_WAVE_LIMIT(0x3F));
5008 si_pm4_set_reg(pm4
, R_00B31C_SPI_SHADER_PGM_RSRC3_ES
,
5009 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
5011 /* If this is 0, Bonaire can hang even if GS isn't being used.
5012 * Other chips are unaffected. These are suboptimal values,
5013 * but we don't use on-chip GS.
5015 si_pm4_set_reg(pm4
, R_028A44_VGT_GS_ONCHIP_CNTL
,
5016 S_028A44_ES_VERTS_PER_SUBGRP(64) |
5017 S_028A44_GS_PRIMS_PER_SUBGRP(4));
5019 si_pm4_set_reg(pm4
, R_00B21C_SPI_SHADER_PGM_RSRC3_GS
,
5020 S_00B21C_CU_EN(0xffff) | S_00B21C_WAVE_LIMIT(0x3F));
5022 /* Compute LATE_ALLOC_VS.LIMIT. */
5023 unsigned num_cu_per_sh
= sscreen
->info
.num_good_cu_per_sh
;
5024 unsigned late_alloc_limit
; /* The limit is per SH. */
5026 if (sctx
->family
== CHIP_KABINI
) {
5027 late_alloc_limit
= 0; /* Potential hang on Kabini. */
5028 } else if (num_cu_per_sh
<= 4) {
5029 /* Too few available compute units per SH. Disallowing
5030 * VS to run on one CU could hurt us more than late VS
5031 * allocation would help.
5033 * 2 is the highest safe number that allows us to keep
5036 late_alloc_limit
= 2;
5038 /* This is a good initial value, allowing 1 late_alloc
5039 * wave per SIMD on num_cu - 2.
5041 late_alloc_limit
= (num_cu_per_sh
- 2) * 4;
5043 /* The limit is 0-based, so 0 means 1. */
5044 assert(late_alloc_limit
> 0 && late_alloc_limit
<= 64);
5045 late_alloc_limit
-= 1;
5048 /* VS can't execute on one CU if the limit is > 2. */
5049 si_pm4_set_reg(pm4
, R_00B118_SPI_SHADER_PGM_RSRC3_VS
,
5050 S_00B118_CU_EN(late_alloc_limit
> 2 ? 0xfffe : 0xffff) |
5051 S_00B118_WAVE_LIMIT(0x3F));
5052 si_pm4_set_reg(pm4
, R_00B11C_SPI_SHADER_LATE_ALLOC_VS
,
5053 S_00B11C_LIMIT(late_alloc_limit
));
5054 si_pm4_set_reg(pm4
, R_00B01C_SPI_SHADER_PGM_RSRC3_PS
,
5055 S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
5058 if (sctx
->chip_class
>= VI
) {
5059 unsigned vgt_tess_distribution
;
5061 vgt_tess_distribution
=
5062 S_028B50_ACCUM_ISOLINE(32) |
5063 S_028B50_ACCUM_TRI(11) |
5064 S_028B50_ACCUM_QUAD(11) |
5065 S_028B50_DONUT_SPLIT(16);
5067 /* Testing with Unigine Heaven extreme tesselation yielded best results
5068 * with TRAP_SPLIT = 3.
5070 if (sctx
->family
== CHIP_FIJI
||
5071 sctx
->family
>= CHIP_POLARIS10
)
5072 vgt_tess_distribution
|= S_028B50_TRAP_SPLIT(3);
5074 si_pm4_set_reg(pm4
, R_028B50_VGT_TESS_DISTRIBUTION
, vgt_tess_distribution
);
5075 } else if (!has_clear_state
) {
5076 si_pm4_set_reg(pm4
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
, 14);
5077 si_pm4_set_reg(pm4
, R_028C5C_VGT_OUT_DEALLOC_CNTL
, 16);
5080 si_pm4_set_reg(pm4
, R_028080_TA_BC_BASE_ADDR
, border_color_va
>> 8);
5081 if (sctx
->chip_class
>= CIK
) {
5082 si_pm4_set_reg(pm4
, R_028084_TA_BC_BASE_ADDR_HI
,
5083 S_028084_ADDRESS(border_color_va
>> 40));
5085 si_pm4_add_bo(pm4
, sctx
->border_color_buffer
, RADEON_USAGE_READ
,
5086 RADEON_PRIO_BORDER_COLORS
);
5088 if (sctx
->chip_class
>= GFX9
) {
5089 unsigned num_se
= sscreen
->info
.max_se
;
5090 unsigned pc_lines
= 0;
5092 switch (sctx
->family
) {
5106 si_pm4_set_reg(pm4
, R_028C48_PA_SC_BINNER_CNTL_1
,
5107 S_028C48_MAX_ALLOC_COUNT(MIN2(128, pc_lines
/ (4 * num_se
))) |
5108 S_028C48_MAX_PRIM_PER_BATCH(1023));
5109 si_pm4_set_reg(pm4
, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
,
5110 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
5111 si_pm4_set_reg(pm4
, R_030968_VGT_INSTANCE_BASE_ID
, 0);
5114 si_pm4_upload_indirect_buffer(sctx
, pm4
);
5115 sctx
->init_config
= pm4
;