2 * Copyright 2012 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "si_build_pm4.h"
29 #include "util/u_dual_blend.h"
30 #include "util/u_format.h"
31 #include "util/u_format_s3tc.h"
32 #include "util/u_memory.h"
33 #include "util/u_resource.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/fast_idiv_by_const.h"
38 unsigned img_format
:9;
40 /* Various formats are only supported with workarounds for vertex fetch,
41 * and some 32_32_32 formats are supported natively, but only for buffers
42 * (possibly with some image support, actually, but no filtering). */
46 #include "gfx10_format_table.h"
48 static unsigned si_map_swizzle(unsigned swizzle
)
52 return V_008F0C_SQ_SEL_Y
;
54 return V_008F0C_SQ_SEL_Z
;
56 return V_008F0C_SQ_SEL_W
;
58 return V_008F0C_SQ_SEL_0
;
60 return V_008F0C_SQ_SEL_1
;
61 default: /* PIPE_SWIZZLE_X */
62 return V_008F0C_SQ_SEL_X
;
66 /* 12.4 fixed-point */
67 static unsigned si_pack_float_12p4(float x
)
70 x
>= 4096 ? 0xffff : x
* 16;
74 * Inferred framebuffer and blender state.
76 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
77 * if there is not enough PS outputs.
79 static void si_emit_cb_render_state(struct si_context
*sctx
)
81 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
82 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
83 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
84 * but you never know. */
85 uint32_t cb_target_mask
= sctx
->framebuffer
.colorbuf_enabled_4bit
;
89 cb_target_mask
&= blend
->cb_target_mask
;
91 /* Avoid a hang that happens when dual source blending is enabled
92 * but there is not enough color outputs. This is undefined behavior,
93 * so disable color writes completely.
95 * Reproducible with Unigine Heaven 4.0 and drirc missing.
97 if (blend
&& blend
->dual_src_blend
&&
98 sctx
->ps_shader
.cso
&&
99 (sctx
->ps_shader
.cso
->info
.colors_written
& 0x3) != 0x3)
102 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
103 * I think we don't have to do anything between IBs.
105 if (sctx
->screen
->dfsm_allowed
&&
106 sctx
->last_cb_target_mask
!= cb_target_mask
) {
107 sctx
->last_cb_target_mask
= cb_target_mask
;
109 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
110 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
113 unsigned initial_cdw
= cs
->current
.cdw
;
114 radeon_opt_set_context_reg(sctx
, R_028238_CB_TARGET_MASK
,
115 SI_TRACKED_CB_TARGET_MASK
, cb_target_mask
);
117 if (sctx
->chip_class
>= GFX8
) {
118 /* DCC MSAA workaround for blending.
119 * Alternatively, we can set CB_COLORi_DCC_CONTROL.OVERWRITE_-
120 * COMBINER_DISABLE, but that would be more complicated.
122 bool oc_disable
= (sctx
->chip_class
== GFX8
||
123 sctx
->chip_class
== GFX9
) &&
125 blend
->blend_enable_4bit
& cb_target_mask
&&
126 sctx
->framebuffer
.nr_samples
>= 2;
127 unsigned watermark
= sctx
->framebuffer
.dcc_overwrite_combiner_watermark
;
129 radeon_opt_set_context_reg(
130 sctx
, R_028424_CB_DCC_CONTROL
,
131 SI_TRACKED_CB_DCC_CONTROL
,
132 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
133 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark
) |
134 S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable
) |
135 S_028424_DISABLE_CONSTANT_ENCODE_REG(sctx
->screen
->has_dcc_constant_encode
));
138 /* RB+ register settings. */
139 if (sctx
->screen
->rbplus_allowed
) {
140 unsigned spi_shader_col_format
=
141 sctx
->ps_shader
.cso
?
142 sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.spi_shader_col_format
: 0;
143 unsigned sx_ps_downconvert
= 0;
144 unsigned sx_blend_opt_epsilon
= 0;
145 unsigned sx_blend_opt_control
= 0;
147 for (i
= 0; i
< sctx
->framebuffer
.state
.nr_cbufs
; i
++) {
148 struct si_surface
*surf
=
149 (struct si_surface
*)sctx
->framebuffer
.state
.cbufs
[i
];
150 unsigned format
, swap
, spi_format
, colormask
;
151 bool has_alpha
, has_rgb
;
156 format
= G_028C70_FORMAT(surf
->cb_color_info
);
157 swap
= G_028C70_COMP_SWAP(surf
->cb_color_info
);
158 spi_format
= (spi_shader_col_format
>> (i
* 4)) & 0xf;
159 colormask
= (cb_target_mask
>> (i
* 4)) & 0xf;
161 /* Set if RGB and A are present. */
162 has_alpha
= !G_028C74_FORCE_DST_ALPHA_1(surf
->cb_color_attrib
);
164 if (format
== V_028C70_COLOR_8
||
165 format
== V_028C70_COLOR_16
||
166 format
== V_028C70_COLOR_32
)
167 has_rgb
= !has_alpha
;
171 /* Check the colormask and export format. */
172 if (!(colormask
& (PIPE_MASK_RGBA
& ~PIPE_MASK_A
)))
174 if (!(colormask
& PIPE_MASK_A
))
177 if (spi_format
== V_028714_SPI_SHADER_ZERO
) {
182 /* Disable value checking for disabled channels. */
184 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
186 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
188 /* Enable down-conversion for 32bpp and smaller formats. */
190 case V_028C70_COLOR_8
:
191 case V_028C70_COLOR_8_8
:
192 case V_028C70_COLOR_8_8_8_8
:
193 /* For 1 and 2-channel formats, use the superset thereof. */
194 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
||
195 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
196 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
197 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_8_8_8_8
<< (i
* 4);
198 sx_blend_opt_epsilon
|= V_028758_8BIT_FORMAT
<< (i
* 4);
202 case V_028C70_COLOR_5_6_5
:
203 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
204 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_5_6_5
<< (i
* 4);
205 sx_blend_opt_epsilon
|= V_028758_6BIT_FORMAT
<< (i
* 4);
209 case V_028C70_COLOR_1_5_5_5
:
210 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
211 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_1_5_5_5
<< (i
* 4);
212 sx_blend_opt_epsilon
|= V_028758_5BIT_FORMAT
<< (i
* 4);
216 case V_028C70_COLOR_4_4_4_4
:
217 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
218 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_4_4_4_4
<< (i
* 4);
219 sx_blend_opt_epsilon
|= V_028758_4BIT_FORMAT
<< (i
* 4);
223 case V_028C70_COLOR_32
:
224 if (swap
== V_028C70_SWAP_STD
&&
225 spi_format
== V_028714_SPI_SHADER_32_R
)
226 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_R
<< (i
* 4);
227 else if (swap
== V_028C70_SWAP_ALT_REV
&&
228 spi_format
== V_028714_SPI_SHADER_32_AR
)
229 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_A
<< (i
* 4);
232 case V_028C70_COLOR_16
:
233 case V_028C70_COLOR_16_16
:
234 /* For 1-channel formats, use the superset thereof. */
235 if (spi_format
== V_028714_SPI_SHADER_UNORM16_ABGR
||
236 spi_format
== V_028714_SPI_SHADER_SNORM16_ABGR
||
237 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
238 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
239 if (swap
== V_028C70_SWAP_STD
||
240 swap
== V_028C70_SWAP_STD_REV
)
241 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_GR
<< (i
* 4);
243 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_AR
<< (i
* 4);
247 case V_028C70_COLOR_10_11_11
:
248 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
249 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_10_11_11
<< (i
* 4);
250 sx_blend_opt_epsilon
|= V_028758_11BIT_FORMAT
<< (i
* 4);
254 case V_028C70_COLOR_2_10_10_10
:
255 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
256 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_2_10_10_10
<< (i
* 4);
257 sx_blend_opt_epsilon
|= V_028758_10BIT_FORMAT
<< (i
* 4);
263 /* SX_PS_DOWNCONVERT, SX_BLEND_OPT_EPSILON, SX_BLEND_OPT_CONTROL */
264 radeon_opt_set_context_reg3(sctx
, R_028754_SX_PS_DOWNCONVERT
,
265 SI_TRACKED_SX_PS_DOWNCONVERT
,
266 sx_ps_downconvert
, sx_blend_opt_epsilon
,
267 sx_blend_opt_control
);
269 if (initial_cdw
!= cs
->current
.cdw
)
270 sctx
->context_roll
= true;
277 static uint32_t si_translate_blend_function(int blend_func
)
279 switch (blend_func
) {
281 return V_028780_COMB_DST_PLUS_SRC
;
282 case PIPE_BLEND_SUBTRACT
:
283 return V_028780_COMB_SRC_MINUS_DST
;
284 case PIPE_BLEND_REVERSE_SUBTRACT
:
285 return V_028780_COMB_DST_MINUS_SRC
;
287 return V_028780_COMB_MIN_DST_SRC
;
289 return V_028780_COMB_MAX_DST_SRC
;
291 PRINT_ERR("Unknown blend function %d\n", blend_func
);
298 static uint32_t si_translate_blend_factor(int blend_fact
)
300 switch (blend_fact
) {
301 case PIPE_BLENDFACTOR_ONE
:
302 return V_028780_BLEND_ONE
;
303 case PIPE_BLENDFACTOR_SRC_COLOR
:
304 return V_028780_BLEND_SRC_COLOR
;
305 case PIPE_BLENDFACTOR_SRC_ALPHA
:
306 return V_028780_BLEND_SRC_ALPHA
;
307 case PIPE_BLENDFACTOR_DST_ALPHA
:
308 return V_028780_BLEND_DST_ALPHA
;
309 case PIPE_BLENDFACTOR_DST_COLOR
:
310 return V_028780_BLEND_DST_COLOR
;
311 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
312 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
313 case PIPE_BLENDFACTOR_CONST_COLOR
:
314 return V_028780_BLEND_CONSTANT_COLOR
;
315 case PIPE_BLENDFACTOR_CONST_ALPHA
:
316 return V_028780_BLEND_CONSTANT_ALPHA
;
317 case PIPE_BLENDFACTOR_ZERO
:
318 return V_028780_BLEND_ZERO
;
319 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
320 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
321 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
322 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
323 case PIPE_BLENDFACTOR_INV_DST_ALPHA
:
324 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
325 case PIPE_BLENDFACTOR_INV_DST_COLOR
:
326 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
327 case PIPE_BLENDFACTOR_INV_CONST_COLOR
:
328 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR
;
329 case PIPE_BLENDFACTOR_INV_CONST_ALPHA
:
330 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA
;
331 case PIPE_BLENDFACTOR_SRC1_COLOR
:
332 return V_028780_BLEND_SRC1_COLOR
;
333 case PIPE_BLENDFACTOR_SRC1_ALPHA
:
334 return V_028780_BLEND_SRC1_ALPHA
;
335 case PIPE_BLENDFACTOR_INV_SRC1_COLOR
:
336 return V_028780_BLEND_INV_SRC1_COLOR
;
337 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA
:
338 return V_028780_BLEND_INV_SRC1_ALPHA
;
340 PRINT_ERR("Bad blend factor %d not supported!\n", blend_fact
);
347 static uint32_t si_translate_blend_opt_function(int blend_func
)
349 switch (blend_func
) {
351 return V_028760_OPT_COMB_ADD
;
352 case PIPE_BLEND_SUBTRACT
:
353 return V_028760_OPT_COMB_SUBTRACT
;
354 case PIPE_BLEND_REVERSE_SUBTRACT
:
355 return V_028760_OPT_COMB_REVSUBTRACT
;
357 return V_028760_OPT_COMB_MIN
;
359 return V_028760_OPT_COMB_MAX
;
361 return V_028760_OPT_COMB_BLEND_DISABLED
;
365 static uint32_t si_translate_blend_opt_factor(int blend_fact
, bool is_alpha
)
367 switch (blend_fact
) {
368 case PIPE_BLENDFACTOR_ZERO
:
369 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL
;
370 case PIPE_BLENDFACTOR_ONE
:
371 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
;
372 case PIPE_BLENDFACTOR_SRC_COLOR
:
373 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
374 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0
;
375 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
376 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
377 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1
;
378 case PIPE_BLENDFACTOR_SRC_ALPHA
:
379 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
;
380 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
381 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
;
382 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
383 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
384 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
386 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
390 static void si_blend_check_commutativity(struct si_screen
*sscreen
,
391 struct si_state_blend
*blend
,
392 enum pipe_blend_func func
,
393 enum pipe_blendfactor src
,
394 enum pipe_blendfactor dst
,
397 /* Src factor is allowed when it does not depend on Dst */
398 static const uint32_t src_allowed
=
399 (1u << PIPE_BLENDFACTOR_ONE
) |
400 (1u << PIPE_BLENDFACTOR_SRC_COLOR
) |
401 (1u << PIPE_BLENDFACTOR_SRC_ALPHA
) |
402 (1u << PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
) |
403 (1u << PIPE_BLENDFACTOR_CONST_COLOR
) |
404 (1u << PIPE_BLENDFACTOR_CONST_ALPHA
) |
405 (1u << PIPE_BLENDFACTOR_SRC1_COLOR
) |
406 (1u << PIPE_BLENDFACTOR_SRC1_ALPHA
) |
407 (1u << PIPE_BLENDFACTOR_ZERO
) |
408 (1u << PIPE_BLENDFACTOR_INV_SRC_COLOR
) |
409 (1u << PIPE_BLENDFACTOR_INV_SRC_ALPHA
) |
410 (1u << PIPE_BLENDFACTOR_INV_CONST_COLOR
) |
411 (1u << PIPE_BLENDFACTOR_INV_CONST_ALPHA
) |
412 (1u << PIPE_BLENDFACTOR_INV_SRC1_COLOR
) |
413 (1u << PIPE_BLENDFACTOR_INV_SRC1_ALPHA
);
415 if (dst
== PIPE_BLENDFACTOR_ONE
&&
416 (src_allowed
& (1u << src
))) {
417 /* Addition is commutative, but floating point addition isn't
418 * associative: subtle changes can be introduced via different
421 * Out-of-order is also non-deterministic, which means that
422 * this breaks OpenGL invariance requirements. So only enable
423 * out-of-order additive blending if explicitly allowed by a
426 if (func
== PIPE_BLEND_MAX
|| func
== PIPE_BLEND_MIN
||
427 (func
== PIPE_BLEND_ADD
&& sscreen
->commutative_blend_add
))
428 blend
->commutative_4bit
|= chanmask
;
433 * Get rid of DST in the blend factors by commuting the operands:
434 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
436 static void si_blend_remove_dst(unsigned *func
, unsigned *src_factor
,
437 unsigned *dst_factor
, unsigned expected_dst
,
438 unsigned replacement_src
)
440 if (*src_factor
== expected_dst
&&
441 *dst_factor
== PIPE_BLENDFACTOR_ZERO
) {
442 *src_factor
= PIPE_BLENDFACTOR_ZERO
;
443 *dst_factor
= replacement_src
;
445 /* Commuting the operands requires reversing subtractions. */
446 if (*func
== PIPE_BLEND_SUBTRACT
)
447 *func
= PIPE_BLEND_REVERSE_SUBTRACT
;
448 else if (*func
== PIPE_BLEND_REVERSE_SUBTRACT
)
449 *func
= PIPE_BLEND_SUBTRACT
;
453 static bool si_blend_factor_uses_dst(unsigned factor
)
455 return factor
== PIPE_BLENDFACTOR_DST_COLOR
||
456 factor
== PIPE_BLENDFACTOR_DST_ALPHA
||
457 factor
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
458 factor
== PIPE_BLENDFACTOR_INV_DST_ALPHA
||
459 factor
== PIPE_BLENDFACTOR_INV_DST_COLOR
;
462 static void *si_create_blend_state_mode(struct pipe_context
*ctx
,
463 const struct pipe_blend_state
*state
,
466 struct si_context
*sctx
= (struct si_context
*)ctx
;
467 struct si_state_blend
*blend
= CALLOC_STRUCT(si_state_blend
);
468 struct si_pm4_state
*pm4
= &blend
->pm4
;
469 uint32_t sx_mrt_blend_opt
[8] = {0};
470 uint32_t color_control
= 0;
475 blend
->alpha_to_coverage
= state
->alpha_to_coverage
;
476 blend
->alpha_to_one
= state
->alpha_to_one
;
477 blend
->dual_src_blend
= util_blend_state_is_dual(state
, 0);
478 blend
->logicop_enable
= state
->logicop_enable
;
480 if (state
->logicop_enable
) {
481 color_control
|= S_028808_ROP3(state
->logicop_func
| (state
->logicop_func
<< 4));
483 color_control
|= S_028808_ROP3(0xcc);
486 si_pm4_set_reg(pm4
, R_028B70_DB_ALPHA_TO_MASK
,
487 S_028B70_ALPHA_TO_MASK_ENABLE(state
->alpha_to_coverage
) |
488 S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
489 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
490 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
491 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
492 S_028B70_OFFSET_ROUND(1));
494 if (state
->alpha_to_coverage
)
495 blend
->need_src_alpha_4bit
|= 0xf;
497 blend
->cb_target_mask
= 0;
498 blend
->cb_target_enabled_4bit
= 0;
500 for (int i
= 0; i
< 8; i
++) {
501 /* state->rt entries > 0 only written if independent blending */
502 const int j
= state
->independent_blend_enable
? i
: 0;
504 unsigned eqRGB
= state
->rt
[j
].rgb_func
;
505 unsigned srcRGB
= state
->rt
[j
].rgb_src_factor
;
506 unsigned dstRGB
= state
->rt
[j
].rgb_dst_factor
;
507 unsigned eqA
= state
->rt
[j
].alpha_func
;
508 unsigned srcA
= state
->rt
[j
].alpha_src_factor
;
509 unsigned dstA
= state
->rt
[j
].alpha_dst_factor
;
511 unsigned srcRGB_opt
, dstRGB_opt
, srcA_opt
, dstA_opt
;
512 unsigned blend_cntl
= 0;
514 sx_mrt_blend_opt
[i
] =
515 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) |
516 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
518 /* Only set dual source blending for MRT0 to avoid a hang. */
519 if (i
>= 1 && blend
->dual_src_blend
) {
520 /* Vulkan does this for dual source blending. */
522 blend_cntl
|= S_028780_ENABLE(1);
524 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
528 /* Only addition and subtraction equations are supported with
529 * dual source blending.
531 if (blend
->dual_src_blend
&&
532 (eqRGB
== PIPE_BLEND_MIN
|| eqRGB
== PIPE_BLEND_MAX
||
533 eqA
== PIPE_BLEND_MIN
|| eqA
== PIPE_BLEND_MAX
)) {
534 assert(!"Unsupported equation for dual source blending");
535 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
539 /* cb_render_state will disable unused ones */
540 blend
->cb_target_mask
|= (unsigned)state
->rt
[j
].colormask
<< (4 * i
);
541 if (state
->rt
[j
].colormask
)
542 blend
->cb_target_enabled_4bit
|= 0xf << (4 * i
);
544 if (!state
->rt
[j
].colormask
|| !state
->rt
[j
].blend_enable
) {
545 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
549 si_blend_check_commutativity(sctx
->screen
, blend
,
550 eqRGB
, srcRGB
, dstRGB
, 0x7 << (4 * i
));
551 si_blend_check_commutativity(sctx
->screen
, blend
,
552 eqA
, srcA
, dstA
, 0x8 << (4 * i
));
554 /* Blending optimizations for RB+.
555 * These transformations don't change the behavior.
557 * First, get rid of DST in the blend factors:
558 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
560 si_blend_remove_dst(&eqRGB
, &srcRGB
, &dstRGB
,
561 PIPE_BLENDFACTOR_DST_COLOR
,
562 PIPE_BLENDFACTOR_SRC_COLOR
);
563 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
564 PIPE_BLENDFACTOR_DST_COLOR
,
565 PIPE_BLENDFACTOR_SRC_COLOR
);
566 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
567 PIPE_BLENDFACTOR_DST_ALPHA
,
568 PIPE_BLENDFACTOR_SRC_ALPHA
);
570 /* Look up the ideal settings from tables. */
571 srcRGB_opt
= si_translate_blend_opt_factor(srcRGB
, false);
572 dstRGB_opt
= si_translate_blend_opt_factor(dstRGB
, false);
573 srcA_opt
= si_translate_blend_opt_factor(srcA
, true);
574 dstA_opt
= si_translate_blend_opt_factor(dstA
, true);
576 /* Handle interdependencies. */
577 if (si_blend_factor_uses_dst(srcRGB
))
578 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
579 if (si_blend_factor_uses_dst(srcA
))
580 dstA_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
582 if (srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
&&
583 (dstRGB
== PIPE_BLENDFACTOR_ZERO
||
584 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
585 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
))
586 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
588 /* Set the final value. */
589 sx_mrt_blend_opt
[i
] =
590 S_028760_COLOR_SRC_OPT(srcRGB_opt
) |
591 S_028760_COLOR_DST_OPT(dstRGB_opt
) |
592 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB
)) |
593 S_028760_ALPHA_SRC_OPT(srcA_opt
) |
594 S_028760_ALPHA_DST_OPT(dstA_opt
) |
595 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA
));
597 /* Set blend state. */
598 blend_cntl
|= S_028780_ENABLE(1);
599 blend_cntl
|= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB
));
600 blend_cntl
|= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB
));
601 blend_cntl
|= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB
));
603 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
604 blend_cntl
|= S_028780_SEPARATE_ALPHA_BLEND(1);
605 blend_cntl
|= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA
));
606 blend_cntl
|= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA
));
607 blend_cntl
|= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA
));
609 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
611 blend
->blend_enable_4bit
|= 0xfu
<< (i
* 4);
613 /* This is only important for formats without alpha. */
614 if (srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
615 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
616 srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
617 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
618 srcRGB
== PIPE_BLENDFACTOR_INV_SRC_ALPHA
||
619 dstRGB
== PIPE_BLENDFACTOR_INV_SRC_ALPHA
)
620 blend
->need_src_alpha_4bit
|= 0xfu
<< (i
* 4);
623 if (blend
->cb_target_mask
) {
624 color_control
|= S_028808_MODE(mode
);
626 color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
629 if (sctx
->screen
->rbplus_allowed
) {
630 /* Disable RB+ blend optimizations for dual source blending.
633 if (blend
->dual_src_blend
) {
634 for (int i
= 0; i
< 8; i
++) {
635 sx_mrt_blend_opt
[i
] =
636 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE
) |
637 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE
);
641 for (int i
= 0; i
< 8; i
++)
642 si_pm4_set_reg(pm4
, R_028760_SX_MRT0_BLEND_OPT
+ i
* 4,
643 sx_mrt_blend_opt
[i
]);
645 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
646 if (blend
->dual_src_blend
|| state
->logicop_enable
||
647 mode
== V_028808_CB_RESOLVE
)
648 color_control
|= S_028808_DISABLE_DUAL_QUAD(1);
651 si_pm4_set_reg(pm4
, R_028808_CB_COLOR_CONTROL
, color_control
);
655 static void *si_create_blend_state(struct pipe_context
*ctx
,
656 const struct pipe_blend_state
*state
)
658 return si_create_blend_state_mode(ctx
, state
, V_028808_CB_NORMAL
);
661 static void si_bind_blend_state(struct pipe_context
*ctx
, void *state
)
663 struct si_context
*sctx
= (struct si_context
*)ctx
;
664 struct si_state_blend
*old_blend
= sctx
->queued
.named
.blend
;
665 struct si_state_blend
*blend
= (struct si_state_blend
*)state
;
670 si_pm4_bind_state(sctx
, blend
, state
);
673 old_blend
->cb_target_mask
!= blend
->cb_target_mask
||
674 old_blend
->dual_src_blend
!= blend
->dual_src_blend
||
675 (old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
&&
676 sctx
->framebuffer
.nr_samples
>= 2 &&
677 sctx
->screen
->dcc_msaa_allowed
))
678 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
681 old_blend
->cb_target_mask
!= blend
->cb_target_mask
||
682 old_blend
->alpha_to_coverage
!= blend
->alpha_to_coverage
||
683 old_blend
->alpha_to_one
!= blend
->alpha_to_one
||
684 old_blend
->dual_src_blend
!= blend
->dual_src_blend
||
685 old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
||
686 old_blend
->need_src_alpha_4bit
!= blend
->need_src_alpha_4bit
)
687 sctx
->do_update_shaders
= true;
689 if (sctx
->screen
->dpbb_allowed
&&
691 old_blend
->alpha_to_coverage
!= blend
->alpha_to_coverage
||
692 old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
||
693 old_blend
->cb_target_enabled_4bit
!= blend
->cb_target_enabled_4bit
))
694 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
696 if (sctx
->screen
->has_out_of_order_rast
&&
698 (old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
||
699 old_blend
->cb_target_enabled_4bit
!= blend
->cb_target_enabled_4bit
||
700 old_blend
->commutative_4bit
!= blend
->commutative_4bit
||
701 old_blend
->logicop_enable
!= blend
->logicop_enable
)))
702 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
705 static void si_delete_blend_state(struct pipe_context
*ctx
, void *state
)
707 struct si_context
*sctx
= (struct si_context
*)ctx
;
708 si_pm4_delete_state(sctx
, blend
, (struct si_state_blend
*)state
);
711 static void si_set_blend_color(struct pipe_context
*ctx
,
712 const struct pipe_blend_color
*state
)
714 struct si_context
*sctx
= (struct si_context
*)ctx
;
715 static const struct pipe_blend_color zeros
;
717 sctx
->blend_color
.state
= *state
;
718 sctx
->blend_color
.any_nonzeros
= memcmp(state
, &zeros
, sizeof(*state
)) != 0;
719 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.blend_color
);
722 static void si_emit_blend_color(struct si_context
*sctx
)
724 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
726 radeon_set_context_reg_seq(cs
, R_028414_CB_BLEND_RED
, 4);
727 radeon_emit_array(cs
, (uint32_t*)sctx
->blend_color
.state
.color
, 4);
734 static void si_set_clip_state(struct pipe_context
*ctx
,
735 const struct pipe_clip_state
*state
)
737 struct si_context
*sctx
= (struct si_context
*)ctx
;
738 struct pipe_constant_buffer cb
;
739 static const struct pipe_clip_state zeros
;
741 if (memcmp(&sctx
->clip_state
.state
, state
, sizeof(*state
)) == 0)
744 sctx
->clip_state
.state
= *state
;
745 sctx
->clip_state
.any_nonzeros
= memcmp(state
, &zeros
, sizeof(*state
)) != 0;
746 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_state
);
749 cb
.user_buffer
= state
->ucp
;
750 cb
.buffer_offset
= 0;
751 cb
.buffer_size
= 4*4*8;
752 si_set_rw_buffer(sctx
, SI_VS_CONST_CLIP_PLANES
, &cb
);
753 pipe_resource_reference(&cb
.buffer
, NULL
);
756 static void si_emit_clip_state(struct si_context
*sctx
)
758 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
760 radeon_set_context_reg_seq(cs
, R_0285BC_PA_CL_UCP_0_X
, 6*4);
761 radeon_emit_array(cs
, (uint32_t*)sctx
->clip_state
.state
.ucp
, 6*4);
764 static void si_emit_clip_regs(struct si_context
*sctx
)
766 struct si_shader
*vs
= si_get_vs_state(sctx
);
767 struct si_shader_selector
*vs_sel
= vs
->selector
;
768 struct tgsi_shader_info
*info
= &vs_sel
->info
;
769 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
770 unsigned window_space
=
771 info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
772 unsigned clipdist_mask
= vs_sel
->clipdist_mask
;
773 unsigned ucp_mask
= clipdist_mask
? 0 : rs
->clip_plane_enable
& SIX_BITS
;
774 unsigned culldist_mask
= vs_sel
->culldist_mask
;
777 if (vs
->key
.opt
.clip_disable
) {
778 assert(!info
->culldist_writemask
);
782 total_mask
= clipdist_mask
| culldist_mask
;
784 /* Clip distances on points have no effect, so need to be implemented
785 * as cull distances. This applies for the clipvertex case as well.
787 * Setting this for primitives other than points should have no adverse
790 clipdist_mask
&= rs
->clip_plane_enable
;
791 culldist_mask
|= clipdist_mask
;
793 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
794 radeon_opt_set_context_reg(sctx
, R_02881C_PA_CL_VS_OUT_CNTL
,
795 SI_TRACKED_PA_CL_VS_OUT_CNTL
,
796 vs_sel
->pa_cl_vs_out_cntl
|
797 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0F) != 0) |
798 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xF0) != 0) |
799 clipdist_mask
| (culldist_mask
<< 8));
800 radeon_opt_set_context_reg(sctx
, R_028810_PA_CL_CLIP_CNTL
,
801 SI_TRACKED_PA_CL_CLIP_CNTL
,
802 rs
->pa_cl_clip_cntl
|
804 S_028810_CLIP_DISABLE(window_space
));
806 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
807 sctx
->context_roll
= true;
811 * inferred state between framebuffer and rasterizer
813 static void si_update_poly_offset_state(struct si_context
*sctx
)
815 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
817 if (!rs
|| !rs
->uses_poly_offset
|| !sctx
->framebuffer
.state
.zsbuf
) {
818 si_pm4_bind_state(sctx
, poly_offset
, NULL
);
822 /* Use the user format, not db_render_format, so that the polygon
823 * offset behaves as expected by applications.
825 switch (sctx
->framebuffer
.state
.zsbuf
->texture
->format
) {
826 case PIPE_FORMAT_Z16_UNORM
:
827 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[0]);
829 default: /* 24-bit */
830 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[1]);
832 case PIPE_FORMAT_Z32_FLOAT
:
833 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
834 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[2]);
843 static uint32_t si_translate_fill(uint32_t func
)
846 case PIPE_POLYGON_MODE_FILL
:
847 return V_028814_X_DRAW_TRIANGLES
;
848 case PIPE_POLYGON_MODE_LINE
:
849 return V_028814_X_DRAW_LINES
;
850 case PIPE_POLYGON_MODE_POINT
:
851 return V_028814_X_DRAW_POINTS
;
854 return V_028814_X_DRAW_POINTS
;
858 static void *si_create_rs_state(struct pipe_context
*ctx
,
859 const struct pipe_rasterizer_state
*state
)
861 struct si_screen
*sscreen
= ((struct si_context
*)ctx
)->screen
;
862 struct si_state_rasterizer
*rs
= CALLOC_STRUCT(si_state_rasterizer
);
863 struct si_pm4_state
*pm4
= &rs
->pm4
;
865 float psize_min
, psize_max
;
871 if (!state
->front_ccw
) {
872 rs
->cull_front
= !!(state
->cull_face
& PIPE_FACE_FRONT
);
873 rs
->cull_back
= !!(state
->cull_face
& PIPE_FACE_BACK
);
875 rs
->cull_back
= !!(state
->cull_face
& PIPE_FACE_FRONT
);
876 rs
->cull_front
= !!(state
->cull_face
& PIPE_FACE_BACK
);
878 rs
->depth_clamp_any
= !state
->depth_clip_near
|| !state
->depth_clip_far
;
879 rs
->provoking_vertex_first
= state
->flatshade_first
;
880 rs
->scissor_enable
= state
->scissor
;
881 rs
->clip_halfz
= state
->clip_halfz
;
882 rs
->two_side
= state
->light_twoside
;
883 rs
->multisample_enable
= state
->multisample
;
884 rs
->force_persample_interp
= state
->force_persample_interp
;
885 rs
->clip_plane_enable
= state
->clip_plane_enable
;
886 rs
->half_pixel_center
= state
->half_pixel_center
;
887 rs
->line_stipple_enable
= state
->line_stipple_enable
;
888 rs
->poly_stipple_enable
= state
->poly_stipple_enable
;
889 rs
->line_smooth
= state
->line_smooth
;
890 rs
->line_width
= state
->line_width
;
891 rs
->poly_smooth
= state
->poly_smooth
;
892 rs
->uses_poly_offset
= state
->offset_point
|| state
->offset_line
||
894 rs
->clamp_fragment_color
= state
->clamp_fragment_color
;
895 rs
->clamp_vertex_color
= state
->clamp_vertex_color
;
896 rs
->flatshade
= state
->flatshade
;
897 rs
->sprite_coord_enable
= state
->sprite_coord_enable
;
898 rs
->rasterizer_discard
= state
->rasterizer_discard
;
899 rs
->pa_sc_line_stipple
= state
->line_stipple_enable
?
900 S_028A0C_LINE_PATTERN(state
->line_stipple_pattern
) |
901 S_028A0C_REPEAT_COUNT(state
->line_stipple_factor
) : 0;
902 rs
->pa_cl_clip_cntl
=
903 S_028810_DX_CLIP_SPACE_DEF(state
->clip_halfz
) |
904 S_028810_ZCLIP_NEAR_DISABLE(!state
->depth_clip_near
) |
905 S_028810_ZCLIP_FAR_DISABLE(!state
->depth_clip_far
) |
906 S_028810_DX_RASTERIZATION_KILL(state
->rasterizer_discard
) |
907 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
909 si_pm4_set_reg(pm4
, R_0286D4_SPI_INTERP_CONTROL_0
,
910 S_0286D4_FLAT_SHADE_ENA(1) |
911 S_0286D4_PNT_SPRITE_ENA(state
->point_quad_rasterization
) |
912 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S
) |
913 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T
) |
914 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0
) |
915 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1
) |
916 S_0286D4_PNT_SPRITE_TOP_1(state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
));
918 /* point size 12.4 fixed point */
919 tmp
= (unsigned)(state
->point_size
* 8.0);
920 si_pm4_set_reg(pm4
, R_028A00_PA_SU_POINT_SIZE
, S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
));
922 if (state
->point_size_per_vertex
) {
923 psize_min
= util_get_min_point_size(state
);
924 psize_max
= SI_MAX_POINT_SIZE
;
926 /* Force the point size to be as if the vertex output was disabled. */
927 psize_min
= state
->point_size
;
928 psize_max
= state
->point_size
;
930 rs
->max_point_size
= psize_max
;
932 /* Divide by two, because 0.5 = 1 pixel. */
933 si_pm4_set_reg(pm4
, R_028A04_PA_SU_POINT_MINMAX
,
934 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min
/2)) |
935 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max
/2)));
937 si_pm4_set_reg(pm4
, R_028A08_PA_SU_LINE_CNTL
,
938 S_028A08_WIDTH(si_pack_float_12p4(state
->line_width
/2)));
939 si_pm4_set_reg(pm4
, R_028A48_PA_SC_MODE_CNTL_0
,
940 S_028A48_LINE_STIPPLE_ENABLE(state
->line_stipple_enable
) |
941 S_028A48_MSAA_ENABLE(state
->multisample
||
942 state
->poly_smooth
||
943 state
->line_smooth
) |
944 S_028A48_VPORT_SCISSOR_ENABLE(1) |
945 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen
->info
.chip_class
>= GFX9
));
947 si_pm4_set_reg(pm4
, R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, fui(state
->offset_clamp
));
948 si_pm4_set_reg(pm4
, R_028814_PA_SU_SC_MODE_CNTL
,
949 S_028814_PROVOKING_VTX_LAST(!state
->flatshade_first
) |
950 S_028814_CULL_FRONT((state
->cull_face
& PIPE_FACE_FRONT
) ? 1 : 0) |
951 S_028814_CULL_BACK((state
->cull_face
& PIPE_FACE_BACK
) ? 1 : 0) |
952 S_028814_FACE(!state
->front_ccw
) |
953 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state
, state
->fill_front
)) |
954 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state
, state
->fill_back
)) |
955 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_point
|| state
->offset_line
) |
956 S_028814_POLY_MODE(state
->fill_front
!= PIPE_POLYGON_MODE_FILL
||
957 state
->fill_back
!= PIPE_POLYGON_MODE_FILL
) |
958 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state
->fill_front
)) |
959 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state
->fill_back
)));
961 if (!rs
->uses_poly_offset
)
964 rs
->pm4_poly_offset
= CALLOC(3, sizeof(struct si_pm4_state
));
965 if (!rs
->pm4_poly_offset
) {
970 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
971 for (i
= 0; i
< 3; i
++) {
972 struct si_pm4_state
*pm4
= &rs
->pm4_poly_offset
[i
];
973 float offset_units
= state
->offset_units
;
974 float offset_scale
= state
->offset_scale
* 16.0f
;
975 uint32_t pa_su_poly_offset_db_fmt_cntl
= 0;
977 if (!state
->offset_units_unscaled
) {
979 case 0: /* 16-bit zbuffer */
980 offset_units
*= 4.0f
;
981 pa_su_poly_offset_db_fmt_cntl
=
982 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
984 case 1: /* 24-bit zbuffer */
985 offset_units
*= 2.0f
;
986 pa_su_poly_offset_db_fmt_cntl
=
987 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
989 case 2: /* 32-bit zbuffer */
990 offset_units
*= 1.0f
;
991 pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
992 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
997 si_pm4_set_reg(pm4
, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE
,
999 si_pm4_set_reg(pm4
, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET
,
1001 si_pm4_set_reg(pm4
, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE
,
1003 si_pm4_set_reg(pm4
, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET
,
1005 si_pm4_set_reg(pm4
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
1006 pa_su_poly_offset_db_fmt_cntl
);
1012 static void si_bind_rs_state(struct pipe_context
*ctx
, void *state
)
1014 struct si_context
*sctx
= (struct si_context
*)ctx
;
1015 struct si_state_rasterizer
*old_rs
=
1016 (struct si_state_rasterizer
*)sctx
->queued
.named
.rasterizer
;
1017 struct si_state_rasterizer
*rs
= (struct si_state_rasterizer
*)state
;
1022 if (!old_rs
|| old_rs
->multisample_enable
!= rs
->multisample_enable
) {
1023 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
1025 /* Update the small primitive filter workaround if necessary. */
1026 if (sctx
->screen
->has_msaa_sample_loc_bug
&&
1027 sctx
->framebuffer
.nr_samples
> 1)
1028 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_sample_locs
);
1031 sctx
->current_vs_state
&= C_VS_STATE_CLAMP_VERTEX_COLOR
;
1032 sctx
->current_vs_state
|= S_VS_STATE_CLAMP_VERTEX_COLOR(rs
->clamp_vertex_color
);
1034 si_pm4_bind_state(sctx
, rasterizer
, rs
);
1035 si_update_poly_offset_state(sctx
);
1038 old_rs
->scissor_enable
!= rs
->scissor_enable
)
1039 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.scissors
);
1042 old_rs
->line_width
!= rs
->line_width
||
1043 old_rs
->max_point_size
!= rs
->max_point_size
||
1044 old_rs
->half_pixel_center
!= rs
->half_pixel_center
)
1045 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.guardband
);
1048 old_rs
->clip_halfz
!= rs
->clip_halfz
)
1049 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.viewports
);
1052 old_rs
->clip_plane_enable
!= rs
->clip_plane_enable
||
1053 old_rs
->pa_cl_clip_cntl
!= rs
->pa_cl_clip_cntl
)
1054 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_regs
);
1056 sctx
->ia_multi_vgt_param_key
.u
.line_stipple_enabled
=
1057 rs
->line_stipple_enable
;
1060 old_rs
->clip_plane_enable
!= rs
->clip_plane_enable
||
1061 old_rs
->rasterizer_discard
!= rs
->rasterizer_discard
||
1062 old_rs
->sprite_coord_enable
!= rs
->sprite_coord_enable
||
1063 old_rs
->flatshade
!= rs
->flatshade
||
1064 old_rs
->two_side
!= rs
->two_side
||
1065 old_rs
->multisample_enable
!= rs
->multisample_enable
||
1066 old_rs
->poly_stipple_enable
!= rs
->poly_stipple_enable
||
1067 old_rs
->poly_smooth
!= rs
->poly_smooth
||
1068 old_rs
->line_smooth
!= rs
->line_smooth
||
1069 old_rs
->clamp_fragment_color
!= rs
->clamp_fragment_color
||
1070 old_rs
->force_persample_interp
!= rs
->force_persample_interp
)
1071 sctx
->do_update_shaders
= true;
1074 static void si_delete_rs_state(struct pipe_context
*ctx
, void *state
)
1076 struct si_context
*sctx
= (struct si_context
*)ctx
;
1077 struct si_state_rasterizer
*rs
= (struct si_state_rasterizer
*)state
;
1079 if (sctx
->queued
.named
.rasterizer
== state
)
1080 si_pm4_bind_state(sctx
, poly_offset
, NULL
);
1082 FREE(rs
->pm4_poly_offset
);
1083 si_pm4_delete_state(sctx
, rasterizer
, rs
);
1087 * infeered state between dsa and stencil ref
1089 static void si_emit_stencil_ref(struct si_context
*sctx
)
1091 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
1092 struct pipe_stencil_ref
*ref
= &sctx
->stencil_ref
.state
;
1093 struct si_dsa_stencil_ref_part
*dsa
= &sctx
->stencil_ref
.dsa_part
;
1095 radeon_set_context_reg_seq(cs
, R_028430_DB_STENCILREFMASK
, 2);
1096 radeon_emit(cs
, S_028430_STENCILTESTVAL(ref
->ref_value
[0]) |
1097 S_028430_STENCILMASK(dsa
->valuemask
[0]) |
1098 S_028430_STENCILWRITEMASK(dsa
->writemask
[0]) |
1099 S_028430_STENCILOPVAL(1));
1100 radeon_emit(cs
, S_028434_STENCILTESTVAL_BF(ref
->ref_value
[1]) |
1101 S_028434_STENCILMASK_BF(dsa
->valuemask
[1]) |
1102 S_028434_STENCILWRITEMASK_BF(dsa
->writemask
[1]) |
1103 S_028434_STENCILOPVAL_BF(1));
1106 static void si_set_stencil_ref(struct pipe_context
*ctx
,
1107 const struct pipe_stencil_ref
*state
)
1109 struct si_context
*sctx
= (struct si_context
*)ctx
;
1111 if (memcmp(&sctx
->stencil_ref
.state
, state
, sizeof(*state
)) == 0)
1114 sctx
->stencil_ref
.state
= *state
;
1115 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.stencil_ref
);
1123 static uint32_t si_translate_stencil_op(int s_op
)
1126 case PIPE_STENCIL_OP_KEEP
:
1127 return V_02842C_STENCIL_KEEP
;
1128 case PIPE_STENCIL_OP_ZERO
:
1129 return V_02842C_STENCIL_ZERO
;
1130 case PIPE_STENCIL_OP_REPLACE
:
1131 return V_02842C_STENCIL_REPLACE_TEST
;
1132 case PIPE_STENCIL_OP_INCR
:
1133 return V_02842C_STENCIL_ADD_CLAMP
;
1134 case PIPE_STENCIL_OP_DECR
:
1135 return V_02842C_STENCIL_SUB_CLAMP
;
1136 case PIPE_STENCIL_OP_INCR_WRAP
:
1137 return V_02842C_STENCIL_ADD_WRAP
;
1138 case PIPE_STENCIL_OP_DECR_WRAP
:
1139 return V_02842C_STENCIL_SUB_WRAP
;
1140 case PIPE_STENCIL_OP_INVERT
:
1141 return V_02842C_STENCIL_INVERT
;
1143 PRINT_ERR("Unknown stencil op %d", s_op
);
1150 static bool si_dsa_writes_stencil(const struct pipe_stencil_state
*s
)
1152 return s
->enabled
&& s
->writemask
&&
1153 (s
->fail_op
!= PIPE_STENCIL_OP_KEEP
||
1154 s
->zfail_op
!= PIPE_STENCIL_OP_KEEP
||
1155 s
->zpass_op
!= PIPE_STENCIL_OP_KEEP
);
1158 static bool si_order_invariant_stencil_op(enum pipe_stencil_op op
)
1160 /* REPLACE is normally order invariant, except when the stencil
1161 * reference value is written by the fragment shader. Tracking this
1162 * interaction does not seem worth the effort, so be conservative. */
1163 return op
!= PIPE_STENCIL_OP_INCR
&&
1164 op
!= PIPE_STENCIL_OP_DECR
&&
1165 op
!= PIPE_STENCIL_OP_REPLACE
;
1168 /* Compute whether, assuming Z writes are disabled, this stencil state is order
1169 * invariant in the sense that the set of passing fragments as well as the
1170 * final stencil buffer result does not depend on the order of fragments. */
1171 static bool si_order_invariant_stencil_state(const struct pipe_stencil_state
*state
)
1173 return !state
->enabled
|| !state
->writemask
||
1174 /* The following assumes that Z writes are disabled. */
1175 (state
->func
== PIPE_FUNC_ALWAYS
&&
1176 si_order_invariant_stencil_op(state
->zpass_op
) &&
1177 si_order_invariant_stencil_op(state
->zfail_op
)) ||
1178 (state
->func
== PIPE_FUNC_NEVER
&&
1179 si_order_invariant_stencil_op(state
->fail_op
));
1182 static void *si_create_dsa_state(struct pipe_context
*ctx
,
1183 const struct pipe_depth_stencil_alpha_state
*state
)
1185 struct si_context
*sctx
= (struct si_context
*)ctx
;
1186 struct si_state_dsa
*dsa
= CALLOC_STRUCT(si_state_dsa
);
1187 struct si_pm4_state
*pm4
= &dsa
->pm4
;
1188 unsigned db_depth_control
;
1189 uint32_t db_stencil_control
= 0;
1195 dsa
->stencil_ref
.valuemask
[0] = state
->stencil
[0].valuemask
;
1196 dsa
->stencil_ref
.valuemask
[1] = state
->stencil
[1].valuemask
;
1197 dsa
->stencil_ref
.writemask
[0] = state
->stencil
[0].writemask
;
1198 dsa
->stencil_ref
.writemask
[1] = state
->stencil
[1].writemask
;
1200 db_depth_control
= S_028800_Z_ENABLE(state
->depth
.enabled
) |
1201 S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
1202 S_028800_ZFUNC(state
->depth
.func
) |
1203 S_028800_DEPTH_BOUNDS_ENABLE(state
->depth
.bounds_test
);
1206 if (state
->stencil
[0].enabled
) {
1207 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
1208 db_depth_control
|= S_028800_STENCILFUNC(state
->stencil
[0].func
);
1209 db_stencil_control
|= S_02842C_STENCILFAIL(si_translate_stencil_op(state
->stencil
[0].fail_op
));
1210 db_stencil_control
|= S_02842C_STENCILZPASS(si_translate_stencil_op(state
->stencil
[0].zpass_op
));
1211 db_stencil_control
|= S_02842C_STENCILZFAIL(si_translate_stencil_op(state
->stencil
[0].zfail_op
));
1213 if (state
->stencil
[1].enabled
) {
1214 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
1215 db_depth_control
|= S_028800_STENCILFUNC_BF(state
->stencil
[1].func
);
1216 db_stencil_control
|= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state
->stencil
[1].fail_op
));
1217 db_stencil_control
|= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state
->stencil
[1].zpass_op
));
1218 db_stencil_control
|= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state
->stencil
[1].zfail_op
));
1223 if (state
->alpha
.enabled
) {
1224 dsa
->alpha_func
= state
->alpha
.func
;
1226 si_pm4_set_reg(pm4
, R_00B030_SPI_SHADER_USER_DATA_PS_0
+
1227 SI_SGPR_ALPHA_REF
* 4, fui(state
->alpha
.ref_value
));
1229 dsa
->alpha_func
= PIPE_FUNC_ALWAYS
;
1232 si_pm4_set_reg(pm4
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
1233 if (state
->stencil
[0].enabled
)
1234 si_pm4_set_reg(pm4
, R_02842C_DB_STENCIL_CONTROL
, db_stencil_control
);
1235 if (state
->depth
.bounds_test
) {
1236 si_pm4_set_reg(pm4
, R_028020_DB_DEPTH_BOUNDS_MIN
, fui(state
->depth
.bounds_min
));
1237 si_pm4_set_reg(pm4
, R_028024_DB_DEPTH_BOUNDS_MAX
, fui(state
->depth
.bounds_max
));
1240 dsa
->depth_enabled
= state
->depth
.enabled
;
1241 dsa
->depth_write_enabled
= state
->depth
.enabled
&&
1242 state
->depth
.writemask
;
1243 dsa
->stencil_enabled
= state
->stencil
[0].enabled
;
1244 dsa
->stencil_write_enabled
= state
->stencil
[0].enabled
&&
1245 (si_dsa_writes_stencil(&state
->stencil
[0]) ||
1246 si_dsa_writes_stencil(&state
->stencil
[1]));
1247 dsa
->db_can_write
= dsa
->depth_write_enabled
||
1248 dsa
->stencil_write_enabled
;
1250 bool zfunc_is_ordered
=
1251 state
->depth
.func
== PIPE_FUNC_NEVER
||
1252 state
->depth
.func
== PIPE_FUNC_LESS
||
1253 state
->depth
.func
== PIPE_FUNC_LEQUAL
||
1254 state
->depth
.func
== PIPE_FUNC_GREATER
||
1255 state
->depth
.func
== PIPE_FUNC_GEQUAL
;
1257 bool nozwrite_and_order_invariant_stencil
=
1258 !dsa
->db_can_write
||
1259 (!dsa
->depth_write_enabled
&&
1260 si_order_invariant_stencil_state(&state
->stencil
[0]) &&
1261 si_order_invariant_stencil_state(&state
->stencil
[1]));
1263 dsa
->order_invariance
[1].zs
=
1264 nozwrite_and_order_invariant_stencil
||
1265 (!dsa
->stencil_write_enabled
&& zfunc_is_ordered
);
1266 dsa
->order_invariance
[0].zs
= !dsa
->depth_write_enabled
|| zfunc_is_ordered
;
1268 dsa
->order_invariance
[1].pass_set
=
1269 nozwrite_and_order_invariant_stencil
||
1270 (!dsa
->stencil_write_enabled
&&
1271 (state
->depth
.func
== PIPE_FUNC_ALWAYS
||
1272 state
->depth
.func
== PIPE_FUNC_NEVER
));
1273 dsa
->order_invariance
[0].pass_set
=
1274 !dsa
->depth_write_enabled
||
1275 (state
->depth
.func
== PIPE_FUNC_ALWAYS
||
1276 state
->depth
.func
== PIPE_FUNC_NEVER
);
1278 dsa
->order_invariance
[1].pass_last
=
1279 sctx
->screen
->assume_no_z_fights
&&
1280 !dsa
->stencil_write_enabled
&&
1281 dsa
->depth_write_enabled
&& zfunc_is_ordered
;
1282 dsa
->order_invariance
[0].pass_last
=
1283 sctx
->screen
->assume_no_z_fights
&&
1284 dsa
->depth_write_enabled
&& zfunc_is_ordered
;
1289 static void si_bind_dsa_state(struct pipe_context
*ctx
, void *state
)
1291 struct si_context
*sctx
= (struct si_context
*)ctx
;
1292 struct si_state_dsa
*old_dsa
= sctx
->queued
.named
.dsa
;
1293 struct si_state_dsa
*dsa
= state
;
1298 si_pm4_bind_state(sctx
, dsa
, dsa
);
1300 if (memcmp(&dsa
->stencil_ref
, &sctx
->stencil_ref
.dsa_part
,
1301 sizeof(struct si_dsa_stencil_ref_part
)) != 0) {
1302 sctx
->stencil_ref
.dsa_part
= dsa
->stencil_ref
;
1303 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.stencil_ref
);
1306 if (!old_dsa
|| old_dsa
->alpha_func
!= dsa
->alpha_func
)
1307 sctx
->do_update_shaders
= true;
1309 if (sctx
->screen
->dpbb_allowed
&&
1311 (old_dsa
->depth_enabled
!= dsa
->depth_enabled
||
1312 old_dsa
->stencil_enabled
!= dsa
->stencil_enabled
||
1313 old_dsa
->db_can_write
!= dsa
->db_can_write
)))
1314 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
1316 if (sctx
->screen
->has_out_of_order_rast
&&
1318 memcmp(old_dsa
->order_invariance
, dsa
->order_invariance
,
1319 sizeof(old_dsa
->order_invariance
))))
1320 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
1323 static void si_delete_dsa_state(struct pipe_context
*ctx
, void *state
)
1325 struct si_context
*sctx
= (struct si_context
*)ctx
;
1326 si_pm4_delete_state(sctx
, dsa
, (struct si_state_dsa
*)state
);
1329 static void *si_create_db_flush_dsa(struct si_context
*sctx
)
1331 struct pipe_depth_stencil_alpha_state dsa
= {};
1333 return sctx
->b
.create_depth_stencil_alpha_state(&sctx
->b
, &dsa
);
1336 /* DB RENDER STATE */
1338 static void si_set_active_query_state(struct pipe_context
*ctx
, boolean enable
)
1340 struct si_context
*sctx
= (struct si_context
*)ctx
;
1342 /* Pipeline stat & streamout queries. */
1344 sctx
->flags
&= ~SI_CONTEXT_STOP_PIPELINE_STATS
;
1345 sctx
->flags
|= SI_CONTEXT_START_PIPELINE_STATS
;
1347 sctx
->flags
&= ~SI_CONTEXT_START_PIPELINE_STATS
;
1348 sctx
->flags
|= SI_CONTEXT_STOP_PIPELINE_STATS
;
1351 /* Occlusion queries. */
1352 if (sctx
->occlusion_queries_disabled
!= !enable
) {
1353 sctx
->occlusion_queries_disabled
= !enable
;
1354 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
1358 void si_set_occlusion_query_state(struct si_context
*sctx
,
1359 bool old_perfect_enable
)
1361 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
1363 bool perfect_enable
= sctx
->num_perfect_occlusion_queries
!= 0;
1365 if (perfect_enable
!= old_perfect_enable
)
1366 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
1369 void si_save_qbo_state(struct si_context
*sctx
, struct si_qbo_state
*st
)
1371 st
->saved_compute
= sctx
->cs_shader_state
.program
;
1373 si_get_pipe_constant_buffer(sctx
, PIPE_SHADER_COMPUTE
, 0, &st
->saved_const0
);
1374 si_get_shader_buffers(sctx
, PIPE_SHADER_COMPUTE
, 0, 3, st
->saved_ssbo
);
1376 st
->saved_ssbo_writable_mask
= 0;
1378 for (unsigned i
= 0; i
< 3; i
++) {
1379 if (sctx
->const_and_shader_buffers
[PIPE_SHADER_COMPUTE
].writable_mask
&
1380 (1u << si_get_shaderbuf_slot(i
)))
1381 st
->saved_ssbo_writable_mask
|= 1 << i
;
1385 void si_restore_qbo_state(struct si_context
*sctx
, struct si_qbo_state
*st
)
1387 sctx
->b
.bind_compute_state(&sctx
->b
, st
->saved_compute
);
1389 sctx
->b
.set_constant_buffer(&sctx
->b
, PIPE_SHADER_COMPUTE
, 0, &st
->saved_const0
);
1390 pipe_resource_reference(&st
->saved_const0
.buffer
, NULL
);
1392 sctx
->b
.set_shader_buffers(&sctx
->b
, PIPE_SHADER_COMPUTE
, 0, 3, st
->saved_ssbo
,
1393 st
->saved_ssbo_writable_mask
);
1394 for (unsigned i
= 0; i
< 3; ++i
)
1395 pipe_resource_reference(&st
->saved_ssbo
[i
].buffer
, NULL
);
1398 static void si_emit_db_render_state(struct si_context
*sctx
)
1400 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
1401 unsigned db_shader_control
, db_render_control
, db_count_control
;
1402 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1404 /* DB_RENDER_CONTROL */
1405 if (sctx
->dbcb_depth_copy_enabled
||
1406 sctx
->dbcb_stencil_copy_enabled
) {
1408 S_028000_DEPTH_COPY(sctx
->dbcb_depth_copy_enabled
) |
1409 S_028000_STENCIL_COPY(sctx
->dbcb_stencil_copy_enabled
) |
1410 S_028000_COPY_CENTROID(1) |
1411 S_028000_COPY_SAMPLE(sctx
->dbcb_copy_sample
);
1412 } else if (sctx
->db_flush_depth_inplace
|| sctx
->db_flush_stencil_inplace
) {
1414 S_028000_DEPTH_COMPRESS_DISABLE(sctx
->db_flush_depth_inplace
) |
1415 S_028000_STENCIL_COMPRESS_DISABLE(sctx
->db_flush_stencil_inplace
);
1418 S_028000_DEPTH_CLEAR_ENABLE(sctx
->db_depth_clear
) |
1419 S_028000_STENCIL_CLEAR_ENABLE(sctx
->db_stencil_clear
);
1422 /* DB_COUNT_CONTROL (occlusion queries) */
1423 if (sctx
->num_occlusion_queries
> 0 &&
1424 !sctx
->occlusion_queries_disabled
) {
1425 bool perfect
= sctx
->num_perfect_occlusion_queries
> 0;
1427 if (sctx
->chip_class
>= GFX7
) {
1428 unsigned log_sample_rate
= sctx
->framebuffer
.log_samples
;
1430 /* Stoney doesn't increment occlusion query counters
1431 * if the sample rate is 16x. Use 8x sample rate instead.
1433 if (sctx
->family
== CHIP_STONEY
)
1434 log_sample_rate
= MIN2(log_sample_rate
, 3);
1437 S_028004_PERFECT_ZPASS_COUNTS(perfect
) |
1438 S_028004_SAMPLE_RATE(log_sample_rate
) |
1439 S_028004_ZPASS_ENABLE(1) |
1440 S_028004_SLICE_EVEN_ENABLE(1) |
1441 S_028004_SLICE_ODD_ENABLE(1);
1444 S_028004_PERFECT_ZPASS_COUNTS(perfect
) |
1445 S_028004_SAMPLE_RATE(sctx
->framebuffer
.log_samples
);
1448 /* Disable occlusion queries. */
1449 if (sctx
->chip_class
>= GFX7
) {
1450 db_count_control
= 0;
1452 db_count_control
= S_028004_ZPASS_INCREMENT_DISABLE(1);
1456 radeon_opt_set_context_reg2(sctx
, R_028000_DB_RENDER_CONTROL
,
1457 SI_TRACKED_DB_RENDER_CONTROL
, db_render_control
,
1460 /* DB_RENDER_OVERRIDE2 */
1461 radeon_opt_set_context_reg(sctx
, R_028010_DB_RENDER_OVERRIDE2
,
1462 SI_TRACKED_DB_RENDER_OVERRIDE2
,
1463 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx
->db_depth_disable_expclear
) |
1464 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx
->db_stencil_disable_expclear
) |
1465 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx
->framebuffer
.nr_samples
>= 4));
1467 db_shader_control
= sctx
->ps_db_shader_control
;
1469 /* Bug workaround for smoothing (overrasterization) on GFX6. */
1470 if (sctx
->chip_class
== GFX6
&& sctx
->smoothing_enabled
) {
1471 db_shader_control
&= C_02880C_Z_ORDER
;
1472 db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
);
1475 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1476 if (!rs
->multisample_enable
)
1477 db_shader_control
&= C_02880C_MASK_EXPORT_ENABLE
;
1479 if (sctx
->screen
->has_rbplus
&&
1480 !sctx
->screen
->rbplus_allowed
)
1481 db_shader_control
|= S_02880C_DUAL_QUAD_DISABLE(1);
1483 radeon_opt_set_context_reg(sctx
, R_02880C_DB_SHADER_CONTROL
,
1484 SI_TRACKED_DB_SHADER_CONTROL
, db_shader_control
);
1486 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
1487 sctx
->context_roll
= true;
1491 * format translation
1493 static uint32_t si_translate_colorformat(enum pipe_format format
)
1495 const struct util_format_description
*desc
= util_format_description(format
);
1497 return V_028C70_COLOR_INVALID
;
1499 #define HAS_SIZE(x,y,z,w) \
1500 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1501 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1503 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
1504 return V_028C70_COLOR_10_11_11
;
1506 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
1507 return V_028C70_COLOR_INVALID
;
1509 /* hw cannot support mixed formats (except depth/stencil, since
1510 * stencil is not written to). */
1511 if (desc
->is_mixed
&& desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
)
1512 return V_028C70_COLOR_INVALID
;
1514 switch (desc
->nr_channels
) {
1516 switch (desc
->channel
[0].size
) {
1518 return V_028C70_COLOR_8
;
1520 return V_028C70_COLOR_16
;
1522 return V_028C70_COLOR_32
;
1526 if (desc
->channel
[0].size
== desc
->channel
[1].size
) {
1527 switch (desc
->channel
[0].size
) {
1529 return V_028C70_COLOR_8_8
;
1531 return V_028C70_COLOR_16_16
;
1533 return V_028C70_COLOR_32_32
;
1535 } else if (HAS_SIZE(8,24,0,0)) {
1536 return V_028C70_COLOR_24_8
;
1537 } else if (HAS_SIZE(24,8,0,0)) {
1538 return V_028C70_COLOR_8_24
;
1542 if (HAS_SIZE(5,6,5,0)) {
1543 return V_028C70_COLOR_5_6_5
;
1544 } else if (HAS_SIZE(32,8,24,0)) {
1545 return V_028C70_COLOR_X24_8_32_FLOAT
;
1549 if (desc
->channel
[0].size
== desc
->channel
[1].size
&&
1550 desc
->channel
[0].size
== desc
->channel
[2].size
&&
1551 desc
->channel
[0].size
== desc
->channel
[3].size
) {
1552 switch (desc
->channel
[0].size
) {
1554 return V_028C70_COLOR_4_4_4_4
;
1556 return V_028C70_COLOR_8_8_8_8
;
1558 return V_028C70_COLOR_16_16_16_16
;
1560 return V_028C70_COLOR_32_32_32_32
;
1562 } else if (HAS_SIZE(5,5,5,1)) {
1563 return V_028C70_COLOR_1_5_5_5
;
1564 } else if (HAS_SIZE(1,5,5,5)) {
1565 return V_028C70_COLOR_5_5_5_1
;
1566 } else if (HAS_SIZE(10,10,10,2)) {
1567 return V_028C70_COLOR_2_10_10_10
;
1571 return V_028C70_COLOR_INVALID
;
1574 static uint32_t si_colorformat_endian_swap(uint32_t colorformat
)
1576 if (SI_BIG_ENDIAN
) {
1577 switch(colorformat
) {
1578 /* 8-bit buffers. */
1579 case V_028C70_COLOR_8
:
1580 return V_028C70_ENDIAN_NONE
;
1582 /* 16-bit buffers. */
1583 case V_028C70_COLOR_5_6_5
:
1584 case V_028C70_COLOR_1_5_5_5
:
1585 case V_028C70_COLOR_4_4_4_4
:
1586 case V_028C70_COLOR_16
:
1587 case V_028C70_COLOR_8_8
:
1588 return V_028C70_ENDIAN_8IN16
;
1590 /* 32-bit buffers. */
1591 case V_028C70_COLOR_8_8_8_8
:
1592 case V_028C70_COLOR_2_10_10_10
:
1593 case V_028C70_COLOR_8_24
:
1594 case V_028C70_COLOR_24_8
:
1595 case V_028C70_COLOR_16_16
:
1596 return V_028C70_ENDIAN_8IN32
;
1598 /* 64-bit buffers. */
1599 case V_028C70_COLOR_16_16_16_16
:
1600 return V_028C70_ENDIAN_8IN16
;
1602 case V_028C70_COLOR_32_32
:
1603 return V_028C70_ENDIAN_8IN32
;
1605 /* 128-bit buffers. */
1606 case V_028C70_COLOR_32_32_32_32
:
1607 return V_028C70_ENDIAN_8IN32
;
1609 return V_028C70_ENDIAN_NONE
; /* Unsupported. */
1612 return V_028C70_ENDIAN_NONE
;
1616 static uint32_t si_translate_dbformat(enum pipe_format format
)
1619 case PIPE_FORMAT_Z16_UNORM
:
1620 return V_028040_Z_16
;
1621 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1622 case PIPE_FORMAT_X8Z24_UNORM
:
1623 case PIPE_FORMAT_Z24X8_UNORM
:
1624 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1625 return V_028040_Z_24
; /* deprecated on AMD GCN */
1626 case PIPE_FORMAT_Z32_FLOAT
:
1627 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1628 return V_028040_Z_32_FLOAT
;
1630 return V_028040_Z_INVALID
;
1635 * Texture translation
1638 static uint32_t si_translate_texformat(struct pipe_screen
*screen
,
1639 enum pipe_format format
,
1640 const struct util_format_description
*desc
,
1643 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1644 bool uniform
= true;
1647 assert(sscreen
->info
.chip_class
<= GFX9
);
1649 /* Colorspace (return non-RGB formats directly). */
1650 switch (desc
->colorspace
) {
1651 /* Depth stencil formats */
1652 case UTIL_FORMAT_COLORSPACE_ZS
:
1654 case PIPE_FORMAT_Z16_UNORM
:
1655 return V_008F14_IMG_DATA_FORMAT_16
;
1656 case PIPE_FORMAT_X24S8_UINT
:
1657 case PIPE_FORMAT_S8X24_UINT
:
1659 * Implemented as an 8_8_8_8 data format to fix texture
1660 * gathers in stencil sampling. This affects at least
1661 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
1663 if (sscreen
->info
.chip_class
<= GFX8
)
1664 return V_008F14_IMG_DATA_FORMAT_8_8_8_8
;
1666 if (format
== PIPE_FORMAT_X24S8_UINT
)
1667 return V_008F14_IMG_DATA_FORMAT_8_24
;
1669 return V_008F14_IMG_DATA_FORMAT_24_8
;
1670 case PIPE_FORMAT_Z24X8_UNORM
:
1671 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1672 return V_008F14_IMG_DATA_FORMAT_8_24
;
1673 case PIPE_FORMAT_X8Z24_UNORM
:
1674 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1675 return V_008F14_IMG_DATA_FORMAT_24_8
;
1676 case PIPE_FORMAT_S8_UINT
:
1677 return V_008F14_IMG_DATA_FORMAT_8
;
1678 case PIPE_FORMAT_Z32_FLOAT
:
1679 return V_008F14_IMG_DATA_FORMAT_32
;
1680 case PIPE_FORMAT_X32_S8X24_UINT
:
1681 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1682 return V_008F14_IMG_DATA_FORMAT_X24_8_32
;
1687 case UTIL_FORMAT_COLORSPACE_YUV
:
1688 goto out_unknown
; /* TODO */
1690 case UTIL_FORMAT_COLORSPACE_SRGB
:
1691 if (desc
->nr_channels
!= 4 && desc
->nr_channels
!= 1)
1699 if (desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
) {
1700 if (!sscreen
->info
.has_format_bc1_through_bc7
)
1704 case PIPE_FORMAT_RGTC1_SNORM
:
1705 case PIPE_FORMAT_LATC1_SNORM
:
1706 case PIPE_FORMAT_RGTC1_UNORM
:
1707 case PIPE_FORMAT_LATC1_UNORM
:
1708 return V_008F14_IMG_DATA_FORMAT_BC4
;
1709 case PIPE_FORMAT_RGTC2_SNORM
:
1710 case PIPE_FORMAT_LATC2_SNORM
:
1711 case PIPE_FORMAT_RGTC2_UNORM
:
1712 case PIPE_FORMAT_LATC2_UNORM
:
1713 return V_008F14_IMG_DATA_FORMAT_BC5
;
1719 if (desc
->layout
== UTIL_FORMAT_LAYOUT_ETC
&&
1720 (sscreen
->info
.family
== CHIP_STONEY
||
1721 sscreen
->info
.family
== CHIP_VEGA10
||
1722 sscreen
->info
.family
== CHIP_RAVEN
)) {
1724 case PIPE_FORMAT_ETC1_RGB8
:
1725 case PIPE_FORMAT_ETC2_RGB8
:
1726 case PIPE_FORMAT_ETC2_SRGB8
:
1727 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB
;
1728 case PIPE_FORMAT_ETC2_RGB8A1
:
1729 case PIPE_FORMAT_ETC2_SRGB8A1
:
1730 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1
;
1731 case PIPE_FORMAT_ETC2_RGBA8
:
1732 case PIPE_FORMAT_ETC2_SRGBA8
:
1733 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA
;
1734 case PIPE_FORMAT_ETC2_R11_UNORM
:
1735 case PIPE_FORMAT_ETC2_R11_SNORM
:
1736 return V_008F14_IMG_DATA_FORMAT_ETC2_R
;
1737 case PIPE_FORMAT_ETC2_RG11_UNORM
:
1738 case PIPE_FORMAT_ETC2_RG11_SNORM
:
1739 return V_008F14_IMG_DATA_FORMAT_ETC2_RG
;
1745 if (desc
->layout
== UTIL_FORMAT_LAYOUT_BPTC
) {
1746 if (!sscreen
->info
.has_format_bc1_through_bc7
)
1750 case PIPE_FORMAT_BPTC_RGBA_UNORM
:
1751 case PIPE_FORMAT_BPTC_SRGBA
:
1752 return V_008F14_IMG_DATA_FORMAT_BC7
;
1753 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
1754 case PIPE_FORMAT_BPTC_RGB_UFLOAT
:
1755 return V_008F14_IMG_DATA_FORMAT_BC6
;
1761 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
1763 case PIPE_FORMAT_R8G8_B8G8_UNORM
:
1764 case PIPE_FORMAT_G8R8_B8R8_UNORM
:
1765 return V_008F14_IMG_DATA_FORMAT_GB_GR
;
1766 case PIPE_FORMAT_G8R8_G8B8_UNORM
:
1767 case PIPE_FORMAT_R8G8_R8B8_UNORM
:
1768 return V_008F14_IMG_DATA_FORMAT_BG_RG
;
1774 if (desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
1775 if (!sscreen
->info
.has_format_bc1_through_bc7
)
1779 case PIPE_FORMAT_DXT1_RGB
:
1780 case PIPE_FORMAT_DXT1_RGBA
:
1781 case PIPE_FORMAT_DXT1_SRGB
:
1782 case PIPE_FORMAT_DXT1_SRGBA
:
1783 return V_008F14_IMG_DATA_FORMAT_BC1
;
1784 case PIPE_FORMAT_DXT3_RGBA
:
1785 case PIPE_FORMAT_DXT3_SRGBA
:
1786 return V_008F14_IMG_DATA_FORMAT_BC2
;
1787 case PIPE_FORMAT_DXT5_RGBA
:
1788 case PIPE_FORMAT_DXT5_SRGBA
:
1789 return V_008F14_IMG_DATA_FORMAT_BC3
;
1795 if (format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
1796 return V_008F14_IMG_DATA_FORMAT_5_9_9_9
;
1797 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
1798 return V_008F14_IMG_DATA_FORMAT_10_11_11
;
1801 /* R8G8Bx_SNORM - TODO CxV8U8 */
1803 /* hw cannot support mixed formats (except depth/stencil, since only
1805 if (desc
->is_mixed
&& desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
)
1808 /* See whether the components are of the same size. */
1809 for (i
= 1; i
< desc
->nr_channels
; i
++) {
1810 uniform
= uniform
&& desc
->channel
[0].size
== desc
->channel
[i
].size
;
1813 /* Non-uniform formats. */
1815 switch(desc
->nr_channels
) {
1817 if (desc
->channel
[0].size
== 5 &&
1818 desc
->channel
[1].size
== 6 &&
1819 desc
->channel
[2].size
== 5) {
1820 return V_008F14_IMG_DATA_FORMAT_5_6_5
;
1824 if (desc
->channel
[0].size
== 5 &&
1825 desc
->channel
[1].size
== 5 &&
1826 desc
->channel
[2].size
== 5 &&
1827 desc
->channel
[3].size
== 1) {
1828 return V_008F14_IMG_DATA_FORMAT_1_5_5_5
;
1830 if (desc
->channel
[0].size
== 1 &&
1831 desc
->channel
[1].size
== 5 &&
1832 desc
->channel
[2].size
== 5 &&
1833 desc
->channel
[3].size
== 5) {
1834 return V_008F14_IMG_DATA_FORMAT_5_5_5_1
;
1836 if (desc
->channel
[0].size
== 10 &&
1837 desc
->channel
[1].size
== 10 &&
1838 desc
->channel
[2].size
== 10 &&
1839 desc
->channel
[3].size
== 2) {
1840 return V_008F14_IMG_DATA_FORMAT_2_10_10_10
;
1847 if (first_non_void
< 0 || first_non_void
> 3)
1850 /* uniform formats */
1851 switch (desc
->channel
[first_non_void
].size
) {
1853 switch (desc
->nr_channels
) {
1854 #if 0 /* Not supported for render targets */
1856 return V_008F14_IMG_DATA_FORMAT_4_4
;
1859 return V_008F14_IMG_DATA_FORMAT_4_4_4_4
;
1863 switch (desc
->nr_channels
) {
1865 return V_008F14_IMG_DATA_FORMAT_8
;
1867 return V_008F14_IMG_DATA_FORMAT_8_8
;
1869 return V_008F14_IMG_DATA_FORMAT_8_8_8_8
;
1873 switch (desc
->nr_channels
) {
1875 return V_008F14_IMG_DATA_FORMAT_16
;
1877 return V_008F14_IMG_DATA_FORMAT_16_16
;
1879 return V_008F14_IMG_DATA_FORMAT_16_16_16_16
;
1883 switch (desc
->nr_channels
) {
1885 return V_008F14_IMG_DATA_FORMAT_32
;
1887 return V_008F14_IMG_DATA_FORMAT_32_32
;
1888 #if 0 /* Not supported for render targets */
1890 return V_008F14_IMG_DATA_FORMAT_32_32_32
;
1893 return V_008F14_IMG_DATA_FORMAT_32_32_32_32
;
1901 static unsigned si_tex_wrap(unsigned wrap
)
1905 case PIPE_TEX_WRAP_REPEAT
:
1906 return V_008F30_SQ_TEX_WRAP
;
1907 case PIPE_TEX_WRAP_CLAMP
:
1908 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER
;
1909 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
1910 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL
;
1911 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
1912 return V_008F30_SQ_TEX_CLAMP_BORDER
;
1913 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
1914 return V_008F30_SQ_TEX_MIRROR
;
1915 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
1916 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
1917 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
1918 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
1919 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
1920 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER
;
1924 static unsigned si_tex_mipfilter(unsigned filter
)
1927 case PIPE_TEX_MIPFILTER_NEAREST
:
1928 return V_008F38_SQ_TEX_Z_FILTER_POINT
;
1929 case PIPE_TEX_MIPFILTER_LINEAR
:
1930 return V_008F38_SQ_TEX_Z_FILTER_LINEAR
;
1932 case PIPE_TEX_MIPFILTER_NONE
:
1933 return V_008F38_SQ_TEX_Z_FILTER_NONE
;
1937 static unsigned si_tex_compare(unsigned compare
)
1941 case PIPE_FUNC_NEVER
:
1942 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
1943 case PIPE_FUNC_LESS
:
1944 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS
;
1945 case PIPE_FUNC_EQUAL
:
1946 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL
;
1947 case PIPE_FUNC_LEQUAL
:
1948 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
1949 case PIPE_FUNC_GREATER
:
1950 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER
;
1951 case PIPE_FUNC_NOTEQUAL
:
1952 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
1953 case PIPE_FUNC_GEQUAL
:
1954 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
1955 case PIPE_FUNC_ALWAYS
:
1956 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
1960 static unsigned si_tex_dim(struct si_screen
*sscreen
, struct si_texture
*tex
,
1961 unsigned view_target
, unsigned nr_samples
)
1963 unsigned res_target
= tex
->buffer
.b
.b
.target
;
1965 if (view_target
== PIPE_TEXTURE_CUBE
||
1966 view_target
== PIPE_TEXTURE_CUBE_ARRAY
)
1967 res_target
= view_target
;
1968 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1969 else if (res_target
== PIPE_TEXTURE_CUBE
||
1970 res_target
== PIPE_TEXTURE_CUBE_ARRAY
)
1971 res_target
= PIPE_TEXTURE_2D_ARRAY
;
1973 /* GFX9 allocates 1D textures as 2D. */
1974 if ((res_target
== PIPE_TEXTURE_1D
||
1975 res_target
== PIPE_TEXTURE_1D_ARRAY
) &&
1976 sscreen
->info
.chip_class
>= GFX9
&&
1977 tex
->surface
.u
.gfx9
.resource_type
== RADEON_RESOURCE_2D
) {
1978 if (res_target
== PIPE_TEXTURE_1D
)
1979 res_target
= PIPE_TEXTURE_2D
;
1981 res_target
= PIPE_TEXTURE_2D_ARRAY
;
1984 switch (res_target
) {
1986 case PIPE_TEXTURE_1D
:
1987 return V_008F1C_SQ_RSRC_IMG_1D
;
1988 case PIPE_TEXTURE_1D_ARRAY
:
1989 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY
;
1990 case PIPE_TEXTURE_2D
:
1991 case PIPE_TEXTURE_RECT
:
1992 return nr_samples
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA
:
1993 V_008F1C_SQ_RSRC_IMG_2D
;
1994 case PIPE_TEXTURE_2D_ARRAY
:
1995 return nr_samples
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
:
1996 V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
1997 case PIPE_TEXTURE_3D
:
1998 return V_008F1C_SQ_RSRC_IMG_3D
;
1999 case PIPE_TEXTURE_CUBE
:
2000 case PIPE_TEXTURE_CUBE_ARRAY
:
2001 return V_008F1C_SQ_RSRC_IMG_CUBE
;
2006 * Format support testing
2009 static bool si_is_sampler_format_supported(struct pipe_screen
*screen
, enum pipe_format format
)
2011 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2013 if (sscreen
->info
.chip_class
>= GFX10
) {
2014 const struct gfx10_format
*fmt
= &gfx10_format_table
[format
];
2015 if (!fmt
->img_format
|| fmt
->buffers_only
)
2020 const struct util_format_description
*desc
= util_format_description(format
);
2024 return si_translate_texformat(screen
, format
, desc
,
2025 util_format_get_first_non_void_channel(format
)) != ~0U;
2028 static uint32_t si_translate_buffer_dataformat(struct pipe_screen
*screen
,
2029 const struct util_format_description
*desc
,
2034 assert(((struct si_screen
*)screen
)->info
.chip_class
<= GFX9
);
2036 if (desc
->format
== PIPE_FORMAT_R11G11B10_FLOAT
)
2037 return V_008F0C_BUF_DATA_FORMAT_10_11_11
;
2039 assert(first_non_void
>= 0);
2041 if (desc
->nr_channels
== 4 &&
2042 desc
->channel
[0].size
== 10 &&
2043 desc
->channel
[1].size
== 10 &&
2044 desc
->channel
[2].size
== 10 &&
2045 desc
->channel
[3].size
== 2)
2046 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10
;
2048 /* See whether the components are of the same size. */
2049 for (i
= 0; i
< desc
->nr_channels
; i
++) {
2050 if (desc
->channel
[first_non_void
].size
!= desc
->channel
[i
].size
)
2051 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
2054 switch (desc
->channel
[first_non_void
].size
) {
2056 switch (desc
->nr_channels
) {
2058 case 3: /* 3 loads */
2059 return V_008F0C_BUF_DATA_FORMAT_8
;
2061 return V_008F0C_BUF_DATA_FORMAT_8_8
;
2063 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8
;
2067 switch (desc
->nr_channels
) {
2069 case 3: /* 3 loads */
2070 return V_008F0C_BUF_DATA_FORMAT_16
;
2072 return V_008F0C_BUF_DATA_FORMAT_16_16
;
2074 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16
;
2078 switch (desc
->nr_channels
) {
2080 return V_008F0C_BUF_DATA_FORMAT_32
;
2082 return V_008F0C_BUF_DATA_FORMAT_32_32
;
2084 return V_008F0C_BUF_DATA_FORMAT_32_32_32
;
2086 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
2090 /* Legacy double formats. */
2091 switch (desc
->nr_channels
) {
2092 case 1: /* 1 load */
2093 return V_008F0C_BUF_DATA_FORMAT_32_32
;
2094 case 2: /* 1 load */
2095 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
2096 case 3: /* 3 loads */
2097 return V_008F0C_BUF_DATA_FORMAT_32_32
;
2098 case 4: /* 2 loads */
2099 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
2104 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
2107 static uint32_t si_translate_buffer_numformat(struct pipe_screen
*screen
,
2108 const struct util_format_description
*desc
,
2111 assert(((struct si_screen
*)screen
)->info
.chip_class
<= GFX9
);
2113 if (desc
->format
== PIPE_FORMAT_R11G11B10_FLOAT
)
2114 return V_008F0C_BUF_NUM_FORMAT_FLOAT
;
2116 assert(first_non_void
>= 0);
2118 switch (desc
->channel
[first_non_void
].type
) {
2119 case UTIL_FORMAT_TYPE_SIGNED
:
2120 case UTIL_FORMAT_TYPE_FIXED
:
2121 if (desc
->channel
[first_non_void
].size
>= 32 ||
2122 desc
->channel
[first_non_void
].pure_integer
)
2123 return V_008F0C_BUF_NUM_FORMAT_SINT
;
2124 else if (desc
->channel
[first_non_void
].normalized
)
2125 return V_008F0C_BUF_NUM_FORMAT_SNORM
;
2127 return V_008F0C_BUF_NUM_FORMAT_SSCALED
;
2129 case UTIL_FORMAT_TYPE_UNSIGNED
:
2130 if (desc
->channel
[first_non_void
].size
>= 32 ||
2131 desc
->channel
[first_non_void
].pure_integer
)
2132 return V_008F0C_BUF_NUM_FORMAT_UINT
;
2133 else if (desc
->channel
[first_non_void
].normalized
)
2134 return V_008F0C_BUF_NUM_FORMAT_UNORM
;
2136 return V_008F0C_BUF_NUM_FORMAT_USCALED
;
2138 case UTIL_FORMAT_TYPE_FLOAT
:
2140 return V_008F0C_BUF_NUM_FORMAT_FLOAT
;
2144 static unsigned si_is_vertex_format_supported(struct pipe_screen
*screen
,
2145 enum pipe_format format
,
2148 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2149 const struct util_format_description
*desc
;
2151 unsigned data_format
;
2153 assert((usage
& ~(PIPE_BIND_SHADER_IMAGE
|
2154 PIPE_BIND_SAMPLER_VIEW
|
2155 PIPE_BIND_VERTEX_BUFFER
)) == 0);
2157 desc
= util_format_description(format
);
2161 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
2162 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
2163 * for read-only access (with caveats surrounding bounds checks), but
2164 * obviously fails for write access which we have to implement for
2165 * shader images. Luckily, OpenGL doesn't expect this to be supported
2166 * anyway, and so the only impact is on PBO uploads / downloads, which
2167 * shouldn't be expected to be fast for GL_RGB anyway.
2169 if (desc
->block
.bits
== 3 * 8 ||
2170 desc
->block
.bits
== 3 * 16) {
2171 if (usage
& (PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SAMPLER_VIEW
)) {
2172 usage
&= ~(PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SAMPLER_VIEW
);
2178 if (sscreen
->info
.chip_class
>= GFX10
) {
2179 const struct gfx10_format
*fmt
= &gfx10_format_table
[format
];
2180 if (!fmt
->img_format
|| fmt
->img_format
>= 128)
2185 first_non_void
= util_format_get_first_non_void_channel(format
);
2186 data_format
= si_translate_buffer_dataformat(screen
, desc
, first_non_void
);
2187 if (data_format
== V_008F0C_BUF_DATA_FORMAT_INVALID
)
2193 static bool si_is_colorbuffer_format_supported(enum pipe_format format
)
2195 return si_translate_colorformat(format
) != V_028C70_COLOR_INVALID
&&
2196 si_translate_colorswap(format
, false) != ~0U;
2199 static bool si_is_zs_format_supported(enum pipe_format format
)
2201 return si_translate_dbformat(format
) != V_028040_Z_INVALID
;
2204 static boolean
si_is_format_supported(struct pipe_screen
*screen
,
2205 enum pipe_format format
,
2206 enum pipe_texture_target target
,
2207 unsigned sample_count
,
2208 unsigned storage_sample_count
,
2211 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2212 unsigned retval
= 0;
2214 if (target
>= PIPE_MAX_TEXTURE_TYPES
) {
2215 PRINT_ERR("radeonsi: unsupported texture type %d\n", target
);
2219 if (MAX2(1, sample_count
) < MAX2(1, storage_sample_count
))
2222 if (sample_count
> 1) {
2223 if (!screen
->get_param(screen
, PIPE_CAP_TEXTURE_MULTISAMPLE
))
2226 if (usage
& PIPE_BIND_SHADER_IMAGE
)
2229 /* Only power-of-two sample counts are supported. */
2230 if (!util_is_power_of_two_or_zero(sample_count
) ||
2231 !util_is_power_of_two_or_zero(storage_sample_count
))
2234 /* MSAA support without framebuffer attachments. */
2235 if (format
== PIPE_FORMAT_NONE
&& sample_count
<= 16)
2238 if (!sscreen
->info
.has_eqaa_surface_allocator
||
2239 util_format_is_depth_or_stencil(format
)) {
2240 /* Color without EQAA or depth/stencil. */
2241 if (sample_count
> 8 ||
2242 sample_count
!= storage_sample_count
)
2245 /* Color with EQAA. */
2246 if (sample_count
> 16 ||
2247 storage_sample_count
> 8)
2252 if (usage
& (PIPE_BIND_SAMPLER_VIEW
|
2253 PIPE_BIND_SHADER_IMAGE
)) {
2254 if (target
== PIPE_BUFFER
) {
2255 retval
|= si_is_vertex_format_supported(
2256 screen
, format
, usage
& (PIPE_BIND_SAMPLER_VIEW
|
2257 PIPE_BIND_SHADER_IMAGE
));
2259 if (si_is_sampler_format_supported(screen
, format
))
2260 retval
|= usage
& (PIPE_BIND_SAMPLER_VIEW
|
2261 PIPE_BIND_SHADER_IMAGE
);
2265 if ((usage
& (PIPE_BIND_RENDER_TARGET
|
2266 PIPE_BIND_DISPLAY_TARGET
|
2269 PIPE_BIND_BLENDABLE
)) &&
2270 si_is_colorbuffer_format_supported(format
)) {
2272 (PIPE_BIND_RENDER_TARGET
|
2273 PIPE_BIND_DISPLAY_TARGET
|
2276 if (!util_format_is_pure_integer(format
) &&
2277 !util_format_is_depth_or_stencil(format
))
2278 retval
|= usage
& PIPE_BIND_BLENDABLE
;
2281 if ((usage
& PIPE_BIND_DEPTH_STENCIL
) &&
2282 si_is_zs_format_supported(format
)) {
2283 retval
|= PIPE_BIND_DEPTH_STENCIL
;
2286 if (usage
& PIPE_BIND_VERTEX_BUFFER
) {
2287 retval
|= si_is_vertex_format_supported(screen
, format
,
2288 PIPE_BIND_VERTEX_BUFFER
);
2291 if ((usage
& PIPE_BIND_LINEAR
) &&
2292 !util_format_is_compressed(format
) &&
2293 !(usage
& PIPE_BIND_DEPTH_STENCIL
))
2294 retval
|= PIPE_BIND_LINEAR
;
2296 return retval
== usage
;
2300 * framebuffer handling
2303 static void si_choose_spi_color_formats(struct si_surface
*surf
,
2304 unsigned format
, unsigned swap
,
2305 unsigned ntype
, bool is_depth
)
2307 /* Alpha is needed for alpha-to-coverage.
2308 * Blending may be with or without alpha.
2310 unsigned normal
= 0; /* most optimal, may not support blending or export alpha */
2311 unsigned alpha
= 0; /* exports alpha, but may not support blending */
2312 unsigned blend
= 0; /* supports blending, but may not export alpha */
2313 unsigned blend_alpha
= 0; /* least optimal, supports blending and exports alpha */
2315 /* Choose the SPI color formats. These are required values for RB+.
2316 * Other chips have multiple choices, though they are not necessarily better.
2319 case V_028C70_COLOR_5_6_5
:
2320 case V_028C70_COLOR_1_5_5_5
:
2321 case V_028C70_COLOR_5_5_5_1
:
2322 case V_028C70_COLOR_4_4_4_4
:
2323 case V_028C70_COLOR_10_11_11
:
2324 case V_028C70_COLOR_11_11_10
:
2325 case V_028C70_COLOR_8
:
2326 case V_028C70_COLOR_8_8
:
2327 case V_028C70_COLOR_8_8_8_8
:
2328 case V_028C70_COLOR_10_10_10_2
:
2329 case V_028C70_COLOR_2_10_10_10
:
2330 if (ntype
== V_028C70_NUMBER_UINT
)
2331 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
2332 else if (ntype
== V_028C70_NUMBER_SINT
)
2333 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
2335 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
2338 case V_028C70_COLOR_16
:
2339 case V_028C70_COLOR_16_16
:
2340 case V_028C70_COLOR_16_16_16_16
:
2341 if (ntype
== V_028C70_NUMBER_UNORM
||
2342 ntype
== V_028C70_NUMBER_SNORM
) {
2343 /* UNORM16 and SNORM16 don't support blending */
2344 if (ntype
== V_028C70_NUMBER_UNORM
)
2345 normal
= alpha
= V_028714_SPI_SHADER_UNORM16_ABGR
;
2347 normal
= alpha
= V_028714_SPI_SHADER_SNORM16_ABGR
;
2349 /* Use 32 bits per channel for blending. */
2350 if (format
== V_028C70_COLOR_16
) {
2351 if (swap
== V_028C70_SWAP_STD
) { /* R */
2352 blend
= V_028714_SPI_SHADER_32_R
;
2353 blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2354 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
2355 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2358 } else if (format
== V_028C70_COLOR_16_16
) {
2359 if (swap
== V_028C70_SWAP_STD
) { /* RG */
2360 blend
= V_028714_SPI_SHADER_32_GR
;
2361 blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2362 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
2363 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2366 } else /* 16_16_16_16 */
2367 blend
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2368 } else if (ntype
== V_028C70_NUMBER_UINT
)
2369 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
2370 else if (ntype
== V_028C70_NUMBER_SINT
)
2371 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
2372 else if (ntype
== V_028C70_NUMBER_FLOAT
)
2373 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
2378 case V_028C70_COLOR_32
:
2379 if (swap
== V_028C70_SWAP_STD
) { /* R */
2380 blend
= normal
= V_028714_SPI_SHADER_32_R
;
2381 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2382 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
2383 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
2388 case V_028C70_COLOR_32_32
:
2389 if (swap
== V_028C70_SWAP_STD
) { /* RG */
2390 blend
= normal
= V_028714_SPI_SHADER_32_GR
;
2391 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2392 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
2393 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
2398 case V_028C70_COLOR_32_32_32_32
:
2399 case V_028C70_COLOR_8_24
:
2400 case V_028C70_COLOR_24_8
:
2401 case V_028C70_COLOR_X24_8_32_FLOAT
:
2402 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
2410 /* The DB->CB copy needs 32_ABGR. */
2412 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
2414 surf
->spi_shader_col_format
= normal
;
2415 surf
->spi_shader_col_format_alpha
= alpha
;
2416 surf
->spi_shader_col_format_blend
= blend
;
2417 surf
->spi_shader_col_format_blend_alpha
= blend_alpha
;
2420 static void si_initialize_color_surface(struct si_context
*sctx
,
2421 struct si_surface
*surf
)
2423 struct si_texture
*tex
= (struct si_texture
*)surf
->base
.texture
;
2424 unsigned color_info
, color_attrib
;
2425 unsigned format
, swap
, ntype
, endian
;
2426 const struct util_format_description
*desc
;
2428 unsigned blend_clamp
= 0, blend_bypass
= 0;
2430 desc
= util_format_description(surf
->base
.format
);
2431 for (firstchan
= 0; firstchan
< 4; firstchan
++) {
2432 if (desc
->channel
[firstchan
].type
!= UTIL_FORMAT_TYPE_VOID
) {
2436 if (firstchan
== 4 || desc
->channel
[firstchan
].type
== UTIL_FORMAT_TYPE_FLOAT
) {
2437 ntype
= V_028C70_NUMBER_FLOAT
;
2439 ntype
= V_028C70_NUMBER_UNORM
;
2440 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
2441 ntype
= V_028C70_NUMBER_SRGB
;
2442 else if (desc
->channel
[firstchan
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2443 if (desc
->channel
[firstchan
].pure_integer
) {
2444 ntype
= V_028C70_NUMBER_SINT
;
2446 assert(desc
->channel
[firstchan
].normalized
);
2447 ntype
= V_028C70_NUMBER_SNORM
;
2449 } else if (desc
->channel
[firstchan
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
2450 if (desc
->channel
[firstchan
].pure_integer
) {
2451 ntype
= V_028C70_NUMBER_UINT
;
2453 assert(desc
->channel
[firstchan
].normalized
);
2454 ntype
= V_028C70_NUMBER_UNORM
;
2459 format
= si_translate_colorformat(surf
->base
.format
);
2460 if (format
== V_028C70_COLOR_INVALID
) {
2461 PRINT_ERR("Invalid CB format: %d, disabling CB.\n", surf
->base
.format
);
2463 assert(format
!= V_028C70_COLOR_INVALID
);
2464 swap
= si_translate_colorswap(surf
->base
.format
, false);
2465 endian
= si_colorformat_endian_swap(format
);
2467 /* blend clamp should be set for all NORM/SRGB types */
2468 if (ntype
== V_028C70_NUMBER_UNORM
||
2469 ntype
== V_028C70_NUMBER_SNORM
||
2470 ntype
== V_028C70_NUMBER_SRGB
)
2473 /* set blend bypass according to docs if SINT/UINT or
2474 8/24 COLOR variants */
2475 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
2476 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
2477 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
2482 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
) {
2483 if (format
== V_028C70_COLOR_8
||
2484 format
== V_028C70_COLOR_8_8
||
2485 format
== V_028C70_COLOR_8_8_8_8
)
2486 surf
->color_is_int8
= true;
2487 else if (format
== V_028C70_COLOR_10_10_10_2
||
2488 format
== V_028C70_COLOR_2_10_10_10
)
2489 surf
->color_is_int10
= true;
2492 color_info
= S_028C70_FORMAT(format
) |
2493 S_028C70_COMP_SWAP(swap
) |
2494 S_028C70_BLEND_CLAMP(blend_clamp
) |
2495 S_028C70_BLEND_BYPASS(blend_bypass
) |
2496 S_028C70_SIMPLE_FLOAT(1) |
2497 S_028C70_ROUND_MODE(ntype
!= V_028C70_NUMBER_UNORM
&&
2498 ntype
!= V_028C70_NUMBER_SNORM
&&
2499 ntype
!= V_028C70_NUMBER_SRGB
&&
2500 format
!= V_028C70_COLOR_8_24
&&
2501 format
!= V_028C70_COLOR_24_8
) |
2502 S_028C70_NUMBER_TYPE(ntype
) |
2503 S_028C70_ENDIAN(endian
);
2505 /* Intensity is implemented as Red, so treat it that way. */
2506 color_attrib
= S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] == PIPE_SWIZZLE_1
||
2507 util_format_is_intensity(surf
->base
.format
));
2509 if (tex
->buffer
.b
.b
.nr_samples
> 1) {
2510 unsigned log_samples
= util_logbase2(tex
->buffer
.b
.b
.nr_samples
);
2511 unsigned log_fragments
= util_logbase2(tex
->buffer
.b
.b
.nr_storage_samples
);
2513 color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
2514 S_028C74_NUM_FRAGMENTS(log_fragments
);
2516 if (tex
->fmask_offset
) {
2517 color_info
|= S_028C70_COMPRESSION(1);
2518 unsigned fmask_bankh
= util_logbase2(tex
->surface
.u
.legacy
.fmask
.bankh
);
2520 if (sctx
->chip_class
== GFX6
) {
2521 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on GFX6 too */
2522 color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh
);
2527 if (sctx
->chip_class
>= GFX10
) {
2528 unsigned min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_32B
;
2530 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2531 64 for APU because all of our APUs to date use DIMMs which have
2532 a request granularity size of 64B while all other chips have a
2534 if (!sctx
->screen
->info
.has_dedicated_vram
)
2535 min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_64B
;
2537 surf
->cb_dcc_control
=
2538 S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_256B
) |
2539 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_128B
) |
2540 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size
) |
2541 S_028C78_INDEPENDENT_64B_BLOCKS(0) |
2542 S_028C78_INDEPENDENT_128B_BLOCKS(1);
2543 } else if (sctx
->chip_class
>= GFX8
) {
2544 unsigned max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_256B
;
2545 unsigned min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_32B
;
2547 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2548 64 for APU because all of our APUs to date use DIMMs which have
2549 a request granularity size of 64B while all other chips have a
2551 if (!sctx
->screen
->info
.has_dedicated_vram
)
2552 min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_64B
;
2554 if (tex
->buffer
.b
.b
.nr_storage_samples
> 1) {
2555 if (tex
->surface
.bpe
== 1)
2556 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_64B
;
2557 else if (tex
->surface
.bpe
== 2)
2558 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_128B
;
2561 surf
->cb_dcc_control
= S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size
) |
2562 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size
) |
2563 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2566 /* This must be set for fast clear to work without FMASK. */
2567 if (!tex
->surface
.fmask_size
&& sctx
->chip_class
== GFX6
) {
2568 unsigned bankh
= util_logbase2(tex
->surface
.u
.legacy
.bankh
);
2569 color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(bankh
);
2572 /* GFX10 field has the same base shift as the GFX6 field */
2573 unsigned color_view
= S_028C6C_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
2574 S_028C6C_SLICE_MAX_GFX10(surf
->base
.u
.tex
.last_layer
);
2575 unsigned mip0_depth
= util_max_layer(&tex
->buffer
.b
.b
, 0);
2577 if (sctx
->chip_class
>= GFX10
) {
2578 color_view
|= S_028C6C_MIP_LEVEL_GFX10(surf
->base
.u
.tex
.level
);
2580 surf
->cb_color_attrib3
= S_028EE0_MIP0_DEPTH(mip0_depth
) |
2581 S_028EE0_RESOURCE_TYPE(tex
->surface
.u
.gfx9
.resource_type
) |
2582 S_028EE0_RESOURCE_LEVEL(1);
2583 } else if (sctx
->chip_class
>= GFX9
) {
2584 color_view
|= S_028C6C_MIP_LEVEL_GFX9(surf
->base
.u
.tex
.level
);
2585 color_attrib
|= S_028C74_MIP0_DEPTH(mip0_depth
) |
2586 S_028C74_RESOURCE_TYPE(tex
->surface
.u
.gfx9
.resource_type
);
2589 if (sctx
->chip_class
>= GFX9
) {
2590 surf
->cb_color_attrib2
= S_028C68_MIP0_WIDTH(surf
->width0
- 1) |
2591 S_028C68_MIP0_HEIGHT(surf
->height0
- 1) |
2592 S_028C68_MAX_MIP(tex
->buffer
.b
.b
.last_level
);
2595 surf
->cb_color_view
= color_view
;
2596 surf
->cb_color_info
= color_info
;
2597 surf
->cb_color_attrib
= color_attrib
;
2599 /* Determine pixel shader export format */
2600 si_choose_spi_color_formats(surf
, format
, swap
, ntype
, tex
->is_depth
);
2602 surf
->color_initialized
= true;
2605 static void si_init_depth_surface(struct si_context
*sctx
,
2606 struct si_surface
*surf
)
2608 struct si_texture
*tex
= (struct si_texture
*)surf
->base
.texture
;
2609 unsigned level
= surf
->base
.u
.tex
.level
;
2610 unsigned format
, stencil_format
;
2611 uint32_t z_info
, s_info
;
2613 format
= si_translate_dbformat(tex
->db_render_format
);
2614 stencil_format
= tex
->surface
.has_stencil
?
2615 V_028044_STENCIL_8
: V_028044_STENCIL_INVALID
;
2617 assert(format
!= V_028040_Z_INVALID
);
2618 if (format
== V_028040_Z_INVALID
)
2619 PRINT_ERR("Invalid DB format: %d, disabling DB.\n", tex
->buffer
.b
.b
.format
);
2621 surf
->db_depth_view
= S_028008_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
2622 S_028008_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
2623 surf
->db_htile_data_base
= 0;
2624 surf
->db_htile_surface
= 0;
2626 if (sctx
->chip_class
>= GFX10
) {
2627 surf
->db_depth_view
|= S_028008_SLICE_START_HI(surf
->base
.u
.tex
.first_layer
>> 11) |
2628 S_028008_SLICE_MAX_HI(surf
->base
.u
.tex
.last_layer
>> 11);
2631 if (sctx
->chip_class
>= GFX9
) {
2632 assert(tex
->surface
.u
.gfx9
.surf_offset
== 0);
2633 surf
->db_depth_base
= tex
->buffer
.gpu_address
>> 8;
2634 surf
->db_stencil_base
= (tex
->buffer
.gpu_address
+
2635 tex
->surface
.u
.gfx9
.stencil_offset
) >> 8;
2636 z_info
= S_028038_FORMAT(format
) |
2637 S_028038_NUM_SAMPLES(util_logbase2(tex
->buffer
.b
.b
.nr_samples
)) |
2638 S_028038_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
2639 S_028038_MAXMIP(tex
->buffer
.b
.b
.last_level
);
2640 s_info
= S_02803C_FORMAT(stencil_format
) |
2641 S_02803C_SW_MODE(tex
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
2643 if (sctx
->chip_class
== GFX9
) {
2644 surf
->db_z_info2
= S_028068_EPITCH(tex
->surface
.u
.gfx9
.surf
.epitch
);
2645 surf
->db_stencil_info2
= S_02806C_EPITCH(tex
->surface
.u
.gfx9
.stencil
.epitch
);
2647 surf
->db_depth_view
|= S_028008_MIPID(level
);
2648 surf
->db_depth_size
= S_02801C_X_MAX(tex
->buffer
.b
.b
.width0
- 1) |
2649 S_02801C_Y_MAX(tex
->buffer
.b
.b
.height0
- 1);
2651 if (si_htile_enabled(tex
, level
)) {
2652 z_info
|= S_028038_TILE_SURFACE_ENABLE(1) |
2653 S_028038_ALLOW_EXPCLEAR(1);
2655 if (tex
->tc_compatible_htile
) {
2656 unsigned max_zplanes
= 4;
2658 if (tex
->db_render_format
== PIPE_FORMAT_Z16_UNORM
&&
2659 tex
->buffer
.b
.b
.nr_samples
> 1)
2662 z_info
|= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes
+ 1);
2664 if (sctx
->chip_class
>= GFX10
) {
2665 z_info
|= S_028040_ITERATE_FLUSH(1);
2666 s_info
|= S_028044_ITERATE_FLUSH(1);
2668 z_info
|= S_028038_ITERATE_FLUSH(1);
2669 s_info
|= S_02803C_ITERATE_FLUSH(1);
2673 if (tex
->surface
.has_stencil
) {
2674 /* Stencil buffer workaround ported from the GFX6-GFX8 code.
2675 * See that for explanation.
2677 s_info
|= S_02803C_ALLOW_EXPCLEAR(tex
->buffer
.b
.b
.nr_samples
<= 1);
2679 /* Use all HTILE for depth if there's no stencil. */
2680 s_info
|= S_02803C_TILE_STENCIL_DISABLE(1);
2683 surf
->db_htile_data_base
= (tex
->buffer
.gpu_address
+
2684 tex
->htile_offset
) >> 8;
2685 surf
->db_htile_surface
= S_028ABC_FULL_CACHE(1) |
2686 S_028ABC_PIPE_ALIGNED(tex
->surface
.u
.gfx9
.htile
.pipe_aligned
);
2687 if (sctx
->chip_class
== GFX9
) {
2688 surf
->db_htile_surface
|=
2689 S_028ABC_RB_ALIGNED(tex
->surface
.u
.gfx9
.htile
.rb_aligned
);
2694 struct legacy_surf_level
*levelinfo
= &tex
->surface
.u
.legacy
.level
[level
];
2696 assert(levelinfo
->nblk_x
% 8 == 0 && levelinfo
->nblk_y
% 8 == 0);
2698 surf
->db_depth_base
= (tex
->buffer
.gpu_address
+
2699 tex
->surface
.u
.legacy
.level
[level
].offset
) >> 8;
2700 surf
->db_stencil_base
= (tex
->buffer
.gpu_address
+
2701 tex
->surface
.u
.legacy
.stencil_level
[level
].offset
) >> 8;
2703 z_info
= S_028040_FORMAT(format
) |
2704 S_028040_NUM_SAMPLES(util_logbase2(tex
->buffer
.b
.b
.nr_samples
));
2705 s_info
= S_028044_FORMAT(stencil_format
);
2706 surf
->db_depth_info
= S_02803C_ADDR5_SWIZZLE_MASK(!tex
->tc_compatible_htile
);
2708 if (sctx
->chip_class
>= GFX7
) {
2709 struct radeon_info
*info
= &sctx
->screen
->info
;
2710 unsigned index
= tex
->surface
.u
.legacy
.tiling_index
[level
];
2711 unsigned stencil_index
= tex
->surface
.u
.legacy
.stencil_tiling_index
[level
];
2712 unsigned macro_index
= tex
->surface
.u
.legacy
.macro_tile_index
;
2713 unsigned tile_mode
= info
->si_tile_mode_array
[index
];
2714 unsigned stencil_tile_mode
= info
->si_tile_mode_array
[stencil_index
];
2715 unsigned macro_mode
= info
->cik_macrotile_mode_array
[macro_index
];
2717 surf
->db_depth_info
|=
2718 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode
)) |
2719 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode
)) |
2720 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode
)) |
2721 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode
)) |
2722 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode
)) |
2723 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode
));
2724 z_info
|= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode
));
2725 s_info
|= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode
));
2727 unsigned tile_mode_index
= si_tile_mode_index(tex
, level
, false);
2728 z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
2729 tile_mode_index
= si_tile_mode_index(tex
, level
, true);
2730 s_info
|= S_028044_TILE_MODE_INDEX(tile_mode_index
);
2733 surf
->db_depth_size
= S_028058_PITCH_TILE_MAX((levelinfo
->nblk_x
/ 8) - 1) |
2734 S_028058_HEIGHT_TILE_MAX((levelinfo
->nblk_y
/ 8) - 1);
2735 surf
->db_depth_slice
= S_02805C_SLICE_TILE_MAX((levelinfo
->nblk_x
*
2736 levelinfo
->nblk_y
) / 64 - 1);
2738 if (si_htile_enabled(tex
, level
)) {
2739 z_info
|= S_028040_TILE_SURFACE_ENABLE(1) |
2740 S_028040_ALLOW_EXPCLEAR(1);
2742 if (tex
->surface
.has_stencil
) {
2743 /* Workaround: For a not yet understood reason, the
2744 * combination of MSAA, fast stencil clear and stencil
2745 * decompress messes with subsequent stencil buffer
2746 * uses. Problem was reproduced on Verde, Bonaire,
2747 * Tonga, and Carrizo.
2749 * Disabling EXPCLEAR works around the problem.
2751 * Check piglit's arb_texture_multisample-stencil-clear
2752 * test if you want to try changing this.
2754 if (tex
->buffer
.b
.b
.nr_samples
<= 1)
2755 s_info
|= S_028044_ALLOW_EXPCLEAR(1);
2756 } else if (!tex
->tc_compatible_htile
) {
2757 /* Use all of the htile_buffer for depth if there's no stencil.
2758 * This must not be set when TC-compatible HTILE is enabled
2761 s_info
|= S_028044_TILE_STENCIL_DISABLE(1);
2764 surf
->db_htile_data_base
= (tex
->buffer
.gpu_address
+
2765 tex
->htile_offset
) >> 8;
2766 surf
->db_htile_surface
= S_028ABC_FULL_CACHE(1);
2768 if (tex
->tc_compatible_htile
) {
2769 surf
->db_htile_surface
|= S_028ABC_TC_COMPATIBLE(1);
2771 /* 0 = full compression. N = only compress up to N-1 Z planes. */
2772 if (tex
->buffer
.b
.b
.nr_samples
<= 1)
2773 z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2774 else if (tex
->buffer
.b
.b
.nr_samples
<= 4)
2775 z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2777 z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2782 surf
->db_z_info
= z_info
;
2783 surf
->db_stencil_info
= s_info
;
2785 surf
->depth_initialized
= true;
2788 void si_update_fb_dirtiness_after_rendering(struct si_context
*sctx
)
2790 if (sctx
->decompression_enabled
)
2793 if (sctx
->framebuffer
.state
.zsbuf
) {
2794 struct pipe_surface
*surf
= sctx
->framebuffer
.state
.zsbuf
;
2795 struct si_texture
*tex
= (struct si_texture
*)surf
->texture
;
2797 tex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2799 if (tex
->surface
.has_stencil
)
2800 tex
->stencil_dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2803 unsigned compressed_cb_mask
= sctx
->framebuffer
.compressed_cb_mask
;
2804 while (compressed_cb_mask
) {
2805 unsigned i
= u_bit_scan(&compressed_cb_mask
);
2806 struct pipe_surface
*surf
= sctx
->framebuffer
.state
.cbufs
[i
];
2807 struct si_texture
*tex
= (struct si_texture
*)surf
->texture
;
2809 if (tex
->fmask_offset
)
2810 tex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2811 if (tex
->dcc_gather_statistics
)
2812 tex
->separate_dcc_dirty
= true;
2816 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state
*state
)
2818 for (int i
= 0; i
< state
->nr_cbufs
; ++i
) {
2819 struct si_surface
*surf
= NULL
;
2820 struct si_texture
*tex
;
2822 if (!state
->cbufs
[i
])
2824 surf
= (struct si_surface
*)state
->cbufs
[i
];
2825 tex
= (struct si_texture
*)surf
->base
.texture
;
2827 p_atomic_dec(&tex
->framebuffers_bound
);
2831 static void si_set_framebuffer_state(struct pipe_context
*ctx
,
2832 const struct pipe_framebuffer_state
*state
)
2834 struct si_context
*sctx
= (struct si_context
*)ctx
;
2835 struct si_surface
*surf
= NULL
;
2836 struct si_texture
*tex
;
2837 bool old_any_dst_linear
= sctx
->framebuffer
.any_dst_linear
;
2838 unsigned old_nr_samples
= sctx
->framebuffer
.nr_samples
;
2839 unsigned old_colorbuf_enabled_4bit
= sctx
->framebuffer
.colorbuf_enabled_4bit
;
2840 bool old_has_zsbuf
= !!sctx
->framebuffer
.state
.zsbuf
;
2841 bool old_has_stencil
=
2843 ((struct si_texture
*)sctx
->framebuffer
.state
.zsbuf
->texture
)->surface
.has_stencil
;
2844 bool unbound
= false;
2847 /* Reject zero-sized framebuffers due to a hw bug on GFX6 that occurs
2848 * when PA_SU_HARDWARE_SCREEN_OFFSET != 0 and any_scissor.BR_X/Y <= 0.
2849 * We could implement the full workaround here, but it's a useless case.
2851 if ((!state
->width
|| !state
->height
) && (state
->nr_cbufs
|| state
->zsbuf
)) {
2852 unreachable("the framebuffer shouldn't have zero area");
2856 si_update_fb_dirtiness_after_rendering(sctx
);
2858 for (i
= 0; i
< sctx
->framebuffer
.state
.nr_cbufs
; i
++) {
2859 if (!sctx
->framebuffer
.state
.cbufs
[i
])
2862 tex
= (struct si_texture
*)sctx
->framebuffer
.state
.cbufs
[i
]->texture
;
2863 if (tex
->dcc_gather_statistics
)
2864 vi_separate_dcc_stop_query(sctx
, tex
);
2867 /* Disable DCC if the formats are incompatible. */
2868 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
2869 if (!state
->cbufs
[i
])
2872 surf
= (struct si_surface
*)state
->cbufs
[i
];
2873 tex
= (struct si_texture
*)surf
->base
.texture
;
2875 if (!surf
->dcc_incompatible
)
2878 /* Since the DCC decompression calls back into set_framebuffer-
2879 * _state, we need to unbind the framebuffer, so that
2880 * vi_separate_dcc_stop_query isn't called twice with the same
2884 util_copy_framebuffer_state(&sctx
->framebuffer
.state
, NULL
);
2888 if (vi_dcc_enabled(tex
, surf
->base
.u
.tex
.level
))
2889 if (!si_texture_disable_dcc(sctx
, tex
))
2890 si_decompress_dcc(sctx
, tex
);
2892 surf
->dcc_incompatible
= false;
2895 /* Only flush TC when changing the framebuffer state, because
2896 * the only client not using TC that can change textures is
2899 * Wait for compute shaders because of possible transitions:
2900 * - FB write -> shader read
2901 * - shader write -> FB read
2903 * DB caches are flushed on demand (using si_decompress_textures).
2905 * When MSAA is enabled, CB and TC caches are flushed on demand
2906 * (after FMASK decompression). Shader write -> FB read transitions
2907 * cannot happen for MSAA textures, because MSAA shader images are
2910 * Only flush and wait for CB if there is actually a bound color buffer.
2912 if (sctx
->framebuffer
.uncompressed_cb_mask
) {
2913 si_make_CB_shader_coherent(sctx
, sctx
->framebuffer
.nr_samples
,
2914 sctx
->framebuffer
.CB_has_shader_readable_metadata
,
2915 sctx
->framebuffer
.all_DCC_pipe_aligned
);
2918 sctx
->flags
|= SI_CONTEXT_CS_PARTIAL_FLUSH
;
2920 /* u_blitter doesn't invoke depth decompression when it does multiple
2921 * blits in a row, but the only case when it matters for DB is when
2922 * doing generate_mipmap. So here we flush DB manually between
2923 * individual generate_mipmap blits.
2924 * Note that lower mipmap levels aren't compressed.
2926 if (sctx
->generate_mipmap_for_depth
) {
2927 si_make_DB_shader_coherent(sctx
, 1, false,
2928 sctx
->framebuffer
.DB_has_shader_readable_metadata
);
2929 } else if (sctx
->chip_class
== GFX9
) {
2930 /* It appears that DB metadata "leaks" in a sequence of:
2932 * - DCC decompress for shader image writes (with DB disabled)
2933 * - render with DEPTH_BEFORE_SHADER=1
2934 * Flushing DB metadata works around the problem.
2936 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_DB_META
;
2939 /* Take the maximum of the old and new count. If the new count is lower,
2940 * dirtying is needed to disable the unbound colorbuffers.
2942 sctx
->framebuffer
.dirty_cbufs
|=
2943 (1 << MAX2(sctx
->framebuffer
.state
.nr_cbufs
, state
->nr_cbufs
)) - 1;
2944 sctx
->framebuffer
.dirty_zsbuf
|= sctx
->framebuffer
.state
.zsbuf
!= state
->zsbuf
;
2946 si_dec_framebuffer_counters(&sctx
->framebuffer
.state
);
2947 util_copy_framebuffer_state(&sctx
->framebuffer
.state
, state
);
2949 sctx
->framebuffer
.colorbuf_enabled_4bit
= 0;
2950 sctx
->framebuffer
.spi_shader_col_format
= 0;
2951 sctx
->framebuffer
.spi_shader_col_format_alpha
= 0;
2952 sctx
->framebuffer
.spi_shader_col_format_blend
= 0;
2953 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
= 0;
2954 sctx
->framebuffer
.color_is_int8
= 0;
2955 sctx
->framebuffer
.color_is_int10
= 0;
2957 sctx
->framebuffer
.compressed_cb_mask
= 0;
2958 sctx
->framebuffer
.uncompressed_cb_mask
= 0;
2959 sctx
->framebuffer
.nr_samples
= util_framebuffer_get_num_samples(state
);
2960 sctx
->framebuffer
.nr_color_samples
= sctx
->framebuffer
.nr_samples
;
2961 sctx
->framebuffer
.log_samples
= util_logbase2(sctx
->framebuffer
.nr_samples
);
2962 sctx
->framebuffer
.any_dst_linear
= false;
2963 sctx
->framebuffer
.CB_has_shader_readable_metadata
= false;
2964 sctx
->framebuffer
.DB_has_shader_readable_metadata
= false;
2965 sctx
->framebuffer
.all_DCC_pipe_aligned
= true;
2966 unsigned num_bpp64_colorbufs
= 0;
2968 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
2969 if (!state
->cbufs
[i
])
2972 surf
= (struct si_surface
*)state
->cbufs
[i
];
2973 tex
= (struct si_texture
*)surf
->base
.texture
;
2975 if (!surf
->color_initialized
) {
2976 si_initialize_color_surface(sctx
, surf
);
2979 sctx
->framebuffer
.colorbuf_enabled_4bit
|= 0xf << (i
* 4);
2980 sctx
->framebuffer
.spi_shader_col_format
|=
2981 surf
->spi_shader_col_format
<< (i
* 4);
2982 sctx
->framebuffer
.spi_shader_col_format_alpha
|=
2983 surf
->spi_shader_col_format_alpha
<< (i
* 4);
2984 sctx
->framebuffer
.spi_shader_col_format_blend
|=
2985 surf
->spi_shader_col_format_blend
<< (i
* 4);
2986 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
|=
2987 surf
->spi_shader_col_format_blend_alpha
<< (i
* 4);
2989 if (surf
->color_is_int8
)
2990 sctx
->framebuffer
.color_is_int8
|= 1 << i
;
2991 if (surf
->color_is_int10
)
2992 sctx
->framebuffer
.color_is_int10
|= 1 << i
;
2994 if (tex
->fmask_offset
)
2995 sctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
2997 sctx
->framebuffer
.uncompressed_cb_mask
|= 1 << i
;
2999 /* Don't update nr_color_samples for non-AA buffers.
3000 * (e.g. destination of MSAA resolve)
3002 if (tex
->buffer
.b
.b
.nr_samples
>= 2 &&
3003 tex
->buffer
.b
.b
.nr_storage_samples
< tex
->buffer
.b
.b
.nr_samples
) {
3004 sctx
->framebuffer
.nr_color_samples
=
3005 MIN2(sctx
->framebuffer
.nr_color_samples
,
3006 tex
->buffer
.b
.b
.nr_storage_samples
);
3007 sctx
->framebuffer
.nr_color_samples
=
3008 MAX2(1, sctx
->framebuffer
.nr_color_samples
);
3011 if (tex
->surface
.is_linear
)
3012 sctx
->framebuffer
.any_dst_linear
= true;
3013 if (tex
->surface
.bpe
>= 8)
3014 num_bpp64_colorbufs
++;
3016 if (vi_dcc_enabled(tex
, surf
->base
.u
.tex
.level
)) {
3017 sctx
->framebuffer
.CB_has_shader_readable_metadata
= true;
3019 if (sctx
->chip_class
>= GFX9
&&
3020 !tex
->surface
.u
.gfx9
.dcc
.pipe_aligned
)
3021 sctx
->framebuffer
.all_DCC_pipe_aligned
= false;
3024 si_context_add_resource_size(sctx
, surf
->base
.texture
);
3026 p_atomic_inc(&tex
->framebuffers_bound
);
3028 if (tex
->dcc_gather_statistics
) {
3029 /* Dirty tracking must be enabled for DCC usage analysis. */
3030 sctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
3031 vi_separate_dcc_start_query(sctx
, tex
);
3035 /* For optimal DCC performance. */
3036 if (sctx
->chip_class
== GFX8
)
3037 sctx
->framebuffer
.dcc_overwrite_combiner_watermark
= 4;
3038 else if (num_bpp64_colorbufs
>= 5)
3039 sctx
->framebuffer
.dcc_overwrite_combiner_watermark
= 8;
3041 sctx
->framebuffer
.dcc_overwrite_combiner_watermark
= 6;
3043 struct si_texture
*zstex
= NULL
;
3046 surf
= (struct si_surface
*)state
->zsbuf
;
3047 zstex
= (struct si_texture
*)surf
->base
.texture
;
3049 if (!surf
->depth_initialized
) {
3050 si_init_depth_surface(sctx
, surf
);
3053 if (vi_tc_compat_htile_enabled(zstex
, surf
->base
.u
.tex
.level
))
3054 sctx
->framebuffer
.DB_has_shader_readable_metadata
= true;
3056 si_context_add_resource_size(sctx
, surf
->base
.texture
);
3059 si_update_ps_colorbuf0_slot(sctx
);
3060 si_update_poly_offset_state(sctx
);
3061 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
3062 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.framebuffer
);
3064 if (sctx
->screen
->dpbb_allowed
)
3065 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
3067 if (sctx
->framebuffer
.any_dst_linear
!= old_any_dst_linear
)
3068 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
3070 if (sctx
->screen
->has_out_of_order_rast
&&
3071 (sctx
->framebuffer
.colorbuf_enabled_4bit
!= old_colorbuf_enabled_4bit
||
3072 !!sctx
->framebuffer
.state
.zsbuf
!= old_has_zsbuf
||
3073 (zstex
&& zstex
->surface
.has_stencil
!= old_has_stencil
)))
3074 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
3076 if (sctx
->framebuffer
.nr_samples
!= old_nr_samples
) {
3077 struct pipe_constant_buffer constbuf
= {0};
3079 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
3080 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
3082 constbuf
.buffer
= sctx
->sample_pos_buffer
;
3084 /* Set sample locations as fragment shader constants. */
3085 switch (sctx
->framebuffer
.nr_samples
) {
3087 constbuf
.buffer_offset
= 0;
3090 constbuf
.buffer_offset
= (ubyte
*)sctx
->sample_positions
.x2
-
3091 (ubyte
*)sctx
->sample_positions
.x1
;
3094 constbuf
.buffer_offset
= (ubyte
*)sctx
->sample_positions
.x4
-
3095 (ubyte
*)sctx
->sample_positions
.x1
;
3098 constbuf
.buffer_offset
= (ubyte
*)sctx
->sample_positions
.x8
-
3099 (ubyte
*)sctx
->sample_positions
.x1
;
3102 constbuf
.buffer_offset
= (ubyte
*)sctx
->sample_positions
.x16
-
3103 (ubyte
*)sctx
->sample_positions
.x1
;
3106 PRINT_ERR("Requested an invalid number of samples %i.\n",
3107 sctx
->framebuffer
.nr_samples
);
3110 constbuf
.buffer_size
= sctx
->framebuffer
.nr_samples
* 2 * 4;
3111 si_set_rw_buffer(sctx
, SI_PS_CONST_SAMPLE_POSITIONS
, &constbuf
);
3113 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_sample_locs
);
3116 sctx
->do_update_shaders
= true;
3118 if (!sctx
->decompression_enabled
) {
3119 /* Prevent textures decompression when the framebuffer state
3120 * changes come from the decompression passes themselves.
3122 sctx
->need_check_render_feedback
= true;
3126 static void si_emit_framebuffer_state(struct si_context
*sctx
)
3128 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
3129 struct pipe_framebuffer_state
*state
= &sctx
->framebuffer
.state
;
3130 unsigned i
, nr_cbufs
= state
->nr_cbufs
;
3131 struct si_texture
*tex
= NULL
;
3132 struct si_surface
*cb
= NULL
;
3133 unsigned cb_color_info
= 0;
3136 for (i
= 0; i
< nr_cbufs
; i
++) {
3137 uint64_t cb_color_base
, cb_color_fmask
, cb_color_cmask
, cb_dcc_base
;
3138 unsigned cb_color_attrib
;
3140 if (!(sctx
->framebuffer
.dirty_cbufs
& (1 << i
)))
3143 cb
= (struct si_surface
*)state
->cbufs
[i
];
3145 radeon_set_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
3146 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
3150 tex
= (struct si_texture
*)cb
->base
.texture
;
3151 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
3152 &tex
->buffer
, RADEON_USAGE_READWRITE
,
3153 tex
->buffer
.b
.b
.nr_samples
> 1 ?
3154 RADEON_PRIO_COLOR_BUFFER_MSAA
:
3155 RADEON_PRIO_COLOR_BUFFER
);
3157 if (tex
->cmask_buffer
&& tex
->cmask_buffer
!= &tex
->buffer
) {
3158 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
3159 tex
->cmask_buffer
, RADEON_USAGE_READWRITE
,
3160 RADEON_PRIO_SEPARATE_META
);
3163 if (tex
->dcc_separate_buffer
)
3164 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
3165 tex
->dcc_separate_buffer
,
3166 RADEON_USAGE_READWRITE
,
3167 RADEON_PRIO_SEPARATE_META
);
3169 /* Compute mutable surface parameters. */
3170 cb_color_base
= tex
->buffer
.gpu_address
>> 8;
3172 cb_color_cmask
= tex
->cmask_base_address_reg
;
3174 cb_color_info
= cb
->cb_color_info
| tex
->cb_color_info
;
3175 cb_color_attrib
= cb
->cb_color_attrib
;
3177 if (cb
->base
.u
.tex
.level
> 0)
3178 cb_color_info
&= C_028C70_FAST_CLEAR
;
3180 if (tex
->fmask_offset
) {
3181 cb_color_fmask
= (tex
->buffer
.gpu_address
+ tex
->fmask_offset
) >> 8;
3182 cb_color_fmask
|= tex
->surface
.fmask_tile_swizzle
;
3186 if (vi_dcc_enabled(tex
, cb
->base
.u
.tex
.level
)) {
3187 bool is_msaa_resolve_dst
= state
->cbufs
[0] &&
3188 state
->cbufs
[0]->texture
->nr_samples
> 1 &&
3189 state
->cbufs
[1] == &cb
->base
&&
3190 state
->cbufs
[1]->texture
->nr_samples
<= 1;
3192 if (!is_msaa_resolve_dst
)
3193 cb_color_info
|= S_028C70_DCC_ENABLE(1);
3195 cb_dcc_base
= ((!tex
->dcc_separate_buffer
? tex
->buffer
.gpu_address
: 0) +
3196 tex
->dcc_offset
) >> 8;
3198 unsigned dcc_tile_swizzle
= tex
->surface
.tile_swizzle
;
3199 dcc_tile_swizzle
&= (tex
->surface
.dcc_alignment
- 1) >> 8;
3200 cb_dcc_base
|= dcc_tile_swizzle
;
3203 if (sctx
->chip_class
>= GFX10
) {
3204 unsigned cb_color_attrib3
;
3206 /* Set mutable surface parameters. */
3207 cb_color_base
+= tex
->surface
.u
.gfx9
.surf_offset
>> 8;
3208 cb_color_base
|= tex
->surface
.tile_swizzle
;
3209 if (!tex
->fmask_offset
)
3210 cb_color_fmask
= cb_color_base
;
3211 if (cb
->base
.u
.tex
.level
> 0)
3212 cb_color_cmask
= cb_color_base
;
3214 cb_color_attrib3
= cb
->cb_color_attrib3
|
3215 S_028EE0_COLOR_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
3216 S_028EE0_FMASK_SW_MODE(tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
) |
3217 S_028EE0_CMASK_PIPE_ALIGNED(tex
->surface
.u
.gfx9
.cmask
.pipe_aligned
) |
3218 S_028EE0_DCC_PIPE_ALIGNED(tex
->surface
.u
.gfx9
.dcc
.pipe_aligned
);
3220 radeon_set_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C, 14);
3221 radeon_emit(cs
, cb_color_base
); /* CB_COLOR0_BASE */
3222 radeon_emit(cs
, 0); /* hole */
3223 radeon_emit(cs
, 0); /* hole */
3224 radeon_emit(cs
, cb
->cb_color_view
); /* CB_COLOR0_VIEW */
3225 radeon_emit(cs
, cb_color_info
); /* CB_COLOR0_INFO */
3226 radeon_emit(cs
, cb_color_attrib
); /* CB_COLOR0_ATTRIB */
3227 radeon_emit(cs
, cb
->cb_dcc_control
); /* CB_COLOR0_DCC_CONTROL */
3228 radeon_emit(cs
, cb_color_cmask
); /* CB_COLOR0_CMASK */
3229 radeon_emit(cs
, 0); /* hole */
3230 radeon_emit(cs
, cb_color_fmask
); /* CB_COLOR0_FMASK */
3231 radeon_emit(cs
, 0); /* hole */
3232 radeon_emit(cs
, tex
->color_clear_value
[0]); /* CB_COLOR0_CLEAR_WORD0 */
3233 radeon_emit(cs
, tex
->color_clear_value
[1]); /* CB_COLOR0_CLEAR_WORD1 */
3234 radeon_emit(cs
, cb_dcc_base
); /* CB_COLOR0_DCC_BASE */
3236 radeon_set_context_reg(cs
, R_028E40_CB_COLOR0_BASE_EXT
+ i
* 4,
3237 cb_color_base
>> 32);
3238 radeon_set_context_reg(cs
, R_028E60_CB_COLOR0_CMASK_BASE_EXT
+ i
* 4,
3239 cb_color_cmask
>> 32);
3240 radeon_set_context_reg(cs
, R_028E80_CB_COLOR0_FMASK_BASE_EXT
+ i
* 4,
3241 cb_color_fmask
>> 32);
3242 radeon_set_context_reg(cs
, R_028EA0_CB_COLOR0_DCC_BASE_EXT
+ i
* 4,
3244 radeon_set_context_reg(cs
, R_028EC0_CB_COLOR0_ATTRIB2
+ i
* 4,
3245 cb
->cb_color_attrib2
);
3246 radeon_set_context_reg(cs
, R_028EE0_CB_COLOR0_ATTRIB3
+ i
* 4,
3248 } else if (sctx
->chip_class
>= GFX9
) {
3249 struct gfx9_surf_meta_flags meta
;
3251 if (tex
->dcc_offset
)
3252 meta
= tex
->surface
.u
.gfx9
.dcc
;
3254 meta
= tex
->surface
.u
.gfx9
.cmask
;
3256 /* Set mutable surface parameters. */
3257 cb_color_base
+= tex
->surface
.u
.gfx9
.surf_offset
>> 8;
3258 cb_color_base
|= tex
->surface
.tile_swizzle
;
3259 if (!tex
->fmask_offset
)
3260 cb_color_fmask
= cb_color_base
;
3261 if (cb
->base
.u
.tex
.level
> 0)
3262 cb_color_cmask
= cb_color_base
;
3263 cb_color_attrib
|= S_028C74_COLOR_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
3264 S_028C74_FMASK_SW_MODE(tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
) |
3265 S_028C74_RB_ALIGNED(meta
.rb_aligned
) |
3266 S_028C74_PIPE_ALIGNED(meta
.pipe_aligned
);
3268 radeon_set_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C, 15);
3269 radeon_emit(cs
, cb_color_base
); /* CB_COLOR0_BASE */
3270 radeon_emit(cs
, S_028C64_BASE_256B(cb_color_base
>> 32)); /* CB_COLOR0_BASE_EXT */
3271 radeon_emit(cs
, cb
->cb_color_attrib2
); /* CB_COLOR0_ATTRIB2 */
3272 radeon_emit(cs
, cb
->cb_color_view
); /* CB_COLOR0_VIEW */
3273 radeon_emit(cs
, cb_color_info
); /* CB_COLOR0_INFO */
3274 radeon_emit(cs
, cb_color_attrib
); /* CB_COLOR0_ATTRIB */
3275 radeon_emit(cs
, cb
->cb_dcc_control
); /* CB_COLOR0_DCC_CONTROL */
3276 radeon_emit(cs
, cb_color_cmask
); /* CB_COLOR0_CMASK */
3277 radeon_emit(cs
, S_028C80_BASE_256B(cb_color_cmask
>> 32)); /* CB_COLOR0_CMASK_BASE_EXT */
3278 radeon_emit(cs
, cb_color_fmask
); /* CB_COLOR0_FMASK */
3279 radeon_emit(cs
, S_028C88_BASE_256B(cb_color_fmask
>> 32)); /* CB_COLOR0_FMASK_BASE_EXT */
3280 radeon_emit(cs
, tex
->color_clear_value
[0]); /* CB_COLOR0_CLEAR_WORD0 */
3281 radeon_emit(cs
, tex
->color_clear_value
[1]); /* CB_COLOR0_CLEAR_WORD1 */
3282 radeon_emit(cs
, cb_dcc_base
); /* CB_COLOR0_DCC_BASE */
3283 radeon_emit(cs
, S_028C98_BASE_256B(cb_dcc_base
>> 32)); /* CB_COLOR0_DCC_BASE_EXT */
3285 radeon_set_context_reg(cs
, R_0287A0_CB_MRT0_EPITCH
+ i
* 4,
3286 S_0287A0_EPITCH(tex
->surface
.u
.gfx9
.surf
.epitch
));
3288 /* Compute mutable surface parameters (GFX6-GFX8). */
3289 const struct legacy_surf_level
*level_info
=
3290 &tex
->surface
.u
.legacy
.level
[cb
->base
.u
.tex
.level
];
3291 unsigned pitch_tile_max
, slice_tile_max
, tile_mode_index
;
3292 unsigned cb_color_pitch
, cb_color_slice
, cb_color_fmask_slice
;
3294 cb_color_base
+= level_info
->offset
>> 8;
3295 /* Only macrotiled modes can set tile swizzle. */
3296 if (level_info
->mode
== RADEON_SURF_MODE_2D
)
3297 cb_color_base
|= tex
->surface
.tile_swizzle
;
3299 if (!tex
->fmask_offset
)
3300 cb_color_fmask
= cb_color_base
;
3301 if (cb
->base
.u
.tex
.level
> 0)
3302 cb_color_cmask
= cb_color_base
;
3304 cb_dcc_base
+= level_info
->dcc_offset
>> 8;
3306 pitch_tile_max
= level_info
->nblk_x
/ 8 - 1;
3307 slice_tile_max
= level_info
->nblk_x
*
3308 level_info
->nblk_y
/ 64 - 1;
3309 tile_mode_index
= si_tile_mode_index(tex
, cb
->base
.u
.tex
.level
, false);
3311 cb_color_attrib
|= S_028C74_TILE_MODE_INDEX(tile_mode_index
);
3312 cb_color_pitch
= S_028C64_TILE_MAX(pitch_tile_max
);
3313 cb_color_slice
= S_028C68_TILE_MAX(slice_tile_max
);
3315 if (tex
->fmask_offset
) {
3316 if (sctx
->chip_class
>= GFX7
)
3317 cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(tex
->surface
.u
.legacy
.fmask
.pitch_in_pixels
/ 8 - 1);
3318 cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tex
->surface
.u
.legacy
.fmask
.tiling_index
);
3319 cb_color_fmask_slice
= S_028C88_TILE_MAX(tex
->surface
.u
.legacy
.fmask
.slice_tile_max
);
3321 /* This must be set for fast clear to work without FMASK. */
3322 if (sctx
->chip_class
>= GFX7
)
3323 cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(pitch_tile_max
);
3324 cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index
);
3325 cb_color_fmask_slice
= S_028C88_TILE_MAX(slice_tile_max
);
3328 radeon_set_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C,
3329 sctx
->chip_class
>= GFX8
? 14 : 13);
3330 radeon_emit(cs
, cb_color_base
); /* CB_COLOR0_BASE */
3331 radeon_emit(cs
, cb_color_pitch
); /* CB_COLOR0_PITCH */
3332 radeon_emit(cs
, cb_color_slice
); /* CB_COLOR0_SLICE */
3333 radeon_emit(cs
, cb
->cb_color_view
); /* CB_COLOR0_VIEW */
3334 radeon_emit(cs
, cb_color_info
); /* CB_COLOR0_INFO */
3335 radeon_emit(cs
, cb_color_attrib
); /* CB_COLOR0_ATTRIB */
3336 radeon_emit(cs
, cb
->cb_dcc_control
); /* CB_COLOR0_DCC_CONTROL */
3337 radeon_emit(cs
, cb_color_cmask
); /* CB_COLOR0_CMASK */
3338 radeon_emit(cs
, tex
->surface
.u
.legacy
.cmask_slice_tile_max
); /* CB_COLOR0_CMASK_SLICE */
3339 radeon_emit(cs
, cb_color_fmask
); /* CB_COLOR0_FMASK */
3340 radeon_emit(cs
, cb_color_fmask_slice
); /* CB_COLOR0_FMASK_SLICE */
3341 radeon_emit(cs
, tex
->color_clear_value
[0]); /* CB_COLOR0_CLEAR_WORD0 */
3342 radeon_emit(cs
, tex
->color_clear_value
[1]); /* CB_COLOR0_CLEAR_WORD1 */
3344 if (sctx
->chip_class
>= GFX8
) /* R_028C94_CB_COLOR0_DCC_BASE */
3345 radeon_emit(cs
, cb_dcc_base
);
3349 if (sctx
->framebuffer
.dirty_cbufs
& (1 << i
))
3350 radeon_set_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C, 0);
3353 if (state
->zsbuf
&& sctx
->framebuffer
.dirty_zsbuf
) {
3354 struct si_surface
*zb
= (struct si_surface
*)state
->zsbuf
;
3355 struct si_texture
*tex
= (struct si_texture
*)zb
->base
.texture
;
3357 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
3358 &tex
->buffer
, RADEON_USAGE_READWRITE
,
3359 zb
->base
.texture
->nr_samples
> 1 ?
3360 RADEON_PRIO_DEPTH_BUFFER_MSAA
:
3361 RADEON_PRIO_DEPTH_BUFFER
);
3363 if (sctx
->chip_class
>= GFX10
) {
3364 radeon_set_context_reg(cs
, R_028014_DB_HTILE_DATA_BASE
, zb
->db_htile_data_base
);
3365 radeon_set_context_reg(cs
, R_02801C_DB_DEPTH_SIZE_XY
, zb
->db_depth_size
);
3367 radeon_set_context_reg_seq(cs
, R_02803C_DB_DEPTH_INFO
, 7);
3368 radeon_emit(cs
, S_02803C_RESOURCE_LEVEL(1)); /* DB_DEPTH_INFO */
3369 radeon_emit(cs
, zb
->db_z_info
| /* DB_Z_INFO */
3370 S_028038_ZRANGE_PRECISION(tex
->depth_clear_value
!= 0));
3371 radeon_emit(cs
, zb
->db_stencil_info
); /* DB_STENCIL_INFO */
3372 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_READ_BASE */
3373 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_READ_BASE */
3374 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_WRITE_BASE */
3375 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_WRITE_BASE */
3377 radeon_set_context_reg_seq(cs
, R_028068_DB_Z_READ_BASE_HI
, 5);
3378 radeon_emit(cs
, zb
->db_depth_base
>> 32); /* DB_Z_READ_BASE_HI */
3379 radeon_emit(cs
, zb
->db_stencil_base
>> 32); /* DB_STENCIL_READ_BASE_HI */
3380 radeon_emit(cs
, zb
->db_depth_base
>> 32); /* DB_Z_WRITE_BASE_HI */
3381 radeon_emit(cs
, zb
->db_stencil_base
>> 32); /* DB_STENCIL_WRITE_BASE_HI */
3382 radeon_emit(cs
, zb
->db_htile_data_base
>> 32); /* DB_HTILE_DATA_BASE_HI */
3383 } else if (sctx
->chip_class
>= GFX9
) {
3384 radeon_set_context_reg_seq(cs
, R_028014_DB_HTILE_DATA_BASE
, 3);
3385 radeon_emit(cs
, zb
->db_htile_data_base
); /* DB_HTILE_DATA_BASE */
3386 radeon_emit(cs
, S_028018_BASE_HI(zb
->db_htile_data_base
>> 32)); /* DB_HTILE_DATA_BASE_HI */
3387 radeon_emit(cs
, zb
->db_depth_size
); /* DB_DEPTH_SIZE */
3389 radeon_set_context_reg_seq(cs
, R_028038_DB_Z_INFO
, 10);
3390 radeon_emit(cs
, zb
->db_z_info
| /* DB_Z_INFO */
3391 S_028038_ZRANGE_PRECISION(tex
->depth_clear_value
!= 0));
3392 radeon_emit(cs
, zb
->db_stencil_info
); /* DB_STENCIL_INFO */
3393 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_READ_BASE */
3394 radeon_emit(cs
, S_028044_BASE_HI(zb
->db_depth_base
>> 32)); /* DB_Z_READ_BASE_HI */
3395 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_READ_BASE */
3396 radeon_emit(cs
, S_02804C_BASE_HI(zb
->db_stencil_base
>> 32)); /* DB_STENCIL_READ_BASE_HI */
3397 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_WRITE_BASE */
3398 radeon_emit(cs
, S_028054_BASE_HI(zb
->db_depth_base
>> 32)); /* DB_Z_WRITE_BASE_HI */
3399 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_WRITE_BASE */
3400 radeon_emit(cs
, S_02805C_BASE_HI(zb
->db_stencil_base
>> 32)); /* DB_STENCIL_WRITE_BASE_HI */
3402 radeon_set_context_reg_seq(cs
, R_028068_DB_Z_INFO2
, 2);
3403 radeon_emit(cs
, zb
->db_z_info2
); /* DB_Z_INFO2 */
3404 radeon_emit(cs
, zb
->db_stencil_info2
); /* DB_STENCIL_INFO2 */
3406 radeon_set_context_reg(cs
, R_028014_DB_HTILE_DATA_BASE
, zb
->db_htile_data_base
);
3408 radeon_set_context_reg_seq(cs
, R_02803C_DB_DEPTH_INFO
, 9);
3409 radeon_emit(cs
, zb
->db_depth_info
); /* DB_DEPTH_INFO */
3410 radeon_emit(cs
, zb
->db_z_info
| /* DB_Z_INFO */
3411 S_028040_ZRANGE_PRECISION(tex
->depth_clear_value
!= 0));
3412 radeon_emit(cs
, zb
->db_stencil_info
); /* DB_STENCIL_INFO */
3413 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_READ_BASE */
3414 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_READ_BASE */
3415 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_WRITE_BASE */
3416 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_WRITE_BASE */
3417 radeon_emit(cs
, zb
->db_depth_size
); /* DB_DEPTH_SIZE */
3418 radeon_emit(cs
, zb
->db_depth_slice
); /* DB_DEPTH_SLICE */
3421 radeon_set_context_reg_seq(cs
, R_028028_DB_STENCIL_CLEAR
, 2);
3422 radeon_emit(cs
, tex
->stencil_clear_value
); /* R_028028_DB_STENCIL_CLEAR */
3423 radeon_emit(cs
, fui(tex
->depth_clear_value
)); /* R_02802C_DB_DEPTH_CLEAR */
3425 radeon_set_context_reg(cs
, R_028008_DB_DEPTH_VIEW
, zb
->db_depth_view
);
3426 radeon_set_context_reg(cs
, R_028ABC_DB_HTILE_SURFACE
, zb
->db_htile_surface
);
3427 } else if (sctx
->framebuffer
.dirty_zsbuf
) {
3428 if (sctx
->chip_class
== GFX9
)
3429 radeon_set_context_reg_seq(cs
, R_028038_DB_Z_INFO
, 2);
3431 radeon_set_context_reg_seq(cs
, R_028040_DB_Z_INFO
, 2);
3433 radeon_emit(cs
, S_028040_FORMAT(V_028040_Z_INVALID
)); /* DB_Z_INFO */
3434 radeon_emit(cs
, S_028044_FORMAT(V_028044_STENCIL_INVALID
)); /* DB_STENCIL_INFO */
3437 /* Framebuffer dimensions. */
3438 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
3439 radeon_set_context_reg(cs
, R_028208_PA_SC_WINDOW_SCISSOR_BR
,
3440 S_028208_BR_X(state
->width
) | S_028208_BR_Y(state
->height
));
3442 if (sctx
->screen
->dfsm_allowed
) {
3443 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3444 radeon_emit(cs
, EVENT_TYPE(V_028A90_BREAK_BATCH
) | EVENT_INDEX(0));
3447 sctx
->framebuffer
.dirty_cbufs
= 0;
3448 sctx
->framebuffer
.dirty_zsbuf
= false;
3451 static void si_emit_msaa_sample_locs(struct si_context
*sctx
)
3453 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
3454 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
3455 unsigned nr_samples
= sctx
->framebuffer
.nr_samples
;
3456 bool has_msaa_sample_loc_bug
= sctx
->screen
->has_msaa_sample_loc_bug
;
3458 /* Smoothing (only possible with nr_samples == 1) uses the same
3459 * sample locations as the MSAA it simulates.
3461 if (nr_samples
<= 1 && sctx
->smoothing_enabled
)
3462 nr_samples
= SI_NUM_SMOOTH_AA_SAMPLES
;
3464 /* On Polaris, the small primitive filter uses the sample locations
3465 * even when MSAA is off, so we need to make sure they're set to 0.
3467 * GFX10 uses sample locations unconditionally, so they always need
3470 if ((nr_samples
>= 2 || has_msaa_sample_loc_bug
||
3471 sctx
->chip_class
>= GFX10
) &&
3472 nr_samples
!= sctx
->sample_locs_num_samples
) {
3473 sctx
->sample_locs_num_samples
= nr_samples
;
3474 si_emit_sample_locations(cs
, nr_samples
);
3477 if (sctx
->family
>= CHIP_POLARIS10
) {
3478 unsigned small_prim_filter_cntl
=
3479 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
3481 S_028830_LINE_FILTER_DISABLE(sctx
->family
<= CHIP_POLARIS12
);
3483 /* The alternative of setting sample locations to 0 would
3484 * require a DB flush to avoid Z errors, see
3485 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
3487 if (has_msaa_sample_loc_bug
&&
3488 sctx
->framebuffer
.nr_samples
> 1 &&
3489 !rs
->multisample_enable
)
3490 small_prim_filter_cntl
&= C_028830_SMALL_PRIM_FILTER_ENABLE
;
3492 radeon_opt_set_context_reg(sctx
,
3493 R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL
,
3494 SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL
,
3495 small_prim_filter_cntl
);
3498 /* The exclusion bits can be set to improve rasterization efficiency
3499 * if no sample lies on the pixel boundary (-8 sample offset).
3501 bool exclusion
= sctx
->chip_class
>= GFX7
&&
3502 (!rs
->multisample_enable
|| nr_samples
!= 16);
3503 radeon_opt_set_context_reg(sctx
, R_02882C_PA_SU_PRIM_FILTER_CNTL
,
3504 SI_TRACKED_PA_SU_PRIM_FILTER_CNTL
,
3505 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion
) |
3506 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion
));
3509 static bool si_out_of_order_rasterization(struct si_context
*sctx
)
3511 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
3512 struct si_state_dsa
*dsa
= sctx
->queued
.named
.dsa
;
3514 if (!sctx
->screen
->has_out_of_order_rast
)
3517 unsigned colormask
= sctx
->framebuffer
.colorbuf_enabled_4bit
;
3520 colormask
&= blend
->cb_target_enabled_4bit
;
3525 /* Conservative: No logic op. */
3526 if (colormask
&& blend
->logicop_enable
)
3529 struct si_dsa_order_invariance dsa_order_invariant
= {
3530 .zs
= true, .pass_set
= true, .pass_last
= false
3533 if (sctx
->framebuffer
.state
.zsbuf
) {
3534 struct si_texture
*zstex
=
3535 (struct si_texture
*)sctx
->framebuffer
.state
.zsbuf
->texture
;
3536 bool has_stencil
= zstex
->surface
.has_stencil
;
3537 dsa_order_invariant
= dsa
->order_invariance
[has_stencil
];
3538 if (!dsa_order_invariant
.zs
)
3541 /* The set of PS invocations is always order invariant,
3542 * except when early Z/S tests are requested. */
3543 if (sctx
->ps_shader
.cso
&&
3544 sctx
->ps_shader
.cso
->info
.writes_memory
&&
3545 sctx
->ps_shader
.cso
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
] &&
3546 !dsa_order_invariant
.pass_set
)
3549 if (sctx
->num_perfect_occlusion_queries
!= 0 &&
3550 !dsa_order_invariant
.pass_set
)
3557 unsigned blendmask
= colormask
& blend
->blend_enable_4bit
;
3560 /* Only commutative blending. */
3561 if (blendmask
& ~blend
->commutative_4bit
)
3564 if (!dsa_order_invariant
.pass_set
)
3568 if (colormask
& ~blendmask
) {
3569 if (!dsa_order_invariant
.pass_last
)
3576 static void si_emit_msaa_config(struct si_context
*sctx
)
3578 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
3579 unsigned num_tile_pipes
= sctx
->screen
->info
.num_tile_pipes
;
3580 /* 33% faster rendering to linear color buffers */
3581 bool dst_is_linear
= sctx
->framebuffer
.any_dst_linear
;
3582 bool out_of_order_rast
= si_out_of_order_rasterization(sctx
);
3583 unsigned sc_mode_cntl_1
=
3584 S_028A4C_WALK_SIZE(dst_is_linear
) |
3585 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear
) |
3586 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes
== 2 ? 2 : 3) |
3587 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast
) |
3588 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
3590 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
3591 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
3592 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
3593 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
3594 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
3595 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
3596 unsigned db_eqaa
= S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3597 S_028804_INCOHERENT_EQAA_READS(1) |
3598 S_028804_INTERPOLATE_COMP_Z(1) |
3599 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
3600 unsigned coverage_samples
, color_samples
, z_samples
;
3601 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
3603 /* S: Coverage samples (up to 16x):
3604 * - Scan conversion samples (PA_SC_AA_CONFIG.MSAA_NUM_SAMPLES)
3605 * - CB FMASK samples (CB_COLORi_ATTRIB.NUM_SAMPLES)
3607 * Z: Z/S samples (up to 8x, must be <= coverage samples and >= color samples):
3608 * - Value seen by DB (DB_Z_INFO.NUM_SAMPLES)
3609 * - Value seen by CB, must be correct even if Z/S is unbound (DB_EQAA.MAX_ANCHOR_SAMPLES)
3610 * # Missing samples are derived from Z planes if Z is compressed (up to 16x quality), or
3611 * # from the closest defined sample if Z is uncompressed (same quality as the number of
3614 * F: Color samples (up to 8x, must be <= coverage samples):
3615 * - CB color samples (CB_COLORi_ATTRIB.NUM_FRAGMENTS)
3616 * - PS iter samples (DB_EQAA.PS_ITER_SAMPLES)
3618 * Can be anything between coverage and color samples:
3619 * - SampleMaskIn samples (PA_SC_AA_CONFIG.MSAA_EXPOSED_SAMPLES)
3620 * - SampleMaskOut samples (DB_EQAA.MASK_EXPORT_NUM_SAMPLES)
3621 * - Alpha-to-coverage samples (DB_EQAA.ALPHA_TO_MASK_NUM_SAMPLES)
3622 * - Occlusion query samples (DB_COUNT_CONTROL.SAMPLE_RATE)
3623 * # All are currently set the same as coverage samples.
3625 * If color samples < coverage samples, FMASK has a higher bpp to store an "unknown"
3626 * flag for undefined color samples. A shader-based resolve must handle unknowns
3627 * or mask them out with AND. Unknowns can also be guessed from neighbors via
3628 * an edge-detect shader-based resolve, which is required to make "color samples = 1"
3629 * useful. The CB resolve always drops unknowns.
3631 * Sensible AA configurations:
3632 * EQAA 16s 8z 8f - might look the same as 16x MSAA if Z is compressed
3633 * EQAA 16s 8z 4f - might look the same as 16x MSAA if Z is compressed
3634 * EQAA 16s 4z 4f - might look the same as 16x MSAA if Z is compressed
3635 * EQAA 8s 8z 8f = 8x MSAA
3636 * EQAA 8s 8z 4f - might look the same as 8x MSAA
3637 * EQAA 8s 8z 2f - might look the same as 8x MSAA with low-density geometry
3638 * EQAA 8s 4z 4f - might look the same as 8x MSAA if Z is compressed
3639 * EQAA 8s 4z 2f - might look the same as 8x MSAA with low-density geometry if Z is compressed
3640 * EQAA 4s 4z 4f = 4x MSAA
3641 * EQAA 4s 4z 2f - might look the same as 4x MSAA with low-density geometry
3642 * EQAA 2s 2z 2f = 2x MSAA
3644 if (sctx
->framebuffer
.nr_samples
> 1 && rs
->multisample_enable
) {
3645 coverage_samples
= sctx
->framebuffer
.nr_samples
;
3646 color_samples
= sctx
->framebuffer
.nr_color_samples
;
3648 if (sctx
->framebuffer
.state
.zsbuf
) {
3649 z_samples
= sctx
->framebuffer
.state
.zsbuf
->texture
->nr_samples
;
3650 z_samples
= MAX2(1, z_samples
);
3652 z_samples
= coverage_samples
;
3654 } else if (sctx
->smoothing_enabled
) {
3655 coverage_samples
= color_samples
= z_samples
= SI_NUM_SMOOTH_AA_SAMPLES
;
3657 coverage_samples
= color_samples
= z_samples
= 1;
3660 /* Required by OpenGL line rasterization.
3662 * TODO: We should also enable perpendicular endcaps for AA lines,
3663 * but that requires implementing line stippling in the pixel
3664 * shader. SC can only do line stippling with axis-aligned
3667 unsigned sc_line_cntl
= S_028BDC_DX10_DIAMOND_TEST_ENA(1);
3668 unsigned sc_aa_config
= 0;
3670 if (coverage_samples
> 1) {
3671 /* distance from the pixel center, indexed by log2(nr_samples) */
3672 static unsigned max_dist
[] = {
3679 unsigned log_samples
= util_logbase2(coverage_samples
);
3680 unsigned log_z_samples
= util_logbase2(z_samples
);
3681 unsigned ps_iter_samples
= si_get_ps_iter_samples(sctx
);
3682 unsigned log_ps_iter_samples
= util_logbase2(ps_iter_samples
);
3684 sc_line_cntl
|= S_028BDC_EXPAND_LINE_WIDTH(1);
3685 sc_aa_config
= S_028BE0_MSAA_NUM_SAMPLES(log_samples
) |
3686 S_028BE0_MAX_SAMPLE_DIST(max_dist
[log_samples
]) |
3687 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples
);
3689 if (sctx
->framebuffer
.nr_samples
> 1) {
3690 db_eqaa
|= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples
) |
3691 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples
) |
3692 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples
) |
3693 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples
);
3694 sc_mode_cntl_1
|= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples
> 1);
3695 } else if (sctx
->smoothing_enabled
) {
3696 db_eqaa
|= S_028804_OVERRASTERIZATION_AMOUNT(log_samples
);
3700 unsigned initial_cdw
= cs
->current
.cdw
;
3702 /* R_028BDC_PA_SC_LINE_CNTL, R_028BE0_PA_SC_AA_CONFIG */
3703 radeon_opt_set_context_reg2(sctx
, R_028BDC_PA_SC_LINE_CNTL
,
3704 SI_TRACKED_PA_SC_LINE_CNTL
, sc_line_cntl
,
3706 /* R_028804_DB_EQAA */
3707 radeon_opt_set_context_reg(sctx
, R_028804_DB_EQAA
, SI_TRACKED_DB_EQAA
,
3709 /* R_028A4C_PA_SC_MODE_CNTL_1 */
3710 radeon_opt_set_context_reg(sctx
, R_028A4C_PA_SC_MODE_CNTL_1
,
3711 SI_TRACKED_PA_SC_MODE_CNTL_1
, sc_mode_cntl_1
);
3713 if (initial_cdw
!= cs
->current
.cdw
) {
3714 sctx
->context_roll
= true;
3716 /* GFX9: Flush DFSM when the AA mode changes. */
3717 if (sctx
->screen
->dfsm_allowed
) {
3718 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3719 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
3724 void si_update_ps_iter_samples(struct si_context
*sctx
)
3726 if (sctx
->framebuffer
.nr_samples
> 1)
3727 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
3728 if (sctx
->screen
->dpbb_allowed
)
3729 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
3732 static void si_set_min_samples(struct pipe_context
*ctx
, unsigned min_samples
)
3734 struct si_context
*sctx
= (struct si_context
*)ctx
;
3736 /* The hardware can only do sample shading with 2^n samples. */
3737 min_samples
= util_next_power_of_two(min_samples
);
3739 if (sctx
->ps_iter_samples
== min_samples
)
3742 sctx
->ps_iter_samples
= min_samples
;
3743 sctx
->do_update_shaders
= true;
3745 si_update_ps_iter_samples(sctx
);
3753 * Build the sampler view descriptor for a buffer texture.
3754 * @param state 256-bit descriptor; only the high 128 bits are filled in
3757 si_make_buffer_descriptor(struct si_screen
*screen
, struct si_resource
*buf
,
3758 enum pipe_format format
,
3759 unsigned offset
, unsigned size
,
3762 const struct util_format_description
*desc
;
3764 unsigned num_records
;
3766 desc
= util_format_description(format
);
3767 stride
= desc
->block
.bits
/ 8;
3769 num_records
= size
/ stride
;
3770 num_records
= MIN2(num_records
, (buf
->b
.b
.width0
- offset
) / stride
);
3772 /* The NUM_RECORDS field has a different meaning depending on the chip,
3773 * instruction type, STRIDE, and SWIZZLE_ENABLE.
3776 * - If STRIDE == 0, it's in byte units.
3777 * - If STRIDE != 0, it's in units of STRIDE, used with inst.IDXEN.
3780 * - For SMEM and STRIDE == 0, it's in byte units.
3781 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3782 * - For VMEM and STRIDE == 0 or SWIZZLE_ENABLE == 0, it's in byte units.
3783 * - For VMEM and STRIDE != 0 and SWIZZLE_ENABLE == 1, it's in units of STRIDE.
3784 * NOTE: There is incompatibility between VMEM and SMEM opcodes due to SWIZZLE_-
3785 * ENABLE. The workaround is to set STRIDE = 0 if SWIZZLE_ENABLE == 0 when
3786 * using SMEM. This can be done in the shader by clearing STRIDE with s_and.
3787 * That way the same descriptor can be used by both SMEM and VMEM.
3790 * - For SMEM and STRIDE == 0, it's in byte units.
3791 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3792 * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
3793 * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
3795 if (screen
->info
.chip_class
== GFX9
&& HAVE_LLVM
< 0x0800)
3796 /* When vindex == 0, LLVM < 8.0 sets IDXEN = 0, thus changing units
3797 * from STRIDE to bytes. This works around it by setting
3798 * NUM_RECORDS to at least the size of one element, so that
3799 * the first element is readable when IDXEN == 0.
3801 num_records
= num_records
? MAX2(num_records
, stride
) : 0;
3802 else if (screen
->info
.chip_class
== GFX8
)
3803 num_records
*= stride
;
3806 state
[5] = S_008F04_STRIDE(stride
);
3807 state
[6] = num_records
;
3808 state
[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc
->swizzle
[0])) |
3809 S_008F0C_DST_SEL_Y(si_map_swizzle(desc
->swizzle
[1])) |
3810 S_008F0C_DST_SEL_Z(si_map_swizzle(desc
->swizzle
[2])) |
3811 S_008F0C_DST_SEL_W(si_map_swizzle(desc
->swizzle
[3]));
3813 if (screen
->info
.chip_class
>= GFX10
) {
3814 const struct gfx10_format
*fmt
= &gfx10_format_table
[format
];
3816 /* OOB_SELECT chooses the out-of-bounds check:
3817 * - 0: (index >= NUM_RECORDS) || (offset >= STRIDE)
3818 * - 1: index >= NUM_RECORDS
3819 * - 2: NUM_RECORDS == 0
3820 * - 3: if SWIZZLE_ENABLE == 0: offset >= NUM_RECORDS
3821 * else: swizzle_address >= NUM_RECORDS
3823 state
[7] |= S_008F0C_FORMAT(fmt
->img_format
) |
3824 S_008F0C_OOB_SELECT(0) |
3825 S_008F0C_RESOURCE_LEVEL(1);
3828 unsigned num_format
, data_format
;
3830 first_non_void
= util_format_get_first_non_void_channel(format
);
3831 num_format
= si_translate_buffer_numformat(&screen
->b
, desc
, first_non_void
);
3832 data_format
= si_translate_buffer_dataformat(&screen
->b
, desc
, first_non_void
);
3834 state
[7] |= S_008F0C_NUM_FORMAT(num_format
) |
3835 S_008F0C_DATA_FORMAT(data_format
);
3839 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle
[4])
3841 unsigned bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
3843 if (swizzle
[3] == PIPE_SWIZZLE_X
) {
3844 /* For the pre-defined border color values (white, opaque
3845 * black, transparent black), the only thing that matters is
3846 * that the alpha channel winds up in the correct place
3847 * (because the RGB channels are all the same) so either of
3848 * these enumerations will work.
3850 if (swizzle
[2] == PIPE_SWIZZLE_Y
)
3851 bc_swizzle
= V_008F20_BC_SWIZZLE_WZYX
;
3853 bc_swizzle
= V_008F20_BC_SWIZZLE_WXYZ
;
3854 } else if (swizzle
[0] == PIPE_SWIZZLE_X
) {
3855 if (swizzle
[1] == PIPE_SWIZZLE_Y
)
3856 bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
3858 bc_swizzle
= V_008F20_BC_SWIZZLE_XWYZ
;
3859 } else if (swizzle
[1] == PIPE_SWIZZLE_X
) {
3860 bc_swizzle
= V_008F20_BC_SWIZZLE_YXWZ
;
3861 } else if (swizzle
[2] == PIPE_SWIZZLE_X
) {
3862 bc_swizzle
= V_008F20_BC_SWIZZLE_ZYXW
;
3869 * Build the sampler view descriptor for a texture.
3872 gfx10_make_texture_descriptor(struct si_screen
*screen
,
3873 struct si_texture
*tex
,
3875 enum pipe_texture_target target
,
3876 enum pipe_format pipe_format
,
3877 const unsigned char state_swizzle
[4],
3878 unsigned first_level
, unsigned last_level
,
3879 unsigned first_layer
, unsigned last_layer
,
3880 unsigned width
, unsigned height
, unsigned depth
,
3882 uint32_t *fmask_state
)
3884 struct pipe_resource
*res
= &tex
->buffer
.b
.b
;
3885 const struct util_format_description
*desc
;
3886 unsigned img_format
;
3887 unsigned char swizzle
[4];
3891 desc
= util_format_description(pipe_format
);
3892 img_format
= gfx10_format_table
[pipe_format
].img_format
;
3894 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
) {
3895 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
3896 const unsigned char swizzle_yyyy
[4] = {1, 1, 1, 1};
3897 const unsigned char swizzle_wwww
[4] = {3, 3, 3, 3};
3898 bool is_stencil
= false;
3900 switch (pipe_format
) {
3901 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
3902 case PIPE_FORMAT_X32_S8X24_UINT
:
3903 case PIPE_FORMAT_X8Z24_UNORM
:
3904 util_format_compose_swizzles(swizzle_yyyy
, state_swizzle
, swizzle
);
3907 case PIPE_FORMAT_X24S8_UINT
:
3909 * X24S8 is implemented as an 8_8_8_8 data format, to
3910 * fix texture gathers. This affects at least
3911 * GL45-CTS.texture_cube_map_array.sampling on VI.
3913 util_format_compose_swizzles(swizzle_wwww
, state_swizzle
, swizzle
);
3917 util_format_compose_swizzles(swizzle_xxxx
, state_swizzle
, swizzle
);
3918 is_stencil
= pipe_format
== PIPE_FORMAT_S8_UINT
;
3921 if (tex
->upgraded_depth
&& !is_stencil
) {
3922 assert(img_format
== V_008F0C_IMG_FORMAT_32_FLOAT
);
3923 img_format
= V_008F0C_IMG_FORMAT_32_FLOAT_CLAMP
;
3926 util_format_compose_swizzles(desc
->swizzle
, state_swizzle
, swizzle
);
3930 (res
->target
== PIPE_TEXTURE_CUBE
||
3931 res
->target
== PIPE_TEXTURE_CUBE_ARRAY
)) {
3932 /* For the purpose of shader images, treat cube maps as 2D
3935 type
= V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
3937 type
= si_tex_dim(screen
, tex
, target
, res
->nr_samples
);
3940 if (type
== V_008F1C_SQ_RSRC_IMG_1D_ARRAY
) {
3942 depth
= res
->array_size
;
3943 } else if (type
== V_008F1C_SQ_RSRC_IMG_2D_ARRAY
||
3944 type
== V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
) {
3945 if (sampler
|| res
->target
!= PIPE_TEXTURE_3D
)
3946 depth
= res
->array_size
;
3947 } else if (type
== V_008F1C_SQ_RSRC_IMG_CUBE
)
3948 depth
= res
->array_size
/ 6;
3951 state
[1] = S_00A004_FORMAT(img_format
) |
3952 S_00A004_WIDTH_LO(width
- 1);
3953 state
[2] = S_00A008_WIDTH_HI((width
- 1) >> 2) |
3954 S_00A008_HEIGHT(height
- 1) |
3955 S_00A008_RESOURCE_LEVEL(1);
3956 state
[3] = S_00A00C_DST_SEL_X(si_map_swizzle(swizzle
[0])) |
3957 S_00A00C_DST_SEL_Y(si_map_swizzle(swizzle
[1])) |
3958 S_00A00C_DST_SEL_Z(si_map_swizzle(swizzle
[2])) |
3959 S_00A00C_DST_SEL_W(si_map_swizzle(swizzle
[3])) |
3960 S_00A00C_BASE_LEVEL(res
->nr_samples
> 1 ?
3962 S_00A00C_LAST_LEVEL(res
->nr_samples
> 1 ?
3963 util_logbase2(res
->nr_samples
) :
3965 S_00A00C_BC_SWIZZLE(gfx9_border_color_swizzle(desc
->swizzle
)) |
3966 S_00A00C_TYPE(type
);
3967 /* Depth is the the last accessible layer on gfx9+. The hw doesn't need
3968 * to know the total number of layers.
3970 state
[4] = S_00A010_DEPTH((type
== V_008F1C_SQ_RSRC_IMG_3D
&& sampler
)
3971 ? depth
- 1 : last_layer
) |
3972 S_00A010_BASE_ARRAY(first_layer
);
3973 state
[5] = S_00A014_ARRAY_PITCH(!!(type
== V_008F1C_SQ_RSRC_IMG_3D
&& !sampler
)) |
3974 S_00A014_MAX_MIP(res
->nr_samples
> 1 ?
3975 util_logbase2(res
->nr_samples
) :
3976 tex
->buffer
.b
.b
.last_level
) |
3977 S_00A014_PERF_MOD(4);
3981 if (tex
->dcc_offset
) {
3982 state
[6] |= S_00A018_MAX_UNCOMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_256B
) |
3983 S_00A018_MAX_COMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_128B
) |
3984 S_00A018_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(pipe_format
));
3987 /* Initialize the sampler view for FMASK. */
3988 if (tex
->fmask_offset
) {
3991 va
= tex
->buffer
.gpu_address
+ tex
->fmask_offset
;
3993 #define FMASK(s,f) (((unsigned)(MAX2(1, s)) * 16) + (MAX2(1, f)))
3994 switch (FMASK(res
->nr_samples
, res
->nr_storage_samples
)) {
3996 format
= V_008F0C_IMG_FORMAT_FMASK8_S2_F1
;
3999 format
= V_008F0C_IMG_FORMAT_FMASK8_S2_F2
;
4002 format
= V_008F0C_IMG_FORMAT_FMASK8_S4_F1
;
4005 format
= V_008F0C_IMG_FORMAT_FMASK8_S4_F2
;
4008 format
= V_008F0C_IMG_FORMAT_FMASK8_S4_F4
;
4011 format
= V_008F0C_IMG_FORMAT_FMASK8_S8_F1
;
4014 format
= V_008F0C_IMG_FORMAT_FMASK16_S8_F2
;
4017 format
= V_008F0C_IMG_FORMAT_FMASK32_S8_F4
;
4020 format
= V_008F0C_IMG_FORMAT_FMASK32_S8_F8
;
4023 format
= V_008F0C_IMG_FORMAT_FMASK16_S16_F1
;
4026 format
= V_008F0C_IMG_FORMAT_FMASK32_S16_F2
;
4029 format
= V_008F0C_IMG_FORMAT_FMASK64_S16_F4
;
4032 format
= V_008F0C_IMG_FORMAT_FMASK64_S16_F8
;
4035 unreachable("invalid nr_samples");
4038 fmask_state
[0] = (va
>> 8) | tex
->surface
.fmask_tile_swizzle
;
4039 fmask_state
[1] = S_00A004_BASE_ADDRESS_HI(va
>> 40) |
4040 S_00A004_FORMAT(format
) |
4041 S_00A004_WIDTH_LO(width
- 1);
4042 fmask_state
[2] = S_00A008_WIDTH_HI((width
- 1) >> 2) |
4043 S_00A008_HEIGHT(height
- 1) |
4044 S_00A008_RESOURCE_LEVEL(1);
4045 fmask_state
[3] = S_00A00C_DST_SEL_X(V_008F1C_SQ_SEL_X
) |
4046 S_00A00C_DST_SEL_Y(V_008F1C_SQ_SEL_X
) |
4047 S_00A00C_DST_SEL_Z(V_008F1C_SQ_SEL_X
) |
4048 S_00A00C_DST_SEL_W(V_008F1C_SQ_SEL_X
) |
4049 S_00A00C_SW_MODE(tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
) |
4050 S_00A00C_TYPE(si_tex_dim(screen
, tex
, target
, 0));
4051 fmask_state
[4] = S_00A010_DEPTH(last_layer
) |
4052 S_00A010_BASE_ARRAY(first_layer
);
4054 fmask_state
[6] = S_00A018_META_PIPE_ALIGNED(tex
->surface
.u
.gfx9
.cmask
.pipe_aligned
);
4060 * Build the sampler view descriptor for a texture (SI-GFX9).
4063 si_make_texture_descriptor(struct si_screen
*screen
,
4064 struct si_texture
*tex
,
4066 enum pipe_texture_target target
,
4067 enum pipe_format pipe_format
,
4068 const unsigned char state_swizzle
[4],
4069 unsigned first_level
, unsigned last_level
,
4070 unsigned first_layer
, unsigned last_layer
,
4071 unsigned width
, unsigned height
, unsigned depth
,
4073 uint32_t *fmask_state
)
4075 struct pipe_resource
*res
= &tex
->buffer
.b
.b
;
4076 const struct util_format_description
*desc
;
4077 unsigned char swizzle
[4];
4079 unsigned num_format
, data_format
, type
, num_samples
;
4082 desc
= util_format_description(pipe_format
);
4084 num_samples
= desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
?
4085 MAX2(1, res
->nr_samples
) :
4086 MAX2(1, res
->nr_storage_samples
);
4088 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
) {
4089 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
4090 const unsigned char swizzle_yyyy
[4] = {1, 1, 1, 1};
4091 const unsigned char swizzle_wwww
[4] = {3, 3, 3, 3};
4093 switch (pipe_format
) {
4094 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
4095 case PIPE_FORMAT_X32_S8X24_UINT
:
4096 case PIPE_FORMAT_X8Z24_UNORM
:
4097 util_format_compose_swizzles(swizzle_yyyy
, state_swizzle
, swizzle
);
4099 case PIPE_FORMAT_X24S8_UINT
:
4101 * X24S8 is implemented as an 8_8_8_8 data format, to
4102 * fix texture gathers. This affects at least
4103 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
4105 if (screen
->info
.chip_class
<= GFX8
)
4106 util_format_compose_swizzles(swizzle_wwww
, state_swizzle
, swizzle
);
4108 util_format_compose_swizzles(swizzle_yyyy
, state_swizzle
, swizzle
);
4111 util_format_compose_swizzles(swizzle_xxxx
, state_swizzle
, swizzle
);
4114 util_format_compose_swizzles(desc
->swizzle
, state_swizzle
, swizzle
);
4117 first_non_void
= util_format_get_first_non_void_channel(pipe_format
);
4119 switch (pipe_format
) {
4120 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
4121 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
4124 if (first_non_void
< 0) {
4125 if (util_format_is_compressed(pipe_format
)) {
4126 switch (pipe_format
) {
4127 case PIPE_FORMAT_DXT1_SRGB
:
4128 case PIPE_FORMAT_DXT1_SRGBA
:
4129 case PIPE_FORMAT_DXT3_SRGBA
:
4130 case PIPE_FORMAT_DXT5_SRGBA
:
4131 case PIPE_FORMAT_BPTC_SRGBA
:
4132 case PIPE_FORMAT_ETC2_SRGB8
:
4133 case PIPE_FORMAT_ETC2_SRGB8A1
:
4134 case PIPE_FORMAT_ETC2_SRGBA8
:
4135 num_format
= V_008F14_IMG_NUM_FORMAT_SRGB
;
4137 case PIPE_FORMAT_RGTC1_SNORM
:
4138 case PIPE_FORMAT_LATC1_SNORM
:
4139 case PIPE_FORMAT_RGTC2_SNORM
:
4140 case PIPE_FORMAT_LATC2_SNORM
:
4141 case PIPE_FORMAT_ETC2_R11_SNORM
:
4142 case PIPE_FORMAT_ETC2_RG11_SNORM
:
4143 /* implies float, so use SNORM/UNORM to determine
4144 whether data is signed or not */
4145 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
4146 num_format
= V_008F14_IMG_NUM_FORMAT_SNORM
;
4149 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
4152 } else if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
4153 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
4155 num_format
= V_008F14_IMG_NUM_FORMAT_FLOAT
;
4157 } else if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
) {
4158 num_format
= V_008F14_IMG_NUM_FORMAT_SRGB
;
4160 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
4162 switch (desc
->channel
[first_non_void
].type
) {
4163 case UTIL_FORMAT_TYPE_FLOAT
:
4164 num_format
= V_008F14_IMG_NUM_FORMAT_FLOAT
;
4166 case UTIL_FORMAT_TYPE_SIGNED
:
4167 if (desc
->channel
[first_non_void
].normalized
)
4168 num_format
= V_008F14_IMG_NUM_FORMAT_SNORM
;
4169 else if (desc
->channel
[first_non_void
].pure_integer
)
4170 num_format
= V_008F14_IMG_NUM_FORMAT_SINT
;
4172 num_format
= V_008F14_IMG_NUM_FORMAT_SSCALED
;
4174 case UTIL_FORMAT_TYPE_UNSIGNED
:
4175 if (desc
->channel
[first_non_void
].normalized
)
4176 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
4177 else if (desc
->channel
[first_non_void
].pure_integer
)
4178 num_format
= V_008F14_IMG_NUM_FORMAT_UINT
;
4180 num_format
= V_008F14_IMG_NUM_FORMAT_USCALED
;
4185 data_format
= si_translate_texformat(&screen
->b
, pipe_format
, desc
, first_non_void
);
4186 if (data_format
== ~0) {
4190 /* S8 with Z32 HTILE needs a special format. */
4191 if (screen
->info
.chip_class
>= GFX9
&&
4192 pipe_format
== PIPE_FORMAT_S8_UINT
&&
4193 tex
->tc_compatible_htile
)
4194 data_format
= V_008F14_IMG_DATA_FORMAT_S8_32
;
4197 (res
->target
== PIPE_TEXTURE_CUBE
||
4198 res
->target
== PIPE_TEXTURE_CUBE_ARRAY
||
4199 (screen
->info
.chip_class
<= GFX8
&&
4200 res
->target
== PIPE_TEXTURE_3D
))) {
4201 /* For the purpose of shader images, treat cube maps and 3D
4202 * textures as 2D arrays. For 3D textures, the address
4203 * calculations for mipmaps are different, so we rely on the
4204 * caller to effectively disable mipmaps.
4206 type
= V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
4208 assert(res
->target
!= PIPE_TEXTURE_3D
|| (first_level
== 0 && last_level
== 0));
4210 type
= si_tex_dim(screen
, tex
, target
, num_samples
);
4213 if (type
== V_008F1C_SQ_RSRC_IMG_1D_ARRAY
) {
4215 depth
= res
->array_size
;
4216 } else if (type
== V_008F1C_SQ_RSRC_IMG_2D_ARRAY
||
4217 type
== V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
) {
4218 if (sampler
|| res
->target
!= PIPE_TEXTURE_3D
)
4219 depth
= res
->array_size
;
4220 } else if (type
== V_008F1C_SQ_RSRC_IMG_CUBE
)
4221 depth
= res
->array_size
/ 6;
4224 state
[1] = (S_008F14_DATA_FORMAT(data_format
) |
4225 S_008F14_NUM_FORMAT(num_format
));
4226 state
[2] = (S_008F18_WIDTH(width
- 1) |
4227 S_008F18_HEIGHT(height
- 1) |
4228 S_008F18_PERF_MOD(4));
4229 state
[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle
[0])) |
4230 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle
[1])) |
4231 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle
[2])) |
4232 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle
[3])) |
4233 S_008F1C_BASE_LEVEL(num_samples
> 1 ? 0 : first_level
) |
4234 S_008F1C_LAST_LEVEL(num_samples
> 1 ?
4235 util_logbase2(num_samples
) :
4237 S_008F1C_TYPE(type
));
4239 state
[5] = S_008F24_BASE_ARRAY(first_layer
);
4243 if (screen
->info
.chip_class
>= GFX9
) {
4244 unsigned bc_swizzle
= gfx9_border_color_swizzle(desc
->swizzle
);
4246 /* Depth is the the last accessible layer on Gfx9.
4247 * The hw doesn't need to know the total number of layers.
4249 if (type
== V_008F1C_SQ_RSRC_IMG_3D
)
4250 state
[4] |= S_008F20_DEPTH(depth
- 1);
4252 state
[4] |= S_008F20_DEPTH(last_layer
);
4254 state
[4] |= S_008F20_BC_SWIZZLE(bc_swizzle
);
4255 state
[5] |= S_008F24_MAX_MIP(num_samples
> 1 ?
4256 util_logbase2(num_samples
) :
4257 tex
->buffer
.b
.b
.last_level
);
4259 state
[3] |= S_008F1C_POW2_PAD(res
->last_level
> 0);
4260 state
[4] |= S_008F20_DEPTH(depth
- 1);
4261 state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
4264 if (tex
->dcc_offset
) {
4265 state
[6] = S_008F28_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(pipe_format
));
4267 /* The last dword is unused by hw. The shader uses it to clear
4268 * bits in the first dword of sampler state.
4270 if (screen
->info
.chip_class
<= GFX7
&& res
->nr_samples
<= 1) {
4271 if (first_level
== last_level
)
4272 state
[7] = C_008F30_MAX_ANISO_RATIO
;
4274 state
[7] = 0xffffffff;
4278 /* Initialize the sampler view for FMASK. */
4279 if (tex
->fmask_offset
) {
4280 uint32_t data_format
, num_format
;
4282 va
= tex
->buffer
.gpu_address
+ tex
->fmask_offset
;
4284 #define FMASK(s,f) (((unsigned)(MAX2(1, s)) * 16) + (MAX2(1, f)))
4285 if (screen
->info
.chip_class
>= GFX9
) {
4286 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK
;
4287 switch (FMASK(res
->nr_samples
, res
->nr_storage_samples
)) {
4289 num_format
= V_008F14_IMG_FMASK_8_2_1
;
4292 num_format
= V_008F14_IMG_FMASK_8_2_2
;
4295 num_format
= V_008F14_IMG_FMASK_8_4_1
;
4298 num_format
= V_008F14_IMG_FMASK_8_4_2
;
4301 num_format
= V_008F14_IMG_FMASK_8_4_4
;
4304 num_format
= V_008F14_IMG_FMASK_8_8_1
;
4307 num_format
= V_008F14_IMG_FMASK_16_8_2
;
4310 num_format
= V_008F14_IMG_FMASK_32_8_4
;
4313 num_format
= V_008F14_IMG_FMASK_32_8_8
;
4316 num_format
= V_008F14_IMG_FMASK_16_16_1
;
4319 num_format
= V_008F14_IMG_FMASK_32_16_2
;
4322 num_format
= V_008F14_IMG_FMASK_64_16_4
;
4325 num_format
= V_008F14_IMG_FMASK_64_16_8
;
4328 unreachable("invalid nr_samples");
4331 switch (FMASK(res
->nr_samples
, res
->nr_storage_samples
)) {
4333 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F1
;
4336 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2
;
4339 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F1
;
4342 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F2
;
4345 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4
;
4348 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S8_F1
;
4351 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK16_S8_F2
;
4354 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F4
;
4357 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8
;
4360 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK16_S16_F1
;
4363 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S16_F2
;
4366 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F4
;
4369 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F8
;
4372 unreachable("invalid nr_samples");
4374 num_format
= V_008F14_IMG_NUM_FORMAT_UINT
;
4378 fmask_state
[0] = (va
>> 8) | tex
->surface
.fmask_tile_swizzle
;
4379 fmask_state
[1] = S_008F14_BASE_ADDRESS_HI(va
>> 40) |
4380 S_008F14_DATA_FORMAT(data_format
) |
4381 S_008F14_NUM_FORMAT(num_format
);
4382 fmask_state
[2] = S_008F18_WIDTH(width
- 1) |
4383 S_008F18_HEIGHT(height
- 1);
4384 fmask_state
[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X
) |
4385 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X
) |
4386 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X
) |
4387 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X
) |
4388 S_008F1C_TYPE(si_tex_dim(screen
, tex
, target
, 0));
4390 fmask_state
[5] = S_008F24_BASE_ARRAY(first_layer
);
4394 if (screen
->info
.chip_class
>= GFX9
) {
4395 fmask_state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
);
4396 fmask_state
[4] |= S_008F20_DEPTH(last_layer
) |
4397 S_008F20_PITCH(tex
->surface
.u
.gfx9
.fmask
.epitch
);
4398 fmask_state
[5] |= S_008F24_META_PIPE_ALIGNED(tex
->surface
.u
.gfx9
.cmask
.pipe_aligned
) |
4399 S_008F24_META_RB_ALIGNED(tex
->surface
.u
.gfx9
.cmask
.rb_aligned
);
4401 fmask_state
[3] |= S_008F1C_TILING_INDEX(tex
->surface
.u
.legacy
.fmask
.tiling_index
);
4402 fmask_state
[4] |= S_008F20_DEPTH(depth
- 1) |
4403 S_008F20_PITCH(tex
->surface
.u
.legacy
.fmask
.pitch_in_pixels
- 1);
4404 fmask_state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
4410 * Create a sampler view.
4412 * @param ctx context
4413 * @param texture texture
4414 * @param state sampler view template
4415 * @param width0 width0 override (for compressed textures as int)
4416 * @param height0 height0 override (for compressed textures as int)
4417 * @param force_level set the base address to the level (for compressed textures)
4419 struct pipe_sampler_view
*
4420 si_create_sampler_view_custom(struct pipe_context
*ctx
,
4421 struct pipe_resource
*texture
,
4422 const struct pipe_sampler_view
*state
,
4423 unsigned width0
, unsigned height0
,
4424 unsigned force_level
)
4426 struct si_context
*sctx
= (struct si_context
*)ctx
;
4427 struct si_sampler_view
*view
= CALLOC_STRUCT(si_sampler_view
);
4428 struct si_texture
*tex
= (struct si_texture
*)texture
;
4429 unsigned base_level
, first_level
, last_level
;
4430 unsigned char state_swizzle
[4];
4431 unsigned height
, depth
, width
;
4432 unsigned last_layer
= state
->u
.tex
.last_layer
;
4433 enum pipe_format pipe_format
;
4434 const struct legacy_surf_level
*surflevel
;
4439 /* initialize base object */
4440 view
->base
= *state
;
4441 view
->base
.texture
= NULL
;
4442 view
->base
.reference
.count
= 1;
4443 view
->base
.context
= ctx
;
4446 pipe_resource_reference(&view
->base
.texture
, texture
);
4448 if (state
->format
== PIPE_FORMAT_X24S8_UINT
||
4449 state
->format
== PIPE_FORMAT_S8X24_UINT
||
4450 state
->format
== PIPE_FORMAT_X32_S8X24_UINT
||
4451 state
->format
== PIPE_FORMAT_S8_UINT
)
4452 view
->is_stencil_sampler
= true;
4454 /* Buffer resource. */
4455 if (texture
->target
== PIPE_BUFFER
) {
4456 si_make_buffer_descriptor(sctx
->screen
,
4457 si_resource(texture
),
4459 state
->u
.buf
.offset
,
4465 state_swizzle
[0] = state
->swizzle_r
;
4466 state_swizzle
[1] = state
->swizzle_g
;
4467 state_swizzle
[2] = state
->swizzle_b
;
4468 state_swizzle
[3] = state
->swizzle_a
;
4471 first_level
= state
->u
.tex
.first_level
;
4472 last_level
= state
->u
.tex
.last_level
;
4475 depth
= texture
->depth0
;
4477 if (sctx
->chip_class
<= GFX8
&& force_level
) {
4478 assert(force_level
== first_level
&&
4479 force_level
== last_level
);
4480 base_level
= force_level
;
4483 width
= u_minify(width
, force_level
);
4484 height
= u_minify(height
, force_level
);
4485 depth
= u_minify(depth
, force_level
);
4488 /* This is not needed if state trackers set last_layer correctly. */
4489 if (state
->target
== PIPE_TEXTURE_1D
||
4490 state
->target
== PIPE_TEXTURE_2D
||
4491 state
->target
== PIPE_TEXTURE_RECT
||
4492 state
->target
== PIPE_TEXTURE_CUBE
)
4493 last_layer
= state
->u
.tex
.first_layer
;
4495 /* Texturing with separate depth and stencil. */
4496 pipe_format
= state
->format
;
4498 /* Depth/stencil texturing sometimes needs separate texture. */
4499 if (tex
->is_depth
&& !si_can_sample_zs(tex
, view
->is_stencil_sampler
)) {
4500 if (!tex
->flushed_depth_texture
&&
4501 !si_init_flushed_depth_texture(ctx
, texture
)) {
4502 pipe_resource_reference(&view
->base
.texture
, NULL
);
4507 assert(tex
->flushed_depth_texture
);
4509 /* Override format for the case where the flushed texture
4510 * contains only Z or only S.
4512 if (tex
->flushed_depth_texture
->buffer
.b
.b
.format
!= tex
->buffer
.b
.b
.format
)
4513 pipe_format
= tex
->flushed_depth_texture
->buffer
.b
.b
.format
;
4515 tex
= tex
->flushed_depth_texture
;
4518 surflevel
= tex
->surface
.u
.legacy
.level
;
4520 if (tex
->db_compatible
) {
4521 if (!view
->is_stencil_sampler
)
4522 pipe_format
= tex
->db_render_format
;
4524 switch (pipe_format
) {
4525 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
4526 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
4528 case PIPE_FORMAT_X8Z24_UNORM
:
4529 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
4530 /* Z24 is always stored like this for DB
4533 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
4535 case PIPE_FORMAT_X24S8_UINT
:
4536 case PIPE_FORMAT_S8X24_UINT
:
4537 case PIPE_FORMAT_X32_S8X24_UINT
:
4538 pipe_format
= PIPE_FORMAT_S8_UINT
;
4539 surflevel
= tex
->surface
.u
.legacy
.stencil_level
;
4545 view
->dcc_incompatible
=
4546 vi_dcc_formats_are_incompatible(texture
,
4547 state
->u
.tex
.first_level
,
4550 sctx
->screen
->make_texture_descriptor(sctx
->screen
, tex
, true,
4551 state
->target
, pipe_format
, state_swizzle
,
4552 first_level
, last_level
,
4553 state
->u
.tex
.first_layer
, last_layer
,
4554 width
, height
, depth
,
4555 view
->state
, view
->fmask_state
);
4557 const struct util_format_description
*desc
= util_format_description(pipe_format
);
4558 view
->is_integer
= false;
4560 for (unsigned i
= 0; i
< desc
->nr_channels
; ++i
) {
4561 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_VOID
)
4564 /* Whether the number format is {U,S}{SCALED,INT} */
4566 (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
||
4567 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) &&
4568 (desc
->channel
[i
].pure_integer
|| !desc
->channel
[i
].normalized
);
4572 view
->base_level_info
= &surflevel
[base_level
];
4573 view
->base_level
= base_level
;
4574 view
->block_width
= util_format_get_blockwidth(pipe_format
);
4578 static struct pipe_sampler_view
*
4579 si_create_sampler_view(struct pipe_context
*ctx
,
4580 struct pipe_resource
*texture
,
4581 const struct pipe_sampler_view
*state
)
4583 return si_create_sampler_view_custom(ctx
, texture
, state
,
4584 texture
? texture
->width0
: 0,
4585 texture
? texture
->height0
: 0, 0);
4588 static void si_sampler_view_destroy(struct pipe_context
*ctx
,
4589 struct pipe_sampler_view
*state
)
4591 struct si_sampler_view
*view
= (struct si_sampler_view
*)state
;
4593 pipe_resource_reference(&state
->texture
, NULL
);
4597 static bool wrap_mode_uses_border_color(unsigned wrap
, bool linear_filter
)
4599 return wrap
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
||
4600 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
||
4602 (wrap
== PIPE_TEX_WRAP_CLAMP
||
4603 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP
));
4606 static uint32_t si_translate_border_color(struct si_context
*sctx
,
4607 const struct pipe_sampler_state
*state
,
4608 const union pipe_color_union
*color
,
4611 bool linear_filter
= state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
||
4612 state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
;
4614 if (!wrap_mode_uses_border_color(state
->wrap_s
, linear_filter
) &&
4615 !wrap_mode_uses_border_color(state
->wrap_t
, linear_filter
) &&
4616 !wrap_mode_uses_border_color(state
->wrap_r
, linear_filter
))
4617 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
);
4619 #define simple_border_types(elt) \
4621 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4622 color->elt[2] == 0 && color->elt[3] == 0) \
4623 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK); \
4624 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4625 color->elt[2] == 0 && color->elt[3] == 1) \
4626 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK); \
4627 if (color->elt[0] == 1 && color->elt[1] == 1 && \
4628 color->elt[2] == 1 && color->elt[3] == 1) \
4629 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE); \
4633 simple_border_types(ui
);
4635 simple_border_types(f
);
4637 #undef simple_border_types
4641 /* Check if the border has been uploaded already. */
4642 for (i
= 0; i
< sctx
->border_color_count
; i
++)
4643 if (memcmp(&sctx
->border_color_table
[i
], color
,
4644 sizeof(*color
)) == 0)
4647 if (i
>= SI_MAX_BORDER_COLORS
) {
4648 /* Getting 4096 unique border colors is very unlikely. */
4649 fprintf(stderr
, "radeonsi: The border color table is full. "
4650 "Any new border colors will be just black. "
4651 "Please file a bug.\n");
4652 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
);
4655 if (i
== sctx
->border_color_count
) {
4656 /* Upload a new border color. */
4657 memcpy(&sctx
->border_color_table
[i
], color
,
4659 util_memcpy_cpu_to_le32(&sctx
->border_color_map
[i
],
4660 color
, sizeof(*color
));
4661 sctx
->border_color_count
++;
4664 return S_008F3C_BORDER_COLOR_PTR(i
) |
4665 S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER
);
4668 static inline int S_FIXED(float value
, unsigned frac_bits
)
4670 return value
* (1 << frac_bits
);
4673 static inline unsigned si_tex_filter(unsigned filter
, unsigned max_aniso
)
4675 if (filter
== PIPE_TEX_FILTER_LINEAR
)
4676 return max_aniso
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
4677 : V_008F38_SQ_TEX_XY_FILTER_BILINEAR
;
4679 return max_aniso
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
4680 : V_008F38_SQ_TEX_XY_FILTER_POINT
;
4683 static inline unsigned si_tex_aniso_filter(unsigned filter
)
4696 static void *si_create_sampler_state(struct pipe_context
*ctx
,
4697 const struct pipe_sampler_state
*state
)
4699 struct si_context
*sctx
= (struct si_context
*)ctx
;
4700 struct si_screen
*sscreen
= sctx
->screen
;
4701 struct si_sampler_state
*rstate
= CALLOC_STRUCT(si_sampler_state
);
4702 unsigned max_aniso
= sscreen
->force_aniso
>= 0 ? sscreen
->force_aniso
4703 : state
->max_anisotropy
;
4704 unsigned max_aniso_ratio
= si_tex_aniso_filter(max_aniso
);
4705 union pipe_color_union clamped_border_color
;
4712 rstate
->magic
= SI_SAMPLER_STATE_MAGIC
;
4714 rstate
->val
[0] = (S_008F30_CLAMP_X(si_tex_wrap(state
->wrap_s
)) |
4715 S_008F30_CLAMP_Y(si_tex_wrap(state
->wrap_t
)) |
4716 S_008F30_CLAMP_Z(si_tex_wrap(state
->wrap_r
)) |
4717 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio
) |
4718 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state
->compare_func
)) |
4719 S_008F30_FORCE_UNNORMALIZED(!state
->normalized_coords
) |
4720 S_008F30_ANISO_THRESHOLD(max_aniso_ratio
>> 1) |
4721 S_008F30_ANISO_BIAS(max_aniso_ratio
) |
4722 S_008F30_DISABLE_CUBE_WRAP(!state
->seamless_cube_map
) |
4723 S_008F30_COMPAT_MODE(sctx
->chip_class
== GFX8
|| sctx
->chip_class
== GFX9
));
4724 rstate
->val
[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 8)) |
4725 S_008F34_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 8)) |
4726 S_008F34_PERF_MIP(max_aniso_ratio
? max_aniso_ratio
+ 6 : 0));
4727 rstate
->val
[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 8)) |
4728 S_008F38_XY_MAG_FILTER(si_tex_filter(state
->mag_img_filter
, max_aniso
)) |
4729 S_008F38_XY_MIN_FILTER(si_tex_filter(state
->min_img_filter
, max_aniso
)) |
4730 S_008F38_MIP_FILTER(si_tex_mipfilter(state
->min_mip_filter
)) |
4731 S_008F38_MIP_POINT_PRECLAMP(0));
4732 rstate
->val
[3] = si_translate_border_color(sctx
, state
, &state
->border_color
, false);
4734 if (sscreen
->info
.chip_class
>= GFX10
) {
4735 rstate
->val
[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
4737 rstate
->val
[2] |= S_008F38_DISABLE_LSB_CEIL(sctx
->chip_class
<= GFX8
) |
4738 S_008F38_FILTER_PREC_FIX(1) |
4739 S_008F38_ANISO_OVERRIDE_GFX6(sctx
->chip_class
>= GFX8
);
4742 /* Create sampler resource for integer textures. */
4743 memcpy(rstate
->integer_val
, rstate
->val
, sizeof(rstate
->val
));
4744 rstate
->integer_val
[3] = si_translate_border_color(sctx
, state
, &state
->border_color
, true);
4746 /* Create sampler resource for upgraded depth textures. */
4747 memcpy(rstate
->upgraded_depth_val
, rstate
->val
, sizeof(rstate
->val
));
4749 for (unsigned i
= 0; i
< 4; ++i
) {
4750 /* Use channel 0 on purpose, so that we can use OPAQUE_WHITE
4751 * when the border color is 1.0. */
4752 clamped_border_color
.f
[i
] = CLAMP(state
->border_color
.f
[0], 0, 1);
4755 if (memcmp(&state
->border_color
, &clamped_border_color
, sizeof(clamped_border_color
)) == 0) {
4756 if (sscreen
->info
.chip_class
<= GFX9
)
4757 rstate
->upgraded_depth_val
[3] |= S_008F3C_UPGRADED_DEPTH(1);
4759 rstate
->upgraded_depth_val
[3] =
4760 si_translate_border_color(sctx
, state
, &clamped_border_color
, false);
4766 static void si_set_sample_mask(struct pipe_context
*ctx
, unsigned sample_mask
)
4768 struct si_context
*sctx
= (struct si_context
*)ctx
;
4770 if (sctx
->sample_mask
== (uint16_t)sample_mask
)
4773 sctx
->sample_mask
= sample_mask
;
4774 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.sample_mask
);
4777 static void si_emit_sample_mask(struct si_context
*sctx
)
4779 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
4780 unsigned mask
= sctx
->sample_mask
;
4782 /* Needed for line and polygon smoothing as well as for the Polaris
4783 * small primitive filter. We expect the state tracker to take care of
4786 assert(mask
== 0xffff || sctx
->framebuffer
.nr_samples
> 1 ||
4787 (mask
& 1 && sctx
->blitter
->running
));
4789 radeon_set_context_reg_seq(cs
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
4790 radeon_emit(cs
, mask
| (mask
<< 16));
4791 radeon_emit(cs
, mask
| (mask
<< 16));
4794 static void si_delete_sampler_state(struct pipe_context
*ctx
, void *state
)
4797 struct si_sampler_state
*s
= state
;
4799 assert(s
->magic
== SI_SAMPLER_STATE_MAGIC
);
4806 * Vertex elements & buffers
4809 struct si_fast_udiv_info32
4810 si_compute_fast_udiv_info32(uint32_t D
, unsigned num_bits
)
4812 struct util_fast_udiv_info info
=
4813 util_compute_fast_udiv_info(D
, num_bits
, 32);
4815 struct si_fast_udiv_info32 result
= {
4824 static void *si_create_vertex_elements(struct pipe_context
*ctx
,
4826 const struct pipe_vertex_element
*elements
)
4828 struct si_screen
*sscreen
= (struct si_screen
*)ctx
->screen
;
4829 struct si_vertex_elements
*v
= CALLOC_STRUCT(si_vertex_elements
);
4830 bool used
[SI_NUM_VERTEX_BUFFERS
] = {};
4831 struct si_fast_udiv_info32 divisor_factors
[SI_MAX_ATTRIBS
] = {};
4832 STATIC_ASSERT(sizeof(struct si_fast_udiv_info32
) == 16);
4833 STATIC_ASSERT(sizeof(divisor_factors
[0].multiplier
) == 4);
4834 STATIC_ASSERT(sizeof(divisor_factors
[0].pre_shift
) == 4);
4835 STATIC_ASSERT(sizeof(divisor_factors
[0].post_shift
) == 4);
4836 STATIC_ASSERT(sizeof(divisor_factors
[0].increment
) == 4);
4839 assert(count
<= SI_MAX_ATTRIBS
);
4844 v
->desc_list_byte_size
= align(count
* 16, SI_CPDMA_ALIGNMENT
);
4846 for (i
= 0; i
< count
; ++i
) {
4847 const struct util_format_description
*desc
;
4848 const struct util_format_channel_description
*channel
;
4850 unsigned vbo_index
= elements
[i
].vertex_buffer_index
;
4852 if (vbo_index
>= SI_NUM_VERTEX_BUFFERS
) {
4857 unsigned instance_divisor
= elements
[i
].instance_divisor
;
4858 if (instance_divisor
) {
4859 v
->uses_instance_divisors
= true;
4861 if (instance_divisor
== 1) {
4862 v
->instance_divisor_is_one
|= 1u << i
;
4864 v
->instance_divisor_is_fetched
|= 1u << i
;
4865 divisor_factors
[i
] =
4866 si_compute_fast_udiv_info32(instance_divisor
, 32);
4870 if (!used
[vbo_index
]) {
4871 v
->first_vb_use_mask
|= 1 << i
;
4872 used
[vbo_index
] = true;
4875 desc
= util_format_description(elements
[i
].src_format
);
4876 first_non_void
= util_format_get_first_non_void_channel(elements
[i
].src_format
);
4877 channel
= first_non_void
>= 0 ? &desc
->channel
[first_non_void
] : NULL
;
4879 v
->format_size
[i
] = desc
->block
.bits
/ 8;
4880 v
->src_offset
[i
] = elements
[i
].src_offset
;
4881 v
->vertex_buffer_index
[i
] = vbo_index
;
4883 bool always_fix
= false;
4884 union si_vs_fix_fetch fix_fetch
;
4885 unsigned log_hw_load_size
; /* the load element size as seen by the hardware */
4888 log_hw_load_size
= MIN2(2, util_logbase2(desc
->block
.bits
) - 3);
4891 switch (channel
->type
) {
4892 case UTIL_FORMAT_TYPE_FLOAT
: fix_fetch
.u
.format
= AC_FETCH_FORMAT_FLOAT
; break;
4893 case UTIL_FORMAT_TYPE_FIXED
: fix_fetch
.u
.format
= AC_FETCH_FORMAT_FIXED
; break;
4894 case UTIL_FORMAT_TYPE_SIGNED
: {
4895 if (channel
->pure_integer
)
4896 fix_fetch
.u
.format
= AC_FETCH_FORMAT_SINT
;
4897 else if (channel
->normalized
)
4898 fix_fetch
.u
.format
= AC_FETCH_FORMAT_SNORM
;
4900 fix_fetch
.u
.format
= AC_FETCH_FORMAT_SSCALED
;
4903 case UTIL_FORMAT_TYPE_UNSIGNED
: {
4904 if (channel
->pure_integer
)
4905 fix_fetch
.u
.format
= AC_FETCH_FORMAT_UINT
;
4906 else if (channel
->normalized
)
4907 fix_fetch
.u
.format
= AC_FETCH_FORMAT_UNORM
;
4909 fix_fetch
.u
.format
= AC_FETCH_FORMAT_USCALED
;
4912 default: unreachable("bad format type");
4915 switch (elements
[i
].src_format
) {
4916 case PIPE_FORMAT_R11G11B10_FLOAT
: fix_fetch
.u
.format
= AC_FETCH_FORMAT_FLOAT
; break;
4917 default: unreachable("bad other format");
4921 if (desc
->channel
[0].size
== 10) {
4922 fix_fetch
.u
.log_size
= 3; /* special encoding for 2_10_10_10 */
4923 log_hw_load_size
= 2;
4925 /* The hardware always treats the 2-bit alpha channel as
4926 * unsigned, so a shader workaround is needed. The affected
4927 * chips are GFX8 and older except Stoney (GFX8.1).
4929 always_fix
= sscreen
->info
.chip_class
<= GFX8
&&
4930 sscreen
->info
.family
!= CHIP_STONEY
&&
4931 channel
->type
== UTIL_FORMAT_TYPE_SIGNED
;
4932 } else if (elements
[i
].src_format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
4933 fix_fetch
.u
.log_size
= 3; /* special encoding */
4934 fix_fetch
.u
.format
= AC_FETCH_FORMAT_FIXED
;
4935 log_hw_load_size
= 2;
4937 fix_fetch
.u
.log_size
= util_logbase2(channel
->size
) - 3;
4938 fix_fetch
.u
.num_channels_m1
= desc
->nr_channels
- 1;
4941 * - doubles (multiple loads + truncate to float)
4942 * - 32-bit requiring a conversion
4945 (fix_fetch
.u
.log_size
== 3) ||
4946 (fix_fetch
.u
.log_size
== 2 &&
4947 fix_fetch
.u
.format
!= AC_FETCH_FORMAT_FLOAT
&&
4948 fix_fetch
.u
.format
!= AC_FETCH_FORMAT_UINT
&&
4949 fix_fetch
.u
.format
!= AC_FETCH_FORMAT_SINT
);
4951 /* Also fixup 8_8_8 and 16_16_16. */
4952 if (desc
->nr_channels
== 3 && fix_fetch
.u
.log_size
<= 1) {
4954 log_hw_load_size
= fix_fetch
.u
.log_size
;
4958 if (desc
->swizzle
[0] != PIPE_SWIZZLE_X
) {
4959 assert(desc
->swizzle
[0] == PIPE_SWIZZLE_Z
&&
4960 (desc
->swizzle
[2] == PIPE_SWIZZLE_X
|| desc
->swizzle
[2] == PIPE_SWIZZLE_0
));
4961 fix_fetch
.u
.reverse
= 1;
4964 /* Force the workaround for unaligned access here already if the
4965 * offset relative to the vertex buffer base is unaligned.
4967 * There is a theoretical case in which this is too conservative:
4968 * if the vertex buffer's offset is also unaligned in just the
4969 * right way, we end up with an aligned address after all.
4970 * However, this case should be extremely rare in practice (it
4971 * won't happen in well-behaved applications), and taking it
4972 * into account would complicate the fast path (where everything
4973 * is nicely aligned).
4975 bool check_alignment
= log_hw_load_size
>= 1 && sscreen
->info
.chip_class
== GFX6
;
4976 bool opencode
= sscreen
->options
.vs_fetch_always_opencode
;
4978 if (check_alignment
&&
4979 (elements
[i
].src_offset
& ((1 << log_hw_load_size
) - 1)) != 0)
4982 if (always_fix
|| check_alignment
|| opencode
)
4983 v
->fix_fetch
[i
] = fix_fetch
.bits
;
4986 v
->fix_fetch_opencode
|= 1 << i
;
4987 if (opencode
|| always_fix
)
4988 v
->fix_fetch_always
|= 1 << i
;
4990 if (check_alignment
&& !opencode
) {
4991 assert(log_hw_load_size
== 1 || log_hw_load_size
== 2);
4993 v
->fix_fetch_unaligned
|= 1 << i
;
4994 v
->hw_load_is_dword
|= (log_hw_load_size
- 1) << i
;
4995 v
->vb_alignment_check_mask
|= 1 << vbo_index
;
4998 v
->rsrc_word3
[i
] = S_008F0C_DST_SEL_X(si_map_swizzle(desc
->swizzle
[0])) |
4999 S_008F0C_DST_SEL_Y(si_map_swizzle(desc
->swizzle
[1])) |
5000 S_008F0C_DST_SEL_Z(si_map_swizzle(desc
->swizzle
[2])) |
5001 S_008F0C_DST_SEL_W(si_map_swizzle(desc
->swizzle
[3]));
5003 if (sscreen
->info
.chip_class
>= GFX10
) {
5004 const struct gfx10_format
*fmt
=
5005 &gfx10_format_table
[elements
[i
].src_format
];
5006 assert(fmt
->img_format
!= 0 && fmt
->img_format
< 128);
5007 v
->rsrc_word3
[i
] |= S_008F0C_FORMAT(fmt
->img_format
) |
5008 S_008F0C_RESOURCE_LEVEL(1);
5010 unsigned data_format
, num_format
;
5011 data_format
= si_translate_buffer_dataformat(ctx
->screen
, desc
, first_non_void
);
5012 num_format
= si_translate_buffer_numformat(ctx
->screen
, desc
, first_non_void
);
5013 v
->rsrc_word3
[i
] |= S_008F0C_NUM_FORMAT(num_format
) |
5014 S_008F0C_DATA_FORMAT(data_format
);
5018 if (v
->instance_divisor_is_fetched
) {
5019 unsigned num_divisors
= util_last_bit(v
->instance_divisor_is_fetched
);
5021 v
->instance_divisor_factor_buffer
=
5022 (struct si_resource
*)
5023 pipe_buffer_create(&sscreen
->b
, 0, PIPE_USAGE_DEFAULT
,
5024 num_divisors
* sizeof(divisor_factors
[0]));
5025 if (!v
->instance_divisor_factor_buffer
) {
5029 void *map
= sscreen
->ws
->buffer_map(v
->instance_divisor_factor_buffer
->buf
,
5030 NULL
, PIPE_TRANSFER_WRITE
);
5031 memcpy(map
, divisor_factors
, num_divisors
* sizeof(divisor_factors
[0]));
5036 static void si_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
5038 struct si_context
*sctx
= (struct si_context
*)ctx
;
5039 struct si_vertex_elements
*old
= sctx
->vertex_elements
;
5040 struct si_vertex_elements
*v
= (struct si_vertex_elements
*)state
;
5042 sctx
->vertex_elements
= v
;
5043 sctx
->vertex_buffers_dirty
= true;
5047 old
->count
!= v
->count
||
5048 old
->uses_instance_divisors
!= v
->uses_instance_divisors
||
5049 /* we don't check which divisors changed */
5050 v
->uses_instance_divisors
||
5051 (old
->vb_alignment_check_mask
^ v
->vb_alignment_check_mask
) & sctx
->vertex_buffer_unaligned
||
5052 ((v
->vb_alignment_check_mask
& sctx
->vertex_buffer_unaligned
) &&
5053 memcmp(old
->vertex_buffer_index
, v
->vertex_buffer_index
,
5054 sizeof(v
->vertex_buffer_index
[0]) * v
->count
)) ||
5055 /* fix_fetch_{always,opencode,unaligned} and hw_load_is_dword are
5056 * functions of fix_fetch and the src_offset alignment.
5057 * If they change and fix_fetch doesn't, it must be due to different
5058 * src_offset alignment, which is reflected in fix_fetch_opencode. */
5059 old
->fix_fetch_opencode
!= v
->fix_fetch_opencode
||
5060 memcmp(old
->fix_fetch
, v
->fix_fetch
, sizeof(v
->fix_fetch
[0]) * v
->count
)))
5061 sctx
->do_update_shaders
= true;
5063 if (v
&& v
->instance_divisor_is_fetched
) {
5064 struct pipe_constant_buffer cb
;
5066 cb
.buffer
= &v
->instance_divisor_factor_buffer
->b
.b
;
5067 cb
.user_buffer
= NULL
;
5068 cb
.buffer_offset
= 0;
5069 cb
.buffer_size
= 0xffffffff;
5070 si_set_rw_buffer(sctx
, SI_VS_CONST_INSTANCE_DIVISORS
, &cb
);
5074 static void si_delete_vertex_element(struct pipe_context
*ctx
, void *state
)
5076 struct si_context
*sctx
= (struct si_context
*)ctx
;
5077 struct si_vertex_elements
*v
= (struct si_vertex_elements
*)state
;
5079 if (sctx
->vertex_elements
== state
)
5080 sctx
->vertex_elements
= NULL
;
5081 si_resource_reference(&v
->instance_divisor_factor_buffer
, NULL
);
5085 static void si_set_vertex_buffers(struct pipe_context
*ctx
,
5086 unsigned start_slot
, unsigned count
,
5087 const struct pipe_vertex_buffer
*buffers
)
5089 struct si_context
*sctx
= (struct si_context
*)ctx
;
5090 struct pipe_vertex_buffer
*dst
= sctx
->vertex_buffer
+ start_slot
;
5091 uint32_t orig_unaligned
= sctx
->vertex_buffer_unaligned
;
5092 uint32_t unaligned
= orig_unaligned
;
5095 assert(start_slot
+ count
<= ARRAY_SIZE(sctx
->vertex_buffer
));
5098 for (i
= 0; i
< count
; i
++) {
5099 const struct pipe_vertex_buffer
*src
= buffers
+ i
;
5100 struct pipe_vertex_buffer
*dsti
= dst
+ i
;
5101 struct pipe_resource
*buf
= src
->buffer
.resource
;
5103 pipe_resource_reference(&dsti
->buffer
.resource
, buf
);
5104 dsti
->buffer_offset
= src
->buffer_offset
;
5105 dsti
->stride
= src
->stride
;
5106 if (dsti
->buffer_offset
& 3 || dsti
->stride
& 3)
5107 unaligned
|= 1 << (start_slot
+ i
);
5109 unaligned
&= ~(1 << (start_slot
+ i
));
5111 si_context_add_resource_size(sctx
, buf
);
5113 si_resource(buf
)->bind_history
|= PIPE_BIND_VERTEX_BUFFER
;
5116 for (i
= 0; i
< count
; i
++) {
5117 pipe_resource_reference(&dst
[i
].buffer
.resource
, NULL
);
5119 unaligned
&= ~u_bit_consecutive(start_slot
, count
);
5121 sctx
->vertex_buffers_dirty
= true;
5122 sctx
->vertex_buffer_unaligned
= unaligned
;
5124 /* Check whether alignment may have changed in a way that requires
5125 * shader changes. This check is conservative: a vertex buffer can only
5126 * trigger a shader change if the misalignment amount changes (e.g.
5127 * from byte-aligned to short-aligned), but we only keep track of
5128 * whether buffers are at least dword-aligned, since that should always
5129 * be the case in well-behaved applications anyway.
5131 if (sctx
->vertex_elements
&&
5132 (sctx
->vertex_elements
->vb_alignment_check_mask
&
5133 (unaligned
| orig_unaligned
) & u_bit_consecutive(start_slot
, count
)))
5134 sctx
->do_update_shaders
= true;
5141 static void si_set_tess_state(struct pipe_context
*ctx
,
5142 const float default_outer_level
[4],
5143 const float default_inner_level
[2])
5145 struct si_context
*sctx
= (struct si_context
*)ctx
;
5146 struct pipe_constant_buffer cb
;
5149 memcpy(array
, default_outer_level
, sizeof(float) * 4);
5150 memcpy(array
+4, default_inner_level
, sizeof(float) * 2);
5153 cb
.user_buffer
= NULL
;
5154 cb
.buffer_size
= sizeof(array
);
5156 si_upload_const_buffer(sctx
, (struct si_resource
**)&cb
.buffer
,
5157 (void*)array
, sizeof(array
),
5160 si_set_rw_buffer(sctx
, SI_HS_CONST_DEFAULT_TESS_LEVELS
, &cb
);
5161 pipe_resource_reference(&cb
.buffer
, NULL
);
5164 static void si_texture_barrier(struct pipe_context
*ctx
, unsigned flags
)
5166 struct si_context
*sctx
= (struct si_context
*)ctx
;
5168 si_update_fb_dirtiness_after_rendering(sctx
);
5170 /* Multisample surfaces are flushed in si_decompress_textures. */
5171 if (sctx
->framebuffer
.uncompressed_cb_mask
) {
5172 si_make_CB_shader_coherent(sctx
, sctx
->framebuffer
.nr_samples
,
5173 sctx
->framebuffer
.CB_has_shader_readable_metadata
,
5174 sctx
->framebuffer
.all_DCC_pipe_aligned
);
5178 /* This only ensures coherency for shader image/buffer stores. */
5179 static void si_memory_barrier(struct pipe_context
*ctx
, unsigned flags
)
5181 struct si_context
*sctx
= (struct si_context
*)ctx
;
5183 if (!(flags
& ~PIPE_BARRIER_UPDATE
))
5186 /* Subsequent commands must wait for all shader invocations to
5188 sctx
->flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
|
5189 SI_CONTEXT_CS_PARTIAL_FLUSH
;
5191 if (flags
& PIPE_BARRIER_CONSTANT_BUFFER
)
5192 sctx
->flags
|= SI_CONTEXT_INV_SCACHE
|
5193 SI_CONTEXT_INV_VCACHE
;
5195 if (flags
& (PIPE_BARRIER_VERTEX_BUFFER
|
5196 PIPE_BARRIER_SHADER_BUFFER
|
5197 PIPE_BARRIER_TEXTURE
|
5198 PIPE_BARRIER_IMAGE
|
5199 PIPE_BARRIER_STREAMOUT_BUFFER
|
5200 PIPE_BARRIER_GLOBAL_BUFFER
)) {
5201 /* As far as I can tell, L1 contents are written back to L2
5202 * automatically at end of shader, but the contents of other
5203 * L1 caches might still be stale. */
5204 sctx
->flags
|= SI_CONTEXT_INV_VCACHE
;
5207 if (flags
& PIPE_BARRIER_INDEX_BUFFER
) {
5208 /* Indices are read through TC L2 since GFX8.
5211 if (sctx
->screen
->info
.chip_class
<= GFX7
)
5212 sctx
->flags
|= SI_CONTEXT_WB_L2
;
5215 /* MSAA color, any depth and any stencil are flushed in
5216 * si_decompress_textures when needed.
5218 if (flags
& PIPE_BARRIER_FRAMEBUFFER
&&
5219 sctx
->framebuffer
.uncompressed_cb_mask
) {
5220 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_CB
;
5222 if (sctx
->chip_class
<= GFX8
)
5223 sctx
->flags
|= SI_CONTEXT_WB_L2
;
5226 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
5227 if (sctx
->screen
->info
.chip_class
<= GFX8
&&
5228 flags
& PIPE_BARRIER_INDIRECT_BUFFER
)
5229 sctx
->flags
|= SI_CONTEXT_WB_L2
;
5232 static void *si_create_blend_custom(struct si_context
*sctx
, unsigned mode
)
5234 struct pipe_blend_state blend
;
5236 memset(&blend
, 0, sizeof(blend
));
5237 blend
.independent_blend_enable
= true;
5238 blend
.rt
[0].colormask
= 0xf;
5239 return si_create_blend_state_mode(&sctx
->b
, &blend
, mode
);
5242 static void si_init_config(struct si_context
*sctx
);
5244 void si_init_state_compute_functions(struct si_context
*sctx
)
5246 sctx
->b
.create_sampler_state
= si_create_sampler_state
;
5247 sctx
->b
.delete_sampler_state
= si_delete_sampler_state
;
5248 sctx
->b
.create_sampler_view
= si_create_sampler_view
;
5249 sctx
->b
.sampler_view_destroy
= si_sampler_view_destroy
;
5250 sctx
->b
.memory_barrier
= si_memory_barrier
;
5253 void si_init_state_functions(struct si_context
*sctx
)
5255 sctx
->atoms
.s
.framebuffer
.emit
= si_emit_framebuffer_state
;
5256 sctx
->atoms
.s
.msaa_sample_locs
.emit
= si_emit_msaa_sample_locs
;
5257 sctx
->atoms
.s
.db_render_state
.emit
= si_emit_db_render_state
;
5258 sctx
->atoms
.s
.dpbb_state
.emit
= si_emit_dpbb_state
;
5259 sctx
->atoms
.s
.msaa_config
.emit
= si_emit_msaa_config
;
5260 sctx
->atoms
.s
.sample_mask
.emit
= si_emit_sample_mask
;
5261 sctx
->atoms
.s
.cb_render_state
.emit
= si_emit_cb_render_state
;
5262 sctx
->atoms
.s
.blend_color
.emit
= si_emit_blend_color
;
5263 sctx
->atoms
.s
.clip_regs
.emit
= si_emit_clip_regs
;
5264 sctx
->atoms
.s
.clip_state
.emit
= si_emit_clip_state
;
5265 sctx
->atoms
.s
.stencil_ref
.emit
= si_emit_stencil_ref
;
5267 sctx
->b
.create_blend_state
= si_create_blend_state
;
5268 sctx
->b
.bind_blend_state
= si_bind_blend_state
;
5269 sctx
->b
.delete_blend_state
= si_delete_blend_state
;
5270 sctx
->b
.set_blend_color
= si_set_blend_color
;
5272 sctx
->b
.create_rasterizer_state
= si_create_rs_state
;
5273 sctx
->b
.bind_rasterizer_state
= si_bind_rs_state
;
5274 sctx
->b
.delete_rasterizer_state
= si_delete_rs_state
;
5276 sctx
->b
.create_depth_stencil_alpha_state
= si_create_dsa_state
;
5277 sctx
->b
.bind_depth_stencil_alpha_state
= si_bind_dsa_state
;
5278 sctx
->b
.delete_depth_stencil_alpha_state
= si_delete_dsa_state
;
5280 sctx
->custom_dsa_flush
= si_create_db_flush_dsa(sctx
);
5281 sctx
->custom_blend_resolve
= si_create_blend_custom(sctx
, V_028808_CB_RESOLVE
);
5282 sctx
->custom_blend_fmask_decompress
= si_create_blend_custom(sctx
, V_028808_CB_FMASK_DECOMPRESS
);
5283 sctx
->custom_blend_eliminate_fastclear
= si_create_blend_custom(sctx
, V_028808_CB_ELIMINATE_FAST_CLEAR
);
5284 sctx
->custom_blend_dcc_decompress
= si_create_blend_custom(sctx
, V_028808_CB_DCC_DECOMPRESS
);
5286 sctx
->b
.set_clip_state
= si_set_clip_state
;
5287 sctx
->b
.set_stencil_ref
= si_set_stencil_ref
;
5289 sctx
->b
.set_framebuffer_state
= si_set_framebuffer_state
;
5291 sctx
->b
.set_sample_mask
= si_set_sample_mask
;
5293 sctx
->b
.create_vertex_elements_state
= si_create_vertex_elements
;
5294 sctx
->b
.bind_vertex_elements_state
= si_bind_vertex_elements
;
5295 sctx
->b
.delete_vertex_elements_state
= si_delete_vertex_element
;
5296 sctx
->b
.set_vertex_buffers
= si_set_vertex_buffers
;
5298 sctx
->b
.texture_barrier
= si_texture_barrier
;
5299 sctx
->b
.set_min_samples
= si_set_min_samples
;
5300 sctx
->b
.set_tess_state
= si_set_tess_state
;
5302 sctx
->b
.set_active_query_state
= si_set_active_query_state
;
5304 si_init_config(sctx
);
5307 void si_init_screen_state_functions(struct si_screen
*sscreen
)
5309 sscreen
->b
.is_format_supported
= si_is_format_supported
;
5311 if (sscreen
->info
.chip_class
>= GFX10
) {
5312 sscreen
->make_texture_descriptor
= gfx10_make_texture_descriptor
;
5314 sscreen
->make_texture_descriptor
= si_make_texture_descriptor
;
5318 static void si_set_grbm_gfx_index(struct si_context
*sctx
,
5319 struct si_pm4_state
*pm4
, unsigned value
)
5321 unsigned reg
= sctx
->chip_class
>= GFX7
? R_030800_GRBM_GFX_INDEX
:
5322 R_00802C_GRBM_GFX_INDEX
;
5323 si_pm4_set_reg(pm4
, reg
, value
);
5326 static void si_set_grbm_gfx_index_se(struct si_context
*sctx
,
5327 struct si_pm4_state
*pm4
, unsigned se
)
5329 assert(se
== ~0 || se
< sctx
->screen
->info
.max_se
);
5330 si_set_grbm_gfx_index(sctx
, pm4
,
5331 (se
== ~0 ? S_030800_SE_BROADCAST_WRITES(1) :
5332 S_030800_SE_INDEX(se
)) |
5333 S_030800_SH_BROADCAST_WRITES(1) |
5334 S_030800_INSTANCE_BROADCAST_WRITES(1));
5338 si_write_harvested_raster_configs(struct si_context
*sctx
,
5339 struct si_pm4_state
*pm4
,
5340 unsigned raster_config
,
5341 unsigned raster_config_1
)
5343 unsigned num_se
= MAX2(sctx
->screen
->info
.max_se
, 1);
5344 unsigned raster_config_se
[4];
5347 ac_get_harvested_configs(&sctx
->screen
->info
,
5352 for (se
= 0; se
< num_se
; se
++) {
5353 si_set_grbm_gfx_index_se(sctx
, pm4
, se
);
5354 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
, raster_config_se
[se
]);
5356 si_set_grbm_gfx_index(sctx
, pm4
, ~0);
5358 if (sctx
->chip_class
>= GFX7
) {
5359 si_pm4_set_reg(pm4
, R_028354_PA_SC_RASTER_CONFIG_1
, raster_config_1
);
5363 static void si_set_raster_config(struct si_context
*sctx
, struct si_pm4_state
*pm4
)
5365 struct si_screen
*sscreen
= sctx
->screen
;
5366 unsigned num_rb
= MIN2(sscreen
->info
.num_render_backends
, 16);
5367 unsigned rb_mask
= sscreen
->info
.enabled_rb_mask
;
5368 unsigned raster_config
= sscreen
->pa_sc_raster_config
;
5369 unsigned raster_config_1
= sscreen
->pa_sc_raster_config_1
;
5371 if (!rb_mask
|| util_bitcount(rb_mask
) >= num_rb
) {
5372 /* Always use the default config when all backends are enabled
5373 * (or when we failed to determine the enabled backends).
5375 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
,
5377 if (sctx
->chip_class
>= GFX7
)
5378 si_pm4_set_reg(pm4
, R_028354_PA_SC_RASTER_CONFIG_1
,
5381 si_write_harvested_raster_configs(sctx
, pm4
, raster_config
, raster_config_1
);
5385 static void si_init_config(struct si_context
*sctx
)
5387 struct si_screen
*sscreen
= sctx
->screen
;
5388 uint64_t border_color_va
= sctx
->border_color_buffer
->gpu_address
;
5389 bool has_clear_state
= sscreen
->has_clear_state
;
5390 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
5392 /* GFX6, radeon kernel disabled CLEAR_STATE. */
5393 assert(has_clear_state
|| sscreen
->info
.chip_class
== GFX6
||
5394 !sscreen
->info
.is_amdgpu
);
5399 si_pm4_cmd_begin(pm4
, PKT3_CONTEXT_CONTROL
);
5400 si_pm4_cmd_add(pm4
, CONTEXT_CONTROL_LOAD_ENABLE(1));
5401 si_pm4_cmd_add(pm4
, CONTEXT_CONTROL_SHADOW_ENABLE(1));
5402 si_pm4_cmd_end(pm4
, false);
5404 if (has_clear_state
) {
5405 si_pm4_cmd_begin(pm4
, PKT3_CLEAR_STATE
);
5406 si_pm4_cmd_add(pm4
, 0);
5407 si_pm4_cmd_end(pm4
, false);
5410 if (sctx
->chip_class
<= GFX8
)
5411 si_set_raster_config(sctx
, pm4
);
5413 si_pm4_set_reg(pm4
, R_028A18_VGT_HOS_MAX_TESS_LEVEL
, fui(64));
5414 if (!has_clear_state
)
5415 si_pm4_set_reg(pm4
, R_028A1C_VGT_HOS_MIN_TESS_LEVEL
, fui(0));
5417 /* FIXME calculate these values somehow ??? */
5418 if (sctx
->chip_class
<= GFX8
) {
5419 si_pm4_set_reg(pm4
, R_028A54_VGT_GS_PER_ES
, SI_GS_PER_ES
);
5420 si_pm4_set_reg(pm4
, R_028A58_VGT_ES_PER_GS
, 0x40);
5423 if (!has_clear_state
) {
5424 si_pm4_set_reg(pm4
, R_028A5C_VGT_GS_PER_VS
, 0x2);
5425 si_pm4_set_reg(pm4
, R_028A8C_VGT_PRIMITIVEID_RESET
, 0x0);
5426 si_pm4_set_reg(pm4
, R_028B98_VGT_STRMOUT_BUFFER_CONFIG
, 0x0);
5429 si_pm4_set_reg(pm4
, R_028AA0_VGT_INSTANCE_STEP_RATE_0
, 1);
5430 if (!has_clear_state
)
5431 si_pm4_set_reg(pm4
, R_028AB8_VGT_VTX_CNT_EN
, 0x0);
5432 if (sctx
->chip_class
< GFX7
)
5433 si_pm4_set_reg(pm4
, R_008A14_PA_CL_ENHANCE
, S_008A14_NUM_CLIP_SEQ(3) |
5434 S_008A14_CLIP_VTX_REORDER_ENA(1));
5436 /* CLEAR_STATE doesn't clear these correctly on certain generations.
5437 * I don't know why. Deduced by trial and error.
5439 if (sctx
->chip_class
<= GFX7
) {
5440 si_pm4_set_reg(pm4
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
5441 si_pm4_set_reg(pm4
, R_028204_PA_SC_WINDOW_SCISSOR_TL
, S_028204_WINDOW_OFFSET_DISABLE(1));
5442 si_pm4_set_reg(pm4
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, S_028240_WINDOW_OFFSET_DISABLE(1));
5443 si_pm4_set_reg(pm4
, R_028244_PA_SC_GENERIC_SCISSOR_BR
,
5444 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
5445 si_pm4_set_reg(pm4
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 0);
5446 si_pm4_set_reg(pm4
, R_028034_PA_SC_SCREEN_SCISSOR_BR
,
5447 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
5450 if (!has_clear_state
) {
5451 si_pm4_set_reg(pm4
, R_028230_PA_SC_EDGERULE
,
5452 S_028230_ER_TRI(0xA) |
5453 S_028230_ER_POINT(0xA) |
5454 S_028230_ER_RECT(0xA) |
5455 /* Required by DX10_DIAMOND_TEST_ENA: */
5456 S_028230_ER_LINE_LR(0x1A) |
5457 S_028230_ER_LINE_RL(0x26) |
5458 S_028230_ER_LINE_TB(0xA) |
5459 S_028230_ER_LINE_BT(0xA));
5460 si_pm4_set_reg(pm4
, R_028820_PA_CL_NANINF_CNTL
, 0);
5461 si_pm4_set_reg(pm4
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 0x0);
5462 si_pm4_set_reg(pm4
, R_028AC4_DB_SRESULTS_COMPARE_STATE1
, 0x0);
5463 si_pm4_set_reg(pm4
, R_028AC8_DB_PRELOAD_CONTROL
, 0x0);
5464 si_pm4_set_reg(pm4
, R_02800C_DB_RENDER_OVERRIDE
, 0);
5467 if (sctx
->chip_class
>= GFX10
) {
5468 si_pm4_set_reg(pm4
, R_030964_GE_MAX_VTX_INDX
, ~0);
5469 si_pm4_set_reg(pm4
, R_030924_GE_MIN_VTX_INDX
, 0);
5470 si_pm4_set_reg(pm4
, R_030928_GE_INDX_OFFSET
, 0);
5471 } else if (sctx
->chip_class
>= GFX9
) {
5472 si_pm4_set_reg(pm4
, R_030920_VGT_MAX_VTX_INDX
, ~0);
5473 si_pm4_set_reg(pm4
, R_030924_VGT_MIN_VTX_INDX
, 0);
5474 si_pm4_set_reg(pm4
, R_030928_VGT_INDX_OFFSET
, 0);
5476 /* These registers, when written, also overwrite the CLEAR_STATE
5477 * context, so we can't rely on CLEAR_STATE setting them.
5478 * It would be an issue if there was another UMD changing them.
5480 si_pm4_set_reg(pm4
, R_028400_VGT_MAX_VTX_INDX
, ~0);
5481 si_pm4_set_reg(pm4
, R_028404_VGT_MIN_VTX_INDX
, 0);
5482 si_pm4_set_reg(pm4
, R_028408_VGT_INDX_OFFSET
, 0);
5485 if (sctx
->chip_class
>= GFX7
) {
5486 if (sctx
->chip_class
>= GFX10
) {
5487 /* Logical CUs 16 - 31 */
5488 si_pm4_set_reg(pm4
, R_00B404_SPI_SHADER_PGM_RSRC4_HS
,
5489 S_00B404_CU_EN(0xffff));
5490 si_pm4_set_reg(pm4
, R_00B204_SPI_SHADER_PGM_RSRC4_GS
,
5491 S_00B204_CU_EN(0xffff) |
5492 S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(0));
5493 si_pm4_set_reg(pm4
, R_00B104_SPI_SHADER_PGM_RSRC4_VS
,
5494 S_00B104_CU_EN(0xffff));
5495 si_pm4_set_reg(pm4
, R_00B004_SPI_SHADER_PGM_RSRC4_PS
,
5496 S_00B004_CU_EN(0xffff));
5499 if (sctx
->chip_class
>= GFX9
) {
5500 si_pm4_set_reg(pm4
, R_00B41C_SPI_SHADER_PGM_RSRC3_HS
,
5501 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
5503 si_pm4_set_reg(pm4
, R_00B51C_SPI_SHADER_PGM_RSRC3_LS
,
5504 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
5505 si_pm4_set_reg(pm4
, R_00B41C_SPI_SHADER_PGM_RSRC3_HS
,
5506 S_00B41C_WAVE_LIMIT(0x3F));
5507 si_pm4_set_reg(pm4
, R_00B31C_SPI_SHADER_PGM_RSRC3_ES
,
5508 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
5510 /* If this is 0, Bonaire can hang even if GS isn't being used.
5511 * Other chips are unaffected. These are suboptimal values,
5512 * but we don't use on-chip GS.
5514 si_pm4_set_reg(pm4
, R_028A44_VGT_GS_ONCHIP_CNTL
,
5515 S_028A44_ES_VERTS_PER_SUBGRP(64) |
5516 S_028A44_GS_PRIMS_PER_SUBGRP(4));
5518 si_pm4_set_reg(pm4
, R_00B21C_SPI_SHADER_PGM_RSRC3_GS
,
5519 S_00B21C_CU_EN(0xffff) | S_00B21C_WAVE_LIMIT(0x3F));
5521 /* Compute LATE_ALLOC_VS.LIMIT. */
5522 unsigned num_cu_per_sh
= sscreen
->info
.num_good_cu_per_sh
;
5523 unsigned late_alloc_limit
; /* The limit is per SH. */
5525 if (sctx
->family
== CHIP_KABINI
) {
5526 late_alloc_limit
= 0; /* Potential hang on Kabini. */
5527 } else if (num_cu_per_sh
<= 4) {
5528 /* Too few available compute units per SH. Disallowing
5529 * VS to run on one CU could hurt us more than late VS
5530 * allocation would help.
5532 * 2 is the highest safe number that allows us to keep
5535 late_alloc_limit
= 2;
5537 /* This is a good initial value, allowing 1 late_alloc
5538 * wave per SIMD on num_cu - 2.
5540 late_alloc_limit
= (num_cu_per_sh
- 2) * 4;
5543 /* VS can't execute on one CU if the limit is > 2. */
5544 si_pm4_set_reg(pm4
, R_00B118_SPI_SHADER_PGM_RSRC3_VS
,
5545 S_00B118_CU_EN(late_alloc_limit
> 2 ? 0xfffe : 0xffff) |
5546 S_00B118_WAVE_LIMIT(0x3F));
5547 si_pm4_set_reg(pm4
, R_00B11C_SPI_SHADER_LATE_ALLOC_VS
,
5548 S_00B11C_LIMIT(late_alloc_limit
));
5550 si_pm4_set_reg(pm4
, R_00B01C_SPI_SHADER_PGM_RSRC3_PS
,
5551 S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
5554 if (sctx
->chip_class
>= GFX10
) {
5555 /* Break up a pixel wave if it contains deallocs for more than
5556 * half the parameter cache.
5558 * To avoid a deadlock where pixel waves aren't launched
5559 * because they're waiting for more pixels while the frontend
5560 * is stuck waiting for PC space, the maximum allowed value is
5561 * the size of the PC minus the largest possible allocation for
5562 * a single primitive shader subgroup.
5564 si_pm4_set_reg(pm4
, R_028C50_PA_SC_NGG_MODE_CNTL
,
5565 S_028C50_MAX_DEALLOCS_IN_WAVE(512));
5566 si_pm4_set_reg(pm4
, R_028838_PA_CL_NGG_CNTL
, 0); /* TODO edge flags? */
5569 if (sctx
->chip_class
>= GFX8
) {
5570 unsigned vgt_tess_distribution
;
5572 vgt_tess_distribution
=
5573 S_028B50_ACCUM_ISOLINE(32) |
5574 S_028B50_ACCUM_TRI(11) |
5575 S_028B50_ACCUM_QUAD(11) |
5576 S_028B50_DONUT_SPLIT(16);
5578 /* Testing with Unigine Heaven extreme tesselation yielded best results
5579 * with TRAP_SPLIT = 3.
5581 if (sctx
->family
== CHIP_FIJI
||
5582 sctx
->family
>= CHIP_POLARIS10
)
5583 vgt_tess_distribution
|= S_028B50_TRAP_SPLIT(3);
5585 si_pm4_set_reg(pm4
, R_028B50_VGT_TESS_DISTRIBUTION
, vgt_tess_distribution
);
5586 } else if (!has_clear_state
) {
5587 si_pm4_set_reg(pm4
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
, 14);
5588 si_pm4_set_reg(pm4
, R_028C5C_VGT_OUT_DEALLOC_CNTL
, 16);
5591 si_pm4_set_reg(pm4
, R_028080_TA_BC_BASE_ADDR
, border_color_va
>> 8);
5592 if (sctx
->chip_class
>= GFX7
) {
5593 si_pm4_set_reg(pm4
, R_028084_TA_BC_BASE_ADDR_HI
,
5594 S_028084_ADDRESS(border_color_va
>> 40));
5596 si_pm4_add_bo(pm4
, sctx
->border_color_buffer
, RADEON_USAGE_READ
,
5597 RADEON_PRIO_BORDER_COLORS
);
5599 if (sctx
->chip_class
>= GFX9
) {
5600 unsigned num_se
= sscreen
->info
.max_se
;
5601 unsigned pc_lines
= 0;
5602 unsigned max_alloc_count
= 0;
5604 switch (sctx
->family
) {
5623 if (sctx
->chip_class
>= GFX10
) {
5624 max_alloc_count
= pc_lines
/ 3;
5626 max_alloc_count
= MIN2(128, pc_lines
/ (4 * num_se
));
5629 si_pm4_set_reg(pm4
, R_028C48_PA_SC_BINNER_CNTL_1
,
5630 S_028C48_MAX_ALLOC_COUNT(max_alloc_count
) |
5631 S_028C48_MAX_PRIM_PER_BATCH(1023));
5632 si_pm4_set_reg(pm4
, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
,
5633 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
5634 si_pm4_set_reg(pm4
, R_030968_VGT_INSTANCE_BASE_ID
, 0);
5637 si_pm4_upload_indirect_buffer(sctx
, pm4
);
5638 sctx
->init_config
= pm4
;